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b4cbaee4 DE |
1 | # Simulator main loop for m32r. -*- C -*- |
2 | # Copyright (C) 1996, 1997 Free Software Foundation, Inc. | |
3 | # | |
4 | # This file is part of the GNU Simulators. | |
5 | # | |
6 | # This program is free software; you can redistribute it and/or modify | |
7 | # it under the terms of the GNU General Public License as published by | |
8 | # the Free Software Foundation; either version 2, or (at your option) | |
9 | # any later version. | |
10 | # | |
11 | # This program is distributed in the hope that it will be useful, | |
12 | # but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | # GNU General Public License for more details. | |
15 | # | |
16 | # You should have received a copy of the GNU General Public License along | |
17 | # with this program; if not, write to the Free Software Foundation, Inc., | |
18 | # 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
19 | ||
20 | # Syntax: | |
21 | # /bin/sh mainloop.in init|support|{full,fast}-{extract,exec}-{scache,noscache} | |
22 | ||
23 | # ??? After a few more ports are done, revisit. | |
24 | # Will eventually need to machine generate a lot of this. | |
25 | ||
26 | case "x$1" in | |
27 | ||
28 | xsupport) | |
29 | ||
30 | cat <<EOF | |
31 | ||
32 | static INLINE void | |
33 | extract16 (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, | |
34 | SCACHE *sc, int fast_p) | |
35 | { | |
36 | const IDESC *d = @cpu@_decode (current_cpu, pc, insn); | |
37 | (*d->extract) (current_cpu, pc, insn, &sc->argbuf); | |
38 | if (fast_p) | |
39 | { | |
40 | #if WITH_SEM_SWITCH_FAST | |
41 | #ifdef __GNUC__ | |
42 | sc->semantic.sem_case = d->sem_fast_lab; | |
43 | #else | |
44 | sc->semantic.sem_case = d->num; | |
45 | #endif | |
46 | #else | |
47 | sc->semantic.sem_fast = d->sem_fast; | |
48 | #endif | |
49 | } | |
50 | else | |
51 | { | |
52 | sc->semantic.sem_full = d->sem_full; | |
53 | } | |
54 | sc->argbuf.idesc = d; | |
55 | sc->next = pc + 2; | |
56 | } | |
57 | ||
58 | static INLINE void | |
59 | extract32 (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, | |
60 | SCACHE *sc, int fast_p) | |
61 | { | |
62 | const IDESC *d = @cpu@_decode (current_cpu, pc, (USI) insn >> 16); | |
63 | (*d->extract) (current_cpu, pc, insn, &sc->argbuf); | |
64 | if (fast_p) | |
65 | { | |
66 | #if WITH_SEM_SWITCH_FAST | |
67 | #ifdef __GNUC__ | |
68 | sc->semantic.sem_case = d->sem_fast_lab; | |
69 | #else | |
70 | sc->semantic.sem_case = d->num; | |
71 | #endif | |
72 | #else | |
73 | sc->semantic.sem_fast_fn = d->sem_fast; | |
74 | #endif | |
75 | } | |
76 | else | |
77 | { | |
78 | sc->semantic.sem_full = d->sem_full; | |
79 | } | |
80 | sc->argbuf.idesc = d; | |
81 | sc->next = pc + 4; | |
82 | } | |
83 | ||
84 | static INLINE PCADDR | |
85 | execute (SIM_CPU *current_cpu, SCACHE *sc, int fast_p) | |
86 | { | |
87 | PCADDR pc; | |
88 | ||
89 | if (fast_p) | |
90 | { | |
91 | #if WITH_SCACHE && ! WITH_SEM_SWITCH_FAST | |
92 | pc = (*sc->semantic.sem_fast) (current_cpu, sc); | |
93 | #else | |
94 | #if 0 | |
95 | pc = (*sc->semantic.sem_full) (current_cpu, &sc->argbuf); | |
96 | #else | |
97 | pc = (*sc->semantic.sem_full) (current_cpu, sc); | |
98 | #endif | |
99 | #endif | |
100 | } | |
101 | else | |
102 | { | |
103 | m32r_model_init_insn_cycles (current_cpu, 1); | |
104 | TRACE_INSN_INIT (current_cpu, 1); | |
105 | TRACE_INSN (current_cpu, sc->argbuf.idesc->opcode, (const struct argbuf *) &sc->argbuf, sc->argbuf.addr); | |
106 | #if 0 | |
107 | pc = (*sc->semantic.sem_full) (current_cpu, &sc->argbuf); | |
108 | #else | |
109 | pc = (*sc->semantic.sem_full) (current_cpu, sc); | |
110 | #endif | |
111 | m32r_model_update_insn_cycles (current_cpu, 1); | |
112 | TRACE_INSN_FINI (current_cpu, 1); | |
113 | } | |
114 | ||
115 | return pc; | |
116 | } | |
117 | ||
118 | EOF | |
119 | ||
120 | ;; | |
121 | ||
122 | xinit) | |
123 | ||
124 | cat <<EOF | |
125 | /*xxxinit*/ | |
126 | EOF | |
127 | ||
128 | ;; | |
129 | ||
130 | xfull-extract-* | xfast-extract-*) | |
131 | ||
132 | cat <<EOF | |
133 | { | |
134 | PCADDR pc = CPU (h_pc); | |
135 | ||
136 | if ((pc & 3) != 0) | |
137 | { | |
138 | /* This only occurs when single stepping. | |
139 | The test is unnecessary otherwise, but the cost is teensy, | |
140 | compared with decoding/extraction. */ | |
141 | UHI insn = GETIMEMUHI (current_cpu, pc); | |
142 | extract16 (current_cpu, pc, insn & 0x7fff, sc, FAST_P); | |
143 | } | |
144 | else | |
145 | { | |
146 | USI insn = GETIMEMUSI (current_cpu, pc); | |
147 | if ((SI) insn < 0) | |
148 | { | |
149 | extract32 (current_cpu, pc, insn, sc, FAST_P); | |
150 | } | |
151 | else | |
152 | { | |
153 | extract16 (current_cpu, pc, insn >> 16, sc, FAST_P); | |
154 | extract16 (current_cpu, pc + 2, insn & 0x7fff, sc + 1, FAST_P); | |
155 | /* The m32r doesn't support parallel execution. */ | |
156 | if ((insn & 0x8000) != 0 | |
157 | && (insn & 0x7fff) != 0x7000) /* parallel nops are ok */ | |
158 | sim_engine_illegal_insn (current_cpu, pc); | |
159 | } | |
160 | } | |
161 | } | |
162 | EOF | |
163 | ||
164 | ;; | |
165 | ||
166 | xfull-exec-* | xfast-exec-*) | |
167 | ||
168 | cat <<EOF | |
169 | { | |
170 | #if WITH_SCACHE && FAST_P && WITH_SEM_SWITCH_FAST | |
171 | #define DEFINE_SWITCH | |
172 | #include "sem-switch.c" | |
173 | #else | |
174 | PCADDR new_pc = execute (current_cpu, sc, FAST_P); | |
175 | CPU (h_pc) = new_pc; | |
176 | #endif | |
177 | } | |
178 | EOF | |
179 | ||
180 | ;; | |
181 | ||
182 | *) | |
183 | echo "Invalid argument to mainloop.in: $1" >&2 | |
184 | exit 1 | |
185 | ;; | |
186 | ||
187 | esac |