Commit | Line | Data |
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9d70630e DE |
1 | /* Simulator model support for m32r. |
2 | ||
e0bd6e18 DE |
3 | This file is machine generated with CGEN. |
4 | ||
9d70630e DE |
5 | Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. |
6 | ||
7 | This file is part of the GNU Simulators. | |
8 | ||
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2, or (at your option) | |
12 | any later version. | |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License along | |
20 | with this program; if not, write to the Free Software Foundation, Inc., | |
21 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
22 | ||
23 | */ | |
24 | ||
25 | #define WANT_CPU | |
26 | #define WANT_CPU_M32R | |
27 | ||
28 | #include "sim-main.h" | |
29 | #include "cpu-sim.h" | |
30 | #include "cpu-opc.h" | |
31 | ||
32 | /* The profiling data is recorded here, but is accessed via the profiling | |
33 | mechanism. After all, this is information for profiling. */ | |
34 | ||
35 | #if WITH_PROFILE_MODEL_P | |
36 | ||
37 | /* Track function unit usage for an instruction. */ | |
38 | ||
39 | void | |
e0bd6e18 | 40 | m32r_model_profile_insn (SIM_CPU *current_cpu, ARGBUF *abuf) |
9d70630e DE |
41 | { |
42 | const MODEL *model = CPU_MODEL (current_cpu); | |
43 | const INSN_TIMING *timing = MODEL_TIMING (model); | |
44 | const CGEN_INSN *insn = abuf->opcode; | |
d9e3a135 | 45 | const UNIT *unit = &timing[CGEN_INSN_NUM (insn)].units[0]; |
9d70630e DE |
46 | const UNIT *unit_end = unit + MAX_UNITS; |
47 | PROFILE_DATA *profile = CPU_PROFILE_DATA (current_cpu); | |
48 | ||
49 | do | |
50 | { | |
51 | switch (unit->name) | |
52 | { | |
53 | case UNIT_M32R_D_U_STORE : | |
54 | PROFILE_MODEL_CYCLE_COUNT (profile) += unit->done; | |
55 | m32r_model_mark_unbusy_reg (current_cpu, abuf); | |
56 | break; | |
57 | case UNIT_M32R_D_U_LOAD : | |
58 | PROFILE_MODEL_CYCLE_COUNT (profile) += unit->done; | |
59 | m32r_model_mark_busy_reg (current_cpu, abuf); | |
60 | break; | |
61 | case UNIT_M32R_D_U_EXEC : | |
62 | PROFILE_MODEL_CYCLE_COUNT (profile) += unit->done; | |
63 | m32r_model_mark_unbusy_reg (current_cpu, abuf); | |
64 | break; | |
65 | case UNIT_TEST_U_EXEC : | |
66 | PROFILE_MODEL_CYCLE_COUNT (profile) += unit->done; | |
67 | break; | |
68 | } | |
69 | ++unit; | |
70 | } | |
71 | while (unit != unit_end && unit->name != UNIT_NONE); | |
72 | } | |
73 | ||
74 | /* Track function unit usage for an instruction. */ | |
75 | ||
76 | void | |
e0bd6e18 | 77 | m32r_model_profile_cti_insn (SIM_CPU *current_cpu, ARGBUF *abuf, int taken_p) |
9d70630e DE |
78 | { |
79 | const MODEL *model = CPU_MODEL (current_cpu); | |
80 | const INSN_TIMING *timing = MODEL_TIMING (model); | |
81 | const CGEN_INSN *insn = abuf->opcode; | |
d9e3a135 | 82 | const UNIT *unit = &timing[CGEN_INSN_NUM (insn)].units[0]; |
9d70630e DE |
83 | const UNIT *unit_end = unit + MAX_UNITS; |
84 | PROFILE_DATA *profile = CPU_PROFILE_DATA (current_cpu); | |
85 | ||
86 | do | |
87 | { | |
88 | switch (unit->name) | |
89 | { | |
90 | case UNIT_M32R_D_U_STORE : | |
91 | PROFILE_MODEL_CYCLE_COUNT (profile) += unit->done; | |
92 | m32r_model_mark_unbusy_reg (current_cpu, abuf); | |
93 | break; | |
94 | case UNIT_M32R_D_U_LOAD : | |
95 | PROFILE_MODEL_CYCLE_COUNT (profile) += unit->done; | |
96 | m32r_model_mark_busy_reg (current_cpu, abuf); | |
97 | break; | |
98 | case UNIT_M32R_D_U_EXEC : | |
99 | PROFILE_MODEL_CYCLE_COUNT (profile) += unit->done; | |
100 | if (taken_p) PROFILE_MODEL_CTI_STALL_COUNT (profile) += 2; | |
101 | m32r_model_mark_unbusy_reg (current_cpu, abuf); | |
102 | break; | |
103 | case UNIT_TEST_U_EXEC : | |
104 | PROFILE_MODEL_CYCLE_COUNT (profile) += unit->done; | |
105 | break; | |
106 | } | |
107 | if (taken_p) | |
108 | PROFILE_MODEL_TAKEN_COUNT (profile) += 1; | |
109 | else | |
110 | PROFILE_MODEL_UNTAKEN_COUNT (profile) += 1; | |
111 | ++unit; | |
112 | } | |
113 | while (unit != unit_end && unit->name != UNIT_NONE); | |
114 | } | |
115 | ||
116 | /* We assume UNIT_NONE == 0 because the tables don't always terminate | |
117 | entries with it. */ | |
118 | ||
119 | /* Model timing data for `m32r/d'. */ | |
120 | ||
121 | static const INSN_TIMING m32r_d_timing[] = { | |
122 | { { (UQI) UNIT_NONE } }, /* illegal insn */ | |
123 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* add */ | |
124 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* add3 */ | |
125 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* and */ | |
126 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* and3 */ | |
127 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* or */ | |
128 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* or3 */ | |
129 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* xor */ | |
130 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* xor3 */ | |
131 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* addi */ | |
132 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* addv */ | |
133 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* addv3 */ | |
134 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* addx */ | |
135 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* bc8 */ | |
9d70630e | 136 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* bc24 */ |
9d70630e DE |
137 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* beq */ |
138 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* beqz */ | |
139 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* bgez */ | |
140 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* bgtz */ | |
141 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* blez */ | |
142 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* bltz */ | |
143 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* bnez */ | |
144 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* bl8 */ | |
9d70630e | 145 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* bl24 */ |
9d70630e | 146 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* bnc8 */ |
9d70630e | 147 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* bnc24 */ |
9d70630e DE |
148 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* bne */ |
149 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* bra8 */ | |
9d70630e | 150 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* bra24 */ |
9d70630e DE |
151 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* cmp */ |
152 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* cmpi */ | |
153 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* cmpu */ | |
154 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* cmpui */ | |
155 | { { (UQI) UNIT_M32R_D_U_EXEC, 37, 37 } }, /* div */ | |
cab58155 | 156 | { { (UQI) UNIT_M32R_D_U_EXEC, 37, 37 } }, /* divu */ |
9d70630e | 157 | { { (UQI) UNIT_M32R_D_U_EXEC, 37, 37 } }, /* rem */ |
cab58155 | 158 | { { (UQI) UNIT_M32R_D_U_EXEC, 37, 37 } }, /* remu */ |
9d70630e DE |
159 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* jl */ |
160 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* jmp */ | |
161 | { { (UQI) UNIT_M32R_D_U_LOAD, 1, 1 } }, /* ld */ | |
e0bd6e18 | 162 | { { (UQI) UNIT_M32R_D_U_LOAD, 2, 2 } }, /* ld-d */ |
9d70630e | 163 | { { (UQI) UNIT_M32R_D_U_LOAD, 1, 1 } }, /* ldb */ |
e0bd6e18 | 164 | { { (UQI) UNIT_M32R_D_U_LOAD, 2, 2 } }, /* ldb-d */ |
9d70630e | 165 | { { (UQI) UNIT_M32R_D_U_LOAD, 1, 1 } }, /* ldh */ |
e0bd6e18 | 166 | { { (UQI) UNIT_M32R_D_U_LOAD, 2, 2 } }, /* ldh-d */ |
9d70630e | 167 | { { (UQI) UNIT_M32R_D_U_LOAD, 1, 1 } }, /* ldub */ |
e0bd6e18 | 168 | { { (UQI) UNIT_M32R_D_U_LOAD, 2, 2 } }, /* ldub-d */ |
9d70630e | 169 | { { (UQI) UNIT_M32R_D_U_LOAD, 1, 1 } }, /* lduh */ |
e0bd6e18 | 170 | { { (UQI) UNIT_M32R_D_U_LOAD, 2, 2 } }, /* lduh-d */ |
9d70630e DE |
171 | { { (UQI) UNIT_M32R_D_U_LOAD, 1, 1 } }, /* ld-plus */ |
172 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* ld24 */ | |
173 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* ldi8 */ | |
9d70630e | 174 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* ldi16 */ |
9d70630e DE |
175 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* lock */ |
176 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* machi */ | |
177 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* maclo */ | |
178 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* macwhi */ | |
179 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* macwlo */ | |
e0bd6e18 | 180 | { { (UQI) UNIT_M32R_D_U_EXEC, 4, 4 } }, /* mul */ |
9d70630e DE |
181 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* mulhi */ |
182 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* mullo */ | |
183 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* mulwhi */ | |
184 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* mulwlo */ | |
185 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* mv */ | |
cab58155 DE |
186 | { { (UQI) UNIT_M32R_D_U_EXEC, 2, 2 } }, /* mvfachi */ |
187 | { { (UQI) UNIT_M32R_D_U_EXEC, 2, 2 } }, /* mvfaclo */ | |
188 | { { (UQI) UNIT_M32R_D_U_EXEC, 2, 2 } }, /* mvfacmi */ | |
9d70630e DE |
189 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* mvfc */ |
190 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* mvtachi */ | |
191 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* mvtaclo */ | |
192 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* mvtc */ | |
193 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* neg */ | |
194 | { { (UQI) UNIT_M32R_D_U_EXEC, 0, 0 } }, /* nop */ | |
195 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* not */ | |
196 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* rac */ | |
197 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* rach */ | |
198 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* rte */ | |
199 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* seth */ | |
200 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* sll */ | |
201 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* sll3 */ | |
202 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* slli */ | |
203 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* sra */ | |
204 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* sra3 */ | |
205 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* srai */ | |
206 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* srl */ | |
207 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* srl3 */ | |
208 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* srli */ | |
209 | { { (UQI) UNIT_M32R_D_U_STORE, 1, 1 } }, /* st */ | |
e0bd6e18 | 210 | { { (UQI) UNIT_M32R_D_U_STORE, 2, 2 } }, /* st-d */ |
9d70630e | 211 | { { (UQI) UNIT_M32R_D_U_STORE, 1, 1 } }, /* stb */ |
e0bd6e18 | 212 | { { (UQI) UNIT_M32R_D_U_STORE, 2, 2 } }, /* stb-d */ |
9d70630e | 213 | { { (UQI) UNIT_M32R_D_U_STORE, 1, 1 } }, /* sth */ |
e0bd6e18 | 214 | { { (UQI) UNIT_M32R_D_U_STORE, 2, 2 } }, /* sth-d */ |
9d70630e DE |
215 | { { (UQI) UNIT_M32R_D_U_STORE, 1, 1 } }, /* st-plus */ |
216 | { { (UQI) UNIT_M32R_D_U_STORE, 1, 1 } }, /* st-minus */ | |
217 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* sub */ | |
218 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* subv */ | |
219 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* subx */ | |
220 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* trap */ | |
221 | { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* unlock */ | |
9d70630e DE |
222 | }; |
223 | ||
224 | /* Model timing data for `test'. */ | |
225 | ||
226 | static const INSN_TIMING test_timing[] = { | |
227 | { { (UQI) UNIT_NONE } }, /* illegal insn */ | |
228 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* add */ | |
229 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* add3 */ | |
230 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* and */ | |
231 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* and3 */ | |
232 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* or */ | |
233 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* or3 */ | |
234 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* xor */ | |
235 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* xor3 */ | |
236 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* addi */ | |
237 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* addv */ | |
238 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* addv3 */ | |
239 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* addx */ | |
240 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* bc8 */ | |
9d70630e | 241 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* bc24 */ |
9d70630e DE |
242 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* beq */ |
243 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* beqz */ | |
244 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* bgez */ | |
245 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* bgtz */ | |
246 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* blez */ | |
247 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* bltz */ | |
248 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* bnez */ | |
249 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* bl8 */ | |
9d70630e | 250 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* bl24 */ |
9d70630e | 251 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* bnc8 */ |
9d70630e | 252 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* bnc24 */ |
9d70630e DE |
253 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* bne */ |
254 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* bra8 */ | |
9d70630e | 255 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* bra24 */ |
9d70630e DE |
256 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* cmp */ |
257 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* cmpi */ | |
258 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* cmpu */ | |
259 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* cmpui */ | |
260 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* div */ | |
261 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* divu */ | |
262 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* rem */ | |
263 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* remu */ | |
264 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* jl */ | |
265 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* jmp */ | |
266 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* ld */ | |
9d70630e | 267 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* ld-d */ |
9d70630e | 268 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* ldb */ |
9d70630e | 269 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* ldb-d */ |
9d70630e | 270 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* ldh */ |
9d70630e | 271 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* ldh-d */ |
9d70630e | 272 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* ldub */ |
9d70630e | 273 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* ldub-d */ |
9d70630e | 274 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* lduh */ |
9d70630e | 275 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* lduh-d */ |
9d70630e DE |
276 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* ld-plus */ |
277 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* ld24 */ | |
278 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* ldi8 */ | |
9d70630e | 279 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* ldi16 */ |
9d70630e DE |
280 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* lock */ |
281 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* machi */ | |
282 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* maclo */ | |
283 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* macwhi */ | |
284 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* macwlo */ | |
285 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* mul */ | |
286 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* mulhi */ | |
287 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* mullo */ | |
288 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* mulwhi */ | |
289 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* mulwlo */ | |
290 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* mv */ | |
291 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* mvfachi */ | |
292 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* mvfaclo */ | |
293 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* mvfacmi */ | |
294 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* mvfc */ | |
295 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* mvtachi */ | |
296 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* mvtaclo */ | |
297 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* mvtc */ | |
298 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* neg */ | |
299 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* nop */ | |
300 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* not */ | |
301 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* rac */ | |
302 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* rach */ | |
303 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* rte */ | |
304 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* seth */ | |
305 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* sll */ | |
306 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* sll3 */ | |
307 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* slli */ | |
308 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* sra */ | |
309 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* sra3 */ | |
310 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* srai */ | |
311 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* srl */ | |
312 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* srl3 */ | |
313 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* srli */ | |
314 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* st */ | |
9d70630e | 315 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* st-d */ |
9d70630e | 316 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* stb */ |
9d70630e | 317 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* stb-d */ |
9d70630e | 318 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* sth */ |
9d70630e | 319 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* sth-d */ |
9d70630e DE |
320 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* st-plus */ |
321 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* st-minus */ | |
322 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* sub */ | |
323 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* subv */ | |
324 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* subx */ | |
325 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* trap */ | |
326 | { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* unlock */ | |
9d70630e DE |
327 | }; |
328 | ||
329 | #endif /* WITH_PROFILE_MODEL_P */ | |
330 | ||
331 | #if WITH_PROFILE_MODEL_P | |
332 | #define TIMING_DATA(td) td | |
333 | #else | |
334 | #define TIMING_DATA(td) 0 | |
335 | #endif | |
336 | ||
337 | const MODEL m32r_models[] = { | |
338 | { "m32r/d", &machs[MACH_M32R], TIMING_DATA (& m32r_d_timing[0]) }, | |
339 | { "test", &machs[MACH_M32R], TIMING_DATA (& test_timing[0]) }, | |
340 | { 0 } | |
341 | }; | |
342 | ||
343 | /* The properties of this cpu's implementation. */ | |
344 | ||
345 | const IMP_PROPERTIES m32r_imp_properties = { | |
346 | sizeof (SIM_CPU) | |
347 | #if WITH_SCACHE | |
348 | , sizeof (SCACHE) | |
349 | #endif | |
350 | }; | |
351 |