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[deliverable/binutils-gdb.git] / sim / m32r / modelx.c
CommitLineData
e0bd6e18
DE		 1/* Simulator model support for m32rx.
2
3This file is machine generated with CGEN.
4
5Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
6
7This file is part of the GNU Simulators.
8
9This program is free software; you can redistribute it and/or modify
10it under the terms of the GNU General Public License as published by
11the Free Software Foundation; either version 2, or (at your option)
12any later version.
13
14This program is distributed in the hope that it will be useful,
15but WITHOUT ANY WARRANTY; without even the implied warranty of
16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17GNU General Public License for more details.
18
19You should have received a copy of the GNU General Public License along
20with this program; if not, write to the Free Software Foundation, Inc.,
2159 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22
23*/
24
25#define WANT_CPU
26#define WANT_CPU_M32RX
27
28#include "sim-main.h"
29#include "cpu-sim.h"
30#include "cpu-opc.h"
31
32/* The profiling data is recorded here, but is accessed via the profiling
33 mechanism. After all, this is information for profiling. */
34
35#if WITH_PROFILE_MODEL_P
36
37/* Track function unit usage for an instruction. */
38
39void
40m32rx_model_profile_insn (SIM_CPU *current_cpu, ARGBUF *abuf)
41{
42 const MODEL *model = CPU_MODEL (current_cpu);
43 const INSN_TIMING *timing = MODEL_TIMING (model);
44 const CGEN_INSN *insn = abuf->opcode;
d9e3a135 45 const UNIT *unit = &timing[CGEN_INSN_NUM (insn)].units[0];
e0bd6e18
DE		 46 const UNIT *unit_end = unit + MAX_UNITS;
47 PROFILE_DATA *profile = CPU_PROFILE_DATA (current_cpu);
48
49 do
50 {
51 switch (unit->name)
52 {
53 case UNIT_M32RX_U_EXEC :
54 PROFILE_MODEL_CYCLE_COUNT (profile) += unit->done;
55 break;
56 }
57 ++unit;
58 }
59 while (unit != unit_end && unit->name != UNIT_NONE);
60}
61
62/* Track function unit usage for an instruction. */
63
64void
65m32rx_model_profile_cti_insn (SIM_CPU *current_cpu, ARGBUF *abuf, int taken_p)
66{
67 const MODEL *model = CPU_MODEL (current_cpu);
68 const INSN_TIMING *timing = MODEL_TIMING (model);
69 const CGEN_INSN *insn = abuf->opcode;
d9e3a135 70 const UNIT *unit = &timing[CGEN_INSN_NUM (insn)].units[0];
e0bd6e18
DE		 71 const UNIT *unit_end = unit + MAX_UNITS;
72 PROFILE_DATA *profile = CPU_PROFILE_DATA (current_cpu);
73
74 do
75 {
76 switch (unit->name)
77 {
78 case UNIT_M32RX_U_EXEC :
79 PROFILE_MODEL_CYCLE_COUNT (profile) += unit->done;
80 break;
81 }
82 if (taken_p)
83 PROFILE_MODEL_TAKEN_COUNT (profile) += 1;
84 else
85 PROFILE_MODEL_UNTAKEN_COUNT (profile) += 1;
86 ++unit;
87 }
88 while (unit != unit_end && unit->name != UNIT_NONE);
89}
90
91/* We assume UNIT_NONE == 0 because the tables don't always terminate
92 entries with it. */
93
94/* Model timing data for `m32rx'. */
95
96static const INSN_TIMING m32rx_timing[] = {
97 { { (UQI) UNIT_NONE } }, /* illegal insn */
98 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* add */
99 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* add3 */
e0bd6e18
DE		 100 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* and */
101 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* and3 */
e0bd6e18
DE		 102 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* or */
103 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* or3 */
e0bd6e18
DE		 104 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* xor */
105 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* xor3 */
e0bd6e18 106 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* addi */
e0bd6e18
DE		 107 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* addv */
108 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* addv3 */
e0bd6e18
DE		 109 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* addx */
110 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* bc8 */
e0bd6e18 111 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* bc24 */
e0bd6e18
DE		 112 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* beq */
113 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* beqz */
114 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* bgez */
115 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* bgtz */
116 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* blez */
117 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* bltz */
118 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* bnez */
119 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* bl8 */
e0bd6e18 120 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* bl24 */
e0bd6e18 121 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* bcl8 */
e0bd6e18 122 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* bcl24 */
e0bd6e18 123 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* bnc8 */
e0bd6e18 124 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* bnc24 */
e0bd6e18
DE		 125 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* bne */
126 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* bra8 */
e0bd6e18 127 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* bra24 */
e0bd6e18 128 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* bncl8 */
e0bd6e18 129 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* bncl24 */
e0bd6e18
DE		 130 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* cmp */
131 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* cmpi */
e0bd6e18
DE		 132 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* cmpu */
133 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* cmpui */
e0bd6e18
DE		 134 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* cmpeq */
135 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* cmpz */
136 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* div */
137 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* divu */
138 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* rem */
139 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* remu */
d9e3a135 140 { { (UQI) UNIT_M32RX_U_EXEC, 21, 21 } }, /* divh */
e0bd6e18
DE		 141 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* jc */
142 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* jnc */
143 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* jl */
144 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* jmp */
145 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* ld */
e0bd6e18 146 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* ld-d */
e0bd6e18 147 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* ldb */
e0bd6e18 148 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* ldb-d */
e0bd6e18 149 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* ldh */
e0bd6e18 150 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* ldh-d */
e0bd6e18 151 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* ldub */
e0bd6e18 152 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* ldub-d */
e0bd6e18 153 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* lduh */
e0bd6e18 154 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* lduh-d */
e0bd6e18
DE		 155 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* ld-plus */
156 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* ld24 */
e0bd6e18 157 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* ldi8 */
e0bd6e18 158 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* ldi16 */
e0bd6e18
DE		 159 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* lock */
160 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* machi-a */
161 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* maclo-a */
d9e3a135
DE		 162 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* macwhi */
163 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* macwlo */
e0bd6e18
DE		 164 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* mul */
165 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* mulhi-a */
166 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* mullo-a */
d9e3a135
DE		 167 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* mulwhi */
168 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* mulwlo */
e0bd6e18 169 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* mv */
d9e3a135
DE		 170 { { (UQI) UNIT_M32RX_U_EXEC, 2, 2 } }, /* mvfachi-a */
171 { { (UQI) UNIT_M32RX_U_EXEC, 2, 2 } }, /* mvfaclo-a */
172 { { (UQI) UNIT_M32RX_U_EXEC, 2, 2 } }, /* mvfacmi-a */
e0bd6e18
DE		 173 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* mvfc */
174 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* mvtachi-a */
175 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* mvtaclo-a */
176 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* mvtc */
177 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* neg */
178 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* nop */
179 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* not */
e0bd6e18 180 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* rac-dsi */
e0bd6e18
DE		 181 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* rach-dsi */
182 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* rte */
183 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* seth */
e0bd6e18
DE		 184 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* sll */
185 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* sll3 */
e0bd6e18 186 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* slli */
e0bd6e18
DE		 187 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* sra */
188 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* sra3 */
e0bd6e18 189 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* srai */
e0bd6e18
DE		 190 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* srl */
191 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* srl3 */
e0bd6e18 192 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* srli */
e0bd6e18 193 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* st */
e0bd6e18 194 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* st-d */
e0bd6e18 195 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* stb */
e0bd6e18 196 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* stb-d */
e0bd6e18 197 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* sth */
e0bd6e18 198 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* sth-d */
e0bd6e18
DE		 199 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* st-plus */
200 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* st-minus */
201 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* sub */
202 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* subv */
203 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* subx */
204 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* trap */
e0bd6e18 205 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* unlock */
e0bd6e18
DE		 206 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* satb */
207 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* sath */
208 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* sat */
209 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* pcmpbz */
210 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* sadd */
211 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* macwu1 */
212 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* msblo */
213 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* mulwu1 */
214 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* maclh1 */
215 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* sc */
216 { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* snc */
217};
218
219#endif /* WITH_PROFILE_MODEL_P */
220
221#if WITH_PROFILE_MODEL_P
222#define TIMING_DATA(td) td
223#else
224#define TIMING_DATA(td) 0
225#endif
226
227const MODEL m32rx_models[] = {
228 { "m32rx", &machs[MACH_M32RX], TIMING_DATA (& m32rx_timing[0]) },
229 { 0 }
230};
231
232/* The properties of this cpu's implementation. */
233
234const IMP_PROPERTIES m32rx_imp_properties = {
235 sizeof (SIM_CPU)
236#if WITH_SCACHE
237 , sizeof (SCACHE)
238#endif
239};
240
GDB Binutils - Deliverables
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