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* Makefile.in (stamp-arch): Pass FLAGS to cgen.
[deliverable/binutils-gdb.git] / sim / m32r / modelx.c
CommitLineData
368fc7db 1/* Simulator model support for m32rxf.
e0bd6e18 2
368fc7db 3THIS FILE IS MACHINE GENERATED WITH CGEN.
e0bd6e18 4
ddfae34d 5Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
e0bd6e18
DE		 6
7This file is part of the GNU Simulators.
8
9This program is free software; you can redistribute it and/or modify
10it under the terms of the GNU General Public License as published by
11the Free Software Foundation; either version 2, or (at your option)
12any later version.
13
14This program is distributed in the hope that it will be useful,
15but WITHOUT ANY WARRANTY; without even the implied warranty of
16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17GNU General Public License for more details.
18
19You should have received a copy of the GNU General Public License along
20with this program; if not, write to the Free Software Foundation, Inc.,
2159 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22
23*/
24
368fc7db
DE		 25#define WANT_CPU m32rxf
26#define WANT_CPU_M32RXF
e0bd6e18
DE		 27
28#include "sim-main.h"
e0bd6e18
DE		 29
30/* The profiling data is recorded here, but is accessed via the profiling
31 mechanism. After all, this is information for profiling. */
32
33#if WITH_PROFILE_MODEL_P
34
368fc7db
DE		 35/* Model handlers for each insn. */
36
368fc7db
DE		 37static int
38model_m32rx_add (SIM_CPU *current_cpu, void *sem_arg)
39{
40#define FLD(f) abuf->fields.fmt_add.f
ddfae34d
DE		 41 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
42 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 43 int cycles = 0;
44 {
45 int referenced = 0;
46 int UNUSED insn_referenced = abuf->written;
47 INT sr = -1;
48 INT sr2 = -1;
49 INT dr = -1;
50 sr = FLD (in_sr);
51 dr = FLD (out_dr);
52 referenced |= 1 << 0;
53 referenced |= 1 << 2;
ddfae34d 54 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
368fc7db
DE		 55 }
56 return cycles;
57#undef FLD
58}
59
60static int
61model_m32rx_add3 (SIM_CPU *current_cpu, void *sem_arg)
62{
63#define FLD(f) abuf->fields.fmt_add3.f
ddfae34d
DE		 64 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
65 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 66 int cycles = 0;
67 {
68 int referenced = 0;
69 int UNUSED insn_referenced = abuf->written;
70 INT sr = -1;
71 INT sr2 = -1;
72 INT dr = -1;
73 sr = FLD (in_sr);
74 dr = FLD (out_dr);
75 referenced |= 1 << 0;
76 referenced |= 1 << 2;
ddfae34d 77 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
368fc7db
DE		 78 }
79 return cycles;
80#undef FLD
81}
82
83static int
84model_m32rx_and (SIM_CPU *current_cpu, void *sem_arg)
85{
86#define FLD(f) abuf->fields.fmt_add.f
ddfae34d
DE		 87 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
88 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 89 int cycles = 0;
90 {
91 int referenced = 0;
92 int UNUSED insn_referenced = abuf->written;
93 INT sr = -1;
94 INT sr2 = -1;
95 INT dr = -1;
96 sr = FLD (in_sr);
97 dr = FLD (out_dr);
98 referenced |= 1 << 0;
99 referenced |= 1 << 2;
ddfae34d 100 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
368fc7db
DE		 101 }
102 return cycles;
103#undef FLD
104}
105
106static int
107model_m32rx_and3 (SIM_CPU *current_cpu, void *sem_arg)
108{
109#define FLD(f) abuf->fields.fmt_and3.f
ddfae34d
DE		 110 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
111 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 112 int cycles = 0;
113 {
114 int referenced = 0;
115 int UNUSED insn_referenced = abuf->written;
116 INT sr = -1;
117 INT sr2 = -1;
118 INT dr = -1;
119 sr = FLD (in_sr);
120 dr = FLD (out_dr);
121 referenced |= 1 << 0;
122 referenced |= 1 << 2;
ddfae34d 123 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
368fc7db
DE		 124 }
125 return cycles;
126#undef FLD
127}
128
129static int
130model_m32rx_or (SIM_CPU *current_cpu, void *sem_arg)
131{
132#define FLD(f) abuf->fields.fmt_add.f
ddfae34d
DE		 133 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
134 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 135 int cycles = 0;
136 {
137 int referenced = 0;
138 int UNUSED insn_referenced = abuf->written;
139 INT sr = -1;
140 INT sr2 = -1;
141 INT dr = -1;
142 sr = FLD (in_sr);
143 dr = FLD (out_dr);
144 referenced |= 1 << 0;
145 referenced |= 1 << 2;
ddfae34d 146 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
368fc7db
DE		 147 }
148 return cycles;
149#undef FLD
150}
151
152static int
153model_m32rx_or3 (SIM_CPU *current_cpu, void *sem_arg)
154{
155#define FLD(f) abuf->fields.fmt_or3.f
ddfae34d
DE		 156 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
157 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 158 int cycles = 0;
159 {
160 int referenced = 0;
161 int UNUSED insn_referenced = abuf->written;
162 INT sr = -1;
163 INT sr2 = -1;
164 INT dr = -1;
165 sr = FLD (in_sr);
166 dr = FLD (out_dr);
167 referenced |= 1 << 0;
168 referenced |= 1 << 2;
ddfae34d 169 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
368fc7db
DE		 170 }
171 return cycles;
172#undef FLD
173}
174
175static int
176model_m32rx_xor (SIM_CPU *current_cpu, void *sem_arg)
177{
178#define FLD(f) abuf->fields.fmt_add.f
ddfae34d
DE		 179 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
180 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 181 int cycles = 0;
182 {
183 int referenced = 0;
184 int UNUSED insn_referenced = abuf->written;
185 INT sr = -1;
186 INT sr2 = -1;
187 INT dr = -1;
188 sr = FLD (in_sr);
189 dr = FLD (out_dr);
190 referenced |= 1 << 0;
191 referenced |= 1 << 2;
ddfae34d 192 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
368fc7db
DE		 193 }
194 return cycles;
195#undef FLD
196}
197
198static int
199model_m32rx_xor3 (SIM_CPU *current_cpu, void *sem_arg)
200{
201#define FLD(f) abuf->fields.fmt_and3.f
ddfae34d
DE		 202 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
203 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 204 int cycles = 0;
205 {
206 int referenced = 0;
207 int UNUSED insn_referenced = abuf->written;
208 INT sr = -1;
209 INT sr2 = -1;
210 INT dr = -1;
211 sr = FLD (in_sr);
212 dr = FLD (out_dr);
213 referenced |= 1 << 0;
214 referenced |= 1 << 2;
ddfae34d 215 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
368fc7db
DE		 216 }
217 return cycles;
218#undef FLD
219}
220
221static int
222model_m32rx_addi (SIM_CPU *current_cpu, void *sem_arg)
223{
224#define FLD(f) abuf->fields.fmt_addi.f
ddfae34d
DE		 225 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
226 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 227 int cycles = 0;
228 {
229 int referenced = 0;
230 int UNUSED insn_referenced = abuf->written;
231 INT sr = -1;
232 INT sr2 = -1;
233 INT dr = -1;
234 dr = FLD (out_dr);
235 sr = FLD (in_dr);
236 referenced |= 1 << 0;
237 referenced |= 1 << 2;
ddfae34d 238 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
368fc7db
DE		 239 }
240 return cycles;
241#undef FLD
242}
243
244static int
245model_m32rx_addv (SIM_CPU *current_cpu, void *sem_arg)
246{
247#define FLD(f) abuf->fields.fmt_addv.f
ddfae34d
DE		 248 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
249 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 250 int cycles = 0;
251 {
252 int referenced = 0;
253 int UNUSED insn_referenced = abuf->written;
254 INT sr = -1;
255 INT sr2 = -1;
256 INT dr = -1;
257 sr = FLD (in_sr);
258 dr = FLD (out_dr);
259 referenced |= 1 << 0;
260 referenced |= 1 << 2;
ddfae34d 261 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
368fc7db
DE		 262 }
263 return cycles;
264#undef FLD
265}
266
267static int
268model_m32rx_addv3 (SIM_CPU *current_cpu, void *sem_arg)
269{
270#define FLD(f) abuf->fields.fmt_addv3.f
ddfae34d
DE		 271 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
272 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 273 int cycles = 0;
274 {
275 int referenced = 0;
276 int UNUSED insn_referenced = abuf->written;
277 INT sr = -1;
278 INT sr2 = -1;
279 INT dr = -1;
280 sr = FLD (in_sr);
281 dr = FLD (out_dr);
282 referenced |= 1 << 0;
283 referenced |= 1 << 2;
ddfae34d 284 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
368fc7db
DE		 285 }
286 return cycles;
287#undef FLD
288}
289
290static int
291model_m32rx_addx (SIM_CPU *current_cpu, void *sem_arg)
292{
293#define FLD(f) abuf->fields.fmt_addx.f
ddfae34d
DE		 294 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
295 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 296 int cycles = 0;
297 {
298 int referenced = 0;
299 int UNUSED insn_referenced = abuf->written;
300 INT sr = -1;
301 INT sr2 = -1;
302 INT dr = -1;
303 sr = FLD (in_sr);
304 dr = FLD (out_dr);
305 referenced |= 1 << 0;
306 referenced |= 1 << 2;
ddfae34d 307 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
368fc7db
DE		 308 }
309 return cycles;
310#undef FLD
311}
312
313static int
314model_m32rx_bc8 (SIM_CPU *current_cpu, void *sem_arg)
315{
316#define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
ddfae34d
DE		 317 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
318 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 319 int cycles = 0;
320 {
321 int referenced = 0;
322 int UNUSED insn_referenced = abuf->written;
323 INT sr = -1;
324 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
ddfae34d 325 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr);
368fc7db
DE		 326 }
327 return cycles;
328#undef FLD
329}
330
331static int
332model_m32rx_bc24 (SIM_CPU *current_cpu, void *sem_arg)
333{
334#define FLD(f) abuf->fields.cti.fields.fmt_bc24.f
ddfae34d
DE		 335 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
336 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 337 int cycles = 0;
338 {
339 int referenced = 0;
340 int UNUSED insn_referenced = abuf->written;
341 INT sr = -1;
342 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
ddfae34d 343 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr);
368fc7db
DE		 344 }
345 return cycles;
346#undef FLD
347}
348
349static int
350model_m32rx_beq (SIM_CPU *current_cpu, void *sem_arg)
351{
352#define FLD(f) abuf->fields.cti.fields.fmt_beq.f
ddfae34d
DE		 353 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
354 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 355 int cycles = 0;
356 {
357 int referenced = 0;
358 int UNUSED insn_referenced = abuf->written;
359 INT sr = -1;
360 if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
ddfae34d 361 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr);
368fc7db
DE		 362 }
363 {
364 int referenced = 0;
365 int UNUSED insn_referenced = abuf->written;
366 INT src1 = -1;
367 INT src2 = -1;
368 src1 = FLD (in_src1);
369 src2 = FLD (in_src2);
370 referenced |= 1 << 0;
371 referenced |= 1 << 1;
ddfae34d 372 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, src1, src2);
368fc7db
DE		 373 }
374 return cycles;
375#undef FLD
376}
377
378static int
379model_m32rx_beqz (SIM_CPU *current_cpu, void *sem_arg)
380{
381#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
ddfae34d
DE		 382 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
383 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 384 int cycles = 0;
385 {
386 int referenced = 0;
387 int UNUSED insn_referenced = abuf->written;
388 INT sr = -1;
389 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
ddfae34d 390 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr);
368fc7db
DE		 391 }
392 {
393 int referenced = 0;
394 int UNUSED insn_referenced = abuf->written;
395 INT src1 = -1;
396 INT src2 = -1;
397 src2 = FLD (in_src2);
398 referenced |= 1 << 1;
ddfae34d 399 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, src1, src2);
368fc7db
DE		 400 }
401 return cycles;
402#undef FLD
403}
404
405static int
406model_m32rx_bgez (SIM_CPU *current_cpu, void *sem_arg)
407{
408#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
ddfae34d
DE		 409 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
410 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 411 int cycles = 0;
412 {
413 int referenced = 0;
414 int UNUSED insn_referenced = abuf->written;
415 INT sr = -1;
416 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
ddfae34d 417 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr);
368fc7db
DE		 418 }
419 {
420 int referenced = 0;
421 int UNUSED insn_referenced = abuf->written;
422 INT src1 = -1;
423 INT src2 = -1;
424 src2 = FLD (in_src2);
425 referenced |= 1 << 1;
ddfae34d 426 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, src1, src2);
368fc7db
DE		 427 }
428 return cycles;
429#undef FLD
430}
431
432static int
433model_m32rx_bgtz (SIM_CPU *current_cpu, void *sem_arg)
434{
435#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
ddfae34d
DE		 436 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
437 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 438 int cycles = 0;
439 {
440 int referenced = 0;
441 int UNUSED insn_referenced = abuf->written;
442 INT sr = -1;
443 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
ddfae34d 444 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr);
368fc7db
DE		 445 }
446 {
447 int referenced = 0;
448 int UNUSED insn_referenced = abuf->written;
449 INT src1 = -1;
450 INT src2 = -1;
451 src2 = FLD (in_src2);
452 referenced |= 1 << 1;
ddfae34d 453 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, src1, src2);
368fc7db
DE		 454 }
455 return cycles;
456#undef FLD
457}
458
459static int
460model_m32rx_blez (SIM_CPU *current_cpu, void *sem_arg)
461{
462#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
ddfae34d
DE		 463 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
464 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 465 int cycles = 0;
466 {
467 int referenced = 0;
468 int UNUSED insn_referenced = abuf->written;
469 INT sr = -1;
470 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
ddfae34d 471 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr);
368fc7db
DE		 472 }
473 {
474 int referenced = 0;
475 int UNUSED insn_referenced = abuf->written;
476 INT src1 = -1;
477 INT src2 = -1;
478 src2 = FLD (in_src2);
479 referenced |= 1 << 1;
ddfae34d 480 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, src1, src2);
368fc7db
DE		 481 }
482 return cycles;
483#undef FLD
484}
485
486static int
487model_m32rx_bltz (SIM_CPU *current_cpu, void *sem_arg)
488{
489#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
ddfae34d
DE		 490 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
491 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 492 int cycles = 0;
493 {
494 int referenced = 0;
495 int UNUSED insn_referenced = abuf->written;
496 INT sr = -1;
497 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
ddfae34d 498 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr);
368fc7db
DE		 499 }
500 {
501 int referenced = 0;
502 int UNUSED insn_referenced = abuf->written;
503 INT src1 = -1;
504 INT src2 = -1;
505 src2 = FLD (in_src2);
506 referenced |= 1 << 1;
ddfae34d 507 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, src1, src2);
368fc7db
DE		 508 }
509 return cycles;
510#undef FLD
511}
512
513static int
514model_m32rx_bnez (SIM_CPU *current_cpu, void *sem_arg)
515{
516#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
ddfae34d
DE		 517 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
518 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 519 int cycles = 0;
520 {
521 int referenced = 0;
522 int UNUSED insn_referenced = abuf->written;
523 INT sr = -1;
524 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
ddfae34d 525 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr);
368fc7db
DE		 526 }
527 {
528 int referenced = 0;
529 int UNUSED insn_referenced = abuf->written;
530 INT src1 = -1;
531 INT src2 = -1;
532 src2 = FLD (in_src2);
533 referenced |= 1 << 1;
ddfae34d 534 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, src1, src2);
368fc7db
DE		 535 }
536 return cycles;
537#undef FLD
538}
539
540static int
541model_m32rx_bl8 (SIM_CPU *current_cpu, void *sem_arg)
542{
543#define FLD(f) abuf->fields.cti.fields.fmt_bl8.f
ddfae34d
DE		 544 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
545 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 546 int cycles = 0;
547 {
548 int referenced = 0;
549 int UNUSED insn_referenced = abuf->written;
550 INT sr = -1;
551 referenced |= 1 << 1;
ddfae34d 552 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr);
368fc7db
DE		 553 }
554 return cycles;
555#undef FLD
556}
557
558static int
559model_m32rx_bl24 (SIM_CPU *current_cpu, void *sem_arg)
560{
561#define FLD(f) abuf->fields.cti.fields.fmt_bl24.f
ddfae34d
DE		 562 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
563 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 564 int cycles = 0;
565 {
566 int referenced = 0;
567 int UNUSED insn_referenced = abuf->written;
568 INT sr = -1;
569 referenced |= 1 << 1;
ddfae34d 570 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr);
368fc7db
DE		 571 }
572 return cycles;
573#undef FLD
574}
575
576static int
577model_m32rx_bcl8 (SIM_CPU *current_cpu, void *sem_arg)
578{
579#define FLD(f) abuf->fields.cti.fields.fmt_bcl8.f
ddfae34d
DE		 580 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
581 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 582 int cycles = 0;
583 {
584 int referenced = 0;
585 int UNUSED insn_referenced = abuf->written;
586 INT sr = -1;
587 if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
ddfae34d 588 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr);
368fc7db
DE		 589 }
590 return cycles;
591#undef FLD
592}
593
594static int
595model_m32rx_bcl24 (SIM_CPU *current_cpu, void *sem_arg)
596{
597#define FLD(f) abuf->fields.cti.fields.fmt_bcl24.f
ddfae34d
DE		 598 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
599 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 600 int cycles = 0;
601 {
602 int referenced = 0;
603 int UNUSED insn_referenced = abuf->written;
604 INT sr = -1;
605 if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
ddfae34d 606 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr);
368fc7db
DE		 607 }
608 return cycles;
609#undef FLD
610}
611
612static int
613model_m32rx_bnc8 (SIM_CPU *current_cpu, void *sem_arg)
614{
615#define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
ddfae34d
DE		 616 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
617 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 618 int cycles = 0;
619 {
620 int referenced = 0;
621 int UNUSED insn_referenced = abuf->written;
622 INT sr = -1;
623 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
ddfae34d 624 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr);
368fc7db
DE		 625 }
626 return cycles;
627#undef FLD
628}
629
630static int
631model_m32rx_bnc24 (SIM_CPU *current_cpu, void *sem_arg)
632{
633#define FLD(f) abuf->fields.cti.fields.fmt_bc24.f
ddfae34d
DE		 634 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
635 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 636 int cycles = 0;
637 {
638 int referenced = 0;
639 int UNUSED insn_referenced = abuf->written;
640 INT sr = -1;
641 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
ddfae34d 642 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr);
368fc7db
DE		 643 }
644 return cycles;
645#undef FLD
646}
647
648static int
649model_m32rx_bne (SIM_CPU *current_cpu, void *sem_arg)
650{
651#define FLD(f) abuf->fields.cti.fields.fmt_beq.f
ddfae34d
DE		 652 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
653 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 654 int cycles = 0;
655 {
656 int referenced = 0;
657 int UNUSED insn_referenced = abuf->written;
658 INT sr = -1;
659 if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
ddfae34d 660 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr);
368fc7db
DE		 661 }
662 {
663 int referenced = 0;
664 int UNUSED insn_referenced = abuf->written;
665 INT src1 = -1;
666 INT src2 = -1;
667 src1 = FLD (in_src1);
668 src2 = FLD (in_src2);
669 referenced |= 1 << 0;
670 referenced |= 1 << 1;
ddfae34d 671 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, src1, src2);
368fc7db
DE		 672 }
673 return cycles;
674#undef FLD
675}
676
677static int
678model_m32rx_bra8 (SIM_CPU *current_cpu, void *sem_arg)
679{
680#define FLD(f) abuf->fields.cti.fields.fmt_bra8.f
ddfae34d
DE		 681 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
682 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 683 int cycles = 0;
684 {
685 int referenced = 0;
686 int UNUSED insn_referenced = abuf->written;
687 INT sr = -1;
688 referenced |= 1 << 1;
ddfae34d 689 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr);
368fc7db
DE		 690 }
691 return cycles;
692#undef FLD
693}
694
695static int
696model_m32rx_bra24 (SIM_CPU *current_cpu, void *sem_arg)
697{
698#define FLD(f) abuf->fields.cti.fields.fmt_bra24.f
ddfae34d
DE		 699 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
700 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 701 int cycles = 0;
702 {
703 int referenced = 0;
704 int UNUSED insn_referenced = abuf->written;
705 INT sr = -1;
706 referenced |= 1 << 1;
ddfae34d 707 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr);
368fc7db
DE		 708 }
709 return cycles;
710#undef FLD
711}
712
713static int
714model_m32rx_bncl8 (SIM_CPU *current_cpu, void *sem_arg)
715{
716#define FLD(f) abuf->fields.cti.fields.fmt_bcl8.f
ddfae34d
DE		 717 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
718 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 719 int cycles = 0;
720 {
721 int referenced = 0;
722 int UNUSED insn_referenced = abuf->written;
723 INT sr = -1;
724 if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
ddfae34d 725 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr);
368fc7db
DE		 726 }
727 return cycles;
728#undef FLD
729}
730
731static int
732model_m32rx_bncl24 (SIM_CPU *current_cpu, void *sem_arg)
733{
734#define FLD(f) abuf->fields.cti.fields.fmt_bcl24.f
ddfae34d
DE		 735 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
736 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 737 int cycles = 0;
738 {
739 int referenced = 0;
740 int UNUSED insn_referenced = abuf->written;
741 INT sr = -1;
742 if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
ddfae34d 743 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr);
368fc7db
DE		 744 }
745 return cycles;
746#undef FLD
747}
748
749static int
750model_m32rx_cmp (SIM_CPU *current_cpu, void *sem_arg)
751{
752#define FLD(f) abuf->fields.fmt_cmp.f
ddfae34d
DE		 753 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
754 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 755 int cycles = 0;
756 {
757 int referenced = 0;
758 int UNUSED insn_referenced = abuf->written;
759 INT src1 = -1;
760 INT src2 = -1;
761 src1 = FLD (in_src1);
762 src2 = FLD (in_src2);
763 referenced |= 1 << 0;
764 referenced |= 1 << 1;
ddfae34d 765 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, src1, src2);
368fc7db
DE		 766 }
767 return cycles;
768#undef FLD
769}
770
771static int
772model_m32rx_cmpi (SIM_CPU *current_cpu, void *sem_arg)
773{
774#define FLD(f) abuf->fields.fmt_cmpi.f
ddfae34d
DE		 775 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
776 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 777 int cycles = 0;
778 {
779 int referenced = 0;
780 int UNUSED insn_referenced = abuf->written;
781 INT src1 = -1;
782 INT src2 = -1;
783 src2 = FLD (in_src2);
784 referenced |= 1 << 1;
ddfae34d 785 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, src1, src2);
368fc7db
DE		 786 }
787 return cycles;
788#undef FLD
789}
790
791static int
792model_m32rx_cmpu (SIM_CPU *current_cpu, void *sem_arg)
793{
794#define FLD(f) abuf->fields.fmt_cmp.f
ddfae34d
DE		 795 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
796 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 797 int cycles = 0;
798 {
799 int referenced = 0;
800 int UNUSED insn_referenced = abuf->written;
801 INT src1 = -1;
802 INT src2 = -1;
803 src1 = FLD (in_src1);
804 src2 = FLD (in_src2);
805 referenced |= 1 << 0;
806 referenced |= 1 << 1;
ddfae34d 807 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, src1, src2);
368fc7db
DE		 808 }
809 return cycles;
810#undef FLD
811}
812
813static int
814model_m32rx_cmpui (SIM_CPU *current_cpu, void *sem_arg)
815{
816#define FLD(f) abuf->fields.fmt_cmpi.f
ddfae34d
DE		 817 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
818 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 819 int cycles = 0;
820 {
821 int referenced = 0;
822 int UNUSED insn_referenced = abuf->written;
823 INT src1 = -1;
824 INT src2 = -1;
825 src2 = FLD (in_src2);
826 referenced |= 1 << 1;
ddfae34d 827 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, src1, src2);
368fc7db
DE		 828 }
829 return cycles;
830#undef FLD
831}
832
833static int
834model_m32rx_cmpeq (SIM_CPU *current_cpu, void *sem_arg)
835{
836#define FLD(f) abuf->fields.fmt_cmp.f
ddfae34d
DE		 837 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
838 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 839 int cycles = 0;
840 {
841 int referenced = 0;
842 int UNUSED insn_referenced = abuf->written;
843 INT src1 = -1;
844 INT src2 = -1;
845 src1 = FLD (in_src1);
846 src2 = FLD (in_src2);
847 referenced |= 1 << 0;
848 referenced |= 1 << 1;
ddfae34d 849 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, src1, src2);
368fc7db
DE		 850 }
851 return cycles;
852#undef FLD
853}
854
855static int
856model_m32rx_cmpz (SIM_CPU *current_cpu, void *sem_arg)
857{
858#define FLD(f) abuf->fields.fmt_cmpz.f
ddfae34d
DE		 859 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
860 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 861 int cycles = 0;
862 {
863 int referenced = 0;
864 int UNUSED insn_referenced = abuf->written;
865 INT src1 = -1;
866 INT src2 = -1;
867 src2 = FLD (in_src2);
868 referenced |= 1 << 1;
ddfae34d 869 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, src1, src2);
368fc7db
DE		 870 }
871 return cycles;
872#undef FLD
873}
874
875static int
876model_m32rx_div (SIM_CPU *current_cpu, void *sem_arg)
877{
878#define FLD(f) abuf->fields.fmt_div.f
ddfae34d
DE		 879 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
880 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 881 int cycles = 0;
882 {
883 int referenced = 0;
884 int UNUSED insn_referenced = abuf->written;
885 INT sr = -1;
886 INT sr2 = -1;
887 INT dr = -1;
888 sr = FLD (in_sr);
889 dr = FLD (out_dr);
890 referenced |= 1 << 0;
891 if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
ddfae34d 892 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
368fc7db
DE		 893 }
894 return cycles;
895#undef FLD
896}
897
898static int
899model_m32rx_divu (SIM_CPU *current_cpu, void *sem_arg)
900{
901#define FLD(f) abuf->fields.fmt_div.f
ddfae34d
DE		 902 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
903 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 904 int cycles = 0;
905 {
906 int referenced = 0;
907 int UNUSED insn_referenced = abuf->written;
908 INT sr = -1;
909 INT sr2 = -1;
910 INT dr = -1;
911 sr = FLD (in_sr);
912 dr = FLD (out_dr);
913 referenced |= 1 << 0;
914 if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
ddfae34d 915 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
368fc7db
DE		 916 }
917 return cycles;
918#undef FLD
919}
920
921static int
922model_m32rx_rem (SIM_CPU *current_cpu, void *sem_arg)
923{
924#define FLD(f) abuf->fields.fmt_div.f
ddfae34d
DE		 925 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
926 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 927 int cycles = 0;
928 {
929 int referenced = 0;
930 int UNUSED insn_referenced = abuf->written;
931 INT sr = -1;
932 INT sr2 = -1;
933 INT dr = -1;
934 sr = FLD (in_sr);
935 dr = FLD (out_dr);
936 referenced |= 1 << 0;
937 if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
ddfae34d 938 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
368fc7db
DE		 939 }
940 return cycles;
941#undef FLD
942}
943
944static int
945model_m32rx_remu (SIM_CPU *current_cpu, void *sem_arg)
946{
947#define FLD(f) abuf->fields.fmt_div.f
ddfae34d
DE		 948 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
949 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 950 int cycles = 0;
951 {
952 int referenced = 0;
953 int UNUSED insn_referenced = abuf->written;
954 INT sr = -1;
955 INT sr2 = -1;
956 INT dr = -1;
957 sr = FLD (in_sr);
958 dr = FLD (out_dr);
959 referenced |= 1 << 0;
960 if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
ddfae34d 961 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
368fc7db
DE		 962 }
963 return cycles;
964#undef FLD
965}
966
967static int
968model_m32rx_divh (SIM_CPU *current_cpu, void *sem_arg)
969{
970#define FLD(f) abuf->fields.fmt_div.f
ddfae34d
DE		 971 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
972 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 973 int cycles = 0;
974 {
975 int referenced = 0;
976 int UNUSED insn_referenced = abuf->written;
977 INT sr = -1;
978 INT sr2 = -1;
979 INT dr = -1;
980 sr = FLD (in_sr);
981 dr = FLD (out_dr);
982 referenced |= 1 << 0;
983 if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
ddfae34d 984 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
368fc7db
DE		 985 }
986 return cycles;
987#undef FLD
988}
989
990static int
991model_m32rx_jc (SIM_CPU *current_cpu, void *sem_arg)
992{
993#define FLD(f) abuf->fields.cti.fields.fmt_jc.f
ddfae34d
DE		 994 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
995 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 996 int cycles = 0;
997 {
998 int referenced = 0;
999 int UNUSED insn_referenced = abuf->written;
1000 INT sr = -1;
1001 sr = FLD (in_sr);
1002 if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
1003 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
ddfae34d 1004 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr);
368fc7db
DE		 1005 }
1006 return cycles;
1007#undef FLD
1008}
1009
1010static int
1011model_m32rx_jnc (SIM_CPU *current_cpu, void *sem_arg)
1012{
1013#define FLD(f) abuf->fields.cti.fields.fmt_jc.f
ddfae34d
DE		 1014 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1015 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1016 int cycles = 0;
1017 {
1018 int referenced = 0;
1019 int UNUSED insn_referenced = abuf->written;
1020 INT sr = -1;
1021 sr = FLD (in_sr);
1022 if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
1023 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
ddfae34d 1024 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr);
368fc7db
DE		 1025 }
1026 return cycles;
1027#undef FLD
1028}
1029
1030static int
1031model_m32rx_jl (SIM_CPU *current_cpu, void *sem_arg)
1032{
1033#define FLD(f) abuf->fields.cti.fields.fmt_jl.f
ddfae34d
DE		 1034 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1035 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1036 int cycles = 0;
1037 {
1038 int referenced = 0;
1039 int UNUSED insn_referenced = abuf->written;
1040 INT sr = -1;
1041 sr = FLD (in_sr);
1042 referenced |= 1 << 0;
1043 referenced |= 1 << 1;
ddfae34d 1044 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr);
368fc7db
DE		 1045 }
1046 return cycles;
1047#undef FLD
1048}
1049
1050static int
1051model_m32rx_jmp (SIM_CPU *current_cpu, void *sem_arg)
1052{
1053#define FLD(f) abuf->fields.cti.fields.fmt_jmp.f
ddfae34d
DE		 1054 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1055 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1056 int cycles = 0;
1057 {
1058 int referenced = 0;
1059 int UNUSED insn_referenced = abuf->written;
1060 INT sr = -1;
1061 sr = FLD (in_sr);
1062 referenced |= 1 << 0;
1063 referenced |= 1 << 1;
ddfae34d 1064 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr);
368fc7db
DE		 1065 }
1066 return cycles;
1067#undef FLD
1068}
1069
1070static int
1071model_m32rx_ld (SIM_CPU *current_cpu, void *sem_arg)
1072{
1073#define FLD(f) abuf->fields.fmt_ld.f
ddfae34d
DE		 1074 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1075 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1076 int cycles = 0;
1077 {
1078 int referenced = 0;
1079 int UNUSED insn_referenced = abuf->written;
1080 INT sr = 0;
1081 INT dr = 0;
1082 sr = FLD (in_sr);
1083 dr = FLD (out_dr);
1084 referenced |= 1 << 0;
1085 referenced |= 1 << 1;
ddfae34d 1086 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, sr, dr);
368fc7db
DE		 1087 }
1088 return cycles;
1089#undef FLD
1090}
1091
1092static int
1093model_m32rx_ld_d (SIM_CPU *current_cpu, void *sem_arg)
1094{
1095#define FLD(f) abuf->fields.fmt_ld_d.f
ddfae34d
DE		 1096 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1097 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1098 int cycles = 0;
1099 {
1100 int referenced = 0;
1101 int UNUSED insn_referenced = abuf->written;
1102 INT sr = 0;
1103 INT dr = 0;
1104 sr = FLD (in_sr);
1105 dr = FLD (out_dr);
1106 referenced |= 1 << 0;
1107 referenced |= 1 << 1;
ddfae34d 1108 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, sr, dr);
368fc7db
DE		 1109 }
1110 return cycles;
1111#undef FLD
1112}
1113
1114static int
1115model_m32rx_ldb (SIM_CPU *current_cpu, void *sem_arg)
1116{
1117#define FLD(f) abuf->fields.fmt_ldb.f
ddfae34d
DE		 1118 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1119 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1120 int cycles = 0;
1121 {
1122 int referenced = 0;
1123 int UNUSED insn_referenced = abuf->written;
1124 INT sr = 0;
1125 INT dr = 0;
1126 sr = FLD (in_sr);
1127 dr = FLD (out_dr);
1128 referenced |= 1 << 0;
1129 referenced |= 1 << 1;
ddfae34d 1130 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, sr, dr);
368fc7db
DE		 1131 }
1132 return cycles;
1133#undef FLD
1134}
1135
1136static int
1137model_m32rx_ldb_d (SIM_CPU *current_cpu, void *sem_arg)
1138{
1139#define FLD(f) abuf->fields.fmt_ldb_d.f
ddfae34d
DE		 1140 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1141 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1142 int cycles = 0;
1143 {
1144 int referenced = 0;
1145 int UNUSED insn_referenced = abuf->written;
1146 INT sr = 0;
1147 INT dr = 0;
1148 sr = FLD (in_sr);
1149 dr = FLD (out_dr);
1150 referenced |= 1 << 0;
1151 referenced |= 1 << 1;
ddfae34d 1152 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, sr, dr);
368fc7db
DE		 1153 }
1154 return cycles;
1155#undef FLD
1156}
1157
1158static int
1159model_m32rx_ldh (SIM_CPU *current_cpu, void *sem_arg)
1160{
1161#define FLD(f) abuf->fields.fmt_ldh.f
ddfae34d
DE		 1162 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1163 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1164 int cycles = 0;
1165 {
1166 int referenced = 0;
1167 int UNUSED insn_referenced = abuf->written;
1168 INT sr = 0;
1169 INT dr = 0;
1170 sr = FLD (in_sr);
1171 dr = FLD (out_dr);
1172 referenced |= 1 << 0;
1173 referenced |= 1 << 1;
ddfae34d 1174 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, sr, dr);
368fc7db
DE		 1175 }
1176 return cycles;
1177#undef FLD
1178}
1179
1180static int
1181model_m32rx_ldh_d (SIM_CPU *current_cpu, void *sem_arg)
1182{
1183#define FLD(f) abuf->fields.fmt_ldh_d.f
ddfae34d
DE		 1184 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1185 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1186 int cycles = 0;
1187 {
1188 int referenced = 0;
1189 int UNUSED insn_referenced = abuf->written;
1190 INT sr = 0;
1191 INT dr = 0;
1192 sr = FLD (in_sr);
1193 dr = FLD (out_dr);
1194 referenced |= 1 << 0;
1195 referenced |= 1 << 1;
ddfae34d 1196 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, sr, dr);
368fc7db
DE		 1197 }
1198 return cycles;
1199#undef FLD
1200}
1201
1202static int
1203model_m32rx_ldub (SIM_CPU *current_cpu, void *sem_arg)
1204{
1205#define FLD(f) abuf->fields.fmt_ldb.f
ddfae34d
DE		 1206 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1207 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1208 int cycles = 0;
1209 {
1210 int referenced = 0;
1211 int UNUSED insn_referenced = abuf->written;
1212 INT sr = 0;
1213 INT dr = 0;
1214 sr = FLD (in_sr);
1215 dr = FLD (out_dr);
1216 referenced |= 1 << 0;
1217 referenced |= 1 << 1;
ddfae34d 1218 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, sr, dr);
368fc7db
DE		 1219 }
1220 return cycles;
1221#undef FLD
1222}
1223
1224static int
1225model_m32rx_ldub_d (SIM_CPU *current_cpu, void *sem_arg)
1226{
1227#define FLD(f) abuf->fields.fmt_ldb_d.f
ddfae34d
DE		 1228 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1229 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1230 int cycles = 0;
1231 {
1232 int referenced = 0;
1233 int UNUSED insn_referenced = abuf->written;
1234 INT sr = 0;
1235 INT dr = 0;
1236 sr = FLD (in_sr);
1237 dr = FLD (out_dr);
1238 referenced |= 1 << 0;
1239 referenced |= 1 << 1;
ddfae34d 1240 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, sr, dr);
368fc7db
DE		 1241 }
1242 return cycles;
1243#undef FLD
1244}
1245
1246static int
1247model_m32rx_lduh (SIM_CPU *current_cpu, void *sem_arg)
1248{
1249#define FLD(f) abuf->fields.fmt_ldh.f
ddfae34d
DE		 1250 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1251 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1252 int cycles = 0;
1253 {
1254 int referenced = 0;
1255 int UNUSED insn_referenced = abuf->written;
1256 INT sr = 0;
1257 INT dr = 0;
1258 sr = FLD (in_sr);
1259 dr = FLD (out_dr);
1260 referenced |= 1 << 0;
1261 referenced |= 1 << 1;
ddfae34d 1262 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, sr, dr);
368fc7db
DE		 1263 }
1264 return cycles;
1265#undef FLD
1266}
1267
1268static int
1269model_m32rx_lduh_d (SIM_CPU *current_cpu, void *sem_arg)
1270{
1271#define FLD(f) abuf->fields.fmt_ldh_d.f
ddfae34d
DE		 1272 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1273 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1274 int cycles = 0;
1275 {
1276 int referenced = 0;
1277 int UNUSED insn_referenced = abuf->written;
1278 INT sr = 0;
1279 INT dr = 0;
1280 sr = FLD (in_sr);
1281 dr = FLD (out_dr);
1282 referenced |= 1 << 0;
1283 referenced |= 1 << 1;
ddfae34d 1284 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, sr, dr);
368fc7db
DE		 1285 }
1286 return cycles;
1287#undef FLD
1288}
1289
1290static int
1291model_m32rx_ld_plus (SIM_CPU *current_cpu, void *sem_arg)
1292{
1293#define FLD(f) abuf->fields.fmt_ld_plus.f
ddfae34d
DE		 1294 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1295 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1296 int cycles = 0;
1297 {
1298 int referenced = 0;
1299 int UNUSED insn_referenced = abuf->written;
1300 INT sr = 0;
1301 INT dr = 0;
1302 sr = FLD (in_sr);
1303 dr = FLD (out_dr);
1304 referenced |= 1 << 0;
1305 referenced |= 1 << 1;
ddfae34d 1306 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, sr, dr);
368fc7db
DE		 1307 }
1308 {
1309 int referenced = 0;
1310 int UNUSED insn_referenced = abuf->written;
1311 INT sr = -1;
1312 INT sr2 = -1;
1313 INT dr = -1;
1314 sr = FLD (in_sr);
1315 dr = FLD (out_sr);
1316 referenced |= 1 << 0;
1317 referenced |= 1 << 2;
ddfae34d 1318 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 1, referenced, sr, sr2, dr);
368fc7db
DE		 1319 }
1320 return cycles;
1321#undef FLD
1322}
1323
1324static int
1325model_m32rx_ld24 (SIM_CPU *current_cpu, void *sem_arg)
1326{
1327#define FLD(f) abuf->fields.fmt_ld24.f
ddfae34d
DE		 1328 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1329 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1330 int cycles = 0;
1331 {
1332 int referenced = 0;
1333 int UNUSED insn_referenced = abuf->written;
1334 INT sr = -1;
1335 INT sr2 = -1;
1336 INT dr = -1;
1337 dr = FLD (out_dr);
1338 referenced |= 1 << 2;
ddfae34d 1339 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
368fc7db
DE		 1340 }
1341 return cycles;
1342#undef FLD
1343}
1344
1345static int
1346model_m32rx_ldi8 (SIM_CPU *current_cpu, void *sem_arg)
1347{
1348#define FLD(f) abuf->fields.fmt_ldi8.f
ddfae34d
DE		 1349 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1350 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1351 int cycles = 0;
1352 {
1353 int referenced = 0;
1354 int UNUSED insn_referenced = abuf->written;
1355 INT sr = -1;
1356 INT sr2 = -1;
1357 INT dr = -1;
1358 dr = FLD (out_dr);
1359 referenced |= 1 << 2;
ddfae34d 1360 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
368fc7db
DE		 1361 }
1362 return cycles;
1363#undef FLD
1364}
1365
1366static int
1367model_m32rx_ldi16 (SIM_CPU *current_cpu, void *sem_arg)
1368{
1369#define FLD(f) abuf->fields.fmt_ldi16.f
ddfae34d
DE		 1370 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1371 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1372 int cycles = 0;
1373 {
1374 int referenced = 0;
1375 int UNUSED insn_referenced = abuf->written;
1376 INT sr = -1;
1377 INT sr2 = -1;
1378 INT dr = -1;
1379 dr = FLD (out_dr);
1380 referenced |= 1 << 2;
ddfae34d 1381 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
368fc7db
DE		 1382 }
1383 return cycles;
1384#undef FLD
1385}
1386
1387static int
1388model_m32rx_lock (SIM_CPU *current_cpu, void *sem_arg)
1389{
1390#define FLD(f) abuf->fields.fmt_lock.f
ddfae34d
DE		 1391 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1392 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1393 int cycles = 0;
1394 {
1395 int referenced = 0;
1396 int UNUSED insn_referenced = abuf->written;
1397 INT sr = 0;
1398 INT dr = 0;
1399 sr = FLD (in_sr);
1400 dr = FLD (out_dr);
1401 referenced |= 1 << 0;
1402 referenced |= 1 << 1;
ddfae34d 1403 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, sr, dr);
368fc7db
DE		 1404 }
1405 return cycles;
1406#undef FLD
1407}
1408
1409static int
1410model_m32rx_machi_a (SIM_CPU *current_cpu, void *sem_arg)
1411{
1412#define FLD(f) abuf->fields.fmt_machi_a.f
ddfae34d
DE		 1413 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1414 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1415 int cycles = 0;
1416 {
1417 int referenced = 0;
1418 int UNUSED insn_referenced = abuf->written;
1419 INT src1 = -1;
1420 INT src2 = -1;
1421 src1 = FLD (in_src1);
1422 src2 = FLD (in_src2);
1423 referenced |= 1 << 0;
1424 referenced |= 1 << 1;
ddfae34d 1425 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, src1, src2);
368fc7db
DE		 1426 }
1427 return cycles;
1428#undef FLD
1429}
1430
1431static int
1432model_m32rx_maclo_a (SIM_CPU *current_cpu, void *sem_arg)
1433{
1434#define FLD(f) abuf->fields.fmt_machi_a.f
ddfae34d
DE		 1435 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1436 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1437 int cycles = 0;
1438 {
1439 int referenced = 0;
1440 int UNUSED insn_referenced = abuf->written;
1441 INT src1 = -1;
1442 INT src2 = -1;
1443 src1 = FLD (in_src1);
1444 src2 = FLD (in_src2);
1445 referenced |= 1 << 0;
1446 referenced |= 1 << 1;
ddfae34d 1447 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, src1, src2);
368fc7db
DE		 1448 }
1449 return cycles;
1450#undef FLD
1451}
1452
1453static int
1454model_m32rx_macwhi_a (SIM_CPU *current_cpu, void *sem_arg)
1455{
1456#define FLD(f) abuf->fields.fmt_machi_a.f
ddfae34d
DE		 1457 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1458 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1459 int cycles = 0;
1460 {
1461 int referenced = 0;
1462 int UNUSED insn_referenced = abuf->written;
1463 INT src1 = -1;
1464 INT src2 = -1;
1465 src1 = FLD (in_src1);
1466 src2 = FLD (in_src2);
1467 referenced |= 1 << 0;
1468 referenced |= 1 << 1;
ddfae34d 1469 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, src1, src2);
368fc7db
DE		 1470 }
1471 return cycles;
1472#undef FLD
1473}
1474
1475static int
1476model_m32rx_macwlo_a (SIM_CPU *current_cpu, void *sem_arg)
1477{
1478#define FLD(f) abuf->fields.fmt_machi_a.f
ddfae34d
DE		 1479 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1480 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1481 int cycles = 0;
1482 {
1483 int referenced = 0;
1484 int UNUSED insn_referenced = abuf->written;
1485 INT src1 = -1;
1486 INT src2 = -1;
1487 src1 = FLD (in_src1);
1488 src2 = FLD (in_src2);
1489 referenced |= 1 << 0;
1490 referenced |= 1 << 1;
ddfae34d 1491 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, src1, src2);
368fc7db
DE		 1492 }
1493 return cycles;
1494#undef FLD
1495}
1496
1497static int
1498model_m32rx_mul (SIM_CPU *current_cpu, void *sem_arg)
1499{
1500#define FLD(f) abuf->fields.fmt_add.f
ddfae34d
DE		 1501 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1502 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1503 int cycles = 0;
1504 {
1505 int referenced = 0;
1506 int UNUSED insn_referenced = abuf->written;
1507 INT sr = -1;
1508 INT sr2 = -1;
1509 INT dr = -1;
1510 sr = FLD (in_sr);
1511 dr = FLD (out_dr);
1512 referenced |= 1 << 0;
1513 referenced |= 1 << 2;
ddfae34d 1514 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
368fc7db
DE		 1515 }
1516 return cycles;
1517#undef FLD
1518}
1519
1520static int
1521model_m32rx_mulhi_a (SIM_CPU *current_cpu, void *sem_arg)
1522{
1523#define FLD(f) abuf->fields.fmt_mulhi_a.f
ddfae34d
DE		 1524 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1525 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1526 int cycles = 0;
1527 {
1528 int referenced = 0;
1529 int UNUSED insn_referenced = abuf->written;
1530 INT src1 = -1;
1531 INT src2 = -1;
1532 src1 = FLD (in_src1);
1533 src2 = FLD (in_src2);
1534 referenced |= 1 << 0;
1535 referenced |= 1 << 1;
ddfae34d 1536 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, src1, src2);
368fc7db
DE		 1537 }
1538 return cycles;
1539#undef FLD
1540}
1541
1542static int
1543model_m32rx_mullo_a (SIM_CPU *current_cpu, void *sem_arg)
1544{
1545#define FLD(f) abuf->fields.fmt_mulhi_a.f
ddfae34d
DE		 1546 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1547 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1548 int cycles = 0;
1549 {
1550 int referenced = 0;
1551 int UNUSED insn_referenced = abuf->written;
1552 INT src1 = -1;
1553 INT src2 = -1;
1554 src1 = FLD (in_src1);
1555 src2 = FLD (in_src2);
1556 referenced |= 1 << 0;
1557 referenced |= 1 << 1;
ddfae34d 1558 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, src1, src2);
368fc7db
DE		 1559 }
1560 return cycles;
1561#undef FLD
1562}
1563
1564static int
1565model_m32rx_mulwhi_a (SIM_CPU *current_cpu, void *sem_arg)
1566{
1567#define FLD(f) abuf->fields.fmt_mulhi_a.f
ddfae34d
DE		 1568 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1569 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1570 int cycles = 0;
1571 {
1572 int referenced = 0;
1573 int UNUSED insn_referenced = abuf->written;
1574 INT src1 = -1;
1575 INT src2 = -1;
1576 src1 = FLD (in_src1);
1577 src2 = FLD (in_src2);
1578 referenced |= 1 << 0;
1579 referenced |= 1 << 1;
ddfae34d 1580 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, src1, src2);
368fc7db
DE		 1581 }
1582 return cycles;
1583#undef FLD
1584}
1585
1586static int
1587model_m32rx_mulwlo_a (SIM_CPU *current_cpu, void *sem_arg)
1588{
1589#define FLD(f) abuf->fields.fmt_mulhi_a.f
ddfae34d
DE		 1590 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1591 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1592 int cycles = 0;
1593 {
1594 int referenced = 0;
1595 int UNUSED insn_referenced = abuf->written;
1596 INT src1 = -1;
1597 INT src2 = -1;
1598 src1 = FLD (in_src1);
1599 src2 = FLD (in_src2);
1600 referenced |= 1 << 0;
1601 referenced |= 1 << 1;
ddfae34d 1602 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, src1, src2);
368fc7db
DE		 1603 }
1604 return cycles;
1605#undef FLD
1606}
1607
1608static int
1609model_m32rx_mv (SIM_CPU *current_cpu, void *sem_arg)
1610{
1611#define FLD(f) abuf->fields.fmt_mv.f
ddfae34d
DE		 1612 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1613 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1614 int cycles = 0;
1615 {
1616 int referenced = 0;
1617 int UNUSED insn_referenced = abuf->written;
1618 INT sr = -1;
1619 INT sr2 = -1;
1620 INT dr = -1;
1621 sr = FLD (in_sr);
1622 dr = FLD (out_dr);
1623 referenced |= 1 << 0;
1624 referenced |= 1 << 2;
ddfae34d 1625 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
368fc7db
DE		 1626 }
1627 return cycles;
1628#undef FLD
1629}
1630
1631static int
1632model_m32rx_mvfachi_a (SIM_CPU *current_cpu, void *sem_arg)
1633{
1634#define FLD(f) abuf->fields.fmt_mvfachi_a.f
ddfae34d
DE		 1635 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1636 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1637 int cycles = 0;
1638 {
1639 int referenced = 0;
1640 int UNUSED insn_referenced = abuf->written;
1641 INT sr = -1;
1642 INT sr2 = -1;
1643 INT dr = -1;
1644 dr = FLD (out_dr);
1645 referenced |= 1 << 2;
ddfae34d 1646 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
368fc7db
DE		 1647 }
1648 return cycles;
1649#undef FLD
1650}
1651
1652static int
1653model_m32rx_mvfaclo_a (SIM_CPU *current_cpu, void *sem_arg)
1654{
1655#define FLD(f) abuf->fields.fmt_mvfachi_a.f
ddfae34d
DE		 1656 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1657 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1658 int cycles = 0;
1659 {
1660 int referenced = 0;
1661 int UNUSED insn_referenced = abuf->written;
1662 INT sr = -1;
1663 INT sr2 = -1;
1664 INT dr = -1;
1665 dr = FLD (out_dr);
1666 referenced |= 1 << 2;
ddfae34d 1667 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
368fc7db
DE		 1668 }
1669 return cycles;
1670#undef FLD
1671}
1672
1673static int
1674model_m32rx_mvfacmi_a (SIM_CPU *current_cpu, void *sem_arg)
1675{
1676#define FLD(f) abuf->fields.fmt_mvfachi_a.f
ddfae34d
DE		 1677 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1678 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1679 int cycles = 0;
1680 {
1681 int referenced = 0;
1682 int UNUSED insn_referenced = abuf->written;
1683 INT sr = -1;
1684 INT sr2 = -1;
1685 INT dr = -1;
1686 dr = FLD (out_dr);
1687 referenced |= 1 << 2;
ddfae34d 1688 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
368fc7db
DE		 1689 }
1690 return cycles;
1691#undef FLD
1692}
1693
1694static int
1695model_m32rx_mvfc (SIM_CPU *current_cpu, void *sem_arg)
1696{
1697#define FLD(f) abuf->fields.fmt_mvfc.f
ddfae34d
DE		 1698 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1699 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1700 int cycles = 0;
1701 {
1702 int referenced = 0;
1703 int UNUSED insn_referenced = abuf->written;
1704 INT sr = -1;
1705 INT sr2 = -1;
1706 INT dr = -1;
1707 dr = FLD (out_dr);
1708 referenced |= 1 << 2;
ddfae34d 1709 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
368fc7db
DE		 1710 }
1711 return cycles;
1712#undef FLD
1713}
1714
1715static int
1716model_m32rx_mvtachi_a (SIM_CPU *current_cpu, void *sem_arg)
1717{
1718#define FLD(f) abuf->fields.fmt_mvtachi_a.f
ddfae34d
DE		 1719 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1720 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1721 int cycles = 0;
1722 {
1723 int referenced = 0;
1724 int UNUSED insn_referenced = abuf->written;
1725 INT sr = -1;
1726 INT sr2 = -1;
1727 INT dr = -1;
1728 sr = FLD (in_src1);
1729 referenced |= 1 << 0;
ddfae34d 1730 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
368fc7db
DE		 1731 }
1732 return cycles;
1733#undef FLD
1734}
1735
1736static int
1737model_m32rx_mvtaclo_a (SIM_CPU *current_cpu, void *sem_arg)
1738{
1739#define FLD(f) abuf->fields.fmt_mvtachi_a.f
ddfae34d
DE		 1740 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1741 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1742 int cycles = 0;
1743 {
1744 int referenced = 0;
1745 int UNUSED insn_referenced = abuf->written;
1746 INT sr = -1;
1747 INT sr2 = -1;
1748 INT dr = -1;
1749 sr = FLD (in_src1);
1750 referenced |= 1 << 0;
ddfae34d 1751 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
368fc7db
DE		 1752 }
1753 return cycles;
1754#undef FLD
1755}
1756
1757static int
1758model_m32rx_mvtc (SIM_CPU *current_cpu, void *sem_arg)
1759{
1760#define FLD(f) abuf->fields.fmt_mvtc.f
ddfae34d
DE		 1761 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1762 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1763 int cycles = 0;
1764 {
1765 int referenced = 0;
1766 int UNUSED insn_referenced = abuf->written;
1767 INT sr = -1;
1768 INT sr2 = -1;
1769 INT dr = -1;
1770 sr = FLD (in_sr);
1771 referenced |= 1 << 0;
ddfae34d 1772 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
368fc7db
DE		 1773 }
1774 return cycles;
1775#undef FLD
1776}
1777
1778static int
1779model_m32rx_neg (SIM_CPU *current_cpu, void *sem_arg)
1780{
1781#define FLD(f) abuf->fields.fmt_mv.f
ddfae34d
DE		 1782 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1783 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1784 int cycles = 0;
1785 {
1786 int referenced = 0;
1787 int UNUSED insn_referenced = abuf->written;
1788 INT sr = -1;
1789 INT sr2 = -1;
1790 INT dr = -1;
1791 sr = FLD (in_sr);
1792 dr = FLD (out_dr);
1793 referenced |= 1 << 0;
1794 referenced |= 1 << 2;
ddfae34d 1795 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
368fc7db
DE		 1796 }
1797 return cycles;
1798#undef FLD
1799}
1800
1801static int
1802model_m32rx_nop (SIM_CPU *current_cpu, void *sem_arg)
1803{
1804#define FLD(f) abuf->fields.fmt_nop.f
ddfae34d
DE		 1805 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1806 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1807 int cycles = 0;
1808 {
1809 int referenced = 0;
1810 int UNUSED insn_referenced = abuf->written;
1811 INT sr = -1;
1812 INT sr2 = -1;
1813 INT dr = -1;
ddfae34d 1814 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
368fc7db
DE		 1815 }
1816 return cycles;
1817#undef FLD
1818}
1819
1820static int
1821model_m32rx_not (SIM_CPU *current_cpu, void *sem_arg)
1822{
1823#define FLD(f) abuf->fields.fmt_mv.f
ddfae34d
DE		 1824 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1825 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1826 int cycles = 0;
1827 {
1828 int referenced = 0;
1829 int UNUSED insn_referenced = abuf->written;
1830 INT sr = -1;
1831 INT sr2 = -1;
1832 INT dr = -1;
1833 sr = FLD (in_sr);
1834 dr = FLD (out_dr);
1835 referenced |= 1 << 0;
1836 referenced |= 1 << 2;
ddfae34d 1837 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
368fc7db
DE		 1838 }
1839 return cycles;
1840#undef FLD
1841}
1842
1843static int
1844model_m32rx_rac_dsi (SIM_CPU *current_cpu, void *sem_arg)
1845{
1846#define FLD(f) abuf->fields.fmt_rac_dsi.f
ddfae34d
DE		 1847 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1848 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1849 int cycles = 0;
1850 {
1851 int referenced = 0;
1852 int UNUSED insn_referenced = abuf->written;
1853 INT src1 = -1;
1854 INT src2 = -1;
ddfae34d 1855 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, src1, src2);
368fc7db
DE		 1856 }
1857 return cycles;
1858#undef FLD
1859}
1860
1861static int
1862model_m32rx_rach_dsi (SIM_CPU *current_cpu, void *sem_arg)
1863{
1864#define FLD(f) abuf->fields.fmt_rac_dsi.f
ddfae34d
DE		 1865 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1866 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1867 int cycles = 0;
1868 {
1869 int referenced = 0;
1870 int UNUSED insn_referenced = abuf->written;
1871 INT src1 = -1;
1872 INT src2 = -1;
ddfae34d 1873 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, src1, src2);
368fc7db
DE		 1874 }
1875 return cycles;
1876#undef FLD
1877}
1878
1879static int
1880model_m32rx_rte (SIM_CPU *current_cpu, void *sem_arg)
1881{
1882#define FLD(f) abuf->fields.cti.fields.fmt_rte.f
ddfae34d
DE		 1883 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1884 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1885 int cycles = 0;
1886 {
1887 int referenced = 0;
1888 int UNUSED insn_referenced = abuf->written;
1889 INT sr = -1;
1890 INT sr2 = -1;
1891 INT dr = -1;
ddfae34d 1892 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
368fc7db
DE		 1893 }
1894 return cycles;
1895#undef FLD
1896}
1897
1898static int
1899model_m32rx_seth (SIM_CPU *current_cpu, void *sem_arg)
1900{
1901#define FLD(f) abuf->fields.fmt_seth.f
ddfae34d
DE		 1902 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1903 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1904 int cycles = 0;
1905 {
1906 int referenced = 0;
1907 int UNUSED insn_referenced = abuf->written;
1908 INT sr = -1;
1909 INT sr2 = -1;
1910 INT dr = -1;
1911 dr = FLD (out_dr);
1912 referenced |= 1 << 2;
ddfae34d 1913 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
368fc7db
DE		 1914 }
1915 return cycles;
1916#undef FLD
1917}
1918
1919static int
1920model_m32rx_sll (SIM_CPU *current_cpu, void *sem_arg)
1921{
1922#define FLD(f) abuf->fields.fmt_add.f
ddfae34d
DE		 1923 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1924 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1925 int cycles = 0;
1926 {
1927 int referenced = 0;
1928 int UNUSED insn_referenced = abuf->written;
1929 INT sr = -1;
1930 INT sr2 = -1;
1931 INT dr = -1;
1932 sr = FLD (in_sr);
1933 dr = FLD (out_dr);
1934 referenced |= 1 << 0;
1935 referenced |= 1 << 2;
ddfae34d 1936 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
368fc7db
DE		 1937 }
1938 return cycles;
1939#undef FLD
1940}
1941
1942static int
1943model_m32rx_sll3 (SIM_CPU *current_cpu, void *sem_arg)
1944{
1945#define FLD(f) abuf->fields.fmt_sll3.f
ddfae34d
DE		 1946 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1947 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1948 int cycles = 0;
1949 {
1950 int referenced = 0;
1951 int UNUSED insn_referenced = abuf->written;
1952 INT sr = -1;
1953 INT sr2 = -1;
1954 INT dr = -1;
1955 sr = FLD (in_sr);
1956 dr = FLD (out_dr);
1957 referenced |= 1 << 0;
1958 referenced |= 1 << 2;
ddfae34d 1959 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
368fc7db
DE		 1960 }
1961 return cycles;
1962#undef FLD
1963}
1964
1965static int
1966model_m32rx_slli (SIM_CPU *current_cpu, void *sem_arg)
1967{
1968#define FLD(f) abuf->fields.fmt_slli.f
ddfae34d
DE		 1969 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1970 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1971 int cycles = 0;
1972 {
1973 int referenced = 0;
1974 int UNUSED insn_referenced = abuf->written;
1975 INT sr = -1;
1976 INT sr2 = -1;
1977 INT dr = -1;
1978 dr = FLD (out_dr);
1979 referenced |= 1 << 2;
ddfae34d 1980 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
368fc7db
DE		 1981 }
1982 return cycles;
1983#undef FLD
1984}
1985
1986static int
1987model_m32rx_sra (SIM_CPU *current_cpu, void *sem_arg)
1988{
1989#define FLD(f) abuf->fields.fmt_add.f
ddfae34d
DE		 1990 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1991 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1992 int cycles = 0;
1993 {
1994 int referenced = 0;
1995 int UNUSED insn_referenced = abuf->written;
1996 INT sr = -1;
1997 INT sr2 = -1;
1998 INT dr = -1;
1999 sr = FLD (in_sr);
2000 dr = FLD (out_dr);
2001 referenced |= 1 << 0;
2002 referenced |= 1 << 2;
ddfae34d 2003 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
368fc7db
DE		 2004 }
2005 return cycles;
2006#undef FLD
2007}
2008
2009static int
2010model_m32rx_sra3 (SIM_CPU *current_cpu, void *sem_arg)
2011{
2012#define FLD(f) abuf->fields.fmt_sll3.f
ddfae34d
DE		 2013 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2014 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2015 int cycles = 0;
2016 {
2017 int referenced = 0;
2018 int UNUSED insn_referenced = abuf->written;
2019 INT sr = -1;
2020 INT sr2 = -1;
2021 INT dr = -1;
2022 sr = FLD (in_sr);
2023 dr = FLD (out_dr);
2024 referenced |= 1 << 0;
2025 referenced |= 1 << 2;
ddfae34d 2026 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
368fc7db
DE		 2027 }
2028 return cycles;
2029#undef FLD
2030}
2031
2032static int
2033model_m32rx_srai (SIM_CPU *current_cpu, void *sem_arg)
2034{
2035#define FLD(f) abuf->fields.fmt_slli.f
ddfae34d
DE		 2036 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2037 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2038 int cycles = 0;
2039 {
2040 int referenced = 0;
2041 int UNUSED insn_referenced = abuf->written;
2042 INT sr = -1;
2043 INT sr2 = -1;
2044 INT dr = -1;
2045 dr = FLD (out_dr);
2046 referenced |= 1 << 2;
ddfae34d 2047 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
368fc7db
DE		 2048 }
2049 return cycles;
2050#undef FLD
2051}
2052
2053static int
2054model_m32rx_srl (SIM_CPU *current_cpu, void *sem_arg)
2055{
2056#define FLD(f) abuf->fields.fmt_add.f
ddfae34d
DE		 2057 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2058 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2059 int cycles = 0;
2060 {
2061 int referenced = 0;
2062 int UNUSED insn_referenced = abuf->written;
2063 INT sr = -1;
2064 INT sr2 = -1;
2065 INT dr = -1;
2066 sr = FLD (in_sr);
2067 dr = FLD (out_dr);
2068 referenced |= 1 << 0;
2069 referenced |= 1 << 2;
ddfae34d 2070 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
368fc7db
DE		 2071 }
2072 return cycles;
2073#undef FLD
2074}
2075
2076static int
2077model_m32rx_srl3 (SIM_CPU *current_cpu, void *sem_arg)
2078{
2079#define FLD(f) abuf->fields.fmt_sll3.f
ddfae34d
DE		 2080 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2081 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2082 int cycles = 0;
2083 {
2084 int referenced = 0;
2085 int UNUSED insn_referenced = abuf->written;
2086 INT sr = -1;
2087 INT sr2 = -1;
2088 INT dr = -1;
2089 sr = FLD (in_sr);
2090 dr = FLD (out_dr);
2091 referenced |= 1 << 0;
2092 referenced |= 1 << 2;
ddfae34d 2093 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
368fc7db
DE		 2094 }
2095 return cycles;
2096#undef FLD
2097}
2098
2099static int
2100model_m32rx_srli (SIM_CPU *current_cpu, void *sem_arg)
2101{
2102#define FLD(f) abuf->fields.fmt_slli.f
ddfae34d
DE		 2103 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2104 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2105 int cycles = 0;
2106 {
2107 int referenced = 0;
2108 int UNUSED insn_referenced = abuf->written;
2109 INT sr = -1;
2110 INT sr2 = -1;
2111 INT dr = -1;
2112 dr = FLD (out_dr);
2113 referenced |= 1 << 2;
ddfae34d 2114 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
368fc7db
DE		 2115 }
2116 return cycles;
2117#undef FLD
2118}
2119
2120static int
2121model_m32rx_st (SIM_CPU *current_cpu, void *sem_arg)
2122{
2123#define FLD(f) abuf->fields.fmt_st.f
ddfae34d
DE		 2124 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2125 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2126 int cycles = 0;
2127 {
2128 int referenced = 0;
2129 int UNUSED insn_referenced = abuf->written;
2130 INT src1 = 0;
2131 INT src2 = 0;
2132 src1 = FLD (in_src1);
2133 src2 = FLD (in_src2);
2134 referenced |= 1 << 0;
2135 referenced |= 1 << 1;
ddfae34d 2136 cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, src1, src2);
368fc7db
DE		 2137 }
2138 return cycles;
2139#undef FLD
2140}
2141
2142static int
2143model_m32rx_st_d (SIM_CPU *current_cpu, void *sem_arg)
2144{
2145#define FLD(f) abuf->fields.fmt_st_d.f
ddfae34d
DE		 2146 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2147 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2148 int cycles = 0;
2149 {
2150 int referenced = 0;
2151 int UNUSED insn_referenced = abuf->written;
2152 INT src1 = 0;
2153 INT src2 = 0;
2154 src1 = FLD (in_src1);
2155 src2 = FLD (in_src2);
2156 referenced |= 1 << 0;
2157 referenced |= 1 << 1;
ddfae34d 2158 cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, src1, src2);
368fc7db
DE		 2159 }
2160 return cycles;
2161#undef FLD
2162}
2163
2164static int
2165model_m32rx_stb (SIM_CPU *current_cpu, void *sem_arg)
2166{
2167#define FLD(f) abuf->fields.fmt_stb.f
ddfae34d
DE		 2168 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2169 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2170 int cycles = 0;
2171 {
2172 int referenced = 0;
2173 int UNUSED insn_referenced = abuf->written;
2174 INT src1 = 0;
2175 INT src2 = 0;
2176 src1 = FLD (in_src1);
2177 src2 = FLD (in_src2);
2178 referenced |= 1 << 0;
2179 referenced |= 1 << 1;
ddfae34d 2180 cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, src1, src2);
368fc7db
DE		 2181 }
2182 return cycles;
2183#undef FLD
2184}
2185
2186static int
2187model_m32rx_stb_d (SIM_CPU *current_cpu, void *sem_arg)
2188{
2189#define FLD(f) abuf->fields.fmt_stb_d.f
ddfae34d
DE		 2190 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2191 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2192 int cycles = 0;
2193 {
2194 int referenced = 0;
2195 int UNUSED insn_referenced = abuf->written;
2196 INT src1 = 0;
2197 INT src2 = 0;
2198 src1 = FLD (in_src1);
2199 src2 = FLD (in_src2);
2200 referenced |= 1 << 0;
2201 referenced |= 1 << 1;
ddfae34d 2202 cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, src1, src2);
368fc7db
DE		 2203 }
2204 return cycles;
2205#undef FLD
2206}
2207
2208static int
2209model_m32rx_sth (SIM_CPU *current_cpu, void *sem_arg)
2210{
2211#define FLD(f) abuf->fields.fmt_sth.f
ddfae34d
DE		 2212 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2213 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2214 int cycles = 0;
2215 {
2216 int referenced = 0;
2217 int UNUSED insn_referenced = abuf->written;
2218 INT src1 = 0;
2219 INT src2 = 0;
2220 src1 = FLD (in_src1);
2221 src2 = FLD (in_src2);
2222 referenced |= 1 << 0;
2223 referenced |= 1 << 1;
ddfae34d 2224 cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, src1, src2);
368fc7db
DE		 2225 }
2226 return cycles;
2227#undef FLD
2228}
2229
2230static int
2231model_m32rx_sth_d (SIM_CPU *current_cpu, void *sem_arg)
2232{
2233#define FLD(f) abuf->fields.fmt_sth_d.f
ddfae34d
DE		 2234 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2235 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2236 int cycles = 0;
2237 {
2238 int referenced = 0;
2239 int UNUSED insn_referenced = abuf->written;
2240 INT src1 = 0;
2241 INT src2 = 0;
2242 src1 = FLD (in_src1);
2243 src2 = FLD (in_src2);
2244 referenced |= 1 << 0;
2245 referenced |= 1 << 1;
ddfae34d 2246 cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, src1, src2);
368fc7db
DE		 2247 }
2248 return cycles;
2249#undef FLD
2250}
2251
2252static int
2253model_m32rx_st_plus (SIM_CPU *current_cpu, void *sem_arg)
2254{
2255#define FLD(f) abuf->fields.fmt_st_plus.f
ddfae34d
DE		 2256 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2257 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2258 int cycles = 0;
2259 {
2260 int referenced = 0;
2261 int UNUSED insn_referenced = abuf->written;
2262 INT src1 = 0;
2263 INT src2 = 0;
2264 src1 = FLD (in_src1);
2265 src2 = FLD (in_src2);
2266 referenced |= 1 << 0;
2267 referenced |= 1 << 1;
ddfae34d 2268 cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, src1, src2);
368fc7db
DE		 2269 }
2270 {
2271 int referenced = 0;
2272 int UNUSED insn_referenced = abuf->written;
2273 INT sr = -1;
2274 INT sr2 = -1;
2275 INT dr = -1;
2276 dr = FLD (out_src2);
2277 sr = FLD (in_src2);
2278 referenced |= 1 << 0;
2279 referenced |= 1 << 2;
ddfae34d 2280 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 1, referenced, sr, sr2, dr);
368fc7db
DE		 2281 }
2282 return cycles;
2283#undef FLD
2284}
2285
2286static int
2287model_m32rx_st_minus (SIM_CPU *current_cpu, void *sem_arg)
2288{
2289#define FLD(f) abuf->fields.fmt_st_plus.f
ddfae34d
DE		 2290 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2291 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2292 int cycles = 0;
2293 {
2294 int referenced = 0;
2295 int UNUSED insn_referenced = abuf->written;
2296 INT src1 = 0;
2297 INT src2 = 0;
2298 src1 = FLD (in_src1);
2299 src2 = FLD (in_src2);
2300 referenced |= 1 << 0;
2301 referenced |= 1 << 1;
ddfae34d 2302 cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, src1, src2);
368fc7db
DE		 2303 }
2304 {
2305 int referenced = 0;
2306 int UNUSED insn_referenced = abuf->written;
2307 INT sr = -1;
2308 INT sr2 = -1;
2309 INT dr = -1;
2310 dr = FLD (out_src2);
2311 sr = FLD (in_src2);
2312 referenced |= 1 << 0;
2313 referenced |= 1 << 2;
ddfae34d 2314 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 1, referenced, sr, sr2, dr);
368fc7db
DE		 2315 }
2316 return cycles;
2317#undef FLD
2318}
2319
2320static int
2321model_m32rx_sub (SIM_CPU *current_cpu, void *sem_arg)
2322{
2323#define FLD(f) abuf->fields.fmt_add.f
ddfae34d
DE		 2324 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2325 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2326 int cycles = 0;
2327 {
2328 int referenced = 0;
2329 int UNUSED insn_referenced = abuf->written;
2330 INT sr = -1;
2331 INT sr2 = -1;
2332 INT dr = -1;
2333 sr = FLD (in_sr);
2334 dr = FLD (out_dr);
2335 referenced |= 1 << 0;
2336 referenced |= 1 << 2;
ddfae34d 2337 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
368fc7db
DE		 2338 }
2339 return cycles;
2340#undef FLD
2341}
2342
2343static int
2344model_m32rx_subv (SIM_CPU *current_cpu, void *sem_arg)
2345{
2346#define FLD(f) abuf->fields.fmt_addv.f
ddfae34d
DE		 2347 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2348 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2349 int cycles = 0;
2350 {
2351 int referenced = 0;
2352 int UNUSED insn_referenced = abuf->written;
2353 INT sr = -1;
2354 INT sr2 = -1;
2355 INT dr = -1;
2356 sr = FLD (in_sr);
2357 dr = FLD (out_dr);
2358 referenced |= 1 << 0;
2359 referenced |= 1 << 2;
ddfae34d 2360 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
368fc7db
DE		 2361 }
2362 return cycles;
2363#undef FLD
2364}
2365
2366static int
2367model_m32rx_subx (SIM_CPU *current_cpu, void *sem_arg)
2368{
2369#define FLD(f) abuf->fields.fmt_addx.f
ddfae34d
DE		 2370 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2371 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2372 int cycles = 0;
2373 {
2374 int referenced = 0;
2375 int UNUSED insn_referenced = abuf->written;
2376 INT sr = -1;
2377 INT sr2 = -1;
2378 INT dr = -1;
2379 sr = FLD (in_sr);
2380 dr = FLD (out_dr);
2381 referenced |= 1 << 0;
2382 referenced |= 1 << 2;
ddfae34d 2383 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
368fc7db
DE		 2384 }
2385 return cycles;
2386#undef FLD
2387}
2388
2389static int
2390model_m32rx_trap (SIM_CPU *current_cpu, void *sem_arg)
2391{
2392#define FLD(f) abuf->fields.cti.fields.fmt_trap.f
ddfae34d
DE		 2393 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2394 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2395 int cycles = 0;
2396 {
2397 int referenced = 0;
2398 int UNUSED insn_referenced = abuf->written;
2399 INT sr = -1;
2400 INT sr2 = -1;
2401 INT dr = -1;
ddfae34d 2402 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
368fc7db
DE		 2403 }
2404 return cycles;
2405#undef FLD
2406}
2407
2408static int
2409model_m32rx_unlock (SIM_CPU *current_cpu, void *sem_arg)
2410{
2411#define FLD(f) abuf->fields.fmt_unlock.f
ddfae34d
DE		 2412 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2413 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2414 int cycles = 0;
2415 {
2416 int referenced = 0;
2417 int UNUSED insn_referenced = abuf->written;
2418 INT sr = 0;
2419 INT dr = 0;
ddfae34d 2420 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, sr, dr);
368fc7db
DE		 2421 }
2422 return cycles;
2423#undef FLD
2424}
2425
2426static int
2427model_m32rx_satb (SIM_CPU *current_cpu, void *sem_arg)
2428{
2429#define FLD(f) abuf->fields.fmt_satb.f
ddfae34d
DE		 2430 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2431 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2432 int cycles = 0;
2433 {
2434 int referenced = 0;
2435 int UNUSED insn_referenced = abuf->written;
2436 INT sr = -1;
2437 INT sr2 = -1;
2438 INT dr = -1;
2439 sr = FLD (in_sr);
2440 dr = FLD (out_dr);
2441 referenced |= 1 << 0;
2442 referenced |= 1 << 2;
ddfae34d 2443 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
368fc7db
DE		 2444 }
2445 return cycles;
2446#undef FLD
2447}
2448
2449static int
2450model_m32rx_sath (SIM_CPU *current_cpu, void *sem_arg)
2451{
2452#define FLD(f) abuf->fields.fmt_satb.f
ddfae34d
DE		 2453 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2454 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2455 int cycles = 0;
2456 {
2457 int referenced = 0;
2458 int UNUSED insn_referenced = abuf->written;
2459 INT sr = -1;
2460 INT sr2 = -1;
2461 INT dr = -1;
2462 sr = FLD (in_sr);
2463 dr = FLD (out_dr);
2464 referenced |= 1 << 0;
2465 referenced |= 1 << 2;
ddfae34d 2466 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
368fc7db
DE		 2467 }
2468 return cycles;
2469#undef FLD
2470}
2471
2472static int
2473model_m32rx_sat (SIM_CPU *current_cpu, void *sem_arg)
2474{
2475#define FLD(f) abuf->fields.fmt_sat.f
ddfae34d
DE		 2476 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2477 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2478 int cycles = 0;
2479 {
2480 int referenced = 0;
2481 int UNUSED insn_referenced = abuf->written;
2482 INT sr = -1;
2483 INT sr2 = -1;
2484 INT dr = -1;
2485 sr = FLD (in_sr);
2486 dr = FLD (out_dr);
2487 if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
2488 referenced |= 1 << 2;
ddfae34d 2489 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
368fc7db
DE		 2490 }
2491 return cycles;
2492#undef FLD
2493}
2494
2495static int
2496model_m32rx_pcmpbz (SIM_CPU *current_cpu, void *sem_arg)
2497{
2498#define FLD(f) abuf->fields.fmt_cmpz.f
ddfae34d
DE		 2499 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2500 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2501 int cycles = 0;
2502 {
2503 int referenced = 0;
2504 int UNUSED insn_referenced = abuf->written;
2505 INT src1 = -1;
2506 INT src2 = -1;
2507 src2 = FLD (in_src2);
2508 referenced |= 1 << 1;
ddfae34d 2509 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, src1, src2);
368fc7db
DE		 2510 }
2511 return cycles;
2512#undef FLD
2513}
2514
2515static int
2516model_m32rx_sadd (SIM_CPU *current_cpu, void *sem_arg)
2517{
2518#define FLD(f) abuf->fields.fmt_sadd.f
ddfae34d
DE		 2519 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2520 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2521 int cycles = 0;
2522 {
2523 int referenced = 0;
2524 int UNUSED insn_referenced = abuf->written;
2525 INT src1 = -1;
2526 INT src2 = -1;
ddfae34d 2527 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, src1, src2);
368fc7db
DE		 2528 }
2529 return cycles;
2530#undef FLD
2531}
2532
2533static int
2534model_m32rx_macwu1 (SIM_CPU *current_cpu, void *sem_arg)
2535{
2536#define FLD(f) abuf->fields.fmt_macwu1.f
ddfae34d
DE		 2537 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2538 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2539 int cycles = 0;
2540 {
2541 int referenced = 0;
2542 int UNUSED insn_referenced = abuf->written;
2543 INT src1 = -1;
2544 INT src2 = -1;
2545 src1 = FLD (in_src1);
2546 src2 = FLD (in_src2);
2547 referenced |= 1 << 0;
2548 referenced |= 1 << 1;
ddfae34d 2549 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, src1, src2);
368fc7db
DE		 2550 }
2551 return cycles;
2552#undef FLD
2553}
2554
2555static int
2556model_m32rx_msblo (SIM_CPU *current_cpu, void *sem_arg)
2557{
2558#define FLD(f) abuf->fields.fmt_msblo.f
ddfae34d
DE		 2559 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2560 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2561 int cycles = 0;
2562 {
2563 int referenced = 0;
2564 int UNUSED insn_referenced = abuf->written;
2565 INT src1 = -1;
2566 INT src2 = -1;
2567 src1 = FLD (in_src1);
2568 src2 = FLD (in_src2);
2569 referenced |= 1 << 0;
2570 referenced |= 1 << 1;
ddfae34d 2571 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, src1, src2);
368fc7db
DE		 2572 }
2573 return cycles;
2574#undef FLD
2575}
2576
2577static int
2578model_m32rx_mulwu1 (SIM_CPU *current_cpu, void *sem_arg)
2579{
2580#define FLD(f) abuf->fields.fmt_mulwu1.f
ddfae34d
DE		 2581 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2582 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2583 int cycles = 0;
2584 {
2585 int referenced = 0;
2586 int UNUSED insn_referenced = abuf->written;
2587 INT src1 = -1;
2588 INT src2 = -1;
2589 src1 = FLD (in_src1);
2590 src2 = FLD (in_src2);
2591 referenced |= 1 << 0;
2592 referenced |= 1 << 1;
ddfae34d 2593 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, src1, src2);
368fc7db
DE		 2594 }
2595 return cycles;
2596#undef FLD
2597}
2598
2599static int
2600model_m32rx_maclh1 (SIM_CPU *current_cpu, void *sem_arg)
2601{
2602#define FLD(f) abuf->fields.fmt_macwu1.f
ddfae34d
DE		 2603 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2604 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2605 int cycles = 0;
2606 {
2607 int referenced = 0;
2608 int UNUSED insn_referenced = abuf->written;
2609 INT src1 = -1;
2610 INT src2 = -1;
2611 src1 = FLD (in_src1);
2612 src2 = FLD (in_src2);
2613 referenced |= 1 << 0;
2614 referenced |= 1 << 1;
ddfae34d 2615 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, src1, src2);
368fc7db
DE		 2616 }
2617 return cycles;
2618#undef FLD
2619}
2620
2621static int
2622model_m32rx_sc (SIM_CPU *current_cpu, void *sem_arg)
2623{
2624#define FLD(f) abuf->fields.cti.fields.fmt_sc.f
ddfae34d
DE		 2625 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2626 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2627 int cycles = 0;
2628 {
2629 int referenced = 0;
2630 int UNUSED insn_referenced = abuf->written;
2631 INT sr = -1;
2632 INT sr2 = -1;
2633 INT dr = -1;
ddfae34d 2634 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
368fc7db
DE		 2635 }
2636 return cycles;
2637#undef FLD
2638}
2639
2640static int
2641model_m32rx_snc (SIM_CPU *current_cpu, void *sem_arg)
2642{
2643#define FLD(f) abuf->fields.cti.fields.fmt_sc.f
ddfae34d
DE		 2644 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2645 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2646 int cycles = 0;
2647 {
2648 int referenced = 0;
2649 int UNUSED insn_referenced = abuf->written;
2650 INT sr = -1;
2651 INT sr2 = -1;
2652 INT dr = -1;
ddfae34d 2653 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
368fc7db
DE		 2654 }
2655 return cycles;
2656#undef FLD
e0bd6e18
DE		 2657}
2658
2659/* We assume UNIT_NONE == 0 because the tables don't always terminate
2660 entries with it. */
2661
2662/* Model timing data for `m32rx'. */
2663
2664static const INSN_TIMING m32rx_timing[] = {
ddfae34d
DE		 2665 { M32RXF_INSN_X_INVALID, 0, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2666 { M32RXF_INSN_X_AFTER, 0, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2667 { M32RXF_INSN_X_BEFORE, 0, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2668 { M32RXF_INSN_X_CTI_CHAIN, 0, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2669 { M32RXF_INSN_X_CHAIN, 0, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2670 { M32RXF_INSN_X_BEGIN, 0, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
368fc7db
DE		 2671 { M32RXF_INSN_ADD, model_m32rx_add, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2672 { M32RXF_INSN_ADD3, model_m32rx_add3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2673 { M32RXF_INSN_AND, model_m32rx_and, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2674 { M32RXF_INSN_AND3, model_m32rx_and3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2675 { M32RXF_INSN_OR, model_m32rx_or, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2676 { M32RXF_INSN_OR3, model_m32rx_or3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2677 { M32RXF_INSN_XOR, model_m32rx_xor, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2678 { M32RXF_INSN_XOR3, model_m32rx_xor3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2679 { M32RXF_INSN_ADDI, model_m32rx_addi, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2680 { M32RXF_INSN_ADDV, model_m32rx_addv, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2681 { M32RXF_INSN_ADDV3, model_m32rx_addv3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2682 { M32RXF_INSN_ADDX, model_m32rx_addx, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2683 { M32RXF_INSN_BC8, model_m32rx_bc8, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2684 { M32RXF_INSN_BC24, model_m32rx_bc24, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2685 { M32RXF_INSN_BEQ, model_m32rx_beq, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } },
2686 { M32RXF_INSN_BEQZ, model_m32rx_beqz, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } },
2687 { M32RXF_INSN_BGEZ, model_m32rx_bgez, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } },
2688 { M32RXF_INSN_BGTZ, model_m32rx_bgtz, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } },
2689 { M32RXF_INSN_BLEZ, model_m32rx_blez, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } },
2690 { M32RXF_INSN_BLTZ, model_m32rx_bltz, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } },
2691 { M32RXF_INSN_BNEZ, model_m32rx_bnez, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } },
2692 { M32RXF_INSN_BL8, model_m32rx_bl8, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2693 { M32RXF_INSN_BL24, model_m32rx_bl24, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2694 { M32RXF_INSN_BCL8, model_m32rx_bcl8, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2695 { M32RXF_INSN_BCL24, model_m32rx_bcl24, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2696 { M32RXF_INSN_BNC8, model_m32rx_bnc8, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2697 { M32RXF_INSN_BNC24, model_m32rx_bnc24, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2698 { M32RXF_INSN_BNE, model_m32rx_bne, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } },
2699 { M32RXF_INSN_BRA8, model_m32rx_bra8, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2700 { M32RXF_INSN_BRA24, model_m32rx_bra24, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2701 { M32RXF_INSN_BNCL8, model_m32rx_bncl8, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2702 { M32RXF_INSN_BNCL24, model_m32rx_bncl24, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2703 { M32RXF_INSN_CMP, model_m32rx_cmp, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } },
2704 { M32RXF_INSN_CMPI, model_m32rx_cmpi, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } },
2705 { M32RXF_INSN_CMPU, model_m32rx_cmpu, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } },
2706 { M32RXF_INSN_CMPUI, model_m32rx_cmpui, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } },
2707 { M32RXF_INSN_CMPEQ, model_m32rx_cmpeq, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } },
2708 { M32RXF_INSN_CMPZ, model_m32rx_cmpz, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } },
2709 { M32RXF_INSN_DIV, model_m32rx_div, { { (int) UNIT_M32RX_U_EXEC, 1, 37 } } },
2710 { M32RXF_INSN_DIVU, model_m32rx_divu, { { (int) UNIT_M32RX_U_EXEC, 1, 37 } } },
2711 { M32RXF_INSN_REM, model_m32rx_rem, { { (int) UNIT_M32RX_U_EXEC, 1, 37 } } },
2712 { M32RXF_INSN_REMU, model_m32rx_remu, { { (int) UNIT_M32RX_U_EXEC, 1, 37 } } },
2713 { M32RXF_INSN_DIVH, model_m32rx_divh, { { (int) UNIT_M32RX_U_EXEC, 1, 21 } } },
2714 { M32RXF_INSN_JC, model_m32rx_jc, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2715 { M32RXF_INSN_JNC, model_m32rx_jnc, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2716 { M32RXF_INSN_JL, model_m32rx_jl, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2717 { M32RXF_INSN_JMP, model_m32rx_jmp, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2718 { M32RXF_INSN_LD, model_m32rx_ld, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } },
2719 { M32RXF_INSN_LD_D, model_m32rx_ld_d, { { (int) UNIT_M32RX_U_LOAD, 1, 2 } } },
2720 { M32RXF_INSN_LDB, model_m32rx_ldb, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } },
2721 { M32RXF_INSN_LDB_D, model_m32rx_ldb_d, { { (int) UNIT_M32RX_U_LOAD, 1, 2 } } },
2722 { M32RXF_INSN_LDH, model_m32rx_ldh, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } },
2723 { M32RXF_INSN_LDH_D, model_m32rx_ldh_d, { { (int) UNIT_M32RX_U_LOAD, 1, 2 } } },
2724 { M32RXF_INSN_LDUB, model_m32rx_ldub, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } },
2725 { M32RXF_INSN_LDUB_D, model_m32rx_ldub_d, { { (int) UNIT_M32RX_U_LOAD, 1, 2 } } },
2726 { M32RXF_INSN_LDUH, model_m32rx_lduh, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } },
2727 { M32RXF_INSN_LDUH_D, model_m32rx_lduh_d, { { (int) UNIT_M32RX_U_LOAD, 1, 2 } } },
2728 { M32RXF_INSN_LD_PLUS, model_m32rx_ld_plus, { { (int) UNIT_M32RX_U_LOAD, 1, 1 }, { (int) UNIT_M32RX_U_EXEC, 1, 0 } } },
2729 { M32RXF_INSN_LD24, model_m32rx_ld24, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2730 { M32RXF_INSN_LDI8, model_m32rx_ldi8, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2731 { M32RXF_INSN_LDI16, model_m32rx_ldi16, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2732 { M32RXF_INSN_LOCK, model_m32rx_lock, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } },
2733 { M32RXF_INSN_MACHI_A, model_m32rx_machi_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2734 { M32RXF_INSN_MACLO_A, model_m32rx_maclo_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2735 { M32RXF_INSN_MACWHI_A, model_m32rx_macwhi_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2736 { M32RXF_INSN_MACWLO_A, model_m32rx_macwlo_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2737 { M32RXF_INSN_MUL, model_m32rx_mul, { { (int) UNIT_M32RX_U_EXEC, 1, 4 } } },
2738 { M32RXF_INSN_MULHI_A, model_m32rx_mulhi_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2739 { M32RXF_INSN_MULLO_A, model_m32rx_mullo_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2740 { M32RXF_INSN_MULWHI_A, model_m32rx_mulwhi_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2741 { M32RXF_INSN_MULWLO_A, model_m32rx_mulwlo_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2742 { M32RXF_INSN_MV, model_m32rx_mv, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2743 { M32RXF_INSN_MVFACHI_A, model_m32rx_mvfachi_a, { { (int) UNIT_M32RX_U_EXEC, 1, 2 } } },
2744 { M32RXF_INSN_MVFACLO_A, model_m32rx_mvfaclo_a, { { (int) UNIT_M32RX_U_EXEC, 1, 2 } } },
2745 { M32RXF_INSN_MVFACMI_A, model_m32rx_mvfacmi_a, { { (int) UNIT_M32RX_U_EXEC, 1, 2 } } },
2746 { M32RXF_INSN_MVFC, model_m32rx_mvfc, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2747 { M32RXF_INSN_MVTACHI_A, model_m32rx_mvtachi_a, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2748 { M32RXF_INSN_MVTACLO_A, model_m32rx_mvtaclo_a, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2749 { M32RXF_INSN_MVTC, model_m32rx_mvtc, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2750 { M32RXF_INSN_NEG, model_m32rx_neg, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2751 { M32RXF_INSN_NOP, model_m32rx_nop, { { (int) UNIT_M32RX_U_EXEC, 1, 0 } } },
2752 { M32RXF_INSN_NOT, model_m32rx_not, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2753 { M32RXF_INSN_RAC_DSI, model_m32rx_rac_dsi, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2754 { M32RXF_INSN_RACH_DSI, model_m32rx_rach_dsi, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2755 { M32RXF_INSN_RTE, model_m32rx_rte, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2756 { M32RXF_INSN_SETH, model_m32rx_seth, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2757 { M32RXF_INSN_SLL, model_m32rx_sll, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2758 { M32RXF_INSN_SLL3, model_m32rx_sll3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2759 { M32RXF_INSN_SLLI, model_m32rx_slli, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2760 { M32RXF_INSN_SRA, model_m32rx_sra, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2761 { M32RXF_INSN_SRA3, model_m32rx_sra3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2762 { M32RXF_INSN_SRAI, model_m32rx_srai, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2763 { M32RXF_INSN_SRL, model_m32rx_srl, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2764 { M32RXF_INSN_SRL3, model_m32rx_srl3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2765 { M32RXF_INSN_SRLI, model_m32rx_srli, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2766 { M32RXF_INSN_ST, model_m32rx_st, { { (int) UNIT_M32RX_U_STORE, 1, 1 } } },
2767 { M32RXF_INSN_ST_D, model_m32rx_st_d, { { (int) UNIT_M32RX_U_STORE, 1, 2 } } },
2768 { M32RXF_INSN_STB, model_m32rx_stb, { { (int) UNIT_M32RX_U_STORE, 1, 1 } } },
2769 { M32RXF_INSN_STB_D, model_m32rx_stb_d, { { (int) UNIT_M32RX_U_STORE, 1, 2 } } },
2770 { M32RXF_INSN_STH, model_m32rx_sth, { { (int) UNIT_M32RX_U_STORE, 1, 1 } } },
2771 { M32RXF_INSN_STH_D, model_m32rx_sth_d, { { (int) UNIT_M32RX_U_STORE, 1, 2 } } },
2772 { M32RXF_INSN_ST_PLUS, model_m32rx_st_plus, { { (int) UNIT_M32RX_U_STORE, 1, 1 }, { (int) UNIT_M32RX_U_EXEC, 1, 0 } } },
2773 { M32RXF_INSN_ST_MINUS, model_m32rx_st_minus, { { (int) UNIT_M32RX_U_STORE, 1, 1 }, { (int) UNIT_M32RX_U_EXEC, 1, 0 } } },
2774 { M32RXF_INSN_SUB, model_m32rx_sub, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2775 { M32RXF_INSN_SUBV, model_m32rx_subv, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2776 { M32RXF_INSN_SUBX, model_m32rx_subx, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2777 { M32RXF_INSN_TRAP, model_m32rx_trap, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2778 { M32RXF_INSN_UNLOCK, model_m32rx_unlock, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } },
2779 { M32RXF_INSN_SATB, model_m32rx_satb, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2780 { M32RXF_INSN_SATH, model_m32rx_sath, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2781 { M32RXF_INSN_SAT, model_m32rx_sat, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2782 { M32RXF_INSN_PCMPBZ, model_m32rx_pcmpbz, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } },
2783 { M32RXF_INSN_SADD, model_m32rx_sadd, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2784 { M32RXF_INSN_MACWU1, model_m32rx_macwu1, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2785 { M32RXF_INSN_MSBLO, model_m32rx_msblo, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2786 { M32RXF_INSN_MULWU1, model_m32rx_mulwu1, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2787 { M32RXF_INSN_MACLH1, model_m32rx_maclh1, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2788 { M32RXF_INSN_SC, model_m32rx_sc, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2789 { M32RXF_INSN_SNC, model_m32rx_snc, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
e0bd6e18
DE		 2790};
2791
2792#endif /* WITH_PROFILE_MODEL_P */
2793
368fc7db
DE		 2794static void
2795m32rx_model_init (SIM_CPU *cpu)
2796{
2797 CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_M32RX_DATA));
2798}
2799
e0bd6e18
DE		 2800#if WITH_PROFILE_MODEL_P
2801#define TIMING_DATA(td) td
2802#else
2803#define TIMING_DATA(td) 0
2804#endif
2805
368fc7db
DE		 2806static const MODEL m32rx_models[] =
2807{
2808 { "m32rx", & m32rx_mach, MODEL_M32RX, TIMING_DATA (& m32rx_timing[0]), m32rx_model_init },
e0bd6e18
DE		 2809 { 0 }
2810};
2811
2812/* The properties of this cpu's implementation. */
2813
368fc7db
DE		 2814static const MACH_IMP_PROPERTIES m32rxf_imp_properties =
2815{
2816 sizeof (SIM_CPU),
e0bd6e18 2817#if WITH_SCACHE
368fc7db
DE		 2818 sizeof (SCACHE)
2819#else
2820 0
2821#endif
2822};
2823
2824static const CGEN_INSN *
2825m32rxf_opcode (SIM_CPU *cpu, int inum)
2826{
2827 return CPU_IDESC (cpu) [inum].opcode;
2828}
2829
2830/* start-sanitize-m32rx */
2831static void
2832m32rx_init_cpu (SIM_CPU *cpu)
2833{
2834 CPU_REG_FETCH (cpu) = m32rxf_fetch_register;
2835 CPU_REG_STORE (cpu) = m32rxf_store_register;
2836 CPU_PC_FETCH (cpu) = m32rxf_h_pc_get;
2837 CPU_PC_STORE (cpu) = m32rxf_h_pc_set;
2838 CPU_OPCODE (cpu) = m32rxf_opcode;
2839 CPU_MAX_INSNS (cpu) = M32RXF_INSN_MAX;
2840 CPU_INSN_NAME (cpu) = cgen_insn_name;
2841 CPU_FULL_ENGINE_FN (cpu) = m32rxf_engine_run_full;
2842#if WITH_FAST
2843 CPU_FAST_ENGINE_FN (cpu) = m32rxf_engine_run_fast;
2844#else
2845 CPU_FAST_ENGINE_FN (cpu) = m32rxf_engine_run_full;
e0bd6e18 2846#endif
368fc7db
DE		 2847 m32rxf_init_idesc_table (cpu);
2848}
2849
2850const MACH m32rx_mach =
2851{
2852 "m32rx", "m32rx",
2853 32, 32, & m32rx_models[0], & m32rxf_imp_properties,
2854 m32rx_init_cpu
e0bd6e18
DE		 2855};
2856
368fc7db 2857/* end-sanitize-m32rx */
GDB Binutils - Deliverables
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