Commit | Line | Data |
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2ddc0492 DE |
1 | /* Simulator instruction semantics for m32r. |
2 | ||
e0bd6e18 DE |
3 | This file is machine generated with CGEN. |
4 | ||
2ddc0492 DE |
5 | Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. |
6 | ||
7 | This file is part of the GNU Simulators. | |
8 | ||
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2, or (at your option) | |
12 | any later version. | |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License along | |
20 | with this program; if not, write to the Free Software Foundation, Inc., | |
21 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
22 | ||
23 | */ | |
24 | ||
25 | #ifdef DEFINE_LABELS | |
26 | #undef DEFINE_LABELS | |
27 | ||
2ddc0492 DE |
28 | /* The labels have the case they have because the enum of insn types |
29 | is all uppercase and in the non-stdc case the insn symbol is built | |
a8981d67 DE |
30 | into the enum name. */ |
31 | ||
32 | static struct { | |
33 | int index; | |
34 | void *label; | |
35 | } labels[] = { | |
36 | { M32R_XINSN_ILLEGAL, && case_sem_INSN_ILLEGAL }, | |
37 | { M32R_XINSN_ADD, && case_sem_INSN_ADD }, | |
38 | { M32R_XINSN_ADD3, && case_sem_INSN_ADD3 }, | |
39 | { M32R_XINSN_AND, && case_sem_INSN_AND }, | |
40 | { M32R_XINSN_AND3, && case_sem_INSN_AND3 }, | |
41 | { M32R_XINSN_OR, && case_sem_INSN_OR }, | |
42 | { M32R_XINSN_OR3, && case_sem_INSN_OR3 }, | |
43 | { M32R_XINSN_XOR, && case_sem_INSN_XOR }, | |
44 | { M32R_XINSN_XOR3, && case_sem_INSN_XOR3 }, | |
45 | { M32R_XINSN_ADDI, && case_sem_INSN_ADDI }, | |
46 | { M32R_XINSN_ADDV, && case_sem_INSN_ADDV }, | |
47 | { M32R_XINSN_ADDV3, && case_sem_INSN_ADDV3 }, | |
48 | { M32R_XINSN_ADDX, && case_sem_INSN_ADDX }, | |
49 | { M32R_XINSN_BC8, && case_sem_INSN_BC8 }, | |
50 | { M32R_XINSN_BC24, && case_sem_INSN_BC24 }, | |
51 | { M32R_XINSN_BEQ, && case_sem_INSN_BEQ }, | |
52 | { M32R_XINSN_BEQZ, && case_sem_INSN_BEQZ }, | |
53 | { M32R_XINSN_BGEZ, && case_sem_INSN_BGEZ }, | |
54 | { M32R_XINSN_BGTZ, && case_sem_INSN_BGTZ }, | |
55 | { M32R_XINSN_BLEZ, && case_sem_INSN_BLEZ }, | |
56 | { M32R_XINSN_BLTZ, && case_sem_INSN_BLTZ }, | |
57 | { M32R_XINSN_BNEZ, && case_sem_INSN_BNEZ }, | |
58 | { M32R_XINSN_BL8, && case_sem_INSN_BL8 }, | |
59 | { M32R_XINSN_BL24, && case_sem_INSN_BL24 }, | |
60 | { M32R_XINSN_BNC8, && case_sem_INSN_BNC8 }, | |
61 | { M32R_XINSN_BNC24, && case_sem_INSN_BNC24 }, | |
62 | { M32R_XINSN_BNE, && case_sem_INSN_BNE }, | |
63 | { M32R_XINSN_BRA8, && case_sem_INSN_BRA8 }, | |
64 | { M32R_XINSN_BRA24, && case_sem_INSN_BRA24 }, | |
65 | { M32R_XINSN_CMP, && case_sem_INSN_CMP }, | |
66 | { M32R_XINSN_CMPI, && case_sem_INSN_CMPI }, | |
67 | { M32R_XINSN_CMPU, && case_sem_INSN_CMPU }, | |
68 | { M32R_XINSN_CMPUI, && case_sem_INSN_CMPUI }, | |
69 | { M32R_XINSN_DIV, && case_sem_INSN_DIV }, | |
70 | { M32R_XINSN_DIVU, && case_sem_INSN_DIVU }, | |
71 | { M32R_XINSN_REM, && case_sem_INSN_REM }, | |
72 | { M32R_XINSN_REMU, && case_sem_INSN_REMU }, | |
73 | { M32R_XINSN_JL, && case_sem_INSN_JL }, | |
74 | { M32R_XINSN_JMP, && case_sem_INSN_JMP }, | |
75 | { M32R_XINSN_LD, && case_sem_INSN_LD }, | |
76 | { M32R_XINSN_LD_D, && case_sem_INSN_LD_D }, | |
77 | { M32R_XINSN_LDB, && case_sem_INSN_LDB }, | |
78 | { M32R_XINSN_LDB_D, && case_sem_INSN_LDB_D }, | |
79 | { M32R_XINSN_LDH, && case_sem_INSN_LDH }, | |
80 | { M32R_XINSN_LDH_D, && case_sem_INSN_LDH_D }, | |
81 | { M32R_XINSN_LDUB, && case_sem_INSN_LDUB }, | |
82 | { M32R_XINSN_LDUB_D, && case_sem_INSN_LDUB_D }, | |
83 | { M32R_XINSN_LDUH, && case_sem_INSN_LDUH }, | |
84 | { M32R_XINSN_LDUH_D, && case_sem_INSN_LDUH_D }, | |
85 | { M32R_XINSN_LD_PLUS, && case_sem_INSN_LD_PLUS }, | |
86 | { M32R_XINSN_LD24, && case_sem_INSN_LD24 }, | |
87 | { M32R_XINSN_LDI8, && case_sem_INSN_LDI8 }, | |
88 | { M32R_XINSN_LDI16, && case_sem_INSN_LDI16 }, | |
89 | { M32R_XINSN_LOCK, && case_sem_INSN_LOCK }, | |
90 | { M32R_XINSN_MACHI, && case_sem_INSN_MACHI }, | |
91 | { M32R_XINSN_MACLO, && case_sem_INSN_MACLO }, | |
92 | { M32R_XINSN_MACWHI, && case_sem_INSN_MACWHI }, | |
93 | { M32R_XINSN_MACWLO, && case_sem_INSN_MACWLO }, | |
94 | { M32R_XINSN_MUL, && case_sem_INSN_MUL }, | |
95 | { M32R_XINSN_MULHI, && case_sem_INSN_MULHI }, | |
96 | { M32R_XINSN_MULLO, && case_sem_INSN_MULLO }, | |
97 | { M32R_XINSN_MULWHI, && case_sem_INSN_MULWHI }, | |
98 | { M32R_XINSN_MULWLO, && case_sem_INSN_MULWLO }, | |
99 | { M32R_XINSN_MV, && case_sem_INSN_MV }, | |
100 | { M32R_XINSN_MVFACHI, && case_sem_INSN_MVFACHI }, | |
101 | { M32R_XINSN_MVFACLO, && case_sem_INSN_MVFACLO }, | |
102 | { M32R_XINSN_MVFACMI, && case_sem_INSN_MVFACMI }, | |
103 | { M32R_XINSN_MVFC, && case_sem_INSN_MVFC }, | |
104 | { M32R_XINSN_MVTACHI, && case_sem_INSN_MVTACHI }, | |
105 | { M32R_XINSN_MVTACLO, && case_sem_INSN_MVTACLO }, | |
106 | { M32R_XINSN_MVTC, && case_sem_INSN_MVTC }, | |
107 | { M32R_XINSN_NEG, && case_sem_INSN_NEG }, | |
108 | { M32R_XINSN_NOP, && case_sem_INSN_NOP }, | |
109 | { M32R_XINSN_NOT, && case_sem_INSN_NOT }, | |
110 | { M32R_XINSN_RAC, && case_sem_INSN_RAC }, | |
111 | { M32R_XINSN_RACH, && case_sem_INSN_RACH }, | |
112 | { M32R_XINSN_RTE, && case_sem_INSN_RTE }, | |
113 | { M32R_XINSN_SETH, && case_sem_INSN_SETH }, | |
114 | { M32R_XINSN_SLL, && case_sem_INSN_SLL }, | |
115 | { M32R_XINSN_SLL3, && case_sem_INSN_SLL3 }, | |
116 | { M32R_XINSN_SLLI, && case_sem_INSN_SLLI }, | |
117 | { M32R_XINSN_SRA, && case_sem_INSN_SRA }, | |
118 | { M32R_XINSN_SRA3, && case_sem_INSN_SRA3 }, | |
119 | { M32R_XINSN_SRAI, && case_sem_INSN_SRAI }, | |
120 | { M32R_XINSN_SRL, && case_sem_INSN_SRL }, | |
121 | { M32R_XINSN_SRL3, && case_sem_INSN_SRL3 }, | |
122 | { M32R_XINSN_SRLI, && case_sem_INSN_SRLI }, | |
123 | { M32R_XINSN_ST, && case_sem_INSN_ST }, | |
124 | { M32R_XINSN_ST_D, && case_sem_INSN_ST_D }, | |
125 | { M32R_XINSN_STB, && case_sem_INSN_STB }, | |
126 | { M32R_XINSN_STB_D, && case_sem_INSN_STB_D }, | |
127 | { M32R_XINSN_STH, && case_sem_INSN_STH }, | |
128 | { M32R_XINSN_STH_D, && case_sem_INSN_STH_D }, | |
129 | { M32R_XINSN_ST_PLUS, && case_sem_INSN_ST_PLUS }, | |
130 | { M32R_XINSN_ST_MINUS, && case_sem_INSN_ST_MINUS }, | |
131 | { M32R_XINSN_SUB, && case_sem_INSN_SUB }, | |
132 | { M32R_XINSN_SUBV, && case_sem_INSN_SUBV }, | |
133 | { M32R_XINSN_SUBX, && case_sem_INSN_SUBX }, | |
134 | { M32R_XINSN_TRAP, && case_sem_INSN_TRAP }, | |
135 | { M32R_XINSN_UNLOCK, && case_sem_INSN_UNLOCK }, | |
136 | { 0, 0 } | |
2ddc0492 | 137 | }; |
2ddc0492 DE |
138 | int i; |
139 | ||
a8981d67 DE |
140 | for (i = 0; labels[i].label != 0; ++i) |
141 | CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label; | |
2ddc0492 DE |
142 | |
143 | #endif /* DEFINE_LABELS */ | |
144 | ||
145 | #ifdef DEFINE_SWITCH | |
146 | #undef DEFINE_SWITCH | |
147 | ||
148 | /* If hyper-fast [well not unnecessarily slow] execution is selected, turn | |
149 | off frills like tracing and profiling. */ | |
150 | /* FIXME: A better way would be to have TRACE_RESULT check for something | |
151 | that can cause it to be optimized out. */ | |
152 | ||
153 | #if FAST_P | |
154 | #undef TRACE_RESULT | |
155 | #define TRACE_RESULT(cpu, name, type, val) | |
156 | #endif | |
157 | ||
158 | #undef GET_ATTR | |
a8981d67 | 159 | #define GET_ATTR(cpu, num, attr) CGEN_INSN_ATTR (abuf->idesc->opcode, CGEN_INSN_##attr) |
2ddc0492 DE |
160 | |
161 | { | |
162 | SEM_ARG sem_arg = sc; | |
163 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
e0bd6e18 | 164 | CIA new_pc; |
2ddc0492 DE |
165 | |
166 | SWITCH (sem, sem_arg->semantic.sem_case) | |
167 | { | |
168 | ||
169 | CASE (sem, INSN_ILLEGAL) : | |
170 | { | |
171 | sim_engine_halt (CPU_STATE (current_cpu), current_cpu, NULL, NULL_CIA/*FIXME*/, | |
172 | sim_stopped, SIM_SIGILL); | |
173 | BREAK (sem); | |
174 | } | |
175 | ||
176 | CASE (sem, INSN_ADD) : /* add $dr,$sr */ | |
177 | { | |
970a8fd6 | 178 | #define FLD(f) abuf->fields.fmt_add.f |
02310b01 | 179 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 180 | |
2ddc0492 DE |
181 | * FLD (f_r1) = ADDSI (* FLD (f_r1), * FLD (f_r2)); |
182 | TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1)); | |
e0bd6e18 | 183 | |
2ddc0492 DE |
184 | #undef FLD |
185 | } | |
186 | BREAK (sem); | |
187 | ||
970a8fd6 | 188 | CASE (sem, INSN_ADD3) : /* add3 $dr,$sr,$hash$slo16 */ |
2ddc0492 | 189 | { |
970a8fd6 | 190 | #define FLD(f) abuf->fields.fmt_add3.f |
02310b01 | 191 | new_pc = SEM_NEXT_PC (sem_arg, 4); |
e0bd6e18 | 192 | |
2ddc0492 DE |
193 | * FLD (f_r1) = ADDSI (* FLD (f_r2), FLD (f_simm16)); |
194 | TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1)); | |
e0bd6e18 | 195 | |
2ddc0492 DE |
196 | #undef FLD |
197 | } | |
198 | BREAK (sem); | |
199 | ||
200 | CASE (sem, INSN_AND) : /* and $dr,$sr */ | |
201 | { | |
970a8fd6 | 202 | #define FLD(f) abuf->fields.fmt_add.f |
02310b01 | 203 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 204 | |
2ddc0492 DE |
205 | * FLD (f_r1) = ANDSI (* FLD (f_r1), * FLD (f_r2)); |
206 | TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1)); | |
e0bd6e18 | 207 | |
2ddc0492 DE |
208 | #undef FLD |
209 | } | |
210 | BREAK (sem); | |
211 | ||
970a8fd6 | 212 | CASE (sem, INSN_AND3) : /* and3 $dr,$sr,$uimm16 */ |
2ddc0492 | 213 | { |
970a8fd6 | 214 | #define FLD(f) abuf->fields.fmt_and3.f |
02310b01 | 215 | new_pc = SEM_NEXT_PC (sem_arg, 4); |
e0bd6e18 | 216 | |
2ddc0492 DE |
217 | * FLD (f_r1) = ANDSI (* FLD (f_r2), FLD (f_uimm16)); |
218 | TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1)); | |
e0bd6e18 | 219 | |
2ddc0492 DE |
220 | #undef FLD |
221 | } | |
222 | BREAK (sem); | |
223 | ||
224 | CASE (sem, INSN_OR) : /* or $dr,$sr */ | |
225 | { | |
970a8fd6 | 226 | #define FLD(f) abuf->fields.fmt_add.f |
02310b01 | 227 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 228 | |
2ddc0492 DE |
229 | * FLD (f_r1) = ORSI (* FLD (f_r1), * FLD (f_r2)); |
230 | TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1)); | |
e0bd6e18 | 231 | |
2ddc0492 DE |
232 | #undef FLD |
233 | } | |
234 | BREAK (sem); | |
235 | ||
970a8fd6 | 236 | CASE (sem, INSN_OR3) : /* or3 $dr,$sr,$hash$ulo16 */ |
2ddc0492 | 237 | { |
970a8fd6 | 238 | #define FLD(f) abuf->fields.fmt_or3.f |
02310b01 | 239 | new_pc = SEM_NEXT_PC (sem_arg, 4); |
e0bd6e18 | 240 | |
2ddc0492 DE |
241 | * FLD (f_r1) = ORSI (* FLD (f_r2), FLD (f_uimm16)); |
242 | TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1)); | |
e0bd6e18 | 243 | |
2ddc0492 DE |
244 | #undef FLD |
245 | } | |
246 | BREAK (sem); | |
247 | ||
248 | CASE (sem, INSN_XOR) : /* xor $dr,$sr */ | |
249 | { | |
970a8fd6 | 250 | #define FLD(f) abuf->fields.fmt_add.f |
02310b01 | 251 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 252 | |
2ddc0492 DE |
253 | * FLD (f_r1) = XORSI (* FLD (f_r1), * FLD (f_r2)); |
254 | TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1)); | |
e0bd6e18 | 255 | |
2ddc0492 DE |
256 | #undef FLD |
257 | } | |
258 | BREAK (sem); | |
259 | ||
970a8fd6 | 260 | CASE (sem, INSN_XOR3) : /* xor3 $dr,$sr,$uimm16 */ |
2ddc0492 | 261 | { |
970a8fd6 | 262 | #define FLD(f) abuf->fields.fmt_and3.f |
02310b01 | 263 | new_pc = SEM_NEXT_PC (sem_arg, 4); |
e0bd6e18 | 264 | |
2ddc0492 DE |
265 | * FLD (f_r1) = XORSI (* FLD (f_r2), FLD (f_uimm16)); |
266 | TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1)); | |
e0bd6e18 | 267 | |
2ddc0492 DE |
268 | #undef FLD |
269 | } | |
270 | BREAK (sem); | |
271 | ||
970a8fd6 | 272 | CASE (sem, INSN_ADDI) : /* addi $dr,$simm8 */ |
2ddc0492 | 273 | { |
970a8fd6 | 274 | #define FLD(f) abuf->fields.fmt_addi.f |
02310b01 | 275 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 276 | |
2ddc0492 DE |
277 | * FLD (f_r1) = ADDSI (* FLD (f_r1), FLD (f_simm8)); |
278 | TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1)); | |
e0bd6e18 | 279 | |
2ddc0492 DE |
280 | #undef FLD |
281 | } | |
282 | BREAK (sem); | |
283 | ||
284 | CASE (sem, INSN_ADDV) : /* addv $dr,$sr */ | |
285 | { | |
970a8fd6 | 286 | #define FLD(f) abuf->fields.fmt_addv.f |
02310b01 | 287 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 288 | |
2ddc0492 | 289 | do { |
a040908c | 290 | UBI temp1;SI temp0; |
2ddc0492 DE |
291 | temp0 = ADDSI (* FLD (f_r1), * FLD (f_r2)); |
292 | temp1 = ADDOFSI (* FLD (f_r1), * FLD (f_r2), 0); | |
293 | * FLD (f_r1) = temp0; | |
294 | TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1)); | |
295 | CPU (h_cond) = temp1; | |
296 | TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond)); | |
297 | } while (0); | |
e0bd6e18 | 298 | |
2ddc0492 DE |
299 | #undef FLD |
300 | } | |
301 | BREAK (sem); | |
302 | ||
970a8fd6 | 303 | CASE (sem, INSN_ADDV3) : /* addv3 $dr,$sr,$simm16 */ |
2ddc0492 | 304 | { |
970a8fd6 | 305 | #define FLD(f) abuf->fields.fmt_addv3.f |
02310b01 | 306 | new_pc = SEM_NEXT_PC (sem_arg, 4); |
e0bd6e18 | 307 | |
2ddc0492 | 308 | do { |
a040908c | 309 | UBI temp1;SI temp0; |
2ddc0492 DE |
310 | temp0 = ADDSI (* FLD (f_r2), FLD (f_simm16)); |
311 | temp1 = ADDOFSI (* FLD (f_r2), FLD (f_simm16), 0); | |
312 | * FLD (f_r1) = temp0; | |
313 | TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1)); | |
314 | CPU (h_cond) = temp1; | |
315 | TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond)); | |
316 | } while (0); | |
e0bd6e18 | 317 | |
2ddc0492 DE |
318 | #undef FLD |
319 | } | |
320 | BREAK (sem); | |
321 | ||
322 | CASE (sem, INSN_ADDX) : /* addx $dr,$sr */ | |
323 | { | |
970a8fd6 | 324 | #define FLD(f) abuf->fields.fmt_addx.f |
02310b01 | 325 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 326 | |
2ddc0492 | 327 | do { |
a040908c | 328 | UBI temp1;SI temp0; |
2ddc0492 DE |
329 | temp0 = ADDCSI (* FLD (f_r1), * FLD (f_r2), CPU (h_cond)); |
330 | temp1 = ADDCFSI (* FLD (f_r1), * FLD (f_r2), CPU (h_cond)); | |
331 | * FLD (f_r1) = temp0; | |
332 | TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1)); | |
333 | CPU (h_cond) = temp1; | |
334 | TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond)); | |
335 | } while (0); | |
e0bd6e18 | 336 | |
2ddc0492 DE |
337 | #undef FLD |
338 | } | |
339 | BREAK (sem); | |
340 | ||
a8981d67 | 341 | CASE (sem, INSN_BC8) : /* bc.s $disp8 */ |
2ddc0492 | 342 | { |
970a8fd6 | 343 | #define FLD(f) abuf->fields.fmt_bc8.f |
02310b01 | 344 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 345 | |
2ddc0492 | 346 | if (CPU (h_cond)) { |
02310b01 | 347 | BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp8))); |
a8981d67 | 348 | TRACE_RESULT (current_cpu, "pc", 'x', new_pc); |
2ddc0492 | 349 | } |
e0bd6e18 | 350 | |
2ddc0492 DE |
351 | #undef FLD |
352 | } | |
353 | BREAK (sem); | |
354 | ||
a8981d67 | 355 | CASE (sem, INSN_BC24) : /* bc.l $disp24 */ |
2ddc0492 | 356 | { |
970a8fd6 | 357 | #define FLD(f) abuf->fields.fmt_bc24.f |
02310b01 | 358 | new_pc = SEM_NEXT_PC (sem_arg, 4); |
e0bd6e18 | 359 | |
2ddc0492 | 360 | if (CPU (h_cond)) { |
02310b01 | 361 | BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp24))); |
a8981d67 | 362 | TRACE_RESULT (current_cpu, "pc", 'x', new_pc); |
2ddc0492 | 363 | } |
e0bd6e18 | 364 | |
2ddc0492 DE |
365 | #undef FLD |
366 | } | |
367 | BREAK (sem); | |
368 | ||
369 | CASE (sem, INSN_BEQ) : /* beq $src1,$src2,$disp16 */ | |
370 | { | |
970a8fd6 | 371 | #define FLD(f) abuf->fields.fmt_beq.f |
02310b01 | 372 | new_pc = SEM_NEXT_PC (sem_arg, 4); |
e0bd6e18 | 373 | |
2ddc0492 | 374 | if (EQSI (* FLD (f_r1), * FLD (f_r2))) { |
02310b01 | 375 | BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16))); |
a8981d67 | 376 | TRACE_RESULT (current_cpu, "pc", 'x', new_pc); |
2ddc0492 | 377 | } |
e0bd6e18 | 378 | |
2ddc0492 DE |
379 | #undef FLD |
380 | } | |
381 | BREAK (sem); | |
382 | ||
383 | CASE (sem, INSN_BEQZ) : /* beqz $src2,$disp16 */ | |
384 | { | |
970a8fd6 | 385 | #define FLD(f) abuf->fields.fmt_beqz.f |
02310b01 | 386 | new_pc = SEM_NEXT_PC (sem_arg, 4); |
e0bd6e18 | 387 | |
2ddc0492 | 388 | if (EQSI (* FLD (f_r2), 0)) { |
02310b01 | 389 | BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16))); |
a8981d67 | 390 | TRACE_RESULT (current_cpu, "pc", 'x', new_pc); |
2ddc0492 | 391 | } |
e0bd6e18 | 392 | |
2ddc0492 DE |
393 | #undef FLD |
394 | } | |
395 | BREAK (sem); | |
396 | ||
397 | CASE (sem, INSN_BGEZ) : /* bgez $src2,$disp16 */ | |
398 | { | |
970a8fd6 | 399 | #define FLD(f) abuf->fields.fmt_beqz.f |
02310b01 | 400 | new_pc = SEM_NEXT_PC (sem_arg, 4); |
e0bd6e18 | 401 | |
2ddc0492 | 402 | if (GESI (* FLD (f_r2), 0)) { |
02310b01 | 403 | BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16))); |
a8981d67 | 404 | TRACE_RESULT (current_cpu, "pc", 'x', new_pc); |
2ddc0492 | 405 | } |
e0bd6e18 | 406 | |
2ddc0492 DE |
407 | #undef FLD |
408 | } | |
409 | BREAK (sem); | |
410 | ||
411 | CASE (sem, INSN_BGTZ) : /* bgtz $src2,$disp16 */ | |
412 | { | |
970a8fd6 | 413 | #define FLD(f) abuf->fields.fmt_beqz.f |
02310b01 | 414 | new_pc = SEM_NEXT_PC (sem_arg, 4); |
e0bd6e18 | 415 | |
2ddc0492 | 416 | if (GTSI (* FLD (f_r2), 0)) { |
02310b01 | 417 | BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16))); |
a8981d67 | 418 | TRACE_RESULT (current_cpu, "pc", 'x', new_pc); |
2ddc0492 | 419 | } |
e0bd6e18 | 420 | |
2ddc0492 DE |
421 | #undef FLD |
422 | } | |
423 | BREAK (sem); | |
424 | ||
425 | CASE (sem, INSN_BLEZ) : /* blez $src2,$disp16 */ | |
426 | { | |
970a8fd6 | 427 | #define FLD(f) abuf->fields.fmt_beqz.f |
02310b01 | 428 | new_pc = SEM_NEXT_PC (sem_arg, 4); |
e0bd6e18 | 429 | |
2ddc0492 | 430 | if (LESI (* FLD (f_r2), 0)) { |
02310b01 | 431 | BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16))); |
a8981d67 | 432 | TRACE_RESULT (current_cpu, "pc", 'x', new_pc); |
2ddc0492 | 433 | } |
e0bd6e18 | 434 | |
2ddc0492 DE |
435 | #undef FLD |
436 | } | |
437 | BREAK (sem); | |
438 | ||
439 | CASE (sem, INSN_BLTZ) : /* bltz $src2,$disp16 */ | |
440 | { | |
970a8fd6 | 441 | #define FLD(f) abuf->fields.fmt_beqz.f |
02310b01 | 442 | new_pc = SEM_NEXT_PC (sem_arg, 4); |
e0bd6e18 | 443 | |
2ddc0492 | 444 | if (LTSI (* FLD (f_r2), 0)) { |
02310b01 | 445 | BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16))); |
a8981d67 | 446 | TRACE_RESULT (current_cpu, "pc", 'x', new_pc); |
2ddc0492 | 447 | } |
e0bd6e18 | 448 | |
2ddc0492 DE |
449 | #undef FLD |
450 | } | |
451 | BREAK (sem); | |
452 | ||
453 | CASE (sem, INSN_BNEZ) : /* bnez $src2,$disp16 */ | |
454 | { | |
970a8fd6 | 455 | #define FLD(f) abuf->fields.fmt_beqz.f |
02310b01 | 456 | new_pc = SEM_NEXT_PC (sem_arg, 4); |
e0bd6e18 | 457 | |
2ddc0492 | 458 | if (NESI (* FLD (f_r2), 0)) { |
02310b01 | 459 | BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16))); |
a8981d67 | 460 | TRACE_RESULT (current_cpu, "pc", 'x', new_pc); |
2ddc0492 | 461 | } |
e0bd6e18 | 462 | |
2ddc0492 DE |
463 | #undef FLD |
464 | } | |
465 | BREAK (sem); | |
466 | ||
a8981d67 | 467 | CASE (sem, INSN_BL8) : /* bl.s $disp8 */ |
2ddc0492 | 468 | { |
970a8fd6 | 469 | #define FLD(f) abuf->fields.fmt_bl8.f |
02310b01 | 470 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 471 | |
2ddc0492 DE |
472 | do { |
473 | CPU (h_gr[14]) = ADDSI (ANDSI (CPU (h_pc), -4), 4); | |
a8981d67 | 474 | TRACE_RESULT (current_cpu, "gr-14", 'x', CPU (h_gr[14])); |
02310b01 | 475 | BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp8))); |
a8981d67 | 476 | TRACE_RESULT (current_cpu, "pc", 'x', new_pc); |
2ddc0492 | 477 | } while (0); |
e0bd6e18 | 478 | |
2ddc0492 DE |
479 | #undef FLD |
480 | } | |
481 | BREAK (sem); | |
482 | ||
a8981d67 | 483 | CASE (sem, INSN_BL24) : /* bl.l $disp24 */ |
2ddc0492 | 484 | { |
970a8fd6 | 485 | #define FLD(f) abuf->fields.fmt_bl24.f |
02310b01 | 486 | new_pc = SEM_NEXT_PC (sem_arg, 4); |
e0bd6e18 | 487 | |
2ddc0492 DE |
488 | do { |
489 | CPU (h_gr[14]) = ADDSI (CPU (h_pc), 4); | |
a8981d67 | 490 | TRACE_RESULT (current_cpu, "gr-14", 'x', CPU (h_gr[14])); |
02310b01 | 491 | BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp24))); |
a8981d67 | 492 | TRACE_RESULT (current_cpu, "pc", 'x', new_pc); |
2ddc0492 | 493 | } while (0); |
e0bd6e18 | 494 | |
2ddc0492 DE |
495 | #undef FLD |
496 | } | |
497 | BREAK (sem); | |
498 | ||
a8981d67 | 499 | CASE (sem, INSN_BNC8) : /* bnc.s $disp8 */ |
2ddc0492 | 500 | { |
970a8fd6 | 501 | #define FLD(f) abuf->fields.fmt_bc8.f |
02310b01 | 502 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 503 | |
2ddc0492 | 504 | if (NOTBI (CPU (h_cond))) { |
02310b01 | 505 | BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp8))); |
a8981d67 | 506 | TRACE_RESULT (current_cpu, "pc", 'x', new_pc); |
2ddc0492 | 507 | } |
e0bd6e18 | 508 | |
2ddc0492 DE |
509 | #undef FLD |
510 | } | |
511 | BREAK (sem); | |
512 | ||
a8981d67 | 513 | CASE (sem, INSN_BNC24) : /* bnc.l $disp24 */ |
2ddc0492 | 514 | { |
970a8fd6 | 515 | #define FLD(f) abuf->fields.fmt_bc24.f |
02310b01 | 516 | new_pc = SEM_NEXT_PC (sem_arg, 4); |
e0bd6e18 | 517 | |
2ddc0492 | 518 | if (NOTBI (CPU (h_cond))) { |
02310b01 | 519 | BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp24))); |
a8981d67 | 520 | TRACE_RESULT (current_cpu, "pc", 'x', new_pc); |
2ddc0492 | 521 | } |
e0bd6e18 | 522 | |
2ddc0492 DE |
523 | #undef FLD |
524 | } | |
525 | BREAK (sem); | |
526 | ||
527 | CASE (sem, INSN_BNE) : /* bne $src1,$src2,$disp16 */ | |
528 | { | |
970a8fd6 | 529 | #define FLD(f) abuf->fields.fmt_beq.f |
02310b01 | 530 | new_pc = SEM_NEXT_PC (sem_arg, 4); |
e0bd6e18 | 531 | |
2ddc0492 | 532 | if (NESI (* FLD (f_r1), * FLD (f_r2))) { |
02310b01 | 533 | BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16))); |
a8981d67 | 534 | TRACE_RESULT (current_cpu, "pc", 'x', new_pc); |
2ddc0492 | 535 | } |
e0bd6e18 | 536 | |
2ddc0492 DE |
537 | #undef FLD |
538 | } | |
539 | BREAK (sem); | |
540 | ||
a8981d67 | 541 | CASE (sem, INSN_BRA8) : /* bra.s $disp8 */ |
2ddc0492 | 542 | { |
970a8fd6 | 543 | #define FLD(f) abuf->fields.fmt_bra8.f |
02310b01 | 544 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 545 | |
02310b01 | 546 | BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp8))); |
a8981d67 | 547 | TRACE_RESULT (current_cpu, "pc", 'x', new_pc); |
e0bd6e18 | 548 | |
2ddc0492 DE |
549 | #undef FLD |
550 | } | |
551 | BREAK (sem); | |
552 | ||
a8981d67 | 553 | CASE (sem, INSN_BRA24) : /* bra.l $disp24 */ |
2ddc0492 | 554 | { |
970a8fd6 | 555 | #define FLD(f) abuf->fields.fmt_bra24.f |
02310b01 | 556 | new_pc = SEM_NEXT_PC (sem_arg, 4); |
e0bd6e18 | 557 | |
02310b01 | 558 | BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp24))); |
a8981d67 | 559 | TRACE_RESULT (current_cpu, "pc", 'x', new_pc); |
e0bd6e18 | 560 | |
2ddc0492 DE |
561 | #undef FLD |
562 | } | |
563 | BREAK (sem); | |
564 | ||
565 | CASE (sem, INSN_CMP) : /* cmp $src1,$src2 */ | |
566 | { | |
970a8fd6 | 567 | #define FLD(f) abuf->fields.fmt_cmp.f |
02310b01 | 568 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 569 | |
2ddc0492 DE |
570 | CPU (h_cond) = LTSI (* FLD (f_r1), * FLD (f_r2)); |
571 | TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond)); | |
e0bd6e18 | 572 | |
2ddc0492 DE |
573 | #undef FLD |
574 | } | |
575 | BREAK (sem); | |
576 | ||
970a8fd6 | 577 | CASE (sem, INSN_CMPI) : /* cmpi $src2,$simm16 */ |
2ddc0492 | 578 | { |
970a8fd6 | 579 | #define FLD(f) abuf->fields.fmt_cmpi.f |
02310b01 | 580 | new_pc = SEM_NEXT_PC (sem_arg, 4); |
e0bd6e18 | 581 | |
2ddc0492 DE |
582 | CPU (h_cond) = LTSI (* FLD (f_r2), FLD (f_simm16)); |
583 | TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond)); | |
e0bd6e18 | 584 | |
2ddc0492 DE |
585 | #undef FLD |
586 | } | |
587 | BREAK (sem); | |
588 | ||
589 | CASE (sem, INSN_CMPU) : /* cmpu $src1,$src2 */ | |
590 | { | |
970a8fd6 | 591 | #define FLD(f) abuf->fields.fmt_cmp.f |
02310b01 | 592 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 593 | |
2ddc0492 DE |
594 | CPU (h_cond) = LTUSI (* FLD (f_r1), * FLD (f_r2)); |
595 | TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond)); | |
e0bd6e18 | 596 | |
2ddc0492 DE |
597 | #undef FLD |
598 | } | |
599 | BREAK (sem); | |
600 | ||
970a8fd6 | 601 | CASE (sem, INSN_CMPUI) : /* cmpui $src2,$simm16 */ |
2ddc0492 | 602 | { |
970a8fd6 | 603 | #define FLD(f) abuf->fields.fmt_cmpi.f |
02310b01 | 604 | new_pc = SEM_NEXT_PC (sem_arg, 4); |
e0bd6e18 | 605 | |
970a8fd6 | 606 | CPU (h_cond) = LTUSI (* FLD (f_r2), FLD (f_simm16)); |
2ddc0492 | 607 | TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond)); |
e0bd6e18 | 608 | |
2ddc0492 DE |
609 | #undef FLD |
610 | } | |
611 | BREAK (sem); | |
612 | ||
613 | CASE (sem, INSN_DIV) : /* div $dr,$sr */ | |
614 | { | |
970a8fd6 | 615 | #define FLD(f) abuf->fields.fmt_div.f |
02310b01 | 616 | new_pc = SEM_NEXT_PC (sem_arg, 4); |
e0bd6e18 | 617 | |
2ddc0492 DE |
618 | if (NESI (* FLD (f_r2), 0)) { |
619 | * FLD (f_r1) = DIVSI (* FLD (f_r1), * FLD (f_r2)); | |
620 | TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1)); | |
621 | } | |
e0bd6e18 | 622 | |
2ddc0492 DE |
623 | #undef FLD |
624 | } | |
625 | BREAK (sem); | |
626 | ||
627 | CASE (sem, INSN_DIVU) : /* divu $dr,$sr */ | |
628 | { | |
970a8fd6 | 629 | #define FLD(f) abuf->fields.fmt_div.f |
02310b01 | 630 | new_pc = SEM_NEXT_PC (sem_arg, 4); |
e0bd6e18 | 631 | |
2ddc0492 DE |
632 | if (NESI (* FLD (f_r2), 0)) { |
633 | * FLD (f_r1) = UDIVSI (* FLD (f_r1), * FLD (f_r2)); | |
634 | TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1)); | |
635 | } | |
e0bd6e18 | 636 | |
2ddc0492 DE |
637 | #undef FLD |
638 | } | |
639 | BREAK (sem); | |
640 | ||
641 | CASE (sem, INSN_REM) : /* rem $dr,$sr */ | |
642 | { | |
970a8fd6 | 643 | #define FLD(f) abuf->fields.fmt_div.f |
02310b01 | 644 | new_pc = SEM_NEXT_PC (sem_arg, 4); |
e0bd6e18 | 645 | |
2ddc0492 DE |
646 | if (NESI (* FLD (f_r2), 0)) { |
647 | * FLD (f_r1) = MODSI (* FLD (f_r1), * FLD (f_r2)); | |
648 | TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1)); | |
649 | } | |
e0bd6e18 | 650 | |
2ddc0492 DE |
651 | #undef FLD |
652 | } | |
653 | BREAK (sem); | |
654 | ||
655 | CASE (sem, INSN_REMU) : /* remu $dr,$sr */ | |
656 | { | |
970a8fd6 | 657 | #define FLD(f) abuf->fields.fmt_div.f |
02310b01 | 658 | new_pc = SEM_NEXT_PC (sem_arg, 4); |
e0bd6e18 | 659 | |
2ddc0492 DE |
660 | if (NESI (* FLD (f_r2), 0)) { |
661 | * FLD (f_r1) = UMODSI (* FLD (f_r1), * FLD (f_r2)); | |
662 | TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1)); | |
663 | } | |
e0bd6e18 | 664 | |
2ddc0492 DE |
665 | #undef FLD |
666 | } | |
667 | BREAK (sem); | |
668 | ||
669 | CASE (sem, INSN_JL) : /* jl $sr */ | |
670 | { | |
970a8fd6 | 671 | #define FLD(f) abuf->fields.fmt_jl.f |
02310b01 | 672 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 673 | |
2ddc0492 | 674 | do { |
a040908c | 675 | USI temp1;SI temp0; |
2ddc0492 | 676 | temp0 = ADDSI (ANDSI (CPU (h_pc), -4), 4); |
a040908c | 677 | temp1 = ANDSI (* FLD (f_r2), -4); |
2ddc0492 | 678 | CPU (h_gr[14]) = temp0; |
a8981d67 | 679 | TRACE_RESULT (current_cpu, "gr-14", 'x', CPU (h_gr[14])); |
02310b01 | 680 | BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, temp1)); |
a8981d67 | 681 | TRACE_RESULT (current_cpu, "pc", 'x', new_pc); |
2ddc0492 | 682 | } while (0); |
e0bd6e18 | 683 | |
2ddc0492 DE |
684 | #undef FLD |
685 | } | |
686 | BREAK (sem); | |
687 | ||
688 | CASE (sem, INSN_JMP) : /* jmp $sr */ | |
689 | { | |
970a8fd6 | 690 | #define FLD(f) abuf->fields.fmt_jmp.f |
02310b01 | 691 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 692 | |
a040908c | 693 | BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, ANDSI (* FLD (f_r2), -4))); |
a8981d67 | 694 | TRACE_RESULT (current_cpu, "pc", 'x', new_pc); |
e0bd6e18 | 695 | |
2ddc0492 DE |
696 | #undef FLD |
697 | } | |
698 | BREAK (sem); | |
699 | ||
700 | CASE (sem, INSN_LD) : /* ld $dr,@$sr */ | |
701 | { | |
970a8fd6 | 702 | #define FLD(f) abuf->fields.fmt_ld.f |
02310b01 | 703 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 704 | |
2ddc0492 DE |
705 | * FLD (f_r1) = GETMEMSI (current_cpu, * FLD (f_r2)); |
706 | TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1)); | |
e0bd6e18 | 707 | |
2ddc0492 DE |
708 | #undef FLD |
709 | } | |
710 | BREAK (sem); | |
711 | ||
712 | CASE (sem, INSN_LD_D) : /* ld $dr,@($slo16,$sr) */ | |
713 | { | |
970a8fd6 | 714 | #define FLD(f) abuf->fields.fmt_ld_d.f |
02310b01 | 715 | new_pc = SEM_NEXT_PC (sem_arg, 4); |
e0bd6e18 | 716 | |
2ddc0492 DE |
717 | * FLD (f_r1) = GETMEMSI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))); |
718 | TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1)); | |
e0bd6e18 | 719 | |
2ddc0492 DE |
720 | #undef FLD |
721 | } | |
722 | BREAK (sem); | |
723 | ||
724 | CASE (sem, INSN_LDB) : /* ldb $dr,@$sr */ | |
725 | { | |
970a8fd6 | 726 | #define FLD(f) abuf->fields.fmt_ldb.f |
02310b01 | 727 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 728 | |
2ddc0492 DE |
729 | * FLD (f_r1) = EXTQISI (GETMEMQI (current_cpu, * FLD (f_r2))); |
730 | TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1)); | |
e0bd6e18 | 731 | |
2ddc0492 DE |
732 | #undef FLD |
733 | } | |
734 | BREAK (sem); | |
735 | ||
736 | CASE (sem, INSN_LDB_D) : /* ldb $dr,@($slo16,$sr) */ | |
737 | { | |
970a8fd6 | 738 | #define FLD(f) abuf->fields.fmt_ldb_d.f |
02310b01 | 739 | new_pc = SEM_NEXT_PC (sem_arg, 4); |
e0bd6e18 | 740 | |
2ddc0492 DE |
741 | * FLD (f_r1) = EXTQISI (GETMEMQI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)))); |
742 | TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1)); | |
e0bd6e18 | 743 | |
2ddc0492 DE |
744 | #undef FLD |
745 | } | |
746 | BREAK (sem); | |
747 | ||
748 | CASE (sem, INSN_LDH) : /* ldh $dr,@$sr */ | |
749 | { | |
970a8fd6 | 750 | #define FLD(f) abuf->fields.fmt_ldh.f |
02310b01 | 751 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 752 | |
2ddc0492 DE |
753 | * FLD (f_r1) = EXTHISI (GETMEMHI (current_cpu, * FLD (f_r2))); |
754 | TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1)); | |
e0bd6e18 | 755 | |
2ddc0492 DE |
756 | #undef FLD |
757 | } | |
758 | BREAK (sem); | |
759 | ||
760 | CASE (sem, INSN_LDH_D) : /* ldh $dr,@($slo16,$sr) */ | |
761 | { | |
970a8fd6 | 762 | #define FLD(f) abuf->fields.fmt_ldh_d.f |
02310b01 | 763 | new_pc = SEM_NEXT_PC (sem_arg, 4); |
e0bd6e18 | 764 | |
2ddc0492 DE |
765 | * FLD (f_r1) = EXTHISI (GETMEMHI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)))); |
766 | TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1)); | |
e0bd6e18 | 767 | |
2ddc0492 DE |
768 | #undef FLD |
769 | } | |
770 | BREAK (sem); | |
771 | ||
772 | CASE (sem, INSN_LDUB) : /* ldub $dr,@$sr */ | |
773 | { | |
970a8fd6 | 774 | #define FLD(f) abuf->fields.fmt_ldb.f |
02310b01 | 775 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 776 | |
2ddc0492 DE |
777 | * FLD (f_r1) = ZEXTQISI (GETMEMQI (current_cpu, * FLD (f_r2))); |
778 | TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1)); | |
e0bd6e18 | 779 | |
2ddc0492 DE |
780 | #undef FLD |
781 | } | |
782 | BREAK (sem); | |
783 | ||
784 | CASE (sem, INSN_LDUB_D) : /* ldub $dr,@($slo16,$sr) */ | |
785 | { | |
970a8fd6 | 786 | #define FLD(f) abuf->fields.fmt_ldb_d.f |
02310b01 | 787 | new_pc = SEM_NEXT_PC (sem_arg, 4); |
e0bd6e18 | 788 | |
2ddc0492 DE |
789 | * FLD (f_r1) = ZEXTQISI (GETMEMQI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)))); |
790 | TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1)); | |
e0bd6e18 | 791 | |
2ddc0492 DE |
792 | #undef FLD |
793 | } | |
794 | BREAK (sem); | |
795 | ||
796 | CASE (sem, INSN_LDUH) : /* lduh $dr,@$sr */ | |
797 | { | |
970a8fd6 | 798 | #define FLD(f) abuf->fields.fmt_ldh.f |
02310b01 | 799 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 800 | |
2ddc0492 DE |
801 | * FLD (f_r1) = ZEXTHISI (GETMEMHI (current_cpu, * FLD (f_r2))); |
802 | TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1)); | |
e0bd6e18 | 803 | |
2ddc0492 DE |
804 | #undef FLD |
805 | } | |
806 | BREAK (sem); | |
807 | ||
808 | CASE (sem, INSN_LDUH_D) : /* lduh $dr,@($slo16,$sr) */ | |
809 | { | |
970a8fd6 | 810 | #define FLD(f) abuf->fields.fmt_ldh_d.f |
02310b01 | 811 | new_pc = SEM_NEXT_PC (sem_arg, 4); |
e0bd6e18 | 812 | |
2ddc0492 DE |
813 | * FLD (f_r1) = ZEXTHISI (GETMEMHI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)))); |
814 | TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1)); | |
e0bd6e18 | 815 | |
2ddc0492 DE |
816 | #undef FLD |
817 | } | |
818 | BREAK (sem); | |
819 | ||
820 | CASE (sem, INSN_LD_PLUS) : /* ld $dr,@$sr+ */ | |
821 | { | |
970a8fd6 | 822 | #define FLD(f) abuf->fields.fmt_ld_plus.f |
02310b01 | 823 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 824 | |
2ddc0492 DE |
825 | do { |
826 | SI temp1;SI temp0; | |
827 | temp0 = GETMEMSI (current_cpu, * FLD (f_r2)); | |
828 | temp1 = ADDSI (* FLD (f_r2), 4); | |
829 | * FLD (f_r1) = temp0; | |
830 | TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1)); | |
831 | * FLD (f_r2) = temp1; | |
832 | TRACE_RESULT (current_cpu, "sr", 'x', * FLD (f_r2)); | |
833 | } while (0); | |
e0bd6e18 | 834 | |
2ddc0492 DE |
835 | #undef FLD |
836 | } | |
837 | BREAK (sem); | |
838 | ||
970a8fd6 | 839 | CASE (sem, INSN_LD24) : /* ld24 $dr,$uimm24 */ |
2ddc0492 | 840 | { |
970a8fd6 | 841 | #define FLD(f) abuf->fields.fmt_ld24.f |
02310b01 | 842 | new_pc = SEM_NEXT_PC (sem_arg, 4); |
e0bd6e18 | 843 | |
2ddc0492 DE |
844 | * FLD (f_r1) = FLD (f_uimm24); |
845 | TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1)); | |
e0bd6e18 | 846 | |
2ddc0492 DE |
847 | #undef FLD |
848 | } | |
849 | BREAK (sem); | |
850 | ||
a8981d67 | 851 | CASE (sem, INSN_LDI8) : /* ldi8 $dr,$simm8 */ |
2ddc0492 | 852 | { |
970a8fd6 | 853 | #define FLD(f) abuf->fields.fmt_ldi8.f |
02310b01 | 854 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 855 | |
2ddc0492 DE |
856 | * FLD (f_r1) = FLD (f_simm8); |
857 | TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1)); | |
e0bd6e18 | 858 | |
2ddc0492 DE |
859 | #undef FLD |
860 | } | |
861 | BREAK (sem); | |
862 | ||
a8981d67 | 863 | CASE (sem, INSN_LDI16) : /* ldi16 $dr,$hash$slo16 */ |
2ddc0492 | 864 | { |
970a8fd6 | 865 | #define FLD(f) abuf->fields.fmt_ldi16.f |
02310b01 | 866 | new_pc = SEM_NEXT_PC (sem_arg, 4); |
e0bd6e18 | 867 | |
2ddc0492 DE |
868 | * FLD (f_r1) = FLD (f_simm16); |
869 | TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1)); | |
e0bd6e18 | 870 | |
2ddc0492 DE |
871 | #undef FLD |
872 | } | |
873 | BREAK (sem); | |
874 | ||
875 | CASE (sem, INSN_LOCK) : /* lock $dr,@$sr */ | |
876 | { | |
970a8fd6 | 877 | #define FLD(f) abuf->fields.fmt_lock.f |
02310b01 | 878 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 879 | |
cab58155 DE |
880 | do { |
881 | CPU (h_lock) = 1; | |
a8981d67 | 882 | TRACE_RESULT (current_cpu, "lock-0", 'x', CPU (h_lock)); |
cab58155 DE |
883 | * FLD (f_r1) = GETMEMSI (current_cpu, * FLD (f_r2)); |
884 | TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1)); | |
885 | } while (0); | |
e0bd6e18 | 886 | |
2ddc0492 DE |
887 | #undef FLD |
888 | } | |
889 | BREAK (sem); | |
890 | ||
891 | CASE (sem, INSN_MACHI) : /* machi $src1,$src2 */ | |
892 | { | |
970a8fd6 | 893 | #define FLD(f) abuf->fields.fmt_machi.f |
02310b01 | 894 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 895 | |
970a8fd6 DE |
896 | m32r_h_accum_set (current_cpu, SRADI (SLLDI (ADDDI (m32r_h_accum_get (current_cpu), MULDI (EXTSIDI (ANDSI (* FLD (f_r1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (f_r2), 16))))), 8), 8)); |
897 | TRACE_RESULT (current_cpu, "accum", 'D', m32r_h_accum_get (current_cpu)); | |
e0bd6e18 | 898 | |
2ddc0492 DE |
899 | #undef FLD |
900 | } | |
901 | BREAK (sem); | |
902 | ||
903 | CASE (sem, INSN_MACLO) : /* maclo $src1,$src2 */ | |
904 | { | |
970a8fd6 | 905 | #define FLD(f) abuf->fields.fmt_machi.f |
02310b01 | 906 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 907 | |
970a8fd6 DE |
908 | m32r_h_accum_set (current_cpu, SRADI (SLLDI (ADDDI (m32r_h_accum_get (current_cpu), MULDI (EXTSIDI (SLLSI (* FLD (f_r1), 16)), EXTHIDI (TRUNCSIHI (* FLD (f_r2))))), 8), 8)); |
909 | TRACE_RESULT (current_cpu, "accum", 'D', m32r_h_accum_get (current_cpu)); | |
e0bd6e18 | 910 | |
2ddc0492 DE |
911 | #undef FLD |
912 | } | |
913 | BREAK (sem); | |
914 | ||
915 | CASE (sem, INSN_MACWHI) : /* macwhi $src1,$src2 */ | |
916 | { | |
970a8fd6 | 917 | #define FLD(f) abuf->fields.fmt_machi.f |
02310b01 | 918 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 919 | |
970a8fd6 DE |
920 | m32r_h_accum_set (current_cpu, SRADI (SLLDI (ADDDI (m32r_h_accum_get (current_cpu), MULDI (EXTSIDI (* FLD (f_r1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (f_r2), 16))))), 8), 8)); |
921 | TRACE_RESULT (current_cpu, "accum", 'D', m32r_h_accum_get (current_cpu)); | |
e0bd6e18 | 922 | |
2ddc0492 DE |
923 | #undef FLD |
924 | } | |
925 | BREAK (sem); | |
926 | ||
927 | CASE (sem, INSN_MACWLO) : /* macwlo $src1,$src2 */ | |
928 | { | |
970a8fd6 | 929 | #define FLD(f) abuf->fields.fmt_machi.f |
02310b01 | 930 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 931 | |
970a8fd6 DE |
932 | m32r_h_accum_set (current_cpu, SRADI (SLLDI (ADDDI (m32r_h_accum_get (current_cpu), MULDI (EXTSIDI (* FLD (f_r1)), EXTHIDI (TRUNCSIHI (* FLD (f_r2))))), 8), 8)); |
933 | TRACE_RESULT (current_cpu, "accum", 'D', m32r_h_accum_get (current_cpu)); | |
e0bd6e18 | 934 | |
2ddc0492 DE |
935 | #undef FLD |
936 | } | |
937 | BREAK (sem); | |
938 | ||
939 | CASE (sem, INSN_MUL) : /* mul $dr,$sr */ | |
940 | { | |
970a8fd6 | 941 | #define FLD(f) abuf->fields.fmt_add.f |
02310b01 | 942 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 943 | |
2ddc0492 DE |
944 | * FLD (f_r1) = MULSI (* FLD (f_r1), * FLD (f_r2)); |
945 | TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1)); | |
e0bd6e18 | 946 | |
2ddc0492 DE |
947 | #undef FLD |
948 | } | |
949 | BREAK (sem); | |
950 | ||
951 | CASE (sem, INSN_MULHI) : /* mulhi $src1,$src2 */ | |
952 | { | |
970a8fd6 | 953 | #define FLD(f) abuf->fields.fmt_mulhi.f |
02310b01 | 954 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 955 | |
970a8fd6 DE |
956 | m32r_h_accum_set (current_cpu, SRADI (SLLDI (MULDI (EXTSIDI (ANDSI (* FLD (f_r1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (f_r2), 16)))), 16), 16)); |
957 | TRACE_RESULT (current_cpu, "accum", 'D', m32r_h_accum_get (current_cpu)); | |
e0bd6e18 | 958 | |
2ddc0492 DE |
959 | #undef FLD |
960 | } | |
961 | BREAK (sem); | |
962 | ||
963 | CASE (sem, INSN_MULLO) : /* mullo $src1,$src2 */ | |
964 | { | |
970a8fd6 | 965 | #define FLD(f) abuf->fields.fmt_mulhi.f |
02310b01 | 966 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 967 | |
970a8fd6 DE |
968 | m32r_h_accum_set (current_cpu, SRADI (SLLDI (MULDI (EXTSIDI (SLLSI (* FLD (f_r1), 16)), EXTHIDI (TRUNCSIHI (* FLD (f_r2)))), 16), 16)); |
969 | TRACE_RESULT (current_cpu, "accum", 'D', m32r_h_accum_get (current_cpu)); | |
e0bd6e18 | 970 | |
2ddc0492 DE |
971 | #undef FLD |
972 | } | |
973 | BREAK (sem); | |
974 | ||
975 | CASE (sem, INSN_MULWHI) : /* mulwhi $src1,$src2 */ | |
976 | { | |
970a8fd6 | 977 | #define FLD(f) abuf->fields.fmt_mulhi.f |
02310b01 | 978 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 979 | |
970a8fd6 DE |
980 | m32r_h_accum_set (current_cpu, SRADI (SLLDI (MULDI (EXTSIDI (* FLD (f_r1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (f_r2), 16)))), 8), 8)); |
981 | TRACE_RESULT (current_cpu, "accum", 'D', m32r_h_accum_get (current_cpu)); | |
e0bd6e18 | 982 | |
2ddc0492 DE |
983 | #undef FLD |
984 | } | |
985 | BREAK (sem); | |
986 | ||
987 | CASE (sem, INSN_MULWLO) : /* mulwlo $src1,$src2 */ | |
988 | { | |
970a8fd6 | 989 | #define FLD(f) abuf->fields.fmt_mulhi.f |
02310b01 | 990 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 991 | |
970a8fd6 DE |
992 | m32r_h_accum_set (current_cpu, SRADI (SLLDI (MULDI (EXTSIDI (* FLD (f_r1)), EXTHIDI (TRUNCSIHI (* FLD (f_r2)))), 8), 8)); |
993 | TRACE_RESULT (current_cpu, "accum", 'D', m32r_h_accum_get (current_cpu)); | |
e0bd6e18 | 994 | |
2ddc0492 DE |
995 | #undef FLD |
996 | } | |
997 | BREAK (sem); | |
998 | ||
999 | CASE (sem, INSN_MV) : /* mv $dr,$sr */ | |
1000 | { | |
970a8fd6 | 1001 | #define FLD(f) abuf->fields.fmt_mv.f |
02310b01 | 1002 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 1003 | |
2ddc0492 DE |
1004 | * FLD (f_r1) = * FLD (f_r2); |
1005 | TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1)); | |
e0bd6e18 | 1006 | |
2ddc0492 DE |
1007 | #undef FLD |
1008 | } | |
1009 | BREAK (sem); | |
1010 | ||
1011 | CASE (sem, INSN_MVFACHI) : /* mvfachi $dr */ | |
1012 | { | |
970a8fd6 | 1013 | #define FLD(f) abuf->fields.fmt_mvfachi.f |
02310b01 | 1014 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 1015 | |
970a8fd6 | 1016 | * FLD (f_r1) = TRUNCDISI (SRADI (m32r_h_accum_get (current_cpu), 32)); |
2ddc0492 | 1017 | TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1)); |
e0bd6e18 | 1018 | |
2ddc0492 DE |
1019 | #undef FLD |
1020 | } | |
1021 | BREAK (sem); | |
1022 | ||
1023 | CASE (sem, INSN_MVFACLO) : /* mvfaclo $dr */ | |
1024 | { | |
970a8fd6 | 1025 | #define FLD(f) abuf->fields.fmt_mvfachi.f |
02310b01 | 1026 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 1027 | |
970a8fd6 | 1028 | * FLD (f_r1) = TRUNCDISI (m32r_h_accum_get (current_cpu)); |
2ddc0492 | 1029 | TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1)); |
e0bd6e18 | 1030 | |
2ddc0492 DE |
1031 | #undef FLD |
1032 | } | |
1033 | BREAK (sem); | |
1034 | ||
1035 | CASE (sem, INSN_MVFACMI) : /* mvfacmi $dr */ | |
1036 | { | |
970a8fd6 | 1037 | #define FLD(f) abuf->fields.fmt_mvfachi.f |
02310b01 | 1038 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 1039 | |
970a8fd6 | 1040 | * FLD (f_r1) = TRUNCDISI (SRADI (m32r_h_accum_get (current_cpu), 16)); |
2ddc0492 | 1041 | TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1)); |
e0bd6e18 | 1042 | |
2ddc0492 DE |
1043 | #undef FLD |
1044 | } | |
1045 | BREAK (sem); | |
1046 | ||
1047 | CASE (sem, INSN_MVFC) : /* mvfc $dr,$scr */ | |
1048 | { | |
970a8fd6 | 1049 | #define FLD(f) abuf->fields.fmt_mvfc.f |
02310b01 | 1050 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 1051 | |
2ddc0492 DE |
1052 | * FLD (f_r1) = m32r_h_cr_get (current_cpu, FLD (f_r2)); |
1053 | TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1)); | |
e0bd6e18 | 1054 | |
2ddc0492 DE |
1055 | #undef FLD |
1056 | } | |
1057 | BREAK (sem); | |
1058 | ||
1059 | CASE (sem, INSN_MVTACHI) : /* mvtachi $src1 */ | |
1060 | { | |
970a8fd6 | 1061 | #define FLD(f) abuf->fields.fmt_mvtachi.f |
02310b01 | 1062 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 1063 | |
970a8fd6 DE |
1064 | m32r_h_accum_set (current_cpu, ORDI (ANDDI (m32r_h_accum_get (current_cpu), MAKEDI (0, 0xffffffff)), SLLDI (EXTSIDI (* FLD (f_r1)), 32))); |
1065 | TRACE_RESULT (current_cpu, "accum", 'D', m32r_h_accum_get (current_cpu)); | |
e0bd6e18 | 1066 | |
2ddc0492 DE |
1067 | #undef FLD |
1068 | } | |
1069 | BREAK (sem); | |
1070 | ||
1071 | CASE (sem, INSN_MVTACLO) : /* mvtaclo $src1 */ | |
1072 | { | |
970a8fd6 | 1073 | #define FLD(f) abuf->fields.fmt_mvtachi.f |
02310b01 | 1074 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 1075 | |
970a8fd6 DE |
1076 | m32r_h_accum_set (current_cpu, ORDI (ANDDI (m32r_h_accum_get (current_cpu), MAKEDI (0xffffffff, 0)), ZEXTSIDI (* FLD (f_r1)))); |
1077 | TRACE_RESULT (current_cpu, "accum", 'D', m32r_h_accum_get (current_cpu)); | |
e0bd6e18 | 1078 | |
2ddc0492 DE |
1079 | #undef FLD |
1080 | } | |
1081 | BREAK (sem); | |
1082 | ||
1083 | CASE (sem, INSN_MVTC) : /* mvtc $sr,$dcr */ | |
1084 | { | |
970a8fd6 | 1085 | #define FLD(f) abuf->fields.fmt_mvtc.f |
02310b01 | 1086 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 1087 | |
2ddc0492 DE |
1088 | m32r_h_cr_set (current_cpu, FLD (f_r1), * FLD (f_r2)); |
1089 | TRACE_RESULT (current_cpu, "dcr", 'x', m32r_h_cr_get (current_cpu, FLD (f_r1))); | |
e0bd6e18 | 1090 | |
2ddc0492 DE |
1091 | #undef FLD |
1092 | } | |
1093 | BREAK (sem); | |
1094 | ||
1095 | CASE (sem, INSN_NEG) : /* neg $dr,$sr */ | |
1096 | { | |
970a8fd6 | 1097 | #define FLD(f) abuf->fields.fmt_mv.f |
02310b01 | 1098 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 1099 | |
2ddc0492 DE |
1100 | * FLD (f_r1) = NEGSI (* FLD (f_r2)); |
1101 | TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1)); | |
e0bd6e18 | 1102 | |
2ddc0492 DE |
1103 | #undef FLD |
1104 | } | |
1105 | BREAK (sem); | |
1106 | ||
1107 | CASE (sem, INSN_NOP) : /* nop */ | |
1108 | { | |
970a8fd6 | 1109 | #define FLD(f) abuf->fields.fmt_nop.f |
02310b01 | 1110 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 1111 | |
2ddc0492 | 1112 | PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr); |
e0bd6e18 | 1113 | |
2ddc0492 DE |
1114 | #undef FLD |
1115 | } | |
1116 | BREAK (sem); | |
1117 | ||
1118 | CASE (sem, INSN_NOT) : /* not $dr,$sr */ | |
1119 | { | |
970a8fd6 | 1120 | #define FLD(f) abuf->fields.fmt_mv.f |
02310b01 | 1121 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 1122 | |
2ddc0492 DE |
1123 | * FLD (f_r1) = INVSI (* FLD (f_r2)); |
1124 | TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1)); | |
e0bd6e18 | 1125 | |
2ddc0492 DE |
1126 | #undef FLD |
1127 | } | |
1128 | BREAK (sem); | |
1129 | ||
1130 | CASE (sem, INSN_RAC) : /* rac */ | |
1131 | { | |
970a8fd6 | 1132 | #define FLD(f) abuf->fields.fmt_rac.f |
02310b01 | 1133 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 1134 | |
2ddc0492 DE |
1135 | do { |
1136 | DI tmp_tmp1; | |
970a8fd6 | 1137 | tmp_tmp1 = SLLDI (m32r_h_accum_get (current_cpu), 1); |
e0bd6e18 | 1138 | tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 32768)); |
970a8fd6 DE |
1139 | m32r_h_accum_set (current_cpu, (GTDI (tmp_tmp1, MAKEDI (32767, 0xffff0000))) ? (MAKEDI (32767, 0xffff0000)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0xffff0000)))); |
1140 | TRACE_RESULT (current_cpu, "accum", 'D', m32r_h_accum_get (current_cpu)); | |
2ddc0492 | 1141 | } while (0); |
e0bd6e18 | 1142 | |
2ddc0492 DE |
1143 | #undef FLD |
1144 | } | |
1145 | BREAK (sem); | |
1146 | ||
1147 | CASE (sem, INSN_RACH) : /* rach */ | |
1148 | { | |
970a8fd6 | 1149 | #define FLD(f) abuf->fields.fmt_rac.f |
02310b01 | 1150 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 1151 | |
2ddc0492 DE |
1152 | do { |
1153 | DI tmp_tmp1; | |
970a8fd6 | 1154 | tmp_tmp1 = ANDDI (m32r_h_accum_get (current_cpu), MAKEDI (16777215, 0xffffffff)); |
a040908c | 1155 | if (ANDIF (GEDI (tmp_tmp1, MAKEDI (16383, 0x80000000)), LEDI (tmp_tmp1, MAKEDI (8388607, 0xffffffff)))) { |
2ddc0492 DE |
1156 | tmp_tmp1 = MAKEDI (16383, 0x80000000); |
1157 | } else { | |
a040908c | 1158 | if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (16760832, 0)))) { |
2ddc0492 DE |
1159 | tmp_tmp1 = MAKEDI (16760832, 0); |
1160 | } else { | |
970a8fd6 | 1161 | tmp_tmp1 = ANDDI (ADDDI (m32r_h_accum_get (current_cpu), MAKEDI (0, 1073741824)), MAKEDI (0xffffffff, 0x80000000)); |
2ddc0492 DE |
1162 | } |
1163 | } | |
1164 | tmp_tmp1 = SLLDI (tmp_tmp1, 1); | |
970a8fd6 DE |
1165 | m32r_h_accum_set (current_cpu, SRADI (SLLDI (tmp_tmp1, 7), 7)); |
1166 | TRACE_RESULT (current_cpu, "accum", 'D', m32r_h_accum_get (current_cpu)); | |
2ddc0492 | 1167 | } while (0); |
e0bd6e18 | 1168 | |
2ddc0492 DE |
1169 | #undef FLD |
1170 | } | |
1171 | BREAK (sem); | |
1172 | ||
1173 | CASE (sem, INSN_RTE) : /* rte */ | |
1174 | { | |
970a8fd6 | 1175 | #define FLD(f) abuf->fields.fmt_rte.f |
02310b01 | 1176 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 1177 | |
2ddc0492 DE |
1178 | do { |
1179 | CPU (h_sm) = CPU (h_bsm); | |
a8981d67 | 1180 | TRACE_RESULT (current_cpu, "sm-0", 'x', CPU (h_sm)); |
2ddc0492 | 1181 | CPU (h_ie) = CPU (h_bie); |
a8981d67 | 1182 | TRACE_RESULT (current_cpu, "ie-0", 'x', CPU (h_ie)); |
2ddc0492 DE |
1183 | CPU (h_cond) = CPU (h_bcond); |
1184 | TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond)); | |
970a8fd6 | 1185 | BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, ANDSI (CPU (h_bpc), -4))); |
a8981d67 | 1186 | TRACE_RESULT (current_cpu, "pc", 'x', new_pc); |
2ddc0492 | 1187 | } while (0); |
e0bd6e18 | 1188 | |
2ddc0492 DE |
1189 | #undef FLD |
1190 | } | |
1191 | BREAK (sem); | |
1192 | ||
970a8fd6 | 1193 | CASE (sem, INSN_SETH) : /* seth $dr,$hash$hi16 */ |
2ddc0492 | 1194 | { |
970a8fd6 | 1195 | #define FLD(f) abuf->fields.fmt_seth.f |
02310b01 | 1196 | new_pc = SEM_NEXT_PC (sem_arg, 4); |
e0bd6e18 | 1197 | |
2ddc0492 DE |
1198 | * FLD (f_r1) = SLLSI (FLD (f_hi16), 16); |
1199 | TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1)); | |
e0bd6e18 | 1200 | |
2ddc0492 DE |
1201 | #undef FLD |
1202 | } | |
1203 | BREAK (sem); | |
1204 | ||
1205 | CASE (sem, INSN_SLL) : /* sll $dr,$sr */ | |
1206 | { | |
970a8fd6 | 1207 | #define FLD(f) abuf->fields.fmt_add.f |
02310b01 | 1208 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 1209 | |
2ddc0492 DE |
1210 | * FLD (f_r1) = SLLSI (* FLD (f_r1), ANDSI (* FLD (f_r2), 31)); |
1211 | TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1)); | |
e0bd6e18 | 1212 | |
2ddc0492 DE |
1213 | #undef FLD |
1214 | } | |
1215 | BREAK (sem); | |
1216 | ||
970a8fd6 | 1217 | CASE (sem, INSN_SLL3) : /* sll3 $dr,$sr,$simm16 */ |
2ddc0492 | 1218 | { |
970a8fd6 | 1219 | #define FLD(f) abuf->fields.fmt_sll3.f |
02310b01 | 1220 | new_pc = SEM_NEXT_PC (sem_arg, 4); |
e0bd6e18 | 1221 | |
2ddc0492 DE |
1222 | * FLD (f_r1) = SLLSI (* FLD (f_r2), ANDSI (FLD (f_simm16), 31)); |
1223 | TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1)); | |
e0bd6e18 | 1224 | |
2ddc0492 DE |
1225 | #undef FLD |
1226 | } | |
1227 | BREAK (sem); | |
1228 | ||
970a8fd6 | 1229 | CASE (sem, INSN_SLLI) : /* slli $dr,$uimm5 */ |
2ddc0492 | 1230 | { |
970a8fd6 | 1231 | #define FLD(f) abuf->fields.fmt_slli.f |
02310b01 | 1232 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 1233 | |
2ddc0492 DE |
1234 | * FLD (f_r1) = SLLSI (* FLD (f_r1), FLD (f_uimm5)); |
1235 | TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1)); | |
e0bd6e18 | 1236 | |
2ddc0492 DE |
1237 | #undef FLD |
1238 | } | |
1239 | BREAK (sem); | |
1240 | ||
1241 | CASE (sem, INSN_SRA) : /* sra $dr,$sr */ | |
1242 | { | |
970a8fd6 | 1243 | #define FLD(f) abuf->fields.fmt_add.f |
02310b01 | 1244 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 1245 | |
2ddc0492 DE |
1246 | * FLD (f_r1) = SRASI (* FLD (f_r1), ANDSI (* FLD (f_r2), 31)); |
1247 | TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1)); | |
e0bd6e18 | 1248 | |
2ddc0492 DE |
1249 | #undef FLD |
1250 | } | |
1251 | BREAK (sem); | |
1252 | ||
970a8fd6 | 1253 | CASE (sem, INSN_SRA3) : /* sra3 $dr,$sr,$simm16 */ |
2ddc0492 | 1254 | { |
970a8fd6 | 1255 | #define FLD(f) abuf->fields.fmt_sll3.f |
02310b01 | 1256 | new_pc = SEM_NEXT_PC (sem_arg, 4); |
e0bd6e18 | 1257 | |
2ddc0492 DE |
1258 | * FLD (f_r1) = SRASI (* FLD (f_r2), ANDSI (FLD (f_simm16), 31)); |
1259 | TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1)); | |
e0bd6e18 | 1260 | |
2ddc0492 DE |
1261 | #undef FLD |
1262 | } | |
1263 | BREAK (sem); | |
1264 | ||
970a8fd6 | 1265 | CASE (sem, INSN_SRAI) : /* srai $dr,$uimm5 */ |
2ddc0492 | 1266 | { |
970a8fd6 | 1267 | #define FLD(f) abuf->fields.fmt_slli.f |
02310b01 | 1268 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 1269 | |
2ddc0492 DE |
1270 | * FLD (f_r1) = SRASI (* FLD (f_r1), FLD (f_uimm5)); |
1271 | TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1)); | |
e0bd6e18 | 1272 | |
2ddc0492 DE |
1273 | #undef FLD |
1274 | } | |
1275 | BREAK (sem); | |
1276 | ||
1277 | CASE (sem, INSN_SRL) : /* srl $dr,$sr */ | |
1278 | { | |
970a8fd6 | 1279 | #define FLD(f) abuf->fields.fmt_add.f |
02310b01 | 1280 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 1281 | |
2ddc0492 DE |
1282 | * FLD (f_r1) = SRLSI (* FLD (f_r1), ANDSI (* FLD (f_r2), 31)); |
1283 | TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1)); | |
e0bd6e18 | 1284 | |
2ddc0492 DE |
1285 | #undef FLD |
1286 | } | |
1287 | BREAK (sem); | |
1288 | ||
970a8fd6 | 1289 | CASE (sem, INSN_SRL3) : /* srl3 $dr,$sr,$simm16 */ |
2ddc0492 | 1290 | { |
970a8fd6 | 1291 | #define FLD(f) abuf->fields.fmt_sll3.f |
02310b01 | 1292 | new_pc = SEM_NEXT_PC (sem_arg, 4); |
e0bd6e18 | 1293 | |
2ddc0492 DE |
1294 | * FLD (f_r1) = SRLSI (* FLD (f_r2), ANDSI (FLD (f_simm16), 31)); |
1295 | TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1)); | |
e0bd6e18 | 1296 | |
2ddc0492 DE |
1297 | #undef FLD |
1298 | } | |
1299 | BREAK (sem); | |
1300 | ||
970a8fd6 | 1301 | CASE (sem, INSN_SRLI) : /* srli $dr,$uimm5 */ |
2ddc0492 | 1302 | { |
970a8fd6 | 1303 | #define FLD(f) abuf->fields.fmt_slli.f |
02310b01 | 1304 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 1305 | |
2ddc0492 DE |
1306 | * FLD (f_r1) = SRLSI (* FLD (f_r1), FLD (f_uimm5)); |
1307 | TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1)); | |
e0bd6e18 | 1308 | |
2ddc0492 DE |
1309 | #undef FLD |
1310 | } | |
1311 | BREAK (sem); | |
1312 | ||
1313 | CASE (sem, INSN_ST) : /* st $src1,@$src2 */ | |
1314 | { | |
970a8fd6 | 1315 | #define FLD(f) abuf->fields.fmt_st.f |
02310b01 | 1316 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 1317 | |
2ddc0492 | 1318 | SETMEMSI (current_cpu, * FLD (f_r2), * FLD (f_r1)); |
a8981d67 | 1319 | TRACE_RESULT (current_cpu, "memory", 'x', GETMEMSI (current_cpu, * FLD (f_r2))); |
e0bd6e18 | 1320 | |
2ddc0492 DE |
1321 | #undef FLD |
1322 | } | |
1323 | BREAK (sem); | |
1324 | ||
1325 | CASE (sem, INSN_ST_D) : /* st $src1,@($slo16,$src2) */ | |
1326 | { | |
970a8fd6 | 1327 | #define FLD(f) abuf->fields.fmt_st_d.f |
02310b01 | 1328 | new_pc = SEM_NEXT_PC (sem_arg, 4); |
e0bd6e18 | 1329 | |
2ddc0492 | 1330 | SETMEMSI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)), * FLD (f_r1)); |
a8981d67 | 1331 | TRACE_RESULT (current_cpu, "memory", 'x', GETMEMSI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)))); |
e0bd6e18 | 1332 | |
2ddc0492 DE |
1333 | #undef FLD |
1334 | } | |
1335 | BREAK (sem); | |
1336 | ||
1337 | CASE (sem, INSN_STB) : /* stb $src1,@$src2 */ | |
1338 | { | |
970a8fd6 | 1339 | #define FLD(f) abuf->fields.fmt_stb.f |
02310b01 | 1340 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 1341 | |
2ddc0492 | 1342 | SETMEMQI (current_cpu, * FLD (f_r2), * FLD (f_r1)); |
a8981d67 | 1343 | TRACE_RESULT (current_cpu, "memory", 'x', GETMEMQI (current_cpu, * FLD (f_r2))); |
e0bd6e18 | 1344 | |
2ddc0492 DE |
1345 | #undef FLD |
1346 | } | |
1347 | BREAK (sem); | |
1348 | ||
1349 | CASE (sem, INSN_STB_D) : /* stb $src1,@($slo16,$src2) */ | |
1350 | { | |
970a8fd6 | 1351 | #define FLD(f) abuf->fields.fmt_stb_d.f |
02310b01 | 1352 | new_pc = SEM_NEXT_PC (sem_arg, 4); |
e0bd6e18 | 1353 | |
2ddc0492 | 1354 | SETMEMQI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)), * FLD (f_r1)); |
a8981d67 | 1355 | TRACE_RESULT (current_cpu, "memory", 'x', GETMEMQI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)))); |
e0bd6e18 | 1356 | |
2ddc0492 DE |
1357 | #undef FLD |
1358 | } | |
1359 | BREAK (sem); | |
1360 | ||
1361 | CASE (sem, INSN_STH) : /* sth $src1,@$src2 */ | |
1362 | { | |
970a8fd6 | 1363 | #define FLD(f) abuf->fields.fmt_sth.f |
02310b01 | 1364 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 1365 | |
2ddc0492 | 1366 | SETMEMHI (current_cpu, * FLD (f_r2), * FLD (f_r1)); |
a8981d67 | 1367 | TRACE_RESULT (current_cpu, "memory", 'x', GETMEMHI (current_cpu, * FLD (f_r2))); |
e0bd6e18 | 1368 | |
2ddc0492 DE |
1369 | #undef FLD |
1370 | } | |
1371 | BREAK (sem); | |
1372 | ||
1373 | CASE (sem, INSN_STH_D) : /* sth $src1,@($slo16,$src2) */ | |
1374 | { | |
970a8fd6 | 1375 | #define FLD(f) abuf->fields.fmt_sth_d.f |
02310b01 | 1376 | new_pc = SEM_NEXT_PC (sem_arg, 4); |
e0bd6e18 | 1377 | |
2ddc0492 | 1378 | SETMEMHI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)), * FLD (f_r1)); |
a8981d67 | 1379 | TRACE_RESULT (current_cpu, "memory", 'x', GETMEMHI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)))); |
e0bd6e18 | 1380 | |
2ddc0492 DE |
1381 | #undef FLD |
1382 | } | |
1383 | BREAK (sem); | |
1384 | ||
1385 | CASE (sem, INSN_ST_PLUS) : /* st $src1,@+$src2 */ | |
1386 | { | |
970a8fd6 | 1387 | #define FLD(f) abuf->fields.fmt_st_plus.f |
02310b01 | 1388 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 1389 | |
2ddc0492 | 1390 | do { |
02310b01 DE |
1391 | SI tmp_new_src2; |
1392 | tmp_new_src2 = ADDSI (* FLD (f_r2), 4); | |
1393 | SETMEMSI (current_cpu, tmp_new_src2, * FLD (f_r1)); | |
a8981d67 | 1394 | TRACE_RESULT (current_cpu, "memory", 'x', GETMEMSI (current_cpu, tmp_new_src2)); |
02310b01 | 1395 | * FLD (f_r2) = tmp_new_src2; |
2ddc0492 | 1396 | TRACE_RESULT (current_cpu, "src2", 'x', * FLD (f_r2)); |
2ddc0492 | 1397 | } while (0); |
e0bd6e18 | 1398 | |
2ddc0492 DE |
1399 | #undef FLD |
1400 | } | |
1401 | BREAK (sem); | |
1402 | ||
1403 | CASE (sem, INSN_ST_MINUS) : /* st $src1,@-$src2 */ | |
1404 | { | |
970a8fd6 | 1405 | #define FLD(f) abuf->fields.fmt_st_plus.f |
02310b01 | 1406 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 1407 | |
2ddc0492 | 1408 | do { |
02310b01 DE |
1409 | SI tmp_new_src2; |
1410 | tmp_new_src2 = SUBSI (* FLD (f_r2), 4); | |
1411 | SETMEMSI (current_cpu, tmp_new_src2, * FLD (f_r1)); | |
a8981d67 | 1412 | TRACE_RESULT (current_cpu, "memory", 'x', GETMEMSI (current_cpu, tmp_new_src2)); |
02310b01 | 1413 | * FLD (f_r2) = tmp_new_src2; |
2ddc0492 | 1414 | TRACE_RESULT (current_cpu, "src2", 'x', * FLD (f_r2)); |
2ddc0492 | 1415 | } while (0); |
e0bd6e18 | 1416 | |
2ddc0492 DE |
1417 | #undef FLD |
1418 | } | |
1419 | BREAK (sem); | |
1420 | ||
1421 | CASE (sem, INSN_SUB) : /* sub $dr,$sr */ | |
1422 | { | |
970a8fd6 | 1423 | #define FLD(f) abuf->fields.fmt_add.f |
02310b01 | 1424 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 1425 | |
2ddc0492 DE |
1426 | * FLD (f_r1) = SUBSI (* FLD (f_r1), * FLD (f_r2)); |
1427 | TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1)); | |
e0bd6e18 | 1428 | |
2ddc0492 DE |
1429 | #undef FLD |
1430 | } | |
1431 | BREAK (sem); | |
1432 | ||
1433 | CASE (sem, INSN_SUBV) : /* subv $dr,$sr */ | |
1434 | { | |
970a8fd6 | 1435 | #define FLD(f) abuf->fields.fmt_addv.f |
02310b01 | 1436 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 1437 | |
2ddc0492 | 1438 | do { |
a040908c | 1439 | UBI temp1;SI temp0; |
2ddc0492 DE |
1440 | temp0 = SUBSI (* FLD (f_r1), * FLD (f_r2)); |
1441 | temp1 = SUBOFSI (* FLD (f_r1), * FLD (f_r2), 0); | |
1442 | * FLD (f_r1) = temp0; | |
1443 | TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1)); | |
1444 | CPU (h_cond) = temp1; | |
1445 | TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond)); | |
1446 | } while (0); | |
e0bd6e18 | 1447 | |
2ddc0492 DE |
1448 | #undef FLD |
1449 | } | |
1450 | BREAK (sem); | |
1451 | ||
1452 | CASE (sem, INSN_SUBX) : /* subx $dr,$sr */ | |
1453 | { | |
970a8fd6 | 1454 | #define FLD(f) abuf->fields.fmt_addx.f |
02310b01 | 1455 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 1456 | |
2ddc0492 | 1457 | do { |
a040908c | 1458 | UBI temp1;SI temp0; |
2ddc0492 DE |
1459 | temp0 = SUBCSI (* FLD (f_r1), * FLD (f_r2), CPU (h_cond)); |
1460 | temp1 = SUBCFSI (* FLD (f_r1), * FLD (f_r2), CPU (h_cond)); | |
1461 | * FLD (f_r1) = temp0; | |
1462 | TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1)); | |
1463 | CPU (h_cond) = temp1; | |
1464 | TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond)); | |
1465 | } while (0); | |
e0bd6e18 | 1466 | |
2ddc0492 DE |
1467 | #undef FLD |
1468 | } | |
1469 | BREAK (sem); | |
1470 | ||
970a8fd6 | 1471 | CASE (sem, INSN_TRAP) : /* trap $uimm4 */ |
2ddc0492 | 1472 | { |
970a8fd6 | 1473 | #define FLD(f) abuf->fields.fmt_trap.f |
02310b01 | 1474 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 1475 | |
cab58155 DE |
1476 | do { |
1477 | m32r_h_cr_set (current_cpu, 6, ADDSI (CPU (h_pc), 4)); | |
a8981d67 | 1478 | TRACE_RESULT (current_cpu, "cr-6", 'x', m32r_h_cr_get (current_cpu, 6)); |
970a8fd6 | 1479 | m32r_h_cr_set (current_cpu, 0, ANDSI (SLLSI (m32r_h_cr_get (current_cpu, 0), 8), 65408)); |
a8981d67 | 1480 | TRACE_RESULT (current_cpu, "cr-0", 'x', m32r_h_cr_get (current_cpu, 0)); |
a040908c | 1481 | BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, a_m32r_trap (current_cpu, FLD (f_uimm4)))); |
a8981d67 | 1482 | TRACE_RESULT (current_cpu, "pc", 'x', new_pc); |
cab58155 | 1483 | } while (0); |
e0bd6e18 | 1484 | |
2ddc0492 DE |
1485 | #undef FLD |
1486 | } | |
1487 | BREAK (sem); | |
1488 | ||
1489 | CASE (sem, INSN_UNLOCK) : /* unlock $src1,@$src2 */ | |
1490 | { | |
970a8fd6 | 1491 | #define FLD(f) abuf->fields.fmt_unlock.f |
02310b01 | 1492 | new_pc = SEM_NEXT_PC (sem_arg, 2); |
e0bd6e18 | 1493 | |
cab58155 DE |
1494 | do { |
1495 | if (CPU (h_lock)) { | |
1496 | SETMEMSI (current_cpu, * FLD (f_r2), * FLD (f_r1)); | |
a8981d67 | 1497 | TRACE_RESULT (current_cpu, "memory", 'x', GETMEMSI (current_cpu, * FLD (f_r2))); |
cab58155 DE |
1498 | } |
1499 | CPU (h_lock) = 0; | |
a8981d67 | 1500 | TRACE_RESULT (current_cpu, "lock-0", 'x', CPU (h_lock)); |
cab58155 | 1501 | } while (0); |
e0bd6e18 | 1502 | |
2ddc0492 DE |
1503 | #undef FLD |
1504 | } | |
1505 | BREAK (sem); | |
1506 | ||
1507 | ||
1508 | } | |
1509 | ENDSWITCH (sem) /* End of semantic switch. */ | |
1510 | ||
1511 | PC = new_pc; | |
1512 | } | |
1513 | ||
1514 | #endif /* DEFINE_SWITCH */ |