Commit | Line | Data |
---|---|---|
c906108c SS |
1 | /* Simulator instruction semantics for m32rbf. |
2 | ||
3 | THIS FILE IS MACHINE GENERATED WITH CGEN. | |
4 | ||
5 | Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc. | |
6 | ||
7 | This file is part of the GNU Simulators. | |
8 | ||
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2, or (at your option) | |
12 | any later version. | |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License along | |
20 | with this program; if not, write to the Free Software Foundation, Inc., | |
21 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
22 | ||
23 | */ | |
24 | ||
25 | #ifdef DEFINE_LABELS | |
26 | ||
27 | /* The labels have the case they have because the enum of insn types | |
28 | is all uppercase and in the non-stdc case the insn symbol is built | |
29 | into the enum name. */ | |
30 | ||
31 | static struct { | |
32 | int index; | |
33 | void *label; | |
34 | } labels[] = { | |
35 | { M32RBF_INSN_X_INVALID, && case_sem_INSN_X_INVALID }, | |
36 | { M32RBF_INSN_X_AFTER, && case_sem_INSN_X_AFTER }, | |
37 | { M32RBF_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE }, | |
38 | { M32RBF_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN }, | |
39 | { M32RBF_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN }, | |
40 | { M32RBF_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN }, | |
41 | { M32RBF_INSN_ADD, && case_sem_INSN_ADD }, | |
42 | { M32RBF_INSN_ADD3, && case_sem_INSN_ADD3 }, | |
43 | { M32RBF_INSN_AND, && case_sem_INSN_AND }, | |
44 | { M32RBF_INSN_AND3, && case_sem_INSN_AND3 }, | |
45 | { M32RBF_INSN_OR, && case_sem_INSN_OR }, | |
46 | { M32RBF_INSN_OR3, && case_sem_INSN_OR3 }, | |
47 | { M32RBF_INSN_XOR, && case_sem_INSN_XOR }, | |
48 | { M32RBF_INSN_XOR3, && case_sem_INSN_XOR3 }, | |
49 | { M32RBF_INSN_ADDI, && case_sem_INSN_ADDI }, | |
50 | { M32RBF_INSN_ADDV, && case_sem_INSN_ADDV }, | |
51 | { M32RBF_INSN_ADDV3, && case_sem_INSN_ADDV3 }, | |
52 | { M32RBF_INSN_ADDX, && case_sem_INSN_ADDX }, | |
53 | { M32RBF_INSN_BC8, && case_sem_INSN_BC8 }, | |
54 | { M32RBF_INSN_BC24, && case_sem_INSN_BC24 }, | |
55 | { M32RBF_INSN_BEQ, && case_sem_INSN_BEQ }, | |
56 | { M32RBF_INSN_BEQZ, && case_sem_INSN_BEQZ }, | |
57 | { M32RBF_INSN_BGEZ, && case_sem_INSN_BGEZ }, | |
58 | { M32RBF_INSN_BGTZ, && case_sem_INSN_BGTZ }, | |
59 | { M32RBF_INSN_BLEZ, && case_sem_INSN_BLEZ }, | |
60 | { M32RBF_INSN_BLTZ, && case_sem_INSN_BLTZ }, | |
61 | { M32RBF_INSN_BNEZ, && case_sem_INSN_BNEZ }, | |
62 | { M32RBF_INSN_BL8, && case_sem_INSN_BL8 }, | |
63 | { M32RBF_INSN_BL24, && case_sem_INSN_BL24 }, | |
64 | { M32RBF_INSN_BNC8, && case_sem_INSN_BNC8 }, | |
65 | { M32RBF_INSN_BNC24, && case_sem_INSN_BNC24 }, | |
66 | { M32RBF_INSN_BNE, && case_sem_INSN_BNE }, | |
67 | { M32RBF_INSN_BRA8, && case_sem_INSN_BRA8 }, | |
68 | { M32RBF_INSN_BRA24, && case_sem_INSN_BRA24 }, | |
69 | { M32RBF_INSN_CMP, && case_sem_INSN_CMP }, | |
70 | { M32RBF_INSN_CMPI, && case_sem_INSN_CMPI }, | |
71 | { M32RBF_INSN_CMPU, && case_sem_INSN_CMPU }, | |
72 | { M32RBF_INSN_CMPUI, && case_sem_INSN_CMPUI }, | |
73 | { M32RBF_INSN_DIV, && case_sem_INSN_DIV }, | |
74 | { M32RBF_INSN_DIVU, && case_sem_INSN_DIVU }, | |
75 | { M32RBF_INSN_REM, && case_sem_INSN_REM }, | |
76 | { M32RBF_INSN_REMU, && case_sem_INSN_REMU }, | |
77 | { M32RBF_INSN_JL, && case_sem_INSN_JL }, | |
78 | { M32RBF_INSN_JMP, && case_sem_INSN_JMP }, | |
79 | { M32RBF_INSN_LD, && case_sem_INSN_LD }, | |
80 | { M32RBF_INSN_LD_D, && case_sem_INSN_LD_D }, | |
81 | { M32RBF_INSN_LDB, && case_sem_INSN_LDB }, | |
82 | { M32RBF_INSN_LDB_D, && case_sem_INSN_LDB_D }, | |
83 | { M32RBF_INSN_LDH, && case_sem_INSN_LDH }, | |
84 | { M32RBF_INSN_LDH_D, && case_sem_INSN_LDH_D }, | |
85 | { M32RBF_INSN_LDUB, && case_sem_INSN_LDUB }, | |
86 | { M32RBF_INSN_LDUB_D, && case_sem_INSN_LDUB_D }, | |
87 | { M32RBF_INSN_LDUH, && case_sem_INSN_LDUH }, | |
88 | { M32RBF_INSN_LDUH_D, && case_sem_INSN_LDUH_D }, | |
89 | { M32RBF_INSN_LD_PLUS, && case_sem_INSN_LD_PLUS }, | |
90 | { M32RBF_INSN_LD24, && case_sem_INSN_LD24 }, | |
91 | { M32RBF_INSN_LDI8, && case_sem_INSN_LDI8 }, | |
92 | { M32RBF_INSN_LDI16, && case_sem_INSN_LDI16 }, | |
93 | { M32RBF_INSN_LOCK, && case_sem_INSN_LOCK }, | |
94 | { M32RBF_INSN_MACHI, && case_sem_INSN_MACHI }, | |
95 | { M32RBF_INSN_MACLO, && case_sem_INSN_MACLO }, | |
96 | { M32RBF_INSN_MACWHI, && case_sem_INSN_MACWHI }, | |
97 | { M32RBF_INSN_MACWLO, && case_sem_INSN_MACWLO }, | |
98 | { M32RBF_INSN_MUL, && case_sem_INSN_MUL }, | |
99 | { M32RBF_INSN_MULHI, && case_sem_INSN_MULHI }, | |
100 | { M32RBF_INSN_MULLO, && case_sem_INSN_MULLO }, | |
101 | { M32RBF_INSN_MULWHI, && case_sem_INSN_MULWHI }, | |
102 | { M32RBF_INSN_MULWLO, && case_sem_INSN_MULWLO }, | |
103 | { M32RBF_INSN_MV, && case_sem_INSN_MV }, | |
104 | { M32RBF_INSN_MVFACHI, && case_sem_INSN_MVFACHI }, | |
105 | { M32RBF_INSN_MVFACLO, && case_sem_INSN_MVFACLO }, | |
106 | { M32RBF_INSN_MVFACMI, && case_sem_INSN_MVFACMI }, | |
107 | { M32RBF_INSN_MVFC, && case_sem_INSN_MVFC }, | |
108 | { M32RBF_INSN_MVTACHI, && case_sem_INSN_MVTACHI }, | |
109 | { M32RBF_INSN_MVTACLO, && case_sem_INSN_MVTACLO }, | |
110 | { M32RBF_INSN_MVTC, && case_sem_INSN_MVTC }, | |
111 | { M32RBF_INSN_NEG, && case_sem_INSN_NEG }, | |
112 | { M32RBF_INSN_NOP, && case_sem_INSN_NOP }, | |
113 | { M32RBF_INSN_NOT, && case_sem_INSN_NOT }, | |
114 | { M32RBF_INSN_RAC, && case_sem_INSN_RAC }, | |
115 | { M32RBF_INSN_RACH, && case_sem_INSN_RACH }, | |
116 | { M32RBF_INSN_RTE, && case_sem_INSN_RTE }, | |
117 | { M32RBF_INSN_SETH, && case_sem_INSN_SETH }, | |
118 | { M32RBF_INSN_SLL, && case_sem_INSN_SLL }, | |
119 | { M32RBF_INSN_SLL3, && case_sem_INSN_SLL3 }, | |
120 | { M32RBF_INSN_SLLI, && case_sem_INSN_SLLI }, | |
121 | { M32RBF_INSN_SRA, && case_sem_INSN_SRA }, | |
122 | { M32RBF_INSN_SRA3, && case_sem_INSN_SRA3 }, | |
123 | { M32RBF_INSN_SRAI, && case_sem_INSN_SRAI }, | |
124 | { M32RBF_INSN_SRL, && case_sem_INSN_SRL }, | |
125 | { M32RBF_INSN_SRL3, && case_sem_INSN_SRL3 }, | |
126 | { M32RBF_INSN_SRLI, && case_sem_INSN_SRLI }, | |
127 | { M32RBF_INSN_ST, && case_sem_INSN_ST }, | |
128 | { M32RBF_INSN_ST_D, && case_sem_INSN_ST_D }, | |
129 | { M32RBF_INSN_STB, && case_sem_INSN_STB }, | |
130 | { M32RBF_INSN_STB_D, && case_sem_INSN_STB_D }, | |
131 | { M32RBF_INSN_STH, && case_sem_INSN_STH }, | |
132 | { M32RBF_INSN_STH_D, && case_sem_INSN_STH_D }, | |
133 | { M32RBF_INSN_ST_PLUS, && case_sem_INSN_ST_PLUS }, | |
134 | { M32RBF_INSN_ST_MINUS, && case_sem_INSN_ST_MINUS }, | |
135 | { M32RBF_INSN_SUB, && case_sem_INSN_SUB }, | |
136 | { M32RBF_INSN_SUBV, && case_sem_INSN_SUBV }, | |
137 | { M32RBF_INSN_SUBX, && case_sem_INSN_SUBX }, | |
138 | { M32RBF_INSN_TRAP, && case_sem_INSN_TRAP }, | |
139 | { M32RBF_INSN_UNLOCK, && case_sem_INSN_UNLOCK }, | |
140 | { 0, 0 } | |
141 | }; | |
142 | int i; | |
143 | ||
144 | for (i = 0; labels[i].label != 0; ++i) | |
96baa820 | 145 | { |
c906108c | 146 | #if FAST_P |
96baa820 | 147 | CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label; |
c906108c | 148 | #else |
96baa820 | 149 | CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label; |
c906108c | 150 | #endif |
96baa820 | 151 | } |
c906108c SS |
152 | |
153 | #undef DEFINE_LABELS | |
154 | #endif /* DEFINE_LABELS */ | |
155 | ||
156 | #ifdef DEFINE_SWITCH | |
157 | ||
158 | /* If hyper-fast [well not unnecessarily slow] execution is selected, turn | |
159 | off frills like tracing and profiling. */ | |
160 | /* FIXME: A better way would be to have TRACE_RESULT check for something | |
161 | that can cause it to be optimized out. Another way would be to emit | |
162 | special handlers into the instruction "stream". */ | |
163 | ||
164 | #if FAST_P | |
165 | #undef TRACE_RESULT | |
166 | #define TRACE_RESULT(cpu, abuf, name, type, val) | |
167 | #endif | |
168 | ||
169 | #undef GET_ATTR | |
170 | #define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr) | |
171 | ||
172 | { | |
173 | ||
174 | #if WITH_SCACHE_PBB | |
175 | ||
176 | /* Branch to next handler without going around main loop. */ | |
177 | #define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case | |
178 | SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) | |
179 | ||
180 | #else /* ! WITH_SCACHE_PBB */ | |
181 | ||
182 | #define NEXT(vpc) BREAK (sem) | |
183 | #ifdef __GNUC__ | |
184 | #if FAST_P | |
185 | SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab) | |
186 | #else | |
187 | SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab) | |
188 | #endif | |
189 | #else | |
190 | SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num) | |
191 | #endif | |
192 | ||
193 | #endif /* ! WITH_SCACHE_PBB */ | |
194 | ||
195 | { | |
196 | ||
197 | CASE (sem, INSN_X_INVALID) : /* --invalid-- */ | |
198 | { | |
199 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
200 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
201 | #define FLD(f) abuf->fields.fmt_empty.f | |
202 | int UNUSED written = 0; | |
203 | IADDR UNUSED pc = abuf->addr; | |
204 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
205 | ||
206 | { | |
2acceee2 JM |
207 | /* Update the recorded pc in the cpu state struct. |
208 | Only necessary for WITH_SCACHE case, but to avoid the | |
209 | conditional compilation .... */ | |
c906108c | 210 | SET_H_PC (pc); |
2acceee2 JM |
211 | /* Virtual insns have zero size. Overwrite vpc with address of next insn |
212 | using the default-insn-bitsize spec. When executing insns in parallel | |
213 | we may want to queue the fault and continue execution. */ | |
214 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
215 | vpc = sim_engine_invalid_insn (current_cpu, pc, vpc); | |
c906108c SS |
216 | } |
217 | ||
218 | #undef FLD | |
219 | } | |
220 | NEXT (vpc); | |
221 | ||
222 | CASE (sem, INSN_X_AFTER) : /* --after-- */ | |
223 | { | |
224 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
225 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
226 | #define FLD(f) abuf->fields.fmt_empty.f | |
227 | int UNUSED written = 0; | |
228 | IADDR UNUSED pc = abuf->addr; | |
229 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
230 | ||
231 | { | |
232 | #if WITH_SCACHE_PBB_M32RBF | |
233 | m32rbf_pbb_after (current_cpu, sem_arg); | |
234 | #endif | |
235 | } | |
236 | ||
237 | #undef FLD | |
238 | } | |
239 | NEXT (vpc); | |
240 | ||
241 | CASE (sem, INSN_X_BEFORE) : /* --before-- */ | |
242 | { | |
243 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
244 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
245 | #define FLD(f) abuf->fields.fmt_empty.f | |
246 | int UNUSED written = 0; | |
247 | IADDR UNUSED pc = abuf->addr; | |
248 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
249 | ||
250 | { | |
251 | #if WITH_SCACHE_PBB_M32RBF | |
252 | m32rbf_pbb_before (current_cpu, sem_arg); | |
253 | #endif | |
254 | } | |
255 | ||
256 | #undef FLD | |
257 | } | |
258 | NEXT (vpc); | |
259 | ||
260 | CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */ | |
261 | { | |
262 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
263 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
264 | #define FLD(f) abuf->fields.fmt_empty.f | |
265 | int UNUSED written = 0; | |
266 | IADDR UNUSED pc = abuf->addr; | |
267 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
268 | ||
269 | { | |
270 | #if WITH_SCACHE_PBB_M32RBF | |
271 | #ifdef DEFINE_SWITCH | |
272 | vpc = m32rbf_pbb_cti_chain (current_cpu, sem_arg, | |
96baa820 | 273 | pbb_br_type, pbb_br_npc); |
c906108c SS |
274 | BREAK (sem); |
275 | #else | |
276 | /* FIXME: Allow provision of explicit ifmt spec in insn spec. */ | |
277 | vpc = m32rbf_pbb_cti_chain (current_cpu, sem_arg, | |
96baa820 | 278 | CPU_PBB_BR_TYPE (current_cpu), |
c906108c SS |
279 | CPU_PBB_BR_NPC (current_cpu)); |
280 | #endif | |
281 | #endif | |
282 | } | |
283 | ||
284 | #undef FLD | |
285 | } | |
286 | NEXT (vpc); | |
287 | ||
288 | CASE (sem, INSN_X_CHAIN) : /* --chain-- */ | |
289 | { | |
290 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
291 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
292 | #define FLD(f) abuf->fields.fmt_empty.f | |
293 | int UNUSED written = 0; | |
294 | IADDR UNUSED pc = abuf->addr; | |
295 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
296 | ||
297 | { | |
298 | #if WITH_SCACHE_PBB_M32RBF | |
299 | vpc = m32rbf_pbb_chain (current_cpu, sem_arg); | |
300 | #ifdef DEFINE_SWITCH | |
301 | BREAK (sem); | |
302 | #endif | |
303 | #endif | |
304 | } | |
305 | ||
306 | #undef FLD | |
307 | } | |
308 | NEXT (vpc); | |
309 | ||
310 | CASE (sem, INSN_X_BEGIN) : /* --begin-- */ | |
311 | { | |
312 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
313 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
314 | #define FLD(f) abuf->fields.fmt_empty.f | |
315 | int UNUSED written = 0; | |
316 | IADDR UNUSED pc = abuf->addr; | |
317 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
318 | ||
319 | { | |
320 | #if WITH_SCACHE_PBB_M32RBF | |
fb27a91c | 321 | #if defined DEFINE_SWITCH || defined FAST_P |
c906108c SS |
322 | /* In the switch case FAST_P is a constant, allowing several optimizations |
323 | in any called inline functions. */ | |
324 | vpc = m32rbf_pbb_begin (current_cpu, FAST_P); | |
325 | #else | |
fb27a91c | 326 | #if 0 /* cgen engine can't handle dynamic fast/full switching yet. */ |
c906108c | 327 | vpc = m32rbf_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu))); |
fb27a91c DB |
328 | #else |
329 | vpc = m32rbf_pbb_begin (current_cpu, 0); | |
330 | #endif | |
c906108c SS |
331 | #endif |
332 | #endif | |
333 | } | |
334 | ||
335 | #undef FLD | |
336 | } | |
337 | NEXT (vpc); | |
338 | ||
339 | CASE (sem, INSN_ADD) : /* add $dr,$sr */ | |
340 | { | |
341 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
342 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 343 | #define FLD(f) abuf->fields.sfmt_add.f |
c906108c SS |
344 | int UNUSED written = 0; |
345 | IADDR UNUSED pc = abuf->addr; | |
346 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
347 | ||
348 | { | |
349 | SI opval = ADDSI (* FLD (i_dr), * FLD (i_sr)); | |
350 | * FLD (i_dr) = opval; | |
351 | TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); | |
352 | } | |
353 | ||
354 | #undef FLD | |
355 | } | |
356 | NEXT (vpc); | |
357 | ||
358 | CASE (sem, INSN_ADD3) : /* add3 $dr,$sr,$hash$slo16 */ | |
359 | { | |
360 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
361 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 362 | #define FLD(f) abuf->fields.sfmt_add3.f |
c906108c SS |
363 | int UNUSED written = 0; |
364 | IADDR UNUSED pc = abuf->addr; | |
365 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
366 | ||
367 | { | |
368 | SI opval = ADDSI (* FLD (i_sr), FLD (f_simm16)); | |
369 | * FLD (i_dr) = opval; | |
370 | TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); | |
371 | } | |
372 | ||
373 | #undef FLD | |
374 | } | |
375 | NEXT (vpc); | |
376 | ||
377 | CASE (sem, INSN_AND) : /* and $dr,$sr */ | |
378 | { | |
379 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
380 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 381 | #define FLD(f) abuf->fields.sfmt_add.f |
c906108c SS |
382 | int UNUSED written = 0; |
383 | IADDR UNUSED pc = abuf->addr; | |
384 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
385 | ||
386 | { | |
387 | SI opval = ANDSI (* FLD (i_dr), * FLD (i_sr)); | |
388 | * FLD (i_dr) = opval; | |
389 | TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); | |
390 | } | |
391 | ||
392 | #undef FLD | |
393 | } | |
394 | NEXT (vpc); | |
395 | ||
396 | CASE (sem, INSN_AND3) : /* and3 $dr,$sr,$uimm16 */ | |
397 | { | |
398 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
399 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 400 | #define FLD(f) abuf->fields.sfmt_and3.f |
c906108c SS |
401 | int UNUSED written = 0; |
402 | IADDR UNUSED pc = abuf->addr; | |
403 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
404 | ||
405 | { | |
406 | SI opval = ANDSI (* FLD (i_sr), FLD (f_uimm16)); | |
407 | * FLD (i_dr) = opval; | |
408 | TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); | |
409 | } | |
410 | ||
411 | #undef FLD | |
412 | } | |
413 | NEXT (vpc); | |
414 | ||
415 | CASE (sem, INSN_OR) : /* or $dr,$sr */ | |
416 | { | |
417 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
418 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 419 | #define FLD(f) abuf->fields.sfmt_add.f |
c906108c SS |
420 | int UNUSED written = 0; |
421 | IADDR UNUSED pc = abuf->addr; | |
422 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
423 | ||
424 | { | |
425 | SI opval = ORSI (* FLD (i_dr), * FLD (i_sr)); | |
426 | * FLD (i_dr) = opval; | |
427 | TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); | |
428 | } | |
429 | ||
430 | #undef FLD | |
431 | } | |
432 | NEXT (vpc); | |
433 | ||
434 | CASE (sem, INSN_OR3) : /* or3 $dr,$sr,$hash$ulo16 */ | |
435 | { | |
436 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
437 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 438 | #define FLD(f) abuf->fields.sfmt_and3.f |
c906108c SS |
439 | int UNUSED written = 0; |
440 | IADDR UNUSED pc = abuf->addr; | |
441 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
442 | ||
443 | { | |
444 | SI opval = ORSI (* FLD (i_sr), FLD (f_uimm16)); | |
445 | * FLD (i_dr) = opval; | |
446 | TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); | |
447 | } | |
448 | ||
449 | #undef FLD | |
450 | } | |
451 | NEXT (vpc); | |
452 | ||
453 | CASE (sem, INSN_XOR) : /* xor $dr,$sr */ | |
454 | { | |
455 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
456 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 457 | #define FLD(f) abuf->fields.sfmt_add.f |
c906108c SS |
458 | int UNUSED written = 0; |
459 | IADDR UNUSED pc = abuf->addr; | |
460 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
461 | ||
462 | { | |
463 | SI opval = XORSI (* FLD (i_dr), * FLD (i_sr)); | |
464 | * FLD (i_dr) = opval; | |
465 | TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); | |
466 | } | |
467 | ||
468 | #undef FLD | |
469 | } | |
470 | NEXT (vpc); | |
471 | ||
472 | CASE (sem, INSN_XOR3) : /* xor3 $dr,$sr,$uimm16 */ | |
473 | { | |
474 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
475 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 476 | #define FLD(f) abuf->fields.sfmt_and3.f |
c906108c SS |
477 | int UNUSED written = 0; |
478 | IADDR UNUSED pc = abuf->addr; | |
479 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
480 | ||
481 | { | |
482 | SI opval = XORSI (* FLD (i_sr), FLD (f_uimm16)); | |
483 | * FLD (i_dr) = opval; | |
484 | TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); | |
485 | } | |
486 | ||
487 | #undef FLD | |
488 | } | |
489 | NEXT (vpc); | |
490 | ||
491 | CASE (sem, INSN_ADDI) : /* addi $dr,$simm8 */ | |
492 | { | |
493 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
494 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 495 | #define FLD(f) abuf->fields.sfmt_addi.f |
c906108c SS |
496 | int UNUSED written = 0; |
497 | IADDR UNUSED pc = abuf->addr; | |
498 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
499 | ||
500 | { | |
501 | SI opval = ADDSI (* FLD (i_dr), FLD (f_simm8)); | |
502 | * FLD (i_dr) = opval; | |
503 | TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); | |
504 | } | |
505 | ||
506 | #undef FLD | |
507 | } | |
508 | NEXT (vpc); | |
509 | ||
510 | CASE (sem, INSN_ADDV) : /* addv $dr,$sr */ | |
511 | { | |
512 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
513 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 514 | #define FLD(f) abuf->fields.sfmt_add.f |
c906108c SS |
515 | int UNUSED written = 0; |
516 | IADDR UNUSED pc = abuf->addr; | |
517 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
518 | ||
7a292a7a SS |
519 | { |
520 | SI temp0;BI temp1; | |
c906108c SS |
521 | temp0 = ADDSI (* FLD (i_dr), * FLD (i_sr)); |
522 | temp1 = ADDOFSI (* FLD (i_dr), * FLD (i_sr), 0); | |
523 | { | |
524 | SI opval = temp0; | |
525 | * FLD (i_dr) = opval; | |
526 | TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); | |
527 | } | |
528 | { | |
529 | BI opval = temp1; | |
530 | CPU (h_cond) = opval; | |
531 | TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval); | |
532 | } | |
7a292a7a | 533 | } |
c906108c SS |
534 | |
535 | #undef FLD | |
536 | } | |
537 | NEXT (vpc); | |
538 | ||
539 | CASE (sem, INSN_ADDV3) : /* addv3 $dr,$sr,$simm16 */ | |
540 | { | |
541 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
542 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 543 | #define FLD(f) abuf->fields.sfmt_add3.f |
c906108c SS |
544 | int UNUSED written = 0; |
545 | IADDR UNUSED pc = abuf->addr; | |
546 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
547 | ||
7a292a7a SS |
548 | { |
549 | SI temp0;BI temp1; | |
c906108c SS |
550 | temp0 = ADDSI (* FLD (i_sr), FLD (f_simm16)); |
551 | temp1 = ADDOFSI (* FLD (i_sr), FLD (f_simm16), 0); | |
552 | { | |
553 | SI opval = temp0; | |
554 | * FLD (i_dr) = opval; | |
555 | TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); | |
556 | } | |
557 | { | |
558 | BI opval = temp1; | |
559 | CPU (h_cond) = opval; | |
560 | TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval); | |
561 | } | |
7a292a7a | 562 | } |
c906108c SS |
563 | |
564 | #undef FLD | |
565 | } | |
566 | NEXT (vpc); | |
567 | ||
568 | CASE (sem, INSN_ADDX) : /* addx $dr,$sr */ | |
569 | { | |
570 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
571 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 572 | #define FLD(f) abuf->fields.sfmt_add.f |
c906108c SS |
573 | int UNUSED written = 0; |
574 | IADDR UNUSED pc = abuf->addr; | |
575 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
576 | ||
7a292a7a SS |
577 | { |
578 | SI temp0;BI temp1; | |
c906108c SS |
579 | temp0 = ADDCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond)); |
580 | temp1 = ADDCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond)); | |
581 | { | |
582 | SI opval = temp0; | |
583 | * FLD (i_dr) = opval; | |
584 | TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); | |
585 | } | |
586 | { | |
587 | BI opval = temp1; | |
588 | CPU (h_cond) = opval; | |
589 | TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval); | |
590 | } | |
7a292a7a | 591 | } |
c906108c SS |
592 | |
593 | #undef FLD | |
594 | } | |
595 | NEXT (vpc); | |
596 | ||
597 | CASE (sem, INSN_BC8) : /* bc.s $disp8 */ | |
598 | { | |
599 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
600 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 601 | #define FLD(f) abuf->fields.sfmt_bl8.f |
c906108c SS |
602 | int UNUSED written = 0; |
603 | IADDR UNUSED pc = abuf->addr; | |
604 | SEM_BRANCH_INIT | |
605 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
606 | ||
607 | if (CPU (h_cond)) { | |
608 | { | |
609 | USI opval = FLD (i_disp8); | |
96baa820 | 610 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); |
c906108c SS |
611 | written |= (1 << 2); |
612 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
613 | } | |
614 | } | |
615 | ||
616 | abuf->written = written; | |
617 | SEM_BRANCH_FINI (vpc); | |
618 | #undef FLD | |
619 | } | |
620 | NEXT (vpc); | |
621 | ||
622 | CASE (sem, INSN_BC24) : /* bc.l $disp24 */ | |
623 | { | |
624 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
625 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 626 | #define FLD(f) abuf->fields.sfmt_bl24.f |
c906108c SS |
627 | int UNUSED written = 0; |
628 | IADDR UNUSED pc = abuf->addr; | |
629 | SEM_BRANCH_INIT | |
630 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
631 | ||
632 | if (CPU (h_cond)) { | |
633 | { | |
634 | USI opval = FLD (i_disp24); | |
96baa820 | 635 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); |
c906108c SS |
636 | written |= (1 << 2); |
637 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
638 | } | |
639 | } | |
640 | ||
641 | abuf->written = written; | |
642 | SEM_BRANCH_FINI (vpc); | |
643 | #undef FLD | |
644 | } | |
645 | NEXT (vpc); | |
646 | ||
647 | CASE (sem, INSN_BEQ) : /* beq $src1,$src2,$disp16 */ | |
648 | { | |
649 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
650 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 651 | #define FLD(f) abuf->fields.sfmt_beq.f |
c906108c SS |
652 | int UNUSED written = 0; |
653 | IADDR UNUSED pc = abuf->addr; | |
654 | SEM_BRANCH_INIT | |
655 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
656 | ||
657 | if (EQSI (* FLD (i_src1), * FLD (i_src2))) { | |
658 | { | |
659 | USI opval = FLD (i_disp16); | |
96baa820 | 660 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); |
c906108c SS |
661 | written |= (1 << 3); |
662 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
663 | } | |
664 | } | |
665 | ||
666 | abuf->written = written; | |
667 | SEM_BRANCH_FINI (vpc); | |
668 | #undef FLD | |
669 | } | |
670 | NEXT (vpc); | |
671 | ||
672 | CASE (sem, INSN_BEQZ) : /* beqz $src2,$disp16 */ | |
673 | { | |
674 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
675 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 676 | #define FLD(f) abuf->fields.sfmt_beq.f |
c906108c SS |
677 | int UNUSED written = 0; |
678 | IADDR UNUSED pc = abuf->addr; | |
679 | SEM_BRANCH_INIT | |
680 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
681 | ||
682 | if (EQSI (* FLD (i_src2), 0)) { | |
683 | { | |
684 | USI opval = FLD (i_disp16); | |
96baa820 | 685 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); |
c906108c SS |
686 | written |= (1 << 2); |
687 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
688 | } | |
689 | } | |
690 | ||
691 | abuf->written = written; | |
692 | SEM_BRANCH_FINI (vpc); | |
693 | #undef FLD | |
694 | } | |
695 | NEXT (vpc); | |
696 | ||
697 | CASE (sem, INSN_BGEZ) : /* bgez $src2,$disp16 */ | |
698 | { | |
699 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
700 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 701 | #define FLD(f) abuf->fields.sfmt_beq.f |
c906108c SS |
702 | int UNUSED written = 0; |
703 | IADDR UNUSED pc = abuf->addr; | |
704 | SEM_BRANCH_INIT | |
705 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
706 | ||
707 | if (GESI (* FLD (i_src2), 0)) { | |
708 | { | |
709 | USI opval = FLD (i_disp16); | |
96baa820 | 710 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); |
c906108c SS |
711 | written |= (1 << 2); |
712 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
713 | } | |
714 | } | |
715 | ||
716 | abuf->written = written; | |
717 | SEM_BRANCH_FINI (vpc); | |
718 | #undef FLD | |
719 | } | |
720 | NEXT (vpc); | |
721 | ||
722 | CASE (sem, INSN_BGTZ) : /* bgtz $src2,$disp16 */ | |
723 | { | |
724 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
725 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 726 | #define FLD(f) abuf->fields.sfmt_beq.f |
c906108c SS |
727 | int UNUSED written = 0; |
728 | IADDR UNUSED pc = abuf->addr; | |
729 | SEM_BRANCH_INIT | |
730 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
731 | ||
732 | if (GTSI (* FLD (i_src2), 0)) { | |
733 | { | |
734 | USI opval = FLD (i_disp16); | |
96baa820 | 735 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); |
c906108c SS |
736 | written |= (1 << 2); |
737 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
738 | } | |
739 | } | |
740 | ||
741 | abuf->written = written; | |
742 | SEM_BRANCH_FINI (vpc); | |
743 | #undef FLD | |
744 | } | |
745 | NEXT (vpc); | |
746 | ||
747 | CASE (sem, INSN_BLEZ) : /* blez $src2,$disp16 */ | |
748 | { | |
749 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
750 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 751 | #define FLD(f) abuf->fields.sfmt_beq.f |
c906108c SS |
752 | int UNUSED written = 0; |
753 | IADDR UNUSED pc = abuf->addr; | |
754 | SEM_BRANCH_INIT | |
755 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
756 | ||
757 | if (LESI (* FLD (i_src2), 0)) { | |
758 | { | |
759 | USI opval = FLD (i_disp16); | |
96baa820 | 760 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); |
c906108c SS |
761 | written |= (1 << 2); |
762 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
763 | } | |
764 | } | |
765 | ||
766 | abuf->written = written; | |
767 | SEM_BRANCH_FINI (vpc); | |
768 | #undef FLD | |
769 | } | |
770 | NEXT (vpc); | |
771 | ||
772 | CASE (sem, INSN_BLTZ) : /* bltz $src2,$disp16 */ | |
773 | { | |
774 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
775 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 776 | #define FLD(f) abuf->fields.sfmt_beq.f |
c906108c SS |
777 | int UNUSED written = 0; |
778 | IADDR UNUSED pc = abuf->addr; | |
779 | SEM_BRANCH_INIT | |
780 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
781 | ||
782 | if (LTSI (* FLD (i_src2), 0)) { | |
783 | { | |
784 | USI opval = FLD (i_disp16); | |
96baa820 | 785 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); |
c906108c SS |
786 | written |= (1 << 2); |
787 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
788 | } | |
789 | } | |
790 | ||
791 | abuf->written = written; | |
792 | SEM_BRANCH_FINI (vpc); | |
793 | #undef FLD | |
794 | } | |
795 | NEXT (vpc); | |
796 | ||
797 | CASE (sem, INSN_BNEZ) : /* bnez $src2,$disp16 */ | |
798 | { | |
799 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
800 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 801 | #define FLD(f) abuf->fields.sfmt_beq.f |
c906108c SS |
802 | int UNUSED written = 0; |
803 | IADDR UNUSED pc = abuf->addr; | |
804 | SEM_BRANCH_INIT | |
805 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
806 | ||
807 | if (NESI (* FLD (i_src2), 0)) { | |
808 | { | |
809 | USI opval = FLD (i_disp16); | |
96baa820 | 810 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); |
c906108c SS |
811 | written |= (1 << 2); |
812 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
813 | } | |
814 | } | |
815 | ||
816 | abuf->written = written; | |
817 | SEM_BRANCH_FINI (vpc); | |
818 | #undef FLD | |
819 | } | |
820 | NEXT (vpc); | |
821 | ||
822 | CASE (sem, INSN_BL8) : /* bl.s $disp8 */ | |
823 | { | |
824 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
825 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 826 | #define FLD(f) abuf->fields.sfmt_bl8.f |
c906108c SS |
827 | int UNUSED written = 0; |
828 | IADDR UNUSED pc = abuf->addr; | |
829 | SEM_BRANCH_INIT | |
830 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
831 | ||
7a292a7a | 832 | { |
c906108c SS |
833 | { |
834 | SI opval = ADDSI (ANDSI (pc, -4), 4); | |
835 | CPU (h_gr[((UINT) 14)]) = opval; | |
836 | TRACE_RESULT (current_cpu, abuf, "gr-14", 'x', opval); | |
837 | } | |
838 | { | |
839 | USI opval = FLD (i_disp8); | |
96baa820 | 840 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); |
c906108c SS |
841 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); |
842 | } | |
7a292a7a | 843 | } |
c906108c SS |
844 | |
845 | SEM_BRANCH_FINI (vpc); | |
846 | #undef FLD | |
847 | } | |
848 | NEXT (vpc); | |
849 | ||
850 | CASE (sem, INSN_BL24) : /* bl.l $disp24 */ | |
851 | { | |
852 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
853 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 854 | #define FLD(f) abuf->fields.sfmt_bl24.f |
c906108c SS |
855 | int UNUSED written = 0; |
856 | IADDR UNUSED pc = abuf->addr; | |
857 | SEM_BRANCH_INIT | |
858 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
859 | ||
7a292a7a | 860 | { |
c906108c SS |
861 | { |
862 | SI opval = ADDSI (pc, 4); | |
863 | CPU (h_gr[((UINT) 14)]) = opval; | |
864 | TRACE_RESULT (current_cpu, abuf, "gr-14", 'x', opval); | |
865 | } | |
866 | { | |
867 | USI opval = FLD (i_disp24); | |
96baa820 | 868 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); |
c906108c SS |
869 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); |
870 | } | |
7a292a7a | 871 | } |
c906108c SS |
872 | |
873 | SEM_BRANCH_FINI (vpc); | |
874 | #undef FLD | |
875 | } | |
876 | NEXT (vpc); | |
877 | ||
878 | CASE (sem, INSN_BNC8) : /* bnc.s $disp8 */ | |
879 | { | |
880 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
881 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 882 | #define FLD(f) abuf->fields.sfmt_bl8.f |
c906108c SS |
883 | int UNUSED written = 0; |
884 | IADDR UNUSED pc = abuf->addr; | |
885 | SEM_BRANCH_INIT | |
886 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
887 | ||
888 | if (NOTBI (CPU (h_cond))) { | |
889 | { | |
890 | USI opval = FLD (i_disp8); | |
96baa820 | 891 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); |
c906108c SS |
892 | written |= (1 << 2); |
893 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
894 | } | |
895 | } | |
896 | ||
897 | abuf->written = written; | |
898 | SEM_BRANCH_FINI (vpc); | |
899 | #undef FLD | |
900 | } | |
901 | NEXT (vpc); | |
902 | ||
903 | CASE (sem, INSN_BNC24) : /* bnc.l $disp24 */ | |
904 | { | |
905 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
906 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 907 | #define FLD(f) abuf->fields.sfmt_bl24.f |
c906108c SS |
908 | int UNUSED written = 0; |
909 | IADDR UNUSED pc = abuf->addr; | |
910 | SEM_BRANCH_INIT | |
911 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
912 | ||
913 | if (NOTBI (CPU (h_cond))) { | |
914 | { | |
915 | USI opval = FLD (i_disp24); | |
96baa820 | 916 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); |
c906108c SS |
917 | written |= (1 << 2); |
918 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
919 | } | |
920 | } | |
921 | ||
922 | abuf->written = written; | |
923 | SEM_BRANCH_FINI (vpc); | |
924 | #undef FLD | |
925 | } | |
926 | NEXT (vpc); | |
927 | ||
928 | CASE (sem, INSN_BNE) : /* bne $src1,$src2,$disp16 */ | |
929 | { | |
930 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
931 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 932 | #define FLD(f) abuf->fields.sfmt_beq.f |
c906108c SS |
933 | int UNUSED written = 0; |
934 | IADDR UNUSED pc = abuf->addr; | |
935 | SEM_BRANCH_INIT | |
936 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
937 | ||
938 | if (NESI (* FLD (i_src1), * FLD (i_src2))) { | |
939 | { | |
940 | USI opval = FLD (i_disp16); | |
96baa820 | 941 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); |
c906108c SS |
942 | written |= (1 << 3); |
943 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
944 | } | |
945 | } | |
946 | ||
947 | abuf->written = written; | |
948 | SEM_BRANCH_FINI (vpc); | |
949 | #undef FLD | |
950 | } | |
951 | NEXT (vpc); | |
952 | ||
953 | CASE (sem, INSN_BRA8) : /* bra.s $disp8 */ | |
954 | { | |
955 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
956 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 957 | #define FLD(f) abuf->fields.sfmt_bl8.f |
c906108c SS |
958 | int UNUSED written = 0; |
959 | IADDR UNUSED pc = abuf->addr; | |
960 | SEM_BRANCH_INIT | |
961 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
962 | ||
963 | { | |
964 | USI opval = FLD (i_disp8); | |
96baa820 | 965 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); |
c906108c SS |
966 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); |
967 | } | |
968 | ||
969 | SEM_BRANCH_FINI (vpc); | |
970 | #undef FLD | |
971 | } | |
972 | NEXT (vpc); | |
973 | ||
974 | CASE (sem, INSN_BRA24) : /* bra.l $disp24 */ | |
975 | { | |
976 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
977 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 978 | #define FLD(f) abuf->fields.sfmt_bl24.f |
c906108c SS |
979 | int UNUSED written = 0; |
980 | IADDR UNUSED pc = abuf->addr; | |
981 | SEM_BRANCH_INIT | |
982 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
983 | ||
984 | { | |
985 | USI opval = FLD (i_disp24); | |
96baa820 | 986 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); |
c906108c SS |
987 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); |
988 | } | |
989 | ||
990 | SEM_BRANCH_FINI (vpc); | |
991 | #undef FLD | |
992 | } | |
993 | NEXT (vpc); | |
994 | ||
995 | CASE (sem, INSN_CMP) : /* cmp $src1,$src2 */ | |
996 | { | |
997 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
998 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 999 | #define FLD(f) abuf->fields.sfmt_st_plus.f |
c906108c SS |
1000 | int UNUSED written = 0; |
1001 | IADDR UNUSED pc = abuf->addr; | |
1002 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1003 | ||
1004 | { | |
1005 | BI opval = LTSI (* FLD (i_src1), * FLD (i_src2)); | |
1006 | CPU (h_cond) = opval; | |
1007 | TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval); | |
1008 | } | |
1009 | ||
1010 | #undef FLD | |
1011 | } | |
1012 | NEXT (vpc); | |
1013 | ||
1014 | CASE (sem, INSN_CMPI) : /* cmpi $src2,$simm16 */ | |
1015 | { | |
1016 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1017 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 1018 | #define FLD(f) abuf->fields.sfmt_st_d.f |
c906108c SS |
1019 | int UNUSED written = 0; |
1020 | IADDR UNUSED pc = abuf->addr; | |
1021 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1022 | ||
1023 | { | |
1024 | BI opval = LTSI (* FLD (i_src2), FLD (f_simm16)); | |
1025 | CPU (h_cond) = opval; | |
1026 | TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval); | |
1027 | } | |
1028 | ||
1029 | #undef FLD | |
1030 | } | |
1031 | NEXT (vpc); | |
1032 | ||
1033 | CASE (sem, INSN_CMPU) : /* cmpu $src1,$src2 */ | |
1034 | { | |
1035 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1036 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 1037 | #define FLD(f) abuf->fields.sfmt_st_plus.f |
c906108c SS |
1038 | int UNUSED written = 0; |
1039 | IADDR UNUSED pc = abuf->addr; | |
1040 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1041 | ||
1042 | { | |
1043 | BI opval = LTUSI (* FLD (i_src1), * FLD (i_src2)); | |
1044 | CPU (h_cond) = opval; | |
1045 | TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval); | |
1046 | } | |
1047 | ||
1048 | #undef FLD | |
1049 | } | |
1050 | NEXT (vpc); | |
1051 | ||
1052 | CASE (sem, INSN_CMPUI) : /* cmpui $src2,$simm16 */ | |
1053 | { | |
1054 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1055 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 1056 | #define FLD(f) abuf->fields.sfmt_st_d.f |
c906108c SS |
1057 | int UNUSED written = 0; |
1058 | IADDR UNUSED pc = abuf->addr; | |
1059 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1060 | ||
1061 | { | |
1062 | BI opval = LTUSI (* FLD (i_src2), FLD (f_simm16)); | |
1063 | CPU (h_cond) = opval; | |
1064 | TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval); | |
1065 | } | |
1066 | ||
1067 | #undef FLD | |
1068 | } | |
1069 | NEXT (vpc); | |
1070 | ||
1071 | CASE (sem, INSN_DIV) : /* div $dr,$sr */ | |
1072 | { | |
1073 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1074 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 1075 | #define FLD(f) abuf->fields.sfmt_add.f |
c906108c SS |
1076 | int UNUSED written = 0; |
1077 | IADDR UNUSED pc = abuf->addr; | |
1078 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1079 | ||
1080 | if (NESI (* FLD (i_sr), 0)) { | |
1081 | { | |
1082 | SI opval = DIVSI (* FLD (i_dr), * FLD (i_sr)); | |
1083 | * FLD (i_dr) = opval; | |
1084 | written |= (1 << 2); | |
1085 | TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); | |
1086 | } | |
1087 | } | |
1088 | ||
1089 | abuf->written = written; | |
1090 | #undef FLD | |
1091 | } | |
1092 | NEXT (vpc); | |
1093 | ||
1094 | CASE (sem, INSN_DIVU) : /* divu $dr,$sr */ | |
1095 | { | |
1096 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1097 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 1098 | #define FLD(f) abuf->fields.sfmt_add.f |
c906108c SS |
1099 | int UNUSED written = 0; |
1100 | IADDR UNUSED pc = abuf->addr; | |
1101 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1102 | ||
1103 | if (NESI (* FLD (i_sr), 0)) { | |
1104 | { | |
1105 | SI opval = UDIVSI (* FLD (i_dr), * FLD (i_sr)); | |
1106 | * FLD (i_dr) = opval; | |
1107 | written |= (1 << 2); | |
1108 | TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); | |
1109 | } | |
1110 | } | |
1111 | ||
1112 | abuf->written = written; | |
1113 | #undef FLD | |
1114 | } | |
1115 | NEXT (vpc); | |
1116 | ||
1117 | CASE (sem, INSN_REM) : /* rem $dr,$sr */ | |
1118 | { | |
1119 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1120 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 1121 | #define FLD(f) abuf->fields.sfmt_add.f |
c906108c SS |
1122 | int UNUSED written = 0; |
1123 | IADDR UNUSED pc = abuf->addr; | |
1124 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1125 | ||
1126 | if (NESI (* FLD (i_sr), 0)) { | |
1127 | { | |
1128 | SI opval = MODSI (* FLD (i_dr), * FLD (i_sr)); | |
1129 | * FLD (i_dr) = opval; | |
1130 | written |= (1 << 2); | |
1131 | TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); | |
1132 | } | |
1133 | } | |
1134 | ||
1135 | abuf->written = written; | |
1136 | #undef FLD | |
1137 | } | |
1138 | NEXT (vpc); | |
1139 | ||
1140 | CASE (sem, INSN_REMU) : /* remu $dr,$sr */ | |
1141 | { | |
1142 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1143 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 1144 | #define FLD(f) abuf->fields.sfmt_add.f |
c906108c SS |
1145 | int UNUSED written = 0; |
1146 | IADDR UNUSED pc = abuf->addr; | |
1147 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1148 | ||
1149 | if (NESI (* FLD (i_sr), 0)) { | |
1150 | { | |
1151 | SI opval = UMODSI (* FLD (i_dr), * FLD (i_sr)); | |
1152 | * FLD (i_dr) = opval; | |
1153 | written |= (1 << 2); | |
1154 | TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); | |
1155 | } | |
1156 | } | |
1157 | ||
1158 | abuf->written = written; | |
1159 | #undef FLD | |
1160 | } | |
1161 | NEXT (vpc); | |
1162 | ||
1163 | CASE (sem, INSN_JL) : /* jl $sr */ | |
1164 | { | |
1165 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1166 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 1167 | #define FLD(f) abuf->fields.sfmt_jl.f |
c906108c SS |
1168 | int UNUSED written = 0; |
1169 | IADDR UNUSED pc = abuf->addr; | |
1170 | SEM_BRANCH_INIT | |
1171 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1172 | ||
7a292a7a SS |
1173 | { |
1174 | SI temp0;USI temp1; | |
c906108c SS |
1175 | temp0 = ADDSI (ANDSI (pc, -4), 4); |
1176 | temp1 = ANDSI (* FLD (i_sr), -4); | |
1177 | { | |
1178 | SI opval = temp0; | |
1179 | CPU (h_gr[((UINT) 14)]) = opval; | |
1180 | TRACE_RESULT (current_cpu, abuf, "gr-14", 'x', opval); | |
1181 | } | |
1182 | { | |
1183 | USI opval = temp1; | |
1184 | SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); | |
1185 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
1186 | } | |
7a292a7a | 1187 | } |
c906108c SS |
1188 | |
1189 | SEM_BRANCH_FINI (vpc); | |
1190 | #undef FLD | |
1191 | } | |
1192 | NEXT (vpc); | |
1193 | ||
1194 | CASE (sem, INSN_JMP) : /* jmp $sr */ | |
1195 | { | |
1196 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1197 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
de8f5985 | 1198 | #define FLD(f) abuf->fields.sfmt_jl.f |
c906108c SS |
1199 | int UNUSED written = 0; |
1200 | IADDR UNUSED pc = abuf->addr; | |
1201 | SEM_BRANCH_INIT | |
1202 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1203 | ||
1204 | { | |
1205 | USI opval = ANDSI (* FLD (i_sr), -4); | |
1206 | SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); | |
1207 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
1208 | } | |
1209 | ||
1210 | SEM_BRANCH_FINI (vpc); | |
1211 | #undef FLD | |
1212 | } | |
1213 | NEXT (vpc); | |
1214 | ||
1215 | CASE (sem, INSN_LD) : /* ld $dr,@$sr */ | |
1216 | { | |
1217 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1218 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 1219 | #define FLD(f) abuf->fields.sfmt_ld_plus.f |
c906108c SS |
1220 | int UNUSED written = 0; |
1221 | IADDR UNUSED pc = abuf->addr; | |
1222 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1223 | ||
1224 | { | |
1225 | SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr)); | |
1226 | * FLD (i_dr) = opval; | |
1227 | TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); | |
1228 | } | |
1229 | ||
1230 | #undef FLD | |
1231 | } | |
1232 | NEXT (vpc); | |
1233 | ||
1234 | CASE (sem, INSN_LD_D) : /* ld $dr,@($slo16,$sr) */ | |
1235 | { | |
1236 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1237 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 1238 | #define FLD(f) abuf->fields.sfmt_add3.f |
c906108c SS |
1239 | int UNUSED written = 0; |
1240 | IADDR UNUSED pc = abuf->addr; | |
1241 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1242 | ||
1243 | { | |
1244 | SI opval = GETMEMSI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))); | |
1245 | * FLD (i_dr) = opval; | |
1246 | TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); | |
1247 | } | |
1248 | ||
1249 | #undef FLD | |
1250 | } | |
1251 | NEXT (vpc); | |
1252 | ||
1253 | CASE (sem, INSN_LDB) : /* ldb $dr,@$sr */ | |
1254 | { | |
1255 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1256 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 1257 | #define FLD(f) abuf->fields.sfmt_ld_plus.f |
c906108c SS |
1258 | int UNUSED written = 0; |
1259 | IADDR UNUSED pc = abuf->addr; | |
1260 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1261 | ||
1262 | { | |
1263 | SI opval = EXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr))); | |
1264 | * FLD (i_dr) = opval; | |
1265 | TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); | |
1266 | } | |
1267 | ||
1268 | #undef FLD | |
1269 | } | |
1270 | NEXT (vpc); | |
1271 | ||
1272 | CASE (sem, INSN_LDB_D) : /* ldb $dr,@($slo16,$sr) */ | |
1273 | { | |
1274 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1275 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 1276 | #define FLD(f) abuf->fields.sfmt_add3.f |
c906108c SS |
1277 | int UNUSED written = 0; |
1278 | IADDR UNUSED pc = abuf->addr; | |
1279 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1280 | ||
1281 | { | |
1282 | SI opval = EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)))); | |
1283 | * FLD (i_dr) = opval; | |
1284 | TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); | |
1285 | } | |
1286 | ||
1287 | #undef FLD | |
1288 | } | |
1289 | NEXT (vpc); | |
1290 | ||
1291 | CASE (sem, INSN_LDH) : /* ldh $dr,@$sr */ | |
1292 | { | |
1293 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1294 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 1295 | #define FLD(f) abuf->fields.sfmt_ld_plus.f |
c906108c SS |
1296 | int UNUSED written = 0; |
1297 | IADDR UNUSED pc = abuf->addr; | |
1298 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1299 | ||
1300 | { | |
1301 | SI opval = EXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr))); | |
1302 | * FLD (i_dr) = opval; | |
1303 | TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); | |
1304 | } | |
1305 | ||
1306 | #undef FLD | |
1307 | } | |
1308 | NEXT (vpc); | |
1309 | ||
1310 | CASE (sem, INSN_LDH_D) : /* ldh $dr,@($slo16,$sr) */ | |
1311 | { | |
1312 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1313 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 1314 | #define FLD(f) abuf->fields.sfmt_add3.f |
c906108c SS |
1315 | int UNUSED written = 0; |
1316 | IADDR UNUSED pc = abuf->addr; | |
1317 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1318 | ||
1319 | { | |
1320 | SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)))); | |
1321 | * FLD (i_dr) = opval; | |
1322 | TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); | |
1323 | } | |
1324 | ||
1325 | #undef FLD | |
1326 | } | |
1327 | NEXT (vpc); | |
1328 | ||
1329 | CASE (sem, INSN_LDUB) : /* ldub $dr,@$sr */ | |
1330 | { | |
1331 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1332 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 1333 | #define FLD(f) abuf->fields.sfmt_ld_plus.f |
c906108c SS |
1334 | int UNUSED written = 0; |
1335 | IADDR UNUSED pc = abuf->addr; | |
1336 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1337 | ||
1338 | { | |
1339 | SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr))); | |
1340 | * FLD (i_dr) = opval; | |
1341 | TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); | |
1342 | } | |
1343 | ||
1344 | #undef FLD | |
1345 | } | |
1346 | NEXT (vpc); | |
1347 | ||
1348 | CASE (sem, INSN_LDUB_D) : /* ldub $dr,@($slo16,$sr) */ | |
1349 | { | |
1350 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1351 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 1352 | #define FLD(f) abuf->fields.sfmt_add3.f |
c906108c SS |
1353 | int UNUSED written = 0; |
1354 | IADDR UNUSED pc = abuf->addr; | |
1355 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1356 | ||
1357 | { | |
1358 | SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)))); | |
1359 | * FLD (i_dr) = opval; | |
1360 | TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); | |
1361 | } | |
1362 | ||
1363 | #undef FLD | |
1364 | } | |
1365 | NEXT (vpc); | |
1366 | ||
1367 | CASE (sem, INSN_LDUH) : /* lduh $dr,@$sr */ | |
1368 | { | |
1369 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1370 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 1371 | #define FLD(f) abuf->fields.sfmt_ld_plus.f |
c906108c SS |
1372 | int UNUSED written = 0; |
1373 | IADDR UNUSED pc = abuf->addr; | |
1374 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1375 | ||
1376 | { | |
1377 | SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr))); | |
1378 | * FLD (i_dr) = opval; | |
1379 | TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); | |
1380 | } | |
1381 | ||
1382 | #undef FLD | |
1383 | } | |
1384 | NEXT (vpc); | |
1385 | ||
1386 | CASE (sem, INSN_LDUH_D) : /* lduh $dr,@($slo16,$sr) */ | |
1387 | { | |
1388 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1389 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 1390 | #define FLD(f) abuf->fields.sfmt_add3.f |
c906108c SS |
1391 | int UNUSED written = 0; |
1392 | IADDR UNUSED pc = abuf->addr; | |
1393 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1394 | ||
1395 | { | |
1396 | SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)))); | |
1397 | * FLD (i_dr) = opval; | |
1398 | TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); | |
1399 | } | |
1400 | ||
1401 | #undef FLD | |
1402 | } | |
1403 | NEXT (vpc); | |
1404 | ||
1405 | CASE (sem, INSN_LD_PLUS) : /* ld $dr,@$sr+ */ | |
1406 | { | |
1407 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1408 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 1409 | #define FLD(f) abuf->fields.sfmt_ld_plus.f |
c906108c SS |
1410 | int UNUSED written = 0; |
1411 | IADDR UNUSED pc = abuf->addr; | |
1412 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1413 | ||
7a292a7a SS |
1414 | { |
1415 | SI temp0;SI temp1; | |
c906108c SS |
1416 | temp0 = GETMEMSI (current_cpu, pc, * FLD (i_sr)); |
1417 | temp1 = ADDSI (* FLD (i_sr), 4); | |
1418 | { | |
1419 | SI opval = temp0; | |
1420 | * FLD (i_dr) = opval; | |
1421 | TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); | |
1422 | } | |
1423 | { | |
1424 | SI opval = temp1; | |
1425 | * FLD (i_sr) = opval; | |
1426 | TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval); | |
1427 | } | |
7a292a7a | 1428 | } |
c906108c SS |
1429 | |
1430 | #undef FLD | |
1431 | } | |
1432 | NEXT (vpc); | |
1433 | ||
1434 | CASE (sem, INSN_LD24) : /* ld24 $dr,$uimm24 */ | |
1435 | { | |
1436 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1437 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 1438 | #define FLD(f) abuf->fields.sfmt_ld24.f |
c906108c SS |
1439 | int UNUSED written = 0; |
1440 | IADDR UNUSED pc = abuf->addr; | |
1441 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1442 | ||
1443 | { | |
1444 | SI opval = FLD (i_uimm24); | |
1445 | * FLD (i_dr) = opval; | |
1446 | TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); | |
1447 | } | |
1448 | ||
1449 | #undef FLD | |
1450 | } | |
1451 | NEXT (vpc); | |
1452 | ||
1453 | CASE (sem, INSN_LDI8) : /* ldi8 $dr,$simm8 */ | |
1454 | { | |
1455 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1456 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 1457 | #define FLD(f) abuf->fields.sfmt_addi.f |
c906108c SS |
1458 | int UNUSED written = 0; |
1459 | IADDR UNUSED pc = abuf->addr; | |
1460 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1461 | ||
1462 | { | |
1463 | SI opval = FLD (f_simm8); | |
1464 | * FLD (i_dr) = opval; | |
1465 | TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); | |
1466 | } | |
1467 | ||
1468 | #undef FLD | |
1469 | } | |
1470 | NEXT (vpc); | |
1471 | ||
1472 | CASE (sem, INSN_LDI16) : /* ldi16 $dr,$hash$slo16 */ | |
1473 | { | |
1474 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1475 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 1476 | #define FLD(f) abuf->fields.sfmt_add3.f |
c906108c SS |
1477 | int UNUSED written = 0; |
1478 | IADDR UNUSED pc = abuf->addr; | |
1479 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1480 | ||
1481 | { | |
1482 | SI opval = FLD (f_simm16); | |
1483 | * FLD (i_dr) = opval; | |
1484 | TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); | |
1485 | } | |
1486 | ||
1487 | #undef FLD | |
1488 | } | |
1489 | NEXT (vpc); | |
1490 | ||
1491 | CASE (sem, INSN_LOCK) : /* lock $dr,@$sr */ | |
1492 | { | |
1493 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1494 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 1495 | #define FLD(f) abuf->fields.sfmt_ld_plus.f |
c906108c SS |
1496 | int UNUSED written = 0; |
1497 | IADDR UNUSED pc = abuf->addr; | |
1498 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1499 | ||
7a292a7a | 1500 | { |
c906108c SS |
1501 | { |
1502 | BI opval = 1; | |
1503 | CPU (h_lock) = opval; | |
7a292a7a | 1504 | TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval); |
c906108c SS |
1505 | } |
1506 | { | |
1507 | SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr)); | |
1508 | * FLD (i_dr) = opval; | |
1509 | TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); | |
1510 | } | |
7a292a7a | 1511 | } |
c906108c SS |
1512 | |
1513 | #undef FLD | |
1514 | } | |
1515 | NEXT (vpc); | |
1516 | ||
1517 | CASE (sem, INSN_MACHI) : /* machi $src1,$src2 */ | |
1518 | { | |
1519 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1520 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 1521 | #define FLD(f) abuf->fields.sfmt_st_plus.f |
c906108c SS |
1522 | int UNUSED written = 0; |
1523 | IADDR UNUSED pc = abuf->addr; | |
1524 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1525 | ||
1526 | { | |
1527 | DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUM (), MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))), 8), 8); | |
1528 | SET_H_ACCUM (opval); | |
1529 | TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval); | |
1530 | } | |
1531 | ||
1532 | #undef FLD | |
1533 | } | |
1534 | NEXT (vpc); | |
1535 | ||
1536 | CASE (sem, INSN_MACLO) : /* maclo $src1,$src2 */ | |
1537 | { | |
1538 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1539 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 1540 | #define FLD(f) abuf->fields.sfmt_st_plus.f |
c906108c SS |
1541 | int UNUSED written = 0; |
1542 | IADDR UNUSED pc = abuf->addr; | |
1543 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1544 | ||
1545 | { | |
1546 | DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUM (), MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))), 8), 8); | |
1547 | SET_H_ACCUM (opval); | |
1548 | TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval); | |
1549 | } | |
1550 | ||
1551 | #undef FLD | |
1552 | } | |
1553 | NEXT (vpc); | |
1554 | ||
1555 | CASE (sem, INSN_MACWHI) : /* macwhi $src1,$src2 */ | |
1556 | { | |
1557 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1558 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 1559 | #define FLD(f) abuf->fields.sfmt_st_plus.f |
c906108c SS |
1560 | int UNUSED written = 0; |
1561 | IADDR UNUSED pc = abuf->addr; | |
1562 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1563 | ||
1564 | { | |
1565 | DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUM (), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))), 8), 8); | |
1566 | SET_H_ACCUM (opval); | |
1567 | TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval); | |
1568 | } | |
1569 | ||
1570 | #undef FLD | |
1571 | } | |
1572 | NEXT (vpc); | |
1573 | ||
1574 | CASE (sem, INSN_MACWLO) : /* macwlo $src1,$src2 */ | |
1575 | { | |
1576 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1577 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 1578 | #define FLD(f) abuf->fields.sfmt_st_plus.f |
c906108c SS |
1579 | int UNUSED written = 0; |
1580 | IADDR UNUSED pc = abuf->addr; | |
1581 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1582 | ||
1583 | { | |
1584 | DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUM (), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))), 8), 8); | |
1585 | SET_H_ACCUM (opval); | |
1586 | TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval); | |
1587 | } | |
1588 | ||
1589 | #undef FLD | |
1590 | } | |
1591 | NEXT (vpc); | |
1592 | ||
1593 | CASE (sem, INSN_MUL) : /* mul $dr,$sr */ | |
1594 | { | |
1595 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1596 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 1597 | #define FLD(f) abuf->fields.sfmt_add.f |
c906108c SS |
1598 | int UNUSED written = 0; |
1599 | IADDR UNUSED pc = abuf->addr; | |
1600 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1601 | ||
1602 | { | |
1603 | SI opval = MULSI (* FLD (i_dr), * FLD (i_sr)); | |
1604 | * FLD (i_dr) = opval; | |
1605 | TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); | |
1606 | } | |
1607 | ||
1608 | #undef FLD | |
1609 | } | |
1610 | NEXT (vpc); | |
1611 | ||
1612 | CASE (sem, INSN_MULHI) : /* mulhi $src1,$src2 */ | |
1613 | { | |
1614 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1615 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 1616 | #define FLD(f) abuf->fields.sfmt_st_plus.f |
c906108c SS |
1617 | int UNUSED written = 0; |
1618 | IADDR UNUSED pc = abuf->addr; | |
1619 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1620 | ||
1621 | { | |
1622 | DI opval = SRADI (SLLDI (MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))), 16), 16); | |
1623 | SET_H_ACCUM (opval); | |
1624 | TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval); | |
1625 | } | |
1626 | ||
1627 | #undef FLD | |
1628 | } | |
1629 | NEXT (vpc); | |
1630 | ||
1631 | CASE (sem, INSN_MULLO) : /* mullo $src1,$src2 */ | |
1632 | { | |
1633 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1634 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 1635 | #define FLD(f) abuf->fields.sfmt_st_plus.f |
c906108c SS |
1636 | int UNUSED written = 0; |
1637 | IADDR UNUSED pc = abuf->addr; | |
1638 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1639 | ||
1640 | { | |
1641 | DI opval = SRADI (SLLDI (MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 16), 16); | |
1642 | SET_H_ACCUM (opval); | |
1643 | TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval); | |
1644 | } | |
1645 | ||
1646 | #undef FLD | |
1647 | } | |
1648 | NEXT (vpc); | |
1649 | ||
1650 | CASE (sem, INSN_MULWHI) : /* mulwhi $src1,$src2 */ | |
1651 | { | |
1652 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1653 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 1654 | #define FLD(f) abuf->fields.sfmt_st_plus.f |
c906108c SS |
1655 | int UNUSED written = 0; |
1656 | IADDR UNUSED pc = abuf->addr; | |
1657 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1658 | ||
1659 | { | |
1660 | DI opval = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))), 8), 8); | |
1661 | SET_H_ACCUM (opval); | |
1662 | TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval); | |
1663 | } | |
1664 | ||
1665 | #undef FLD | |
1666 | } | |
1667 | NEXT (vpc); | |
1668 | ||
1669 | CASE (sem, INSN_MULWLO) : /* mulwlo $src1,$src2 */ | |
1670 | { | |
1671 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1672 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 1673 | #define FLD(f) abuf->fields.sfmt_st_plus.f |
c906108c SS |
1674 | int UNUSED written = 0; |
1675 | IADDR UNUSED pc = abuf->addr; | |
1676 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1677 | ||
1678 | { | |
1679 | DI opval = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 8), 8); | |
1680 | SET_H_ACCUM (opval); | |
1681 | TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval); | |
1682 | } | |
1683 | ||
1684 | #undef FLD | |
1685 | } | |
1686 | NEXT (vpc); | |
1687 | ||
1688 | CASE (sem, INSN_MV) : /* mv $dr,$sr */ | |
1689 | { | |
1690 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1691 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 1692 | #define FLD(f) abuf->fields.sfmt_ld_plus.f |
c906108c SS |
1693 | int UNUSED written = 0; |
1694 | IADDR UNUSED pc = abuf->addr; | |
1695 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1696 | ||
1697 | { | |
1698 | SI opval = * FLD (i_sr); | |
1699 | * FLD (i_dr) = opval; | |
1700 | TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); | |
1701 | } | |
1702 | ||
1703 | #undef FLD | |
1704 | } | |
1705 | NEXT (vpc); | |
1706 | ||
1707 | CASE (sem, INSN_MVFACHI) : /* mvfachi $dr */ | |
1708 | { | |
1709 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1710 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 1711 | #define FLD(f) abuf->fields.sfmt_seth.f |
c906108c SS |
1712 | int UNUSED written = 0; |
1713 | IADDR UNUSED pc = abuf->addr; | |
1714 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1715 | ||
1716 | { | |
1717 | SI opval = TRUNCDISI (SRADI (GET_H_ACCUM (), 32)); | |
1718 | * FLD (i_dr) = opval; | |
1719 | TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); | |
1720 | } | |
1721 | ||
1722 | #undef FLD | |
1723 | } | |
1724 | NEXT (vpc); | |
1725 | ||
1726 | CASE (sem, INSN_MVFACLO) : /* mvfaclo $dr */ | |
1727 | { | |
1728 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1729 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 1730 | #define FLD(f) abuf->fields.sfmt_seth.f |
c906108c SS |
1731 | int UNUSED written = 0; |
1732 | IADDR UNUSED pc = abuf->addr; | |
1733 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1734 | ||
1735 | { | |
1736 | SI opval = TRUNCDISI (GET_H_ACCUM ()); | |
1737 | * FLD (i_dr) = opval; | |
1738 | TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); | |
1739 | } | |
1740 | ||
1741 | #undef FLD | |
1742 | } | |
1743 | NEXT (vpc); | |
1744 | ||
1745 | CASE (sem, INSN_MVFACMI) : /* mvfacmi $dr */ | |
1746 | { | |
1747 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1748 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 1749 | #define FLD(f) abuf->fields.sfmt_seth.f |
c906108c SS |
1750 | int UNUSED written = 0; |
1751 | IADDR UNUSED pc = abuf->addr; | |
1752 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1753 | ||
1754 | { | |
1755 | SI opval = TRUNCDISI (SRADI (GET_H_ACCUM (), 16)); | |
1756 | * FLD (i_dr) = opval; | |
1757 | TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); | |
1758 | } | |
1759 | ||
1760 | #undef FLD | |
1761 | } | |
1762 | NEXT (vpc); | |
1763 | ||
1764 | CASE (sem, INSN_MVFC) : /* mvfc $dr,$scr */ | |
1765 | { | |
1766 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1767 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
de8f5985 | 1768 | #define FLD(f) abuf->fields.sfmt_ld_plus.f |
c906108c SS |
1769 | int UNUSED written = 0; |
1770 | IADDR UNUSED pc = abuf->addr; | |
1771 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1772 | ||
1773 | { | |
1774 | SI opval = GET_H_CR (FLD (f_r2)); | |
1775 | * FLD (i_dr) = opval; | |
1776 | TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); | |
1777 | } | |
1778 | ||
1779 | #undef FLD | |
1780 | } | |
1781 | NEXT (vpc); | |
1782 | ||
1783 | CASE (sem, INSN_MVTACHI) : /* mvtachi $src1 */ | |
1784 | { | |
1785 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1786 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 1787 | #define FLD(f) abuf->fields.sfmt_st_plus.f |
c906108c SS |
1788 | int UNUSED written = 0; |
1789 | IADDR UNUSED pc = abuf->addr; | |
1790 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1791 | ||
1792 | { | |
1793 | DI opval = ORDI (ANDDI (GET_H_ACCUM (), MAKEDI (0, 0xffffffff)), SLLDI (EXTSIDI (* FLD (i_src1)), 32)); | |
1794 | SET_H_ACCUM (opval); | |
1795 | TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval); | |
1796 | } | |
1797 | ||
1798 | #undef FLD | |
1799 | } | |
1800 | NEXT (vpc); | |
1801 | ||
1802 | CASE (sem, INSN_MVTACLO) : /* mvtaclo $src1 */ | |
1803 | { | |
1804 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1805 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 1806 | #define FLD(f) abuf->fields.sfmt_st_plus.f |
c906108c SS |
1807 | int UNUSED written = 0; |
1808 | IADDR UNUSED pc = abuf->addr; | |
1809 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1810 | ||
1811 | { | |
1812 | DI opval = ORDI (ANDDI (GET_H_ACCUM (), MAKEDI (0xffffffff, 0)), ZEXTSIDI (* FLD (i_src1))); | |
1813 | SET_H_ACCUM (opval); | |
1814 | TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval); | |
1815 | } | |
1816 | ||
1817 | #undef FLD | |
1818 | } | |
1819 | NEXT (vpc); | |
1820 | ||
1821 | CASE (sem, INSN_MVTC) : /* mvtc $sr,$dcr */ | |
1822 | { | |
1823 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1824 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
de8f5985 | 1825 | #define FLD(f) abuf->fields.sfmt_ld_plus.f |
c906108c SS |
1826 | int UNUSED written = 0; |
1827 | IADDR UNUSED pc = abuf->addr; | |
1828 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1829 | ||
1830 | { | |
1831 | USI opval = * FLD (i_sr); | |
1832 | SET_H_CR (FLD (f_r1), opval); | |
1833 | TRACE_RESULT (current_cpu, abuf, "dcr", 'x', opval); | |
1834 | } | |
1835 | ||
1836 | #undef FLD | |
1837 | } | |
1838 | NEXT (vpc); | |
1839 | ||
1840 | CASE (sem, INSN_NEG) : /* neg $dr,$sr */ | |
1841 | { | |
1842 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1843 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 1844 | #define FLD(f) abuf->fields.sfmt_ld_plus.f |
c906108c SS |
1845 | int UNUSED written = 0; |
1846 | IADDR UNUSED pc = abuf->addr; | |
1847 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1848 | ||
1849 | { | |
1850 | SI opval = NEGSI (* FLD (i_sr)); | |
1851 | * FLD (i_dr) = opval; | |
1852 | TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); | |
1853 | } | |
1854 | ||
1855 | #undef FLD | |
1856 | } | |
1857 | NEXT (vpc); | |
1858 | ||
1859 | CASE (sem, INSN_NOP) : /* nop */ | |
1860 | { | |
1861 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1862 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 1863 | #define FLD(f) abuf->fields.fmt_empty.f |
c906108c SS |
1864 | int UNUSED written = 0; |
1865 | IADDR UNUSED pc = abuf->addr; | |
1866 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1867 | ||
1868 | PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr); | |
1869 | ||
1870 | #undef FLD | |
1871 | } | |
1872 | NEXT (vpc); | |
1873 | ||
1874 | CASE (sem, INSN_NOT) : /* not $dr,$sr */ | |
1875 | { | |
1876 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1877 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 1878 | #define FLD(f) abuf->fields.sfmt_ld_plus.f |
c906108c SS |
1879 | int UNUSED written = 0; |
1880 | IADDR UNUSED pc = abuf->addr; | |
1881 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1882 | ||
1883 | { | |
1884 | SI opval = INVSI (* FLD (i_sr)); | |
1885 | * FLD (i_dr) = opval; | |
1886 | TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); | |
1887 | } | |
1888 | ||
1889 | #undef FLD | |
1890 | } | |
1891 | NEXT (vpc); | |
1892 | ||
1893 | CASE (sem, INSN_RAC) : /* rac */ | |
1894 | { | |
1895 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1896 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 1897 | #define FLD(f) abuf->fields.fmt_empty.f |
c906108c SS |
1898 | int UNUSED written = 0; |
1899 | IADDR UNUSED pc = abuf->addr; | |
1900 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1901 | ||
7a292a7a | 1902 | { |
c906108c SS |
1903 | DI tmp_tmp1; |
1904 | tmp_tmp1 = SLLDI (GET_H_ACCUM (), 1); | |
1905 | tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 32768)); | |
1906 | { | |
1907 | DI opval = (GTDI (tmp_tmp1, MAKEDI (32767, 0xffff0000))) ? (MAKEDI (32767, 0xffff0000)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0xffff0000))); | |
1908 | SET_H_ACCUM (opval); | |
1909 | TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval); | |
1910 | } | |
7a292a7a | 1911 | } |
c906108c SS |
1912 | |
1913 | #undef FLD | |
1914 | } | |
1915 | NEXT (vpc); | |
1916 | ||
1917 | CASE (sem, INSN_RACH) : /* rach */ | |
1918 | { | |
1919 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1920 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 1921 | #define FLD(f) abuf->fields.fmt_empty.f |
c906108c SS |
1922 | int UNUSED written = 0; |
1923 | IADDR UNUSED pc = abuf->addr; | |
1924 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1925 | ||
7a292a7a | 1926 | { |
c906108c SS |
1927 | DI tmp_tmp1; |
1928 | tmp_tmp1 = ANDDI (GET_H_ACCUM (), MAKEDI (16777215, 0xffffffff)); | |
1929 | if (ANDIF (GEDI (tmp_tmp1, MAKEDI (16383, 0x80000000)), LEDI (tmp_tmp1, MAKEDI (8388607, 0xffffffff)))) { | |
1930 | tmp_tmp1 = MAKEDI (16383, 0x80000000); | |
1931 | } else { | |
1932 | if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (16760832, 0)))) { | |
1933 | tmp_tmp1 = MAKEDI (16760832, 0); | |
1934 | } else { | |
1935 | tmp_tmp1 = ANDDI (ADDDI (GET_H_ACCUM (), MAKEDI (0, 1073741824)), MAKEDI (0xffffffff, 0x80000000)); | |
1936 | } | |
1937 | } | |
1938 | tmp_tmp1 = SLLDI (tmp_tmp1, 1); | |
1939 | { | |
1940 | DI opval = SRADI (SLLDI (tmp_tmp1, 7), 7); | |
1941 | SET_H_ACCUM (opval); | |
1942 | TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval); | |
1943 | } | |
7a292a7a | 1944 | } |
c906108c SS |
1945 | |
1946 | #undef FLD | |
1947 | } | |
1948 | NEXT (vpc); | |
1949 | ||
1950 | CASE (sem, INSN_RTE) : /* rte */ | |
1951 | { | |
1952 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1953 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 1954 | #define FLD(f) abuf->fields.fmt_empty.f |
c906108c SS |
1955 | int UNUSED written = 0; |
1956 | IADDR UNUSED pc = abuf->addr; | |
1957 | SEM_BRANCH_INIT | |
1958 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1959 | ||
7a292a7a | 1960 | { |
c906108c SS |
1961 | { |
1962 | USI opval = ANDSI (GET_H_CR (((UINT) 6)), -4); | |
1963 | SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); | |
1964 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
1965 | } | |
1966 | { | |
1967 | USI opval = GET_H_CR (((UINT) 14)); | |
1968 | SET_H_CR (((UINT) 6), opval); | |
1969 | TRACE_RESULT (current_cpu, abuf, "cr-6", 'x', opval); | |
1970 | } | |
1971 | { | |
1972 | UQI opval = CPU (h_bpsw); | |
1973 | SET_H_PSW (opval); | |
7a292a7a | 1974 | TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval); |
c906108c SS |
1975 | } |
1976 | { | |
1977 | UQI opval = CPU (h_bbpsw); | |
1978 | CPU (h_bpsw) = opval; | |
7a292a7a | 1979 | TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval); |
c906108c | 1980 | } |
7a292a7a | 1981 | } |
c906108c SS |
1982 | |
1983 | SEM_BRANCH_FINI (vpc); | |
1984 | #undef FLD | |
1985 | } | |
1986 | NEXT (vpc); | |
1987 | ||
1988 | CASE (sem, INSN_SETH) : /* seth $dr,$hash$hi16 */ | |
1989 | { | |
1990 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1991 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 1992 | #define FLD(f) abuf->fields.sfmt_seth.f |
c906108c SS |
1993 | int UNUSED written = 0; |
1994 | IADDR UNUSED pc = abuf->addr; | |
1995 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1996 | ||
1997 | { | |
1998 | SI opval = SLLSI (FLD (f_hi16), 16); | |
1999 | * FLD (i_dr) = opval; | |
2000 | TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); | |
2001 | } | |
2002 | ||
2003 | #undef FLD | |
2004 | } | |
2005 | NEXT (vpc); | |
2006 | ||
2007 | CASE (sem, INSN_SLL) : /* sll $dr,$sr */ | |
2008 | { | |
2009 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2010 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 2011 | #define FLD(f) abuf->fields.sfmt_add.f |
c906108c SS |
2012 | int UNUSED written = 0; |
2013 | IADDR UNUSED pc = abuf->addr; | |
2014 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2015 | ||
2016 | { | |
2017 | SI opval = SLLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31)); | |
2018 | * FLD (i_dr) = opval; | |
2019 | TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); | |
2020 | } | |
2021 | ||
2022 | #undef FLD | |
2023 | } | |
2024 | NEXT (vpc); | |
2025 | ||
2026 | CASE (sem, INSN_SLL3) : /* sll3 $dr,$sr,$simm16 */ | |
2027 | { | |
2028 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2029 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 2030 | #define FLD(f) abuf->fields.sfmt_add3.f |
c906108c SS |
2031 | int UNUSED written = 0; |
2032 | IADDR UNUSED pc = abuf->addr; | |
2033 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2034 | ||
2035 | { | |
2036 | SI opval = SLLSI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31)); | |
2037 | * FLD (i_dr) = opval; | |
2038 | TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); | |
2039 | } | |
2040 | ||
2041 | #undef FLD | |
2042 | } | |
2043 | NEXT (vpc); | |
2044 | ||
2045 | CASE (sem, INSN_SLLI) : /* slli $dr,$uimm5 */ | |
2046 | { | |
2047 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2048 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 2049 | #define FLD(f) abuf->fields.sfmt_slli.f |
c906108c SS |
2050 | int UNUSED written = 0; |
2051 | IADDR UNUSED pc = abuf->addr; | |
2052 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2053 | ||
2054 | { | |
2055 | SI opval = SLLSI (* FLD (i_dr), FLD (f_uimm5)); | |
2056 | * FLD (i_dr) = opval; | |
2057 | TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); | |
2058 | } | |
2059 | ||
2060 | #undef FLD | |
2061 | } | |
2062 | NEXT (vpc); | |
2063 | ||
2064 | CASE (sem, INSN_SRA) : /* sra $dr,$sr */ | |
2065 | { | |
2066 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2067 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 2068 | #define FLD(f) abuf->fields.sfmt_add.f |
c906108c SS |
2069 | int UNUSED written = 0; |
2070 | IADDR UNUSED pc = abuf->addr; | |
2071 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2072 | ||
2073 | { | |
2074 | SI opval = SRASI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31)); | |
2075 | * FLD (i_dr) = opval; | |
2076 | TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); | |
2077 | } | |
2078 | ||
2079 | #undef FLD | |
2080 | } | |
2081 | NEXT (vpc); | |
2082 | ||
2083 | CASE (sem, INSN_SRA3) : /* sra3 $dr,$sr,$simm16 */ | |
2084 | { | |
2085 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2086 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 2087 | #define FLD(f) abuf->fields.sfmt_add3.f |
c906108c SS |
2088 | int UNUSED written = 0; |
2089 | IADDR UNUSED pc = abuf->addr; | |
2090 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2091 | ||
2092 | { | |
2093 | SI opval = SRASI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31)); | |
2094 | * FLD (i_dr) = opval; | |
2095 | TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); | |
2096 | } | |
2097 | ||
2098 | #undef FLD | |
2099 | } | |
2100 | NEXT (vpc); | |
2101 | ||
2102 | CASE (sem, INSN_SRAI) : /* srai $dr,$uimm5 */ | |
2103 | { | |
2104 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2105 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 2106 | #define FLD(f) abuf->fields.sfmt_slli.f |
c906108c SS |
2107 | int UNUSED written = 0; |
2108 | IADDR UNUSED pc = abuf->addr; | |
2109 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2110 | ||
2111 | { | |
2112 | SI opval = SRASI (* FLD (i_dr), FLD (f_uimm5)); | |
2113 | * FLD (i_dr) = opval; | |
2114 | TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); | |
2115 | } | |
2116 | ||
2117 | #undef FLD | |
2118 | } | |
2119 | NEXT (vpc); | |
2120 | ||
2121 | CASE (sem, INSN_SRL) : /* srl $dr,$sr */ | |
2122 | { | |
2123 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2124 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 2125 | #define FLD(f) abuf->fields.sfmt_add.f |
c906108c SS |
2126 | int UNUSED written = 0; |
2127 | IADDR UNUSED pc = abuf->addr; | |
2128 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2129 | ||
2130 | { | |
2131 | SI opval = SRLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31)); | |
2132 | * FLD (i_dr) = opval; | |
2133 | TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); | |
2134 | } | |
2135 | ||
2136 | #undef FLD | |
2137 | } | |
2138 | NEXT (vpc); | |
2139 | ||
2140 | CASE (sem, INSN_SRL3) : /* srl3 $dr,$sr,$simm16 */ | |
2141 | { | |
2142 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2143 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 2144 | #define FLD(f) abuf->fields.sfmt_add3.f |
c906108c SS |
2145 | int UNUSED written = 0; |
2146 | IADDR UNUSED pc = abuf->addr; | |
2147 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2148 | ||
2149 | { | |
2150 | SI opval = SRLSI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31)); | |
2151 | * FLD (i_dr) = opval; | |
2152 | TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); | |
2153 | } | |
2154 | ||
2155 | #undef FLD | |
2156 | } | |
2157 | NEXT (vpc); | |
2158 | ||
2159 | CASE (sem, INSN_SRLI) : /* srli $dr,$uimm5 */ | |
2160 | { | |
2161 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2162 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 2163 | #define FLD(f) abuf->fields.sfmt_slli.f |
c906108c SS |
2164 | int UNUSED written = 0; |
2165 | IADDR UNUSED pc = abuf->addr; | |
2166 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2167 | ||
2168 | { | |
2169 | SI opval = SRLSI (* FLD (i_dr), FLD (f_uimm5)); | |
2170 | * FLD (i_dr) = opval; | |
2171 | TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); | |
2172 | } | |
2173 | ||
2174 | #undef FLD | |
2175 | } | |
2176 | NEXT (vpc); | |
2177 | ||
2178 | CASE (sem, INSN_ST) : /* st $src1,@$src2 */ | |
2179 | { | |
2180 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2181 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 2182 | #define FLD(f) abuf->fields.sfmt_st_plus.f |
c906108c SS |
2183 | int UNUSED written = 0; |
2184 | IADDR UNUSED pc = abuf->addr; | |
2185 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2186 | ||
2187 | { | |
2188 | SI opval = * FLD (i_src1); | |
2189 | SETMEMSI (current_cpu, pc, * FLD (i_src2), opval); | |
2190 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
2191 | } | |
2192 | ||
2193 | #undef FLD | |
2194 | } | |
2195 | NEXT (vpc); | |
2196 | ||
2197 | CASE (sem, INSN_ST_D) : /* st $src1,@($slo16,$src2) */ | |
2198 | { | |
2199 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2200 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 2201 | #define FLD(f) abuf->fields.sfmt_st_d.f |
c906108c SS |
2202 | int UNUSED written = 0; |
2203 | IADDR UNUSED pc = abuf->addr; | |
2204 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2205 | ||
2206 | { | |
2207 | SI opval = * FLD (i_src1); | |
2208 | SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval); | |
2209 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
2210 | } | |
2211 | ||
2212 | #undef FLD | |
2213 | } | |
2214 | NEXT (vpc); | |
2215 | ||
2216 | CASE (sem, INSN_STB) : /* stb $src1,@$src2 */ | |
2217 | { | |
2218 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2219 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 2220 | #define FLD(f) abuf->fields.sfmt_st_plus.f |
c906108c SS |
2221 | int UNUSED written = 0; |
2222 | IADDR UNUSED pc = abuf->addr; | |
2223 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2224 | ||
2225 | { | |
2226 | QI opval = * FLD (i_src1); | |
2227 | SETMEMQI (current_cpu, pc, * FLD (i_src2), opval); | |
2228 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
2229 | } | |
2230 | ||
2231 | #undef FLD | |
2232 | } | |
2233 | NEXT (vpc); | |
2234 | ||
2235 | CASE (sem, INSN_STB_D) : /* stb $src1,@($slo16,$src2) */ | |
2236 | { | |
2237 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2238 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 2239 | #define FLD(f) abuf->fields.sfmt_st_d.f |
c906108c SS |
2240 | int UNUSED written = 0; |
2241 | IADDR UNUSED pc = abuf->addr; | |
2242 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2243 | ||
2244 | { | |
2245 | QI opval = * FLD (i_src1); | |
2246 | SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval); | |
2247 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
2248 | } | |
2249 | ||
2250 | #undef FLD | |
2251 | } | |
2252 | NEXT (vpc); | |
2253 | ||
2254 | CASE (sem, INSN_STH) : /* sth $src1,@$src2 */ | |
2255 | { | |
2256 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2257 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 2258 | #define FLD(f) abuf->fields.sfmt_st_plus.f |
c906108c SS |
2259 | int UNUSED written = 0; |
2260 | IADDR UNUSED pc = abuf->addr; | |
2261 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2262 | ||
2263 | { | |
2264 | HI opval = * FLD (i_src1); | |
2265 | SETMEMHI (current_cpu, pc, * FLD (i_src2), opval); | |
2266 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
2267 | } | |
2268 | ||
2269 | #undef FLD | |
2270 | } | |
2271 | NEXT (vpc); | |
2272 | ||
2273 | CASE (sem, INSN_STH_D) : /* sth $src1,@($slo16,$src2) */ | |
2274 | { | |
2275 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2276 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 2277 | #define FLD(f) abuf->fields.sfmt_st_d.f |
c906108c SS |
2278 | int UNUSED written = 0; |
2279 | IADDR UNUSED pc = abuf->addr; | |
2280 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2281 | ||
2282 | { | |
2283 | HI opval = * FLD (i_src1); | |
2284 | SETMEMHI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval); | |
2285 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
2286 | } | |
2287 | ||
2288 | #undef FLD | |
2289 | } | |
2290 | NEXT (vpc); | |
2291 | ||
2292 | CASE (sem, INSN_ST_PLUS) : /* st $src1,@+$src2 */ | |
2293 | { | |
2294 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2295 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 2296 | #define FLD(f) abuf->fields.sfmt_st_plus.f |
c906108c SS |
2297 | int UNUSED written = 0; |
2298 | IADDR UNUSED pc = abuf->addr; | |
2299 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2300 | ||
7a292a7a | 2301 | { |
c906108c SS |
2302 | SI tmp_new_src2; |
2303 | tmp_new_src2 = ADDSI (* FLD (i_src2), 4); | |
2304 | { | |
2305 | SI opval = * FLD (i_src1); | |
2306 | SETMEMSI (current_cpu, pc, tmp_new_src2, opval); | |
2307 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
2308 | } | |
2309 | { | |
2310 | SI opval = tmp_new_src2; | |
2311 | * FLD (i_src2) = opval; | |
2312 | TRACE_RESULT (current_cpu, abuf, "src2", 'x', opval); | |
2313 | } | |
7a292a7a | 2314 | } |
c906108c SS |
2315 | |
2316 | #undef FLD | |
2317 | } | |
2318 | NEXT (vpc); | |
2319 | ||
2320 | CASE (sem, INSN_ST_MINUS) : /* st $src1,@-$src2 */ | |
2321 | { | |
2322 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2323 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 2324 | #define FLD(f) abuf->fields.sfmt_st_plus.f |
c906108c SS |
2325 | int UNUSED written = 0; |
2326 | IADDR UNUSED pc = abuf->addr; | |
2327 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2328 | ||
7a292a7a | 2329 | { |
c906108c SS |
2330 | SI tmp_new_src2; |
2331 | tmp_new_src2 = SUBSI (* FLD (i_src2), 4); | |
2332 | { | |
2333 | SI opval = * FLD (i_src1); | |
2334 | SETMEMSI (current_cpu, pc, tmp_new_src2, opval); | |
2335 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
2336 | } | |
2337 | { | |
2338 | SI opval = tmp_new_src2; | |
2339 | * FLD (i_src2) = opval; | |
2340 | TRACE_RESULT (current_cpu, abuf, "src2", 'x', opval); | |
2341 | } | |
7a292a7a | 2342 | } |
c906108c SS |
2343 | |
2344 | #undef FLD | |
2345 | } | |
2346 | NEXT (vpc); | |
2347 | ||
2348 | CASE (sem, INSN_SUB) : /* sub $dr,$sr */ | |
2349 | { | |
2350 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2351 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 2352 | #define FLD(f) abuf->fields.sfmt_add.f |
c906108c SS |
2353 | int UNUSED written = 0; |
2354 | IADDR UNUSED pc = abuf->addr; | |
2355 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2356 | ||
2357 | { | |
2358 | SI opval = SUBSI (* FLD (i_dr), * FLD (i_sr)); | |
2359 | * FLD (i_dr) = opval; | |
2360 | TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); | |
2361 | } | |
2362 | ||
2363 | #undef FLD | |
2364 | } | |
2365 | NEXT (vpc); | |
2366 | ||
2367 | CASE (sem, INSN_SUBV) : /* subv $dr,$sr */ | |
2368 | { | |
2369 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2370 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 2371 | #define FLD(f) abuf->fields.sfmt_add.f |
c906108c SS |
2372 | int UNUSED written = 0; |
2373 | IADDR UNUSED pc = abuf->addr; | |
2374 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2375 | ||
7a292a7a SS |
2376 | { |
2377 | SI temp0;BI temp1; | |
c906108c SS |
2378 | temp0 = SUBSI (* FLD (i_dr), * FLD (i_sr)); |
2379 | temp1 = SUBOFSI (* FLD (i_dr), * FLD (i_sr), 0); | |
2380 | { | |
2381 | SI opval = temp0; | |
2382 | * FLD (i_dr) = opval; | |
2383 | TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); | |
2384 | } | |
2385 | { | |
2386 | BI opval = temp1; | |
2387 | CPU (h_cond) = opval; | |
2388 | TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval); | |
2389 | } | |
7a292a7a | 2390 | } |
c906108c SS |
2391 | |
2392 | #undef FLD | |
2393 | } | |
2394 | NEXT (vpc); | |
2395 | ||
2396 | CASE (sem, INSN_SUBX) : /* subx $dr,$sr */ | |
2397 | { | |
2398 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2399 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 2400 | #define FLD(f) abuf->fields.sfmt_add.f |
c906108c SS |
2401 | int UNUSED written = 0; |
2402 | IADDR UNUSED pc = abuf->addr; | |
2403 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2404 | ||
7a292a7a SS |
2405 | { |
2406 | SI temp0;BI temp1; | |
c906108c SS |
2407 | temp0 = SUBCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond)); |
2408 | temp1 = SUBCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond)); | |
2409 | { | |
2410 | SI opval = temp0; | |
2411 | * FLD (i_dr) = opval; | |
2412 | TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); | |
2413 | } | |
2414 | { | |
2415 | BI opval = temp1; | |
2416 | CPU (h_cond) = opval; | |
2417 | TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval); | |
2418 | } | |
7a292a7a | 2419 | } |
c906108c SS |
2420 | |
2421 | #undef FLD | |
2422 | } | |
2423 | NEXT (vpc); | |
2424 | ||
2425 | CASE (sem, INSN_TRAP) : /* trap $uimm4 */ | |
2426 | { | |
2427 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2428 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 2429 | #define FLD(f) abuf->fields.sfmt_trap.f |
c906108c SS |
2430 | int UNUSED written = 0; |
2431 | IADDR UNUSED pc = abuf->addr; | |
2432 | SEM_BRANCH_INIT | |
2433 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2434 | ||
7a292a7a | 2435 | { |
c906108c SS |
2436 | { |
2437 | USI opval = GET_H_CR (((UINT) 6)); | |
2438 | SET_H_CR (((UINT) 14), opval); | |
2439 | TRACE_RESULT (current_cpu, abuf, "cr-14", 'x', opval); | |
2440 | } | |
2441 | { | |
2442 | USI opval = ADDSI (pc, 4); | |
2443 | SET_H_CR (((UINT) 6), opval); | |
2444 | TRACE_RESULT (current_cpu, abuf, "cr-6", 'x', opval); | |
2445 | } | |
2446 | { | |
2447 | UQI opval = CPU (h_bpsw); | |
2448 | CPU (h_bbpsw) = opval; | |
7a292a7a | 2449 | TRACE_RESULT (current_cpu, abuf, "bbpsw", 'x', opval); |
c906108c SS |
2450 | } |
2451 | { | |
2452 | UQI opval = GET_H_PSW (); | |
2453 | CPU (h_bpsw) = opval; | |
7a292a7a | 2454 | TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval); |
c906108c SS |
2455 | } |
2456 | { | |
2457 | UQI opval = ANDQI (GET_H_PSW (), 128); | |
2458 | SET_H_PSW (opval); | |
7a292a7a | 2459 | TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval); |
c906108c SS |
2460 | } |
2461 | { | |
2462 | SI opval = m32r_trap (current_cpu, pc, FLD (f_uimm4)); | |
2463 | SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); | |
2464 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
2465 | } | |
7a292a7a | 2466 | } |
c906108c SS |
2467 | |
2468 | SEM_BRANCH_FINI (vpc); | |
2469 | #undef FLD | |
2470 | } | |
2471 | NEXT (vpc); | |
2472 | ||
2473 | CASE (sem, INSN_UNLOCK) : /* unlock $src1,@$src2 */ | |
2474 | { | |
2475 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2476 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
96baa820 | 2477 | #define FLD(f) abuf->fields.sfmt_st_plus.f |
c906108c SS |
2478 | int UNUSED written = 0; |
2479 | IADDR UNUSED pc = abuf->addr; | |
2480 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2481 | ||
7a292a7a | 2482 | { |
c906108c SS |
2483 | if (CPU (h_lock)) { |
2484 | { | |
2485 | SI opval = * FLD (i_src1); | |
2486 | SETMEMSI (current_cpu, pc, * FLD (i_src2), opval); | |
2487 | written |= (1 << 4); | |
2488 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
2489 | } | |
2490 | } | |
2491 | { | |
2492 | BI opval = 0; | |
2493 | CPU (h_lock) = opval; | |
7a292a7a | 2494 | TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval); |
c906108c | 2495 | } |
7a292a7a | 2496 | } |
c906108c SS |
2497 | |
2498 | abuf->written = written; | |
2499 | #undef FLD | |
2500 | } | |
2501 | NEXT (vpc); | |
2502 | ||
2503 | ||
2504 | } | |
2505 | ENDSWITCH (sem) /* End of semantic switch. */ | |
2506 | ||
2507 | /* At this point `vpc' contains the next insn to execute. */ | |
2508 | } | |
2509 | ||
2510 | #undef DEFINE_SWITCH | |
2511 | #endif /* DEFINE_SWITCH */ |