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8e420152 DE |
1 | /* Simulator instruction semantics for m32rx. |
2 | ||
3 | Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. | |
4 | ||
5 | This file is part of the GNU Simulators. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License along | |
18 | with this program; if not, write to the Free Software Foundation, Inc., | |
19 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
20 | ||
21 | */ | |
22 | ||
23 | #define WANT_CPU | |
24 | #define WANT_CPU_M32RX | |
25 | ||
26 | #include "sim-main.h" | |
27 | #include "cgen-mem.h" | |
28 | #include "cgen-ops.h" | |
29 | #include "cpu-sim.h" | |
30 | ||
31 | #if ! defined (SCACHE_P) || (defined (SCACHE_P) && WITH_SCACHE) | |
32 | ||
33 | #undef GET_ATTR | |
34 | #define GET_ATTR(cpu, num, attr) CGEN_INSN_ATTR (abuf->opcode, CGEN_INSN_##attr) | |
35 | ||
36 | /* Perform add: add $dr,$sr. */ | |
37 | CIA | |
38 | SEM_FN_NAME (m32rx,add) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
39 | { | |
40 | #define FLD(f) abuf->fields.fmt_0_add.f | |
41 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_0_add.f | |
42 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
43 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
44 | CPU (h_gr[f_r1]) = ADDSI (OPRND (dr), OPRND (sr)); | |
45 | TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr)); | |
46 | #if WITH_PROFILE_MODEL_P | |
47 | if (PROFILE_MODEL_P (current_cpu)) | |
48 | { | |
49 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
50 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
51 | m32rx_model_profile_insn (current_cpu, abuf); | |
52 | } | |
53 | #endif | |
54 | return new_pc; | |
55 | #undef OPRND | |
56 | #undef FLD | |
57 | } | |
58 | ||
59 | /* Perform add3: add3 $dr,$sr,#$slo16. */ | |
60 | CIA | |
61 | SEM_FN_NAME (m32rx,add3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
62 | { | |
63 | #define FLD(f) abuf->fields.fmt_1_add3.f | |
64 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_1_add3.f | |
65 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
66 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
67 | CPU (h_gr[f_r1]) = ADDSI (OPRND (sr), OPRND (slo16)); | |
68 | TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr)); | |
69 | #if WITH_PROFILE_MODEL_P | |
70 | if (PROFILE_MODEL_P (current_cpu)) | |
71 | { | |
72 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
73 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
74 | m32rx_model_profile_insn (current_cpu, abuf); | |
75 | } | |
76 | #endif | |
77 | return new_pc; | |
78 | #undef OPRND | |
79 | #undef FLD | |
80 | } | |
81 | ||
82 | /* Perform and: and $dr,$sr. */ | |
83 | CIA | |
84 | SEM_FN_NAME (m32rx,and) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
85 | { | |
86 | #define FLD(f) abuf->fields.fmt_0_add.f | |
87 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_0_add.f | |
88 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
89 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
90 | CPU (h_gr[f_r1]) = ANDSI (OPRND (dr), OPRND (sr)); | |
91 | TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr)); | |
92 | #if WITH_PROFILE_MODEL_P | |
93 | if (PROFILE_MODEL_P (current_cpu)) | |
94 | { | |
95 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
96 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
97 | m32rx_model_profile_insn (current_cpu, abuf); | |
98 | } | |
99 | #endif | |
100 | return new_pc; | |
101 | #undef OPRND | |
102 | #undef FLD | |
103 | } | |
104 | ||
105 | /* Perform and3: and3 $dr,$sr,#$uimm16. */ | |
106 | CIA | |
107 | SEM_FN_NAME (m32rx,and3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
108 | { | |
109 | #define FLD(f) abuf->fields.fmt_2_and3.f | |
110 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_2_and3.f | |
111 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
112 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
113 | CPU (h_gr[f_r1]) = ANDSI (OPRND (sr), OPRND (uimm16)); | |
114 | TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr)); | |
115 | #if WITH_PROFILE_MODEL_P | |
116 | if (PROFILE_MODEL_P (current_cpu)) | |
117 | { | |
118 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
119 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
120 | m32rx_model_profile_insn (current_cpu, abuf); | |
121 | } | |
122 | #endif | |
123 | return new_pc; | |
124 | #undef OPRND | |
125 | #undef FLD | |
126 | } | |
127 | ||
128 | /* Perform or: or $dr,$sr. */ | |
129 | CIA | |
130 | SEM_FN_NAME (m32rx,or) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
131 | { | |
132 | #define FLD(f) abuf->fields.fmt_0_add.f | |
133 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_0_add.f | |
134 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
135 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
136 | CPU (h_gr[f_r1]) = ORSI (OPRND (dr), OPRND (sr)); | |
137 | TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr)); | |
138 | #if WITH_PROFILE_MODEL_P | |
139 | if (PROFILE_MODEL_P (current_cpu)) | |
140 | { | |
141 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
142 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
143 | m32rx_model_profile_insn (current_cpu, abuf); | |
144 | } | |
145 | #endif | |
146 | return new_pc; | |
147 | #undef OPRND | |
148 | #undef FLD | |
149 | } | |
150 | ||
151 | /* Perform or3: or3 $dr,$sr,#$ulo16. */ | |
152 | CIA | |
153 | SEM_FN_NAME (m32rx,or3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
154 | { | |
155 | #define FLD(f) abuf->fields.fmt_3_or3.f | |
156 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_3_or3.f | |
157 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
158 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
159 | CPU (h_gr[f_r1]) = ORSI (OPRND (sr), OPRND (ulo16)); | |
160 | TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr)); | |
161 | #if WITH_PROFILE_MODEL_P | |
162 | if (PROFILE_MODEL_P (current_cpu)) | |
163 | { | |
164 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
165 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
166 | m32rx_model_profile_insn (current_cpu, abuf); | |
167 | } | |
168 | #endif | |
169 | return new_pc; | |
170 | #undef OPRND | |
171 | #undef FLD | |
172 | } | |
173 | ||
174 | /* Perform xor: xor $dr,$sr. */ | |
175 | CIA | |
176 | SEM_FN_NAME (m32rx,xor) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
177 | { | |
178 | #define FLD(f) abuf->fields.fmt_0_add.f | |
179 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_0_add.f | |
180 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
181 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
182 | CPU (h_gr[f_r1]) = XORSI (OPRND (dr), OPRND (sr)); | |
183 | TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr)); | |
184 | #if WITH_PROFILE_MODEL_P | |
185 | if (PROFILE_MODEL_P (current_cpu)) | |
186 | { | |
187 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
188 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
189 | m32rx_model_profile_insn (current_cpu, abuf); | |
190 | } | |
191 | #endif | |
192 | return new_pc; | |
193 | #undef OPRND | |
194 | #undef FLD | |
195 | } | |
196 | ||
197 | /* Perform xor3: xor3 $dr,$sr,#$uimm16. */ | |
198 | CIA | |
199 | SEM_FN_NAME (m32rx,xor3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
200 | { | |
201 | #define FLD(f) abuf->fields.fmt_2_and3.f | |
202 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_2_and3.f | |
203 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
204 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
205 | CPU (h_gr[f_r1]) = XORSI (OPRND (sr), OPRND (uimm16)); | |
206 | TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr)); | |
207 | #if WITH_PROFILE_MODEL_P | |
208 | if (PROFILE_MODEL_P (current_cpu)) | |
209 | { | |
210 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
211 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
212 | m32rx_model_profile_insn (current_cpu, abuf); | |
213 | } | |
214 | #endif | |
215 | return new_pc; | |
216 | #undef OPRND | |
217 | #undef FLD | |
218 | } | |
219 | ||
220 | /* Perform addi: addi $dr,#$simm8. */ | |
221 | CIA | |
222 | SEM_FN_NAME (m32rx,addi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
223 | { | |
224 | #define FLD(f) abuf->fields.fmt_4_addi.f | |
225 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_4_addi.f | |
226 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
227 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
228 | CPU (h_gr[f_r1]) = ADDSI (OPRND (dr), OPRND (simm8)); | |
229 | TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr)); | |
230 | #if WITH_PROFILE_MODEL_P | |
231 | if (PROFILE_MODEL_P (current_cpu)) | |
232 | { | |
233 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
234 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
235 | m32rx_model_profile_insn (current_cpu, abuf); | |
236 | } | |
237 | #endif | |
238 | return new_pc; | |
239 | #undef OPRND | |
240 | #undef FLD | |
241 | } | |
242 | ||
243 | /* Perform addv: addv $dr,$sr. */ | |
244 | CIA | |
245 | SEM_FN_NAME (m32rx,addv) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
246 | { | |
247 | #define FLD(f) abuf->fields.fmt_0_add.f | |
248 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_0_add.f | |
249 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
250 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
251 | do { | |
252 | BI temp1;SI temp0; | |
253 | temp0 = ADDSI (OPRND (dr), OPRND (sr)); | |
254 | temp1 = ADDOFSI (OPRND (dr), OPRND (sr), 0); | |
255 | CPU (h_gr[f_r1]) = temp0; | |
256 | TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr)); | |
257 | CPU (h_cond) = temp1; | |
258 | TRACE_RESULT (current_cpu, "condbit", 'x', OPRND (condbit)); | |
259 | } while (0); | |
260 | #if WITH_PROFILE_MODEL_P | |
261 | if (PROFILE_MODEL_P (current_cpu)) | |
262 | { | |
263 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
264 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
265 | m32rx_model_profile_insn (current_cpu, abuf); | |
266 | } | |
267 | #endif | |
268 | return new_pc; | |
269 | #undef OPRND | |
270 | #undef FLD | |
271 | } | |
272 | ||
273 | /* Perform addv3: addv3 $dr,$sr,#$simm16. */ | |
274 | CIA | |
275 | SEM_FN_NAME (m32rx,addv3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
276 | { | |
277 | #define FLD(f) abuf->fields.fmt_5_addv3.f | |
278 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_5_addv3.f | |
279 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
280 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
281 | do { | |
282 | BI temp1;SI temp0; | |
283 | temp0 = ADDSI (OPRND (sr), OPRND (simm16)); | |
284 | temp1 = ADDOFSI (OPRND (sr), OPRND (simm16), 0); | |
285 | CPU (h_gr[f_r1]) = temp0; | |
286 | TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr)); | |
287 | CPU (h_cond) = temp1; | |
288 | TRACE_RESULT (current_cpu, "condbit", 'x', OPRND (condbit)); | |
289 | } while (0); | |
290 | #if WITH_PROFILE_MODEL_P | |
291 | if (PROFILE_MODEL_P (current_cpu)) | |
292 | { | |
293 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
294 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
295 | m32rx_model_profile_insn (current_cpu, abuf); | |
296 | } | |
297 | #endif | |
298 | return new_pc; | |
299 | #undef OPRND | |
300 | #undef FLD | |
301 | } | |
302 | ||
303 | /* Perform addx: addx $dr,$sr. */ | |
304 | CIA | |
305 | SEM_FN_NAME (m32rx,addx) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
306 | { | |
307 | #define FLD(f) abuf->fields.fmt_6_addx.f | |
308 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_6_addx.f | |
309 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
310 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
311 | do { | |
312 | BI temp1;SI temp0; | |
313 | temp0 = ADDCSI (OPRND (dr), OPRND (sr), OPRND (condbit)); | |
314 | temp1 = ADDCFSI (OPRND (dr), OPRND (sr), OPRND (condbit)); | |
315 | CPU (h_gr[f_r1]) = temp0; | |
316 | TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr)); | |
317 | CPU (h_cond) = temp1; | |
318 | TRACE_RESULT (current_cpu, "condbit", 'x', OPRND (condbit)); | |
319 | } while (0); | |
320 | #if WITH_PROFILE_MODEL_P | |
321 | if (PROFILE_MODEL_P (current_cpu)) | |
322 | { | |
323 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
324 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
325 | m32rx_model_profile_insn (current_cpu, abuf); | |
326 | } | |
327 | #endif | |
328 | return new_pc; | |
329 | #undef OPRND | |
330 | #undef FLD | |
331 | } | |
332 | ||
333 | /* Perform bc8: bc $disp8. */ | |
334 | CIA | |
335 | SEM_FN_NAME (m32rx,bc8) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
336 | { | |
337 | #define FLD(f) abuf->fields.fmt_7_bc8.f | |
338 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_7_bc8.f | |
339 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
340 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
341 | int taken_p = 0; | |
342 | if (OPRND (condbit)) { | |
343 | BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp8))); | |
344 | } | |
345 | #if WITH_PROFILE_MODEL_P | |
346 | if (PROFILE_MODEL_P (current_cpu)) | |
347 | { | |
348 | m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p); | |
349 | } | |
350 | #endif | |
351 | return new_pc; | |
352 | #undef OPRND | |
353 | #undef FLD | |
354 | } | |
355 | ||
356 | /* Perform bc24: bc $disp24. */ | |
357 | CIA | |
358 | SEM_FN_NAME (m32rx,bc24) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
359 | { | |
360 | #define FLD(f) abuf->fields.fmt_8_bc24.f | |
361 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_8_bc24.f | |
362 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
363 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
364 | int taken_p = 0; | |
365 | if (OPRND (condbit)) { | |
366 | BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp24))); | |
367 | } | |
368 | #if WITH_PROFILE_MODEL_P | |
369 | if (PROFILE_MODEL_P (current_cpu)) | |
370 | { | |
371 | m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p); | |
372 | } | |
373 | #endif | |
374 | return new_pc; | |
375 | #undef OPRND | |
376 | #undef FLD | |
377 | } | |
378 | ||
379 | /* Perform beq: beq $src1,$src2,$disp16. */ | |
380 | CIA | |
381 | SEM_FN_NAME (m32rx,beq) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
382 | { | |
383 | #define FLD(f) abuf->fields.fmt_9_beq.f | |
384 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_9_beq.f | |
385 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
386 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
387 | int taken_p = 0; | |
388 | if (EQSI (OPRND (src1), OPRND (src2))) { | |
389 | BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp16))); | |
390 | } | |
391 | #if WITH_PROFILE_MODEL_P | |
392 | if (PROFILE_MODEL_P (current_cpu)) | |
393 | { | |
394 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
395 | m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p); | |
396 | } | |
397 | #endif | |
398 | return new_pc; | |
399 | #undef OPRND | |
400 | #undef FLD | |
401 | } | |
402 | ||
403 | /* Perform beqz: beqz $src2,$disp16. */ | |
404 | CIA | |
405 | SEM_FN_NAME (m32rx,beqz) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
406 | { | |
407 | #define FLD(f) abuf->fields.fmt_10_beqz.f | |
408 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_10_beqz.f | |
409 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
410 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
411 | int taken_p = 0; | |
412 | if (EQSI (OPRND (src2), 0)) { | |
413 | BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp16))); | |
414 | } | |
415 | #if WITH_PROFILE_MODEL_P | |
416 | if (PROFILE_MODEL_P (current_cpu)) | |
417 | { | |
418 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
419 | m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p); | |
420 | } | |
421 | #endif | |
422 | return new_pc; | |
423 | #undef OPRND | |
424 | #undef FLD | |
425 | } | |
426 | ||
427 | /* Perform bgez: bgez $src2,$disp16. */ | |
428 | CIA | |
429 | SEM_FN_NAME (m32rx,bgez) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
430 | { | |
431 | #define FLD(f) abuf->fields.fmt_10_beqz.f | |
432 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_10_beqz.f | |
433 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
434 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
435 | int taken_p = 0; | |
436 | if (GESI (OPRND (src2), 0)) { | |
437 | BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp16))); | |
438 | } | |
439 | #if WITH_PROFILE_MODEL_P | |
440 | if (PROFILE_MODEL_P (current_cpu)) | |
441 | { | |
442 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
443 | m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p); | |
444 | } | |
445 | #endif | |
446 | return new_pc; | |
447 | #undef OPRND | |
448 | #undef FLD | |
449 | } | |
450 | ||
451 | /* Perform bgtz: bgtz $src2,$disp16. */ | |
452 | CIA | |
453 | SEM_FN_NAME (m32rx,bgtz) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
454 | { | |
455 | #define FLD(f) abuf->fields.fmt_10_beqz.f | |
456 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_10_beqz.f | |
457 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
458 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
459 | int taken_p = 0; | |
460 | if (GTSI (OPRND (src2), 0)) { | |
461 | BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp16))); | |
462 | } | |
463 | #if WITH_PROFILE_MODEL_P | |
464 | if (PROFILE_MODEL_P (current_cpu)) | |
465 | { | |
466 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
467 | m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p); | |
468 | } | |
469 | #endif | |
470 | return new_pc; | |
471 | #undef OPRND | |
472 | #undef FLD | |
473 | } | |
474 | ||
475 | /* Perform blez: blez $src2,$disp16. */ | |
476 | CIA | |
477 | SEM_FN_NAME (m32rx,blez) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
478 | { | |
479 | #define FLD(f) abuf->fields.fmt_10_beqz.f | |
480 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_10_beqz.f | |
481 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
482 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
483 | int taken_p = 0; | |
484 | if (LESI (OPRND (src2), 0)) { | |
485 | BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp16))); | |
486 | } | |
487 | #if WITH_PROFILE_MODEL_P | |
488 | if (PROFILE_MODEL_P (current_cpu)) | |
489 | { | |
490 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
491 | m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p); | |
492 | } | |
493 | #endif | |
494 | return new_pc; | |
495 | #undef OPRND | |
496 | #undef FLD | |
497 | } | |
498 | ||
499 | /* Perform bltz: bltz $src2,$disp16. */ | |
500 | CIA | |
501 | SEM_FN_NAME (m32rx,bltz) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
502 | { | |
503 | #define FLD(f) abuf->fields.fmt_10_beqz.f | |
504 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_10_beqz.f | |
505 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
506 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
507 | int taken_p = 0; | |
508 | if (LTSI (OPRND (src2), 0)) { | |
509 | BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp16))); | |
510 | } | |
511 | #if WITH_PROFILE_MODEL_P | |
512 | if (PROFILE_MODEL_P (current_cpu)) | |
513 | { | |
514 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
515 | m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p); | |
516 | } | |
517 | #endif | |
518 | return new_pc; | |
519 | #undef OPRND | |
520 | #undef FLD | |
521 | } | |
522 | ||
523 | /* Perform bnez: bnez $src2,$disp16. */ | |
524 | CIA | |
525 | SEM_FN_NAME (m32rx,bnez) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
526 | { | |
527 | #define FLD(f) abuf->fields.fmt_10_beqz.f | |
528 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_10_beqz.f | |
529 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
530 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
531 | int taken_p = 0; | |
532 | if (NESI (OPRND (src2), 0)) { | |
533 | BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp16))); | |
534 | } | |
535 | #if WITH_PROFILE_MODEL_P | |
536 | if (PROFILE_MODEL_P (current_cpu)) | |
537 | { | |
538 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
539 | m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p); | |
540 | } | |
541 | #endif | |
542 | return new_pc; | |
543 | #undef OPRND | |
544 | #undef FLD | |
545 | } | |
546 | ||
547 | /* Perform bl8: bl $disp8. */ | |
548 | CIA | |
549 | SEM_FN_NAME (m32rx,bl8) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
550 | { | |
551 | #define FLD(f) abuf->fields.fmt_11_bl8.f | |
552 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_11_bl8.f | |
553 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
554 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
555 | int taken_p = 0; | |
556 | do { | |
557 | CPU (h_gr[14]) = ADDSI (ANDSI (OPRND (pc), -4), 4); | |
558 | TRACE_RESULT (current_cpu, "h-gr", 'x', OPRND (h_gr)); | |
559 | BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp8))); | |
560 | } while (0); | |
561 | #if WITH_PROFILE_MODEL_P | |
562 | if (PROFILE_MODEL_P (current_cpu)) | |
563 | { | |
564 | m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p); | |
565 | } | |
566 | #endif | |
567 | return new_pc; | |
568 | #undef OPRND | |
569 | #undef FLD | |
570 | } | |
571 | ||
572 | /* Perform bl24: bl $disp24. */ | |
573 | CIA | |
574 | SEM_FN_NAME (m32rx,bl24) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
575 | { | |
576 | #define FLD(f) abuf->fields.fmt_12_bl24.f | |
577 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_12_bl24.f | |
578 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
579 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
580 | int taken_p = 0; | |
581 | do { | |
582 | CPU (h_gr[14]) = ADDSI (OPRND (pc), 4); | |
583 | TRACE_RESULT (current_cpu, "h-gr", 'x', OPRND (h_gr)); | |
584 | BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp24))); | |
585 | } while (0); | |
586 | #if WITH_PROFILE_MODEL_P | |
587 | if (PROFILE_MODEL_P (current_cpu)) | |
588 | { | |
589 | m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p); | |
590 | } | |
591 | #endif | |
592 | return new_pc; | |
593 | #undef OPRND | |
594 | #undef FLD | |
595 | } | |
596 | ||
597 | /* Perform bcl8: bcl $disp8. */ | |
598 | CIA | |
599 | SEM_FN_NAME (m32rx,bcl8) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
600 | { | |
601 | #define FLD(f) abuf->fields.fmt_13_bcl8.f | |
602 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_13_bcl8.f | |
603 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
604 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
605 | int taken_p = 0; | |
606 | if (OPRND (condbit)) { | |
607 | do { | |
608 | CPU (h_gr[14]) = ADDSI (ANDSI (OPRND (pc), -4), 4); | |
609 | TRACE_RESULT (current_cpu, "h-gr", 'x', OPRND (h_gr)); | |
610 | BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp8))); | |
611 | } while (0); | |
612 | } | |
613 | #if WITH_PROFILE_MODEL_P | |
614 | if (PROFILE_MODEL_P (current_cpu)) | |
615 | { | |
616 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
617 | m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p); | |
618 | } | |
619 | #endif | |
620 | return new_pc; | |
621 | #undef OPRND | |
622 | #undef FLD | |
623 | } | |
624 | ||
625 | /* Perform bcl24: bcl $disp24. */ | |
626 | CIA | |
627 | SEM_FN_NAME (m32rx,bcl24) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
628 | { | |
629 | #define FLD(f) abuf->fields.fmt_14_bcl24.f | |
630 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_14_bcl24.f | |
631 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
632 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
633 | int taken_p = 0; | |
634 | if (OPRND (condbit)) { | |
635 | do { | |
636 | CPU (h_gr[14]) = ADDSI (ANDSI (OPRND (pc), -4), 4); | |
637 | TRACE_RESULT (current_cpu, "h-gr", 'x', OPRND (h_gr)); | |
638 | BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp24))); | |
639 | } while (0); | |
640 | } | |
641 | #if WITH_PROFILE_MODEL_P | |
642 | if (PROFILE_MODEL_P (current_cpu)) | |
643 | { | |
644 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
645 | m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p); | |
646 | } | |
647 | #endif | |
648 | return new_pc; | |
649 | #undef OPRND | |
650 | #undef FLD | |
651 | } | |
652 | ||
653 | /* Perform bnc8: bnc $disp8. */ | |
654 | CIA | |
655 | SEM_FN_NAME (m32rx,bnc8) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
656 | { | |
657 | #define FLD(f) abuf->fields.fmt_7_bc8.f | |
658 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_7_bc8.f | |
659 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
660 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
661 | int taken_p = 0; | |
662 | if (NOTBI (OPRND (condbit))) { | |
663 | BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp8))); | |
664 | } | |
665 | #if WITH_PROFILE_MODEL_P | |
666 | if (PROFILE_MODEL_P (current_cpu)) | |
667 | { | |
668 | m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p); | |
669 | } | |
670 | #endif | |
671 | return new_pc; | |
672 | #undef OPRND | |
673 | #undef FLD | |
674 | } | |
675 | ||
676 | /* Perform bnc24: bnc $disp24. */ | |
677 | CIA | |
678 | SEM_FN_NAME (m32rx,bnc24) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
679 | { | |
680 | #define FLD(f) abuf->fields.fmt_8_bc24.f | |
681 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_8_bc24.f | |
682 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
683 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
684 | int taken_p = 0; | |
685 | if (NOTBI (OPRND (condbit))) { | |
686 | BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp24))); | |
687 | } | |
688 | #if WITH_PROFILE_MODEL_P | |
689 | if (PROFILE_MODEL_P (current_cpu)) | |
690 | { | |
691 | m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p); | |
692 | } | |
693 | #endif | |
694 | return new_pc; | |
695 | #undef OPRND | |
696 | #undef FLD | |
697 | } | |
698 | ||
699 | /* Perform bne: bne $src1,$src2,$disp16. */ | |
700 | CIA | |
701 | SEM_FN_NAME (m32rx,bne) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
702 | { | |
703 | #define FLD(f) abuf->fields.fmt_9_beq.f | |
704 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_9_beq.f | |
705 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
706 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
707 | int taken_p = 0; | |
708 | if (NESI (OPRND (src1), OPRND (src2))) { | |
709 | BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp16))); | |
710 | } | |
711 | #if WITH_PROFILE_MODEL_P | |
712 | if (PROFILE_MODEL_P (current_cpu)) | |
713 | { | |
714 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
715 | m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p); | |
716 | } | |
717 | #endif | |
718 | return new_pc; | |
719 | #undef OPRND | |
720 | #undef FLD | |
721 | } | |
722 | ||
723 | /* Perform bra8: bra $disp8. */ | |
724 | CIA | |
725 | SEM_FN_NAME (m32rx,bra8) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
726 | { | |
727 | #define FLD(f) abuf->fields.fmt_15_bra8.f | |
728 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_15_bra8.f | |
729 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
730 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
731 | int taken_p = 0; | |
732 | BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp8))); | |
733 | #if WITH_PROFILE_MODEL_P | |
734 | if (PROFILE_MODEL_P (current_cpu)) | |
735 | { | |
736 | m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p); | |
737 | } | |
738 | #endif | |
739 | return new_pc; | |
740 | #undef OPRND | |
741 | #undef FLD | |
742 | } | |
743 | ||
744 | /* Perform bra24: bra $disp24. */ | |
745 | CIA | |
746 | SEM_FN_NAME (m32rx,bra24) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
747 | { | |
748 | #define FLD(f) abuf->fields.fmt_16_bra24.f | |
749 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_16_bra24.f | |
750 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
751 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
752 | int taken_p = 0; | |
753 | BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp24))); | |
754 | #if WITH_PROFILE_MODEL_P | |
755 | if (PROFILE_MODEL_P (current_cpu)) | |
756 | { | |
757 | m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p); | |
758 | } | |
759 | #endif | |
760 | return new_pc; | |
761 | #undef OPRND | |
762 | #undef FLD | |
763 | } | |
764 | ||
765 | /* Perform bncl8: bncl $disp8. */ | |
766 | CIA | |
767 | SEM_FN_NAME (m32rx,bncl8) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
768 | { | |
769 | #define FLD(f) abuf->fields.fmt_13_bcl8.f | |
770 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_13_bcl8.f | |
771 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
772 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
773 | int taken_p = 0; | |
774 | if (NOTBI (OPRND (condbit))) { | |
775 | do { | |
776 | CPU (h_gr[14]) = ADDSI (ANDSI (OPRND (pc), -4), 4); | |
777 | TRACE_RESULT (current_cpu, "h-gr", 'x', OPRND (h_gr)); | |
778 | BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp8))); | |
779 | } while (0); | |
780 | } | |
781 | #if WITH_PROFILE_MODEL_P | |
782 | if (PROFILE_MODEL_P (current_cpu)) | |
783 | { | |
784 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
785 | m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p); | |
786 | } | |
787 | #endif | |
788 | return new_pc; | |
789 | #undef OPRND | |
790 | #undef FLD | |
791 | } | |
792 | ||
793 | /* Perform bncl24: bncl $disp24. */ | |
794 | CIA | |
795 | SEM_FN_NAME (m32rx,bncl24) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
796 | { | |
797 | #define FLD(f) abuf->fields.fmt_14_bcl24.f | |
798 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_14_bcl24.f | |
799 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
800 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
801 | int taken_p = 0; | |
802 | if (NOTBI (OPRND (condbit))) { | |
803 | do { | |
804 | CPU (h_gr[14]) = ADDSI (ANDSI (OPRND (pc), -4), 4); | |
805 | TRACE_RESULT (current_cpu, "h-gr", 'x', OPRND (h_gr)); | |
806 | BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp24))); | |
807 | } while (0); | |
808 | } | |
809 | #if WITH_PROFILE_MODEL_P | |
810 | if (PROFILE_MODEL_P (current_cpu)) | |
811 | { | |
812 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
813 | m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p); | |
814 | } | |
815 | #endif | |
816 | return new_pc; | |
817 | #undef OPRND | |
818 | #undef FLD | |
819 | } | |
820 | ||
821 | /* Perform cmp: cmp $src1,$src2. */ | |
822 | CIA | |
823 | SEM_FN_NAME (m32rx,cmp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
824 | { | |
825 | #define FLD(f) abuf->fields.fmt_17_cmp.f | |
826 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_17_cmp.f | |
827 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
828 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
829 | CPU (h_cond) = LTSI (OPRND (src1), OPRND (src2)); | |
830 | TRACE_RESULT (current_cpu, "condbit", 'x', OPRND (condbit)); | |
831 | #if WITH_PROFILE_MODEL_P | |
832 | if (PROFILE_MODEL_P (current_cpu)) | |
833 | { | |
834 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
835 | m32rx_model_profile_insn (current_cpu, abuf); | |
836 | } | |
837 | #endif | |
838 | return new_pc; | |
839 | #undef OPRND | |
840 | #undef FLD | |
841 | } | |
842 | ||
843 | /* Perform cmpi: cmpi $src2,#$simm16. */ | |
844 | CIA | |
845 | SEM_FN_NAME (m32rx,cmpi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
846 | { | |
847 | #define FLD(f) abuf->fields.fmt_18_cmpi.f | |
848 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_18_cmpi.f | |
849 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
850 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
851 | CPU (h_cond) = LTSI (OPRND (src2), OPRND (simm16)); | |
852 | TRACE_RESULT (current_cpu, "condbit", 'x', OPRND (condbit)); | |
853 | #if WITH_PROFILE_MODEL_P | |
854 | if (PROFILE_MODEL_P (current_cpu)) | |
855 | { | |
856 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
857 | m32rx_model_profile_insn (current_cpu, abuf); | |
858 | } | |
859 | #endif | |
860 | return new_pc; | |
861 | #undef OPRND | |
862 | #undef FLD | |
863 | } | |
864 | ||
865 | /* Perform cmpu: cmpu $src1,$src2. */ | |
866 | CIA | |
867 | SEM_FN_NAME (m32rx,cmpu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
868 | { | |
869 | #define FLD(f) abuf->fields.fmt_17_cmp.f | |
870 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_17_cmp.f | |
871 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
872 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
873 | CPU (h_cond) = LTUSI (OPRND (src1), OPRND (src2)); | |
874 | TRACE_RESULT (current_cpu, "condbit", 'x', OPRND (condbit)); | |
875 | #if WITH_PROFILE_MODEL_P | |
876 | if (PROFILE_MODEL_P (current_cpu)) | |
877 | { | |
878 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
879 | m32rx_model_profile_insn (current_cpu, abuf); | |
880 | } | |
881 | #endif | |
882 | return new_pc; | |
883 | #undef OPRND | |
884 | #undef FLD | |
885 | } | |
886 | ||
887 | /* Perform cmpui: cmpui $src2,#$uimm16. */ | |
888 | CIA | |
889 | SEM_FN_NAME (m32rx,cmpui) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
890 | { | |
891 | #define FLD(f) abuf->fields.fmt_19_cmpui.f | |
892 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_19_cmpui.f | |
893 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
894 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
895 | CPU (h_cond) = LTUSI (OPRND (src2), OPRND (uimm16)); | |
896 | TRACE_RESULT (current_cpu, "condbit", 'x', OPRND (condbit)); | |
897 | #if WITH_PROFILE_MODEL_P | |
898 | if (PROFILE_MODEL_P (current_cpu)) | |
899 | { | |
900 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
901 | m32rx_model_profile_insn (current_cpu, abuf); | |
902 | } | |
903 | #endif | |
904 | return new_pc; | |
905 | #undef OPRND | |
906 | #undef FLD | |
907 | } | |
908 | ||
909 | /* Perform cmpeq: cmpeq $src1,$src2. */ | |
910 | CIA | |
911 | SEM_FN_NAME (m32rx,cmpeq) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
912 | { | |
913 | #define FLD(f) abuf->fields.fmt_17_cmp.f | |
914 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_17_cmp.f | |
915 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
916 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
917 | CPU (h_cond) = EQSI (OPRND (src1), OPRND (src2)); | |
918 | TRACE_RESULT (current_cpu, "condbit", 'x', OPRND (condbit)); | |
919 | #if WITH_PROFILE_MODEL_P | |
920 | if (PROFILE_MODEL_P (current_cpu)) | |
921 | { | |
922 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
923 | m32rx_model_profile_insn (current_cpu, abuf); | |
924 | } | |
925 | #endif | |
926 | return new_pc; | |
927 | #undef OPRND | |
928 | #undef FLD | |
929 | } | |
930 | ||
931 | /* Perform cmpz: cmpz $src2. */ | |
932 | CIA | |
933 | SEM_FN_NAME (m32rx,cmpz) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
934 | { | |
935 | #define FLD(f) abuf->fields.fmt_20_cmpz.f | |
936 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_20_cmpz.f | |
937 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
938 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
939 | CPU (h_cond) = EQSI (OPRND (src2), 0); | |
940 | TRACE_RESULT (current_cpu, "condbit", 'x', OPRND (condbit)); | |
941 | #if WITH_PROFILE_MODEL_P | |
942 | if (PROFILE_MODEL_P (current_cpu)) | |
943 | { | |
944 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
945 | m32rx_model_profile_insn (current_cpu, abuf); | |
946 | } | |
947 | #endif | |
948 | return new_pc; | |
949 | #undef OPRND | |
950 | #undef FLD | |
951 | } | |
952 | ||
953 | /* Perform div: div $dr,$sr. */ | |
954 | CIA | |
955 | SEM_FN_NAME (m32rx,div) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
956 | { | |
957 | #define FLD(f) abuf->fields.fmt_21_div.f | |
958 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_21_div.f | |
959 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
960 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
961 | if (NESI (OPRND (sr), 0)) { | |
962 | CPU (h_gr[f_r1]) = DIVSI (OPRND (dr), OPRND (sr)); | |
963 | TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr)); | |
964 | } | |
965 | #if WITH_PROFILE_MODEL_P | |
966 | if (PROFILE_MODEL_P (current_cpu)) | |
967 | { | |
968 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
969 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
970 | m32rx_model_profile_insn (current_cpu, abuf); | |
971 | } | |
972 | #endif | |
973 | return new_pc; | |
974 | #undef OPRND | |
975 | #undef FLD | |
976 | } | |
977 | ||
978 | /* Perform divu: divu $dr,$sr. */ | |
979 | CIA | |
980 | SEM_FN_NAME (m32rx,divu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
981 | { | |
982 | #define FLD(f) abuf->fields.fmt_21_div.f | |
983 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_21_div.f | |
984 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
985 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
986 | if (NESI (OPRND (sr), 0)) { | |
987 | CPU (h_gr[f_r1]) = UDIVSI (OPRND (dr), OPRND (sr)); | |
988 | TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr)); | |
989 | } | |
990 | #if WITH_PROFILE_MODEL_P | |
991 | if (PROFILE_MODEL_P (current_cpu)) | |
992 | { | |
993 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
994 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
995 | m32rx_model_profile_insn (current_cpu, abuf); | |
996 | } | |
997 | #endif | |
998 | return new_pc; | |
999 | #undef OPRND | |
1000 | #undef FLD | |
1001 | } | |
1002 | ||
1003 | /* Perform rem: rem $dr,$sr. */ | |
1004 | CIA | |
1005 | SEM_FN_NAME (m32rx,rem) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1006 | { | |
1007 | #define FLD(f) abuf->fields.fmt_21_div.f | |
1008 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_21_div.f | |
1009 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1010 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
1011 | if (NESI (OPRND (sr), 0)) { | |
1012 | CPU (h_gr[f_r1]) = MODSI (OPRND (dr), OPRND (sr)); | |
1013 | TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr)); | |
1014 | } | |
1015 | #if WITH_PROFILE_MODEL_P | |
1016 | if (PROFILE_MODEL_P (current_cpu)) | |
1017 | { | |
1018 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
1019 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
1020 | m32rx_model_profile_insn (current_cpu, abuf); | |
1021 | } | |
1022 | #endif | |
1023 | return new_pc; | |
1024 | #undef OPRND | |
1025 | #undef FLD | |
1026 | } | |
1027 | ||
1028 | /* Perform remu: remu $dr,$sr. */ | |
1029 | CIA | |
1030 | SEM_FN_NAME (m32rx,remu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1031 | { | |
1032 | #define FLD(f) abuf->fields.fmt_21_div.f | |
1033 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_21_div.f | |
1034 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1035 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
1036 | if (NESI (OPRND (sr), 0)) { | |
1037 | CPU (h_gr[f_r1]) = UMODSI (OPRND (dr), OPRND (sr)); | |
1038 | TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr)); | |
1039 | } | |
1040 | #if WITH_PROFILE_MODEL_P | |
1041 | if (PROFILE_MODEL_P (current_cpu)) | |
1042 | { | |
1043 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
1044 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
1045 | m32rx_model_profile_insn (current_cpu, abuf); | |
1046 | } | |
1047 | #endif | |
1048 | return new_pc; | |
1049 | #undef OPRND | |
1050 | #undef FLD | |
1051 | } | |
1052 | ||
1053 | /* Perform jc: jc $sr. */ | |
1054 | CIA | |
1055 | SEM_FN_NAME (m32rx,jc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1056 | { | |
1057 | #define FLD(f) abuf->fields.fmt_22_jc.f | |
1058 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_22_jc.f | |
1059 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1060 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
1061 | int taken_p = 0; | |
1062 | if (OPRND (condbit)) { | |
1063 | BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, ANDSI (OPRND (sr), -4))); | |
1064 | } | |
1065 | #if WITH_PROFILE_MODEL_P | |
1066 | if (PROFILE_MODEL_P (current_cpu)) | |
1067 | { | |
1068 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
1069 | m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p); | |
1070 | } | |
1071 | #endif | |
1072 | return new_pc; | |
1073 | #undef OPRND | |
1074 | #undef FLD | |
1075 | } | |
1076 | ||
1077 | /* Perform jnc: jnc $sr. */ | |
1078 | CIA | |
1079 | SEM_FN_NAME (m32rx,jnc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1080 | { | |
1081 | #define FLD(f) abuf->fields.fmt_22_jc.f | |
1082 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_22_jc.f | |
1083 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1084 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
1085 | int taken_p = 0; | |
1086 | if (NOTBI (OPRND (condbit))) { | |
1087 | BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, ANDSI (OPRND (sr), -4))); | |
1088 | } | |
1089 | #if WITH_PROFILE_MODEL_P | |
1090 | if (PROFILE_MODEL_P (current_cpu)) | |
1091 | { | |
1092 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
1093 | m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p); | |
1094 | } | |
1095 | #endif | |
1096 | return new_pc; | |
1097 | #undef OPRND | |
1098 | #undef FLD | |
1099 | } | |
1100 | ||
1101 | /* Perform jl: jl $sr. */ | |
1102 | CIA | |
1103 | SEM_FN_NAME (m32rx,jl) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1104 | { | |
1105 | #define FLD(f) abuf->fields.fmt_23_jl.f | |
1106 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_23_jl.f | |
1107 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1108 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
1109 | int taken_p = 0; | |
1110 | do { | |
1111 | USI temp1;SI temp0; | |
1112 | temp0 = ADDSI (ANDSI (OPRND (pc), -4), 4); | |
1113 | temp1 = OPRND (sr); | |
1114 | CPU (h_gr[14]) = temp0; | |
1115 | TRACE_RESULT (current_cpu, "h-gr", 'x', OPRND (h_gr)); | |
1116 | BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, temp1)); | |
1117 | } while (0); | |
1118 | #if WITH_PROFILE_MODEL_P | |
1119 | if (PROFILE_MODEL_P (current_cpu)) | |
1120 | { | |
1121 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
1122 | m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p); | |
1123 | } | |
1124 | #endif | |
1125 | return new_pc; | |
1126 | #undef OPRND | |
1127 | #undef FLD | |
1128 | } | |
1129 | ||
1130 | /* Perform jmp: jmp $sr. */ | |
1131 | CIA | |
1132 | SEM_FN_NAME (m32rx,jmp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1133 | { | |
1134 | #define FLD(f) abuf->fields.fmt_24_jmp.f | |
1135 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_24_jmp.f | |
1136 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1137 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
1138 | int taken_p = 0; | |
1139 | BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, OPRND (sr))); | |
1140 | #if WITH_PROFILE_MODEL_P | |
1141 | if (PROFILE_MODEL_P (current_cpu)) | |
1142 | { | |
1143 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
1144 | m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p); | |
1145 | } | |
1146 | #endif | |
1147 | return new_pc; | |
1148 | #undef OPRND | |
1149 | #undef FLD | |
1150 | } | |
1151 | ||
1152 | /* Perform ld: ld $dr,@$sr. */ | |
1153 | CIA | |
1154 | SEM_FN_NAME (m32rx,ld) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1155 | { | |
1156 | #define FLD(f) abuf->fields.fmt_25_ld.f | |
1157 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_25_ld.f | |
1158 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1159 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
1160 | CPU (h_gr[f_r1]) = OPRND (h_memory); | |
1161 | TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr)); | |
1162 | #if WITH_PROFILE_MODEL_P | |
1163 | if (PROFILE_MODEL_P (current_cpu)) | |
1164 | { | |
1165 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
1166 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
1167 | m32rx_model_profile_insn (current_cpu, abuf); | |
1168 | } | |
1169 | #endif | |
1170 | return new_pc; | |
1171 | #undef OPRND | |
1172 | #undef FLD | |
1173 | } | |
1174 | ||
1175 | /* Perform ld-d: ld $dr,@($slo16,$sr). */ | |
1176 | CIA | |
1177 | SEM_FN_NAME (m32rx,ld_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1178 | { | |
1179 | #define FLD(f) abuf->fields.fmt_26_ld_d.f | |
1180 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_26_ld_d.f | |
1181 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1182 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
1183 | CPU (h_gr[f_r1]) = OPRND (h_memory); | |
1184 | TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr)); | |
1185 | #if WITH_PROFILE_MODEL_P | |
1186 | if (PROFILE_MODEL_P (current_cpu)) | |
1187 | { | |
1188 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
1189 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
1190 | m32rx_model_profile_insn (current_cpu, abuf); | |
1191 | } | |
1192 | #endif | |
1193 | return new_pc; | |
1194 | #undef OPRND | |
1195 | #undef FLD | |
1196 | } | |
1197 | ||
1198 | /* Perform ldb: ldb $dr,@$sr. */ | |
1199 | CIA | |
1200 | SEM_FN_NAME (m32rx,ldb) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1201 | { | |
1202 | #define FLD(f) abuf->fields.fmt_27_ldb.f | |
1203 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_27_ldb.f | |
1204 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1205 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
1206 | CPU (h_gr[f_r1]) = EXTQISI (OPRND (h_memory)); | |
1207 | TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr)); | |
1208 | #if WITH_PROFILE_MODEL_P | |
1209 | if (PROFILE_MODEL_P (current_cpu)) | |
1210 | { | |
1211 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
1212 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
1213 | m32rx_model_profile_insn (current_cpu, abuf); | |
1214 | } | |
1215 | #endif | |
1216 | return new_pc; | |
1217 | #undef OPRND | |
1218 | #undef FLD | |
1219 | } | |
1220 | ||
1221 | /* Perform ldb-d: ldb $dr,@($slo16,$sr). */ | |
1222 | CIA | |
1223 | SEM_FN_NAME (m32rx,ldb_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1224 | { | |
1225 | #define FLD(f) abuf->fields.fmt_28_ldb_d.f | |
1226 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_28_ldb_d.f | |
1227 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1228 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
1229 | CPU (h_gr[f_r1]) = EXTQISI (OPRND (h_memory)); | |
1230 | TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr)); | |
1231 | #if WITH_PROFILE_MODEL_P | |
1232 | if (PROFILE_MODEL_P (current_cpu)) | |
1233 | { | |
1234 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
1235 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
1236 | m32rx_model_profile_insn (current_cpu, abuf); | |
1237 | } | |
1238 | #endif | |
1239 | return new_pc; | |
1240 | #undef OPRND | |
1241 | #undef FLD | |
1242 | } | |
1243 | ||
1244 | /* Perform ldh: ldh $dr,@$sr. */ | |
1245 | CIA | |
1246 | SEM_FN_NAME (m32rx,ldh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1247 | { | |
1248 | #define FLD(f) abuf->fields.fmt_29_ldh.f | |
1249 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_29_ldh.f | |
1250 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1251 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
1252 | CPU (h_gr[f_r1]) = EXTHISI (OPRND (h_memory)); | |
1253 | TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr)); | |
1254 | #if WITH_PROFILE_MODEL_P | |
1255 | if (PROFILE_MODEL_P (current_cpu)) | |
1256 | { | |
1257 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
1258 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
1259 | m32rx_model_profile_insn (current_cpu, abuf); | |
1260 | } | |
1261 | #endif | |
1262 | return new_pc; | |
1263 | #undef OPRND | |
1264 | #undef FLD | |
1265 | } | |
1266 | ||
1267 | /* Perform ldh-d: ldh $dr,@($slo16,$sr). */ | |
1268 | CIA | |
1269 | SEM_FN_NAME (m32rx,ldh_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1270 | { | |
1271 | #define FLD(f) abuf->fields.fmt_30_ldh_d.f | |
1272 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_30_ldh_d.f | |
1273 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1274 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
1275 | CPU (h_gr[f_r1]) = EXTHISI (OPRND (h_memory)); | |
1276 | TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr)); | |
1277 | #if WITH_PROFILE_MODEL_P | |
1278 | if (PROFILE_MODEL_P (current_cpu)) | |
1279 | { | |
1280 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
1281 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
1282 | m32rx_model_profile_insn (current_cpu, abuf); | |
1283 | } | |
1284 | #endif | |
1285 | return new_pc; | |
1286 | #undef OPRND | |
1287 | #undef FLD | |
1288 | } | |
1289 | ||
1290 | /* Perform ldub: ldub $dr,@$sr. */ | |
1291 | CIA | |
1292 | SEM_FN_NAME (m32rx,ldub) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1293 | { | |
1294 | #define FLD(f) abuf->fields.fmt_27_ldb.f | |
1295 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_27_ldb.f | |
1296 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1297 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
1298 | CPU (h_gr[f_r1]) = ZEXTQISI (OPRND (h_memory)); | |
1299 | TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr)); | |
1300 | #if WITH_PROFILE_MODEL_P | |
1301 | if (PROFILE_MODEL_P (current_cpu)) | |
1302 | { | |
1303 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
1304 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
1305 | m32rx_model_profile_insn (current_cpu, abuf); | |
1306 | } | |
1307 | #endif | |
1308 | return new_pc; | |
1309 | #undef OPRND | |
1310 | #undef FLD | |
1311 | } | |
1312 | ||
1313 | /* Perform ldub-d: ldub $dr,@($slo16,$sr). */ | |
1314 | CIA | |
1315 | SEM_FN_NAME (m32rx,ldub_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1316 | { | |
1317 | #define FLD(f) abuf->fields.fmt_28_ldb_d.f | |
1318 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_28_ldb_d.f | |
1319 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1320 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
1321 | CPU (h_gr[f_r1]) = ZEXTQISI (OPRND (h_memory)); | |
1322 | TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr)); | |
1323 | #if WITH_PROFILE_MODEL_P | |
1324 | if (PROFILE_MODEL_P (current_cpu)) | |
1325 | { | |
1326 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
1327 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
1328 | m32rx_model_profile_insn (current_cpu, abuf); | |
1329 | } | |
1330 | #endif | |
1331 | return new_pc; | |
1332 | #undef OPRND | |
1333 | #undef FLD | |
1334 | } | |
1335 | ||
1336 | /* Perform lduh: lduh $dr,@$sr. */ | |
1337 | CIA | |
1338 | SEM_FN_NAME (m32rx,lduh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1339 | { | |
1340 | #define FLD(f) abuf->fields.fmt_29_ldh.f | |
1341 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_29_ldh.f | |
1342 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1343 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
1344 | CPU (h_gr[f_r1]) = ZEXTHISI (OPRND (h_memory)); | |
1345 | TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr)); | |
1346 | #if WITH_PROFILE_MODEL_P | |
1347 | if (PROFILE_MODEL_P (current_cpu)) | |
1348 | { | |
1349 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
1350 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
1351 | m32rx_model_profile_insn (current_cpu, abuf); | |
1352 | } | |
1353 | #endif | |
1354 | return new_pc; | |
1355 | #undef OPRND | |
1356 | #undef FLD | |
1357 | } | |
1358 | ||
1359 | /* Perform lduh-d: lduh $dr,@($slo16,$sr). */ | |
1360 | CIA | |
1361 | SEM_FN_NAME (m32rx,lduh_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1362 | { | |
1363 | #define FLD(f) abuf->fields.fmt_30_ldh_d.f | |
1364 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_30_ldh_d.f | |
1365 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1366 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
1367 | CPU (h_gr[f_r1]) = ZEXTHISI (OPRND (h_memory)); | |
1368 | TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr)); | |
1369 | #if WITH_PROFILE_MODEL_P | |
1370 | if (PROFILE_MODEL_P (current_cpu)) | |
1371 | { | |
1372 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
1373 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
1374 | m32rx_model_profile_insn (current_cpu, abuf); | |
1375 | } | |
1376 | #endif | |
1377 | return new_pc; | |
1378 | #undef OPRND | |
1379 | #undef FLD | |
1380 | } | |
1381 | ||
1382 | /* Perform ld-plus: ld $dr,@$sr+. */ | |
1383 | CIA | |
1384 | SEM_FN_NAME (m32rx,ld_plus) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1385 | { | |
1386 | #define FLD(f) abuf->fields.fmt_25_ld.f | |
1387 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_25_ld.f | |
1388 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1389 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
1390 | do { | |
1391 | SI temp1;SI temp0; | |
1392 | temp0 = OPRND (h_memory); | |
1393 | temp1 = ADDSI (OPRND (sr), 4); | |
1394 | CPU (h_gr[f_r1]) = temp0; | |
1395 | TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr)); | |
1396 | CPU (h_gr[f_r2]) = temp1; | |
1397 | TRACE_RESULT (current_cpu, "sr", 'x', OPRND (sr)); | |
1398 | } while (0); | |
1399 | #if WITH_PROFILE_MODEL_P | |
1400 | if (PROFILE_MODEL_P (current_cpu)) | |
1401 | { | |
1402 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
1403 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
1404 | m32rx_model_profile_insn (current_cpu, abuf); | |
1405 | } | |
1406 | #endif | |
1407 | return new_pc; | |
1408 | #undef OPRND | |
1409 | #undef FLD | |
1410 | } | |
1411 | ||
1412 | /* Perform ld24: ld24 $dr,#$uimm24. */ | |
1413 | CIA | |
1414 | SEM_FN_NAME (m32rx,ld24) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1415 | { | |
1416 | #define FLD(f) abuf->fields.fmt_31_ld24.f | |
1417 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_31_ld24.f | |
1418 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1419 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
1420 | CPU (h_gr[f_r1]) = OPRND (uimm24); | |
1421 | TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr)); | |
1422 | #if WITH_PROFILE_MODEL_P | |
1423 | if (PROFILE_MODEL_P (current_cpu)) | |
1424 | { | |
1425 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
1426 | m32rx_model_profile_insn (current_cpu, abuf); | |
1427 | } | |
1428 | #endif | |
1429 | return new_pc; | |
1430 | #undef OPRND | |
1431 | #undef FLD | |
1432 | } | |
1433 | ||
1434 | /* Perform ldi8: ldi $dr,#$simm8. */ | |
1435 | CIA | |
1436 | SEM_FN_NAME (m32rx,ldi8) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1437 | { | |
1438 | #define FLD(f) abuf->fields.fmt_32_ldi8.f | |
1439 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_32_ldi8.f | |
1440 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1441 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
1442 | CPU (h_gr[f_r1]) = OPRND (simm8); | |
1443 | TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr)); | |
1444 | #if WITH_PROFILE_MODEL_P | |
1445 | if (PROFILE_MODEL_P (current_cpu)) | |
1446 | { | |
1447 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
1448 | m32rx_model_profile_insn (current_cpu, abuf); | |
1449 | } | |
1450 | #endif | |
1451 | return new_pc; | |
1452 | #undef OPRND | |
1453 | #undef FLD | |
1454 | } | |
1455 | ||
1456 | /* Perform ldi16: ldi $dr,$slo16. */ | |
1457 | CIA | |
1458 | SEM_FN_NAME (m32rx,ldi16) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1459 | { | |
1460 | #define FLD(f) abuf->fields.fmt_33_ldi16.f | |
1461 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_33_ldi16.f | |
1462 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1463 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
1464 | CPU (h_gr[f_r1]) = OPRND (slo16); | |
1465 | TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr)); | |
1466 | #if WITH_PROFILE_MODEL_P | |
1467 | if (PROFILE_MODEL_P (current_cpu)) | |
1468 | { | |
1469 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
1470 | m32rx_model_profile_insn (current_cpu, abuf); | |
1471 | } | |
1472 | #endif | |
1473 | return new_pc; | |
1474 | #undef OPRND | |
1475 | #undef FLD | |
1476 | } | |
1477 | ||
1478 | /* Perform lock: lock $dr,@$sr. */ | |
1479 | CIA | |
1480 | SEM_FN_NAME (m32rx,lock) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1481 | { | |
1482 | #define FLD(f) abuf->fields.fmt_0_add.f | |
1483 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_0_add.f | |
1484 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1485 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
1486 | do_lock (current_cpu, OPRND (dr), OPRND (sr)); | |
1487 | #if WITH_PROFILE_MODEL_P | |
1488 | if (PROFILE_MODEL_P (current_cpu)) | |
1489 | { | |
1490 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
1491 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
1492 | m32rx_model_profile_insn (current_cpu, abuf); | |
1493 | } | |
1494 | #endif | |
1495 | return new_pc; | |
1496 | #undef OPRND | |
1497 | #undef FLD | |
1498 | } | |
1499 | ||
1500 | /* Perform machi: machi $src1,$src2. */ | |
1501 | CIA | |
1502 | SEM_FN_NAME (m32rx,machi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1503 | { | |
1504 | #define FLD(f) abuf->fields.fmt_34_machi.f | |
1505 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_34_machi.f | |
1506 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1507 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
1508 | CPU (h_accum) = SRADI (SLLDI (ADDDI (OPRND (accum), MULDI (EXTSIDI (ANDSI (OPRND (src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (OPRND (src2), 16))))), 8), 8); | |
1509 | TRACE_RESULT (current_cpu, "accum", 'D', OPRND (accum)); | |
1510 | #if WITH_PROFILE_MODEL_P | |
1511 | if (PROFILE_MODEL_P (current_cpu)) | |
1512 | { | |
1513 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
1514 | m32rx_model_profile_insn (current_cpu, abuf); | |
1515 | } | |
1516 | #endif | |
1517 | return new_pc; | |
1518 | #undef OPRND | |
1519 | #undef FLD | |
1520 | } | |
1521 | ||
1522 | /* Perform machi-a: machi $src1,$src2,$acc. */ | |
1523 | CIA | |
1524 | SEM_FN_NAME (m32rx,machi_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1525 | { | |
1526 | #define FLD(f) abuf->fields.fmt_35_machi_a.f | |
1527 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_35_machi_a.f | |
1528 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1529 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
1530 | m32rx_h_accums_set (current_cpu, f_acc, SRADI (SLLDI (ADDDI (OPRND (acc), MULDI (EXTSIDI (ANDSI (OPRND (src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (OPRND (src2), 16))))), 8), 8)); | |
1531 | TRACE_RESULT (current_cpu, "acc", 'D', OPRND (acc)); | |
1532 | #if WITH_PROFILE_MODEL_P | |
1533 | if (PROFILE_MODEL_P (current_cpu)) | |
1534 | { | |
1535 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
1536 | m32rx_model_profile_insn (current_cpu, abuf); | |
1537 | } | |
1538 | #endif | |
1539 | return new_pc; | |
1540 | #undef OPRND | |
1541 | #undef FLD | |
1542 | } | |
1543 | ||
1544 | /* Perform maclo: maclo $src1,$src2. */ | |
1545 | CIA | |
1546 | SEM_FN_NAME (m32rx,maclo) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1547 | { | |
1548 | #define FLD(f) abuf->fields.fmt_34_machi.f | |
1549 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_34_machi.f | |
1550 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1551 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
1552 | CPU (h_accum) = SRADI (SLLDI (ADDDI (OPRND (accum), MULDI (EXTSIDI (SLLSI (OPRND (src1), 16)), EXTHIDI (TRUNCSIHI (OPRND (src2))))), 8), 8); | |
1553 | TRACE_RESULT (current_cpu, "accum", 'D', OPRND (accum)); | |
1554 | #if WITH_PROFILE_MODEL_P | |
1555 | if (PROFILE_MODEL_P (current_cpu)) | |
1556 | { | |
1557 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
1558 | m32rx_model_profile_insn (current_cpu, abuf); | |
1559 | } | |
1560 | #endif | |
1561 | return new_pc; | |
1562 | #undef OPRND | |
1563 | #undef FLD | |
1564 | } | |
1565 | ||
1566 | /* Perform maclo-a: maclo $src1,$src2,$acc. */ | |
1567 | CIA | |
1568 | SEM_FN_NAME (m32rx,maclo_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1569 | { | |
1570 | #define FLD(f) abuf->fields.fmt_35_machi_a.f | |
1571 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_35_machi_a.f | |
1572 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1573 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
1574 | m32rx_h_accums_set (current_cpu, f_acc, SRADI (SLLDI (ADDDI (OPRND (acc), MULDI (EXTSIDI (SLLSI (OPRND (src1), 16)), EXTHIDI (TRUNCSIHI (OPRND (src2))))), 8), 8)); | |
1575 | TRACE_RESULT (current_cpu, "acc", 'D', OPRND (acc)); | |
1576 | #if WITH_PROFILE_MODEL_P | |
1577 | if (PROFILE_MODEL_P (current_cpu)) | |
1578 | { | |
1579 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
1580 | m32rx_model_profile_insn (current_cpu, abuf); | |
1581 | } | |
1582 | #endif | |
1583 | return new_pc; | |
1584 | #undef OPRND | |
1585 | #undef FLD | |
1586 | } | |
1587 | ||
1588 | /* Perform macwhi: macwhi $src1,$src2. */ | |
1589 | CIA | |
1590 | SEM_FN_NAME (m32rx,macwhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1591 | { | |
1592 | #define FLD(f) abuf->fields.fmt_34_machi.f | |
1593 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_34_machi.f | |
1594 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1595 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
1596 | CPU (h_accum) = SRADI (SLLDI (ADDDI (OPRND (accum), MULDI (EXTSIDI (OPRND (src1)), EXTHIDI (TRUNCSIHI (SRASI (OPRND (src2), 16))))), 8), 8); | |
1597 | TRACE_RESULT (current_cpu, "accum", 'D', OPRND (accum)); | |
1598 | #if WITH_PROFILE_MODEL_P | |
1599 | if (PROFILE_MODEL_P (current_cpu)) | |
1600 | { | |
1601 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
1602 | m32rx_model_profile_insn (current_cpu, abuf); | |
1603 | } | |
1604 | #endif | |
1605 | return new_pc; | |
1606 | #undef OPRND | |
1607 | #undef FLD | |
1608 | } | |
1609 | ||
1610 | /* Perform macwhi-a: macwhi $src1,$src2,$acc. */ | |
1611 | CIA | |
1612 | SEM_FN_NAME (m32rx,macwhi_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1613 | { | |
1614 | #define FLD(f) abuf->fields.fmt_35_machi_a.f | |
1615 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_35_machi_a.f | |
1616 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1617 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
1618 | m32rx_h_accums_set (current_cpu, f_acc, SRADI (SLLDI (ADDDI (OPRND (acc), MULDI (EXTSIDI (OPRND (src1)), EXTHIDI (TRUNCSIHI (SRASI (OPRND (src2), 16))))), 8), 8)); | |
1619 | TRACE_RESULT (current_cpu, "acc", 'D', OPRND (acc)); | |
1620 | #if WITH_PROFILE_MODEL_P | |
1621 | if (PROFILE_MODEL_P (current_cpu)) | |
1622 | { | |
1623 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
1624 | m32rx_model_profile_insn (current_cpu, abuf); | |
1625 | } | |
1626 | #endif | |
1627 | return new_pc; | |
1628 | #undef OPRND | |
1629 | #undef FLD | |
1630 | } | |
1631 | ||
1632 | /* Perform macwlo: macwlo $src1,$src2. */ | |
1633 | CIA | |
1634 | SEM_FN_NAME (m32rx,macwlo) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1635 | { | |
1636 | #define FLD(f) abuf->fields.fmt_34_machi.f | |
1637 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_34_machi.f | |
1638 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1639 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
1640 | CPU (h_accum) = SRADI (SLLDI (ADDDI (OPRND (accum), MULDI (EXTSIDI (OPRND (src1)), EXTHIDI (TRUNCSIHI (OPRND (src2))))), 8), 8); | |
1641 | TRACE_RESULT (current_cpu, "accum", 'D', OPRND (accum)); | |
1642 | #if WITH_PROFILE_MODEL_P | |
1643 | if (PROFILE_MODEL_P (current_cpu)) | |
1644 | { | |
1645 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
1646 | m32rx_model_profile_insn (current_cpu, abuf); | |
1647 | } | |
1648 | #endif | |
1649 | return new_pc; | |
1650 | #undef OPRND | |
1651 | #undef FLD | |
1652 | } | |
1653 | ||
1654 | /* Perform macwlo-a: macwlo $src1,$src2,$acc. */ | |
1655 | CIA | |
1656 | SEM_FN_NAME (m32rx,macwlo_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1657 | { | |
1658 | #define FLD(f) abuf->fields.fmt_35_machi_a.f | |
1659 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_35_machi_a.f | |
1660 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1661 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
1662 | m32rx_h_accums_set (current_cpu, f_acc, SRADI (SLLDI (ADDDI (OPRND (acc), MULDI (EXTSIDI (OPRND (src1)), EXTHIDI (TRUNCSIHI (OPRND (src2))))), 8), 8)); | |
1663 | TRACE_RESULT (current_cpu, "acc", 'D', OPRND (acc)); | |
1664 | #if WITH_PROFILE_MODEL_P | |
1665 | if (PROFILE_MODEL_P (current_cpu)) | |
1666 | { | |
1667 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
1668 | m32rx_model_profile_insn (current_cpu, abuf); | |
1669 | } | |
1670 | #endif | |
1671 | return new_pc; | |
1672 | #undef OPRND | |
1673 | #undef FLD | |
1674 | } | |
1675 | ||
1676 | /* Perform mul: mul $dr,$sr. */ | |
1677 | CIA | |
1678 | SEM_FN_NAME (m32rx,mul) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1679 | { | |
1680 | #define FLD(f) abuf->fields.fmt_0_add.f | |
1681 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_0_add.f | |
1682 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1683 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
1684 | CPU (h_gr[f_r1]) = MULSI (OPRND (dr), OPRND (sr)); | |
1685 | TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr)); | |
1686 | #if WITH_PROFILE_MODEL_P | |
1687 | if (PROFILE_MODEL_P (current_cpu)) | |
1688 | { | |
1689 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
1690 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
1691 | m32rx_model_profile_insn (current_cpu, abuf); | |
1692 | } | |
1693 | #endif | |
1694 | return new_pc; | |
1695 | #undef OPRND | |
1696 | #undef FLD | |
1697 | } | |
1698 | ||
1699 | /* Perform mulhi: mulhi $src1,$src2. */ | |
1700 | CIA | |
1701 | SEM_FN_NAME (m32rx,mulhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1702 | { | |
1703 | #define FLD(f) abuf->fields.fmt_17_cmp.f | |
1704 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_17_cmp.f | |
1705 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1706 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
1707 | CPU (h_accum) = SRADI (SLLDI (MULDI (EXTSIDI (ANDSI (OPRND (src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (OPRND (src2), 16)))), 16), 16); | |
1708 | TRACE_RESULT (current_cpu, "accum", 'D', OPRND (accum)); | |
1709 | #if WITH_PROFILE_MODEL_P | |
1710 | if (PROFILE_MODEL_P (current_cpu)) | |
1711 | { | |
1712 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
1713 | m32rx_model_profile_insn (current_cpu, abuf); | |
1714 | } | |
1715 | #endif | |
1716 | return new_pc; | |
1717 | #undef OPRND | |
1718 | #undef FLD | |
1719 | } | |
1720 | ||
1721 | /* Perform mulhi-a: mulhi $src1,$src2,$acc. */ | |
1722 | CIA | |
1723 | SEM_FN_NAME (m32rx,mulhi_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1724 | { | |
1725 | #define FLD(f) abuf->fields.fmt_36_mulhi_a.f | |
1726 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_36_mulhi_a.f | |
1727 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1728 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
1729 | m32rx_h_accums_set (current_cpu, f_acc, SRADI (SLLDI (MULDI (EXTSIDI (ANDSI (OPRND (src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (OPRND (src2), 16)))), 16), 16)); | |
1730 | TRACE_RESULT (current_cpu, "acc", 'D', OPRND (acc)); | |
1731 | #if WITH_PROFILE_MODEL_P | |
1732 | if (PROFILE_MODEL_P (current_cpu)) | |
1733 | { | |
1734 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
1735 | m32rx_model_profile_insn (current_cpu, abuf); | |
1736 | } | |
1737 | #endif | |
1738 | return new_pc; | |
1739 | #undef OPRND | |
1740 | #undef FLD | |
1741 | } | |
1742 | ||
1743 | /* Perform mullo: mullo $src1,$src2. */ | |
1744 | CIA | |
1745 | SEM_FN_NAME (m32rx,mullo) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1746 | { | |
1747 | #define FLD(f) abuf->fields.fmt_17_cmp.f | |
1748 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_17_cmp.f | |
1749 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1750 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
1751 | CPU (h_accum) = SRADI (SLLDI (MULDI (EXTSIDI (SLLSI (OPRND (src1), 16)), EXTHIDI (TRUNCSIHI (OPRND (src2)))), 16), 16); | |
1752 | TRACE_RESULT (current_cpu, "accum", 'D', OPRND (accum)); | |
1753 | #if WITH_PROFILE_MODEL_P | |
1754 | if (PROFILE_MODEL_P (current_cpu)) | |
1755 | { | |
1756 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
1757 | m32rx_model_profile_insn (current_cpu, abuf); | |
1758 | } | |
1759 | #endif | |
1760 | return new_pc; | |
1761 | #undef OPRND | |
1762 | #undef FLD | |
1763 | } | |
1764 | ||
1765 | /* Perform mullo-a: mullo $src1,$src2,$acc. */ | |
1766 | CIA | |
1767 | SEM_FN_NAME (m32rx,mullo_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1768 | { | |
1769 | #define FLD(f) abuf->fields.fmt_36_mulhi_a.f | |
1770 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_36_mulhi_a.f | |
1771 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1772 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
1773 | m32rx_h_accums_set (current_cpu, f_acc, SRADI (SLLDI (MULDI (EXTSIDI (SLLSI (OPRND (src1), 16)), EXTHIDI (TRUNCSIHI (OPRND (src2)))), 16), 16)); | |
1774 | TRACE_RESULT (current_cpu, "acc", 'D', OPRND (acc)); | |
1775 | #if WITH_PROFILE_MODEL_P | |
1776 | if (PROFILE_MODEL_P (current_cpu)) | |
1777 | { | |
1778 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
1779 | m32rx_model_profile_insn (current_cpu, abuf); | |
1780 | } | |
1781 | #endif | |
1782 | return new_pc; | |
1783 | #undef OPRND | |
1784 | #undef FLD | |
1785 | } | |
1786 | ||
1787 | /* Perform mulwhi: mulwhi $src1,$src2. */ | |
1788 | CIA | |
1789 | SEM_FN_NAME (m32rx,mulwhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1790 | { | |
1791 | #define FLD(f) abuf->fields.fmt_17_cmp.f | |
1792 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_17_cmp.f | |
1793 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1794 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
1795 | CPU (h_accum) = SRADI (SLLDI (MULDI (EXTSIDI (OPRND (src1)), EXTHIDI (TRUNCSIHI (SRASI (OPRND (src2), 16)))), 8), 8); | |
1796 | TRACE_RESULT (current_cpu, "accum", 'D', OPRND (accum)); | |
1797 | #if WITH_PROFILE_MODEL_P | |
1798 | if (PROFILE_MODEL_P (current_cpu)) | |
1799 | { | |
1800 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
1801 | m32rx_model_profile_insn (current_cpu, abuf); | |
1802 | } | |
1803 | #endif | |
1804 | return new_pc; | |
1805 | #undef OPRND | |
1806 | #undef FLD | |
1807 | } | |
1808 | ||
1809 | /* Perform mulwhi-a: mulwhi $src1,$src2,$acc. */ | |
1810 | CIA | |
1811 | SEM_FN_NAME (m32rx,mulwhi_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1812 | { | |
1813 | #define FLD(f) abuf->fields.fmt_36_mulhi_a.f | |
1814 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_36_mulhi_a.f | |
1815 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1816 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
1817 | m32rx_h_accums_set (current_cpu, f_acc, SRADI (SLLDI (MULDI (EXTSIDI (OPRND (src1)), EXTHIDI (TRUNCSIHI (SRASI (OPRND (src2), 16)))), 8), 8)); | |
1818 | TRACE_RESULT (current_cpu, "acc", 'D', OPRND (acc)); | |
1819 | #if WITH_PROFILE_MODEL_P | |
1820 | if (PROFILE_MODEL_P (current_cpu)) | |
1821 | { | |
1822 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
1823 | m32rx_model_profile_insn (current_cpu, abuf); | |
1824 | } | |
1825 | #endif | |
1826 | return new_pc; | |
1827 | #undef OPRND | |
1828 | #undef FLD | |
1829 | } | |
1830 | ||
1831 | /* Perform mulwlo: mulwlo $src1,$src2. */ | |
1832 | CIA | |
1833 | SEM_FN_NAME (m32rx,mulwlo) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1834 | { | |
1835 | #define FLD(f) abuf->fields.fmt_17_cmp.f | |
1836 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_17_cmp.f | |
1837 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1838 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
1839 | CPU (h_accum) = SRADI (SLLDI (MULDI (EXTSIDI (OPRND (src1)), EXTHIDI (TRUNCSIHI (OPRND (src2)))), 8), 8); | |
1840 | TRACE_RESULT (current_cpu, "accum", 'D', OPRND (accum)); | |
1841 | #if WITH_PROFILE_MODEL_P | |
1842 | if (PROFILE_MODEL_P (current_cpu)) | |
1843 | { | |
1844 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
1845 | m32rx_model_profile_insn (current_cpu, abuf); | |
1846 | } | |
1847 | #endif | |
1848 | return new_pc; | |
1849 | #undef OPRND | |
1850 | #undef FLD | |
1851 | } | |
1852 | ||
1853 | /* Perform mulwlo-a: mulwlo $src1,$src2,$acc. */ | |
1854 | CIA | |
1855 | SEM_FN_NAME (m32rx,mulwlo_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1856 | { | |
1857 | #define FLD(f) abuf->fields.fmt_36_mulhi_a.f | |
1858 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_36_mulhi_a.f | |
1859 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1860 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
1861 | m32rx_h_accums_set (current_cpu, f_acc, SRADI (SLLDI (MULDI (EXTSIDI (OPRND (src1)), EXTHIDI (TRUNCSIHI (OPRND (src2)))), 8), 8)); | |
1862 | TRACE_RESULT (current_cpu, "acc", 'D', OPRND (acc)); | |
1863 | #if WITH_PROFILE_MODEL_P | |
1864 | if (PROFILE_MODEL_P (current_cpu)) | |
1865 | { | |
1866 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
1867 | m32rx_model_profile_insn (current_cpu, abuf); | |
1868 | } | |
1869 | #endif | |
1870 | return new_pc; | |
1871 | #undef OPRND | |
1872 | #undef FLD | |
1873 | } | |
1874 | ||
1875 | /* Perform mv: mv $dr,$sr. */ | |
1876 | CIA | |
1877 | SEM_FN_NAME (m32rx,mv) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1878 | { | |
1879 | #define FLD(f) abuf->fields.fmt_37_mv.f | |
1880 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_37_mv.f | |
1881 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1882 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
1883 | CPU (h_gr[f_r1]) = OPRND (sr); | |
1884 | TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr)); | |
1885 | #if WITH_PROFILE_MODEL_P | |
1886 | if (PROFILE_MODEL_P (current_cpu)) | |
1887 | { | |
1888 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
1889 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
1890 | m32rx_model_profile_insn (current_cpu, abuf); | |
1891 | } | |
1892 | #endif | |
1893 | return new_pc; | |
1894 | #undef OPRND | |
1895 | #undef FLD | |
1896 | } | |
1897 | ||
1898 | /* Perform mvfachi: mvfachi $dr. */ | |
1899 | CIA | |
1900 | SEM_FN_NAME (m32rx,mvfachi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1901 | { | |
1902 | #define FLD(f) abuf->fields.fmt_38_mvfachi.f | |
1903 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_38_mvfachi.f | |
1904 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1905 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
1906 | CPU (h_gr[f_r1]) = TRUNCDISI (SRADI (OPRND (accum), 32)); | |
1907 | TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr)); | |
1908 | #if WITH_PROFILE_MODEL_P | |
1909 | if (PROFILE_MODEL_P (current_cpu)) | |
1910 | { | |
1911 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
1912 | m32rx_model_profile_insn (current_cpu, abuf); | |
1913 | } | |
1914 | #endif | |
1915 | return new_pc; | |
1916 | #undef OPRND | |
1917 | #undef FLD | |
1918 | } | |
1919 | ||
1920 | /* Perform mvfachi-a: mvfachi $dr,$accs. */ | |
1921 | CIA | |
1922 | SEM_FN_NAME (m32rx,mvfachi_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1923 | { | |
1924 | #define FLD(f) abuf->fields.fmt_39_mvfachi_a.f | |
1925 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_39_mvfachi_a.f | |
1926 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1927 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
1928 | CPU (h_gr[f_r1]) = TRUNCDISI (SRADI (OPRND (accs), 32)); | |
1929 | TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr)); | |
1930 | #if WITH_PROFILE_MODEL_P | |
1931 | if (PROFILE_MODEL_P (current_cpu)) | |
1932 | { | |
1933 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
1934 | m32rx_model_profile_insn (current_cpu, abuf); | |
1935 | } | |
1936 | #endif | |
1937 | return new_pc; | |
1938 | #undef OPRND | |
1939 | #undef FLD | |
1940 | } | |
1941 | ||
1942 | /* Perform mvfaclo: mvfaclo $dr. */ | |
1943 | CIA | |
1944 | SEM_FN_NAME (m32rx,mvfaclo) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1945 | { | |
1946 | #define FLD(f) abuf->fields.fmt_38_mvfachi.f | |
1947 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_38_mvfachi.f | |
1948 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1949 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
1950 | CPU (h_gr[f_r1]) = TRUNCDISI (OPRND (accum)); | |
1951 | TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr)); | |
1952 | #if WITH_PROFILE_MODEL_P | |
1953 | if (PROFILE_MODEL_P (current_cpu)) | |
1954 | { | |
1955 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
1956 | m32rx_model_profile_insn (current_cpu, abuf); | |
1957 | } | |
1958 | #endif | |
1959 | return new_pc; | |
1960 | #undef OPRND | |
1961 | #undef FLD | |
1962 | } | |
1963 | ||
1964 | /* Perform mvfaclo-a: mvfaclo $dr,$accs. */ | |
1965 | CIA | |
1966 | SEM_FN_NAME (m32rx,mvfaclo_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1967 | { | |
1968 | #define FLD(f) abuf->fields.fmt_39_mvfachi_a.f | |
1969 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_39_mvfachi_a.f | |
1970 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1971 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
1972 | CPU (h_gr[f_r1]) = TRUNCDISI (OPRND (accs)); | |
1973 | TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr)); | |
1974 | #if WITH_PROFILE_MODEL_P | |
1975 | if (PROFILE_MODEL_P (current_cpu)) | |
1976 | { | |
1977 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
1978 | m32rx_model_profile_insn (current_cpu, abuf); | |
1979 | } | |
1980 | #endif | |
1981 | return new_pc; | |
1982 | #undef OPRND | |
1983 | #undef FLD | |
1984 | } | |
1985 | ||
1986 | /* Perform mvfacmi: mvfacmi $dr. */ | |
1987 | CIA | |
1988 | SEM_FN_NAME (m32rx,mvfacmi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1989 | { | |
1990 | #define FLD(f) abuf->fields.fmt_38_mvfachi.f | |
1991 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_38_mvfachi.f | |
1992 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1993 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
1994 | CPU (h_gr[f_r1]) = TRUNCDISI (SRADI (OPRND (accum), 16)); | |
1995 | TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr)); | |
1996 | #if WITH_PROFILE_MODEL_P | |
1997 | if (PROFILE_MODEL_P (current_cpu)) | |
1998 | { | |
1999 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
2000 | m32rx_model_profile_insn (current_cpu, abuf); | |
2001 | } | |
2002 | #endif | |
2003 | return new_pc; | |
2004 | #undef OPRND | |
2005 | #undef FLD | |
2006 | } | |
2007 | ||
2008 | /* Perform mvfacmi-a: mvfacmi $dr,$accs. */ | |
2009 | CIA | |
2010 | SEM_FN_NAME (m32rx,mvfacmi_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2011 | { | |
2012 | #define FLD(f) abuf->fields.fmt_39_mvfachi_a.f | |
2013 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_39_mvfachi_a.f | |
2014 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2015 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
2016 | CPU (h_gr[f_r1]) = TRUNCDISI (SRADI (OPRND (accs), 16)); | |
2017 | TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr)); | |
2018 | #if WITH_PROFILE_MODEL_P | |
2019 | if (PROFILE_MODEL_P (current_cpu)) | |
2020 | { | |
2021 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
2022 | m32rx_model_profile_insn (current_cpu, abuf); | |
2023 | } | |
2024 | #endif | |
2025 | return new_pc; | |
2026 | #undef OPRND | |
2027 | #undef FLD | |
2028 | } | |
2029 | ||
2030 | /* Perform mvfc: mvfc $dr,$scr. */ | |
2031 | CIA | |
2032 | SEM_FN_NAME (m32rx,mvfc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2033 | { | |
2034 | #define FLD(f) abuf->fields.fmt_40_mvfc.f | |
2035 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_40_mvfc.f | |
2036 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2037 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
2038 | CPU (h_gr[f_r1]) = OPRND (scr); | |
2039 | TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr)); | |
2040 | #if WITH_PROFILE_MODEL_P | |
2041 | if (PROFILE_MODEL_P (current_cpu)) | |
2042 | { | |
2043 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
2044 | m32rx_model_profile_insn (current_cpu, abuf); | |
2045 | } | |
2046 | #endif | |
2047 | return new_pc; | |
2048 | #undef OPRND | |
2049 | #undef FLD | |
2050 | } | |
2051 | ||
2052 | /* Perform mvtachi: mvtachi $src1. */ | |
2053 | CIA | |
2054 | SEM_FN_NAME (m32rx,mvtachi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2055 | { | |
2056 | #define FLD(f) abuf->fields.fmt_41_mvtachi.f | |
2057 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_41_mvtachi.f | |
2058 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2059 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
2060 | CPU (h_accum) = ORDI (ANDDI (OPRND (accum), MAKEDI (0, 0xffffffff)), SLLDI (EXTSIDI (OPRND (src1)), 32)); | |
2061 | TRACE_RESULT (current_cpu, "accum", 'D', OPRND (accum)); | |
2062 | #if WITH_PROFILE_MODEL_P | |
2063 | if (PROFILE_MODEL_P (current_cpu)) | |
2064 | { | |
2065 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
2066 | m32rx_model_profile_insn (current_cpu, abuf); | |
2067 | } | |
2068 | #endif | |
2069 | return new_pc; | |
2070 | #undef OPRND | |
2071 | #undef FLD | |
2072 | } | |
2073 | ||
2074 | /* Perform mvtachi-a: mvtachi $src1,$accs. */ | |
2075 | CIA | |
2076 | SEM_FN_NAME (m32rx,mvtachi_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2077 | { | |
2078 | #define FLD(f) abuf->fields.fmt_42_mvtachi_a.f | |
2079 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_42_mvtachi_a.f | |
2080 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2081 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
2082 | m32rx_h_accums_set (current_cpu, f_accs, ORDI (ANDDI (OPRND (accs), MAKEDI (0, 0xffffffff)), SLLDI (EXTSIDI (OPRND (src1)), 32))); | |
2083 | TRACE_RESULT (current_cpu, "accs", 'D', OPRND (accs)); | |
2084 | #if WITH_PROFILE_MODEL_P | |
2085 | if (PROFILE_MODEL_P (current_cpu)) | |
2086 | { | |
2087 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
2088 | m32rx_model_profile_insn (current_cpu, abuf); | |
2089 | } | |
2090 | #endif | |
2091 | return new_pc; | |
2092 | #undef OPRND | |
2093 | #undef FLD | |
2094 | } | |
2095 | ||
2096 | /* Perform mvtaclo: mvtaclo $src1. */ | |
2097 | CIA | |
2098 | SEM_FN_NAME (m32rx,mvtaclo) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2099 | { | |
2100 | #define FLD(f) abuf->fields.fmt_41_mvtachi.f | |
2101 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_41_mvtachi.f | |
2102 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2103 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
2104 | CPU (h_accum) = ORDI (ANDDI (OPRND (accum), MAKEDI (0xffffffff, 0)), EXTSIDI (OPRND (src1))); | |
2105 | TRACE_RESULT (current_cpu, "accum", 'D', OPRND (accum)); | |
2106 | #if WITH_PROFILE_MODEL_P | |
2107 | if (PROFILE_MODEL_P (current_cpu)) | |
2108 | { | |
2109 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
2110 | m32rx_model_profile_insn (current_cpu, abuf); | |
2111 | } | |
2112 | #endif | |
2113 | return new_pc; | |
2114 | #undef OPRND | |
2115 | #undef FLD | |
2116 | } | |
2117 | ||
2118 | /* Perform mvtaclo-a: mvtaclo $src1,$accs. */ | |
2119 | CIA | |
2120 | SEM_FN_NAME (m32rx,mvtaclo_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2121 | { | |
2122 | #define FLD(f) abuf->fields.fmt_42_mvtachi_a.f | |
2123 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_42_mvtachi_a.f | |
2124 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2125 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
2126 | m32rx_h_accums_set (current_cpu, f_accs, ORDI (ANDDI (OPRND (accs), MAKEDI (0xffffffff, 0)), EXTSIDI (OPRND (src1)))); | |
2127 | TRACE_RESULT (current_cpu, "accs", 'D', OPRND (accs)); | |
2128 | #if WITH_PROFILE_MODEL_P | |
2129 | if (PROFILE_MODEL_P (current_cpu)) | |
2130 | { | |
2131 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
2132 | m32rx_model_profile_insn (current_cpu, abuf); | |
2133 | } | |
2134 | #endif | |
2135 | return new_pc; | |
2136 | #undef OPRND | |
2137 | #undef FLD | |
2138 | } | |
2139 | ||
2140 | /* Perform mvtc: mvtc $sr,$dcr. */ | |
2141 | CIA | |
2142 | SEM_FN_NAME (m32rx,mvtc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2143 | { | |
2144 | #define FLD(f) abuf->fields.fmt_43_mvtc.f | |
2145 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_43_mvtc.f | |
2146 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2147 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
2148 | m32rx_h_cr_set (current_cpu, f_r1, OPRND (sr)); | |
2149 | TRACE_RESULT (current_cpu, "dcr", 'x', OPRND (dcr)); | |
2150 | #if WITH_PROFILE_MODEL_P | |
2151 | if (PROFILE_MODEL_P (current_cpu)) | |
2152 | { | |
2153 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
2154 | m32rx_model_profile_insn (current_cpu, abuf); | |
2155 | } | |
2156 | #endif | |
2157 | return new_pc; | |
2158 | #undef OPRND | |
2159 | #undef FLD | |
2160 | } | |
2161 | ||
2162 | /* Perform neg: neg $dr,$sr. */ | |
2163 | CIA | |
2164 | SEM_FN_NAME (m32rx,neg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2165 | { | |
2166 | #define FLD(f) abuf->fields.fmt_37_mv.f | |
2167 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_37_mv.f | |
2168 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2169 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
2170 | CPU (h_gr[f_r1]) = NEGSI (OPRND (sr)); | |
2171 | TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr)); | |
2172 | #if WITH_PROFILE_MODEL_P | |
2173 | if (PROFILE_MODEL_P (current_cpu)) | |
2174 | { | |
2175 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
2176 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
2177 | m32rx_model_profile_insn (current_cpu, abuf); | |
2178 | } | |
2179 | #endif | |
2180 | return new_pc; | |
2181 | #undef OPRND | |
2182 | #undef FLD | |
2183 | } | |
2184 | ||
2185 | /* Perform nop: nop. */ | |
2186 | CIA | |
2187 | SEM_FN_NAME (m32rx,nop) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2188 | { | |
2189 | #define FLD(f) abuf->fields.fmt_44_nop.f | |
2190 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_44_nop.f | |
2191 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2192 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
2193 | PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr); | |
2194 | #if WITH_PROFILE_MODEL_P | |
2195 | if (PROFILE_MODEL_P (current_cpu)) | |
2196 | { | |
2197 | m32rx_model_profile_insn (current_cpu, abuf); | |
2198 | } | |
2199 | #endif | |
2200 | return new_pc; | |
2201 | #undef OPRND | |
2202 | #undef FLD | |
2203 | } | |
2204 | ||
2205 | /* Perform not: not $dr,$sr. */ | |
2206 | CIA | |
2207 | SEM_FN_NAME (m32rx,not) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2208 | { | |
2209 | #define FLD(f) abuf->fields.fmt_37_mv.f | |
2210 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_37_mv.f | |
2211 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2212 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
2213 | CPU (h_gr[f_r1]) = INVSI (OPRND (sr)); | |
2214 | TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr)); | |
2215 | #if WITH_PROFILE_MODEL_P | |
2216 | if (PROFILE_MODEL_P (current_cpu)) | |
2217 | { | |
2218 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
2219 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
2220 | m32rx_model_profile_insn (current_cpu, abuf); | |
2221 | } | |
2222 | #endif | |
2223 | return new_pc; | |
2224 | #undef OPRND | |
2225 | #undef FLD | |
2226 | } | |
2227 | ||
2228 | /* Perform rac: rac. */ | |
2229 | CIA | |
2230 | SEM_FN_NAME (m32rx,rac) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2231 | { | |
2232 | #define FLD(f) abuf->fields.fmt_45_rac.f | |
2233 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_45_rac.f | |
2234 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2235 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
2236 | do { | |
2237 | DI tmp_tmp1; | |
2238 | tmp_tmp1 = ANDDI (OPRND (accum), MAKEDI (16777215, 0xffffffff)); | |
2239 | if (ANDIFSI (GEDI (tmp_tmp1, MAKEDI (16383, 0xffff8000)), LEDI (tmp_tmp1, MAKEDI (8388607, 0xffffffff)))) { | |
2240 | tmp_tmp1 = MAKEDI (16383, 0xffff8000); | |
2241 | } else { | |
2242 | if (ANDIFSI (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (16760832, 0)))) { | |
2243 | tmp_tmp1 = MAKEDI (16760832, 0); | |
2244 | } else { | |
2245 | tmp_tmp1 = ANDDI (ADDDI (OPRND (accum), MAKEDI (0, 16384)), MAKEDI (16777215, 0xffff8000)); | |
2246 | } | |
2247 | } | |
2248 | tmp_tmp1 = SLLDI (tmp_tmp1, 1); | |
2249 | CPU (h_accum) = SRADI (SLLDI (tmp_tmp1, 7), 7); | |
2250 | TRACE_RESULT (current_cpu, "accum", 'D', OPRND (accum)); | |
2251 | } while (0); | |
2252 | #if WITH_PROFILE_MODEL_P | |
2253 | if (PROFILE_MODEL_P (current_cpu)) | |
2254 | { | |
2255 | m32rx_model_profile_insn (current_cpu, abuf); | |
2256 | } | |
2257 | #endif | |
2258 | return new_pc; | |
2259 | #undef OPRND | |
2260 | #undef FLD | |
2261 | } | |
2262 | ||
2263 | /* Perform rac-a: rac $accs. */ | |
2264 | CIA | |
2265 | SEM_FN_NAME (m32rx,rac_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2266 | { | |
2267 | #define FLD(f) abuf->fields.fmt_46_rac_a.f | |
2268 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_46_rac_a.f | |
2269 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2270 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
2271 | do { | |
2272 | DI tmp_tmp1; | |
2273 | tmp_tmp1 = ANDDI (OPRND (accs), MAKEDI (16777215, 0xffffffff)); | |
2274 | if (ANDIFSI (GEDI (tmp_tmp1, MAKEDI (16383, 0xffff8000)), LEDI (tmp_tmp1, MAKEDI (8388607, 0xffffffff)))) { | |
2275 | tmp_tmp1 = MAKEDI (16383, 0xffff8000); | |
2276 | } else { | |
2277 | if (ANDIFSI (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (16760832, 0)))) { | |
2278 | tmp_tmp1 = MAKEDI (16760832, 0); | |
2279 | } else { | |
2280 | tmp_tmp1 = ANDDI (ADDDI (OPRND (accs), MAKEDI (0, 16384)), MAKEDI (16777215, 0xffff8000)); | |
2281 | } | |
2282 | } | |
2283 | tmp_tmp1 = SLLDI (tmp_tmp1, 1); | |
2284 | m32rx_h_accums_set (current_cpu, f_accs, SRADI (SLLDI (tmp_tmp1, 7), 7)); | |
2285 | TRACE_RESULT (current_cpu, "accs", 'D', OPRND (accs)); | |
2286 | } while (0); | |
2287 | #if WITH_PROFILE_MODEL_P | |
2288 | if (PROFILE_MODEL_P (current_cpu)) | |
2289 | { | |
2290 | m32rx_model_profile_insn (current_cpu, abuf); | |
2291 | } | |
2292 | #endif | |
2293 | return new_pc; | |
2294 | #undef OPRND | |
2295 | #undef FLD | |
2296 | } | |
2297 | ||
2298 | /* Perform rach: rach. */ | |
2299 | CIA | |
2300 | SEM_FN_NAME (m32rx,rach) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2301 | { | |
2302 | #define FLD(f) abuf->fields.fmt_45_rac.f | |
2303 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_45_rac.f | |
2304 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2305 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
2306 | do { | |
2307 | DI tmp_tmp1; | |
2308 | tmp_tmp1 = ANDDI (OPRND (accum), MAKEDI (16777215, 0xffffffff)); | |
2309 | if (ANDIFSI (GEDI (tmp_tmp1, MAKEDI (16383, 0x80000000)), LEDI (tmp_tmp1, MAKEDI (8388607, 0xffffffff)))) { | |
2310 | tmp_tmp1 = MAKEDI (16383, 0x80000000); | |
2311 | } else { | |
2312 | if (ANDIFSI (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (16760832, 0)))) { | |
2313 | tmp_tmp1 = MAKEDI (16760832, 0); | |
2314 | } else { | |
2315 | tmp_tmp1 = ANDDI (ADDDI (OPRND (accum), MAKEDI (0, 1073741824)), MAKEDI (0xffffffff, 0x80000000)); | |
2316 | } | |
2317 | } | |
2318 | tmp_tmp1 = SLLDI (tmp_tmp1, 1); | |
2319 | CPU (h_accum) = SRADI (SLLDI (tmp_tmp1, 7), 7); | |
2320 | TRACE_RESULT (current_cpu, "accum", 'D', OPRND (accum)); | |
2321 | } while (0); | |
2322 | #if WITH_PROFILE_MODEL_P | |
2323 | if (PROFILE_MODEL_P (current_cpu)) | |
2324 | { | |
2325 | m32rx_model_profile_insn (current_cpu, abuf); | |
2326 | } | |
2327 | #endif | |
2328 | return new_pc; | |
2329 | #undef OPRND | |
2330 | #undef FLD | |
2331 | } | |
2332 | ||
2333 | /* Perform rach-a: rach $accs. */ | |
2334 | CIA | |
2335 | SEM_FN_NAME (m32rx,rach_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2336 | { | |
2337 | #define FLD(f) abuf->fields.fmt_46_rac_a.f | |
2338 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_46_rac_a.f | |
2339 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2340 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
2341 | do { | |
2342 | DI tmp_tmp1; | |
2343 | tmp_tmp1 = ANDDI (OPRND (accs), MAKEDI (16777215, 0xffffffff)); | |
2344 | if (ANDIFSI (GEDI (tmp_tmp1, MAKEDI (16383, 0x80000000)), LEDI (tmp_tmp1, MAKEDI (8388607, 0xffffffff)))) { | |
2345 | tmp_tmp1 = MAKEDI (16383, 0x80000000); | |
2346 | } else { | |
2347 | if (ANDIFSI (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (16760832, 0)))) { | |
2348 | tmp_tmp1 = MAKEDI (16760832, 0); | |
2349 | } else { | |
2350 | tmp_tmp1 = ANDDI (ADDDI (OPRND (accs), MAKEDI (0, 1073741824)), MAKEDI (0xffffffff, 0x80000000)); | |
2351 | } | |
2352 | } | |
2353 | tmp_tmp1 = SLLDI (tmp_tmp1, 1); | |
2354 | m32rx_h_accums_set (current_cpu, f_accs, SRADI (SLLDI (tmp_tmp1, 7), 7)); | |
2355 | TRACE_RESULT (current_cpu, "accs", 'D', OPRND (accs)); | |
2356 | } while (0); | |
2357 | #if WITH_PROFILE_MODEL_P | |
2358 | if (PROFILE_MODEL_P (current_cpu)) | |
2359 | { | |
2360 | m32rx_model_profile_insn (current_cpu, abuf); | |
2361 | } | |
2362 | #endif | |
2363 | return new_pc; | |
2364 | #undef OPRND | |
2365 | #undef FLD | |
2366 | } | |
2367 | ||
2368 | /* Perform rte: rte. */ | |
2369 | CIA | |
2370 | SEM_FN_NAME (m32rx,rte) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2371 | { | |
2372 | #define FLD(f) abuf->fields.fmt_44_nop.f | |
2373 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_44_nop.f | |
2374 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2375 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
2376 | int taken_p = 0; | |
2377 | do { | |
2378 | CPU (h_sm) = OPRND (h_bsm); | |
2379 | TRACE_RESULT (current_cpu, "h-sm", 'x', OPRND (h_sm)); | |
2380 | CPU (h_ie) = OPRND (h_bie); | |
2381 | TRACE_RESULT (current_cpu, "h-ie", 'x', OPRND (h_ie)); | |
2382 | CPU (h_cond) = OPRND (h_bcond); | |
2383 | TRACE_RESULT (current_cpu, "condbit", 'x', OPRND (condbit)); | |
2384 | BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, OPRND (h_bpc))); | |
2385 | TRACE_RESULT (current_cpu, "pc", 'x', OPRND (pc)); | |
2386 | } while (0); | |
2387 | #if WITH_PROFILE_MODEL_P | |
2388 | if (PROFILE_MODEL_P (current_cpu)) | |
2389 | { | |
2390 | m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p); | |
2391 | } | |
2392 | #endif | |
2393 | return new_pc; | |
2394 | #undef OPRND | |
2395 | #undef FLD | |
2396 | } | |
2397 | ||
2398 | /* Perform seth: seth $dr,$hi16. */ | |
2399 | CIA | |
2400 | SEM_FN_NAME (m32rx,seth) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2401 | { | |
2402 | #define FLD(f) abuf->fields.fmt_47_seth.f | |
2403 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_47_seth.f | |
2404 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2405 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
2406 | CPU (h_gr[f_r1]) = SLLSI (OPRND (hi16), 16); | |
2407 | TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr)); | |
2408 | #if WITH_PROFILE_MODEL_P | |
2409 | if (PROFILE_MODEL_P (current_cpu)) | |
2410 | { | |
2411 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
2412 | m32rx_model_profile_insn (current_cpu, abuf); | |
2413 | } | |
2414 | #endif | |
2415 | return new_pc; | |
2416 | #undef OPRND | |
2417 | #undef FLD | |
2418 | } | |
2419 | ||
2420 | /* Perform sll: sll $dr,$sr. */ | |
2421 | CIA | |
2422 | SEM_FN_NAME (m32rx,sll) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2423 | { | |
2424 | #define FLD(f) abuf->fields.fmt_0_add.f | |
2425 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_0_add.f | |
2426 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2427 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
2428 | CPU (h_gr[f_r1]) = SLLSI (OPRND (dr), ANDSI (OPRND (sr), 31)); | |
2429 | TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr)); | |
2430 | #if WITH_PROFILE_MODEL_P | |
2431 | if (PROFILE_MODEL_P (current_cpu)) | |
2432 | { | |
2433 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
2434 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
2435 | m32rx_model_profile_insn (current_cpu, abuf); | |
2436 | } | |
2437 | #endif | |
2438 | return new_pc; | |
2439 | #undef OPRND | |
2440 | #undef FLD | |
2441 | } | |
2442 | ||
2443 | /* Perform sll3: sll3 $dr,$sr,#$simm16. */ | |
2444 | CIA | |
2445 | SEM_FN_NAME (m32rx,sll3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2446 | { | |
2447 | #define FLD(f) abuf->fields.fmt_5_addv3.f | |
2448 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_5_addv3.f | |
2449 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2450 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
2451 | CPU (h_gr[f_r1]) = SLLSI (OPRND (sr), ANDSI (OPRND (simm16), 31)); | |
2452 | TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr)); | |
2453 | #if WITH_PROFILE_MODEL_P | |
2454 | if (PROFILE_MODEL_P (current_cpu)) | |
2455 | { | |
2456 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
2457 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
2458 | m32rx_model_profile_insn (current_cpu, abuf); | |
2459 | } | |
2460 | #endif | |
2461 | return new_pc; | |
2462 | #undef OPRND | |
2463 | #undef FLD | |
2464 | } | |
2465 | ||
2466 | /* Perform slli: slli $dr,#$uimm5. */ | |
2467 | CIA | |
2468 | SEM_FN_NAME (m32rx,slli) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2469 | { | |
2470 | #define FLD(f) abuf->fields.fmt_48_slli.f | |
2471 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_48_slli.f | |
2472 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2473 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
2474 | CPU (h_gr[f_r1]) = SLLSI (OPRND (dr), OPRND (uimm5)); | |
2475 | TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr)); | |
2476 | #if WITH_PROFILE_MODEL_P | |
2477 | if (PROFILE_MODEL_P (current_cpu)) | |
2478 | { | |
2479 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
2480 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
2481 | m32rx_model_profile_insn (current_cpu, abuf); | |
2482 | } | |
2483 | #endif | |
2484 | return new_pc; | |
2485 | #undef OPRND | |
2486 | #undef FLD | |
2487 | } | |
2488 | ||
2489 | /* Perform sra: sra $dr,$sr. */ | |
2490 | CIA | |
2491 | SEM_FN_NAME (m32rx,sra) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2492 | { | |
2493 | #define FLD(f) abuf->fields.fmt_0_add.f | |
2494 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_0_add.f | |
2495 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2496 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
2497 | CPU (h_gr[f_r1]) = SRASI (OPRND (dr), ANDSI (OPRND (sr), 31)); | |
2498 | TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr)); | |
2499 | #if WITH_PROFILE_MODEL_P | |
2500 | if (PROFILE_MODEL_P (current_cpu)) | |
2501 | { | |
2502 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
2503 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
2504 | m32rx_model_profile_insn (current_cpu, abuf); | |
2505 | } | |
2506 | #endif | |
2507 | return new_pc; | |
2508 | #undef OPRND | |
2509 | #undef FLD | |
2510 | } | |
2511 | ||
2512 | /* Perform sra3: sra3 $dr,$sr,#$simm16. */ | |
2513 | CIA | |
2514 | SEM_FN_NAME (m32rx,sra3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2515 | { | |
2516 | #define FLD(f) abuf->fields.fmt_5_addv3.f | |
2517 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_5_addv3.f | |
2518 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2519 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
2520 | CPU (h_gr[f_r1]) = SRASI (OPRND (sr), ANDSI (OPRND (simm16), 31)); | |
2521 | TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr)); | |
2522 | #if WITH_PROFILE_MODEL_P | |
2523 | if (PROFILE_MODEL_P (current_cpu)) | |
2524 | { | |
2525 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
2526 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
2527 | m32rx_model_profile_insn (current_cpu, abuf); | |
2528 | } | |
2529 | #endif | |
2530 | return new_pc; | |
2531 | #undef OPRND | |
2532 | #undef FLD | |
2533 | } | |
2534 | ||
2535 | /* Perform srai: srai $dr,#$uimm5. */ | |
2536 | CIA | |
2537 | SEM_FN_NAME (m32rx,srai) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2538 | { | |
2539 | #define FLD(f) abuf->fields.fmt_48_slli.f | |
2540 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_48_slli.f | |
2541 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2542 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
2543 | CPU (h_gr[f_r1]) = SRASI (OPRND (dr), OPRND (uimm5)); | |
2544 | TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr)); | |
2545 | #if WITH_PROFILE_MODEL_P | |
2546 | if (PROFILE_MODEL_P (current_cpu)) | |
2547 | { | |
2548 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
2549 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
2550 | m32rx_model_profile_insn (current_cpu, abuf); | |
2551 | } | |
2552 | #endif | |
2553 | return new_pc; | |
2554 | #undef OPRND | |
2555 | #undef FLD | |
2556 | } | |
2557 | ||
2558 | /* Perform srl: srl $dr,$sr. */ | |
2559 | CIA | |
2560 | SEM_FN_NAME (m32rx,srl) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2561 | { | |
2562 | #define FLD(f) abuf->fields.fmt_0_add.f | |
2563 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_0_add.f | |
2564 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2565 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
2566 | CPU (h_gr[f_r1]) = SRLSI (OPRND (dr), ANDSI (OPRND (sr), 31)); | |
2567 | TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr)); | |
2568 | #if WITH_PROFILE_MODEL_P | |
2569 | if (PROFILE_MODEL_P (current_cpu)) | |
2570 | { | |
2571 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
2572 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
2573 | m32rx_model_profile_insn (current_cpu, abuf); | |
2574 | } | |
2575 | #endif | |
2576 | return new_pc; | |
2577 | #undef OPRND | |
2578 | #undef FLD | |
2579 | } | |
2580 | ||
2581 | /* Perform srl3: srl3 $dr,$sr,#$simm16. */ | |
2582 | CIA | |
2583 | SEM_FN_NAME (m32rx,srl3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2584 | { | |
2585 | #define FLD(f) abuf->fields.fmt_5_addv3.f | |
2586 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_5_addv3.f | |
2587 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2588 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
2589 | CPU (h_gr[f_r1]) = SRLSI (OPRND (sr), ANDSI (OPRND (simm16), 31)); | |
2590 | TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr)); | |
2591 | #if WITH_PROFILE_MODEL_P | |
2592 | if (PROFILE_MODEL_P (current_cpu)) | |
2593 | { | |
2594 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
2595 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
2596 | m32rx_model_profile_insn (current_cpu, abuf); | |
2597 | } | |
2598 | #endif | |
2599 | return new_pc; | |
2600 | #undef OPRND | |
2601 | #undef FLD | |
2602 | } | |
2603 | ||
2604 | /* Perform srli: srli $dr,#$uimm5. */ | |
2605 | CIA | |
2606 | SEM_FN_NAME (m32rx,srli) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2607 | { | |
2608 | #define FLD(f) abuf->fields.fmt_48_slli.f | |
2609 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_48_slli.f | |
2610 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2611 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
2612 | CPU (h_gr[f_r1]) = SRLSI (OPRND (dr), OPRND (uimm5)); | |
2613 | TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr)); | |
2614 | #if WITH_PROFILE_MODEL_P | |
2615 | if (PROFILE_MODEL_P (current_cpu)) | |
2616 | { | |
2617 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
2618 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
2619 | m32rx_model_profile_insn (current_cpu, abuf); | |
2620 | } | |
2621 | #endif | |
2622 | return new_pc; | |
2623 | #undef OPRND | |
2624 | #undef FLD | |
2625 | } | |
2626 | ||
2627 | /* Perform st: st $src1,@$src2. */ | |
2628 | CIA | |
2629 | SEM_FN_NAME (m32rx,st) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2630 | { | |
2631 | #define FLD(f) abuf->fields.fmt_17_cmp.f | |
2632 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_17_cmp.f | |
2633 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2634 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
2635 | SETMEMSI (current_cpu, OPRND (src2), OPRND (src1)); | |
2636 | TRACE_RESULT (current_cpu, "h-memory", 'x', OPRND (h_memory)); | |
2637 | #if WITH_PROFILE_MODEL_P | |
2638 | if (PROFILE_MODEL_P (current_cpu)) | |
2639 | { | |
2640 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
2641 | m32rx_model_profile_insn (current_cpu, abuf); | |
2642 | } | |
2643 | #endif | |
2644 | return new_pc; | |
2645 | #undef OPRND | |
2646 | #undef FLD | |
2647 | } | |
2648 | ||
2649 | /* Perform st-d: st $src1,@($slo16,$src2). */ | |
2650 | CIA | |
2651 | SEM_FN_NAME (m32rx,st_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2652 | { | |
2653 | #define FLD(f) abuf->fields.fmt_49_st_d.f | |
2654 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_49_st_d.f | |
2655 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2656 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
2657 | SETMEMSI (current_cpu, ADDSI (OPRND (src2), OPRND (slo16)), OPRND (src1)); | |
2658 | TRACE_RESULT (current_cpu, "h-memory", 'x', OPRND (h_memory)); | |
2659 | #if WITH_PROFILE_MODEL_P | |
2660 | if (PROFILE_MODEL_P (current_cpu)) | |
2661 | { | |
2662 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
2663 | m32rx_model_profile_insn (current_cpu, abuf); | |
2664 | } | |
2665 | #endif | |
2666 | return new_pc; | |
2667 | #undef OPRND | |
2668 | #undef FLD | |
2669 | } | |
2670 | ||
2671 | /* Perform stb: stb $src1,@$src2. */ | |
2672 | CIA | |
2673 | SEM_FN_NAME (m32rx,stb) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2674 | { | |
2675 | #define FLD(f) abuf->fields.fmt_17_cmp.f | |
2676 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_17_cmp.f | |
2677 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2678 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
2679 | SETMEMQI (current_cpu, OPRND (src2), OPRND (src1)); | |
2680 | TRACE_RESULT (current_cpu, "h-memory", 'x', OPRND (h_memory)); | |
2681 | #if WITH_PROFILE_MODEL_P | |
2682 | if (PROFILE_MODEL_P (current_cpu)) | |
2683 | { | |
2684 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
2685 | m32rx_model_profile_insn (current_cpu, abuf); | |
2686 | } | |
2687 | #endif | |
2688 | return new_pc; | |
2689 | #undef OPRND | |
2690 | #undef FLD | |
2691 | } | |
2692 | ||
2693 | /* Perform stb-d: stb $src1,@($slo16,$src2). */ | |
2694 | CIA | |
2695 | SEM_FN_NAME (m32rx,stb_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2696 | { | |
2697 | #define FLD(f) abuf->fields.fmt_49_st_d.f | |
2698 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_49_st_d.f | |
2699 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2700 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
2701 | SETMEMQI (current_cpu, ADDSI (OPRND (src2), OPRND (slo16)), OPRND (src1)); | |
2702 | TRACE_RESULT (current_cpu, "h-memory", 'x', OPRND (h_memory)); | |
2703 | #if WITH_PROFILE_MODEL_P | |
2704 | if (PROFILE_MODEL_P (current_cpu)) | |
2705 | { | |
2706 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
2707 | m32rx_model_profile_insn (current_cpu, abuf); | |
2708 | } | |
2709 | #endif | |
2710 | return new_pc; | |
2711 | #undef OPRND | |
2712 | #undef FLD | |
2713 | } | |
2714 | ||
2715 | /* Perform sth: sth $src1,@$src2. */ | |
2716 | CIA | |
2717 | SEM_FN_NAME (m32rx,sth) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2718 | { | |
2719 | #define FLD(f) abuf->fields.fmt_17_cmp.f | |
2720 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_17_cmp.f | |
2721 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2722 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
2723 | SETMEMHI (current_cpu, OPRND (src2), OPRND (src1)); | |
2724 | TRACE_RESULT (current_cpu, "h-memory", 'x', OPRND (h_memory)); | |
2725 | #if WITH_PROFILE_MODEL_P | |
2726 | if (PROFILE_MODEL_P (current_cpu)) | |
2727 | { | |
2728 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
2729 | m32rx_model_profile_insn (current_cpu, abuf); | |
2730 | } | |
2731 | #endif | |
2732 | return new_pc; | |
2733 | #undef OPRND | |
2734 | #undef FLD | |
2735 | } | |
2736 | ||
2737 | /* Perform sth-d: sth $src1,@($slo16,$src2). */ | |
2738 | CIA | |
2739 | SEM_FN_NAME (m32rx,sth_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2740 | { | |
2741 | #define FLD(f) abuf->fields.fmt_49_st_d.f | |
2742 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_49_st_d.f | |
2743 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2744 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
2745 | SETMEMHI (current_cpu, ADDSI (OPRND (src2), OPRND (slo16)), OPRND (src1)); | |
2746 | TRACE_RESULT (current_cpu, "h-memory", 'x', OPRND (h_memory)); | |
2747 | #if WITH_PROFILE_MODEL_P | |
2748 | if (PROFILE_MODEL_P (current_cpu)) | |
2749 | { | |
2750 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
2751 | m32rx_model_profile_insn (current_cpu, abuf); | |
2752 | } | |
2753 | #endif | |
2754 | return new_pc; | |
2755 | #undef OPRND | |
2756 | #undef FLD | |
2757 | } | |
2758 | ||
2759 | /* Perform st-plus: st $src1,@+$src2. */ | |
2760 | CIA | |
2761 | SEM_FN_NAME (m32rx,st_plus) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2762 | { | |
2763 | #define FLD(f) abuf->fields.fmt_17_cmp.f | |
2764 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_17_cmp.f | |
2765 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2766 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
2767 | do { | |
2768 | CPU (h_gr[f_r2]) = ADDSI (OPRND (src2), 4); | |
2769 | TRACE_RESULT (current_cpu, "src2", 'x', OPRND (src2)); | |
2770 | SETMEMSI (current_cpu, OPRND (src2), OPRND (src1)); | |
2771 | TRACE_RESULT (current_cpu, "h-memory", 'x', OPRND (h_memory)); | |
2772 | } while (0); | |
2773 | #if WITH_PROFILE_MODEL_P | |
2774 | if (PROFILE_MODEL_P (current_cpu)) | |
2775 | { | |
2776 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
2777 | m32rx_model_profile_insn (current_cpu, abuf); | |
2778 | } | |
2779 | #endif | |
2780 | return new_pc; | |
2781 | #undef OPRND | |
2782 | #undef FLD | |
2783 | } | |
2784 | ||
2785 | /* Perform st-minus: st $src1,@-$src2. */ | |
2786 | CIA | |
2787 | SEM_FN_NAME (m32rx,st_minus) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2788 | { | |
2789 | #define FLD(f) abuf->fields.fmt_17_cmp.f | |
2790 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_17_cmp.f | |
2791 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2792 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
2793 | do { | |
2794 | CPU (h_gr[f_r2]) = SUBSI (OPRND (src2), 4); | |
2795 | TRACE_RESULT (current_cpu, "src2", 'x', OPRND (src2)); | |
2796 | SETMEMSI (current_cpu, OPRND (src2), OPRND (src1)); | |
2797 | TRACE_RESULT (current_cpu, "h-memory", 'x', OPRND (h_memory)); | |
2798 | } while (0); | |
2799 | #if WITH_PROFILE_MODEL_P | |
2800 | if (PROFILE_MODEL_P (current_cpu)) | |
2801 | { | |
2802 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
2803 | m32rx_model_profile_insn (current_cpu, abuf); | |
2804 | } | |
2805 | #endif | |
2806 | return new_pc; | |
2807 | #undef OPRND | |
2808 | #undef FLD | |
2809 | } | |
2810 | ||
2811 | /* Perform sub: sub $dr,$sr. */ | |
2812 | CIA | |
2813 | SEM_FN_NAME (m32rx,sub) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2814 | { | |
2815 | #define FLD(f) abuf->fields.fmt_0_add.f | |
2816 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_0_add.f | |
2817 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2818 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
2819 | CPU (h_gr[f_r1]) = SUBSI (OPRND (dr), OPRND (sr)); | |
2820 | TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr)); | |
2821 | #if WITH_PROFILE_MODEL_P | |
2822 | if (PROFILE_MODEL_P (current_cpu)) | |
2823 | { | |
2824 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
2825 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
2826 | m32rx_model_profile_insn (current_cpu, abuf); | |
2827 | } | |
2828 | #endif | |
2829 | return new_pc; | |
2830 | #undef OPRND | |
2831 | #undef FLD | |
2832 | } | |
2833 | ||
2834 | /* Perform subv: subv $dr,$sr. */ | |
2835 | CIA | |
2836 | SEM_FN_NAME (m32rx,subv) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2837 | { | |
2838 | #define FLD(f) abuf->fields.fmt_0_add.f | |
2839 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_0_add.f | |
2840 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2841 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
2842 | do { | |
2843 | BI temp1;SI temp0; | |
2844 | temp0 = SUBSI (OPRND (dr), OPRND (sr)); | |
2845 | temp1 = SUBOFSI (OPRND (dr), OPRND (sr), 0); | |
2846 | CPU (h_gr[f_r1]) = temp0; | |
2847 | TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr)); | |
2848 | CPU (h_cond) = temp1; | |
2849 | TRACE_RESULT (current_cpu, "condbit", 'x', OPRND (condbit)); | |
2850 | } while (0); | |
2851 | #if WITH_PROFILE_MODEL_P | |
2852 | if (PROFILE_MODEL_P (current_cpu)) | |
2853 | { | |
2854 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
2855 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
2856 | m32rx_model_profile_insn (current_cpu, abuf); | |
2857 | } | |
2858 | #endif | |
2859 | return new_pc; | |
2860 | #undef OPRND | |
2861 | #undef FLD | |
2862 | } | |
2863 | ||
2864 | /* Perform subx: subx $dr,$sr. */ | |
2865 | CIA | |
2866 | SEM_FN_NAME (m32rx,subx) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2867 | { | |
2868 | #define FLD(f) abuf->fields.fmt_6_addx.f | |
2869 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_6_addx.f | |
2870 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2871 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
2872 | do { | |
2873 | BI temp1;SI temp0; | |
2874 | temp0 = SUBCSI (OPRND (dr), OPRND (sr), OPRND (condbit)); | |
2875 | temp1 = SUBCFSI (OPRND (dr), OPRND (sr), OPRND (condbit)); | |
2876 | CPU (h_gr[f_r1]) = temp0; | |
2877 | TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr)); | |
2878 | CPU (h_cond) = temp1; | |
2879 | TRACE_RESULT (current_cpu, "condbit", 'x', OPRND (condbit)); | |
2880 | } while (0); | |
2881 | #if WITH_PROFILE_MODEL_P | |
2882 | if (PROFILE_MODEL_P (current_cpu)) | |
2883 | { | |
2884 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
2885 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
2886 | m32rx_model_profile_insn (current_cpu, abuf); | |
2887 | } | |
2888 | #endif | |
2889 | return new_pc; | |
2890 | #undef OPRND | |
2891 | #undef FLD | |
2892 | } | |
2893 | ||
2894 | /* Perform trap: trap #$uimm4. */ | |
2895 | CIA | |
2896 | SEM_FN_NAME (m32rx,trap) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2897 | { | |
2898 | #define FLD(f) abuf->fields.fmt_50_trap.f | |
2899 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_50_trap.f | |
2900 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2901 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
2902 | int taken_p = 0; | |
2903 | do_trap (current_cpu, OPRND (uimm4)); | |
2904 | #if WITH_PROFILE_MODEL_P | |
2905 | if (PROFILE_MODEL_P (current_cpu)) | |
2906 | { | |
2907 | m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p); | |
2908 | } | |
2909 | #endif | |
2910 | return new_pc; | |
2911 | #undef OPRND | |
2912 | #undef FLD | |
2913 | } | |
2914 | ||
2915 | /* Perform unlock: unlock $src1,@$src2. */ | |
2916 | CIA | |
2917 | SEM_FN_NAME (m32rx,unlock) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2918 | { | |
2919 | #define FLD(f) abuf->fields.fmt_17_cmp.f | |
2920 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_17_cmp.f | |
2921 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2922 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
2923 | do_unlock (current_cpu, OPRND (src1), OPRND (src2)); | |
2924 | #if WITH_PROFILE_MODEL_P | |
2925 | if (PROFILE_MODEL_P (current_cpu)) | |
2926 | { | |
2927 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
2928 | m32rx_model_profile_insn (current_cpu, abuf); | |
2929 | } | |
2930 | #endif | |
2931 | return new_pc; | |
2932 | #undef OPRND | |
2933 | #undef FLD | |
2934 | } | |
2935 | ||
2936 | /* Perform satb: satb $dr,$src2. */ | |
2937 | CIA | |
2938 | SEM_FN_NAME (m32rx,satb) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2939 | { | |
2940 | #define FLD(f) abuf->fields.fmt_51_satb.f | |
2941 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_51_satb.f | |
2942 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2943 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
2944 | CPU (h_gr[f_r1]) = (GESI (OPRND (src2), 127)) ? (127) : (LESI (OPRND (src2), -128)) ? (-128) : (OPRND (src2)); | |
2945 | TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr)); | |
2946 | #if WITH_PROFILE_MODEL_P | |
2947 | if (PROFILE_MODEL_P (current_cpu)) | |
2948 | { | |
2949 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
2950 | m32rx_model_profile_insn (current_cpu, abuf); | |
2951 | } | |
2952 | #endif | |
2953 | return new_pc; | |
2954 | #undef OPRND | |
2955 | #undef FLD | |
2956 | } | |
2957 | ||
2958 | /* Perform sath: sath $dr,$src2. */ | |
2959 | CIA | |
2960 | SEM_FN_NAME (m32rx,sath) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2961 | { | |
2962 | #define FLD(f) abuf->fields.fmt_51_satb.f | |
2963 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_51_satb.f | |
2964 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2965 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
2966 | CPU (h_gr[f_r1]) = (GESI (OPRND (src2), 32767)) ? (32767) : (LESI (OPRND (src2), -32768)) ? (-32768) : (OPRND (src2)); | |
2967 | TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr)); | |
2968 | #if WITH_PROFILE_MODEL_P | |
2969 | if (PROFILE_MODEL_P (current_cpu)) | |
2970 | { | |
2971 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
2972 | m32rx_model_profile_insn (current_cpu, abuf); | |
2973 | } | |
2974 | #endif | |
2975 | return new_pc; | |
2976 | #undef OPRND | |
2977 | #undef FLD | |
2978 | } | |
2979 | ||
2980 | /* Perform sat: sat $dr,$src2. */ | |
2981 | CIA | |
2982 | SEM_FN_NAME (m32rx,sat) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2983 | { | |
2984 | #define FLD(f) abuf->fields.fmt_51_satb.f | |
2985 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_51_satb.f | |
2986 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2987 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
2988 | CPU (h_gr[f_r1]) = (OPRND (condbit)) ? ((LTSI (OPRND (src2), 0)) ? (2147483647) : (0x80000000)) : (OPRND (src2)); | |
2989 | TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr)); | |
2990 | #if WITH_PROFILE_MODEL_P | |
2991 | if (PROFILE_MODEL_P (current_cpu)) | |
2992 | { | |
2993 | m32rx_model_mark_set_h_gr (current_cpu, abuf); | |
2994 | m32rx_model_profile_insn (current_cpu, abuf); | |
2995 | } | |
2996 | #endif | |
2997 | return new_pc; | |
2998 | #undef OPRND | |
2999 | #undef FLD | |
3000 | } | |
3001 | ||
3002 | /* Perform pcmpbz: pcmpbz $src2. */ | |
3003 | CIA | |
3004 | SEM_FN_NAME (m32rx,pcmpbz) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
3005 | { | |
3006 | #define FLD(f) abuf->fields.fmt_52_pcmpbz.f | |
3007 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_52_pcmpbz.f | |
3008 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3009 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
3010 | CPU (h_cond) = (EQSI (ANDSI (OPRND (src2), 255), 0)) ? (1) : (EQSI (ANDSI (OPRND (src2), 65280), 0)) ? (1) : (EQSI (ANDSI (OPRND (src2), 16711680), 0)) ? (1) : (EQSI (ANDSI (OPRND (src2), 0xff000000), 0)) ? (1) : (0); | |
3011 | TRACE_RESULT (current_cpu, "condbit", 'x', OPRND (condbit)); | |
3012 | #if WITH_PROFILE_MODEL_P | |
3013 | if (PROFILE_MODEL_P (current_cpu)) | |
3014 | { | |
3015 | m32rx_model_profile_insn (current_cpu, abuf); | |
3016 | } | |
3017 | #endif | |
3018 | return new_pc; | |
3019 | #undef OPRND | |
3020 | #undef FLD | |
3021 | } | |
3022 | ||
3023 | /* Perform sadd: sadd. */ | |
3024 | CIA | |
3025 | SEM_FN_NAME (m32rx,sadd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
3026 | { | |
3027 | #define FLD(f) abuf->fields.fmt_53_sadd.f | |
3028 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_53_sadd.f | |
3029 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3030 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
3031 | m32rx_h_accums_set (current_cpu, 0, ADDDI (SRADI (OPRND (h_accums), 16), OPRND (h_accums))); | |
3032 | TRACE_RESULT (current_cpu, "h-accums", 'D', OPRND (h_accums)); | |
3033 | #if WITH_PROFILE_MODEL_P | |
3034 | if (PROFILE_MODEL_P (current_cpu)) | |
3035 | { | |
3036 | m32rx_model_profile_insn (current_cpu, abuf); | |
3037 | } | |
3038 | #endif | |
3039 | return new_pc; | |
3040 | #undef OPRND | |
3041 | #undef FLD | |
3042 | } | |
3043 | ||
3044 | /* Perform macwu1: macwu1 $src1,$src2. */ | |
3045 | CIA | |
3046 | SEM_FN_NAME (m32rx,macwu1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
3047 | { | |
3048 | #define FLD(f) abuf->fields.fmt_54_macwu1.f | |
3049 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_54_macwu1.f | |
3050 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3051 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
3052 | m32rx_h_accums_set (current_cpu, 1, SRADI (SLLDI (ADDDI (OPRND (h_accums), MULDI (EXTSIDI (OPRND (src1)), EXTSIDI (ANDSI (OPRND (src2), 65535)))), 8), 8)); | |
3053 | TRACE_RESULT (current_cpu, "h-accums", 'D', OPRND (h_accums)); | |
3054 | #if WITH_PROFILE_MODEL_P | |
3055 | if (PROFILE_MODEL_P (current_cpu)) | |
3056 | { | |
3057 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
3058 | m32rx_model_profile_insn (current_cpu, abuf); | |
3059 | } | |
3060 | #endif | |
3061 | return new_pc; | |
3062 | #undef OPRND | |
3063 | #undef FLD | |
3064 | } | |
3065 | ||
3066 | /* Perform msblo: msblo $src1,$src2. */ | |
3067 | CIA | |
3068 | SEM_FN_NAME (m32rx,msblo) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
3069 | { | |
3070 | #define FLD(f) abuf->fields.fmt_34_machi.f | |
3071 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_34_machi.f | |
3072 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3073 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
3074 | CPU (h_accum) = SRADI (SLLDI (SUBDI (OPRND (accum), SRADI (SLLDI (MULDI (EXTHIDI (TRUNCSIHI (OPRND (src1))), EXTHIDI (TRUNCSIHI (OPRND (src2)))), 32), 16)), 8), 8); | |
3075 | TRACE_RESULT (current_cpu, "accum", 'D', OPRND (accum)); | |
3076 | #if WITH_PROFILE_MODEL_P | |
3077 | if (PROFILE_MODEL_P (current_cpu)) | |
3078 | { | |
3079 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
3080 | m32rx_model_profile_insn (current_cpu, abuf); | |
3081 | } | |
3082 | #endif | |
3083 | return new_pc; | |
3084 | #undef OPRND | |
3085 | #undef FLD | |
3086 | } | |
3087 | ||
3088 | /* Perform mulwu1: mulwu1 $src1,$src2. */ | |
3089 | CIA | |
3090 | SEM_FN_NAME (m32rx,mulwu1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
3091 | { | |
3092 | #define FLD(f) abuf->fields.fmt_17_cmp.f | |
3093 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_17_cmp.f | |
3094 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3095 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
3096 | m32rx_h_accums_set (current_cpu, 1, SRADI (SLLDI (MULDI (EXTSIDI (OPRND (src1)), EXTSIDI (ANDSI (OPRND (src2), 65535))), 16), 16)); | |
3097 | TRACE_RESULT (current_cpu, "h-accums", 'D', OPRND (h_accums)); | |
3098 | #if WITH_PROFILE_MODEL_P | |
3099 | if (PROFILE_MODEL_P (current_cpu)) | |
3100 | { | |
3101 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
3102 | m32rx_model_profile_insn (current_cpu, abuf); | |
3103 | } | |
3104 | #endif | |
3105 | return new_pc; | |
3106 | #undef OPRND | |
3107 | #undef FLD | |
3108 | } | |
3109 | ||
3110 | /* Perform machl1: machl1 $src1,$src2. */ | |
3111 | CIA | |
3112 | SEM_FN_NAME (m32rx,machl1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
3113 | { | |
3114 | #define FLD(f) abuf->fields.fmt_54_macwu1.f | |
3115 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_54_macwu1.f | |
3116 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3117 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
3118 | m32rx_h_accums_set (current_cpu, 1, SRADI (SLLDI (ADDDI (OPRND (h_accums), SRADI (SLLDI (MULDI (EXTSIDI (SRASI (OPRND (src1), 16)), EXTHIDI (TRUNCSIHI (OPRND (src2)))), 32), 16)), 8), 8)); | |
3119 | TRACE_RESULT (current_cpu, "h-accums", 'D', OPRND (h_accums)); | |
3120 | #if WITH_PROFILE_MODEL_P | |
3121 | if (PROFILE_MODEL_P (current_cpu)) | |
3122 | { | |
3123 | m32rx_model_mark_get_h_gr (current_cpu, abuf); | |
3124 | m32rx_model_profile_insn (current_cpu, abuf); | |
3125 | } | |
3126 | #endif | |
3127 | return new_pc; | |
3128 | #undef OPRND | |
3129 | #undef FLD | |
3130 | } | |
3131 | ||
3132 | /* Perform sc: sc. */ | |
3133 | CIA | |
3134 | SEM_FN_NAME (m32rx,sc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
3135 | { | |
3136 | #define FLD(f) abuf->fields.fmt_55_sc.f | |
3137 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_55_sc.f | |
3138 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3139 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
3140 | if (OPRND (condbit)) { | |
3141 | CPU (h_abort) = 1; | |
3142 | TRACE_RESULT (current_cpu, "abort-parallel-execution", 'x', OPRND (abort_parallel_execution)); | |
3143 | } | |
3144 | #if WITH_PROFILE_MODEL_P | |
3145 | if (PROFILE_MODEL_P (current_cpu)) | |
3146 | { | |
3147 | m32rx_model_profile_insn (current_cpu, abuf); | |
3148 | } | |
3149 | #endif | |
3150 | return new_pc; | |
3151 | #undef OPRND | |
3152 | #undef FLD | |
3153 | } | |
3154 | ||
3155 | /* Perform snc: snc. */ | |
3156 | CIA | |
3157 | SEM_FN_NAME (m32rx,snc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
3158 | { | |
3159 | #define FLD(f) abuf->fields.fmt_55_sc.f | |
3160 | #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_55_sc.f | |
3161 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3162 | CIA new_pc = SEM_NEXT_PC (sem_arg); | |
3163 | if (NOTBI (OPRND (condbit))) { | |
3164 | CPU (h_abort) = 1; | |
3165 | TRACE_RESULT (current_cpu, "abort-parallel-execution", 'x', OPRND (abort_parallel_execution)); | |
3166 | } | |
3167 | #if WITH_PROFILE_MODEL_P | |
3168 | if (PROFILE_MODEL_P (current_cpu)) | |
3169 | { | |
3170 | m32rx_model_profile_insn (current_cpu, abuf); | |
3171 | } | |
3172 | #endif | |
3173 | return new_pc; | |
3174 | #undef OPRND | |
3175 | #undef FLD | |
3176 | } | |
3177 | ||
3178 | /* FIXME: Add "no return" attribute to illegal insn handlers. | |
3179 | They all call longjmp. */ | |
3180 | ||
3181 | PCADDR | |
3182 | SEM_FN_NAME (m32rx,illegal) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
3183 | { | |
3184 | sim_engine_illegal_insn (current_cpu, NULL_CIA /*FIXME*/); | |
3185 | return 0; | |
3186 | } | |
3187 | ||
3188 | #endif /* ! defined (SCACHE_P) || (defined (SCACHE_P) && WITH_SCACHE) */ |