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646c6f2b DE |
1 | /* Main simulator entry points for the M32R. |
2 | Copyright (C) 1996, 1997 Free Software Foundation, Inc. | |
3 | Contributed by Cygnus Support. | |
4 | ||
5 | This program is free software; you can redistribute it and/or modify | |
6 | it under the terms of the GNU General Public License as published by | |
7 | the Free Software Foundation; either version 2, or (at your option) | |
8 | any later version. | |
9 | ||
10 | This program is distributed in the hope that it will be useful, | |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | GNU General Public License for more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along | |
16 | with this program; if not, write to the Free Software Foundation, Inc., | |
17 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
18 | ||
19 | #include "sim-main.h" | |
20 | #include <signal.h> | |
21 | #ifdef HAVE_STDLIB_H | |
22 | #include <stdlib.h> | |
23 | #endif | |
24 | #include "libiberty.h" | |
25 | #include "bfd.h" | |
26 | #include "sim-core.h" | |
27 | #include "cpu-sim.h" | |
28 | ||
646c6f2b DE |
29 | /* Global state until sim_open starts creating and returning it |
30 | [and the other simulator i/f fns take it as an argument]. */ | |
31 | struct sim_state sim_global_state; | |
32 | ||
33 | /* FIXME: Do we *need* to pass state to the semantic routines? */ | |
34 | STATE current_state; | |
35 | ||
36 | /* Create an instance of the simulator. */ | |
37 | ||
38 | SIM_DESC | |
247fccde | 39 | sim_open (kind, callback, abfd, argv) |
646c6f2b | 40 | SIM_OPEN_KIND kind; |
247fccde AC |
41 | host_callback *callback; |
42 | struct _bfd *abfd; | |
646c6f2b DE |
43 | char **argv; |
44 | { | |
45 | int i; | |
46 | SIM_DESC sd = &sim_global_state; | |
47 | ||
48 | /* FIXME: until we alloc one, use the global. */ | |
49 | memset (sd, 0, sizeof (sim_global_state)); | |
50 | STATE_OPEN_KIND (sd) = kind; | |
247fccde | 51 | STATE_CALLBACK (sd) = callback; |
646c6f2b DE |
52 | |
53 | if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK) | |
54 | return 0; | |
55 | ||
56 | #if 0 /* FIXME: 'twould be nice if we could do this */ | |
57 | /* These options override any module options. | |
58 | Obviously ambiguity should be avoided, however the caller may wish to | |
59 | augment the meaning of an option. */ | |
60 | if (extra_options != NULL) | |
61 | sim_add_option_table (sd, extra_options); | |
62 | #endif | |
63 | ||
64 | /* getopt will print the error message so we just have to exit if this fails. | |
65 | FIXME: Hmmm... in the case of gdb we need getopt to call | |
66 | print_filtered. */ | |
67 | if (sim_parse_args (sd, argv) != SIM_RC_OK) | |
68 | { | |
69 | sim_module_uninstall (sd); | |
70 | return 0; | |
71 | } | |
72 | ||
73 | if (sim_post_argv_init (sd) != SIM_RC_OK) | |
74 | { | |
75 | sim_module_uninstall (sd); | |
76 | return 0; | |
77 | } | |
78 | ||
79 | /* Initialize various cgen things not done by common framework. */ | |
80 | cgen_init (sd); | |
81 | ||
82 | /* FIXME:wip */ | |
247fccde AC |
83 | sim_core_attach (sd, NULL, attach_raw_memory, access_read_write_exec, |
84 | 0, 0, M32R_DEFAULT_MEM_SIZE, NULL, NULL); | |
85 | ||
86 | /* Only needed for profiling, but the structure member is small. */ | |
646c6f2b DE |
87 | for (i = 0; i < MAX_NR_PROCESSORS; ++i) |
88 | memset (& CPU_M32R_PROFILE (STATE_CPU (sd, i)), 0, | |
89 | sizeof (CPU_M32R_PROFILE (STATE_CPU (sd, i)))); | |
90 | ||
91 | return &sim_global_state; | |
92 | } | |
93 | ||
94 | void | |
95 | sim_close (sd, quitting) | |
96 | SIM_DESC sd; | |
97 | int quitting; | |
98 | { | |
99 | sim_module_uninstall (sd); | |
100 | } | |
101 | ||
102 | SIM_RC | |
fafce69a | 103 | sim_create_inferior (sd, abfd, argv, envp) |
646c6f2b | 104 | SIM_DESC sd; |
fafce69a | 105 | struct _bfd *abfd; |
646c6f2b DE |
106 | char **argv; |
107 | char **envp; | |
108 | { | |
109 | #if 0 | |
110 | STATE_ARGV (sd) = sim_copy_argv (argv); | |
111 | STATE_ENVP (sd) = sim_copy_argv (envp); | |
112 | #endif | |
fafce69a AC |
113 | if (abfd != NULL) |
114 | STATE_CPU_CPU (sd, 0)->pc = bfd_get_start_address (abfd); | |
115 | else | |
116 | STATE_CPU_CPU (sd, 0)->pc = 0; | |
646c6f2b DE |
117 | return SIM_RC_OK; |
118 | } | |
119 | ||
646c6f2b DE |
120 | int |
121 | sim_stop (SIM_DESC sd) | |
122 | { | |
123 | return engine_stop (sd); | |
124 | } | |
125 | ||
126 | void | |
127 | sim_resume (sd, step, siggnal) | |
128 | SIM_DESC sd; | |
129 | int step, siggnal; | |
130 | { | |
131 | engine_run (sd, step, siggnal); | |
132 | } | |
133 | ||
134 | void | |
135 | sim_stop_reason (sd, reason, sigrc) | |
136 | SIM_DESC sd; | |
137 | enum sim_stop *reason; | |
138 | int *sigrc; | |
139 | { | |
140 | sim_cpu *cpu = STATE_CPU (sd, 0); | |
141 | ||
142 | /* Map sim_state to sim_stop. */ | |
143 | switch (CPU_EXEC_STATE (cpu)) | |
144 | { | |
145 | case EXEC_STATE_EXITED : | |
146 | *reason = sim_exited; | |
147 | *sigrc = CPU_HALT_SIGRC (cpu); | |
148 | break; | |
149 | case EXEC_STATE_STOPPED : | |
150 | *reason = sim_stopped; | |
151 | *sigrc = sim_signal_to_host (CPU_HALT_SIGRC (cpu)); | |
152 | break; | |
153 | case EXEC_STATE_SIGNALLED : | |
154 | *reason = sim_signalled; | |
155 | *sigrc = sim_signal_to_host (CPU_HALT_SIGRC (cpu)); | |
156 | break; | |
157 | } | |
158 | } | |
159 | ||
160 | /* PROFILE_CPU_CALLBACK */ | |
161 | ||
162 | static void | |
163 | print_m32r_misc_cpu (SIM_CPU *cpu, int verbose) | |
164 | { | |
165 | SIM_DESC sd = CPU_STATE (cpu); | |
7a418800 | 166 | char buf[20]; |
646c6f2b DE |
167 | |
168 | if (CPU_PROFILE_FLAGS (cpu) [PROFILE_INSN_IDX]) | |
169 | { | |
170 | sim_io_printf (sd, "Miscellaneous Statistics\n\n"); | |
7a418800 | 171 | sim_io_printf (sd, " %-*s %s\n\n", |
646c6f2b | 172 | PROFILE_LABEL_WIDTH, "Fill nops:", |
7a418800 AC |
173 | sim_add_commas (buf, sizeof (buf), |
174 | CPU_M32R_PROFILE (cpu).fillnop_count)); | |
646c6f2b DE |
175 | } |
176 | } | |
177 | ||
178 | void | |
179 | sim_info (sd, verbose) | |
180 | SIM_DESC sd; | |
181 | int verbose; | |
182 | { | |
183 | profile_print (sd, STATE_VERBOSE_P (sd), NULL, print_m32r_misc_cpu); | |
184 | } | |
185 | ||
646c6f2b DE |
186 | /* The contents of BUF are in target byte order. */ |
187 | ||
188 | void | |
189 | sim_fetch_register (sd, rn, buf) | |
190 | SIM_DESC sd; | |
191 | int rn; | |
192 | unsigned char *buf; | |
193 | { | |
194 | if (rn < 16) | |
195 | SETTWI (buf, STATE_CPU_CPU (sd, 0)->h_gr[rn]); | |
196 | else if (rn < 21) | |
197 | SETTWI (buf, STATE_CPU_CPU (sd, 0)->h_cr[rn - 16]); | |
198 | else switch (rn) { | |
199 | case PC_REGNUM: | |
200 | SETTWI (buf, STATE_CPU_CPU (sd, 0)->pc); | |
201 | break; | |
202 | case ACCL_REGNUM: | |
203 | SETTWI (buf, GETLODI (STATE_CPU_CPU (sd, 0)->h_accum)); | |
204 | break; | |
205 | case ACCH_REGNUM: | |
206 | SETTWI (buf, GETHIDI (STATE_CPU_CPU (sd, 0)->h_accum)); | |
207 | break; | |
208 | #if 0 | |
209 | case 23: *reg = STATE_CPU_CPU (sd, 0)->h_cond; break; | |
210 | case 24: *reg = STATE_CPU_CPU (sd, 0)->h_sm; break; | |
211 | case 25: *reg = STATE_CPU_CPU (sd, 0)->h_bsm; break; | |
212 | case 26: *reg = STATE_CPU_CPU (sd, 0)->h_ie; break; | |
213 | case 27: *reg = STATE_CPU_CPU (sd, 0)->h_bie; break; | |
214 | case 28: *reg = STATE_CPU_CPU (sd, 0)->h_bcarry; break; /* rename: bc */ | |
215 | case 29: memcpy (buf, &STATE_CPU_CPU (sd, 0)->h_bpc, sizeof(WI)); break; /* duplicate */ | |
216 | #endif | |
217 | default: abort (); | |
218 | } | |
219 | } | |
220 | ||
221 | /* The contents of BUF are in target byte order. */ | |
222 | ||
223 | void | |
224 | sim_store_register (sd, rn, buf) | |
225 | SIM_DESC sd; | |
226 | int rn; | |
227 | unsigned char *buf; | |
228 | { | |
229 | if (rn < 16) | |
230 | STATE_CPU_CPU (sd, 0)->h_gr[rn] = GETTWI (buf); | |
231 | else if (rn < 21) | |
232 | STATE_CPU_CPU (sd, 0)->h_cr[rn - 16] = GETTWI (buf); | |
233 | else switch (rn) { | |
234 | case PC_REGNUM: | |
235 | STATE_CPU_CPU (sd, 0)->pc = GETTWI (buf); | |
236 | break; | |
237 | case ACCL_REGNUM: | |
238 | SETLODI (STATE_CPU_CPU (sd, 0)->h_accum, GETTWI (buf)); | |
239 | break; | |
240 | case ACCH_REGNUM: | |
241 | SETHIDI (STATE_CPU_CPU (sd, 0)->h_accum, GETTWI (buf)); | |
242 | break; | |
243 | #if 0 | |
244 | case 23: STATE_CPU_CPU (sd, 0)->h_cond = *reg; break; | |
245 | case 24: STATE_CPU_CPU (sd, 0)->h_sm = *reg; break; | |
246 | case 25: STATE_CPU_CPU (sd, 0)->h_bsm = *reg; break; | |
247 | case 26: STATE_CPU_CPU (sd, 0)->h_ie = *reg; break; | |
248 | case 27: STATE_CPU_CPU (sd, 0)->h_bie = *reg; break; | |
249 | case 28: STATE_CPU_CPU (sd, 0)->h_bcarry = *reg; break; /* rename: bc */ | |
250 | case 29: memcpy (&STATE_CPU_CPU (sd, 0)->h_bpc, buf, sizeof(DI)); break; /* duplicate */ | |
251 | #endif | |
252 | } | |
253 | } | |
254 | ||
255 | int | |
256 | sim_read (sd, addr, buf, len) | |
257 | SIM_DESC sd; | |
258 | SIM_ADDR addr; | |
259 | unsigned char *buf; | |
260 | int len; | |
261 | { | |
262 | #if 1 | |
247fccde | 263 | return sim_core_read_buffer (sd, NULL, sim_core_read_map, |
646c6f2b DE |
264 | buf, addr, len); |
265 | #else | |
266 | return (*STATE_MEM_READ (sd)) (sd, addr, buf, len); | |
267 | #endif | |
268 | } | |
269 | ||
270 | int | |
271 | sim_write (sd, addr, buf, len) | |
272 | SIM_DESC sd; | |
273 | SIM_ADDR addr; | |
274 | unsigned char *buf; | |
275 | int len; | |
276 | { | |
277 | #if 1 | |
247fccde | 278 | return sim_core_write_buffer (sd, NULL, sim_core_write_map, |
646c6f2b DE |
279 | buf, addr, len); |
280 | #else | |
281 | return (*STATE_MEM_WRITE (sd)) (sd, addr, buf, len); | |
282 | #endif | |
283 | } | |
284 | ||
285 | void | |
286 | sim_do_command (sd, cmd) | |
287 | SIM_DESC sd; | |
288 | char *cmd; | |
289 | { | |
290 | sim_io_error (sd, "sim_do_command - unimplemented"); | |
291 | } |