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c906108c SS |
1 | /* m32r exception, interrupt, and trap (EIT) support |
2 | Copyright (C) 1998 Free Software Foundation, Inc. | |
3 | Contributed by Cygnus Solutions. | |
4 | ||
5 | This file is part of GDB, the GNU debugger. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License along | |
18 | with this program; if not, write to the Free Software Foundation, Inc., | |
19 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
20 | ||
21 | #include "sim-main.h" | |
22 | #include "targ-vals.h" | |
23 | ||
2acceee2 JM |
24 | /* The semantic code invokes this for invalid (unrecognized) instructions. |
25 | CIA is the address with the invalid insn. | |
26 | VPC is the virtual pc of the following insn. */ | |
c906108c | 27 | |
2acceee2 JM |
28 | SEM_PC |
29 | sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia, SEM_PC vpc) | |
c906108c SS |
30 | { |
31 | SIM_DESC sd = CPU_STATE (current_cpu); | |
32 | ||
33 | #if 0 | |
34 | if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT) | |
35 | { | |
36 | h_bsm_set (current_cpu, h_sm_get (current_cpu)); | |
37 | h_bie_set (current_cpu, h_ie_get (current_cpu)); | |
38 | h_bcond_set (current_cpu, h_cond_get (current_cpu)); | |
39 | /* sm not changed */ | |
40 | h_ie_set (current_cpu, 0); | |
41 | h_cond_set (current_cpu, 0); | |
42 | ||
43 | h_bpc_set (current_cpu, cia); | |
44 | ||
45 | sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL, | |
46 | EIT_RSVD_INSN_ADDR); | |
47 | } | |
48 | else | |
49 | #endif | |
50 | sim_engine_halt (sd, current_cpu, NULL, cia, sim_stopped, SIM_SIGILL); | |
2acceee2 | 51 | return vpc; |
c906108c SS |
52 | } |
53 | ||
54 | /* Process an address exception. */ | |
55 | ||
56 | void | |
57 | m32r_core_signal (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia, | |
58 | unsigned int map, int nr_bytes, address_word addr, | |
59 | transfer_type transfer, sim_core_signals sig) | |
60 | { | |
61 | if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT) | |
62 | { | |
63 | a_m32r_h_cr_set (current_cpu, H_CR_BBPC, | |
64 | a_m32r_h_cr_get (current_cpu, H_CR_BPC)); | |
7a292a7a SS |
65 | if (MACH_NUM (CPU_MACH (current_cpu)) == MACH_M32R) |
66 | { | |
67 | m32rbf_h_bpsw_set (current_cpu, m32rbf_h_psw_get (current_cpu)); | |
68 | /* sm not changed */ | |
69 | m32rbf_h_psw_set (current_cpu, m32rbf_h_psw_get (current_cpu) & 0x80); | |
70 | } | |
71 | else | |
72 | { | |
73 | m32rxf_h_bpsw_set (current_cpu, m32rxf_h_psw_get (current_cpu)); | |
74 | /* sm not changed */ | |
75 | m32rxf_h_psw_set (current_cpu, m32rxf_h_psw_get (current_cpu) & 0x80); | |
76 | } | |
c906108c SS |
77 | a_m32r_h_cr_set (current_cpu, H_CR_BPC, cia); |
78 | ||
79 | sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL, | |
80 | EIT_ADDR_EXCP_ADDR); | |
81 | } | |
82 | else | |
83 | sim_core_signal (sd, current_cpu, cia, map, nr_bytes, addr, | |
84 | transfer, sig); | |
85 | } | |
86 | \f | |
87 | /* Read/write functions for system call interface. */ | |
88 | ||
89 | static int | |
90 | syscall_read_mem (host_callback *cb, struct cb_syscall *sc, | |
91 | unsigned long taddr, char *buf, int bytes) | |
92 | { | |
93 | SIM_DESC sd = (SIM_DESC) sc->p1; | |
94 | SIM_CPU *cpu = (SIM_CPU *) sc->p2; | |
95 | ||
96 | return sim_core_read_buffer (sd, cpu, read_map, buf, taddr, bytes); | |
97 | } | |
98 | ||
99 | static int | |
100 | syscall_write_mem (host_callback *cb, struct cb_syscall *sc, | |
101 | unsigned long taddr, const char *buf, int bytes) | |
102 | { | |
103 | SIM_DESC sd = (SIM_DESC) sc->p1; | |
104 | SIM_CPU *cpu = (SIM_CPU *) sc->p2; | |
105 | ||
106 | return sim_core_write_buffer (sd, cpu, write_map, buf, taddr, bytes); | |
107 | } | |
108 | ||
109 | /* Trap support. | |
110 | The result is the pc address to continue at. | |
111 | Preprocessing like saving the various registers has already been done. */ | |
112 | ||
113 | USI | |
114 | m32r_trap (SIM_CPU *current_cpu, PCADDR pc, int num) | |
115 | { | |
116 | SIM_DESC sd = CPU_STATE (current_cpu); | |
117 | host_callback *cb = STATE_CALLBACK (sd); | |
118 | ||
119 | #ifdef SIM_HAVE_BREAKPOINTS | |
120 | /* Check for breakpoints "owned" by the simulator first, regardless | |
121 | of --environment. */ | |
122 | if (num == TRAP_BREAKPOINT) | |
123 | { | |
124 | /* First try sim-break.c. If it's a breakpoint the simulator "owns" | |
125 | it doesn't return. Otherwise it returns and let's us try. */ | |
126 | sim_handle_breakpoint (sd, current_cpu, pc); | |
127 | /* Fall through. */ | |
128 | } | |
129 | #endif | |
130 | ||
131 | if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT) | |
132 | { | |
133 | /* The new pc is the trap vector entry. | |
134 | We assume there's a branch there to some handler. */ | |
135 | USI new_pc = EIT_TRAP_BASE_ADDR + num * 4; | |
136 | return new_pc; | |
137 | } | |
138 | ||
139 | switch (num) | |
140 | { | |
141 | case TRAP_SYSCALL : | |
142 | { | |
143 | CB_SYSCALL s; | |
144 | ||
145 | CB_SYSCALL_INIT (&s); | |
146 | s.func = a_m32r_h_gr_get (current_cpu, 0); | |
147 | s.arg1 = a_m32r_h_gr_get (current_cpu, 1); | |
148 | s.arg2 = a_m32r_h_gr_get (current_cpu, 2); | |
149 | s.arg3 = a_m32r_h_gr_get (current_cpu, 3); | |
150 | ||
151 | if (s.func == TARGET_SYS_exit) | |
152 | { | |
153 | sim_engine_halt (sd, current_cpu, NULL, pc, sim_exited, s.arg1); | |
154 | } | |
155 | ||
156 | s.p1 = (PTR) sd; | |
157 | s.p2 = (PTR) current_cpu; | |
158 | s.read_mem = syscall_read_mem; | |
159 | s.write_mem = syscall_write_mem; | |
160 | cb_syscall (cb, &s); | |
161 | a_m32r_h_gr_set (current_cpu, 2, s.errcode); | |
162 | a_m32r_h_gr_set (current_cpu, 0, s.result); | |
163 | a_m32r_h_gr_set (current_cpu, 1, s.result2); | |
164 | break; | |
165 | } | |
166 | ||
167 | case TRAP_BREAKPOINT: | |
168 | sim_engine_halt (sd, current_cpu, NULL, pc, | |
169 | sim_stopped, SIM_SIGTRAP); | |
170 | break; | |
171 | ||
172 | default : | |
173 | { | |
174 | USI new_pc = EIT_TRAP_BASE_ADDR + num * 4; | |
175 | return new_pc; | |
176 | } | |
177 | } | |
178 | ||
179 | /* Fake an "rte" insn. */ | |
180 | /* FIXME: Should duplicate all of rte processing. */ | |
181 | return (pc & -4) + 4; | |
182 | } |