Commit | Line | Data |
---|---|---|
e0709f50 AC |
1 | /* dv-m68hc11spi.c -- Simulation of the 68HC11 SPI |
2 | Copyright (C) 2000 Free Software Foundation, Inc. | |
3 | Written by Stephane Carrez (stcarrez@worldnet.fr) | |
4 | (From a driver model Contributed by Cygnus Solutions.) | |
5 | ||
6 | This file is part of the program GDB, the GNU debugger. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program; if not, write to the Free Software | |
20 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
21 | ||
22 | */ | |
23 | ||
24 | ||
25 | #include "sim-main.h" | |
26 | #include "hw-main.h" | |
27 | #include "dv-sockser.h" | |
28 | #include "sim-assert.h" | |
29 | ||
30 | ||
31 | /* DEVICE | |
32 | ||
33 | m68hc11spi - m68hc11 SPI interface | |
34 | ||
35 | ||
36 | DESCRIPTION | |
37 | ||
38 | Implements the m68hc11 Synchronous Serial Peripheral Interface | |
39 | described in the m68hc11 user guide (Chapter 8 in pink book). | |
40 | The SPI I/O controller is directly connected to the CPU | |
41 | interrupt. The simulator implements: | |
42 | ||
43 | - SPI clock emulation | |
44 | - Data transfer | |
45 | - Write collision detection | |
46 | ||
47 | ||
48 | PROPERTIES | |
49 | ||
50 | None | |
51 | ||
52 | ||
53 | PORTS | |
54 | ||
55 | reset (input) | |
56 | ||
57 | Reset port. This port is only used to simulate a reset of the SPI | |
58 | I/O controller. It should be connected to the RESET output of the cpu. | |
59 | ||
60 | */ | |
61 | ||
62 | ||
63 | ||
64 | /* port ID's */ | |
65 | ||
66 | enum | |
67 | { | |
68 | RESET_PORT | |
69 | }; | |
70 | ||
71 | ||
72 | static const struct hw_port_descriptor m68hc11spi_ports[] = | |
73 | { | |
74 | { "reset", RESET_PORT, 0, input_port, }, | |
75 | { NULL, }, | |
76 | }; | |
77 | ||
78 | ||
79 | /* SPI */ | |
80 | struct m68hc11spi | |
81 | { | |
82 | /* Information about next character to be transmited. */ | |
83 | unsigned char tx_char; | |
84 | int tx_bit; | |
85 | unsigned char mode; | |
86 | ||
87 | unsigned char rx_char; | |
88 | unsigned char rx_clear_scsr; | |
89 | unsigned char clk_pin; | |
90 | ||
91 | /* SPI clock rate (twice the real clock). */ | |
92 | unsigned int clock; | |
93 | ||
94 | /* Periodic SPI event. */ | |
95 | struct hw_event* spi_event; | |
96 | }; | |
97 | ||
98 | ||
99 | ||
100 | /* Finish off the partially created hw device. Attach our local | |
101 | callbacks. Wire up our port names etc */ | |
102 | ||
103 | static hw_io_read_buffer_method m68hc11spi_io_read_buffer; | |
104 | static hw_io_write_buffer_method m68hc11spi_io_write_buffer; | |
105 | static hw_port_event_method m68hc11spi_port_event; | |
106 | static hw_ioctl_method m68hc11spi_ioctl; | |
107 | ||
108 | #define M6811_SPI_FIRST_REG (M6811_SPCR) | |
109 | #define M6811_SPI_LAST_REG (M6811_SPDR) | |
110 | ||
111 | ||
112 | static void | |
113 | attach_m68hc11spi_regs (struct hw *me, | |
114 | struct m68hc11spi *controller) | |
115 | { | |
63348d04 | 116 | hw_attach_address (hw_parent (me), M6811_IO_LEVEL, io_map, |
e0709f50 AC |
117 | M6811_SPI_FIRST_REG, |
118 | M6811_SPI_LAST_REG - M6811_SPI_FIRST_REG + 1, | |
119 | me); | |
120 | } | |
121 | ||
122 | static void | |
123 | m68hc11spi_finish (struct hw *me) | |
124 | { | |
125 | struct m68hc11spi *controller; | |
126 | ||
127 | controller = HW_ZALLOC (me, struct m68hc11spi); | |
e0709f50 AC |
128 | set_hw_data (me, controller); |
129 | set_hw_io_read_buffer (me, m68hc11spi_io_read_buffer); | |
130 | set_hw_io_write_buffer (me, m68hc11spi_io_write_buffer); | |
131 | set_hw_ports (me, m68hc11spi_ports); | |
132 | set_hw_port_event (me, m68hc11spi_port_event); | |
133 | #ifdef set_hw_ioctl | |
134 | set_hw_ioctl (me, m68hc11spi_ioctl); | |
135 | #else | |
136 | me->to_ioctl = m68hc11spi_ioctl; | |
137 | #endif | |
138 | ||
139 | /* Attach ourself to our parent bus. */ | |
140 | attach_m68hc11spi_regs (me, controller); | |
141 | ||
142 | /* Initialize to reset state. */ | |
143 | controller->spi_event = NULL; | |
144 | controller->rx_clear_scsr = 0; | |
145 | } | |
146 | ||
147 | ||
148 | ||
149 | /* An event arrives on an interrupt port */ | |
150 | ||
151 | static void | |
152 | m68hc11spi_port_event (struct hw *me, | |
153 | int my_port, | |
154 | struct hw *source, | |
155 | int source_port, | |
156 | int level) | |
157 | { | |
158 | SIM_DESC sd; | |
159 | struct m68hc11spi *controller; | |
160 | sim_cpu* cpu; | |
161 | unsigned8 val; | |
162 | ||
163 | controller = hw_data (me); | |
164 | sd = hw_system (me); | |
165 | cpu = STATE_CPU (sd, 0); | |
166 | switch (my_port) | |
167 | { | |
168 | case RESET_PORT: | |
169 | { | |
170 | HW_TRACE ((me, "SPI reset")); | |
171 | ||
172 | /* Reset the state of SPI registers. */ | |
173 | controller->rx_clear_scsr = 0; | |
174 | if (controller->spi_event) | |
175 | { | |
176 | hw_event_queue_deschedule (me, controller->spi_event); | |
177 | controller->spi_event = 0; | |
178 | } | |
179 | ||
180 | val = 0; | |
181 | m68hc11spi_io_write_buffer (me, &val, io_map, | |
182 | (unsigned_word) M6811_SPCR, 1); | |
183 | break; | |
184 | } | |
185 | ||
186 | default: | |
187 | hw_abort (me, "Event on unknown port %d", my_port); | |
188 | break; | |
189 | } | |
190 | } | |
191 | ||
192 | static void | |
193 | set_bit_port (struct hw *me, sim_cpu *cpu, int port, int mask, int value) | |
194 | { | |
195 | /* TODO: Post an event to inform other devices that pin 'port' changes. | |
196 | This has only a sense if we provide some device that is logically | |
197 | connected to these pin ports (SCLK and MOSI) and that handles | |
198 | the SPI protocol. */ | |
199 | if (value) | |
200 | cpu->ios[port] |= mask; | |
201 | else | |
202 | cpu->ios[port] &= ~mask; | |
203 | } | |
204 | ||
205 | ||
206 | /* When a character is sent/received by the SPI, the PD2..PD5 line | |
207 | are driven by the following signals: | |
208 | ||
209 | B7 B6 | |
210 | -----+---------+--------+---/-+------- | |
211 | MOSI | | | | | | | |
212 | MISO +---------+--------+---/-+ | |
213 | ____ ___ | |
214 | CLK _______/ \____/ \__ CPOL=0, CPHA=0 | |
215 | _______ ____ __ | |
216 | \____/ \___/ CPOL=1, CPHA=0 | |
217 | ____ ____ __ | |
218 | __/ \____/ \___/ CPOL=0, CPHA=1 | |
219 | __ ____ ___ | |
220 | \____/ \____/ \__ CPOL=1, CPHA=1 | |
221 | ||
222 | SS ___ ____ | |
223 | \__________________________//___/ | |
224 | ||
225 | MISO = PD2 | |
226 | MOSI = PD3 | |
227 | SCK = PD4 | |
228 | SS = PD5 | |
229 | ||
230 | */ | |
231 | ||
232 | #define SPI_START_BIT 0 | |
233 | #define SPI_MIDDLE_BIT 1 | |
234 | ||
235 | void | |
236 | m68hc11spi_clock (struct hw *me, void *data) | |
237 | { | |
238 | SIM_DESC sd; | |
239 | struct m68hc11spi* controller; | |
240 | sim_cpu *cpu; | |
241 | int check_interrupt = 0; | |
242 | ||
243 | controller = hw_data (me); | |
244 | sd = hw_system (me); | |
245 | cpu = STATE_CPU (sd, 0); | |
246 | ||
247 | /* Cleanup current event. */ | |
248 | if (controller->spi_event) | |
249 | { | |
250 | hw_event_queue_deschedule (me, controller->spi_event); | |
251 | controller->spi_event = 0; | |
252 | } | |
253 | ||
254 | /* Change a bit of data at each two SPI event. */ | |
255 | if (controller->mode == SPI_START_BIT) | |
256 | { | |
257 | /* Reflect the bit value on bit 2 of port D. */ | |
258 | set_bit_port (me, cpu, M6811_PORTD, (1 << 2), | |
259 | (controller->tx_char & (1 << controller->tx_bit))); | |
260 | controller->tx_bit--; | |
261 | controller->mode = SPI_MIDDLE_BIT; | |
262 | } | |
263 | else | |
264 | { | |
265 | controller->mode = SPI_START_BIT; | |
266 | } | |
267 | ||
268 | /* Change the SPI clock at each event on bit 4 of port D. */ | |
269 | controller->clk_pin = ~controller->clk_pin; | |
270 | set_bit_port (me, cpu, M6811_PORTD, (1 << 4), controller->clk_pin); | |
271 | ||
272 | /* Transmit is now complete for this byte. */ | |
273 | if (controller->mode == SPI_START_BIT && controller->tx_bit < 0) | |
274 | { | |
275 | controller->rx_clear_scsr = 0; | |
276 | cpu->ios[M6811_SPSR] |= M6811_SPIF; | |
277 | if (cpu->ios[M6811_SPCR] & M6811_SPIE) | |
278 | check_interrupt = 1; | |
279 | } | |
280 | else | |
281 | { | |
282 | controller->spi_event = hw_event_queue_schedule (me, controller->clock, | |
283 | m68hc11spi_clock, | |
284 | NULL); | |
285 | } | |
286 | ||
287 | if (check_interrupt) | |
288 | interrupts_update_pending (&cpu->cpu_interrupts); | |
289 | } | |
290 | ||
291 | /* Flags of the SPCR register. */ | |
292 | io_reg_desc spcr_desc[] = { | |
293 | { M6811_SPIE, "SPIE ", "Serial Peripheral Interrupt Enable" }, | |
294 | { M6811_SPE, "SPE ", "Serial Peripheral System Enable" }, | |
295 | { M6811_DWOM, "DWOM ", "Port D Wire-OR mode option" }, | |
296 | { M6811_MSTR, "MSTR ", "Master Mode Select" }, | |
297 | { M6811_CPOL, "CPOL ", "Clock Polarity" }, | |
298 | { M6811_CPHA, "CPHA ", "Clock Phase" }, | |
299 | { M6811_SPR1, "SPR1 ", "SPI Clock Rate Select" }, | |
300 | { M6811_SPR0, "SPR0 ", "SPI Clock Rate Select" }, | |
301 | { 0, 0, 0 } | |
302 | }; | |
303 | ||
304 | ||
305 | /* Flags of the SPSR register. */ | |
306 | io_reg_desc spsr_desc[] = { | |
307 | { M6811_SPIF, "SPIF ", "SPI Transfer Complete flag" }, | |
308 | { M6811_WCOL, "WCOL ", "Write Collision" }, | |
309 | { M6811_MODF, "MODF ", "Mode Fault" }, | |
310 | { 0, 0, 0 } | |
311 | }; | |
312 | ||
313 | static void | |
314 | m68hc11spi_info (struct hw *me) | |
315 | { | |
316 | SIM_DESC sd; | |
317 | uint16 base = 0; | |
318 | sim_cpu *cpu; | |
319 | struct m68hc11spi *controller; | |
320 | uint8 val; | |
321 | ||
322 | sd = hw_system (me); | |
323 | cpu = STATE_CPU (sd, 0); | |
324 | controller = hw_data (me); | |
325 | ||
326 | sim_io_printf (sd, "M68HC11 SPI:\n"); | |
327 | ||
328 | base = cpu_get_io_base (cpu); | |
329 | ||
330 | val = cpu->ios[M6811_SPCR]; | |
331 | print_io_byte (sd, "SPCR", spcr_desc, val, base + M6811_SPCR); | |
332 | sim_io_printf (sd, "\n"); | |
333 | ||
334 | val = cpu->ios[M6811_SPSR]; | |
335 | print_io_byte (sd, "SPSR", spsr_desc, val, base + M6811_SPSR); | |
336 | sim_io_printf (sd, "\n"); | |
337 | ||
338 | if (controller->spi_event) | |
339 | { | |
340 | signed64 t; | |
341 | ||
342 | t = hw_event_remain_time (me, controller->spi_event); | |
343 | sim_io_printf (sd, " SPI operation finished in %ld cycles\n", | |
344 | (long) t); | |
345 | } | |
346 | } | |
347 | ||
348 | static int | |
349 | m68hc11spi_ioctl (struct hw *me, | |
350 | hw_ioctl_request request, | |
351 | va_list ap) | |
352 | { | |
353 | m68hc11spi_info (me); | |
354 | return 0; | |
355 | } | |
356 | ||
357 | /* generic read/write */ | |
358 | ||
359 | static unsigned | |
360 | m68hc11spi_io_read_buffer (struct hw *me, | |
361 | void *dest, | |
362 | int space, | |
363 | unsigned_word base, | |
364 | unsigned nr_bytes) | |
365 | { | |
366 | SIM_DESC sd; | |
367 | struct m68hc11spi *controller; | |
368 | sim_cpu *cpu; | |
369 | unsigned8 val; | |
370 | ||
371 | HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes)); | |
372 | ||
373 | sd = hw_system (me); | |
374 | cpu = STATE_CPU (sd, 0); | |
375 | controller = hw_data (me); | |
376 | ||
377 | switch (base) | |
378 | { | |
379 | case M6811_SPSR: | |
380 | controller->rx_clear_scsr = cpu->ios[M6811_SCSR] | |
381 | & (M6811_SPIF | M6811_WCOL | M6811_MODF); | |
382 | ||
383 | case M6811_SPCR: | |
384 | val = cpu->ios[base]; | |
385 | break; | |
386 | ||
387 | case M6811_SPDR: | |
388 | if (controller->rx_clear_scsr) | |
389 | { | |
390 | cpu->ios[M6811_SPSR] &= ~controller->rx_clear_scsr; | |
391 | controller->rx_clear_scsr = 0; | |
392 | } | |
393 | val = controller->rx_char; | |
394 | break; | |
395 | ||
396 | default: | |
397 | return 0; | |
398 | } | |
399 | *((unsigned8*) dest) = val; | |
400 | return 1; | |
401 | } | |
402 | ||
403 | static unsigned | |
404 | m68hc11spi_io_write_buffer (struct hw *me, | |
405 | const void *source, | |
406 | int space, | |
407 | unsigned_word base, | |
408 | unsigned nr_bytes) | |
409 | { | |
410 | SIM_DESC sd; | |
411 | struct m68hc11spi *controller; | |
412 | sim_cpu *cpu; | |
413 | unsigned8 val; | |
414 | ||
415 | HW_TRACE ((me, "write 0x%08lx %d", (long) base, (int) nr_bytes)); | |
416 | ||
417 | sd = hw_system (me); | |
418 | cpu = STATE_CPU (sd, 0); | |
419 | controller = hw_data (me); | |
420 | ||
421 | val = *((const unsigned8*) source); | |
422 | switch (base) | |
423 | { | |
424 | case M6811_SPCR: | |
425 | cpu->ios[M6811_SPCR] = val; | |
426 | ||
427 | /* The SPI clock rate is 2, 4, 16, 32 of the internal CPU clock. | |
428 | We have to drive the clock pin and need a 2x faster clock. */ | |
429 | switch (val & (M6811_SPR1 | M6811_SPR0)) | |
430 | { | |
431 | case 0: | |
432 | controller->clock = 1; | |
433 | break; | |
434 | ||
435 | case 1: | |
436 | controller->clock = 2; | |
437 | break; | |
438 | ||
439 | case 2: | |
440 | controller->clock = 8; | |
441 | break; | |
442 | ||
443 | default: | |
444 | controller->clock = 16; | |
445 | break; | |
446 | } | |
447 | ||
448 | /* Set the clock pin. */ | |
449 | if ((val & M6811_CPOL) | |
450 | && (controller->spi_event == 0 | |
451 | || ((val & M6811_CPHA) && controller->mode == 1))) | |
452 | controller->clk_pin = 1; | |
453 | else | |
454 | controller->clk_pin = 0; | |
455 | ||
456 | set_bit_port (me, cpu, M6811_PORTD, (1 << 4), controller->clk_pin); | |
457 | break; | |
458 | ||
459 | /* Can't write to SPSR. */ | |
460 | case M6811_SPSR: | |
461 | break; | |
462 | ||
463 | case M6811_SPDR: | |
464 | if (!(cpu->ios[M6811_SPCR] & M6811_SPE)) | |
465 | { | |
466 | return 0; | |
467 | } | |
468 | ||
469 | /* If transfer is taking place, a write to SPDR | |
470 | generates a collision. */ | |
471 | if (controller->spi_event) | |
472 | { | |
473 | cpu->ios[M6811_SPSR] |= M6811_WCOL; | |
474 | break; | |
475 | } | |
476 | ||
477 | /* Refuse the write if there was no read of SPSR. */ | |
478 | /* ???? TBD. */ | |
479 | ||
480 | /* Prepare to send a byte. */ | |
481 | controller->tx_char = val; | |
482 | controller->tx_bit = 7; | |
483 | controller->mode = 0; | |
484 | ||
485 | /* Toggle clock pin internal value when CPHA is 0 so that | |
486 | it will really change in the middle of a bit. */ | |
487 | if (!(cpu->ios[M6811_SPCR] & M6811_CPHA)) | |
488 | controller->clk_pin = ~controller->clk_pin; | |
489 | ||
490 | cpu->ios[M6811_SPDR] = val; | |
491 | ||
492 | /* Activate transmission. */ | |
493 | m68hc11spi_clock (me, NULL); | |
494 | break; | |
495 | ||
496 | default: | |
497 | return 0; | |
498 | } | |
499 | return nr_bytes; | |
500 | } | |
501 | ||
502 | ||
503 | const struct hw_descriptor dv_m68hc11spi_descriptor[] = { | |
504 | { "m68hc11spi", m68hc11spi_finish, }, | |
505 | { NULL }, | |
506 | }; | |
507 |