[deliverable/binutils-gdb.git] / sim / m68hc11 / dv-m68hc11spi.c

/*  dv-m68hc11spi.c -- Simulation of the 68HC11 SPI
    Copyright (C) 2000 Free Software Foundation, Inc.
    Written by Stephane Carrez (stcarrez@worldnet.fr)
    (From a driver model Contributed by Cygnus Solutions.)

    This file is part of the program GDB, the GNU debugger.
    
    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 2 of the License, or
    (at your option) any later version.
    
    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.
    
    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
    
    */


#include "sim-main.h"
#include "hw-main.h"
#include "dv-sockser.h"
#include "sim-assert.h"


/* DEVICE

        m68hc11spi - m68hc11 SPI interface

   
   DESCRIPTION

        Implements the m68hc11 Synchronous Serial Peripheral Interface
        described in the m68hc11 user guide (Chapter 8 in pink book).
        The SPI I/O controller is directly connected to the CPU
        interrupt.  The simulator implements:

            - SPI clock emulation
            - Data transfer
            - Write collision detection
    

   PROPERTIES

        None

   
   PORTS

   reset (input)

        Reset port. This port is only used to simulate a reset of the SPI
        I/O controller. It should be connected to the RESET output of the cpu.

   */


/* port ID's */

enum
{
  RESET_PORT
};


static const struct hw_port_descriptor m68hc11spi_ports[] = 
{
  { "reset", RESET_PORT, 0, input_port, },
  { NULL, },
};


/* SPI */
struct m68hc11spi 
{
  /* Information about next character to be transmited.  */
  unsigned char tx_char;
  int           tx_bit;
  unsigned char mode;
  
  unsigned char rx_char;
  unsigned char rx_clear_scsr;
  unsigned char clk_pin;
  
  /* SPI clock rate (twice the real clock).  */
  unsigned int clock;
  
  /* Periodic SPI event.  */
  struct hw_event* spi_event;
};


/* Finish off the partially created hw device.  Attach our local
   callbacks.  Wire up our port names etc */

static hw_io_read_buffer_method m68hc11spi_io_read_buffer;
static hw_io_write_buffer_method m68hc11spi_io_write_buffer;
static hw_port_event_method m68hc11spi_port_event;
static hw_ioctl_method m68hc11spi_ioctl;

#define M6811_SPI_FIRST_REG (M6811_SPCR)
#define M6811_SPI_LAST_REG  (M6811_SPDR)


static void
attach_m68hc11spi_regs (struct hw *me,
                        struct m68hc11spi *controller)
{
  hw_attach_address (hw_parent (me), M6811_IO_LEVEL, io_map,
                     M6811_SPI_FIRST_REG,
                     M6811_SPI_LAST_REG - M6811_SPI_FIRST_REG + 1,
		     me);
}

static void
m68hc11spi_finish (struct hw *me)
{
  struct m68hc11spi *controller;

  controller = HW_ZALLOC (me, struct m68hc11spi);
  set_hw_data (me, controller);
  set_hw_io_read_buffer (me, m68hc11spi_io_read_buffer);
  set_hw_io_write_buffer (me, m68hc11spi_io_write_buffer);
  set_hw_ports (me, m68hc11spi_ports);
  set_hw_port_event (me, m68hc11spi_port_event);
#ifdef set_hw_ioctl
  set_hw_ioctl (me, m68hc11spi_ioctl);
#else
  me->to_ioctl = m68hc11spi_ioctl;
#endif

  /* Attach ourself to our parent bus.  */
  attach_m68hc11spi_regs (me, controller);

  /* Initialize to reset state.  */
  controller->spi_event = NULL;
  controller->rx_clear_scsr = 0;
}


/* An event arrives on an interrupt port */

static void
m68hc11spi_port_event (struct hw *me,
                       int my_port,
                       struct hw *source,
                       int source_port,
                       int level)
{
  SIM_DESC sd;
  struct m68hc11spi *controller;
  sim_cpu* cpu;
  unsigned8 val;
  
  controller = hw_data (me);
  sd         = hw_system (me);
  cpu        = STATE_CPU (sd, 0);  
  switch (my_port)
    {
    case RESET_PORT:
      {
	HW_TRACE ((me, "SPI reset"));

        /* Reset the state of SPI registers.  */
        controller->rx_clear_scsr = 0;
        if (controller->spi_event)
          {
            hw_event_queue_deschedule (me, controller->spi_event);
            controller->spi_event = 0;
          }

        val = 0;
        m68hc11spi_io_write_buffer (me, &val, io_map,
                                    (unsigned_word) M6811_SPCR, 1);
        break;
      }

    default:
      hw_abort (me, "Event on unknown port %d", my_port);
      break;
    }
}

static void
set_bit_port (struct hw *me, sim_cpu *cpu, int port, int mask, int value)
{
  /* TODO: Post an event to inform other devices that pin 'port' changes.
     This has only a sense if we provide some device that is logically
     connected to these pin ports (SCLK and MOSI) and that handles
     the SPI protocol.  */
  if (value)
    cpu->ios[port] |= mask;
  else
    cpu->ios[port] &= ~mask;
}


/* When a character is sent/received by the SPI, the PD2..PD5 line
   are driven by the following signals:

	      B7	B6
      -----+---------+--------+---/-+-------
 MOSI      |    |    |   |    |     |
 MISO	   +---------+--------+---/-+
		____      ___
 CLK	_______/    \____/   \__		CPOL=0, CPHA=0
	_______	     ____     __
	       \____/    \___/			CPOL=1, CPHA=0
	   ____	     ____     __
	__/    \____/    \___/			CPOL=0, CPHA=1
	__	____      ___
	  \____/    \____/   \__		CPOL=1, CPHA=1

 SS ___                                 ____
       \__________________________//___/

 MISO = PD2
 MOSI = PD3
 SCK  = PD4
 SS   = PD5

*/

#define SPI_START_BYTE 0
#define SPI_START_BIT  1
#define SPI_MIDDLE_BIT 2

void
m68hc11spi_clock (struct hw *me, void *data)
{
  SIM_DESC sd;
  struct m68hc11spi* controller;
  sim_cpu *cpu;
  int check_interrupt = 0;
  
  controller = hw_data (me);
  sd         = hw_system (me);
  cpu        = STATE_CPU (sd, 0);

  /* Cleanup current event.  */
  if (controller->spi_event)
    {
      hw_event_queue_deschedule (me, controller->spi_event);
      controller->spi_event = 0;
    }

  /* Change a bit of data at each two SPI event.  */
  if (controller->mode == SPI_START_BIT)
    {
      /* Reflect the bit value on bit 2 of port D.  */
      set_bit_port (me, cpu, M6811_PORTD, (1 << 2),
                    (controller->tx_char & (1 << controller->tx_bit)));
      controller->tx_bit--;
      controller->mode = SPI_MIDDLE_BIT;
    }
  else if (controller->mode == SPI_MIDDLE_BIT)
    {
      controller->mode = SPI_START_BIT;
    }

  if (controller->mode == SPI_START_BYTE)
    {
      /* Start a new SPI transfer.  */
      
      /* TBD: clear SS output.  */
      controller->mode = SPI_START_BIT;
      controller->tx_bit = 7;
      set_bit_port (me, cpu, M6811_PORTD, (1 << 4), ~controller->clk_pin);
    }
  else
    {
      /* Change the SPI clock at each event on bit 4 of port D.  */
      controller->clk_pin = ~controller->clk_pin;
      set_bit_port (me, cpu, M6811_PORTD, (1 << 4), controller->clk_pin);
    }
  
  /* Transmit is now complete for this byte.  */
  if (controller->mode == SPI_START_BIT && controller->tx_bit < 0)
    {
      controller->rx_clear_scsr = 0;
      cpu->ios[M6811_SPSR] |= M6811_SPIF;
      if (cpu->ios[M6811_SPCR] & M6811_SPIE)
        check_interrupt = 1;
    }
  else
    {
      controller->spi_event = hw_event_queue_schedule (me, controller->clock,
                                                       m68hc11spi_clock,
                                                       NULL);
    }

  if (check_interrupt)
    interrupts_update_pending (&cpu->cpu_interrupts);
}

/* Flags of the SPCR register.  */
io_reg_desc spcr_desc[] = {
  { M6811_SPIE, "SPIE ", "Serial Peripheral Interrupt Enable" },
  { M6811_SPE,  "SPE  ",  "Serial Peripheral System Enable" },
  { M6811_DWOM, "DWOM ", "Port D Wire-OR mode option" },
  { M6811_MSTR, "MSTR ", "Master Mode Select" },
  { M6811_CPOL, "CPOL ", "Clock Polarity" },
  { M6811_CPHA, "CPHA ", "Clock Phase" },
  { M6811_SPR1, "SPR1 ", "SPI Clock Rate Select" },
  { M6811_SPR0, "SPR0 ", "SPI Clock Rate Select" },
  { 0,  0, 0 }
};


/* Flags of the SPSR register.  */
io_reg_desc spsr_desc[] = {
  { M6811_SPIF,	"SPIF ", "SPI Transfer Complete flag" },
  { M6811_WCOL, "WCOL ", "Write Collision" },
  { M6811_MODF, "MODF ", "Mode Fault" },
  { 0,  0, 0 }
};

static void
m68hc11spi_info (struct hw *me)
{
  SIM_DESC sd;
  uint16 base = 0;
  sim_cpu *cpu;
  struct m68hc11spi *controller;
  uint8 val;
  
  sd = hw_system (me);
  cpu = STATE_CPU (sd, 0);
  controller = hw_data (me);
  
  sim_io_printf (sd, "M68HC11 SPI:\n");

  base = cpu_get_io_base (cpu);

  val = cpu->ios[M6811_SPCR];
  print_io_byte (sd, "SPCR", spcr_desc, val, base + M6811_SPCR);
  sim_io_printf (sd, "\n");

  val = cpu->ios[M6811_SPSR];
  print_io_byte (sd, "SPSR", spsr_desc, val, base + M6811_SPSR);
  sim_io_printf (sd, "\n");

  if (controller->spi_event)
    {
      signed64 t;

      sim_io_printf (sd, "  SPI has %d bits to send\n",
                     controller->tx_bit + 1);
      t = hw_event_remain_time (me, controller->spi_event);
      sim_io_printf (sd, "  SPI operation finished in %ld cycles\n",
		     (long) t);
    }
}

static int
m68hc11spi_ioctl (struct hw *me,
                  hw_ioctl_request request,
                  va_list ap)
{
  m68hc11spi_info (me);
  return 0;
}

/* generic read/write */

static unsigned
m68hc11spi_io_read_buffer (struct hw *me,
                           void *dest,
                           int space,
                           unsigned_word base,
                           unsigned nr_bytes)
{
  SIM_DESC sd;
  struct m68hc11spi *controller;
  sim_cpu *cpu;
  unsigned8 val;
  
  HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes));

  sd  = hw_system (me);
  cpu = STATE_CPU (sd, 0);
  controller = hw_data (me);

  switch (base)
    {
    case M6811_SPSR:
      controller->rx_clear_scsr = cpu->ios[M6811_SCSR]
        & (M6811_SPIF | M6811_WCOL | M6811_MODF);
      
    case M6811_SPCR:
      val = cpu->ios[base];
      break;
      
    case M6811_SPDR:
      if (controller->rx_clear_scsr)
        {
          cpu->ios[M6811_SPSR] &= ~controller->rx_clear_scsr;
          controller->rx_clear_scsr = 0;
          interrupts_update_pending (&cpu->cpu_interrupts);
        }
      val = controller->rx_char;
      break;
      
    default:
      return 0;
    }
  *((unsigned8*) dest) = val;
  return 1;
}

static unsigned
m68hc11spi_io_write_buffer (struct hw *me,
                            const void *source,
                            int space,
                            unsigned_word base,
                            unsigned nr_bytes)
{
  SIM_DESC sd;
  struct m68hc11spi *controller;
  sim_cpu *cpu;
  unsigned8 val;

  HW_TRACE ((me, "write 0x%08lx %d", (long) base, (int) nr_bytes));

  sd  = hw_system (me);
  cpu = STATE_CPU (sd, 0);
  controller = hw_data (me);
  
  val = *((const unsigned8*) source);
  switch (base)
    {
    case M6811_SPCR:
      cpu->ios[M6811_SPCR] = val;

      /* The SPI clock rate is 2, 4, 16, 32 of the internal CPU clock.
         We have to drive the clock pin and need a 2x faster clock.  */
      switch (val & (M6811_SPR1 | M6811_SPR0))
        {
        case 0:
          controller->clock = 1;
          break;

        case 1:
          controller->clock = 2;
          break;

        case 2:
          controller->clock = 8;
          break;

        default:
          controller->clock = 16;
          break;
        }

      /* Set the clock pin.  */
      if ((val & M6811_CPOL)
          && (controller->spi_event == 0
              || ((val & M6811_CPHA) && controller->mode == 1)))
        controller->clk_pin = 1;
      else
        controller->clk_pin = 0;

      set_bit_port (me, cpu, M6811_PORTD, (1 << 4), controller->clk_pin);
      break;
      
      /* Can't write to SPSR.  */
    case M6811_SPSR:
      break;
      
    case M6811_SPDR:
      if (!(cpu->ios[M6811_SPCR] & M6811_SPE))
        {
          return 0;
        }

      if (controller->rx_clear_scsr)
        {
          cpu->ios[M6811_SPSR] &= ~controller->rx_clear_scsr;
          controller->rx_clear_scsr = 0;
          interrupts_update_pending (&cpu->cpu_interrupts);
        }

      /* If transfer is taking place, a write to SPDR
         generates a collision.  */
      if (controller->spi_event)
        {
          cpu->ios[M6811_SPSR] |= M6811_WCOL;
          break;
        }

      /* Refuse the write if there was no read of SPSR.  */
      /* ???? TBD. */

      /* Prepare to send a byte.  */
      controller->tx_char = val;
      controller->mode   = SPI_START_BYTE;

      /* Toggle clock pin internal value when CPHA is 0 so that
         it will really change in the middle of a bit.  */
      if (!(cpu->ios[M6811_SPCR] & M6811_CPHA))
        controller->clk_pin = ~controller->clk_pin;

      cpu->ios[M6811_SPDR] = val;

      /* Activate transmission.  */
      m68hc11spi_clock (me, NULL);
      break;

    default:
      return 0;
    }
  return nr_bytes;
}     


const struct hw_descriptor dv_m68hc11spi_descriptor[] = {
  { "m68hc11spi", m68hc11spi_finish, },
  { NULL },
};
Commit	Line	Data
e0709f50 AC	1	/* dv-m68hc11spi.c -- Simulation of the 68HC11 SPI
	2	Copyright (C) 2000 Free Software Foundation, Inc.
	3	Written by Stephane Carrez (stcarrez@worldnet.fr)
	4	(From a driver model Contributed by Cygnus Solutions.)
	5
	6	This file is part of the program GDB, the GNU debugger.
	7
	8	This program is free software; you can redistribute it and/or modify
	9	it under the terms of the GNU General Public License as published by
	10	the Free Software Foundation; either version 2 of the License, or
	11	(at your option) any later version.
	12
	13	This program is distributed in the hope that it will be useful,
	14	but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	GNU General Public License for more details.
	17
	18	You should have received a copy of the GNU General Public License
	19	along with this program; if not, write to the Free Software
	20	Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
	21
	22	*/
	23
	24
	25	#include "sim-main.h"
	26	#include "hw-main.h"
	27	#include "dv-sockser.h"
	28	#include "sim-assert.h"
	29
	30
	31	/* DEVICE
	32
	33	m68hc11spi - m68hc11 SPI interface
	34
	35
	36	DESCRIPTION
	37
	38	Implements the m68hc11 Synchronous Serial Peripheral Interface
	39	described in the m68hc11 user guide (Chapter 8 in pink book).
	40	The SPI I/O controller is directly connected to the CPU
	41	interrupt. The simulator implements:
	42
	43	- SPI clock emulation
	44	- Data transfer
	45	- Write collision detection
	46
	47
	48	PROPERTIES
	49
	50	None
	51
	52
	53	PORTS
	54
	55	reset (input)
	56
	57	Reset port. This port is only used to simulate a reset of the SPI
	58	I/O controller. It should be connected to the RESET output of the cpu.
	59
	60	*/
	61
	62
	63
	64	/* port ID's */
65
66	enum
67	{
68	RESET_PORT
69	};
70
71
72	static const struct hw_port_descriptor m68hc11spi_ports[] =
73	{
74	{ "reset", RESET_PORT, 0, input_port, },
75	{ NULL, },
76	};
77
78
79	/* SPI */
80	struct m68hc11spi
81	{
82	/* Information about next character to be transmited. */
83	unsigned char tx_char;
84	int tx_bit;
85	unsigned char mode;
86
87	unsigned char rx_char;
88	unsigned char rx_clear_scsr;
89	unsigned char clk_pin;
90
91	/* SPI clock rate (twice the real clock). */
92	unsigned int clock;
93
94	/* Periodic SPI event. */
95	struct hw_event* spi_event;
96	};
97
98
99
100	/* Finish off the partially created hw device. Attach our local
101	callbacks. Wire up our port names etc */
102
103	static hw_io_read_buffer_method m68hc11spi_io_read_buffer;
104	static hw_io_write_buffer_method m68hc11spi_io_write_buffer;
105	static hw_port_event_method m68hc11spi_port_event;
106	static hw_ioctl_method m68hc11spi_ioctl;
107
108	#define M6811_SPI_FIRST_REG (M6811_SPCR)
109	#define M6811_SPI_LAST_REG (M6811_SPDR)
110
111
112	static void
113	attach_m68hc11spi_regs (struct hw *me,
114	struct m68hc11spi *controller)
115	{
63348d04	116	hw_attach_address (hw_parent (me), M6811_IO_LEVEL, io_map,
e0709f50 AC	117	M6811_SPI_FIRST_REG,
	118	M6811_SPI_LAST_REG - M6811_SPI_FIRST_REG + 1,
	119	me);
	120	}
	121
	122	static void
	123	m68hc11spi_finish (struct hw *me)
	124	{
	125	struct m68hc11spi *controller;
	126
	127	controller = HW_ZALLOC (me, struct m68hc11spi);
e0709f50 AC	128	set_hw_data (me, controller);
	129	set_hw_io_read_buffer (me, m68hc11spi_io_read_buffer);
	130	set_hw_io_write_buffer (me, m68hc11spi_io_write_buffer);
	131	set_hw_ports (me, m68hc11spi_ports);
	132	set_hw_port_event (me, m68hc11spi_port_event);
	133	#ifdef set_hw_ioctl
	134	set_hw_ioctl (me, m68hc11spi_ioctl);
	135	#else
	136	me->to_ioctl = m68hc11spi_ioctl;
	137	#endif
	138
	139	/* Attach ourself to our parent bus. */
	140	attach_m68hc11spi_regs (me, controller);
	141
	142	/* Initialize to reset state. */
	143	controller->spi_event = NULL;
	144	controller->rx_clear_scsr = 0;
	145	}
	146
	147
	148
	149	/* An event arrives on an interrupt port */
	150
	151	static void
	152	m68hc11spi_port_event (struct hw *me,
	153	int my_port,
	154	struct hw *source,
	155	int source_port,
	156	int level)
	157	{
	158	SIM_DESC sd;
	159	struct m68hc11spi *controller;
	160	sim_cpu* cpu;
	161	unsigned8 val;
	162
	163	controller = hw_data (me);
	164	sd = hw_system (me);
	165	cpu = STATE_CPU (sd, 0);
	166	switch (my_port)
	167	{
	168	case RESET_PORT:
	169	{
	170	HW_TRACE ((me, "SPI reset"));
	171
	172	/* Reset the state of SPI registers. */
	173	controller->rx_clear_scsr = 0;
	174	if (controller->spi_event)
	175	{
	176	hw_event_queue_deschedule (me, controller->spi_event);
	177	controller->spi_event = 0;
	178	}
	179
	180	val = 0;
	181	m68hc11spi_io_write_buffer (me, &val, io_map,
	182	(unsigned_word) M6811_SPCR, 1);
	183	break;
	184	}
	185
	186	default:
	187	hw_abort (me, "Event on unknown port %d", my_port);
	188	break;
	189	}
	190	}
	191
192	static void
193	set_bit_port (struct hw me, sim_cpu cpu, int port, int mask, int value)
194	{
195	/* TODO: Post an event to inform other devices that pin 'port' changes.
196	This has only a sense if we provide some device that is logically
197	connected to these pin ports (SCLK and MOSI) and that handles
198	the SPI protocol. */
199	if (value)
200	cpu->ios[port] \|= mask;
201	else
202	cpu->ios[port] &= ~mask;
203	}
204
205
206	/* When a character is sent/received by the SPI, the PD2..PD5 line
207	are driven by the following signals:
208
209	B7 B6
210	-----+---------+--------+---/-+-------
211	MOSI \| \| \| \| \| \|
212	MISO +---------+--------+---/-+
213	____ ___
214	CLK _______/ \____/ \__ CPOL=0, CPHA=0
215	_______ ____ __
216	\____/ \___/ CPOL=1, CPHA=0
217	____ ____ __
218	__/ \____/ \___/ CPOL=0, CPHA=1
219	__ ____ ___
220	\____/ \____/ \__ CPOL=1, CPHA=1
221
222	SS ___ ____
223	\__________________________//___/
224
225	MISO = PD2
226	MOSI = PD3
227	SCK = PD4
228	SS = PD5
229
230	*/
231
4d72d17a SC	232	#define SPI_START_BYTE 0
	233	#define SPI_START_BIT 1
	234	#define SPI_MIDDLE_BIT 2
e0709f50 AC	235
	236	void
	237	m68hc11spi_clock (struct hw me, void data)
	238	{
	239	SIM_DESC sd;
	240	struct m68hc11spi* controller;
	241	sim_cpu *cpu;
	242	int check_interrupt = 0;
	243
	244	controller = hw_data (me);
	245	sd = hw_system (me);
	246	cpu = STATE_CPU (sd, 0);
	247
	248	/* Cleanup current event. */
	249	if (controller->spi_event)
	250	{
	251	hw_event_queue_deschedule (me, controller->spi_event);
	252	controller->spi_event = 0;
	253	}
	254
	255	/* Change a bit of data at each two SPI event. */
	256	if (controller->mode == SPI_START_BIT)
	257	{
	258	/* Reflect the bit value on bit 2 of port D. */
	259	set_bit_port (me, cpu, M6811_PORTD, (1 << 2),
	260	(controller->tx_char & (1 << controller->tx_bit)));
	261	controller->tx_bit--;
	262	controller->mode = SPI_MIDDLE_BIT;
	263	}
4d72d17a	264	else if (controller->mode == SPI_MIDDLE_BIT)
e0709f50 AC	265	{
	266	controller->mode = SPI_START_BIT;
	267	}
	268
4d72d17a SC	269	if (controller->mode == SPI_START_BYTE)
	270	{
	271	/* Start a new SPI transfer. */
e0709f50	272
4d72d17a SC	273	/* TBD: clear SS output. */
	274	controller->mode = SPI_START_BIT;
	275	controller->tx_bit = 7;
	276	set_bit_port (me, cpu, M6811_PORTD, (1 << 4), ~controller->clk_pin);
	277	}
	278	else
	279	{
	280	/* Change the SPI clock at each event on bit 4 of port D. */
	281	controller->clk_pin = ~controller->clk_pin;
	282	set_bit_port (me, cpu, M6811_PORTD, (1 << 4), controller->clk_pin);
	283	}
	284
e0709f50 AC	285	/* Transmit is now complete for this byte. */
	286	if (controller->mode == SPI_START_BIT && controller->tx_bit < 0)
	287	{
	288	controller->rx_clear_scsr = 0;
	289	cpu->ios[M6811_SPSR] \|= M6811_SPIF;
	290	if (cpu->ios[M6811_SPCR] & M6811_SPIE)
	291	check_interrupt = 1;
	292	}
	293	else
	294	{
	295	controller->spi_event = hw_event_queue_schedule (me, controller->clock,
	296	m68hc11spi_clock,
	297	NULL);
	298	}
	299
	300	if (check_interrupt)
	301	interrupts_update_pending (&cpu->cpu_interrupts);
	302	}
	303
	304	/* Flags of the SPCR register. */
	305	io_reg_desc spcr_desc[] = {
	306	{ M6811_SPIE, "SPIE ", "Serial Peripheral Interrupt Enable" },
	307	{ M6811_SPE, "SPE ", "Serial Peripheral System Enable" },
	308	{ M6811_DWOM, "DWOM ", "Port D Wire-OR mode option" },
	309	{ M6811_MSTR, "MSTR ", "Master Mode Select" },
	310	{ M6811_CPOL, "CPOL ", "Clock Polarity" },
	311	{ M6811_CPHA, "CPHA ", "Clock Phase" },
	312	{ M6811_SPR1, "SPR1 ", "SPI Clock Rate Select" },
	313	{ M6811_SPR0, "SPR0 ", "SPI Clock Rate Select" },
	314	{ 0, 0, 0 }
	315	};
	316
	317
	318	/* Flags of the SPSR register. */
	319	io_reg_desc spsr_desc[] = {
	320	{ M6811_SPIF, "SPIF ", "SPI Transfer Complete flag" },
	321	{ M6811_WCOL, "WCOL ", "Write Collision" },
	322	{ M6811_MODF, "MODF ", "Mode Fault" },
	323	{ 0, 0, 0 }
	324	};
	325
	326	static void
	327	m68hc11spi_info (struct hw *me)
	328	{
	329	SIM_DESC sd;
	330	uint16 base = 0;
	331	sim_cpu *cpu;
	332	struct m68hc11spi *controller;
	333	uint8 val;
	334
	335	sd = hw_system (me);
	336	cpu = STATE_CPU (sd, 0);
	337	controller = hw_data (me);
	338
	339	sim_io_printf (sd, "M68HC11 SPI:\n");
	340
	341	base = cpu_get_io_base (cpu);
	342
	343	val = cpu->ios[M6811_SPCR];
	344	print_io_byte (sd, "SPCR", spcr_desc, val, base + M6811_SPCR);
	345	sim_io_printf (sd, "\n");
	346
	347	val = cpu->ios[M6811_SPSR];
	348	print_io_byte (sd, "SPSR", spsr_desc, val, base + M6811_SPSR);
349	sim_io_printf (sd, "\n");
350
351	if (controller->spi_event)
352	{
353	signed64 t;
354
4d72d17a SC	355	sim_io_printf (sd, " SPI has %d bits to send\n",
4d72d17a SC	356	controller->tx_bit + 1);
e0709f50 AC	357	t = hw_event_remain_time (me, controller->spi_event);
	358	sim_io_printf (sd, " SPI operation finished in %ld cycles\n",
	359	(long) t);
	360	}
	361	}
	362
	363	static int
	364	m68hc11spi_ioctl (struct hw *me,
	365	hw_ioctl_request request,
	366	va_list ap)
	367	{
	368	m68hc11spi_info (me);
	369	return 0;
	370	}
	371
	372	/* generic read/write */
	373
	374	static unsigned
	375	m68hc11spi_io_read_buffer (struct hw *me,
	376	void *dest,
	377	int space,
	378	unsigned_word base,
	379	unsigned nr_bytes)
	380	{
	381	SIM_DESC sd;
	382	struct m68hc11spi *controller;
	383	sim_cpu *cpu;
	384	unsigned8 val;
	385
	386	HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes));
	387
	388	sd = hw_system (me);
	389	cpu = STATE_CPU (sd, 0);
	390	controller = hw_data (me);
	391
	392	switch (base)
	393	{
	394	case M6811_SPSR:
	395	controller->rx_clear_scsr = cpu->ios[M6811_SCSR]
	396	& (M6811_SPIF \| M6811_WCOL \| M6811_MODF);
	397
	398	case M6811_SPCR:
	399	val = cpu->ios[base];
	400	break;
	401
	402	case M6811_SPDR:
	403	if (controller->rx_clear_scsr)
	404	{
	405	cpu->ios[M6811_SPSR] &= ~controller->rx_clear_scsr;
	406	controller->rx_clear_scsr = 0;
4d72d17a	407	interrupts_update_pending (&cpu->cpu_interrupts);
e0709f50 AC	408	}
	409	val = controller->rx_char;
	410	break;
	411
	412	default:
	413	return 0;
	414	}
	415	((unsigned8) dest) = val;
	416	return 1;
	417	}
	418
	419	static unsigned
	420	m68hc11spi_io_write_buffer (struct hw *me,
	421	const void *source,
	422	int space,
	423	unsigned_word base,
	424	unsigned nr_bytes)
	425	{
	426	SIM_DESC sd;
	427	struct m68hc11spi *controller;
	428	sim_cpu *cpu;
	429	unsigned8 val;
	430
	431	HW_TRACE ((me, "write 0x%08lx %d", (long) base, (int) nr_bytes));
	432
	433	sd = hw_system (me);
	434	cpu = STATE_CPU (sd, 0);
	435	controller = hw_data (me);
	436
	437	val = ((const unsigned8) source);
	438	switch (base)
	439	{
	440	case M6811_SPCR:
	441	cpu->ios[M6811_SPCR] = val;
	442
	443	/* The SPI clock rate is 2, 4, 16, 32 of the internal CPU clock.
	444	We have to drive the clock pin and need a 2x faster clock. */
	445	switch (val & (M6811_SPR1 \| M6811_SPR0))
	446	{
	447	case 0:
	448	controller->clock = 1;
	449	break;
	450
	451	case 1:
	452	controller->clock = 2;
	453	break;
	454
	455	case 2:
	456	controller->clock = 8;
	457	break;
	458
	459	default:
	460	controller->clock = 16;
	461	break;
	462	}
	463
	464	/* Set the clock pin. */
	465	if ((val & M6811_CPOL)
	466	&& (controller->spi_event == 0
	467	\|\| ((val & M6811_CPHA) && controller->mode == 1)))
	468	controller->clk_pin = 1;
	469	else
	470	controller->clk_pin = 0;
	471
472	set_bit_port (me, cpu, M6811_PORTD, (1 << 4), controller->clk_pin);
473	break;
474
475	/* Can't write to SPSR. */
476	case M6811_SPSR:
477	break;
478
479	case M6811_SPDR:
480	if (!(cpu->ios[M6811_SPCR] & M6811_SPE))
481	{
482	return 0;
483	}
484
4d72d17a SC	485	if (controller->rx_clear_scsr)
	486	{
	487	cpu->ios[M6811_SPSR] &= ~controller->rx_clear_scsr;
	488	controller->rx_clear_scsr = 0;
	489	interrupts_update_pending (&cpu->cpu_interrupts);
	490	}
	491
e0709f50 AC	492	/* If transfer is taking place, a write to SPDR
	493	generates a collision. */
	494	if (controller->spi_event)
	495	{
	496	cpu->ios[M6811_SPSR] \|= M6811_WCOL;
	497	break;
	498	}
	499
	500	/* Refuse the write if there was no read of SPSR. */
	501	/* ???? TBD. */
	502
	503	/* Prepare to send a byte. */
	504	controller->tx_char = val;
4d72d17a	505	controller->mode = SPI_START_BYTE;
e0709f50 AC	506
	507	/* Toggle clock pin internal value when CPHA is 0 so that
	508	it will really change in the middle of a bit. */
	509	if (!(cpu->ios[M6811_SPCR] & M6811_CPHA))
	510	controller->clk_pin = ~controller->clk_pin;
	511
	512	cpu->ios[M6811_SPDR] = val;
	513
	514	/* Activate transmission. */
	515	m68hc11spi_clock (me, NULL);
	516	break;
	517
	518	default:
	519	return 0;
	520	}
	521	return nr_bytes;
	522	}
	523
	524
	525	const struct hw_descriptor dv_m68hc11spi_descriptor[] = {
	526	{ "m68hc11spi", m68hc11spi_finish, },
	527	{ NULL },
	528	};
	529