[deliverable/binutils-gdb.git] / sim / m68hc11 / sim-main.h

/* sim-main.h -- Simulator for Motorola 68HC11 & 68HC12
   Copyright (C) 1999, 2000, 2001, 2002, 2003, 2007, 2008, 2009
   Free Software Foundation, Inc.
   Written by Stephane Carrez (stcarrez@nerim.fr)

This file is part of GDB, the GNU debugger.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

#ifndef _SIM_MAIN_H
#define _SIM_MAIN_H

#define WITH_MODULO_MEMORY 1
#define WITH_WATCHPOINTS 1
#define SIM_HANDLES_LMA 1

#include "sim-basics.h"

typedef address_word sim_cia;

#include "sim-signal.h"
#include "sim-base.h"

#include "bfd.h"

#include "opcode/m68hc11.h"

#include "gdb/callback.h"
#include "gdb/remote-sim.h"
#include "opcode/m68hc11.h"
#include "sim-types.h"

typedef unsigned8 uint8;
typedef unsigned16 uint16;
typedef signed16 int16;
typedef unsigned32 uint32;
typedef signed32 int32;
typedef unsigned64 uint64;
typedef signed64 int64;

struct _sim_cpu;

#include "interrupts.h"
#include <setjmp.h>

/* Specifies the level of mapping for the IO, EEprom, nvram and external
   RAM.  IO registers are mapped over everything and the external RAM
   is last (ie, it can be hidden by everything above it in the list).  */
enum m68hc11_map_level
{
  M6811_IO_LEVEL,
  M6811_EEPROM_LEVEL,
  M6811_NVRAM_LEVEL,
  M6811_RAM_LEVEL
};

enum cpu_type
{
  CPU_M6811,
  CPU_M6812
};

#define X_REGNUM 	0
#define D_REGNUM	1
#define Y_REGNUM        2
#define SP_REGNUM 	3
#define PC_REGNUM 	4
#define A_REGNUM        5
#define B_REGNUM        6
#define PSW_REGNUM 	7
#define PAGE_REGNUM     8
#define Z_REGNUM        9

typedef struct m6811_regs {
    unsigned short      d;
    unsigned short      ix;
    unsigned short      iy;
    unsigned short      sp;
    unsigned short      pc;
    unsigned char       ccr;
  unsigned short      page;
} m6811_regs;


/* Description of 68HC11 IO registers.  Such description is only provided
   for the info command to display the current setting of IO registers
   from GDB.  */
struct io_reg_desc
{
  int        mask;
  const char *short_name;
  const char *long_name;
};
typedef struct io_reg_desc io_reg_desc;

extern void print_io_reg_desc (SIM_DESC sd, io_reg_desc *desc, int val,
			       int mode);
extern void print_io_byte (SIM_DESC sd, const char *name,
			   io_reg_desc *desc, uint8 val, uint16 addr);
extern void print_io_word (SIM_DESC sd, const char *name,
			   io_reg_desc *desc, uint16 val, uint16 addr);


/* List of special 68HC11&68HC12 instructions that are not handled by the
   'gencode.c' generator.  These complex instructions are implemented
   by 'cpu_special'.  */
enum M6811_Special
{
  /* 68HC11 instructions.  */
  M6811_DAA,
  M6811_EMUL_SYSCALL,
  M6811_ILLEGAL,
  M6811_RTI,
  M6811_STOP,
  M6811_SWI,
  M6811_TEST,
  M6811_WAI,

  /* 68HC12 instructions.  */
  M6812_BGND,
  M6812_CALL,
  M6812_CALL_INDIRECT,
  M6812_IDIVS,
  M6812_EDIV,
  M6812_EDIVS,
  M6812_EMACS,
  M6812_EMUL,
  M6812_EMULS,
  M6812_ETBL,
  M6812_MEM,
  M6812_REV,
  M6812_REVW,
  M6812_RTC,
  M6812_RTI,
  M6812_WAV
};

#define M6811_MAX_PORTS (0x03f+1)
#define M6812_MAX_PORTS (0x3ff+1)
#define MAX_PORTS       (M6812_MAX_PORTS)

struct _sim_cpu;

typedef void (* cpu_interp) (struct _sim_cpu*);

struct _sim_cpu {
  /* CPU registers.  */
  struct m6811_regs     cpu_regs;

  /* CPU interrupts.  */
  struct interrupts     cpu_interrupts;

  /* Pointer to the interpretor routine.  */
  cpu_interp            cpu_interpretor;

  /* Pointer to the architecture currently configured in the simulator.  */
  const struct bfd_arch_info  *cpu_configured_arch;
  
  /* CPU absolute cycle time.  The cycle time is updated after
     each instruction, by the number of cycles taken by the instruction.
     It is cleared only when reset occurs.  */
  signed64              cpu_absolute_cycle;

  /* Number of cycles to increment after the current instruction.
     This is also the number of ticks for the generic event scheduler.  */
  uint8                 cpu_current_cycle;
  int                   cpu_emul_syscall;
  int                   cpu_is_initialized;
  int                   cpu_running;
  int                   cpu_check_memory;
  int                   cpu_stop_on_interrupt;

  /* When this is set, start execution of program at address specified
     in the ELF header.  This is used for testing some programs that do not
     have an interrupt table linked with them.  Programs created during the
     GCC validation are like this. A normal 68HC11 does not behave like
     this (unless there is some OS or downloadable feature).  */
  int                   cpu_use_elf_start;

  /* The starting address specified in ELF header.  */
  int                   cpu_elf_start;
  
  uint16                cpu_insn_pc;

  /* CPU frequency.  This is the quartz frequency.  It is divided by 4 to
     get the cycle time.  This is used for the timer rate and for the baud
     rate generation.  */
  unsigned long         cpu_frequency;

  /* The mode in which the CPU is configured (MODA and MODB pins).  */
  unsigned int          cpu_mode;
  const char*           cpu_start_mode;

  /* The cpu being configured.  */
  enum cpu_type         cpu_type;
  
  /* Initial value of the CONFIG register.  */
  uint8                 cpu_config;
  uint8                 cpu_use_local_config;
  
  uint8                 ios[MAX_PORTS];

  /* Memory bank parameters which describe how the memory bank window
     is mapped in memory and how to convert it in virtual address.  */
  uint16                bank_start;
  uint16                bank_end;
  address_word          bank_virtual;
  unsigned              bank_shift;
  

  struct hw            *hw_cpu;

  /* ... base type ... */
  sim_cpu_base base;
};

/* Returns the cpu absolute cycle time (A virtual counter incremented
   at each 68HC11 E clock).  */
#define cpu_current_cycle(PROC) ((PROC)->cpu_absolute_cycle)
#define cpu_add_cycles(PROC,T)  ((PROC)->cpu_current_cycle += (signed64) (T))
#define cpu_is_running(PROC)    ((PROC)->cpu_running)

/* Get the IO/RAM base addresses depending on the M6811_INIT register.  */
#define cpu_get_io_base(PROC) \
        (((uint16)(((PROC)->ios[M6811_INIT]) & 0x0F))<<12)
#define cpu_get_reg_base(PROC) \
        (((uint16)(((PROC)->ios[M6811_INIT]) & 0xF0))<<8)

/* Returns the different CPU registers.  */
#define cpu_get_ccr(PROC)          ((PROC)->cpu_regs.ccr)
#define cpu_get_pc(PROC)           ((PROC)->cpu_regs.pc)
#define cpu_get_d(PROC)            ((PROC)->cpu_regs.d)
#define cpu_get_x(PROC)            ((PROC)->cpu_regs.ix)
#define cpu_get_y(PROC)            ((PROC)->cpu_regs.iy)
#define cpu_get_sp(PROC)           ((PROC)->cpu_regs.sp)
#define cpu_get_a(PROC)            ((PROC->cpu_regs.d >> 8) & 0x0FF)
#define cpu_get_b(PROC)            ((PROC->cpu_regs.d) & 0x0FF)
#define cpu_get_page(PROC)         ((PROC)->cpu_regs.page)

/* 68HC12 specific and Motorola internal registers.  */
#define cpu_get_tmp3(PROC)         (0)
#define cpu_get_tmp2(PROC)         (0)

#define cpu_set_d(PROC,VAL)        (((PROC)->cpu_regs.d) = (VAL))
#define cpu_set_x(PROC,VAL)        (((PROC)->cpu_regs.ix) = (VAL))
#define cpu_set_y(PROC,VAL)        (((PROC)->cpu_regs.iy) = (VAL))
#define cpu_set_page(PROC,VAL)     (((PROC)->cpu_regs.page) = (VAL))

/* 68HC12 specific and Motorola internal registers.  */
#define cpu_set_tmp3(PROC,VAL)     (0)
#define cpu_set_tmp2(PROC,VAL)     (void) (0)

#if 0
/* This is a function in m68hc11_sim.c to keep track of the frame.  */
#define cpu_set_sp(PROC,VAL)       (((PROC)->cpu_regs.sp) = (VAL))
#endif

#define cpu_set_pc(PROC,VAL)       (((PROC)->cpu_regs.pc) = (VAL))

#define cpu_set_a(PROC,VAL)  \
      cpu_set_d(PROC,((VAL) << 8) | cpu_get_b(PROC))
#define cpu_set_b(PROC,VAL)  \
      cpu_set_d(PROC,((cpu_get_a(PROC)) << 8)|(VAL & 0x0FF))

#define cpu_set_ccr(PROC,VAL)      ((PROC)->cpu_regs.ccr = (VAL))
#define cpu_get_ccr_H(PROC)        ((cpu_get_ccr(PROC) & M6811_H_BIT) ? 1: 0)
#define cpu_get_ccr_X(PROC)        ((cpu_get_ccr(PROC) & M6811_X_BIT) ? 1: 0)
#define cpu_get_ccr_S(PROC)        ((cpu_get_ccr(PROC) & M6811_S_BIT) ? 1: 0)
#define cpu_get_ccr_N(PROC)        ((cpu_get_ccr(PROC) & M6811_N_BIT) ? 1: 0)
#define cpu_get_ccr_V(PROC)        ((cpu_get_ccr(PROC) & M6811_V_BIT) ? 1: 0)
#define cpu_get_ccr_C(PROC)        ((cpu_get_ccr(PROC) & M6811_C_BIT) ? 1: 0)
#define cpu_get_ccr_Z(PROC)        ((cpu_get_ccr(PROC) & M6811_Z_BIT) ? 1: 0)
#define cpu_get_ccr_I(PROC)        ((cpu_get_ccr(PROC) & M6811_I_BIT) ? 1: 0)

#define cpu_set_ccr_flag(S,B,V) \
cpu_set_ccr(S,(cpu_get_ccr(S) & ~(B)) | ((V) ? B : 0))

#define cpu_set_ccr_H(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_H_BIT, VAL)
#define cpu_set_ccr_X(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_X_BIT, VAL)
#define cpu_set_ccr_S(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_S_BIT, VAL)
#define cpu_set_ccr_N(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_N_BIT, VAL)
#define cpu_set_ccr_V(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_V_BIT, VAL)
#define cpu_set_ccr_C(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_C_BIT, VAL)
#define cpu_set_ccr_Z(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_Z_BIT, VAL)
#define cpu_set_ccr_I(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_I_BIT, VAL)

#undef inline
#define inline static __inline__

extern void cpu_memory_exception (struct _sim_cpu *proc,
                                  SIM_SIGNAL excep,
                                  uint16 addr,
                                  const char *message);

inline address_word
phys_to_virt (sim_cpu *cpu, address_word addr)
{
  if (addr >= cpu->bank_start && addr < cpu->bank_end)
    return ((address_word) (addr - cpu->bank_start)
            + (((address_word) cpu->cpu_regs.page) << cpu->bank_shift)
            + cpu->bank_virtual);
  else
    return (address_word) (addr);
}

inline uint8
memory_read8 (sim_cpu *cpu, uint16 addr)
{
  uint8 val;

  if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1)
    {
      cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
                            "Read error");
    }
  return val;
}

inline void
memory_write8 (sim_cpu *cpu, uint16 addr, uint8 val)
{
  if (sim_core_write_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1)
    {
      cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
                            "Write error");
    }
}

inline uint16
memory_read16 (sim_cpu *cpu, uint16 addr)
{
  uint8 b[2];

  if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, b, addr, 2) != 2)
    {
      cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
                            "Read error");
    }
  return (((uint16) (b[0])) << 8) | ((uint16) b[1]);
}

inline void
memory_write16 (sim_cpu *cpu, uint16 addr, uint16 val)
{
  uint8 b[2];

  b[0] = val >> 8;
  b[1] = val;
  if (sim_core_write_buffer (CPU_STATE (cpu), cpu, 0, b, addr, 2) != 2)
    {
      cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
                            "Write error");
    }
}
extern void
cpu_ccr_update_tst8 (sim_cpu *proc, uint8 val);

     inline void
cpu_ccr_update_tst16 (sim_cpu *proc, uint16 val)
{
  cpu_set_ccr_V (proc, 0);
  cpu_set_ccr_N (proc, val & 0x8000 ? 1 : 0);
  cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
}

     inline void
cpu_ccr_update_shift8 (sim_cpu *proc, uint8 val)
{
  cpu_set_ccr_N (proc, val & 0x80 ? 1 : 0);
  cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
  cpu_set_ccr_V (proc, cpu_get_ccr_N (proc) ^ cpu_get_ccr_C (proc));
}

     inline void
cpu_ccr_update_shift16 (sim_cpu *proc, uint16 val)
{
  cpu_set_ccr_N (proc, val & 0x8000 ? 1 : 0);
  cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
  cpu_set_ccr_V (proc, cpu_get_ccr_N (proc) ^ cpu_get_ccr_C (proc));
}

inline void
cpu_ccr_update_add8 (sim_cpu *proc, uint8 r, uint8 a, uint8 b)
{
  cpu_set_ccr_C (proc, ((a & b) | (b & ~r) | (a & ~r)) & 0x80 ? 1 : 0);
  cpu_set_ccr_V (proc, ((a & b & ~r) | (~a & ~b & r)) & 0x80 ? 1 : 0);
  cpu_set_ccr_Z (proc, r == 0);
  cpu_set_ccr_N (proc, r & 0x80 ? 1 : 0);
}


inline void
cpu_ccr_update_sub8 (sim_cpu *proc, uint8 r, uint8 a, uint8 b)
{
  cpu_set_ccr_C (proc, ((~a & b) | (b & r) | (~a & r)) & 0x80 ? 1 : 0);
  cpu_set_ccr_V (proc, ((a & ~b & ~r) | (~a & b & r)) & 0x80 ? 1 : 0);
  cpu_set_ccr_Z (proc, r == 0);
  cpu_set_ccr_N (proc, r & 0x80 ? 1 : 0);
}

inline void
cpu_ccr_update_add16 (sim_cpu *proc, uint16 r, uint16 a, uint16 b)
{
  cpu_set_ccr_C (proc, ((a & b) | (b & ~r) | (a & ~r)) & 0x8000 ? 1 : 0);
  cpu_set_ccr_V (proc, ((a & b & ~r) | (~a & ~b & r)) & 0x8000 ? 1 : 0);
  cpu_set_ccr_Z (proc, r == 0);
  cpu_set_ccr_N (proc, r & 0x8000 ? 1 : 0);
}

inline void
cpu_ccr_update_sub16 (sim_cpu *proc, uint16 r, uint16 a, uint16 b)
{
  cpu_set_ccr_C (proc, ((~a & b) | (b & r) | (~a & r)) & 0x8000 ? 1 : 0);
  cpu_set_ccr_V (proc, ((a & ~b & ~r) | (~a & b & r)) & 0x8000 ? 1 : 0);
  cpu_set_ccr_Z (proc, r == 0);
  cpu_set_ccr_N (proc, r & 0x8000 ? 1 : 0);
}

/* Push and pop instructions for 68HC11 (next-available stack mode).  */
inline void
cpu_m68hc11_push_uint8 (sim_cpu *proc, uint8 val)
{
  uint16 addr = proc->cpu_regs.sp;

  memory_write8 (proc, addr, val);
  proc->cpu_regs.sp = addr - 1;
}

inline void
cpu_m68hc11_push_uint16 (sim_cpu *proc, uint16 val)
{
  uint16 addr = proc->cpu_regs.sp - 1;

  memory_write16 (proc, addr, val);
  proc->cpu_regs.sp = addr - 1;
}

inline uint8
cpu_m68hc11_pop_uint8 (sim_cpu *proc)
{
  uint16 addr = proc->cpu_regs.sp;
  uint8 val;
  
  val = memory_read8 (proc, addr + 1);
  proc->cpu_regs.sp = addr + 1;
  return val;
}

inline uint16
cpu_m68hc11_pop_uint16 (sim_cpu *proc)
{
  uint16 addr = proc->cpu_regs.sp;
  uint16 val;
  
  val = memory_read16 (proc, addr + 1);
  proc->cpu_regs.sp = addr + 2;
  return val;
}

/* Push and pop instructions for 68HC12 (last-used stack mode).  */
inline void
cpu_m68hc12_push_uint8 (sim_cpu *proc, uint8 val)
{
  uint16 addr = proc->cpu_regs.sp;

  addr --;
  memory_write8 (proc, addr, val);
  proc->cpu_regs.sp = addr;
}

inline void
cpu_m68hc12_push_uint16 (sim_cpu *proc, uint16 val)
{
  uint16 addr = proc->cpu_regs.sp;

  addr -= 2;
  memory_write16 (proc, addr, val);
  proc->cpu_regs.sp = addr;
}

inline uint8
cpu_m68hc12_pop_uint8 (sim_cpu *proc)
{
  uint16 addr = proc->cpu_regs.sp;
  uint8 val;
  
  val = memory_read8 (proc, addr);
  proc->cpu_regs.sp = addr + 1;
  return val;
}

inline uint16
cpu_m68hc12_pop_uint16 (sim_cpu *proc)
{
  uint16 addr = proc->cpu_regs.sp;
  uint16 val;
  
  val = memory_read16 (proc, addr);
  proc->cpu_regs.sp = addr + 2;
  return val;
}

/* Fetch a 8/16 bit value and update the PC.  */
inline uint8
cpu_fetch8 (sim_cpu *proc)
{
  uint16 addr = proc->cpu_regs.pc;
  uint8 val;
  
  val = memory_read8 (proc, addr);
  proc->cpu_regs.pc = addr + 1;
  return val;
}

inline uint16
cpu_fetch16 (sim_cpu *proc)
{
  uint16 addr = proc->cpu_regs.pc;
  uint16 val;
  
  val = memory_read16 (proc, addr);
  proc->cpu_regs.pc = addr + 2;
  return val;
}

extern void cpu_call (sim_cpu* proc, uint16 addr);
extern void cpu_exg (sim_cpu* proc, uint8 code);
extern void cpu_dbcc (sim_cpu* proc);
extern void cpu_special (sim_cpu *proc, enum M6811_Special special);
extern void cpu_move8 (sim_cpu *proc, uint8 op);
extern void cpu_move16 (sim_cpu *proc, uint8 op);

extern uint16 cpu_fetch_relbranch (sim_cpu *proc);
extern uint16 cpu_fetch_relbranch16 (sim_cpu *proc);
extern void cpu_push_all (sim_cpu *proc);
extern void cpu_single_step (sim_cpu *proc);

extern void cpu_info (SIM_DESC sd, sim_cpu *proc);

extern int cpu_initialize (SIM_DESC sd, sim_cpu *cpu);

/* Returns the address of a 68HC12 indexed operand.
   Pre and post modifications are handled on the source register.  */
extern uint16 cpu_get_indexed_operand_addr (sim_cpu* cpu, int restrict);

extern void cpu_return (sim_cpu *cpu);
extern void cpu_set_sp (sim_cpu *cpu, uint16 val);
extern int cpu_reset (sim_cpu *cpu);
extern int cpu_restart (sim_cpu *cpu);
extern void sim_memory_error (sim_cpu *cpu, SIM_SIGNAL excep,
                              uint16 addr, const char *message, ...);
extern void emul_os (int op, sim_cpu *cpu);
extern void cpu_interp_m6811 (sim_cpu *cpu);
extern void cpu_interp_m6812 (sim_cpu *cpu);

extern int m68hc11cpu_set_oscillator (SIM_DESC sd, const char *port,
				      double ton, double toff,
				      signed64 repeat);
extern int m68hc11cpu_clear_oscillator (SIM_DESC sd, const char *port);
extern void m68hc11cpu_set_port (struct hw *me, sim_cpu *cpu,
				 unsigned addr, uint8 val);

/* The current state of the processor; registers, memory, etc.  */

#define CIA_GET(CPU)      (cpu_get_pc (CPU))
#define CIA_SET(CPU,VAL)  (cpu_set_pc ((CPU), (VAL)))

#if (WITH_SMP)
#define STATE_CPU(sd,n) (&(sd)->cpu[n])
#else
#define STATE_CPU(sd,n) (&(sd)->cpu[0])
#endif

struct sim_state {
  sim_cpu        cpu[MAX_NR_PROCESSORS];
  device         *devices;
  sim_state_base base;
};

extern void sim_set_profile (int n);
extern void sim_set_profile_size (int n);
extern void sim_board_reset (SIM_DESC sd);

#define PRINT_TIME  0x01
#define PRINT_CYCLE 0x02
extern const char *cycle_to_string (sim_cpu *cpu, signed64 t, int flags);

#endif
Commit	Line	Data
81e09ed8	1	/* sim-main.h -- Simulator for Motorola 68HC11 & 68HC12
e4d013fc	2	Copyright (C) 1999, 2000, 2001, 2002, 2003, 2007, 2008, 2009
6aba47ca	3	Free Software Foundation, Inc.
63f36def	4	Written by Stephane Carrez (stcarrez@nerim.fr)
e0709f50 AC	5
	6	This file is part of GDB, the GNU debugger.
	7
	8	This program is free software; you can redistribute it and/or modify
	9	it under the terms of the GNU General Public License as published by
4744ac1b JB	10	the Free Software Foundation; either version 3 of the License, or
4744ac1b JB	11	(at your option) any later version.
e0709f50 AC	12
	13	This program is distributed in the hope that it will be useful,
	14	but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	GNU General Public License for more details.
	17
4744ac1b JB	18	You should have received a copy of the GNU General Public License
4744ac1b JB	19	along with this program. If not, see <http://www.gnu.org/licenses/>. */
e0709f50 AC	20
	21	#ifndef _SIM_MAIN_H
	22	#define _SIM_MAIN_H
	23
	24	#define WITH_MODULO_MEMORY 1
	25	#define WITH_WATCHPOINTS 1
	26	#define SIM_HANDLES_LMA 1
	27
	28	#include "sim-basics.h"
	29
	30	typedef address_word sim_cia;
	31
	32	#include "sim-signal.h"
	33	#include "sim-base.h"
	34
	35	#include "bfd.h"
	36
	37	#include "opcode/m68hc11.h"
	38
3c25f8c7 AC	39	#include "gdb/callback.h"
3c25f8c7 AC	40	#include "gdb/remote-sim.h"
e0709f50 AC	41	#include "opcode/m68hc11.h"
	42	#include "sim-types.h"
	43
	44	typedef unsigned8 uint8;
	45	typedef unsigned16 uint16;
	46	typedef signed16 int16;
	47	typedef unsigned32 uint32;
	48	typedef signed32 int32;
	49	typedef unsigned64 uint64;
	50	typedef signed64 int64;
	51
	52	struct _sim_cpu;
	53
	54	#include "interrupts.h"
	55	#include <setjmp.h>
	56
63348d04 SC	57	/* Specifies the level of mapping for the IO, EEprom, nvram and external
	58	RAM. IO registers are mapped over everything and the external RAM
	59	is last (ie, it can be hidden by everything above it in the list). */
	60	enum m68hc11_map_level
	61	{
	62	M6811_IO_LEVEL,
	63	M6811_EEPROM_LEVEL,
	64	M6811_NVRAM_LEVEL,
	65	M6811_RAM_LEVEL
	66	};
	67
81e09ed8 SC	68	enum cpu_type
	69	{
	70	CPU_M6811,
	71	CPU_M6812
	72	};
63348d04	73
e0709f50 AC	74	#define X_REGNUM 0
	75	#define D_REGNUM 1
	76	#define Y_REGNUM 2
	77	#define SP_REGNUM 3
	78	#define PC_REGNUM 4
	79	#define A_REGNUM 5
	80	#define B_REGNUM 6
	81	#define PSW_REGNUM 7
53b3cd22 SC	82	#define PAGE_REGNUM 8
53b3cd22 SC	83	#define Z_REGNUM 9
e0709f50 AC	84
	85	typedef struct m6811_regs {
	86	unsigned short d;
	87	unsigned short ix;
	88	unsigned short iy;
	89	unsigned short sp;
	90	unsigned short pc;
	91	unsigned char ccr;
63f36def	92	unsigned short page;
e0709f50 AC	93	} m6811_regs;
	94
	95
	96	/* Description of 68HC11 IO registers. Such description is only provided
	97	for the info command to display the current setting of IO registers
	98	from GDB. */
	99	struct io_reg_desc
	100	{
	101	int mask;
	102	const char *short_name;
	103	const char *long_name;
	104	};
	105	typedef struct io_reg_desc io_reg_desc;
	106
	107	extern void print_io_reg_desc (SIM_DESC sd, io_reg_desc *desc, int val,
	108	int mode);
	109	extern void print_io_byte (SIM_DESC sd, const char *name,
	110	io_reg_desc *desc, uint8 val, uint16 addr);
962e9d85 SC	111	extern void print_io_word (SIM_DESC sd, const char *name,
962e9d85 SC	112	io_reg_desc *desc, uint16 val, uint16 addr);
e0709f50 AC	113
e0709f50 AC	114
81e09ed8	115	/* List of special 68HC11&68HC12 instructions that are not handled by the
e0709f50 AC	116	'gencode.c' generator. These complex instructions are implemented
	117	by 'cpu_special'. */
	118	enum M6811_Special
	119	{
81e09ed8 SC	120	/* 68HC11 instructions. */
	121	M6811_DAA,
	122	M6811_EMUL_SYSCALL,
	123	M6811_ILLEGAL,
e0709f50	124	M6811_RTI,
81e09ed8	125	M6811_STOP,
e0709f50 AC	126	M6811_SWI,
e0709f50 AC	127	M6811_TEST,
81e09ed8 SC	128	M6811_WAI,
	129
	130	/* 68HC12 instructions. */
	131	M6812_BGND,
	132	M6812_CALL,
63f36def	133	M6812_CALL_INDIRECT,
81e09ed8 SC	134	M6812_IDIVS,
	135	M6812_EDIV,
	136	M6812_EDIVS,
	137	M6812_EMACS,
	138	M6812_EMUL,
	139	M6812_EMULS,
	140	M6812_ETBL,
	141	M6812_MEM,
	142	M6812_REV,
	143	M6812_REVW,
	144	M6812_RTC,
	145	M6812_RTI,
	146	M6812_WAV
e0709f50 AC	147	};
e0709f50 AC	148
81e09ed8 SC	149	#define M6811_MAX_PORTS (0x03f+1)
	150	#define M6812_MAX_PORTS (0x3ff+1)
	151	#define MAX_PORTS (M6812_MAX_PORTS)
e0709f50	152
81e09ed8 SC	153	struct _sim_cpu;
	154
	155	typedef void (* cpu_interp) (struct _sim_cpu*);
	156
e0709f50 AC	157	struct _sim_cpu {
	158	/* CPU registers. */
	159	struct m6811_regs cpu_regs;
	160
	161	/* CPU interrupts. */
	162	struct interrupts cpu_interrupts;
	163
81e09ed8 SC	164	/* Pointer to the interpretor routine. */
	165	cpu_interp cpu_interpretor;
	166
	167	/* Pointer to the architecture currently configured in the simulator. */
	168	const struct bfd_arch_info *cpu_configured_arch;
	169
e0709f50 AC	170	/* CPU absolute cycle time. The cycle time is updated after
	171	each instruction, by the number of cycles taken by the instruction.
	172	It is cleared only when reset occurs. */
	173	signed64 cpu_absolute_cycle;
	174
	175	/* Number of cycles to increment after the current instruction.
	176	This is also the number of ticks for the generic event scheduler. */
	177	uint8 cpu_current_cycle;
	178	int cpu_emul_syscall;
	179	int cpu_is_initialized;
	180	int cpu_running;
	181	int cpu_check_memory;
	182	int cpu_stop_on_interrupt;
	183
	184	/* When this is set, start execution of program at address specified
	185	in the ELF header. This is used for testing some programs that do not
	186	have an interrupt table linked with them. Programs created during the
	187	GCC validation are like this. A normal 68HC11 does not behave like
	188	this (unless there is some OS or downloadable feature). */
	189	int cpu_use_elf_start;
	190
	191	/* The starting address specified in ELF header. */
	192	int cpu_elf_start;
	193
	194	uint16 cpu_insn_pc;
e0709f50 AC	195
	196	/* CPU frequency. This is the quartz frequency. It is divided by 4 to
	197	get the cycle time. This is used for the timer rate and for the baud
	198	rate generation. */
	199	unsigned long cpu_frequency;
	200
	201	/* The mode in which the CPU is configured (MODA and MODB pins). */
	202	unsigned int cpu_mode;
a685700c	203	const char* cpu_start_mode;
e0709f50	204
81e09ed8 SC	205	/* The cpu being configured. */
	206	enum cpu_type cpu_type;
	207
e0709f50 AC	208	/* Initial value of the CONFIG register. */
	209	uint8 cpu_config;
	210	uint8 cpu_use_local_config;
	211
81e09ed8	212	uint8 ios[MAX_PORTS];
827ec39a	213
77342e5e SC	214	/* Memory bank parameters which describe how the memory bank window
	215	is mapped in memory and how to convert it in virtual address. */
	216	uint16 bank_start;
	217	uint16 bank_end;
	218	address_word bank_virtual;
	219	unsigned bank_shift;
	220
	221
827ec39a SC	222	struct hw *hw_cpu;
827ec39a SC	223
e0709f50 AC	224	/* ... base type ... */
	225	sim_cpu_base base;
	226	};
	227
	228	/* Returns the cpu absolute cycle time (A virtual counter incremented
	229	at each 68HC11 E clock). */
	230	#define cpu_current_cycle(PROC) ((PROC)->cpu_absolute_cycle)
	231	#define cpu_add_cycles(PROC,T) ((PROC)->cpu_current_cycle += (signed64) (T))
	232	#define cpu_is_running(PROC) ((PROC)->cpu_running)
	233
	234	/* Get the IO/RAM base addresses depending on the M6811_INIT register. */
	235	#define cpu_get_io_base(PROC) \
	236	(((uint16)(((PROC)->ios[M6811_INIT]) & 0x0F))<<12)
	237	#define cpu_get_reg_base(PROC) \
	238	(((uint16)(((PROC)->ios[M6811_INIT]) & 0xF0))<<8)
	239
	240	/* Returns the different CPU registers. */
	241	#define cpu_get_ccr(PROC) ((PROC)->cpu_regs.ccr)
	242	#define cpu_get_pc(PROC) ((PROC)->cpu_regs.pc)
	243	#define cpu_get_d(PROC) ((PROC)->cpu_regs.d)
	244	#define cpu_get_x(PROC) ((PROC)->cpu_regs.ix)
	245	#define cpu_get_y(PROC) ((PROC)->cpu_regs.iy)
	246	#define cpu_get_sp(PROC) ((PROC)->cpu_regs.sp)
	247	#define cpu_get_a(PROC) ((PROC->cpu_regs.d >> 8) & 0x0FF)
	248	#define cpu_get_b(PROC) ((PROC->cpu_regs.d) & 0x0FF)
77342e5e	249	#define cpu_get_page(PROC) ((PROC)->cpu_regs.page)
e0709f50	250
81e09ed8 SC	251	/* 68HC12 specific and Motorola internal registers. */
	252	#define cpu_get_tmp3(PROC) (0)
	253	#define cpu_get_tmp2(PROC) (0)
	254
e0709f50 AC	255	#define cpu_set_d(PROC,VAL) (((PROC)->cpu_regs.d) = (VAL))
	256	#define cpu_set_x(PROC,VAL) (((PROC)->cpu_regs.ix) = (VAL))
	257	#define cpu_set_y(PROC,VAL) (((PROC)->cpu_regs.iy) = (VAL))
77342e5e	258	#define cpu_set_page(PROC,VAL) (((PROC)->cpu_regs.page) = (VAL))
e0709f50	259
81e09ed8 SC	260	/* 68HC12 specific and Motorola internal registers. */
81e09ed8 SC	261	#define cpu_set_tmp3(PROC,VAL) (0)
63f36def	262	#define cpu_set_tmp2(PROC,VAL) (void) (0)
81e09ed8	263
e0709f50 AC	264	#if 0
	265	/* This is a function in m68hc11_sim.c to keep track of the frame. */
	266	#define cpu_set_sp(PROC,VAL) (((PROC)->cpu_regs.sp) = (VAL))
	267	#endif
	268
	269	#define cpu_set_pc(PROC,VAL) (((PROC)->cpu_regs.pc) = (VAL))
	270
	271	#define cpu_set_a(PROC,VAL) \
	272	cpu_set_d(PROC,((VAL) << 8) \| cpu_get_b(PROC))
	273	#define cpu_set_b(PROC,VAL) \
	274	cpu_set_d(PROC,((cpu_get_a(PROC)) << 8)\|(VAL & 0x0FF))
	275
	276	#define cpu_set_ccr(PROC,VAL) ((PROC)->cpu_regs.ccr = (VAL))
	277	#define cpu_get_ccr_H(PROC) ((cpu_get_ccr(PROC) & M6811_H_BIT) ? 1: 0)
	278	#define cpu_get_ccr_X(PROC) ((cpu_get_ccr(PROC) & M6811_X_BIT) ? 1: 0)
	279	#define cpu_get_ccr_S(PROC) ((cpu_get_ccr(PROC) & M6811_S_BIT) ? 1: 0)
	280	#define cpu_get_ccr_N(PROC) ((cpu_get_ccr(PROC) & M6811_N_BIT) ? 1: 0)
	281	#define cpu_get_ccr_V(PROC) ((cpu_get_ccr(PROC) & M6811_V_BIT) ? 1: 0)
	282	#define cpu_get_ccr_C(PROC) ((cpu_get_ccr(PROC) & M6811_C_BIT) ? 1: 0)
	283	#define cpu_get_ccr_Z(PROC) ((cpu_get_ccr(PROC) & M6811_Z_BIT) ? 1: 0)
	284	#define cpu_get_ccr_I(PROC) ((cpu_get_ccr(PROC) & M6811_I_BIT) ? 1: 0)
	285
	286	#define cpu_set_ccr_flag(S,B,V) \
	287	cpu_set_ccr(S,(cpu_get_ccr(S) & ~(B)) \| ((V) ? B : 0))
	288
	289	#define cpu_set_ccr_H(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_H_BIT, VAL)
	290	#define cpu_set_ccr_X(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_X_BIT, VAL)
	291	#define cpu_set_ccr_S(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_S_BIT, VAL)
	292	#define cpu_set_ccr_N(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_N_BIT, VAL)
	293	#define cpu_set_ccr_V(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_V_BIT, VAL)
	294	#define cpu_set_ccr_C(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_C_BIT, VAL)
	295	#define cpu_set_ccr_Z(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_Z_BIT, VAL)
	296	#define cpu_set_ccr_I(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_I_BIT, VAL)
	297
	298	#undef inline
	299	#define inline static __inline__
	300
	301	extern void cpu_memory_exception (struct _sim_cpu *proc,
	302	SIM_SIGNAL excep,
	303	uint16 addr,
	304	const char *message);
	305
63f36def SC	306	inline address_word
	307	phys_to_virt (sim_cpu *cpu, address_word addr)
	308	{
77342e5e SC	309	if (addr >= cpu->bank_start && addr < cpu->bank_end)
	310	return ((address_word) (addr - cpu->bank_start)
	311	+ (((address_word) cpu->cpu_regs.page) << cpu->bank_shift)
	312	+ cpu->bank_virtual);
63f36def SC	313	else
	314	return (address_word) (addr);
	315	}
	316
e0709f50 AC	317	inline uint8
	318	memory_read8 (sim_cpu *cpu, uint16 addr)
	319	{
	320	uint8 val;
63f36def	321
e0709f50 AC	322	if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1)
	323	{
	324	cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
	325	"Read error");
	326	}
	327	return val;
	328	}
	329
	330	inline void
	331	memory_write8 (sim_cpu *cpu, uint16 addr, uint8 val)
	332	{
	333	if (sim_core_write_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1)
	334	{
	335	cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
	336	"Write error");
	337	}
	338	}
	339
	340	inline uint16
	341	memory_read16 (sim_cpu *cpu, uint16 addr)
	342	{
	343	uint8 b[2];
63f36def	344
e0709f50 AC	345	if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, b, addr, 2) != 2)
	346	{
	347	cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
	348	"Read error");
	349	}
	350	return (((uint16) (b[0])) << 8) \| ((uint16) b[1]);
	351	}
	352
	353	inline void
	354	memory_write16 (sim_cpu *cpu, uint16 addr, uint16 val)
	355	{
	356	uint8 b[2];
	357
	358	b[0] = val >> 8;
	359	b[1] = val;
	360	if (sim_core_write_buffer (CPU_STATE (cpu), cpu, 0, b, addr, 2) != 2)
	361	{
	362	cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
	363	"Write error");
	364	}
	365	}
	366	extern void
	367	cpu_ccr_update_tst8 (sim_cpu *proc, uint8 val);
	368
	369	inline void
	370	cpu_ccr_update_tst16 (sim_cpu *proc, uint16 val)
	371	{
	372	cpu_set_ccr_V (proc, 0);
	373	cpu_set_ccr_N (proc, val & 0x8000 ? 1 : 0);
	374	cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
	375	}
	376
	377	inline void
	378	cpu_ccr_update_shift8 (sim_cpu *proc, uint8 val)
	379	{
	380	cpu_set_ccr_N (proc, val & 0x80 ? 1 : 0);
	381	cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
	382	cpu_set_ccr_V (proc, cpu_get_ccr_N (proc) ^ cpu_get_ccr_C (proc));
	383	}
	384
	385	inline void
	386	cpu_ccr_update_shift16 (sim_cpu *proc, uint16 val)
	387	{
	388	cpu_set_ccr_N (proc, val & 0x8000 ? 1 : 0);
	389	cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
	390	cpu_set_ccr_V (proc, cpu_get_ccr_N (proc) ^ cpu_get_ccr_C (proc));
	391	}
	392
	393	inline void
	394	cpu_ccr_update_add8 (sim_cpu *proc, uint8 r, uint8 a, uint8 b)
	395	{
	396	cpu_set_ccr_C (proc, ((a & b) \| (b & ~r) \| (a & ~r)) & 0x80 ? 1 : 0);
	397	cpu_set_ccr_V (proc, ((a & b & ~r) \| (~a & ~b & r)) & 0x80 ? 1 : 0);
	398	cpu_set_ccr_Z (proc, r == 0);
	399	cpu_set_ccr_N (proc, r & 0x80 ? 1 : 0);
	400	}
	401
	402
	403	inline void
	404	cpu_ccr_update_sub8 (sim_cpu *proc, uint8 r, uint8 a, uint8 b)
	405	{
	406	cpu_set_ccr_C (proc, ((~a & b) \| (b & r) \| (~a & r)) & 0x80 ? 1 : 0);
	407	cpu_set_ccr_V (proc, ((a & ~b & ~r) \| (~a & b & r)) & 0x80 ? 1 : 0);
	408	cpu_set_ccr_Z (proc, r == 0);
409	cpu_set_ccr_N (proc, r & 0x80 ? 1 : 0);
410	}
411
412	inline void
413	cpu_ccr_update_add16 (sim_cpu *proc, uint16 r, uint16 a, uint16 b)
414	{
415	cpu_set_ccr_C (proc, ((a & b) \| (b & ~r) \| (a & ~r)) & 0x8000 ? 1 : 0);
416	cpu_set_ccr_V (proc, ((a & b & ~r) \| (~a & ~b & r)) & 0x8000 ? 1 : 0);
417	cpu_set_ccr_Z (proc, r == 0);
418	cpu_set_ccr_N (proc, r & 0x8000 ? 1 : 0);
419	}
420
421	inline void
422	cpu_ccr_update_sub16 (sim_cpu *proc, uint16 r, uint16 a, uint16 b)
423	{
424	cpu_set_ccr_C (proc, ((~a & b) \| (b & r) \| (~a & r)) & 0x8000 ? 1 : 0);
425	cpu_set_ccr_V (proc, ((a & ~b & ~r) \| (~a & b & r)) & 0x8000 ? 1 : 0);
426	cpu_set_ccr_Z (proc, r == 0);
427	cpu_set_ccr_N (proc, r & 0x8000 ? 1 : 0);
428	}
429
81e09ed8	430	/* Push and pop instructions for 68HC11 (next-available stack mode). */
e0709f50	431	inline void
81e09ed8	432	cpu_m68hc11_push_uint8 (sim_cpu *proc, uint8 val)
e0709f50 AC	433	{
	434	uint16 addr = proc->cpu_regs.sp;
	435
	436	memory_write8 (proc, addr, val);
	437	proc->cpu_regs.sp = addr - 1;
e0709f50 AC	438	}
	439
	440	inline void
81e09ed8	441	cpu_m68hc11_push_uint16 (sim_cpu *proc, uint16 val)
e0709f50 AC	442	{
	443	uint16 addr = proc->cpu_regs.sp - 1;
	444
	445	memory_write16 (proc, addr, val);
	446	proc->cpu_regs.sp = addr - 1;
e0709f50 AC	447	}
	448
	449	inline uint8
81e09ed8	450	cpu_m68hc11_pop_uint8 (sim_cpu *proc)
e0709f50 AC	451	{
	452	uint16 addr = proc->cpu_regs.sp;
	453	uint8 val;
	454
	455	val = memory_read8 (proc, addr + 1);
	456	proc->cpu_regs.sp = addr + 1;
e0709f50 AC	457	return val;
	458	}
	459
	460	inline uint16
81e09ed8	461	cpu_m68hc11_pop_uint16 (sim_cpu *proc)
e0709f50 AC	462	{
	463	uint16 addr = proc->cpu_regs.sp;
	464	uint16 val;
	465
	466	val = memory_read16 (proc, addr + 1);
	467	proc->cpu_regs.sp = addr + 2;
e0709f50 AC	468	return val;
	469	}
	470
81e09ed8 SC	471	/* Push and pop instructions for 68HC12 (last-used stack mode). */
	472	inline void
	473	cpu_m68hc12_push_uint8 (sim_cpu *proc, uint8 val)
	474	{
	475	uint16 addr = proc->cpu_regs.sp;
	476
	477	addr --;
	478	memory_write8 (proc, addr, val);
	479	proc->cpu_regs.sp = addr;
81e09ed8 SC	480	}
	481
	482	inline void
	483	cpu_m68hc12_push_uint16 (sim_cpu *proc, uint16 val)
	484	{
	485	uint16 addr = proc->cpu_regs.sp;
	486
	487	addr -= 2;
	488	memory_write16 (proc, addr, val);
	489	proc->cpu_regs.sp = addr;
81e09ed8 SC	490	}
	491
	492	inline uint8
	493	cpu_m68hc12_pop_uint8 (sim_cpu *proc)
	494	{
	495	uint16 addr = proc->cpu_regs.sp;
	496	uint8 val;
	497
	498	val = memory_read8 (proc, addr);
	499	proc->cpu_regs.sp = addr + 1;
81e09ed8 SC	500	return val;
	501	}
	502
	503	inline uint16
	504	cpu_m68hc12_pop_uint16 (sim_cpu *proc)
	505	{
	506	uint16 addr = proc->cpu_regs.sp;
	507	uint16 val;
	508
	509	val = memory_read16 (proc, addr);
	510	proc->cpu_regs.sp = addr + 2;
81e09ed8 SC	511	return val;
	512	}
	513
	514	/* Fetch a 8/16 bit value and update the PC. */
e0709f50 AC	515	inline uint8
	516	cpu_fetch8 (sim_cpu *proc)
	517	{
	518	uint16 addr = proc->cpu_regs.pc;
	519	uint8 val;
	520
	521	val = memory_read8 (proc, addr);
	522	proc->cpu_regs.pc = addr + 1;
	523	return val;
	524	}
	525
	526	inline uint16
	527	cpu_fetch16 (sim_cpu *proc)
	528	{
	529	uint16 addr = proc->cpu_regs.pc;
	530	uint16 val;
	531
	532	val = memory_read16 (proc, addr);
	533	proc->cpu_regs.pc = addr + 2;
	534	return val;
	535	}
	536
	537	extern void cpu_call (sim_cpu* proc, uint16 addr);
81e09ed8 SC	538	extern void cpu_exg (sim_cpu* proc, uint8 code);
81e09ed8 SC	539	extern void cpu_dbcc (sim_cpu* proc);
e0709f50	540	extern void cpu_special (sim_cpu *proc, enum M6811_Special special);
81e09ed8 SC	541	extern void cpu_move8 (sim_cpu *proc, uint8 op);
81e09ed8 SC	542	extern void cpu_move16 (sim_cpu *proc, uint8 op);
e0709f50 AC	543
e0709f50 AC	544	extern uint16 cpu_fetch_relbranch (sim_cpu *proc);
81e09ed8	545	extern uint16 cpu_fetch_relbranch16 (sim_cpu *proc);
e0709f50 AC	546	extern void cpu_push_all (sim_cpu *proc);
	547	extern void cpu_single_step (sim_cpu *proc);
	548
	549	extern void cpu_info (SIM_DESC sd, sim_cpu *proc);
	550
	551	extern int cpu_initialize (SIM_DESC sd, sim_cpu *cpu);
	552
63f36def SC	553	/* Returns the address of a 68HC12 indexed operand.
	554	Pre and post modifications are handled on the source register. */
	555	extern uint16 cpu_get_indexed_operand_addr (sim_cpu* cpu, int restrict);
	556
	557	extern void cpu_return (sim_cpu *cpu);
e0709f50	558	extern void cpu_set_sp (sim_cpu *cpu, uint16 val);
e0709f50 AC	559	extern int cpu_reset (sim_cpu *cpu);
	560	extern int cpu_restart (sim_cpu *cpu);
	561	extern void sim_memory_error (sim_cpu *cpu, SIM_SIGNAL excep,
	562	uint16 addr, const char *message, ...);
	563	extern void emul_os (int op, sim_cpu *cpu);
81e09ed8 SC	564	extern void cpu_interp_m6811 (sim_cpu *cpu);
81e09ed8 SC	565	extern void cpu_interp_m6812 (sim_cpu *cpu);
e0709f50	566
827ec39a SC	567	extern int m68hc11cpu_set_oscillator (SIM_DESC sd, const char *port,
	568	double ton, double toff,
	569	signed64 repeat);
	570	extern int m68hc11cpu_clear_oscillator (SIM_DESC sd, const char *port);
	571	extern void m68hc11cpu_set_port (struct hw me, sim_cpu cpu,
	572	unsigned addr, uint8 val);
	573
e0709f50 AC	574	/* The current state of the processor; registers, memory, etc. */
	575
	576	#define CIA_GET(CPU) (cpu_get_pc (CPU))
	577	#define CIA_SET(CPU,VAL) (cpu_set_pc ((CPU), (VAL)))
	578
	579	#if (WITH_SMP)
	580	#define STATE_CPU(sd,n) (&(sd)->cpu[n])
	581	#else
	582	#define STATE_CPU(sd,n) (&(sd)->cpu[0])
	583	#endif
	584
	585	struct sim_state {
	586	sim_cpu cpu[MAX_NR_PROCESSORS];
	587	device *devices;
	588	sim_state_base base;
	589	};
	590
	591	extern void sim_set_profile (int n);
	592	extern void sim_set_profile_size (int n);
	593	extern void sim_board_reset (SIM_DESC sd);
	594
a685700c SC	595	#define PRINT_TIME 0x01
	596	#define PRINT_CYCLE 0x02
	597	extern const char cycle_to_string (sim_cpu cpu, signed64 t, int flags);
2990a9f4	598
e0709f50 AC	599	#endif
	600
	601