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e0709f50 AC |
1 | /* sim-main.h -- Simulator for Motorola 68HC11 |
2 | Copyright (C) 1999, 2000 Free Software Foundation, Inc. | |
3 | Written by Stephane Carrez (stcarrez@worldnet.fr) | |
4 | ||
5 | This file is part of GDB, the GNU debugger. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License along | |
18 | with this program; if not, write to the Free Software Foundation, Inc., | |
19 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
20 | ||
21 | #ifndef _SIM_MAIN_H | |
22 | #define _SIM_MAIN_H | |
23 | ||
24 | #define WITH_MODULO_MEMORY 1 | |
25 | #define WITH_WATCHPOINTS 1 | |
26 | #define SIM_HANDLES_LMA 1 | |
27 | ||
28 | #include "sim-basics.h" | |
29 | ||
30 | typedef address_word sim_cia; | |
31 | ||
32 | #include "sim-signal.h" | |
33 | #include "sim-base.h" | |
34 | ||
35 | #include "bfd.h" | |
36 | ||
37 | #include "opcode/m68hc11.h" | |
38 | ||
39 | #include "callback.h" | |
40 | #include "remote-sim.h" | |
41 | #include "opcode/m68hc11.h" | |
42 | #include "sim-types.h" | |
43 | ||
44 | typedef unsigned8 uint8; | |
45 | typedef unsigned16 uint16; | |
46 | typedef signed16 int16; | |
47 | typedef unsigned32 uint32; | |
48 | typedef signed32 int32; | |
49 | typedef unsigned64 uint64; | |
50 | typedef signed64 int64; | |
51 | ||
52 | struct _sim_cpu; | |
53 | ||
54 | #include "interrupts.h" | |
55 | #include <setjmp.h> | |
56 | ||
63348d04 SC |
57 | /* Specifies the level of mapping for the IO, EEprom, nvram and external |
58 | RAM. IO registers are mapped over everything and the external RAM | |
59 | is last (ie, it can be hidden by everything above it in the list). */ | |
60 | enum m68hc11_map_level | |
61 | { | |
62 | M6811_IO_LEVEL, | |
63 | M6811_EEPROM_LEVEL, | |
64 | M6811_NVRAM_LEVEL, | |
65 | M6811_RAM_LEVEL | |
66 | }; | |
67 | ||
68 | ||
e0709f50 AC |
69 | #define X_REGNUM 0 |
70 | #define D_REGNUM 1 | |
71 | #define Y_REGNUM 2 | |
72 | #define SP_REGNUM 3 | |
73 | #define PC_REGNUM 4 | |
74 | #define A_REGNUM 5 | |
75 | #define B_REGNUM 6 | |
76 | #define PSW_REGNUM 7 | |
77 | #define Z_REGNUM 8 | |
78 | #define FP_REGNUM 9 | |
79 | #define TMP_REGNUM 10 | |
80 | #define ZS_REGNUM 11 | |
81 | #define XY_REGNUM 12 | |
82 | #define ZD1_REGNUM 13 | |
83 | #define ZD32_REGNUM (ZD1_REGNUM+31) | |
84 | ||
85 | #define FIRST_SOFT_REGNUM (Z_REGNUM) | |
86 | #define MAX_SOFT_REG (ZD32_REGNUM - Z_REGNUM + 1) | |
87 | ||
88 | typedef struct m6811_regs { | |
89 | unsigned short d; | |
90 | unsigned short ix; | |
91 | unsigned short iy; | |
92 | unsigned short sp; | |
93 | unsigned short pc; | |
94 | unsigned char ccr; | |
95 | } m6811_regs; | |
96 | ||
97 | ||
98 | /* Description of 68HC11 IO registers. Such description is only provided | |
99 | for the info command to display the current setting of IO registers | |
100 | from GDB. */ | |
101 | struct io_reg_desc | |
102 | { | |
103 | int mask; | |
104 | const char *short_name; | |
105 | const char *long_name; | |
106 | }; | |
107 | typedef struct io_reg_desc io_reg_desc; | |
108 | ||
109 | extern void print_io_reg_desc (SIM_DESC sd, io_reg_desc *desc, int val, | |
110 | int mode); | |
111 | extern void print_io_byte (SIM_DESC sd, const char *name, | |
112 | io_reg_desc *desc, uint8 val, uint16 addr); | |
113 | ||
114 | ||
115 | /* List of special 68HC11 instructions that are not handled by the | |
116 | 'gencode.c' generator. These complex instructions are implemented | |
117 | by 'cpu_special'. */ | |
118 | enum M6811_Special | |
119 | { | |
120 | M6811_RTI, | |
121 | M6811_WAI, | |
122 | M6811_SWI, | |
123 | M6811_TEST, | |
124 | M6811_ILLEGAL, | |
125 | M6811_EMUL_SYSCALL | |
126 | }; | |
127 | ||
128 | #define CPU_POP 1 | |
129 | #define CPU_PUSH 2 | |
130 | ||
131 | #define MAX_PORTS 0x40 | |
132 | ||
133 | /* Tentative to keep track of the stack frame. | |
134 | The frame is updated each time a call or a return are made. | |
135 | We also have to take into account changes of stack pointer | |
136 | (either thread switch or longjmp). */ | |
137 | struct cpu_frame | |
138 | { | |
139 | struct cpu_frame *up; | |
140 | uint16 pc; | |
141 | uint16 sp_low; | |
142 | uint16 sp_high; | |
143 | }; | |
144 | ||
145 | /* Represents a list of frames (or a thread). */ | |
146 | struct cpu_frame_list | |
147 | { | |
148 | struct cpu_frame_list *next; | |
149 | struct cpu_frame_list *prev; | |
150 | struct cpu_frame *frame; | |
151 | }; | |
152 | ||
153 | struct _sim_cpu { | |
154 | /* CPU registers. */ | |
155 | struct m6811_regs cpu_regs; | |
156 | ||
157 | /* CPU interrupts. */ | |
158 | struct interrupts cpu_interrupts; | |
159 | ||
160 | struct cpu_frame_list *cpu_frames; | |
161 | struct cpu_frame_list *cpu_current_frame; | |
162 | int cpu_need_update_frame; | |
163 | ||
164 | /* CPU absolute cycle time. The cycle time is updated after | |
165 | each instruction, by the number of cycles taken by the instruction. | |
166 | It is cleared only when reset occurs. */ | |
167 | signed64 cpu_absolute_cycle; | |
168 | ||
169 | /* Number of cycles to increment after the current instruction. | |
170 | This is also the number of ticks for the generic event scheduler. */ | |
171 | uint8 cpu_current_cycle; | |
172 | int cpu_emul_syscall; | |
173 | int cpu_is_initialized; | |
174 | int cpu_running; | |
175 | int cpu_check_memory; | |
176 | int cpu_stop_on_interrupt; | |
177 | ||
178 | /* When this is set, start execution of program at address specified | |
179 | in the ELF header. This is used for testing some programs that do not | |
180 | have an interrupt table linked with them. Programs created during the | |
181 | GCC validation are like this. A normal 68HC11 does not behave like | |
182 | this (unless there is some OS or downloadable feature). */ | |
183 | int cpu_use_elf_start; | |
184 | ||
185 | /* The starting address specified in ELF header. */ | |
186 | int cpu_elf_start; | |
187 | ||
188 | uint16 cpu_insn_pc; | |
189 | unsigned short cpu_nb_pseudo_regs; | |
190 | uint16 cpu_page0_reg[MAX_SOFT_REG]; | |
191 | ||
192 | /* CPU frequency. This is the quartz frequency. It is divided by 4 to | |
193 | get the cycle time. This is used for the timer rate and for the baud | |
194 | rate generation. */ | |
195 | unsigned long cpu_frequency; | |
196 | ||
197 | /* The mode in which the CPU is configured (MODA and MODB pins). */ | |
198 | unsigned int cpu_mode; | |
199 | ||
200 | /* Initial value of the CONFIG register. */ | |
201 | uint8 cpu_config; | |
202 | uint8 cpu_use_local_config; | |
203 | ||
204 | uint8 ios[0x3F]; | |
205 | ||
206 | /* ... base type ... */ | |
207 | sim_cpu_base base; | |
208 | }; | |
209 | ||
210 | /* Returns the cpu absolute cycle time (A virtual counter incremented | |
211 | at each 68HC11 E clock). */ | |
212 | #define cpu_current_cycle(PROC) ((PROC)->cpu_absolute_cycle) | |
213 | #define cpu_add_cycles(PROC,T) ((PROC)->cpu_current_cycle += (signed64) (T)) | |
214 | #define cpu_is_running(PROC) ((PROC)->cpu_running) | |
215 | ||
216 | /* Get the IO/RAM base addresses depending on the M6811_INIT register. */ | |
217 | #define cpu_get_io_base(PROC) \ | |
218 | (((uint16)(((PROC)->ios[M6811_INIT]) & 0x0F))<<12) | |
219 | #define cpu_get_reg_base(PROC) \ | |
220 | (((uint16)(((PROC)->ios[M6811_INIT]) & 0xF0))<<8) | |
221 | ||
222 | /* Returns the different CPU registers. */ | |
223 | #define cpu_get_ccr(PROC) ((PROC)->cpu_regs.ccr) | |
224 | #define cpu_get_pc(PROC) ((PROC)->cpu_regs.pc) | |
225 | #define cpu_get_d(PROC) ((PROC)->cpu_regs.d) | |
226 | #define cpu_get_x(PROC) ((PROC)->cpu_regs.ix) | |
227 | #define cpu_get_y(PROC) ((PROC)->cpu_regs.iy) | |
228 | #define cpu_get_sp(PROC) ((PROC)->cpu_regs.sp) | |
229 | #define cpu_get_a(PROC) ((PROC->cpu_regs.d >> 8) & 0x0FF) | |
230 | #define cpu_get_b(PROC) ((PROC->cpu_regs.d) & 0x0FF) | |
231 | ||
232 | #define cpu_set_d(PROC,VAL) (((PROC)->cpu_regs.d) = (VAL)) | |
233 | #define cpu_set_x(PROC,VAL) (((PROC)->cpu_regs.ix) = (VAL)) | |
234 | #define cpu_set_y(PROC,VAL) (((PROC)->cpu_regs.iy) = (VAL)) | |
235 | ||
236 | #if 0 | |
237 | /* This is a function in m68hc11_sim.c to keep track of the frame. */ | |
238 | #define cpu_set_sp(PROC,VAL) (((PROC)->cpu_regs.sp) = (VAL)) | |
239 | #endif | |
240 | ||
241 | #define cpu_set_pc(PROC,VAL) (((PROC)->cpu_regs.pc) = (VAL)) | |
242 | ||
243 | #define cpu_set_a(PROC,VAL) \ | |
244 | cpu_set_d(PROC,((VAL) << 8) | cpu_get_b(PROC)) | |
245 | #define cpu_set_b(PROC,VAL) \ | |
246 | cpu_set_d(PROC,((cpu_get_a(PROC)) << 8)|(VAL & 0x0FF)) | |
247 | ||
248 | #define cpu_set_ccr(PROC,VAL) ((PROC)->cpu_regs.ccr = (VAL)) | |
249 | #define cpu_get_ccr_H(PROC) ((cpu_get_ccr(PROC) & M6811_H_BIT) ? 1: 0) | |
250 | #define cpu_get_ccr_X(PROC) ((cpu_get_ccr(PROC) & M6811_X_BIT) ? 1: 0) | |
251 | #define cpu_get_ccr_S(PROC) ((cpu_get_ccr(PROC) & M6811_S_BIT) ? 1: 0) | |
252 | #define cpu_get_ccr_N(PROC) ((cpu_get_ccr(PROC) & M6811_N_BIT) ? 1: 0) | |
253 | #define cpu_get_ccr_V(PROC) ((cpu_get_ccr(PROC) & M6811_V_BIT) ? 1: 0) | |
254 | #define cpu_get_ccr_C(PROC) ((cpu_get_ccr(PROC) & M6811_C_BIT) ? 1: 0) | |
255 | #define cpu_get_ccr_Z(PROC) ((cpu_get_ccr(PROC) & M6811_Z_BIT) ? 1: 0) | |
256 | #define cpu_get_ccr_I(PROC) ((cpu_get_ccr(PROC) & M6811_I_BIT) ? 1: 0) | |
257 | ||
258 | #define cpu_set_ccr_flag(S,B,V) \ | |
259 | cpu_set_ccr(S,(cpu_get_ccr(S) & ~(B)) | ((V) ? B : 0)) | |
260 | ||
261 | #define cpu_set_ccr_H(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_H_BIT, VAL) | |
262 | #define cpu_set_ccr_X(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_X_BIT, VAL) | |
263 | #define cpu_set_ccr_S(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_S_BIT, VAL) | |
264 | #define cpu_set_ccr_N(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_N_BIT, VAL) | |
265 | #define cpu_set_ccr_V(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_V_BIT, VAL) | |
266 | #define cpu_set_ccr_C(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_C_BIT, VAL) | |
267 | #define cpu_set_ccr_Z(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_Z_BIT, VAL) | |
268 | #define cpu_set_ccr_I(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_I_BIT, VAL) | |
269 | ||
270 | #undef inline | |
271 | #define inline static __inline__ | |
272 | ||
273 | extern void cpu_memory_exception (struct _sim_cpu *proc, | |
274 | SIM_SIGNAL excep, | |
275 | uint16 addr, | |
276 | const char *message); | |
277 | ||
278 | inline uint8 | |
279 | memory_read8 (sim_cpu *cpu, uint16 addr) | |
280 | { | |
281 | uint8 val; | |
282 | ||
283 | if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1) | |
284 | { | |
285 | cpu_memory_exception (cpu, SIM_SIGSEGV, addr, | |
286 | "Read error"); | |
287 | } | |
288 | return val; | |
289 | } | |
290 | ||
291 | inline void | |
292 | memory_write8 (sim_cpu *cpu, uint16 addr, uint8 val) | |
293 | { | |
294 | if (sim_core_write_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1) | |
295 | { | |
296 | cpu_memory_exception (cpu, SIM_SIGSEGV, addr, | |
297 | "Write error"); | |
298 | } | |
299 | } | |
300 | ||
301 | inline uint16 | |
302 | memory_read16 (sim_cpu *cpu, uint16 addr) | |
303 | { | |
304 | uint8 b[2]; | |
305 | ||
306 | if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, b, addr, 2) != 2) | |
307 | { | |
308 | cpu_memory_exception (cpu, SIM_SIGSEGV, addr, | |
309 | "Read error"); | |
310 | } | |
311 | return (((uint16) (b[0])) << 8) | ((uint16) b[1]); | |
312 | } | |
313 | ||
314 | inline void | |
315 | memory_write16 (sim_cpu *cpu, uint16 addr, uint16 val) | |
316 | { | |
317 | uint8 b[2]; | |
318 | ||
319 | b[0] = val >> 8; | |
320 | b[1] = val; | |
321 | if (sim_core_write_buffer (CPU_STATE (cpu), cpu, 0, b, addr, 2) != 2) | |
322 | { | |
323 | cpu_memory_exception (cpu, SIM_SIGSEGV, addr, | |
324 | "Write error"); | |
325 | } | |
326 | } | |
327 | extern void | |
328 | cpu_ccr_update_tst8 (sim_cpu *proc, uint8 val); | |
329 | ||
330 | inline void | |
331 | cpu_ccr_update_tst16 (sim_cpu *proc, uint16 val) | |
332 | { | |
333 | cpu_set_ccr_V (proc, 0); | |
334 | cpu_set_ccr_N (proc, val & 0x8000 ? 1 : 0); | |
335 | cpu_set_ccr_Z (proc, val == 0 ? 1 : 0); | |
336 | } | |
337 | ||
338 | inline void | |
339 | cpu_ccr_update_shift8 (sim_cpu *proc, uint8 val) | |
340 | { | |
341 | cpu_set_ccr_N (proc, val & 0x80 ? 1 : 0); | |
342 | cpu_set_ccr_Z (proc, val == 0 ? 1 : 0); | |
343 | cpu_set_ccr_V (proc, cpu_get_ccr_N (proc) ^ cpu_get_ccr_C (proc)); | |
344 | } | |
345 | ||
346 | inline void | |
347 | cpu_ccr_update_shift16 (sim_cpu *proc, uint16 val) | |
348 | { | |
349 | cpu_set_ccr_N (proc, val & 0x8000 ? 1 : 0); | |
350 | cpu_set_ccr_Z (proc, val == 0 ? 1 : 0); | |
351 | cpu_set_ccr_V (proc, cpu_get_ccr_N (proc) ^ cpu_get_ccr_C (proc)); | |
352 | } | |
353 | ||
354 | inline void | |
355 | cpu_ccr_update_add8 (sim_cpu *proc, uint8 r, uint8 a, uint8 b) | |
356 | { | |
357 | cpu_set_ccr_C (proc, ((a & b) | (b & ~r) | (a & ~r)) & 0x80 ? 1 : 0); | |
358 | cpu_set_ccr_V (proc, ((a & b & ~r) | (~a & ~b & r)) & 0x80 ? 1 : 0); | |
359 | cpu_set_ccr_Z (proc, r == 0); | |
360 | cpu_set_ccr_N (proc, r & 0x80 ? 1 : 0); | |
361 | } | |
362 | ||
363 | ||
364 | inline void | |
365 | cpu_ccr_update_sub8 (sim_cpu *proc, uint8 r, uint8 a, uint8 b) | |
366 | { | |
367 | cpu_set_ccr_C (proc, ((~a & b) | (b & r) | (~a & r)) & 0x80 ? 1 : 0); | |
368 | cpu_set_ccr_V (proc, ((a & ~b & ~r) | (~a & b & r)) & 0x80 ? 1 : 0); | |
369 | cpu_set_ccr_Z (proc, r == 0); | |
370 | cpu_set_ccr_N (proc, r & 0x80 ? 1 : 0); | |
371 | } | |
372 | ||
373 | inline void | |
374 | cpu_ccr_update_add16 (sim_cpu *proc, uint16 r, uint16 a, uint16 b) | |
375 | { | |
376 | cpu_set_ccr_C (proc, ((a & b) | (b & ~r) | (a & ~r)) & 0x8000 ? 1 : 0); | |
377 | cpu_set_ccr_V (proc, ((a & b & ~r) | (~a & ~b & r)) & 0x8000 ? 1 : 0); | |
378 | cpu_set_ccr_Z (proc, r == 0); | |
379 | cpu_set_ccr_N (proc, r & 0x8000 ? 1 : 0); | |
380 | } | |
381 | ||
382 | inline void | |
383 | cpu_ccr_update_sub16 (sim_cpu *proc, uint16 r, uint16 a, uint16 b) | |
384 | { | |
385 | cpu_set_ccr_C (proc, ((~a & b) | (b & r) | (~a & r)) & 0x8000 ? 1 : 0); | |
386 | cpu_set_ccr_V (proc, ((a & ~b & ~r) | (~a & b & r)) & 0x8000 ? 1 : 0); | |
387 | cpu_set_ccr_Z (proc, r == 0); | |
388 | cpu_set_ccr_N (proc, r & 0x8000 ? 1 : 0); | |
389 | } | |
390 | ||
391 | ||
392 | inline void | |
393 | cpu_push_uint8 (sim_cpu *proc, uint8 val) | |
394 | { | |
395 | uint16 addr = proc->cpu_regs.sp; | |
396 | ||
397 | memory_write8 (proc, addr, val); | |
398 | proc->cpu_regs.sp = addr - 1; | |
399 | proc->cpu_need_update_frame |= CPU_PUSH; | |
400 | } | |
401 | ||
402 | inline void | |
403 | cpu_push_uint16 (sim_cpu *proc, uint16 val) | |
404 | { | |
405 | uint16 addr = proc->cpu_regs.sp - 1; | |
406 | ||
407 | memory_write16 (proc, addr, val); | |
408 | proc->cpu_regs.sp = addr - 1; | |
409 | proc->cpu_need_update_frame |= CPU_PUSH; | |
410 | } | |
411 | ||
412 | inline uint8 | |
413 | cpu_pop_uint8 (sim_cpu *proc) | |
414 | { | |
415 | uint16 addr = proc->cpu_regs.sp; | |
416 | uint8 val; | |
417 | ||
418 | val = memory_read8 (proc, addr + 1); | |
419 | proc->cpu_regs.sp = addr + 1; | |
420 | proc->cpu_need_update_frame |= CPU_POP; | |
421 | return val; | |
422 | } | |
423 | ||
424 | inline uint16 | |
425 | cpu_pop_uint16 (sim_cpu *proc) | |
426 | { | |
427 | uint16 addr = proc->cpu_regs.sp; | |
428 | uint16 val; | |
429 | ||
430 | val = memory_read16 (proc, addr + 1); | |
431 | proc->cpu_regs.sp = addr + 2; | |
432 | proc->cpu_need_update_frame |= CPU_POP; | |
433 | return val; | |
434 | } | |
435 | ||
436 | inline uint8 | |
437 | cpu_fetch8 (sim_cpu *proc) | |
438 | { | |
439 | uint16 addr = proc->cpu_regs.pc; | |
440 | uint8 val; | |
441 | ||
442 | val = memory_read8 (proc, addr); | |
443 | proc->cpu_regs.pc = addr + 1; | |
444 | return val; | |
445 | } | |
446 | ||
447 | inline uint16 | |
448 | cpu_fetch16 (sim_cpu *proc) | |
449 | { | |
450 | uint16 addr = proc->cpu_regs.pc; | |
451 | uint16 val; | |
452 | ||
453 | val = memory_read16 (proc, addr); | |
454 | proc->cpu_regs.pc = addr + 2; | |
455 | return val; | |
456 | } | |
457 | ||
458 | extern void cpu_call (sim_cpu* proc, uint16 addr); | |
459 | extern void cpu_special (sim_cpu *proc, enum M6811_Special special); | |
460 | ||
461 | extern uint16 cpu_fetch_relbranch (sim_cpu *proc); | |
462 | extern void cpu_push_all (sim_cpu *proc); | |
463 | extern void cpu_single_step (sim_cpu *proc); | |
464 | ||
465 | extern void cpu_info (SIM_DESC sd, sim_cpu *proc); | |
466 | ||
467 | extern int cpu_initialize (SIM_DESC sd, sim_cpu *cpu); | |
468 | ||
469 | extern void cpu_print_frame (SIM_DESC sd, sim_cpu *cpu); | |
470 | extern void cpu_set_sp (sim_cpu *cpu, uint16 val); | |
471 | extern uint16 cpu_frame_reg (sim_cpu *cpu, uint16 rn); | |
472 | extern int cpu_reset (sim_cpu *cpu); | |
473 | extern int cpu_restart (sim_cpu *cpu); | |
474 | extern void sim_memory_error (sim_cpu *cpu, SIM_SIGNAL excep, | |
475 | uint16 addr, const char *message, ...); | |
476 | extern void emul_os (int op, sim_cpu *cpu); | |
477 | extern void cpu_interp (sim_cpu *cpu); | |
478 | ||
479 | /* The current state of the processor; registers, memory, etc. */ | |
480 | ||
481 | #define CIA_GET(CPU) (cpu_get_pc (CPU)) | |
482 | #define CIA_SET(CPU,VAL) (cpu_set_pc ((CPU), (VAL))) | |
483 | ||
484 | #if (WITH_SMP) | |
485 | #define STATE_CPU(sd,n) (&(sd)->cpu[n]) | |
486 | #else | |
487 | #define STATE_CPU(sd,n) (&(sd)->cpu[0]) | |
488 | #endif | |
489 | ||
490 | struct sim_state { | |
491 | sim_cpu cpu[MAX_NR_PROCESSORS]; | |
492 | device *devices; | |
493 | sim_state_base base; | |
494 | }; | |
495 | ||
496 | extern void sim_set_profile (int n); | |
497 | extern void sim_set_profile_size (int n); | |
498 | extern void sim_board_reset (SIM_DESC sd); | |
499 | ||
500 | #endif | |
501 | ||
502 |