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2005-05-26 David Ung <davidu@mips.com>
[deliverable/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
e70cb6cd
CD		 12005-05-26 David Ung <davidu@mips.com>
2
3 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
4 tags to all instructions which are applicable to the new ISAs.
5 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
6 vr.igen.
7 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
8 instructions.
9 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
10 to mips.igen.
11 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
12 * configure: Regenerate.
13
2b193c4a
MK		 142005-03-23 Mark Kettenis <kettenis@gnu.org>
15
16 * configure: Regenerate.
17
35695fd6
AC		 182005-01-14 Andrew Cagney <cagney@gnu.org>
19
20 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
21 explicit call to AC_CONFIG_HEADER.
22 * configure: Regenerate.
23
f0569246
AC		 242005-01-12 Andrew Cagney <cagney@gnu.org>
25
26 * configure.ac: Update to use ../common/common.m4.
27 * configure: Re-generate.
28
38f48d72
AC		 292005-01-11 Andrew Cagney <cagney@localhost.localdomain>
30
31 * configure: Regenerated to track ../common/aclocal.m4 changes.
32
b7026657
AC		 332005-01-07 Andrew Cagney <cagney@gnu.org>
34
35 * configure.ac: Rename configure.in, require autoconf 2.59.
36 * configure: Re-generate.
37
379832de
HPN		 382004-12-08 Hans-Peter Nilsson <hp@axis.com>
39
40 * configure: Regenerate for ../common/aclocal.m4 update.
41
cd62154c
AC		 422004-09-24 Monika Chaddha <monika@acmet.com>
43
44 Committed by Andrew Cagney.
45 * m16.igen (CMP, CMPI): Fix assembler.
46
e5da76ec
CD		 472004-08-18 Chris Demetriou <cgd@broadcom.com>
48
49 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
50 * configure: Regenerate.
51
139181c8
CD		 522004-06-25 Chris Demetriou <cgd@broadcom.com>
53
54 * configure.in (sim_m16_machine): Include mipsIII.
55 * configure: Regenerate.
56
1a27f959
CD		 572004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
58
59 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
60 from COP0_BADVADDR.
61 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
62
5dbb7b5a
CD		 632004-04-10 Chris Demetriou <cgd@broadcom.com>
64
65 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
66
14234056
CD		 672004-04-09 Chris Demetriou <cgd@broadcom.com>
68
69 * mips.igen (check_fmt): Remove.
70 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
71 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
72 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
73 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
74 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
75 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
76 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
77 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
78 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
79 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
80
c6f9085c
CD		 812004-04-09 Chris Demetriou <cgd@broadcom.com>
82
83 * sb1.igen (check_sbx): New function.
84 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
85
11d66e66 862004-03-29 Chris Demetriou <cgd@broadcom.com>
0e1b7197
RS		 87 Richard Sandiford <rsandifo@redhat.com>
88
89 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
90 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
91 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
92 separate implementations for mipsIV and mipsV. Use new macros to
93 determine whether the restrictions apply.
94
b3208fb8
CD		 952004-01-19 Chris Demetriou <cgd@broadcom.com>
96
97 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
98 (check_mult_hilo): Improve comments.
99 (check_div_hilo): Likewise. Also, fork off a new version
100 to handle mips32/mips64 (since there are no hazards to check
101 in MIPS32/MIPS64).
102
9a1d84fb
CD		 1032003-06-17 Richard Sandiford <rsandifo@redhat.com>
104
105 * mips.igen (do_dmultx): Fix check for negative operands.
106
ae451ac6
ILT		 1072003-05-16 Ian Lance Taylor <ian@airs.com>
108
109 * Makefile.in (SHELL): Make sure this is defined.
110 (various): Use $(SHELL) whenever we invoke move-if-change.
111
dd69d292
CD		 1122003-05-03 Chris Demetriou <cgd@broadcom.com>
113
114 * cp1.c: Tweak attribution slightly.
115 * cp1.h: Likewise.
116 * mdmx.c: Likewise.
117 * mdmx.igen: Likewise.
118 * mips3d.igen: Likewise.
119 * sb1.igen: Likewise.
120
bcd0068e
CD		 1212003-04-15 Richard Sandiford <rsandifo@redhat.com>
122
123 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
124 unsigned operands.
125
6b4a8935
AC		 1262003-02-27 Andrew Cagney <cagney@redhat.com>
127
601da316
AC		 128 * interp.c (sim_open): Rename _bfd to bfd.
129 (sim_create_inferior): Ditto.
6b4a8935 130
d29e330f
CD		 1312003-01-14 Chris Demetriou <cgd@broadcom.com>
132
133 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
134
a2353a08
CD		 1352003-01-14 Chris Demetriou <cgd@broadcom.com>
136
137 * mips.igen (EI, DI): Remove.
138
80551777
CD		 1392003-01-05 Richard Sandiford <rsandifo@redhat.com>
140
141 * Makefile.in (tmp-run-multi): Fix mips16 filter.
142
4c54fc26
CD		 1432003-01-04 Richard Sandiford <rsandifo@redhat.com>
144 Andrew Cagney <ac131313@redhat.com>
145 Gavin Romig-Koch <gavin@redhat.com>
146 Graydon Hoare <graydon@redhat.com>
147 Aldy Hernandez <aldyh@redhat.com>
148 Dave Brolley <brolley@redhat.com>
149 Chris Demetriou <cgd@broadcom.com>
150
151 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
152 (sim_mach_default): New variable.
153 (mips64vr-*-*, mips64vrel-*-*): New configurations.
154 Add a new simulator generator, MULTI.
155 * configure: Regenerate.
156 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
157 (multi-run.o): New dependency.
158 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
159 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
160 (tmp-multi): Combine them.
161 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
162 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
163 (distclean-extra): New rule.
164 * sim-main.h: Include bfd.h.
165 (MIPS_MACH): New macro.
166 * mips.igen (vr4120, vr5400, vr5500): New models.
167 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
168 * vr.igen: Replace with new version.
169
e6c674b8
CD		 1702003-01-04 Chris Demetriou <cgd@broadcom.com>
171
172 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
173 * configure: Regenerate.
174
28f50ac8
CD		 1752002-12-31 Chris Demetriou <cgd@broadcom.com>
176
177 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
178 * mips.igen: Remove all invocations of check_branch_bug and
179 mark_branch_bug.
180
5071ffe6
CD		 1812002-12-16 Chris Demetriou <cgd@broadcom.com>
182
183 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
184
06e7837e
CD		 1852002-07-30 Chris Demetriou <cgd@broadcom.com>
186
187 * mips.igen (do_load_double, do_store_double): New functions.
188 (LDC1, SDC1): Rename to...
189 (LDC1b, SDC1b): respectively.
190 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
191
2265c243
MS		 1922002-07-29 Michael Snyder <msnyder@redhat.com>
193
194 * cp1.c (fp_recip2): Modify initialization expression so that
195 GCC will recognize it as constant.
196
a2f8b4f3
CD		 1972002-06-18 Chris Demetriou <cgd@broadcom.com>
198
199 * mdmx.c (SD_): Delete.
200 (Unpredictable): Re-define, for now, to directly invoke
201 unpredictable_action().
202 (mdmx_acc_op): Fix error in .ob immediate handling.
203
b4b6c939
AC		 2042002-06-18 Andrew Cagney <cagney@redhat.com>
205
206 * interp.c (sim_firmware_command): Initialize `address'.
207
c8cca39f
AC		 2082002-06-16 Andrew Cagney <ac131313@redhat.com>
209
210 * configure: Regenerated to track ../common/aclocal.m4 changes.
211
e7e81181
CD		 2122002-06-14 Chris Demetriou <cgd@broadcom.com>
213 Ed Satterthwaite <ehs@broadcom.com>
214
215 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
216 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
217 * mips.igen: Include mips3d.igen.
218 (mips3d): New model name for MIPS-3D ASE instructions.
219 (CVT.W.fmt): Don't use this instruction for word (source) format
220 instructions.
221 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
222 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
223 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
224 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
225 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
226 (RSquareRoot1, RSquareRoot2): New macros.
227 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
228 (fp_rsqrt2): New functions.
229 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
230 * configure: Regenerate.
231
3a2b820e 2322002-06-13 Chris Demetriou <cgd@broadcom.com>
eab54952 233 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 234
235 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
236 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
237 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
238 (convert): Note that this function is not used for paired-single
239 format conversions.
240 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
241 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
242 (check_fmt_p): Enable paired-single support.
243 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
244 (PUU.PS): New instructions.
245 (CVT.S.fmt): Don't use this instruction for paired-single format
246 destinations.
247 * sim-main.h (FP_formats): New value 'fmt_ps.'
248 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
249 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
250
d18ea9c2
CD		 2512002-06-12 Chris Demetriou <cgd@broadcom.com>
252
253 * mips.igen: Fix formatting of function calls in
254 many FP operations.
255
95fd5cee
CD		 2562002-06-12 Chris Demetriou <cgd@broadcom.com>
257
258 * mips.igen (MOVN, MOVZ): Trace result.
259 (TNEI): Print "tnei" as the opcode name in traces.
260 (CEIL.W): Add disassembly string for traces.
261 (RSQRT.fmt): Make location of disassembly string consistent
262 with other instructions.
263
4f0d55ae
CD		 2642002-06-12 Chris Demetriou <cgd@broadcom.com>
265
266 * mips.igen (X): Delete unused function.
267
3c25f8c7
AC		 2682002-06-08 Andrew Cagney <cagney@redhat.com>
269
270 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
271
f3c08b7e
CD		 2722002-06-07 Chris Demetriou <cgd@broadcom.com>
273 Ed Satterthwaite <ehs@broadcom.com>
274
275 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
276 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
277 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
278 (fp_nmsub): New prototypes.
279 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
280 (NegMultiplySub): New defines.
281 * mips.igen (RSQRT.fmt): Use RSquareRoot().
282 (MADD.D, MADD.S): Replace with...
283 (MADD.fmt): New instruction.
284 (MSUB.D, MSUB.S): Replace with...
285 (MSUB.fmt): New instruction.
286 (NMADD.D, NMADD.S): Replace with...
287 (NMADD.fmt): New instruction.
288 (NMSUB.D, MSUB.S): Replace with...
289 (NMSUB.fmt): New instruction.
290
52714ff9
CD		 2912002-06-07 Chris Demetriou <cgd@broadcom.com>
292 Ed Satterthwaite <ehs@broadcom.com>
293
294 * cp1.c: Fix more comment spelling and formatting.
295 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
296 (denorm_mode): New function.
297 (fpu_unary, fpu_binary): Round results after operation, collect
298 status from rounding operations, and update the FCSR.
299 (convert): Collect status from integer conversions and rounding
300 operations, and update the FCSR. Adjust NaN values that result
301 from conversions. Convert to use sim_io_eprintf rather than
302 fprintf, and remove some debugging code.
303 * cp1.h (fenr_FS): New define.
304
577d8c4b
CD		 3052002-06-07 Chris Demetriou <cgd@broadcom.com>
306
307 * cp1.c (convert): Remove unusable debugging code, and move MIPS
308 rounding mode to sim FP rounding mode flag conversion code into...
309 (rounding_mode): New function.
310
196496ed
CD		 3112002-06-07 Chris Demetriou <cgd@broadcom.com>
312
313 * cp1.c: Clean up formatting of a few comments.
314 (value_fpr): Reformat switch statement.
315
cfe9ea23
CD		 3162002-06-06 Chris Demetriou <cgd@broadcom.com>
317 Ed Satterthwaite <ehs@broadcom.com>
318
319 * cp1.h: New file.
320 * sim-main.h: Include cp1.h.
321 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
322 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
323 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
324 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
325 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
326 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
327 * cp1.c: Don't include sim-fpu.h; already included by
328 sim-main.h. Clean up formatting of some comments.
329 (NaN, Equal, Less): Remove.
330 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
331 (fp_cmp): New functions.
332 * mips.igen (do_c_cond_fmt): Remove.
333 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
334 Compare. Add result tracing.
335 (CxC1): Remove, replace with...
336 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
337 (DMxC1): Remove, replace with...
338 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
339 (MxC1): Remove, replace with...
340 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
341
ee7254b0
CD		 3422002-06-04 Chris Demetriou <cgd@broadcom.com>
343
344 * sim-main.h (FGRIDX): Remove, replace all uses with...
345 (FGR_BASE): New macro.
346 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
347 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
348 (NR_FGR, FGR): Likewise.
349 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
350 * mips.igen: Likewise.
351
d3eb724f
CD		 3522002-06-04 Chris Demetriou <cgd@broadcom.com>
353
354 * cp1.c: Add an FSF Copyright notice to this file.
355
ba46ddd0
CD		 3562002-06-04 Chris Demetriou <cgd@broadcom.com>
357 Ed Satterthwaite <ehs@broadcom.com>
358
359 * cp1.c (Infinity): Remove.
360 * sim-main.h (Infinity): Likewise.
361
362 * cp1.c (fp_unary, fp_binary): New functions.
363 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
364 (fp_sqrt): New functions, implemented in terms of the above.
365 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
366 (Recip, SquareRoot): Remove (replaced by functions above).
367 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
368 (fp_recip, fp_sqrt): New prototypes.
369 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
370 (Recip, SquareRoot): Replace prototypes with #defines which
371 invoke the functions above.
372
18d8a52d
CD		 3732002-06-03 Chris Demetriou <cgd@broadcom.com>
374
375 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
376 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
377 file, remove PARAMS from prototypes.
378 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
379 simulator state arguments.
380 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
381 pass simulator state arguments.
382 * cp1.c (SD): Redefine as CPU_STATE(cpu).
383 (store_fpr, convert): Remove 'sd' argument.
384 (value_fpr): Likewise. Convert to use 'SD' instead.
385
0f154cbd
CD		 3862002-06-03 Chris Demetriou <cgd@broadcom.com>
387
388 * cp1.c (Min, Max): Remove #if 0'd functions.
389 * sim-main.h (Min, Max): Remove.
390
e80fc152
CD		 3912002-06-03 Chris Demetriou <cgd@broadcom.com>
392
393 * cp1.c: fix formatting of switch case and default labels.
394 * interp.c: Likewise.
395 * sim-main.c: Likewise.
396
bad673a9
CD		 3972002-06-03 Chris Demetriou <cgd@broadcom.com>
398
399 * cp1.c: Clean up comments which describe FP formats.
400 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
401
7cbea089
CD		 4022002-06-03 Chris Demetriou <cgd@broadcom.com>
403 Ed Satterthwaite <ehs@broadcom.com>
404
405 * configure.in (mipsisa64sb1*-*-*): New target for supporting
406 Broadcom SiByte SB-1 processor configurations.
407 * configure: Regenerate.
408 * sb1.igen: New file.
409 * mips.igen: Include sb1.igen.
410 (sb1): New model.
411 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
412 * mdmx.igen: Add "sb1" model to all appropriate functions and
413 instructions.
414 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
415 (ob_func, ob_acc): Reference the above.
416 (qh_acc): Adjust to keep the same size as ob_acc.
417 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
418 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
419
909daa82
CD		 4202002-06-03 Chris Demetriou <cgd@broadcom.com>
421
422 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
423
f4f1b9f1
CD		 4242002-06-02 Chris Demetriou <cgd@broadcom.com>
425 Ed Satterthwaite <ehs@broadcom.com>
426
427 * mips.igen (mdmx): New (pseudo-)model.
428 * mdmx.c, mdmx.igen: New files.
429 * Makefile.in (SIM_OBJS): Add mdmx.o.
430 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
431 New typedefs.
432 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
433 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
434 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
435 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
436 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
437 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
438 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
439 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
440 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
441 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
442 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
443 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
444 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
445 (qh_fmtsel): New macros.
446 (_sim_cpu): New member "acc".
447 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
448 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
449
5accf1ff
CD		 4502002-05-01 Chris Demetriou <cgd@broadcom.com>
451
452 * interp.c: Use 'deprecated' rather than 'depreciated.'
453 * sim-main.h: Likewise.
454
402586aa
CD		 4552002-05-01 Chris Demetriou <cgd@broadcom.com>
456
457 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
458 which wouldn't compile anyway.
459 * sim-main.h (unpredictable_action): New function prototype.
460 (Unpredictable): Define to call igen function unpredictable().
461 (NotWordValue): New macro to call igen function not_word_value().
462 (UndefinedResult): Remove.
463 * interp.c (undefined_result): Remove.
464 (unpredictable_action): New function.
465 * mips.igen (not_word_value, unpredictable): New functions.
466 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
467 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
468 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
469 NotWordValue() to check for unpredictable inputs, then
470 Unpredictable() to handle them.
471
c9b9995a
CD		 4722002-02-24 Chris Demetriou <cgd@broadcom.com>
473
474 * mips.igen: Fix formatting of calls to Unpredictable().
475
e1015982
AC		 4762002-04-20 Andrew Cagney <ac131313@redhat.com>
477
478 * interp.c (sim_open): Revert previous change.
479
b882a66b
AO		 4802002-04-18 Alexandre Oliva <aoliva@redhat.com>
481
482 * interp.c (sim_open): Disable chunk of code that wrote code in
483 vector table entries.
484
c429b7dd
CD		 4852002-03-19 Chris Demetriou <cgd@broadcom.com>
486
487 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
488 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
489 unused definitions.
490
37d146fa
CD		 4912002-03-19 Chris Demetriou <cgd@broadcom.com>
492
493 * cp1.c: Fix many formatting issues.
494
07892c0b
CD		 4952002-03-19 Chris G. Demetriou <cgd@broadcom.com>
496
497 * cp1.c (fpu_format_name): New function to replace...
498 (DOFMT): This. Delete, and update all callers.
499 (fpu_rounding_mode_name): New function to replace...
500 (RMMODE): This. Delete, and update all callers.
501
487f79b7
CD		 5022002-03-19 Chris G. Demetriou <cgd@broadcom.com>
503
504 * interp.c: Move FPU support routines from here to...
505 * cp1.c: Here. New file.
506 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
507 (cp1.o): New target.
508
1e799e28
CD		 5092002-03-12 Chris Demetriou <cgd@broadcom.com>
510
511 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
512 * mips.igen (mips32, mips64): New models, add to all instructions
513 and functions as appropriate.
514 (loadstore_ea, check_u64): New variant for model mips64.
515 (check_fmt_p): New variant for models mipsV and mips64, remove
516 mipsV model marking fro other variant.
517 (SLL) Rename to...
518 (SLLa) this.
519 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
520 for mips32 and mips64.
521 (DCLO, DCLZ): New instructions for mips64.
522
82f728db
CD		 5232002-03-07 Chris Demetriou <cgd@broadcom.com>
524
525 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
526 immediate or code as a hex value with the "%#lx" format.
527 (ANDI): Likewise, and fix printed instruction name.
528
b96e7ef1
CD		 5292002-03-05 Chris Demetriou <cgd@broadcom.com>
530
531 * sim-main.h (UndefinedResult, Unpredictable): New macros
532 which currently do nothing.
533
d35d4f70
CD		 5342002-03-05 Chris Demetriou <cgd@broadcom.com>
535
536 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
537 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
538 (status_CU3): New definitions.
539
540 * sim-main.h (ExceptionCause): Add new values for MIPS32
541 and MIPS64: MDMX, MCheck, CacheErr. Update comments
542 for DebugBreakPoint and NMIReset to note their status in
543 MIPS32 and MIPS64.
544 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
545 (SignalExceptionCacheErr): New exception macros.
546
3ad6f714
CD		 5472002-03-05 Chris Demetriou <cgd@broadcom.com>
548
549 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
550 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
551 is always enabled.
552 (SignalExceptionCoProcessorUnusable): Take as argument the
553 unusable coprocessor number.
554
86b77b47
CD		 5552002-03-05 Chris Demetriou <cgd@broadcom.com>
556
557 * mips.igen: Fix formatting of all SignalException calls.
558
97a88e93 5592002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 560
561 * sim-main.h (SIGNEXTEND): Remove.
562
97a88e93 5632002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 564
565 * mips.igen: Remove gencode comment from top of file, fix
566 spelling in another comment.
567
97a88e93 5682002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 569
570 * mips.igen (check_fmt, check_fmt_p): New functions to check
571 whether specific floating point formats are usable.
572 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
573 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
574 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
575 Use the new functions.
576 (do_c_cond_fmt): Remove format checks...
577 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
578
97a88e93 5792002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 580
581 * mips.igen: Fix formatting of check_fpu calls.
582
41774c9d
CD		 5832002-03-03 Chris Demetriou <cgd@broadcom.com>
584
585 * mips.igen (FLOOR.L.fmt): Store correct destination register.
586
4a0bd876
CD		 5872002-03-03 Chris Demetriou <cgd@broadcom.com>
588
589 * mips.igen: Remove whitespace at end of lines.
590
09297648
CD		 5912002-03-02 Chris Demetriou <cgd@broadcom.com>
592
593 * mips.igen (loadstore_ea): New function to do effective
594 address calculations.
595 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
596 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
597 CACHE): Use loadstore_ea to do effective address computations.
598
043b7057
CD		 5992002-03-02 Chris Demetriou <cgd@broadcom.com>
600
601 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
602 * mips.igen (LL, CxC1, MxC1): Likewise.
603
c1e8ada4
CD		 6042002-03-02 Chris Demetriou <cgd@broadcom.com>
605
606 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
607 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
608 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
609 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
610 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
611 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
612 Don't split opcode fields by hand, use the opcode field values
613 provided by igen.
614
3e1dca16
CD		 6152002-03-01 Chris Demetriou <cgd@broadcom.com>
616
617 * mips.igen (do_divu): Fix spacing.
618
619 * mips.igen (do_dsllv): Move to be right before DSLLV,
620 to match the rest of the do_<shift> functions.
621
fff8d27d
CD		 6222002-03-01 Chris Demetriou <cgd@broadcom.com>
623
624 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
625 DSRL32, do_dsrlv): Trace inputs and results.
626
0d3e762b
CD		 6272002-03-01 Chris Demetriou <cgd@broadcom.com>
628
629 * mips.igen (CACHE): Provide instruction-printing string.
630
631 * interp.c (signal_exception): Comment tokens after #endif.
632
eb5fcf93
CD		 6332002-02-28 Chris Demetriou <cgd@broadcom.com>
634
635 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
636 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
637 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
638 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
639 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
640 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
641 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
642 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
643
bb22bd7d
CD		 6442002-02-28 Chris Demetriou <cgd@broadcom.com>
645
646 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
647 instruction-printing string.
648 (LWU): Use '64' as the filter flag.
649
91a177cf
CD		 6502002-02-28 Chris Demetriou <cgd@broadcom.com>
651
652 * mips.igen (SDXC1): Fix instruction-printing string.
653
387f484a
CD		 6542002-02-28 Chris Demetriou <cgd@broadcom.com>
655
656 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
657 filter flags "32,f".
658
3d81f391
CD		 6592002-02-27 Chris Demetriou <cgd@broadcom.com>
660
661 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
662 as the filter flag.
663
af5107af
CD		 6642002-02-27 Chris Demetriou <cgd@broadcom.com>
665
666 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
667 add a comma) so that it more closely match the MIPS ISA
668 documentation opcode partitioning.
669 (PREF): Put useful names on opcode fields, and include
670 instruction-printing string.
671
ca971540
CD		 6722002-02-27 Chris Demetriou <cgd@broadcom.com>
673
674 * mips.igen (check_u64): New function which in the future will
675 check whether 64-bit instructions are usable and signal an
676 exception if not. Currently a no-op.
677 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
678 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
679 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
680 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
681
682 * mips.igen (check_fpu): New function which in the future will
683 check whether FPU instructions are usable and signal an exception
684 if not. Currently a no-op.
685 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
686 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
687 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
688 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
689 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
690 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
691 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
692 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
693
1c47a468
CD		 6942002-02-27 Chris Demetriou <cgd@broadcom.com>
695
696 * mips.igen (do_load_left, do_load_right): Move to be immediately
697 following do_load.
698 (do_store_left, do_store_right): Move to be immediately following
699 do_store.
700
603a98e7
CD		 7012002-02-27 Chris Demetriou <cgd@broadcom.com>
702
703 * mips.igen (mipsV): New model name. Also, add it to
704 all instructions and functions where it is appropriate.
705
c5d00cc7
CD		 7062002-02-18 Chris Demetriou <cgd@broadcom.com>
707
708 * mips.igen: For all functions and instructions, list model
709 names that support that instruction one per line.
710
074e9cb8
CD		 7112002-02-11 Chris Demetriou <cgd@broadcom.com>
712
713 * mips.igen: Add some additional comments about supported
714 models, and about which instructions go where.
715 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
716 order as is used in the rest of the file.
717
9805e229
CD		 7182002-02-11 Chris Demetriou <cgd@broadcom.com>
719
720 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
721 indicating that ALU32_END or ALU64_END are there to check
722 for overflow.
723 (DADD): Likewise, but also remove previous comment about
724 overflow checking.
725
f701dad2
CD		 7262002-02-10 Chris Demetriou <cgd@broadcom.com>
727
728 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
729 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
730 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
731 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
732 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
733 fields (i.e., add and move commas) so that they more closely
734 match the MIPS ISA documentation opcode partitioning.
735
7362002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098
CD		 737
738 * mips.igen (ADDI): Print immediate value.
739 (BREAK): Print code.
740 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
741 (SLL): Print "nop" specially, and don't run the code
742 that does the shift for the "nop" case.
743
9e52972e
FF		 7442001-11-17 Fred Fish <fnf@redhat.com>
745
746 * sim-main.h (float_operation): Move enum declaration outside
747 of _sim_cpu struct declaration.
748
c0efbca4
JB		 7492001-04-12 Jim Blandy <jimb@redhat.com>
750
751 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
752 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
753 set of the FCSR.
754 * sim-main.h (COCIDX): Remove definition; this isn't supported by
755 PENDING_FILL, and you can get the intended effect gracefully by
756 calling PENDING_SCHED directly.
757
fb891446
BE		 7582001-02-23 Ben Elliston <bje@redhat.com>
759
760 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
761 already defined elsewhere.
762
8030f857
BE		 7632001-02-19 Ben Elliston <bje@redhat.com>
764
765 * sim-main.h (sim_monitor): Return an int.
766 * interp.c (sim_monitor): Add return values.
767 (signal_exception): Handle error conditions from sim_monitor.
768
56b48a7a
CD		 7692001-02-08 Ben Elliston <bje@redhat.com>
770
771 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
772 (store_memory): Likewise, pass cia to sim_core_write*.
773
d3ee60d9
FCE		 7742000-10-19 Frank Ch. Eigler <fche@redhat.com>
775
776 On advice from Chris G. Demetriou <cgd@sibyte.com>:
777 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
778
071da002
AC		 779Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
780
781 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
782 * Makefile.in: Don't delete *.igen when cleaning directory.
783
a28c02cd
AC		 784Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
785
786 * m16.igen (break): Call SignalException not sim_engine_halt.
787
80ee11fa
AC		 788Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
789
790 From Jason Eckhardt:
791 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
792
673388c0
AC		 793Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
794
795 * mips.igen (MxC1, DMxC1): Fix printf formatting.
796
4c0deff4
NC		 7972000-05-24 Michael Hayes <mhayes@cygnus.com>
798
799 * mips.igen (do_dmultx): Fix typo.
800
eb2d80b4
AC		 801Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
802
803 * configure: Regenerated to track ../common/aclocal.m4 changes.
804
dd37a34b
AC		 805Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
806
807 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
808
4c0deff4
NC		 8092000-04-12 Frank Ch. Eigler <fche@redhat.com>
810
811 * sim-main.h (GPR_CLEAR): Define macro.
812
e30db738
AC		 813Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
814
815 * interp.c (decode_coproc): Output long using %lx and not %s.
816
cb7450ea
FCE		 8172000-03-21 Frank Ch. Eigler <fche@redhat.com>
818
819 * interp.c (sim_open): Sort & extend dummy memory regions for
820 --board=jmr3904 for eCos.
821
a3027dd7
FCE		 8222000-03-02 Frank Ch. Eigler <fche@redhat.com>
823
824 * configure: Regenerated.
825
826Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
827
828 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
829 calls, conditional on the simulator being in verbose mode.
830
dfcd3bfb
JM		 831Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
832
833 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
834 cache don't get ReservedInstruction traps.
835
c2d11a7d
JM		 8361999-11-29 Mark Salter <msalter@cygnus.com>
837
838 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
839 to clear status bits in sdisr register. This is how the hardware works.
840
841 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
842 being used by cygmon.
843
4ce44c66
JM		 8441999-11-11 Andrew Haley <aph@cygnus.com>
845
846 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
847 instructions.
848
cff3e48b
JM		 849Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
850
851 * mips.igen (MULT): Correct previous mis-applied patch.
852
d4f3574e
SS		 853Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
854
855 * mips.igen (delayslot32): Handle sequence like
856 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
857 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
858 (MULT): Actually pass the third register...
859
8601999-09-03 Mark Salter <msalter@cygnus.com>
861
862 * interp.c (sim_open): Added more memory aliases for additional
863 hardware being touched by cygmon on jmr3904 board.
864
865Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
866
867 * configure: Regenerated to track ../common/aclocal.m4 changes.
868
a0b3c4fd
JM		 869Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
870
871 * interp.c (sim_store_register): Handle case where client - GDB -
872 specifies that a 4 byte register is 8 bytes in size.
873 (sim_fetch_register): Ditto.
874
adf40b2e
JM		 8751999-07-14 Frank Ch. Eigler <fche@cygnus.com>
876
877 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
878 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
879 (idt_monitor_base): Base address for IDT monitor traps.
880 (pmon_monitor_base): Ditto for PMON.
881 (lsipmon_monitor_base): Ditto for LSI PMON.
882 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
883 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
884 (sim_firmware_command): New function.
885 (mips_option_handler): Call it for OPTION_FIRMWARE.
886 (sim_open): Allocate memory for idt_monitor region. If "--board"
887 option was given, add no monitor by default. Add BREAK hooks only if
888 monitors are also there.
889
43e526b9
JM		 890Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
891
892 * interp.c (sim_monitor): Flush output before reading input.
893
894Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
895
896 * tconfig.in (SIM_HANDLES_LMA): Always define.
897
898Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
899
900 From Mark Salter <msalter@cygnus.com>:
901 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
902 (sim_open): Add setup for BSP board.
903
9846de1b
JM		 904Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
905
906 * mips.igen (MULT, MULTU): Add syntax for two operand version.
907 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
908 them as unimplemented.
909
cd0fc7c3
SS		 9101999-05-08 Felix Lee <flee@cygnus.com>
911
912 * configure: Regenerated to track ../common/aclocal.m4 changes.
913
7a292a7a
SS		 9141999-04-21 Frank Ch. Eigler <fche@cygnus.com>
915
916 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
917
918Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
919
920 * configure.in: Any mips64vr5*-*-* target should have
921 -DTARGET_ENABLE_FR=1.
922 (default_endian): Any mips64vr*el-*-* target should default to
923 LITTLE_ENDIAN.
924 * configure: Re-generate.
925
9261999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
927
928 * mips.igen (ldl): Extend from _16_, not 32.
929
930Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
931
932 * interp.c (sim_store_register): Force registers written to by GDB
933 into an un-interpreted state.
934
c906108c
SS		 9351999-02-05 Frank Ch. Eigler <fche@cygnus.com>
936
937 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
938 CPU, start periodic background I/O polls.
939 (tx3904sio_poll): New function: periodic I/O poller.
940
9411998-12-30 Frank Ch. Eigler <fche@cygnus.com>
942
943 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
944
945Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
946
947 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
948 case statement.
949
9501998-12-29 Frank Ch. Eigler <fche@cygnus.com>
951
952 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
953 (load_word): Call SIM_CORE_SIGNAL hook on error.
954 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
955 starting. For exception dispatching, pass PC instead of NULL_CIA.
956 (decode_coproc): Use COP0_BADVADDR to store faulting address.
957 * sim-main.h (COP0_BADVADDR): Define.
958 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
959 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
960 (_sim_cpu): Add exc_* fields to store register value snapshots.
961 * mips.igen (*): Replace memory-related SignalException* calls
962 with references to SIM_CORE_SIGNAL hook.
963
964 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
965 fix.
966 * sim-main.c (*): Minor warning cleanups.
967
9681998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
969
970 * m16.igen (DADDIU5): Correct type-o.
971
972Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
973
974 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
975 variables.
976
977Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
978
979 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
980 to include path.
981 (interp.o): Add dependency on itable.h
982 (oengine.c, gencode): Delete remaining references.
983 (BUILT_SRC_FROM_GEN): Clean up.
984
9851998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
986
987 * vr4run.c: New.
988 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
989 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
990 tmp-run-hack) : New.
991 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
992 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
993 Drop the "64" qualifier to get the HACK generator working.
994 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
995 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
996 qualifier to get the hack generator working.
997 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
998 (DSLL): Use do_dsll.
999 (DSLLV): Use do_dsllv.
1000 (DSRA): Use do_dsra.
1001 (DSRL): Use do_dsrl.
1002 (DSRLV): Use do_dsrlv.
1003 (BC1): Move *vr4100 to get the HACK generator working.
1004 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
1005 get the HACK generator working.
1006 (MACC) Rename to get the HACK generator working.
1007 (DMACC,MACCS,DMACCS): Add the 64.
1008
10091998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1010
1011 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1012 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1013
10141998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1015
1016 * mips/interp.c (DEBUG): Cleanups.
1017
10181998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1019
1020 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1021 (tx3904sio_tickle): fflush after a stdout character output.
1022
10231998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1024
1025 * interp.c (sim_close): Uninstall modules.
1026
1027Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1028
1029 * sim-main.h, interp.c (sim_monitor): Change to global
1030 function.
1031
1032Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1033
1034 * configure.in (vr4100): Only include vr4100 instructions in
1035 simulator.
1036 * configure: Re-generate.
1037 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1038
1039Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1040
1041 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1042 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1043 true alternative.
1044
1045 * configure.in (sim_default_gen, sim_use_gen): Replace with
1046 sim_gen.
1047 (--enable-sim-igen): Delete config option. Always using IGEN.
1048 * configure: Re-generate.
1049
1050 * Makefile.in (gencode): Kill, kill, kill.
1051 * gencode.c: Ditto.
1052
1053Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1054
1055 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1056 bit mips16 igen simulator.
1057 * configure: Re-generate.
1058
1059 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1060 as part of vr4100 ISA.
1061 * vr.igen: Mark all instructions as 64 bit only.
1062
1063Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1064
1065 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1066 Pacify GCC.
1067
1068Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1069
1070 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1071 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1072 * configure: Re-generate.
1073
1074 * m16.igen (BREAK): Define breakpoint instruction.
1075 (JALX32): Mark instruction as mips16 and not r3900.
1076 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1077
1078 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1079
1080Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1081
1082 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1083 insn as a debug breakpoint.
1084
1085 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1086 pending.slot_size.
1087 (PENDING_SCHED): Clean up trace statement.
1088 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1089 (PENDING_FILL): Delay write by only one cycle.
1090 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1091
1092 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1093 of pending writes.
1094 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1095 32 & 64.
1096 (pending_tick): Move incrementing of index to FOR statement.
1097 (pending_tick): Only update PENDING_OUT after a write has occured.
1098
1099 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1100 build simulator.
1101 * configure: Re-generate.
1102
1103 * interp.c (sim_engine_run OLD): Delete explicit call to
1104 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1105
1106Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1107
1108 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1109 interrupt level number to match changed SignalExceptionInterrupt
1110 macro.
1111
1112Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1113
1114 * interp.c: #include "itable.h" if WITH_IGEN.
1115 (get_insn_name): New function.
1116 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1117 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1118
1119Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1120
1121 * configure: Rebuilt to inhale new common/aclocal.m4.
1122
1123Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1124
1125 * dv-tx3904sio.c: Include sim-assert.h.
1126
1127Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1128
1129 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1130 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1131 Reorganize target-specific sim-hardware checks.
1132 * configure: rebuilt.
1133 * interp.c (sim_open): For tx39 target boards, set
1134 OPERATING_ENVIRONMENT, add tx3904sio devices.
1135 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1136 ROM executables. Install dv-sockser into sim-modules list.
1137
1138 * dv-tx3904irc.c: Compiler warning clean-up.
1139 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1140 frequent hw-trace messages.
1141
1142Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1143
1144 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1145
1146Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1147
1148 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1149
1150 * vr.igen: New file.
1151 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1152 * mips.igen: Define vr4100 model. Include vr.igen.
1153Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1154
1155 * mips.igen (check_mf_hilo): Correct check.
1156
1157Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1158
1159 * sim-main.h (interrupt_event): Add prototype.
1160
1161 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1162 register_ptr, register_value.
1163 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1164
1165 * sim-main.h (tracefh): Make extern.
1166
1167Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1168
1169 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1170 Reduce unnecessarily high timer event frequency.
1171 * dv-tx3904cpu.c: Ditto for interrupt event.
1172
1173Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1174
1175 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1176 to allay warnings.
1177 (interrupt_event): Made non-static.
1178
1179 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1180 interchange of configuration values for external vs. internal
1181 clock dividers.
1182
1183Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1184
1185 * mips.igen (BREAK): Moved code to here for
1186 simulator-reserved break instructions.
1187 * gencode.c (build_instruction): Ditto.
1188 * interp.c (signal_exception): Code moved from here. Non-
1189 reserved instructions now use exception vector, rather
1190 than halting sim.
1191 * sim-main.h: Moved magic constants to here.
1192
1193Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1194
1195 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1196 register upon non-zero interrupt event level, clear upon zero
1197 event value.
1198 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1199 by passing zero event value.
1200 (*_io_{read,write}_buffer): Endianness fixes.
1201 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1202 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1203
1204 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1205 serial I/O and timer module at base address 0xFFFF0000.
1206
1207Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1208
1209 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1210 and BigEndianCPU.
1211
1212Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1213
1214 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1215 parts.
1216 * configure: Update.
1217
1218Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1219
1220 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1221 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1222 * configure.in: Include tx3904tmr in hw_device list.
1223 * configure: Rebuilt.
1224 * interp.c (sim_open): Instantiate three timer instances.
1225 Fix address typo of tx3904irc instance.
1226
1227Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1228
1229 * interp.c (signal_exception): SystemCall exception now uses
1230 the exception vector.
1231
1232Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1233
1234 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1235 to allay warnings.
1236
1237Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1238
1239 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1240
1241Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1242
1243 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1244
1245 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1246 sim-main.h. Declare a struct hw_descriptor instead of struct
1247 hw_device_descriptor.
1248
1249Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1250
1251 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1252 right bits and then re-align left hand bytes to correct byte
1253 lanes. Fix incorrect computation in do_store_left when loading
1254 bytes from second word.
1255
1256Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1257
1258 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1259 * interp.c (sim_open): Only create a device tree when HW is
1260 enabled.
1261
1262 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1263 * interp.c (signal_exception): Ditto.
1264
1265Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1266
1267 * gencode.c: Mark BEGEZALL as LIKELY.
1268
1269Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1270
1271 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1272 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1273
1274Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1275
1276 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1277 modules. Recognize TX39 target with "mips*tx39" pattern.
1278 * configure: Rebuilt.
1279 * sim-main.h (*): Added many macros defining bits in
1280 TX39 control registers.
1281 (SignalInterrupt): Send actual PC instead of NULL.
1282 (SignalNMIReset): New exception type.
1283 * interp.c (board): New variable for future use to identify
1284 a particular board being simulated.
1285 (mips_option_handler,mips_options): Added "--board" option.
1286 (interrupt_event): Send actual PC.
1287 (sim_open): Make memory layout conditional on board setting.
1288 (signal_exception): Initial implementation of hardware interrupt
1289 handling. Accept another break instruction variant for simulator
1290 exit.
1291 (decode_coproc): Implement RFE instruction for TX39.
1292 (mips.igen): Decode RFE instruction as such.
1293 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1294 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1295 bbegin to implement memory map.
1296 * dv-tx3904cpu.c: New file.
1297 * dv-tx3904irc.c: New file.
1298
1299Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1300
1301 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1302
1303Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1304
1305 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1306 with calls to check_div_hilo.
1307
1308Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1309
1310 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1311 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1312 Add special r3900 version of do_mult_hilo.
1313 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1314 with calls to check_mult_hilo.
1315 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1316 with calls to check_div_hilo.
1317
1318Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1319
1320 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1321 Document a replacement.
1322
1323Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1324
1325 * interp.c (sim_monitor): Make mon_printf work.
1326
1327Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1328
1329 * sim-main.h (INSN_NAME): New arg `cpu'.
1330
1331Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1332
1333 * configure: Regenerated to track ../common/aclocal.m4 changes.
1334
1335Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1336
1337 * configure: Regenerated to track ../common/aclocal.m4 changes.
1338 * config.in: Ditto.
1339
1340Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1341
1342 * acconfig.h: New file.
1343 * configure.in: Reverted change of Apr 24; use sinclude again.
1344
1345Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1346
1347 * configure: Regenerated to track ../common/aclocal.m4 changes.
1348 * config.in: Ditto.
1349
1350Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1351
1352 * configure.in: Don't call sinclude.
1353
1354Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1355
1356 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1357
1358Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1359
1360 * mips.igen (ERET): Implement.
1361
1362 * interp.c (decode_coproc): Return sign-extended EPC.
1363
1364 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1365
1366 * interp.c (signal_exception): Do not ignore Trap.
1367 (signal_exception): On TRAP, restart at exception address.
1368 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1369 (signal_exception): Update.
1370 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1371 so that TRAP instructions are caught.
1372
1373Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1374
1375 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1376 contains HI/LO access history.
1377 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1378 (HIACCESS, LOACCESS): Delete, replace with
1379 (HIHISTORY, LOHISTORY): New macros.
1380 (CHECKHILO): Delete all, moved to mips.igen
1381
1382 * gencode.c (build_instruction): Do not generate checks for
1383 correct HI/LO register usage.
1384
1385 * interp.c (old_engine_run): Delete checks for correct HI/LO
1386 register usage.
1387
1388 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1389 check_mf_cycles): New functions.
1390 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1391 do_divu, domultx, do_mult, do_multu): Use.
1392
1393 * tx.igen ("madd", "maddu"): Use.
1394
1395Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1396
1397 * mips.igen (DSRAV): Use function do_dsrav.
1398 (SRAV): Use new function do_srav.
1399
1400 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1401 (B): Sign extend 11 bit immediate.
1402 (EXT-B*): Shift 16 bit immediate left by 1.
1403 (ADDIU*): Don't sign extend immediate value.
1404
1405Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1406
1407 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1408
1409 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1410 functions.
1411
1412 * mips.igen (delayslot32, nullify_next_insn): New functions.
1413 (m16.igen): Always include.
1414 (do_*): Add more tracing.
1415
1416 * m16.igen (delayslot16): Add NIA argument, could be called by a
1417 32 bit MIPS16 instruction.
1418
1419 * interp.c (ifetch16): Move function from here.
1420 * sim-main.c (ifetch16): To here.
1421
1422 * sim-main.c (ifetch16, ifetch32): Update to match current
1423 implementations of LH, LW.
1424 (signal_exception): Don't print out incorrect hex value of illegal
1425 instruction.
1426
1427Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1428
1429 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1430 instruction.
1431
1432 * m16.igen: Implement MIPS16 instructions.
1433
1434 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1435 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1436 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1437 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1438 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1439 bodies of corresponding code from 32 bit insn to these. Also used
1440 by MIPS16 versions of functions.
1441
1442 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1443 (IMEM16): Drop NR argument from macro.
1444
1445Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1446
1447 * Makefile.in (SIM_OBJS): Add sim-main.o.
1448
1449 * sim-main.h (address_translation, load_memory, store_memory,
1450 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1451 as INLINE_SIM_MAIN.
1452 (pr_addr, pr_uword64): Declare.
1453 (sim-main.c): Include when H_REVEALS_MODULE_P.
1454
1455 * interp.c (address_translation, load_memory, store_memory,
1456 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1457 from here.
1458 * sim-main.c: To here. Fix compilation problems.
1459
1460 * configure.in: Enable inlining.
1461 * configure: Re-config.
1462
1463Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1464
1465 * configure: Regenerated to track ../common/aclocal.m4 changes.
1466
1467Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1468
1469 * mips.igen: Include tx.igen.
1470 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1471 * tx.igen: New file, contains MADD and MADDU.
1472
1473 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1474 the hardwired constant `7'.
1475 (store_memory): Ditto.
1476 (LOADDRMASK): Move definition to sim-main.h.
1477
1478 mips.igen (MTC0): Enable for r3900.
1479 (ADDU): Add trace.
1480
1481 mips.igen (do_load_byte): Delete.
1482 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1483 do_store_right): New functions.
1484 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1485
1486 configure.in: Let the tx39 use igen again.
1487 configure: Update.
1488
1489Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1490
1491 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1492 not an address sized quantity. Return zero for cache sizes.
1493
1494Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1495
1496 * mips.igen (r3900): r3900 does not support 64 bit integer
1497 operations.
1498
1499Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1500
1501 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1502 than igen one.
1503 * configure : Rebuild.
1504
1505Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1506
1507 * configure: Regenerated to track ../common/aclocal.m4 changes.
1508
1509Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1510
1511 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1512
1513Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1514
1515 * configure: Regenerated to track ../common/aclocal.m4 changes.
1516 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1517
1518Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1519
1520 * configure: Regenerated to track ../common/aclocal.m4 changes.
1521
1522Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1523
1524 * interp.c (Max, Min): Comment out functions. Not yet used.
1525
1526Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1527
1528 * configure: Regenerated to track ../common/aclocal.m4 changes.
1529
1530Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1531
1532 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1533 configurable settings for stand-alone simulator.
1534
1535 * configure.in: Added X11 search, just in case.
1536
1537 * configure: Regenerated.
1538
1539Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1540
1541 * interp.c (sim_write, sim_read, load_memory, store_memory):
1542 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1543
1544Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1545
1546 * sim-main.h (GETFCC): Return an unsigned value.
1547
1548Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1549
1550 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1551 (DADD): Result destination is RD not RT.
1552
1553Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1554
1555 * sim-main.h (HIACCESS, LOACCESS): Always define.
1556
1557 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1558
1559 * interp.c (sim_info): Delete.
1560
1561Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1562
1563 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1564 (mips_option_handler): New argument `cpu'.
1565 (sim_open): Update call to sim_add_option_table.
1566
1567Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1568
1569 * mips.igen (CxC1): Add tracing.
1570
1571Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1572
1573 * sim-main.h (Max, Min): Declare.
1574
1575 * interp.c (Max, Min): New functions.
1576
1577 * mips.igen (BC1): Add tracing.
1578
1579Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1580
1581 * interp.c Added memory map for stack in vr4100
1582
1583Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1584
1585 * interp.c (load_memory): Add missing "break"'s.
1586
1587Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1588
1589 * interp.c (sim_store_register, sim_fetch_register): Pass in
1590 length parameter. Return -1.
1591
1592Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1593
1594 * interp.c: Added hardware init hook, fixed warnings.
1595
1596Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1597
1598 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1599
1600Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1601
1602 * interp.c (ifetch16): New function.
1603
1604 * sim-main.h (IMEM32): Rename IMEM.
1605 (IMEM16_IMMED): Define.
1606 (IMEM16): Define.
1607 (DELAY_SLOT): Update.
1608
1609 * m16run.c (sim_engine_run): New file.
1610
1611 * m16.igen: All instructions except LB.
1612 (LB): Call do_load_byte.
1613 * mips.igen (do_load_byte): New function.
1614 (LB): Call do_load_byte.
1615
1616 * mips.igen: Move spec for insn bit size and high bit from here.
1617 * Makefile.in (tmp-igen, tmp-m16): To here.
1618
1619 * m16.dc: New file, decode mips16 instructions.
1620
1621 * Makefile.in (SIM_NO_ALL): Define.
1622 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1623
1624Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1625
1626 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1627 point unit to 32 bit registers.
1628 * configure: Re-generate.
1629
1630Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1631
1632 * configure.in (sim_use_gen): Make IGEN the default simulator
1633 generator for generic 32 and 64 bit mips targets.
1634 * configure: Re-generate.
1635
1636Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1637
1638 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1639 bitsize.
1640
1641 * interp.c (sim_fetch_register, sim_store_register): Read/write
1642 FGR from correct location.
1643 (sim_open): Set size of FGR's according to
1644 WITH_TARGET_FLOATING_POINT_BITSIZE.
1645
1646 * sim-main.h (FGR): Store floating point registers in a separate
1647 array.
1648
1649Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1650
1651 * configure: Regenerated to track ../common/aclocal.m4 changes.
1652
1653Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1654
1655 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1656
1657 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1658
1659 * interp.c (pending_tick): New function. Deliver pending writes.
1660
1661 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1662 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1663 it can handle mixed sized quantites and single bits.
1664
1665Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1666
1667 * interp.c (oengine.h): Do not include when building with IGEN.
1668 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1669 (sim_info): Ditto for PROCESSOR_64BIT.
1670 (sim_monitor): Replace ut_reg with unsigned_word.
1671 (*): Ditto for t_reg.
1672 (LOADDRMASK): Define.
1673 (sim_open): Remove defunct check that host FP is IEEE compliant,
1674 using software to emulate floating point.
1675 (value_fpr, ...): Always compile, was conditional on HASFPU.
1676
1677Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1678
1679 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1680 size.
1681
1682 * interp.c (SD, CPU): Define.
1683 (mips_option_handler): Set flags in each CPU.
1684 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1685 (sim_close): Do not clear STATE, deleted anyway.
1686 (sim_write, sim_read): Assume CPU zero's vm should be used for
1687 data transfers.
1688 (sim_create_inferior): Set the PC for all processors.
1689 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1690 argument.
1691 (mips16_entry): Pass correct nr of args to store_word, load_word.
1692 (ColdReset): Cold reset all cpu's.
1693 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1694 (sim_monitor, load_memory, store_memory, signal_exception): Use
1695 `CPU' instead of STATE_CPU.
1696
1697
1698 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1699 SD or CPU_.
1700
1701 * sim-main.h (signal_exception): Add sim_cpu arg.
1702 (SignalException*): Pass both SD and CPU to signal_exception.
1703 * interp.c (signal_exception): Update.
1704
1705 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1706 Ditto
1707 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1708 address_translation): Ditto
1709 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1710
1711Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1712
1713 * configure: Regenerated to track ../common/aclocal.m4 changes.
1714
1715Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1716
1717 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1718
1719 * mips.igen (model): Map processor names onto BFD name.
1720
1721 * sim-main.h (CPU_CIA): Delete.
1722 (SET_CIA, GET_CIA): Define
1723
1724Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1725
1726 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1727 regiser.
1728
1729 * configure.in (default_endian): Configure a big-endian simulator
1730 by default.
1731 * configure: Re-generate.
1732
1733Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1734
1735 * configure: Regenerated to track ../common/aclocal.m4 changes.
1736
1737Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1738
1739 * interp.c (sim_monitor): Handle Densan monitor outbyte
1740 and inbyte functions.
1741
17421997-12-29 Felix Lee <flee@cygnus.com>
1743
1744 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1745
1746Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1747
1748 * Makefile.in (tmp-igen): Arrange for $zero to always be
1749 reset to zero after every instruction.
1750
1751Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1752
1753 * configure: Regenerated to track ../common/aclocal.m4 changes.
1754 * config.in: Ditto.
1755
1756Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1757
1758 * mips.igen (MSUB): Fix to work like MADD.
1759 * gencode.c (MSUB): Similarly.
1760
1761Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1762
1763 * configure: Regenerated to track ../common/aclocal.m4 changes.
1764
1765Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1766
1767 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1768
1769Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1770
1771 * sim-main.h (sim-fpu.h): Include.
1772
1773 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1774 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1775 using host independant sim_fpu module.
1776
1777Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1778
1779 * interp.c (signal_exception): Report internal errors with SIGABRT
1780 not SIGQUIT.
1781
1782 * sim-main.h (C0_CONFIG): New register.
1783 (signal.h): No longer include.
1784
1785 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1786
1787Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1788
1789 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1790
1791Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1792
1793 * mips.igen: Tag vr5000 instructions.
1794 (ANDI): Was missing mipsIV model, fix assembler syntax.
1795 (do_c_cond_fmt): New function.
1796 (C.cond.fmt): Handle mips I-III which do not support CC field
1797 separatly.
1798 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1799 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1800 in IV3.2 spec.
1801 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1802 vr5000 which saves LO in a GPR separatly.
1803
1804 * configure.in (enable-sim-igen): For vr5000, select vr5000
1805 specific instructions.
1806 * configure: Re-generate.
1807
1808Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1809
1810 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1811
1812 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1813 fmt_uninterpreted_64 bit cases to switch. Convert to
1814 fmt_formatted,
1815
1816 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1817
1818 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1819 as specified in IV3.2 spec.
1820 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1821
1822Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1823
1824 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1825 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1826 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1827 PENDING_FILL versions of instructions. Simplify.
1828 (X): New function.
1829 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1830 instructions.
1831 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1832 a signed value.
1833 (MTHI, MFHI): Disable code checking HI-LO.
1834
1835 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1836 global.
1837 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1838
1839Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1840
1841 * gencode.c (build_mips16_operands): Replace IPC with cia.
1842
1843 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1844 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1845 IPC to `cia'.
1846 (UndefinedResult): Replace function with macro/function
1847 combination.
1848 (sim_engine_run): Don't save PC in IPC.
1849
1850 * sim-main.h (IPC): Delete.
1851
1852
1853 * interp.c (signal_exception, store_word, load_word,
1854 address_translation, load_memory, store_memory, cache_op,
1855 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1856 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1857 current instruction address - cia - argument.
1858 (sim_read, sim_write): Call address_translation directly.
1859 (sim_engine_run): Rename variable vaddr to cia.
1860 (signal_exception): Pass cia to sim_monitor
1861
1862 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1863 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1864 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1865
1866 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1867 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1868 SIM_ASSERT.
1869
1870 * interp.c (signal_exception): Pass restart address to
1871 sim_engine_restart.
1872
1873 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1874 idecode.o): Add dependency.
1875
1876 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1877 Delete definitions
1878 (DELAY_SLOT): Update NIA not PC with branch address.
1879 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1880
1881 * mips.igen: Use CIA not PC in branch calculations.
1882 (illegal): Call SignalException.
1883 (BEQ, ADDIU): Fix assembler.
1884
1885Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1886
1887 * m16.igen (JALX): Was missing.
1888
1889 * configure.in (enable-sim-igen): New configuration option.
1890 * configure: Re-generate.
1891
1892 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1893
1894 * interp.c (load_memory, store_memory): Delete parameter RAW.
1895 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1896 bypassing {load,store}_memory.
1897
1898 * sim-main.h (ByteSwapMem): Delete definition.
1899
1900 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1901
1902 * interp.c (sim_do_command, sim_commands): Delete mips specific
1903 commands. Handled by module sim-options.
1904
1905 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1906 (WITH_MODULO_MEMORY): Define.
1907
1908 * interp.c (sim_info): Delete code printing memory size.
1909
1910 * interp.c (mips_size): Nee sim_size, delete function.
1911 (power2): Delete.
1912 (monitor, monitor_base, monitor_size): Delete global variables.
1913 (sim_open, sim_close): Delete code creating monitor and other
1914 memory regions. Use sim-memopts module, via sim_do_commandf, to
1915 manage memory regions.
1916 (load_memory, store_memory): Use sim-core for memory model.
1917
1918 * interp.c (address_translation): Delete all memory map code
1919 except line forcing 32 bit addresses.
1920
1921Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1922
1923 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1924 trace options.
1925
1926 * interp.c (logfh, logfile): Delete globals.
1927 (sim_open, sim_close): Delete code opening & closing log file.
1928 (mips_option_handler): Delete -l and -n options.
1929 (OPTION mips_options): Ditto.
1930
1931 * interp.c (OPTION mips_options): Rename option trace to dinero.
1932 (mips_option_handler): Update.
1933
1934Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1935
1936 * interp.c (fetch_str): New function.
1937 (sim_monitor): Rewrite using sim_read & sim_write.
1938 (sim_open): Check magic number.
1939 (sim_open): Write monitor vectors into memory using sim_write.
1940 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1941 (sim_read, sim_write): Simplify - transfer data one byte at a
1942 time.
1943 (load_memory, store_memory): Clarify meaning of parameter RAW.
1944
1945 * sim-main.h (isHOST): Defete definition.
1946 (isTARGET): Mark as depreciated.
1947 (address_translation): Delete parameter HOST.
1948
1949 * interp.c (address_translation): Delete parameter HOST.
1950
1951Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1952
1953 * mips.igen:
1954
1955 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1956 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1957
1958Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1959
1960 * mips.igen: Add model filter field to records.
1961
1962Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1963
1964 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1965
1966 interp.c (sim_engine_run): Do not compile function sim_engine_run
1967 when WITH_IGEN == 1.
1968
1969 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1970 target architecture.
1971
1972 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1973 igen. Replace with configuration variables sim_igen_flags /
1974 sim_m16_flags.
1975
1976 * m16.igen: New file. Copy mips16 insns here.
1977 * mips.igen: From here.
1978
1979Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1980
1981 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1982 to top.
1983 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1984
1985Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1986
1987 * gencode.c (build_instruction): Follow sim_write's lead in using
1988 BigEndianMem instead of !ByteSwapMem.
1989
1990Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1991
1992 * configure.in (sim_gen): Dependent on target, select type of
1993 generator. Always select old style generator.
1994
1995 configure: Re-generate.
1996
1997 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1998 targets.
1999 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2000 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2001 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2002 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2003 SIM_@sim_gen@_*, set by autoconf.
2004
2005Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2006
2007 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2008
2009 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2010 CURRENT_FLOATING_POINT instead.
2011
2012 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2013 (address_translation): Raise exception InstructionFetch when
2014 translation fails and isINSTRUCTION.
2015
2016 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2017 sim_engine_run): Change type of of vaddr and paddr to
2018 address_word.
2019 (address_translation, prefetch, load_memory, store_memory,
2020 cache_op): Change type of vAddr and pAddr to address_word.
2021
2022 * gencode.c (build_instruction): Change type of vaddr and paddr to
2023 address_word.
2024
2025Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2026
2027 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2028 macro to obtain result of ALU op.
2029
2030Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2031
2032 * interp.c (sim_info): Call profile_print.
2033
2034Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2035
2036 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2037
2038 * sim-main.h (WITH_PROFILE): Do not define, defined in
2039 common/sim-config.h. Use sim-profile module.
2040 (simPROFILE): Delete defintion.
2041
2042 * interp.c (PROFILE): Delete definition.
2043 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2044 (sim_close): Delete code writing profile histogram.
2045 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2046 Delete.
2047 (sim_engine_run): Delete code profiling the PC.
2048
2049Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2050
2051 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2052
2053 * interp.c (sim_monitor): Make register pointers of type
2054 unsigned_word*.
2055
2056 * sim-main.h: Make registers of type unsigned_word not
2057 signed_word.
2058
2059Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2060
2061 * interp.c (sync_operation): Rename from SyncOperation, make
2062 global, add SD argument.
2063 (prefetch): Rename from Prefetch, make global, add SD argument.
2064 (decode_coproc): Make global.
2065
2066 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2067
2068 * gencode.c (build_instruction): Generate DecodeCoproc not
2069 decode_coproc calls.
2070
2071 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2072 (SizeFGR): Move to sim-main.h
2073 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2074 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2075 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2076 sim-main.h.
2077 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2078 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2079 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2080 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2081 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2082 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2083
2084 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2085 exception.
2086 (sim-alu.h): Include.
2087 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2088 (sim_cia): Typedef to instruction_address.
2089
2090Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2091
2092 * Makefile.in (interp.o): Rename generated file engine.c to
2093 oengine.c.
2094
2095 * interp.c: Update.
2096
2097Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2098
2099 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2100
2101Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2102
2103 * gencode.c (build_instruction): For "FPSQRT", output correct
2104 number of arguments to Recip.
2105
2106Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2107
2108 * Makefile.in (interp.o): Depends on sim-main.h
2109
2110 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2111
2112 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2113 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2114 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2115 STATE, DSSTATE): Define
2116 (GPR, FGRIDX, ..): Define.
2117
2118 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2119 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2120 (GPR, FGRIDX, ...): Delete macros.
2121
2122 * interp.c: Update names to match defines from sim-main.h
2123
2124Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2125
2126 * interp.c (sim_monitor): Add SD argument.
2127 (sim_warning): Delete. Replace calls with calls to
2128 sim_io_eprintf.
2129 (sim_error): Delete. Replace calls with sim_io_error.
2130 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2131 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2132 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2133 argument.
2134 (mips_size): Rename from sim_size. Add SD argument.
2135
2136 * interp.c (simulator): Delete global variable.
2137 (callback): Delete global variable.
2138 (mips_option_handler, sim_open, sim_write, sim_read,
2139 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2140 sim_size,sim_monitor): Use sim_io_* not callback->*.
2141 (sim_open): ZALLOC simulator struct.
2142 (PROFILE): Do not define.
2143
2144Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2145
2146 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2147 support.h with corresponding code.
2148
2149 * sim-main.h (word64, uword64), support.h: Move definition to
2150 sim-main.h.
2151 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2152
2153 * support.h: Delete
2154 * Makefile.in: Update dependencies
2155 * interp.c: Do not include.
2156
2157Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2158
2159 * interp.c (address_translation, load_memory, store_memory,
2160 cache_op): Rename to from AddressTranslation et.al., make global,
2161 add SD argument
2162
2163 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2164 CacheOp): Define.
2165
2166 * interp.c (SignalException): Rename to signal_exception, make
2167 global.
2168
2169 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2170
2171 * sim-main.h (SignalException, SignalExceptionInterrupt,
2172 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2173 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2174 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2175 Define.
2176
2177 * interp.c, support.h: Use.
2178
2179Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2180
2181 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2182 to value_fpr / store_fpr. Add SD argument.
2183 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2184 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2185
2186 * sim-main.h (ValueFPR, StoreFPR): Define.
2187
2188Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2189
2190 * interp.c (sim_engine_run): Check consistency between configure
2191 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2192 and HASFPU.
2193
2194 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2195 (mips_fpu): Configure WITH_FLOATING_POINT.
2196 (mips_endian): Configure WITH_TARGET_ENDIAN.
2197 * configure: Update.
2198
2199Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2200
2201 * configure: Regenerated to track ../common/aclocal.m4 changes.
2202
2203Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2204
2205 * configure: Regenerated.
2206
2207Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2208
2209 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2210
2211Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2212
2213 * gencode.c (print_igen_insn_models): Assume certain architectures
2214 include all mips* instructions.
2215 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2216 instruction.
2217
2218 * Makefile.in (tmp.igen): Add target. Generate igen input from
2219 gencode file.
2220
2221 * gencode.c (FEATURE_IGEN): Define.
2222 (main): Add --igen option. Generate output in igen format.
2223 (process_instructions): Format output according to igen option.
2224 (print_igen_insn_format): New function.
2225 (print_igen_insn_models): New function.
2226 (process_instructions): Only issue warnings and ignore
2227 instructions when no FEATURE_IGEN.
2228
2229Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2230
2231 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2232 MIPS targets.
2233
2234Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2235
2236 * configure: Regenerated to track ../common/aclocal.m4 changes.
2237
2238Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2239
2240 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2241 SIM_RESERVED_BITS): Delete, moved to common.
2242 (SIM_EXTRA_CFLAGS): Update.
2243
2244Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2245
2246 * configure.in: Configure non-strict memory alignment.
2247 * configure: Regenerated to track ../common/aclocal.m4 changes.
2248
2249Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2250
2251 * configure: Regenerated to track ../common/aclocal.m4 changes.
2252
2253Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2254
2255 * gencode.c (SDBBP,DERET): Added (3900) insns.
2256 (RFE): Turn on for 3900.
2257 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2258 (dsstate): Made global.
2259 (SUBTARGET_R3900): Added.
2260 (CANCELDELAYSLOT): New.
2261 (SignalException): Ignore SystemCall rather than ignore and
2262 terminate. Add DebugBreakPoint handling.
2263 (decode_coproc): New insns RFE, DERET; and new registers Debug
2264 and DEPC protected by SUBTARGET_R3900.
2265 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2266 bits explicitly.
2267 * Makefile.in,configure.in: Add mips subtarget option.
2268 * configure: Update.
2269
2270Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2271
2272 * gencode.c: Add r3900 (tx39).
2273
2274
2275Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2276
2277 * gencode.c (build_instruction): Don't need to subtract 4 for
2278 JALR, just 2.
2279
2280Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2281
2282 * interp.c: Correct some HASFPU problems.
2283
2284Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2285
2286 * configure: Regenerated to track ../common/aclocal.m4 changes.
2287
2288Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2289
2290 * interp.c (mips_options): Fix samples option short form, should
2291 be `x'.
2292
2293Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2294
2295 * interp.c (sim_info): Enable info code. Was just returning.
2296
2297Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2298
2299 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2300 MFC0.
2301
2302Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2303
2304 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2305 constants.
2306 (build_instruction): Ditto for LL.
2307
2308Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2309
2310 * configure: Regenerated to track ../common/aclocal.m4 changes.
2311
2312Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2313
2314 * configure: Regenerated to track ../common/aclocal.m4 changes.
2315 * config.in: Ditto.
2316
2317Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2318
2319 * interp.c (sim_open): Add call to sim_analyze_program, update
2320 call to sim_config.
2321
2322Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2323
2324 * interp.c (sim_kill): Delete.
2325 (sim_create_inferior): Add ABFD argument. Set PC from same.
2326 (sim_load): Move code initializing trap handlers from here.
2327 (sim_open): To here.
2328 (sim_load): Delete, use sim-hload.c.
2329
2330 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2331
2332Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2333
2334 * configure: Regenerated to track ../common/aclocal.m4 changes.
2335 * config.in: Ditto.
2336
2337Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2338
2339 * interp.c (sim_open): Add ABFD argument.
2340 (sim_load): Move call to sim_config from here.
2341 (sim_open): To here. Check return status.
2342
2343Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2344
2345 * gencode.c (build_instruction): Two arg MADD should
2346 not assign result to $0.
2347
2348Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2349
2350 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2351 * sim/mips/configure.in: Regenerate.
2352
2353Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2354
2355 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2356 signed8, unsigned8 et.al. types.
2357
2358 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2359 hosts when selecting subreg.
2360
2361Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2362
2363 * interp.c (sim_engine_run): Reset the ZERO register to zero
2364 regardless of FEATURE_WARN_ZERO.
2365 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2366
2367Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2368
2369 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2370 (SignalException): For BreakPoints ignore any mode bits and just
2371 save the PC.
2372 (SignalException): Always set the CAUSE register.
2373
2374Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2375
2376 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2377 exception has been taken.
2378
2379 * interp.c: Implement the ERET and mt/f sr instructions.
2380
2381Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2382
2383 * interp.c (SignalException): Don't bother restarting an
2384 interrupt.
2385
2386Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2387
2388 * interp.c (SignalException): Really take an interrupt.
2389 (interrupt_event): Only deliver interrupts when enabled.
2390
2391Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2392
2393 * interp.c (sim_info): Only print info when verbose.
2394 (sim_info) Use sim_io_printf for output.
2395
2396Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2397
2398 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2399 mips architectures.
2400
2401Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2402
2403 * interp.c (sim_do_command): Check for common commands if a
2404 simulator specific command fails.
2405
2406Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2407
2408 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2409 and simBE when DEBUG is defined.
2410
2411Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2412
2413 * interp.c (interrupt_event): New function. Pass exception event
2414 onto exception handler.
2415
2416 * configure.in: Check for stdlib.h.
2417 * configure: Regenerate.
2418
2419 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2420 variable declaration.
2421 (build_instruction): Initialize memval1.
2422 (build_instruction): Add UNUSED attribute to byte, bigend,
2423 reverse.
2424 (build_operands): Ditto.
2425
2426 * interp.c: Fix GCC warnings.
2427 (sim_get_quit_code): Delete.
2428
2429 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2430 * Makefile.in: Ditto.
2431 * configure: Re-generate.
2432
2433 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2434
2435Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2436
2437 * interp.c (mips_option_handler): New function parse argumes using
2438 sim-options.
2439 (myname): Replace with STATE_MY_NAME.
2440 (sim_open): Delete check for host endianness - performed by
2441 sim_config.
2442 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2443 (sim_open): Move much of the initialization from here.
2444 (sim_load): To here. After the image has been loaded and
2445 endianness set.
2446 (sim_open): Move ColdReset from here.
2447 (sim_create_inferior): To here.
2448 (sim_open): Make FP check less dependant on host endianness.
2449
2450 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2451 run.
2452 * interp.c (sim_set_callbacks): Delete.
2453
2454 * interp.c (membank, membank_base, membank_size): Replace with
2455 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2456 (sim_open): Remove call to callback->init. gdb/run do this.
2457
2458 * interp.c: Update
2459
2460 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2461
2462 * interp.c (big_endian_p): Delete, replaced by
2463 current_target_byte_order.
2464
2465Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2466
2467 * interp.c (host_read_long, host_read_word, host_swap_word,
2468 host_swap_long): Delete. Using common sim-endian.
2469 (sim_fetch_register, sim_store_register): Use H2T.
2470 (pipeline_ticks): Delete. Handled by sim-events.
2471 (sim_info): Update.
2472 (sim_engine_run): Update.
2473
2474Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2475
2476 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2477 reason from here.
2478 (SignalException): To here. Signal using sim_engine_halt.
2479 (sim_stop_reason): Delete, moved to common.
2480
2481Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2482
2483 * interp.c (sim_open): Add callback argument.
2484 (sim_set_callbacks): Delete SIM_DESC argument.
2485 (sim_size): Ditto.
2486
2487Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2488
2489 * Makefile.in (SIM_OBJS): Add common modules.
2490
2491 * interp.c (sim_set_callbacks): Also set SD callback.
2492 (set_endianness, xfer_*, swap_*): Delete.
2493 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2494 Change to functions using sim-endian macros.
2495 (control_c, sim_stop): Delete, use common version.
2496 (simulate): Convert into.
2497 (sim_engine_run): This function.
2498 (sim_resume): Delete.
2499
2500 * interp.c (simulation): New variable - the simulator object.
2501 (sim_kind): Delete global - merged into simulation.
2502 (sim_load): Cleanup. Move PC assignment from here.
2503 (sim_create_inferior): To here.
2504
2505 * sim-main.h: New file.
2506 * interp.c (sim-main.h): Include.
2507
2508Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2509
2510 * configure: Regenerated to track ../common/aclocal.m4 changes.
2511
2512Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2513
2514 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2515
2516Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2517
2518 * gencode.c (build_instruction): DIV instructions: check
2519 for division by zero and integer overflow before using
2520 host's division operation.
2521
2522Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2523
2524 * Makefile.in (SIM_OBJS): Add sim-load.o.
2525 * interp.c: #include bfd.h.
2526 (target_byte_order): Delete.
2527 (sim_kind, myname, big_endian_p): New static locals.
2528 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2529 after argument parsing. Recognize -E arg, set endianness accordingly.
2530 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2531 load file into simulator. Set PC from bfd.
2532 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2533 (set_endianness): Use big_endian_p instead of target_byte_order.
2534
2535Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2536
2537 * interp.c (sim_size): Delete prototype - conflicts with
2538 definition in remote-sim.h. Correct definition.
2539
2540Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2541
2542 * configure: Regenerated to track ../common/aclocal.m4 changes.
2543 * config.in: Ditto.
2544
2545Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2546
2547 * interp.c (sim_open): New arg `kind'.
2548
2549 * configure: Regenerated to track ../common/aclocal.m4 changes.
2550
2551Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2552
2553 * configure: Regenerated to track ../common/aclocal.m4 changes.
2554
2555Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2556
2557 * interp.c (sim_open): Set optind to 0 before calling getopt.
2558
2559Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2560
2561 * configure: Regenerated to track ../common/aclocal.m4 changes.
2562
2563Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2564
2565 * interp.c : Replace uses of pr_addr with pr_uword64
2566 where the bit length is always 64 independent of SIM_ADDR.
2567 (pr_uword64) : added.
2568
2569Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2570
2571 * configure: Re-generate.
2572
2573Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2574
2575 * configure: Regenerate to track ../common/aclocal.m4 changes.
2576
2577Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2578
2579 * interp.c (sim_open): New SIM_DESC result. Argument is now
2580 in argv form.
2581 (other sim_*): New SIM_DESC argument.
2582
2583Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2584
2585 * interp.c: Fix printing of addresses for non-64-bit targets.
2586 (pr_addr): Add function to print address based on size.
2587
2588Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2589
2590 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2591
2592Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2593
2594 * gencode.c (build_mips16_operands): Correct computation of base
2595 address for extended PC relative instruction.
2596
2597Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2598
2599 * interp.c (mips16_entry): Add support for floating point cases.
2600 (SignalException): Pass floating point cases to mips16_entry.
2601 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2602 registers.
2603 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2604 or fmt_word.
2605 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2606 and then set the state to fmt_uninterpreted.
2607 (COP_SW): Temporarily set the state to fmt_word while calling
2608 ValueFPR.
2609
2610Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2611
2612 * gencode.c (build_instruction): The high order may be set in the
2613 comparison flags at any ISA level, not just ISA 4.
2614
2615Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2616
2617 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2618 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2619 * configure.in: sinclude ../common/aclocal.m4.
2620 * configure: Regenerated.
2621
2622Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2623
2624 * configure: Rebuild after change to aclocal.m4.
2625
2626Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2627
2628 * configure configure.in Makefile.in: Update to new configure
2629 scheme which is more compatible with WinGDB builds.
2630 * configure.in: Improve comment on how to run autoconf.
2631 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2632 * Makefile.in: Use autoconf substitution to install common
2633 makefile fragment.
2634
2635Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2636
2637 * gencode.c (build_instruction): Use BigEndianCPU instead of
2638 ByteSwapMem.
2639
2640Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2641
2642 * interp.c (sim_monitor): Make output to stdout visible in
2643 wingdb's I/O log window.
2644
2645Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2646
2647 * support.h: Undo previous change to SIGTRAP
2648 and SIGQUIT values.
2649
2650Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2651
2652 * interp.c (store_word, load_word): New static functions.
2653 (mips16_entry): New static function.
2654 (SignalException): Look for mips16 entry and exit instructions.
2655 (simulate): Use the correct index when setting fpr_state after
2656 doing a pending move.
2657
2658Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2659
2660 * interp.c: Fix byte-swapping code throughout to work on
2661 both little- and big-endian hosts.
2662
2663Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2664
2665 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2666 with gdb/config/i386/xm-windows.h.
2667
2668Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2669
2670 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2671 that messes up arithmetic shifts.
2672
2673Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2674
2675 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2676 SIGTRAP and SIGQUIT for _WIN32.
2677
2678Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2679
2680 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2681 force a 64 bit multiplication.
2682 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2683 destination register is 0, since that is the default mips16 nop
2684 instruction.
2685
2686Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2687
2688 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2689 (build_endian_shift): Don't check proc64.
2690 (build_instruction): Always set memval to uword64. Cast op2 to
2691 uword64 when shifting it left in memory instructions. Always use
2692 the same code for stores--don't special case proc64.
2693
2694 * gencode.c (build_mips16_operands): Fix base PC value for PC
2695 relative operands.
2696 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2697 jal instruction.
2698 * interp.c (simJALDELAYSLOT): Define.
2699 (JALDELAYSLOT): Define.
2700 (INDELAYSLOT, INJALDELAYSLOT): Define.
2701 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2702
2703Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2704
2705 * interp.c (sim_open): add flush_cache as a PMON routine
2706 (sim_monitor): handle flush_cache by ignoring it
2707
2708Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2709
2710 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2711 BigEndianMem.
2712 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2713 (BigEndianMem): Rename to ByteSwapMem and change sense.
2714 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2715 BigEndianMem references to !ByteSwapMem.
2716 (set_endianness): New function, with prototype.
2717 (sim_open): Call set_endianness.
2718 (sim_info): Use simBE instead of BigEndianMem.
2719 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2720 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2721 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2722 ifdefs, keeping the prototype declaration.
2723 (swap_word): Rewrite correctly.
2724 (ColdReset): Delete references to CONFIG. Delete endianness related
2725 code; moved to set_endianness.
2726
2727Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2728
2729 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2730 * interp.c (CHECKHILO): Define away.
2731 (simSIGINT): New macro.
2732 (membank_size): Increase from 1MB to 2MB.
2733 (control_c): New function.
2734 (sim_resume): Rename parameter signal to signal_number. Add local
2735 variable prev. Call signal before and after simulate.
2736 (sim_stop_reason): Add simSIGINT support.
2737 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2738 functions always.
2739 (sim_warning): Delete call to SignalException. Do call printf_filtered
2740 if logfh is NULL.
2741 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2742 a call to sim_warning.
2743
2744Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2745
2746 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2747 16 bit instructions.
2748
2749Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2750
2751 Add support for mips16 (16 bit MIPS implementation):
2752 * gencode.c (inst_type): Add mips16 instruction encoding types.
2753 (GETDATASIZEINSN): Define.
2754 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2755 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2756 mtlo.
2757 (MIPS16_DECODE): New table, for mips16 instructions.
2758 (bitmap_val): New static function.
2759 (struct mips16_op): Define.
2760 (mips16_op_table): New table, for mips16 operands.
2761 (build_mips16_operands): New static function.
2762 (process_instructions): If PC is odd, decode a mips16
2763 instruction. Break out instruction handling into new
2764 build_instruction function.
2765 (build_instruction): New static function, broken out of
2766 process_instructions. Check modifiers rather than flags for SHIFT
2767 bit count and m[ft]{hi,lo} direction.
2768 (usage): Pass program name to fprintf.
2769 (main): Remove unused variable this_option_optind. Change
2770 ``*loptarg++'' to ``loptarg++''.
2771 (my_strtoul): Parenthesize && within ||.
2772 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2773 (simulate): If PC is odd, fetch a 16 bit instruction, and
2774 increment PC by 2 rather than 4.
2775 * configure.in: Add case for mips16*-*-*.
2776 * configure: Rebuild.
2777
2778Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2779
2780 * interp.c: Allow -t to enable tracing in standalone simulator.
2781 Fix garbage output in trace file and error messages.
2782
2783Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2784
2785 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2786 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2787 * configure.in: Simplify using macros in ../common/aclocal.m4.
2788 * configure: Regenerated.
2789 * tconfig.in: New file.
2790
2791Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2792
2793 * interp.c: Fix bugs in 64-bit port.
2794 Use ansi function declarations for msvc compiler.
2795 Initialize and test file pointer in trace code.
2796 Prevent duplicate definition of LAST_EMED_REGNUM.
2797
2798Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2799
2800 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2801
2802Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2803
2804 * interp.c (SignalException): Check for explicit terminating
2805 breakpoint value.
2806 * gencode.c: Pass instruction value through SignalException()
2807 calls for Trap, Breakpoint and Syscall.
2808
2809Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2810
2811 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2812 only used on those hosts that provide it.
2813 * configure.in: Add sqrt() to list of functions to be checked for.
2814 * config.in: Re-generated.
2815 * configure: Re-generated.
2816
2817Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2818
2819 * gencode.c (process_instructions): Call build_endian_shift when
2820 expanding STORE RIGHT, to fix swr.
2821 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2822 clear the high bits.
2823 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2824 Fix float to int conversions to produce signed values.
2825
2826Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2827
2828 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2829 (process_instructions): Correct handling of nor instruction.
2830 Correct shift count for 32 bit shift instructions. Correct sign
2831 extension for arithmetic shifts to not shift the number of bits in
2832 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2833 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2834 Fix madd.
2835 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2836 It's OK to have a mult follow a mult. What's not OK is to have a
2837 mult follow an mfhi.
2838 (Convert): Comment out incorrect rounding code.
2839
2840Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2841
2842 * interp.c (sim_monitor): Improved monitor printf
2843 simulation. Tidied up simulator warnings, and added "--log" option
2844 for directing warning message output.
2845 * gencode.c: Use sim_warning() rather than WARNING macro.
2846
2847Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2848
2849 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2850 getopt1.o, rather than on gencode.c. Link objects together.
2851 Don't link against -liberty.
2852 (gencode.o, getopt.o, getopt1.o): New targets.
2853 * gencode.c: Include <ctype.h> and "ansidecl.h".
2854 (AND): Undefine after including "ansidecl.h".
2855 (ULONG_MAX): Define if not defined.
2856 (OP_*): Don't define macros; now defined in opcode/mips.h.
2857 (main): Call my_strtoul rather than strtoul.
2858 (my_strtoul): New static function.
2859
2860Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2861
2862 * gencode.c (process_instructions): Generate word64 and uword64
2863 instead of `long long' and `unsigned long long' data types.
2864 * interp.c: #include sysdep.h to get signals, and define default
2865 for SIGBUS.
2866 * (Convert): Work around for Visual-C++ compiler bug with type
2867 conversion.
2868 * support.h: Make things compile under Visual-C++ by using
2869 __int64 instead of `long long'. Change many refs to long long
2870 into word64/uword64 typedefs.
2871
2872Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2873
2874 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2875 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2876 (docdir): Removed.
2877 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2878 (AC_PROG_INSTALL): Added.
2879 (AC_PROG_CC): Moved to before configure.host call.
2880 * configure: Rebuilt.
2881
2882Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2883
2884 * configure.in: Define @SIMCONF@ depending on mips target.
2885 * configure: Rebuild.
2886 * Makefile.in (run): Add @SIMCONF@ to control simulator
2887 construction.
2888 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2889 * interp.c: Remove some debugging, provide more detailed error
2890 messages, update memory accesses to use LOADDRMASK.
2891
2892Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2893
2894 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2895 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2896 stamp-h.
2897 * configure: Rebuild.
2898 * config.in: New file, generated by autoheader.
2899 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2900 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2901 HAVE_ANINT and HAVE_AINT, as appropriate.
2902 * Makefile.in (run): Use @LIBS@ rather than -lm.
2903 (interp.o): Depend upon config.h.
2904 (Makefile): Just rebuild Makefile.
2905 (clean): Remove stamp-h.
2906 (mostlyclean): Make the same as clean, not as distclean.
2907 (config.h, stamp-h): New targets.
2908
2909Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2910
2911 * interp.c (ColdReset): Fix boolean test. Make all simulator
2912 globals static.
2913
2914Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2915
2916 * interp.c (xfer_direct_word, xfer_direct_long,
2917 swap_direct_word, swap_direct_long, xfer_big_word,
2918 xfer_big_long, xfer_little_word, xfer_little_long,
2919 swap_word,swap_long): Added.
2920 * interp.c (ColdReset): Provide function indirection to
2921 host<->simulated_target transfer routines.
2922 * interp.c (sim_store_register, sim_fetch_register): Updated to
2923 make use of indirected transfer routines.
2924
2925Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2926
2927 * gencode.c (process_instructions): Ensure FP ABS instruction
2928 recognised.
2929 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2930 system call support.
2931
2932Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2933
2934 * interp.c (sim_do_command): Complain if callback structure not
2935 initialised.
2936
2937Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2938
2939 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2940 support for Sun hosts.
2941 * Makefile.in (gencode): Ensure the host compiler and libraries
2942 used for cross-hosted build.
2943
2944Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2945
2946 * interp.c, gencode.c: Some more (TODO) tidying.
2947
2948Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2949
2950 * gencode.c, interp.c: Replaced explicit long long references with
2951 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2952 * support.h (SET64LO, SET64HI): Macros added.
2953
2954Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2955
2956 * configure: Regenerate with autoconf 2.7.
2957
2958Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2959
2960 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2961 * support.h: Remove superfluous "1" from #if.
2962 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2963
2964Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2965
2966 * interp.c (StoreFPR): Control UndefinedResult() call on
2967 WARN_RESULT manifest.
2968
2969Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2970
2971 * gencode.c: Tidied instruction decoding, and added FP instruction
2972 support.
2973
2974 * interp.c: Added dineroIII, and BSD profiling support. Also
2975 run-time FP handling.
2976
2977Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2978
2979 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2980 gencode.c, interp.c, support.h: created.
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