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* stabsread.c (update_method_name_from_physname): Call complaint()
[deliverable/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
28f50ac8
CD		 12002-12-31 Chris Demetriou <cgd@broadcom.com>
2
3 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
4 * mips.igen: Remove all invocations of check_branch_bug and
5 mark_branch_bug.
6
5071ffe6
CD		 72002-12-16 Chris Demetriou <cgd@broadcom.com>
8
9 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
10
06e7837e
CD		 112002-07-30 Chris Demetriou <cgd@broadcom.com>
12
13 * mips.igen (do_load_double, do_store_double): New functions.
14 (LDC1, SDC1): Rename to...
15 (LDC1b, SDC1b): respectively.
16 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
17
2265c243
MS		 182002-07-29 Michael Snyder <msnyder@redhat.com>
19
20 * cp1.c (fp_recip2): Modify initialization expression so that
21 GCC will recognize it as constant.
22
a2f8b4f3
CD		 232002-06-18 Chris Demetriou <cgd@broadcom.com>
24
25 * mdmx.c (SD_): Delete.
26 (Unpredictable): Re-define, for now, to directly invoke
27 unpredictable_action().
28 (mdmx_acc_op): Fix error in .ob immediate handling.
29
b4b6c939
AC		 302002-06-18 Andrew Cagney <cagney@redhat.com>
31
32 * interp.c (sim_firmware_command): Initialize `address'.
33
c8cca39f
AC		 342002-06-16 Andrew Cagney <ac131313@redhat.com>
35
36 * configure: Regenerated to track ../common/aclocal.m4 changes.
37
e7e81181
CD		 382002-06-14 Chris Demetriou <cgd@broadcom.com>
39 Ed Satterthwaite <ehs@broadcom.com>
40
41 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
42 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
43 * mips.igen: Include mips3d.igen.
44 (mips3d): New model name for MIPS-3D ASE instructions.
45 (CVT.W.fmt): Don't use this instruction for word (source) format
46 instructions.
47 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
48 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
49 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
50 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
51 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
52 (RSquareRoot1, RSquareRoot2): New macros.
53 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
54 (fp_rsqrt2): New functions.
55 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
56 * configure: Regenerate.
57
3a2b820e 582002-06-13 Chris Demetriou <cgd@broadcom.com>
eab54952 59 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 60
61 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
62 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
63 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
64 (convert): Note that this function is not used for paired-single
65 format conversions.
66 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
67 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
68 (check_fmt_p): Enable paired-single support.
69 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
70 (PUU.PS): New instructions.
71 (CVT.S.fmt): Don't use this instruction for paired-single format
72 destinations.
73 * sim-main.h (FP_formats): New value 'fmt_ps.'
74 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
75 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
76
d18ea9c2
CD		 772002-06-12 Chris Demetriou <cgd@broadcom.com>
78
79 * mips.igen: Fix formatting of function calls in
80 many FP operations.
81
95fd5cee
CD		 822002-06-12 Chris Demetriou <cgd@broadcom.com>
83
84 * mips.igen (MOVN, MOVZ): Trace result.
85 (TNEI): Print "tnei" as the opcode name in traces.
86 (CEIL.W): Add disassembly string for traces.
87 (RSQRT.fmt): Make location of disassembly string consistent
88 with other instructions.
89
4f0d55ae
CD		 902002-06-12 Chris Demetriou <cgd@broadcom.com>
91
92 * mips.igen (X): Delete unused function.
93
3c25f8c7
AC		 942002-06-08 Andrew Cagney <cagney@redhat.com>
95
96 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
97
f3c08b7e
CD		 982002-06-07 Chris Demetriou <cgd@broadcom.com>
99 Ed Satterthwaite <ehs@broadcom.com>
100
101 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
102 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
103 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
104 (fp_nmsub): New prototypes.
105 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
106 (NegMultiplySub): New defines.
107 * mips.igen (RSQRT.fmt): Use RSquareRoot().
108 (MADD.D, MADD.S): Replace with...
109 (MADD.fmt): New instruction.
110 (MSUB.D, MSUB.S): Replace with...
111 (MSUB.fmt): New instruction.
112 (NMADD.D, NMADD.S): Replace with...
113 (NMADD.fmt): New instruction.
114 (NMSUB.D, MSUB.S): Replace with...
115 (NMSUB.fmt): New instruction.
116
52714ff9
CD		 1172002-06-07 Chris Demetriou <cgd@broadcom.com>
118 Ed Satterthwaite <ehs@broadcom.com>
119
120 * cp1.c: Fix more comment spelling and formatting.
121 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
122 (denorm_mode): New function.
123 (fpu_unary, fpu_binary): Round results after operation, collect
124 status from rounding operations, and update the FCSR.
125 (convert): Collect status from integer conversions and rounding
126 operations, and update the FCSR. Adjust NaN values that result
127 from conversions. Convert to use sim_io_eprintf rather than
128 fprintf, and remove some debugging code.
129 * cp1.h (fenr_FS): New define.
130
577d8c4b
CD		 1312002-06-07 Chris Demetriou <cgd@broadcom.com>
132
133 * cp1.c (convert): Remove unusable debugging code, and move MIPS
134 rounding mode to sim FP rounding mode flag conversion code into...
135 (rounding_mode): New function.
136
196496ed
CD		 1372002-06-07 Chris Demetriou <cgd@broadcom.com>
138
139 * cp1.c: Clean up formatting of a few comments.
140 (value_fpr): Reformat switch statement.
141
cfe9ea23
CD		 1422002-06-06 Chris Demetriou <cgd@broadcom.com>
143 Ed Satterthwaite <ehs@broadcom.com>
144
145 * cp1.h: New file.
146 * sim-main.h: Include cp1.h.
147 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
148 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
149 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
150 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
151 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
152 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
153 * cp1.c: Don't include sim-fpu.h; already included by
154 sim-main.h. Clean up formatting of some comments.
155 (NaN, Equal, Less): Remove.
156 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
157 (fp_cmp): New functions.
158 * mips.igen (do_c_cond_fmt): Remove.
159 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
160 Compare. Add result tracing.
161 (CxC1): Remove, replace with...
162 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
163 (DMxC1): Remove, replace with...
164 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
165 (MxC1): Remove, replace with...
166 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
167
ee7254b0
CD		 1682002-06-04 Chris Demetriou <cgd@broadcom.com>
169
170 * sim-main.h (FGRIDX): Remove, replace all uses with...
171 (FGR_BASE): New macro.
172 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
173 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
174 (NR_FGR, FGR): Likewise.
175 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
176 * mips.igen: Likewise.
177
d3eb724f
CD		 1782002-06-04 Chris Demetriou <cgd@broadcom.com>
179
180 * cp1.c: Add an FSF Copyright notice to this file.
181
ba46ddd0
CD		 1822002-06-04 Chris Demetriou <cgd@broadcom.com>
183 Ed Satterthwaite <ehs@broadcom.com>
184
185 * cp1.c (Infinity): Remove.
186 * sim-main.h (Infinity): Likewise.
187
188 * cp1.c (fp_unary, fp_binary): New functions.
189 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
190 (fp_sqrt): New functions, implemented in terms of the above.
191 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
192 (Recip, SquareRoot): Remove (replaced by functions above).
193 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
194 (fp_recip, fp_sqrt): New prototypes.
195 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
196 (Recip, SquareRoot): Replace prototypes with #defines which
197 invoke the functions above.
198
18d8a52d
CD		 1992002-06-03 Chris Demetriou <cgd@broadcom.com>
200
201 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
202 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
203 file, remove PARAMS from prototypes.
204 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
205 simulator state arguments.
206 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
207 pass simulator state arguments.
208 * cp1.c (SD): Redefine as CPU_STATE(cpu).
209 (store_fpr, convert): Remove 'sd' argument.
210 (value_fpr): Likewise. Convert to use 'SD' instead.
211
0f154cbd
CD		 2122002-06-03 Chris Demetriou <cgd@broadcom.com>
213
214 * cp1.c (Min, Max): Remove #if 0'd functions.
215 * sim-main.h (Min, Max): Remove.
216
e80fc152
CD		 2172002-06-03 Chris Demetriou <cgd@broadcom.com>
218
219 * cp1.c: fix formatting of switch case and default labels.
220 * interp.c: Likewise.
221 * sim-main.c: Likewise.
222
bad673a9
CD		 2232002-06-03 Chris Demetriou <cgd@broadcom.com>
224
225 * cp1.c: Clean up comments which describe FP formats.
226 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
227
7cbea089
CD		 2282002-06-03 Chris Demetriou <cgd@broadcom.com>
229 Ed Satterthwaite <ehs@broadcom.com>
230
231 * configure.in (mipsisa64sb1*-*-*): New target for supporting
232 Broadcom SiByte SB-1 processor configurations.
233 * configure: Regenerate.
234 * sb1.igen: New file.
235 * mips.igen: Include sb1.igen.
236 (sb1): New model.
237 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
238 * mdmx.igen: Add "sb1" model to all appropriate functions and
239 instructions.
240 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
241 (ob_func, ob_acc): Reference the above.
242 (qh_acc): Adjust to keep the same size as ob_acc.
243 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
244 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
245
909daa82
CD		 2462002-06-03 Chris Demetriou <cgd@broadcom.com>
247
248 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
249
f4f1b9f1
CD		 2502002-06-02 Chris Demetriou <cgd@broadcom.com>
251 Ed Satterthwaite <ehs@broadcom.com>
252
253 * mips.igen (mdmx): New (pseudo-)model.
254 * mdmx.c, mdmx.igen: New files.
255 * Makefile.in (SIM_OBJS): Add mdmx.o.
256 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
257 New typedefs.
258 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
259 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
260 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
261 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
262 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
263 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
264 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
265 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
266 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
267 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
268 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
269 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
270 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
271 (qh_fmtsel): New macros.
272 (_sim_cpu): New member "acc".
273 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
274 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
275
5accf1ff
CD		 2762002-05-01 Chris Demetriou <cgd@broadcom.com>
277
278 * interp.c: Use 'deprecated' rather than 'depreciated.'
279 * sim-main.h: Likewise.
280
402586aa
CD		 2812002-05-01 Chris Demetriou <cgd@broadcom.com>
282
283 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
284 which wouldn't compile anyway.
285 * sim-main.h (unpredictable_action): New function prototype.
286 (Unpredictable): Define to call igen function unpredictable().
287 (NotWordValue): New macro to call igen function not_word_value().
288 (UndefinedResult): Remove.
289 * interp.c (undefined_result): Remove.
290 (unpredictable_action): New function.
291 * mips.igen (not_word_value, unpredictable): New functions.
292 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
293 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
294 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
295 NotWordValue() to check for unpredictable inputs, then
296 Unpredictable() to handle them.
297
c9b9995a
CD		 2982002-02-24 Chris Demetriou <cgd@broadcom.com>
299
300 * mips.igen: Fix formatting of calls to Unpredictable().
301
e1015982
AC		 3022002-04-20 Andrew Cagney <ac131313@redhat.com>
303
304 * interp.c (sim_open): Revert previous change.
305
b882a66b
AO		 3062002-04-18 Alexandre Oliva <aoliva@redhat.com>
307
308 * interp.c (sim_open): Disable chunk of code that wrote code in
309 vector table entries.
310
c429b7dd
CD		 3112002-03-19 Chris Demetriou <cgd@broadcom.com>
312
313 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
314 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
315 unused definitions.
316
37d146fa
CD		 3172002-03-19 Chris Demetriou <cgd@broadcom.com>
318
319 * cp1.c: Fix many formatting issues.
320
07892c0b
CD		 3212002-03-19 Chris G. Demetriou <cgd@broadcom.com>
322
323 * cp1.c (fpu_format_name): New function to replace...
324 (DOFMT): This. Delete, and update all callers.
325 (fpu_rounding_mode_name): New function to replace...
326 (RMMODE): This. Delete, and update all callers.
327
487f79b7
CD		 3282002-03-19 Chris G. Demetriou <cgd@broadcom.com>
329
330 * interp.c: Move FPU support routines from here to...
331 * cp1.c: Here. New file.
332 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
333 (cp1.o): New target.
334
1e799e28
CD		 3352002-03-12 Chris Demetriou <cgd@broadcom.com>
336
337 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
338 * mips.igen (mips32, mips64): New models, add to all instructions
339 and functions as appropriate.
340 (loadstore_ea, check_u64): New variant for model mips64.
341 (check_fmt_p): New variant for models mipsV and mips64, remove
342 mipsV model marking fro other variant.
343 (SLL) Rename to...
344 (SLLa) this.
345 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
346 for mips32 and mips64.
347 (DCLO, DCLZ): New instructions for mips64.
348
82f728db
CD		 3492002-03-07 Chris Demetriou <cgd@broadcom.com>
350
351 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
352 immediate or code as a hex value with the "%#lx" format.
353 (ANDI): Likewise, and fix printed instruction name.
354
b96e7ef1
CD		 3552002-03-05 Chris Demetriou <cgd@broadcom.com>
356
357 * sim-main.h (UndefinedResult, Unpredictable): New macros
358 which currently do nothing.
359
d35d4f70
CD		 3602002-03-05 Chris Demetriou <cgd@broadcom.com>
361
362 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
363 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
364 (status_CU3): New definitions.
365
366 * sim-main.h (ExceptionCause): Add new values for MIPS32
367 and MIPS64: MDMX, MCheck, CacheErr. Update comments
368 for DebugBreakPoint and NMIReset to note their status in
369 MIPS32 and MIPS64.
370 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
371 (SignalExceptionCacheErr): New exception macros.
372
3ad6f714
CD		 3732002-03-05 Chris Demetriou <cgd@broadcom.com>
374
375 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
376 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
377 is always enabled.
378 (SignalExceptionCoProcessorUnusable): Take as argument the
379 unusable coprocessor number.
380
86b77b47
CD		 3812002-03-05 Chris Demetriou <cgd@broadcom.com>
382
383 * mips.igen: Fix formatting of all SignalException calls.
384
97a88e93 3852002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 386
387 * sim-main.h (SIGNEXTEND): Remove.
388
97a88e93 3892002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 390
391 * mips.igen: Remove gencode comment from top of file, fix
392 spelling in another comment.
393
97a88e93 3942002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 395
396 * mips.igen (check_fmt, check_fmt_p): New functions to check
397 whether specific floating point formats are usable.
398 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
399 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
400 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
401 Use the new functions.
402 (do_c_cond_fmt): Remove format checks...
403 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
404
97a88e93 4052002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 406
407 * mips.igen: Fix formatting of check_fpu calls.
408
41774c9d
CD		 4092002-03-03 Chris Demetriou <cgd@broadcom.com>
410
411 * mips.igen (FLOOR.L.fmt): Store correct destination register.
412
4a0bd876
CD		 4132002-03-03 Chris Demetriou <cgd@broadcom.com>
414
415 * mips.igen: Remove whitespace at end of lines.
416
09297648
CD		 4172002-03-02 Chris Demetriou <cgd@broadcom.com>
418
419 * mips.igen (loadstore_ea): New function to do effective
420 address calculations.
421 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
422 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
423 CACHE): Use loadstore_ea to do effective address computations.
424
043b7057
CD		 4252002-03-02 Chris Demetriou <cgd@broadcom.com>
426
427 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
428 * mips.igen (LL, CxC1, MxC1): Likewise.
429
c1e8ada4
CD		 4302002-03-02 Chris Demetriou <cgd@broadcom.com>
431
432 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
433 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
434 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
435 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
436 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
437 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
438 Don't split opcode fields by hand, use the opcode field values
439 provided by igen.
440
3e1dca16
CD		 4412002-03-01 Chris Demetriou <cgd@broadcom.com>
442
443 * mips.igen (do_divu): Fix spacing.
444
445 * mips.igen (do_dsllv): Move to be right before DSLLV,
446 to match the rest of the do_<shift> functions.
447
fff8d27d
CD		 4482002-03-01 Chris Demetriou <cgd@broadcom.com>
449
450 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
451 DSRL32, do_dsrlv): Trace inputs and results.
452
0d3e762b
CD		 4532002-03-01 Chris Demetriou <cgd@broadcom.com>
454
455 * mips.igen (CACHE): Provide instruction-printing string.
456
457 * interp.c (signal_exception): Comment tokens after #endif.
458
eb5fcf93
CD		 4592002-02-28 Chris Demetriou <cgd@broadcom.com>
460
461 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
462 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
463 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
464 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
465 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
466 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
467 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
468 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
469
bb22bd7d
CD		 4702002-02-28 Chris Demetriou <cgd@broadcom.com>
471
472 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
473 instruction-printing string.
474 (LWU): Use '64' as the filter flag.
475
91a177cf
CD		 4762002-02-28 Chris Demetriou <cgd@broadcom.com>
477
478 * mips.igen (SDXC1): Fix instruction-printing string.
479
387f484a
CD		 4802002-02-28 Chris Demetriou <cgd@broadcom.com>
481
482 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
483 filter flags "32,f".
484
3d81f391
CD		 4852002-02-27 Chris Demetriou <cgd@broadcom.com>
486
487 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
488 as the filter flag.
489
af5107af
CD		 4902002-02-27 Chris Demetriou <cgd@broadcom.com>
491
492 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
493 add a comma) so that it more closely match the MIPS ISA
494 documentation opcode partitioning.
495 (PREF): Put useful names on opcode fields, and include
496 instruction-printing string.
497
ca971540
CD		 4982002-02-27 Chris Demetriou <cgd@broadcom.com>
499
500 * mips.igen (check_u64): New function which in the future will
501 check whether 64-bit instructions are usable and signal an
502 exception if not. Currently a no-op.
503 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
504 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
505 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
506 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
507
508 * mips.igen (check_fpu): New function which in the future will
509 check whether FPU instructions are usable and signal an exception
510 if not. Currently a no-op.
511 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
512 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
513 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
514 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
515 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
516 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
517 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
518 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
519
1c47a468
CD		 5202002-02-27 Chris Demetriou <cgd@broadcom.com>
521
522 * mips.igen (do_load_left, do_load_right): Move to be immediately
523 following do_load.
524 (do_store_left, do_store_right): Move to be immediately following
525 do_store.
526
603a98e7
CD		 5272002-02-27 Chris Demetriou <cgd@broadcom.com>
528
529 * mips.igen (mipsV): New model name. Also, add it to
530 all instructions and functions where it is appropriate.
531
c5d00cc7
CD		 5322002-02-18 Chris Demetriou <cgd@broadcom.com>
533
534 * mips.igen: For all functions and instructions, list model
535 names that support that instruction one per line.
536
074e9cb8
CD		 5372002-02-11 Chris Demetriou <cgd@broadcom.com>
538
539 * mips.igen: Add some additional comments about supported
540 models, and about which instructions go where.
541 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
542 order as is used in the rest of the file.
543
9805e229
CD		 5442002-02-11 Chris Demetriou <cgd@broadcom.com>
545
546 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
547 indicating that ALU32_END or ALU64_END are there to check
548 for overflow.
549 (DADD): Likewise, but also remove previous comment about
550 overflow checking.
551
f701dad2
CD		 5522002-02-10 Chris Demetriou <cgd@broadcom.com>
553
554 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
555 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
556 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
557 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
558 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
559 fields (i.e., add and move commas) so that they more closely
560 match the MIPS ISA documentation opcode partitioning.
561
5622002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098
CD		 563
564 * mips.igen (ADDI): Print immediate value.
565 (BREAK): Print code.
566 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
567 (SLL): Print "nop" specially, and don't run the code
568 that does the shift for the "nop" case.
569
9e52972e
FF		 5702001-11-17 Fred Fish <fnf@redhat.com>
571
572 * sim-main.h (float_operation): Move enum declaration outside
573 of _sim_cpu struct declaration.
574
c0efbca4
JB		 5752001-04-12 Jim Blandy <jimb@redhat.com>
576
577 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
578 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
579 set of the FCSR.
580 * sim-main.h (COCIDX): Remove definition; this isn't supported by
581 PENDING_FILL, and you can get the intended effect gracefully by
582 calling PENDING_SCHED directly.
583
fb891446
BE		 5842001-02-23 Ben Elliston <bje@redhat.com>
585
586 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
587 already defined elsewhere.
588
8030f857
BE		 5892001-02-19 Ben Elliston <bje@redhat.com>
590
591 * sim-main.h (sim_monitor): Return an int.
592 * interp.c (sim_monitor): Add return values.
593 (signal_exception): Handle error conditions from sim_monitor.
594
56b48a7a
CD		 5952001-02-08 Ben Elliston <bje@redhat.com>
596
597 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
598 (store_memory): Likewise, pass cia to sim_core_write*.
599
d3ee60d9
FCE		 6002000-10-19 Frank Ch. Eigler <fche@redhat.com>
601
602 On advice from Chris G. Demetriou <cgd@sibyte.com>:
603 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
604
071da002
AC		 605Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
606
607 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
608 * Makefile.in: Don't delete *.igen when cleaning directory.
609
a28c02cd
AC		 610Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
611
612 * m16.igen (break): Call SignalException not sim_engine_halt.
613
80ee11fa
AC		 614Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
615
616 From Jason Eckhardt:
617 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
618
673388c0
AC		 619Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
620
621 * mips.igen (MxC1, DMxC1): Fix printf formatting.
622
4c0deff4
NC		 6232000-05-24 Michael Hayes <mhayes@cygnus.com>
624
625 * mips.igen (do_dmultx): Fix typo.
626
eb2d80b4
AC		 627Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
628
629 * configure: Regenerated to track ../common/aclocal.m4 changes.
630
dd37a34b
AC		 631Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
632
633 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
634
4c0deff4
NC		 6352000-04-12 Frank Ch. Eigler <fche@redhat.com>
636
637 * sim-main.h (GPR_CLEAR): Define macro.
638
e30db738
AC		 639Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
640
641 * interp.c (decode_coproc): Output long using %lx and not %s.
642
cb7450ea
FCE		 6432000-03-21 Frank Ch. Eigler <fche@redhat.com>
644
645 * interp.c (sim_open): Sort & extend dummy memory regions for
646 --board=jmr3904 for eCos.
647
a3027dd7
FCE		 6482000-03-02 Frank Ch. Eigler <fche@redhat.com>
649
650 * configure: Regenerated.
651
652Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
653
654 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
655 calls, conditional on the simulator being in verbose mode.
656
dfcd3bfb
JM		 657Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
658
659 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
660 cache don't get ReservedInstruction traps.
661
c2d11a7d
JM		 6621999-11-29 Mark Salter <msalter@cygnus.com>
663
664 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
665 to clear status bits in sdisr register. This is how the hardware works.
666
667 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
668 being used by cygmon.
669
4ce44c66
JM		 6701999-11-11 Andrew Haley <aph@cygnus.com>
671
672 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
673 instructions.
674
cff3e48b
JM		 675Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
676
677 * mips.igen (MULT): Correct previous mis-applied patch.
678
d4f3574e
SS		 679Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
680
681 * mips.igen (delayslot32): Handle sequence like
682 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
683 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
684 (MULT): Actually pass the third register...
685
6861999-09-03 Mark Salter <msalter@cygnus.com>
687
688 * interp.c (sim_open): Added more memory aliases for additional
689 hardware being touched by cygmon on jmr3904 board.
690
691Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
692
693 * configure: Regenerated to track ../common/aclocal.m4 changes.
694
a0b3c4fd
JM		 695Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
696
697 * interp.c (sim_store_register): Handle case where client - GDB -
698 specifies that a 4 byte register is 8 bytes in size.
699 (sim_fetch_register): Ditto.
700
adf40b2e
JM		 7011999-07-14 Frank Ch. Eigler <fche@cygnus.com>
702
703 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
704 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
705 (idt_monitor_base): Base address for IDT monitor traps.
706 (pmon_monitor_base): Ditto for PMON.
707 (lsipmon_monitor_base): Ditto for LSI PMON.
708 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
709 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
710 (sim_firmware_command): New function.
711 (mips_option_handler): Call it for OPTION_FIRMWARE.
712 (sim_open): Allocate memory for idt_monitor region. If "--board"
713 option was given, add no monitor by default. Add BREAK hooks only if
714 monitors are also there.
715
43e526b9
JM		 716Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
717
718 * interp.c (sim_monitor): Flush output before reading input.
719
720Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
721
722 * tconfig.in (SIM_HANDLES_LMA): Always define.
723
724Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
725
726 From Mark Salter <msalter@cygnus.com>:
727 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
728 (sim_open): Add setup for BSP board.
729
9846de1b
JM		 730Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
731
732 * mips.igen (MULT, MULTU): Add syntax for two operand version.
733 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
734 them as unimplemented.
735
cd0fc7c3
SS		 7361999-05-08 Felix Lee <flee@cygnus.com>
737
738 * configure: Regenerated to track ../common/aclocal.m4 changes.
739
7a292a7a
SS		 7401999-04-21 Frank Ch. Eigler <fche@cygnus.com>
741
742 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
743
744Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
745
746 * configure.in: Any mips64vr5*-*-* target should have
747 -DTARGET_ENABLE_FR=1.
748 (default_endian): Any mips64vr*el-*-* target should default to
749 LITTLE_ENDIAN.
750 * configure: Re-generate.
751
7521999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
753
754 * mips.igen (ldl): Extend from _16_, not 32.
755
756Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
757
758 * interp.c (sim_store_register): Force registers written to by GDB
759 into an un-interpreted state.
760
c906108c
SS		 7611999-02-05 Frank Ch. Eigler <fche@cygnus.com>
762
763 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
764 CPU, start periodic background I/O polls.
765 (tx3904sio_poll): New function: periodic I/O poller.
766
7671998-12-30 Frank Ch. Eigler <fche@cygnus.com>
768
769 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
770
771Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
772
773 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
774 case statement.
775
7761998-12-29 Frank Ch. Eigler <fche@cygnus.com>
777
778 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
779 (load_word): Call SIM_CORE_SIGNAL hook on error.
780 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
781 starting. For exception dispatching, pass PC instead of NULL_CIA.
782 (decode_coproc): Use COP0_BADVADDR to store faulting address.
783 * sim-main.h (COP0_BADVADDR): Define.
784 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
785 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
786 (_sim_cpu): Add exc_* fields to store register value snapshots.
787 * mips.igen (*): Replace memory-related SignalException* calls
788 with references to SIM_CORE_SIGNAL hook.
789
790 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
791 fix.
792 * sim-main.c (*): Minor warning cleanups.
793
7941998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
795
796 * m16.igen (DADDIU5): Correct type-o.
797
798Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
799
800 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
801 variables.
802
803Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
804
805 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
806 to include path.
807 (interp.o): Add dependency on itable.h
808 (oengine.c, gencode): Delete remaining references.
809 (BUILT_SRC_FROM_GEN): Clean up.
810
8111998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
812
813 * vr4run.c: New.
814 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
815 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
816 tmp-run-hack) : New.
817 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
818 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
819 Drop the "64" qualifier to get the HACK generator working.
820 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
821 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
822 qualifier to get the hack generator working.
823 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
824 (DSLL): Use do_dsll.
825 (DSLLV): Use do_dsllv.
826 (DSRA): Use do_dsra.
827 (DSRL): Use do_dsrl.
828 (DSRLV): Use do_dsrlv.
829 (BC1): Move *vr4100 to get the HACK generator working.
830 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
831 get the HACK generator working.
832 (MACC) Rename to get the HACK generator working.
833 (DMACC,MACCS,DMACCS): Add the 64.
834
8351998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
836
837 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
838 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
839
8401998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
841
842 * mips/interp.c (DEBUG): Cleanups.
843
8441998-12-10 Frank Ch. Eigler <fche@cygnus.com>
845
846 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
847 (tx3904sio_tickle): fflush after a stdout character output.
848
8491998-12-03 Frank Ch. Eigler <fche@cygnus.com>
850
851 * interp.c (sim_close): Uninstall modules.
852
853Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
854
855 * sim-main.h, interp.c (sim_monitor): Change to global
856 function.
857
858Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
859
860 * configure.in (vr4100): Only include vr4100 instructions in
861 simulator.
862 * configure: Re-generate.
863 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
864
865Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
866
867 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
868 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
869 true alternative.
870
871 * configure.in (sim_default_gen, sim_use_gen): Replace with
872 sim_gen.
873 (--enable-sim-igen): Delete config option. Always using IGEN.
874 * configure: Re-generate.
875
876 * Makefile.in (gencode): Kill, kill, kill.
877 * gencode.c: Ditto.
878
879Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
880
881 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
882 bit mips16 igen simulator.
883 * configure: Re-generate.
884
885 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
886 as part of vr4100 ISA.
887 * vr.igen: Mark all instructions as 64 bit only.
888
889Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
890
891 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
892 Pacify GCC.
893
894Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
895
896 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
897 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
898 * configure: Re-generate.
899
900 * m16.igen (BREAK): Define breakpoint instruction.
901 (JALX32): Mark instruction as mips16 and not r3900.
902 * mips.igen (C.cond.fmt): Fix typo in instruction format.
903
904 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
905
906Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
907
908 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
909 insn as a debug breakpoint.
910
911 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
912 pending.slot_size.
913 (PENDING_SCHED): Clean up trace statement.
914 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
915 (PENDING_FILL): Delay write by only one cycle.
916 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
917
918 * sim-main.c (pending_tick): Clean up trace statements. Add trace
919 of pending writes.
920 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
921 32 & 64.
922 (pending_tick): Move incrementing of index to FOR statement.
923 (pending_tick): Only update PENDING_OUT after a write has occured.
924
925 * configure.in: Add explicit mips-lsi-* target. Use gencode to
926 build simulator.
927 * configure: Re-generate.
928
929 * interp.c (sim_engine_run OLD): Delete explicit call to
930 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
931
932Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
933
934 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
935 interrupt level number to match changed SignalExceptionInterrupt
936 macro.
937
938Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
939
940 * interp.c: #include "itable.h" if WITH_IGEN.
941 (get_insn_name): New function.
942 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
943 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
944
945Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
946
947 * configure: Rebuilt to inhale new common/aclocal.m4.
948
949Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
950
951 * dv-tx3904sio.c: Include sim-assert.h.
952
953Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
954
955 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
956 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
957 Reorganize target-specific sim-hardware checks.
958 * configure: rebuilt.
959 * interp.c (sim_open): For tx39 target boards, set
960 OPERATING_ENVIRONMENT, add tx3904sio devices.
961 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
962 ROM executables. Install dv-sockser into sim-modules list.
963
964 * dv-tx3904irc.c: Compiler warning clean-up.
965 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
966 frequent hw-trace messages.
967
968Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
969
970 * vr.igen (MulAcc): Identify as a vr4100 specific function.
971
972Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
973
974 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
975
976 * vr.igen: New file.
977 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
978 * mips.igen: Define vr4100 model. Include vr.igen.
979Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
980
981 * mips.igen (check_mf_hilo): Correct check.
982
983Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
984
985 * sim-main.h (interrupt_event): Add prototype.
986
987 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
988 register_ptr, register_value.
989 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
990
991 * sim-main.h (tracefh): Make extern.
992
993Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
994
995 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
996 Reduce unnecessarily high timer event frequency.
997 * dv-tx3904cpu.c: Ditto for interrupt event.
998
999Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1000
1001 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1002 to allay warnings.
1003 (interrupt_event): Made non-static.
1004
1005 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1006 interchange of configuration values for external vs. internal
1007 clock dividers.
1008
1009Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1010
1011 * mips.igen (BREAK): Moved code to here for
1012 simulator-reserved break instructions.
1013 * gencode.c (build_instruction): Ditto.
1014 * interp.c (signal_exception): Code moved from here. Non-
1015 reserved instructions now use exception vector, rather
1016 than halting sim.
1017 * sim-main.h: Moved magic constants to here.
1018
1019Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1020
1021 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1022 register upon non-zero interrupt event level, clear upon zero
1023 event value.
1024 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1025 by passing zero event value.
1026 (*_io_{read,write}_buffer): Endianness fixes.
1027 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1028 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1029
1030 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1031 serial I/O and timer module at base address 0xFFFF0000.
1032
1033Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1034
1035 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1036 and BigEndianCPU.
1037
1038Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1039
1040 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1041 parts.
1042 * configure: Update.
1043
1044Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1045
1046 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1047 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1048 * configure.in: Include tx3904tmr in hw_device list.
1049 * configure: Rebuilt.
1050 * interp.c (sim_open): Instantiate three timer instances.
1051 Fix address typo of tx3904irc instance.
1052
1053Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1054
1055 * interp.c (signal_exception): SystemCall exception now uses
1056 the exception vector.
1057
1058Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1059
1060 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1061 to allay warnings.
1062
1063Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1064
1065 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1066
1067Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1068
1069 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1070
1071 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1072 sim-main.h. Declare a struct hw_descriptor instead of struct
1073 hw_device_descriptor.
1074
1075Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1076
1077 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1078 right bits and then re-align left hand bytes to correct byte
1079 lanes. Fix incorrect computation in do_store_left when loading
1080 bytes from second word.
1081
1082Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1083
1084 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1085 * interp.c (sim_open): Only create a device tree when HW is
1086 enabled.
1087
1088 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1089 * interp.c (signal_exception): Ditto.
1090
1091Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1092
1093 * gencode.c: Mark BEGEZALL as LIKELY.
1094
1095Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1096
1097 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1098 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1099
1100Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1101
1102 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1103 modules. Recognize TX39 target with "mips*tx39" pattern.
1104 * configure: Rebuilt.
1105 * sim-main.h (*): Added many macros defining bits in
1106 TX39 control registers.
1107 (SignalInterrupt): Send actual PC instead of NULL.
1108 (SignalNMIReset): New exception type.
1109 * interp.c (board): New variable for future use to identify
1110 a particular board being simulated.
1111 (mips_option_handler,mips_options): Added "--board" option.
1112 (interrupt_event): Send actual PC.
1113 (sim_open): Make memory layout conditional on board setting.
1114 (signal_exception): Initial implementation of hardware interrupt
1115 handling. Accept another break instruction variant for simulator
1116 exit.
1117 (decode_coproc): Implement RFE instruction for TX39.
1118 (mips.igen): Decode RFE instruction as such.
1119 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1120 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1121 bbegin to implement memory map.
1122 * dv-tx3904cpu.c: New file.
1123 * dv-tx3904irc.c: New file.
1124
1125Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1126
1127 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1128
1129Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1130
1131 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1132 with calls to check_div_hilo.
1133
1134Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1135
1136 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1137 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1138 Add special r3900 version of do_mult_hilo.
1139 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1140 with calls to check_mult_hilo.
1141 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1142 with calls to check_div_hilo.
1143
1144Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1145
1146 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1147 Document a replacement.
1148
1149Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1150
1151 * interp.c (sim_monitor): Make mon_printf work.
1152
1153Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1154
1155 * sim-main.h (INSN_NAME): New arg `cpu'.
1156
1157Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1158
1159 * configure: Regenerated to track ../common/aclocal.m4 changes.
1160
1161Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1162
1163 * configure: Regenerated to track ../common/aclocal.m4 changes.
1164 * config.in: Ditto.
1165
1166Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1167
1168 * acconfig.h: New file.
1169 * configure.in: Reverted change of Apr 24; use sinclude again.
1170
1171Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1172
1173 * configure: Regenerated to track ../common/aclocal.m4 changes.
1174 * config.in: Ditto.
1175
1176Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1177
1178 * configure.in: Don't call sinclude.
1179
1180Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1181
1182 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1183
1184Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1185
1186 * mips.igen (ERET): Implement.
1187
1188 * interp.c (decode_coproc): Return sign-extended EPC.
1189
1190 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1191
1192 * interp.c (signal_exception): Do not ignore Trap.
1193 (signal_exception): On TRAP, restart at exception address.
1194 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1195 (signal_exception): Update.
1196 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1197 so that TRAP instructions are caught.
1198
1199Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1200
1201 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1202 contains HI/LO access history.
1203 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1204 (HIACCESS, LOACCESS): Delete, replace with
1205 (HIHISTORY, LOHISTORY): New macros.
1206 (CHECKHILO): Delete all, moved to mips.igen
1207
1208 * gencode.c (build_instruction): Do not generate checks for
1209 correct HI/LO register usage.
1210
1211 * interp.c (old_engine_run): Delete checks for correct HI/LO
1212 register usage.
1213
1214 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1215 check_mf_cycles): New functions.
1216 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1217 do_divu, domultx, do_mult, do_multu): Use.
1218
1219 * tx.igen ("madd", "maddu"): Use.
1220
1221Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1222
1223 * mips.igen (DSRAV): Use function do_dsrav.
1224 (SRAV): Use new function do_srav.
1225
1226 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1227 (B): Sign extend 11 bit immediate.
1228 (EXT-B*): Shift 16 bit immediate left by 1.
1229 (ADDIU*): Don't sign extend immediate value.
1230
1231Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1232
1233 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1234
1235 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1236 functions.
1237
1238 * mips.igen (delayslot32, nullify_next_insn): New functions.
1239 (m16.igen): Always include.
1240 (do_*): Add more tracing.
1241
1242 * m16.igen (delayslot16): Add NIA argument, could be called by a
1243 32 bit MIPS16 instruction.
1244
1245 * interp.c (ifetch16): Move function from here.
1246 * sim-main.c (ifetch16): To here.
1247
1248 * sim-main.c (ifetch16, ifetch32): Update to match current
1249 implementations of LH, LW.
1250 (signal_exception): Don't print out incorrect hex value of illegal
1251 instruction.
1252
1253Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1254
1255 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1256 instruction.
1257
1258 * m16.igen: Implement MIPS16 instructions.
1259
1260 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1261 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1262 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1263 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1264 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1265 bodies of corresponding code from 32 bit insn to these. Also used
1266 by MIPS16 versions of functions.
1267
1268 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1269 (IMEM16): Drop NR argument from macro.
1270
1271Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1272
1273 * Makefile.in (SIM_OBJS): Add sim-main.o.
1274
1275 * sim-main.h (address_translation, load_memory, store_memory,
1276 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1277 as INLINE_SIM_MAIN.
1278 (pr_addr, pr_uword64): Declare.
1279 (sim-main.c): Include when H_REVEALS_MODULE_P.
1280
1281 * interp.c (address_translation, load_memory, store_memory,
1282 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1283 from here.
1284 * sim-main.c: To here. Fix compilation problems.
1285
1286 * configure.in: Enable inlining.
1287 * configure: Re-config.
1288
1289Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1290
1291 * configure: Regenerated to track ../common/aclocal.m4 changes.
1292
1293Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1294
1295 * mips.igen: Include tx.igen.
1296 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1297 * tx.igen: New file, contains MADD and MADDU.
1298
1299 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1300 the hardwired constant `7'.
1301 (store_memory): Ditto.
1302 (LOADDRMASK): Move definition to sim-main.h.
1303
1304 mips.igen (MTC0): Enable for r3900.
1305 (ADDU): Add trace.
1306
1307 mips.igen (do_load_byte): Delete.
1308 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1309 do_store_right): New functions.
1310 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1311
1312 configure.in: Let the tx39 use igen again.
1313 configure: Update.
1314
1315Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1316
1317 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1318 not an address sized quantity. Return zero for cache sizes.
1319
1320Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1321
1322 * mips.igen (r3900): r3900 does not support 64 bit integer
1323 operations.
1324
1325Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1326
1327 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1328 than igen one.
1329 * configure : Rebuild.
1330
1331Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1332
1333 * configure: Regenerated to track ../common/aclocal.m4 changes.
1334
1335Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1336
1337 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1338
1339Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1340
1341 * configure: Regenerated to track ../common/aclocal.m4 changes.
1342 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1343
1344Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1345
1346 * configure: Regenerated to track ../common/aclocal.m4 changes.
1347
1348Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1349
1350 * interp.c (Max, Min): Comment out functions. Not yet used.
1351
1352Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1353
1354 * configure: Regenerated to track ../common/aclocal.m4 changes.
1355
1356Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1357
1358 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1359 configurable settings for stand-alone simulator.
1360
1361 * configure.in: Added X11 search, just in case.
1362
1363 * configure: Regenerated.
1364
1365Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1366
1367 * interp.c (sim_write, sim_read, load_memory, store_memory):
1368 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1369
1370Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1371
1372 * sim-main.h (GETFCC): Return an unsigned value.
1373
1374Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1375
1376 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1377 (DADD): Result destination is RD not RT.
1378
1379Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1380
1381 * sim-main.h (HIACCESS, LOACCESS): Always define.
1382
1383 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1384
1385 * interp.c (sim_info): Delete.
1386
1387Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1388
1389 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1390 (mips_option_handler): New argument `cpu'.
1391 (sim_open): Update call to sim_add_option_table.
1392
1393Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1394
1395 * mips.igen (CxC1): Add tracing.
1396
1397Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1398
1399 * sim-main.h (Max, Min): Declare.
1400
1401 * interp.c (Max, Min): New functions.
1402
1403 * mips.igen (BC1): Add tracing.
1404
1405Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1406
1407 * interp.c Added memory map for stack in vr4100
1408
1409Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1410
1411 * interp.c (load_memory): Add missing "break"'s.
1412
1413Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1414
1415 * interp.c (sim_store_register, sim_fetch_register): Pass in
1416 length parameter. Return -1.
1417
1418Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1419
1420 * interp.c: Added hardware init hook, fixed warnings.
1421
1422Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1423
1424 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1425
1426Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1427
1428 * interp.c (ifetch16): New function.
1429
1430 * sim-main.h (IMEM32): Rename IMEM.
1431 (IMEM16_IMMED): Define.
1432 (IMEM16): Define.
1433 (DELAY_SLOT): Update.
1434
1435 * m16run.c (sim_engine_run): New file.
1436
1437 * m16.igen: All instructions except LB.
1438 (LB): Call do_load_byte.
1439 * mips.igen (do_load_byte): New function.
1440 (LB): Call do_load_byte.
1441
1442 * mips.igen: Move spec for insn bit size and high bit from here.
1443 * Makefile.in (tmp-igen, tmp-m16): To here.
1444
1445 * m16.dc: New file, decode mips16 instructions.
1446
1447 * Makefile.in (SIM_NO_ALL): Define.
1448 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1449
1450Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1451
1452 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1453 point unit to 32 bit registers.
1454 * configure: Re-generate.
1455
1456Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1457
1458 * configure.in (sim_use_gen): Make IGEN the default simulator
1459 generator for generic 32 and 64 bit mips targets.
1460 * configure: Re-generate.
1461
1462Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1463
1464 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1465 bitsize.
1466
1467 * interp.c (sim_fetch_register, sim_store_register): Read/write
1468 FGR from correct location.
1469 (sim_open): Set size of FGR's according to
1470 WITH_TARGET_FLOATING_POINT_BITSIZE.
1471
1472 * sim-main.h (FGR): Store floating point registers in a separate
1473 array.
1474
1475Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1476
1477 * configure: Regenerated to track ../common/aclocal.m4 changes.
1478
1479Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1480
1481 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1482
1483 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1484
1485 * interp.c (pending_tick): New function. Deliver pending writes.
1486
1487 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1488 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1489 it can handle mixed sized quantites and single bits.
1490
1491Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1492
1493 * interp.c (oengine.h): Do not include when building with IGEN.
1494 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1495 (sim_info): Ditto for PROCESSOR_64BIT.
1496 (sim_monitor): Replace ut_reg with unsigned_word.
1497 (*): Ditto for t_reg.
1498 (LOADDRMASK): Define.
1499 (sim_open): Remove defunct check that host FP is IEEE compliant,
1500 using software to emulate floating point.
1501 (value_fpr, ...): Always compile, was conditional on HASFPU.
1502
1503Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1504
1505 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1506 size.
1507
1508 * interp.c (SD, CPU): Define.
1509 (mips_option_handler): Set flags in each CPU.
1510 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1511 (sim_close): Do not clear STATE, deleted anyway.
1512 (sim_write, sim_read): Assume CPU zero's vm should be used for
1513 data transfers.
1514 (sim_create_inferior): Set the PC for all processors.
1515 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1516 argument.
1517 (mips16_entry): Pass correct nr of args to store_word, load_word.
1518 (ColdReset): Cold reset all cpu's.
1519 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1520 (sim_monitor, load_memory, store_memory, signal_exception): Use
1521 `CPU' instead of STATE_CPU.
1522
1523
1524 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1525 SD or CPU_.
1526
1527 * sim-main.h (signal_exception): Add sim_cpu arg.
1528 (SignalException*): Pass both SD and CPU to signal_exception.
1529 * interp.c (signal_exception): Update.
1530
1531 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1532 Ditto
1533 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1534 address_translation): Ditto
1535 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1536
1537Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1538
1539 * configure: Regenerated to track ../common/aclocal.m4 changes.
1540
1541Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1542
1543 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1544
1545 * mips.igen (model): Map processor names onto BFD name.
1546
1547 * sim-main.h (CPU_CIA): Delete.
1548 (SET_CIA, GET_CIA): Define
1549
1550Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1551
1552 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1553 regiser.
1554
1555 * configure.in (default_endian): Configure a big-endian simulator
1556 by default.
1557 * configure: Re-generate.
1558
1559Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1560
1561 * configure: Regenerated to track ../common/aclocal.m4 changes.
1562
1563Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1564
1565 * interp.c (sim_monitor): Handle Densan monitor outbyte
1566 and inbyte functions.
1567
15681997-12-29 Felix Lee <flee@cygnus.com>
1569
1570 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1571
1572Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1573
1574 * Makefile.in (tmp-igen): Arrange for $zero to always be
1575 reset to zero after every instruction.
1576
1577Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1578
1579 * configure: Regenerated to track ../common/aclocal.m4 changes.
1580 * config.in: Ditto.
1581
1582Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1583
1584 * mips.igen (MSUB): Fix to work like MADD.
1585 * gencode.c (MSUB): Similarly.
1586
1587Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1588
1589 * configure: Regenerated to track ../common/aclocal.m4 changes.
1590
1591Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1592
1593 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1594
1595Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1596
1597 * sim-main.h (sim-fpu.h): Include.
1598
1599 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1600 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1601 using host independant sim_fpu module.
1602
1603Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1604
1605 * interp.c (signal_exception): Report internal errors with SIGABRT
1606 not SIGQUIT.
1607
1608 * sim-main.h (C0_CONFIG): New register.
1609 (signal.h): No longer include.
1610
1611 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1612
1613Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1614
1615 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1616
1617Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1618
1619 * mips.igen: Tag vr5000 instructions.
1620 (ANDI): Was missing mipsIV model, fix assembler syntax.
1621 (do_c_cond_fmt): New function.
1622 (C.cond.fmt): Handle mips I-III which do not support CC field
1623 separatly.
1624 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1625 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1626 in IV3.2 spec.
1627 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1628 vr5000 which saves LO in a GPR separatly.
1629
1630 * configure.in (enable-sim-igen): For vr5000, select vr5000
1631 specific instructions.
1632 * configure: Re-generate.
1633
1634Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1635
1636 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1637
1638 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1639 fmt_uninterpreted_64 bit cases to switch. Convert to
1640 fmt_formatted,
1641
1642 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1643
1644 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1645 as specified in IV3.2 spec.
1646 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1647
1648Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1649
1650 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1651 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1652 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1653 PENDING_FILL versions of instructions. Simplify.
1654 (X): New function.
1655 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1656 instructions.
1657 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1658 a signed value.
1659 (MTHI, MFHI): Disable code checking HI-LO.
1660
1661 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1662 global.
1663 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1664
1665Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1666
1667 * gencode.c (build_mips16_operands): Replace IPC with cia.
1668
1669 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1670 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1671 IPC to `cia'.
1672 (UndefinedResult): Replace function with macro/function
1673 combination.
1674 (sim_engine_run): Don't save PC in IPC.
1675
1676 * sim-main.h (IPC): Delete.
1677
1678
1679 * interp.c (signal_exception, store_word, load_word,
1680 address_translation, load_memory, store_memory, cache_op,
1681 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1682 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1683 current instruction address - cia - argument.
1684 (sim_read, sim_write): Call address_translation directly.
1685 (sim_engine_run): Rename variable vaddr to cia.
1686 (signal_exception): Pass cia to sim_monitor
1687
1688 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1689 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1690 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1691
1692 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1693 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1694 SIM_ASSERT.
1695
1696 * interp.c (signal_exception): Pass restart address to
1697 sim_engine_restart.
1698
1699 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1700 idecode.o): Add dependency.
1701
1702 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1703 Delete definitions
1704 (DELAY_SLOT): Update NIA not PC with branch address.
1705 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1706
1707 * mips.igen: Use CIA not PC in branch calculations.
1708 (illegal): Call SignalException.
1709 (BEQ, ADDIU): Fix assembler.
1710
1711Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1712
1713 * m16.igen (JALX): Was missing.
1714
1715 * configure.in (enable-sim-igen): New configuration option.
1716 * configure: Re-generate.
1717
1718 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1719
1720 * interp.c (load_memory, store_memory): Delete parameter RAW.
1721 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1722 bypassing {load,store}_memory.
1723
1724 * sim-main.h (ByteSwapMem): Delete definition.
1725
1726 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1727
1728 * interp.c (sim_do_command, sim_commands): Delete mips specific
1729 commands. Handled by module sim-options.
1730
1731 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1732 (WITH_MODULO_MEMORY): Define.
1733
1734 * interp.c (sim_info): Delete code printing memory size.
1735
1736 * interp.c (mips_size): Nee sim_size, delete function.
1737 (power2): Delete.
1738 (monitor, monitor_base, monitor_size): Delete global variables.
1739 (sim_open, sim_close): Delete code creating monitor and other
1740 memory regions. Use sim-memopts module, via sim_do_commandf, to
1741 manage memory regions.
1742 (load_memory, store_memory): Use sim-core for memory model.
1743
1744 * interp.c (address_translation): Delete all memory map code
1745 except line forcing 32 bit addresses.
1746
1747Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1748
1749 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1750 trace options.
1751
1752 * interp.c (logfh, logfile): Delete globals.
1753 (sim_open, sim_close): Delete code opening & closing log file.
1754 (mips_option_handler): Delete -l and -n options.
1755 (OPTION mips_options): Ditto.
1756
1757 * interp.c (OPTION mips_options): Rename option trace to dinero.
1758 (mips_option_handler): Update.
1759
1760Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1761
1762 * interp.c (fetch_str): New function.
1763 (sim_monitor): Rewrite using sim_read & sim_write.
1764 (sim_open): Check magic number.
1765 (sim_open): Write monitor vectors into memory using sim_write.
1766 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1767 (sim_read, sim_write): Simplify - transfer data one byte at a
1768 time.
1769 (load_memory, store_memory): Clarify meaning of parameter RAW.
1770
1771 * sim-main.h (isHOST): Defete definition.
1772 (isTARGET): Mark as depreciated.
1773 (address_translation): Delete parameter HOST.
1774
1775 * interp.c (address_translation): Delete parameter HOST.
1776
1777Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1778
1779 * mips.igen:
1780
1781 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1782 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1783
1784Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1785
1786 * mips.igen: Add model filter field to records.
1787
1788Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1789
1790 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1791
1792 interp.c (sim_engine_run): Do not compile function sim_engine_run
1793 when WITH_IGEN == 1.
1794
1795 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1796 target architecture.
1797
1798 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1799 igen. Replace with configuration variables sim_igen_flags /
1800 sim_m16_flags.
1801
1802 * m16.igen: New file. Copy mips16 insns here.
1803 * mips.igen: From here.
1804
1805Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1806
1807 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1808 to top.
1809 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1810
1811Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1812
1813 * gencode.c (build_instruction): Follow sim_write's lead in using
1814 BigEndianMem instead of !ByteSwapMem.
1815
1816Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1817
1818 * configure.in (sim_gen): Dependent on target, select type of
1819 generator. Always select old style generator.
1820
1821 configure: Re-generate.
1822
1823 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1824 targets.
1825 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1826 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1827 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1828 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1829 SIM_@sim_gen@_*, set by autoconf.
1830
1831Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1832
1833 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1834
1835 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1836 CURRENT_FLOATING_POINT instead.
1837
1838 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1839 (address_translation): Raise exception InstructionFetch when
1840 translation fails and isINSTRUCTION.
1841
1842 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1843 sim_engine_run): Change type of of vaddr and paddr to
1844 address_word.
1845 (address_translation, prefetch, load_memory, store_memory,
1846 cache_op): Change type of vAddr and pAddr to address_word.
1847
1848 * gencode.c (build_instruction): Change type of vaddr and paddr to
1849 address_word.
1850
1851Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1852
1853 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1854 macro to obtain result of ALU op.
1855
1856Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1857
1858 * interp.c (sim_info): Call profile_print.
1859
1860Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1861
1862 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1863
1864 * sim-main.h (WITH_PROFILE): Do not define, defined in
1865 common/sim-config.h. Use sim-profile module.
1866 (simPROFILE): Delete defintion.
1867
1868 * interp.c (PROFILE): Delete definition.
1869 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1870 (sim_close): Delete code writing profile histogram.
1871 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1872 Delete.
1873 (sim_engine_run): Delete code profiling the PC.
1874
1875Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1876
1877 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1878
1879 * interp.c (sim_monitor): Make register pointers of type
1880 unsigned_word*.
1881
1882 * sim-main.h: Make registers of type unsigned_word not
1883 signed_word.
1884
1885Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1886
1887 * interp.c (sync_operation): Rename from SyncOperation, make
1888 global, add SD argument.
1889 (prefetch): Rename from Prefetch, make global, add SD argument.
1890 (decode_coproc): Make global.
1891
1892 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1893
1894 * gencode.c (build_instruction): Generate DecodeCoproc not
1895 decode_coproc calls.
1896
1897 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1898 (SizeFGR): Move to sim-main.h
1899 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1900 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1901 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1902 sim-main.h.
1903 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1904 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1905 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1906 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1907 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1908 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1909
1910 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1911 exception.
1912 (sim-alu.h): Include.
1913 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1914 (sim_cia): Typedef to instruction_address.
1915
1916Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1917
1918 * Makefile.in (interp.o): Rename generated file engine.c to
1919 oengine.c.
1920
1921 * interp.c: Update.
1922
1923Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1924
1925 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1926
1927Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1928
1929 * gencode.c (build_instruction): For "FPSQRT", output correct
1930 number of arguments to Recip.
1931
1932Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1933
1934 * Makefile.in (interp.o): Depends on sim-main.h
1935
1936 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1937
1938 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1939 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1940 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1941 STATE, DSSTATE): Define
1942 (GPR, FGRIDX, ..): Define.
1943
1944 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1945 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1946 (GPR, FGRIDX, ...): Delete macros.
1947
1948 * interp.c: Update names to match defines from sim-main.h
1949
1950Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1951
1952 * interp.c (sim_monitor): Add SD argument.
1953 (sim_warning): Delete. Replace calls with calls to
1954 sim_io_eprintf.
1955 (sim_error): Delete. Replace calls with sim_io_error.
1956 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1957 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1958 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1959 argument.
1960 (mips_size): Rename from sim_size. Add SD argument.
1961
1962 * interp.c (simulator): Delete global variable.
1963 (callback): Delete global variable.
1964 (mips_option_handler, sim_open, sim_write, sim_read,
1965 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1966 sim_size,sim_monitor): Use sim_io_* not callback->*.
1967 (sim_open): ZALLOC simulator struct.
1968 (PROFILE): Do not define.
1969
1970Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1971
1972 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1973 support.h with corresponding code.
1974
1975 * sim-main.h (word64, uword64), support.h: Move definition to
1976 sim-main.h.
1977 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1978
1979 * support.h: Delete
1980 * Makefile.in: Update dependencies
1981 * interp.c: Do not include.
1982
1983Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1984
1985 * interp.c (address_translation, load_memory, store_memory,
1986 cache_op): Rename to from AddressTranslation et.al., make global,
1987 add SD argument
1988
1989 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1990 CacheOp): Define.
1991
1992 * interp.c (SignalException): Rename to signal_exception, make
1993 global.
1994
1995 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1996
1997 * sim-main.h (SignalException, SignalExceptionInterrupt,
1998 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1999 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2000 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2001 Define.
2002
2003 * interp.c, support.h: Use.
2004
2005Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2006
2007 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2008 to value_fpr / store_fpr. Add SD argument.
2009 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2010 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2011
2012 * sim-main.h (ValueFPR, StoreFPR): Define.
2013
2014Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2015
2016 * interp.c (sim_engine_run): Check consistency between configure
2017 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2018 and HASFPU.
2019
2020 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2021 (mips_fpu): Configure WITH_FLOATING_POINT.
2022 (mips_endian): Configure WITH_TARGET_ENDIAN.
2023 * configure: Update.
2024
2025Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2026
2027 * configure: Regenerated to track ../common/aclocal.m4 changes.
2028
2029Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2030
2031 * configure: Regenerated.
2032
2033Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2034
2035 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2036
2037Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2038
2039 * gencode.c (print_igen_insn_models): Assume certain architectures
2040 include all mips* instructions.
2041 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2042 instruction.
2043
2044 * Makefile.in (tmp.igen): Add target. Generate igen input from
2045 gencode file.
2046
2047 * gencode.c (FEATURE_IGEN): Define.
2048 (main): Add --igen option. Generate output in igen format.
2049 (process_instructions): Format output according to igen option.
2050 (print_igen_insn_format): New function.
2051 (print_igen_insn_models): New function.
2052 (process_instructions): Only issue warnings and ignore
2053 instructions when no FEATURE_IGEN.
2054
2055Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2056
2057 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2058 MIPS targets.
2059
2060Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2061
2062 * configure: Regenerated to track ../common/aclocal.m4 changes.
2063
2064Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2065
2066 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2067 SIM_RESERVED_BITS): Delete, moved to common.
2068 (SIM_EXTRA_CFLAGS): Update.
2069
2070Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2071
2072 * configure.in: Configure non-strict memory alignment.
2073 * configure: Regenerated to track ../common/aclocal.m4 changes.
2074
2075Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2076
2077 * configure: Regenerated to track ../common/aclocal.m4 changes.
2078
2079Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2080
2081 * gencode.c (SDBBP,DERET): Added (3900) insns.
2082 (RFE): Turn on for 3900.
2083 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2084 (dsstate): Made global.
2085 (SUBTARGET_R3900): Added.
2086 (CANCELDELAYSLOT): New.
2087 (SignalException): Ignore SystemCall rather than ignore and
2088 terminate. Add DebugBreakPoint handling.
2089 (decode_coproc): New insns RFE, DERET; and new registers Debug
2090 and DEPC protected by SUBTARGET_R3900.
2091 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2092 bits explicitly.
2093 * Makefile.in,configure.in: Add mips subtarget option.
2094 * configure: Update.
2095
2096Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2097
2098 * gencode.c: Add r3900 (tx39).
2099
2100
2101Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2102
2103 * gencode.c (build_instruction): Don't need to subtract 4 for
2104 JALR, just 2.
2105
2106Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2107
2108 * interp.c: Correct some HASFPU problems.
2109
2110Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2111
2112 * configure: Regenerated to track ../common/aclocal.m4 changes.
2113
2114Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2115
2116 * interp.c (mips_options): Fix samples option short form, should
2117 be `x'.
2118
2119Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2120
2121 * interp.c (sim_info): Enable info code. Was just returning.
2122
2123Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2124
2125 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2126 MFC0.
2127
2128Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2129
2130 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2131 constants.
2132 (build_instruction): Ditto for LL.
2133
2134Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2135
2136 * configure: Regenerated to track ../common/aclocal.m4 changes.
2137
2138Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2139
2140 * configure: Regenerated to track ../common/aclocal.m4 changes.
2141 * config.in: Ditto.
2142
2143Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2144
2145 * interp.c (sim_open): Add call to sim_analyze_program, update
2146 call to sim_config.
2147
2148Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2149
2150 * interp.c (sim_kill): Delete.
2151 (sim_create_inferior): Add ABFD argument. Set PC from same.
2152 (sim_load): Move code initializing trap handlers from here.
2153 (sim_open): To here.
2154 (sim_load): Delete, use sim-hload.c.
2155
2156 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2157
2158Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2159
2160 * configure: Regenerated to track ../common/aclocal.m4 changes.
2161 * config.in: Ditto.
2162
2163Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2164
2165 * interp.c (sim_open): Add ABFD argument.
2166 (sim_load): Move call to sim_config from here.
2167 (sim_open): To here. Check return status.
2168
2169Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2170
2171 * gencode.c (build_instruction): Two arg MADD should
2172 not assign result to $0.
2173
2174Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2175
2176 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2177 * sim/mips/configure.in: Regenerate.
2178
2179Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2180
2181 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2182 signed8, unsigned8 et.al. types.
2183
2184 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2185 hosts when selecting subreg.
2186
2187Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2188
2189 * interp.c (sim_engine_run): Reset the ZERO register to zero
2190 regardless of FEATURE_WARN_ZERO.
2191 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2192
2193Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2194
2195 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2196 (SignalException): For BreakPoints ignore any mode bits and just
2197 save the PC.
2198 (SignalException): Always set the CAUSE register.
2199
2200Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2201
2202 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2203 exception has been taken.
2204
2205 * interp.c: Implement the ERET and mt/f sr instructions.
2206
2207Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2208
2209 * interp.c (SignalException): Don't bother restarting an
2210 interrupt.
2211
2212Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2213
2214 * interp.c (SignalException): Really take an interrupt.
2215 (interrupt_event): Only deliver interrupts when enabled.
2216
2217Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2218
2219 * interp.c (sim_info): Only print info when verbose.
2220 (sim_info) Use sim_io_printf for output.
2221
2222Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2223
2224 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2225 mips architectures.
2226
2227Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2228
2229 * interp.c (sim_do_command): Check for common commands if a
2230 simulator specific command fails.
2231
2232Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2233
2234 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2235 and simBE when DEBUG is defined.
2236
2237Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2238
2239 * interp.c (interrupt_event): New function. Pass exception event
2240 onto exception handler.
2241
2242 * configure.in: Check for stdlib.h.
2243 * configure: Regenerate.
2244
2245 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2246 variable declaration.
2247 (build_instruction): Initialize memval1.
2248 (build_instruction): Add UNUSED attribute to byte, bigend,
2249 reverse.
2250 (build_operands): Ditto.
2251
2252 * interp.c: Fix GCC warnings.
2253 (sim_get_quit_code): Delete.
2254
2255 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2256 * Makefile.in: Ditto.
2257 * configure: Re-generate.
2258
2259 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2260
2261Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2262
2263 * interp.c (mips_option_handler): New function parse argumes using
2264 sim-options.
2265 (myname): Replace with STATE_MY_NAME.
2266 (sim_open): Delete check for host endianness - performed by
2267 sim_config.
2268 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2269 (sim_open): Move much of the initialization from here.
2270 (sim_load): To here. After the image has been loaded and
2271 endianness set.
2272 (sim_open): Move ColdReset from here.
2273 (sim_create_inferior): To here.
2274 (sim_open): Make FP check less dependant on host endianness.
2275
2276 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2277 run.
2278 * interp.c (sim_set_callbacks): Delete.
2279
2280 * interp.c (membank, membank_base, membank_size): Replace with
2281 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2282 (sim_open): Remove call to callback->init. gdb/run do this.
2283
2284 * interp.c: Update
2285
2286 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2287
2288 * interp.c (big_endian_p): Delete, replaced by
2289 current_target_byte_order.
2290
2291Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2292
2293 * interp.c (host_read_long, host_read_word, host_swap_word,
2294 host_swap_long): Delete. Using common sim-endian.
2295 (sim_fetch_register, sim_store_register): Use H2T.
2296 (pipeline_ticks): Delete. Handled by sim-events.
2297 (sim_info): Update.
2298 (sim_engine_run): Update.
2299
2300Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2301
2302 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2303 reason from here.
2304 (SignalException): To here. Signal using sim_engine_halt.
2305 (sim_stop_reason): Delete, moved to common.
2306
2307Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2308
2309 * interp.c (sim_open): Add callback argument.
2310 (sim_set_callbacks): Delete SIM_DESC argument.
2311 (sim_size): Ditto.
2312
2313Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2314
2315 * Makefile.in (SIM_OBJS): Add common modules.
2316
2317 * interp.c (sim_set_callbacks): Also set SD callback.
2318 (set_endianness, xfer_*, swap_*): Delete.
2319 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2320 Change to functions using sim-endian macros.
2321 (control_c, sim_stop): Delete, use common version.
2322 (simulate): Convert into.
2323 (sim_engine_run): This function.
2324 (sim_resume): Delete.
2325
2326 * interp.c (simulation): New variable - the simulator object.
2327 (sim_kind): Delete global - merged into simulation.
2328 (sim_load): Cleanup. Move PC assignment from here.
2329 (sim_create_inferior): To here.
2330
2331 * sim-main.h: New file.
2332 * interp.c (sim-main.h): Include.
2333
2334Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2335
2336 * configure: Regenerated to track ../common/aclocal.m4 changes.
2337
2338Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2339
2340 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2341
2342Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2343
2344 * gencode.c (build_instruction): DIV instructions: check
2345 for division by zero and integer overflow before using
2346 host's division operation.
2347
2348Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2349
2350 * Makefile.in (SIM_OBJS): Add sim-load.o.
2351 * interp.c: #include bfd.h.
2352 (target_byte_order): Delete.
2353 (sim_kind, myname, big_endian_p): New static locals.
2354 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2355 after argument parsing. Recognize -E arg, set endianness accordingly.
2356 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2357 load file into simulator. Set PC from bfd.
2358 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2359 (set_endianness): Use big_endian_p instead of target_byte_order.
2360
2361Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2362
2363 * interp.c (sim_size): Delete prototype - conflicts with
2364 definition in remote-sim.h. Correct definition.
2365
2366Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2367
2368 * configure: Regenerated to track ../common/aclocal.m4 changes.
2369 * config.in: Ditto.
2370
2371Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2372
2373 * interp.c (sim_open): New arg `kind'.
2374
2375 * configure: Regenerated to track ../common/aclocal.m4 changes.
2376
2377Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2378
2379 * configure: Regenerated to track ../common/aclocal.m4 changes.
2380
2381Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2382
2383 * interp.c (sim_open): Set optind to 0 before calling getopt.
2384
2385Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2386
2387 * configure: Regenerated to track ../common/aclocal.m4 changes.
2388
2389Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2390
2391 * interp.c : Replace uses of pr_addr with pr_uword64
2392 where the bit length is always 64 independent of SIM_ADDR.
2393 (pr_uword64) : added.
2394
2395Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2396
2397 * configure: Re-generate.
2398
2399Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2400
2401 * configure: Regenerate to track ../common/aclocal.m4 changes.
2402
2403Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2404
2405 * interp.c (sim_open): New SIM_DESC result. Argument is now
2406 in argv form.
2407 (other sim_*): New SIM_DESC argument.
2408
2409Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2410
2411 * interp.c: Fix printing of addresses for non-64-bit targets.
2412 (pr_addr): Add function to print address based on size.
2413
2414Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2415
2416 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2417
2418Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2419
2420 * gencode.c (build_mips16_operands): Correct computation of base
2421 address for extended PC relative instruction.
2422
2423Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2424
2425 * interp.c (mips16_entry): Add support for floating point cases.
2426 (SignalException): Pass floating point cases to mips16_entry.
2427 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2428 registers.
2429 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2430 or fmt_word.
2431 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2432 and then set the state to fmt_uninterpreted.
2433 (COP_SW): Temporarily set the state to fmt_word while calling
2434 ValueFPR.
2435
2436Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2437
2438 * gencode.c (build_instruction): The high order may be set in the
2439 comparison flags at any ISA level, not just ISA 4.
2440
2441Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2442
2443 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2444 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2445 * configure.in: sinclude ../common/aclocal.m4.
2446 * configure: Regenerated.
2447
2448Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2449
2450 * configure: Rebuild after change to aclocal.m4.
2451
2452Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2453
2454 * configure configure.in Makefile.in: Update to new configure
2455 scheme which is more compatible with WinGDB builds.
2456 * configure.in: Improve comment on how to run autoconf.
2457 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2458 * Makefile.in: Use autoconf substitution to install common
2459 makefile fragment.
2460
2461Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2462
2463 * gencode.c (build_instruction): Use BigEndianCPU instead of
2464 ByteSwapMem.
2465
2466Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2467
2468 * interp.c (sim_monitor): Make output to stdout visible in
2469 wingdb's I/O log window.
2470
2471Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2472
2473 * support.h: Undo previous change to SIGTRAP
2474 and SIGQUIT values.
2475
2476Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2477
2478 * interp.c (store_word, load_word): New static functions.
2479 (mips16_entry): New static function.
2480 (SignalException): Look for mips16 entry and exit instructions.
2481 (simulate): Use the correct index when setting fpr_state after
2482 doing a pending move.
2483
2484Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2485
2486 * interp.c: Fix byte-swapping code throughout to work on
2487 both little- and big-endian hosts.
2488
2489Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2490
2491 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2492 with gdb/config/i386/xm-windows.h.
2493
2494Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2495
2496 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2497 that messes up arithmetic shifts.
2498
2499Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2500
2501 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2502 SIGTRAP and SIGQUIT for _WIN32.
2503
2504Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2505
2506 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2507 force a 64 bit multiplication.
2508 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2509 destination register is 0, since that is the default mips16 nop
2510 instruction.
2511
2512Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2513
2514 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2515 (build_endian_shift): Don't check proc64.
2516 (build_instruction): Always set memval to uword64. Cast op2 to
2517 uword64 when shifting it left in memory instructions. Always use
2518 the same code for stores--don't special case proc64.
2519
2520 * gencode.c (build_mips16_operands): Fix base PC value for PC
2521 relative operands.
2522 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2523 jal instruction.
2524 * interp.c (simJALDELAYSLOT): Define.
2525 (JALDELAYSLOT): Define.
2526 (INDELAYSLOT, INJALDELAYSLOT): Define.
2527 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2528
2529Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2530
2531 * interp.c (sim_open): add flush_cache as a PMON routine
2532 (sim_monitor): handle flush_cache by ignoring it
2533
2534Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2535
2536 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2537 BigEndianMem.
2538 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2539 (BigEndianMem): Rename to ByteSwapMem and change sense.
2540 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2541 BigEndianMem references to !ByteSwapMem.
2542 (set_endianness): New function, with prototype.
2543 (sim_open): Call set_endianness.
2544 (sim_info): Use simBE instead of BigEndianMem.
2545 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2546 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2547 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2548 ifdefs, keeping the prototype declaration.
2549 (swap_word): Rewrite correctly.
2550 (ColdReset): Delete references to CONFIG. Delete endianness related
2551 code; moved to set_endianness.
2552
2553Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2554
2555 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2556 * interp.c (CHECKHILO): Define away.
2557 (simSIGINT): New macro.
2558 (membank_size): Increase from 1MB to 2MB.
2559 (control_c): New function.
2560 (sim_resume): Rename parameter signal to signal_number. Add local
2561 variable prev. Call signal before and after simulate.
2562 (sim_stop_reason): Add simSIGINT support.
2563 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2564 functions always.
2565 (sim_warning): Delete call to SignalException. Do call printf_filtered
2566 if logfh is NULL.
2567 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2568 a call to sim_warning.
2569
2570Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2571
2572 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2573 16 bit instructions.
2574
2575Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2576
2577 Add support for mips16 (16 bit MIPS implementation):
2578 * gencode.c (inst_type): Add mips16 instruction encoding types.
2579 (GETDATASIZEINSN): Define.
2580 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2581 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2582 mtlo.
2583 (MIPS16_DECODE): New table, for mips16 instructions.
2584 (bitmap_val): New static function.
2585 (struct mips16_op): Define.
2586 (mips16_op_table): New table, for mips16 operands.
2587 (build_mips16_operands): New static function.
2588 (process_instructions): If PC is odd, decode a mips16
2589 instruction. Break out instruction handling into new
2590 build_instruction function.
2591 (build_instruction): New static function, broken out of
2592 process_instructions. Check modifiers rather than flags for SHIFT
2593 bit count and m[ft]{hi,lo} direction.
2594 (usage): Pass program name to fprintf.
2595 (main): Remove unused variable this_option_optind. Change
2596 ``*loptarg++'' to ``loptarg++''.
2597 (my_strtoul): Parenthesize && within ||.
2598 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2599 (simulate): If PC is odd, fetch a 16 bit instruction, and
2600 increment PC by 2 rather than 4.
2601 * configure.in: Add case for mips16*-*-*.
2602 * configure: Rebuild.
2603
2604Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2605
2606 * interp.c: Allow -t to enable tracing in standalone simulator.
2607 Fix garbage output in trace file and error messages.
2608
2609Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2610
2611 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2612 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2613 * configure.in: Simplify using macros in ../common/aclocal.m4.
2614 * configure: Regenerated.
2615 * tconfig.in: New file.
2616
2617Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2618
2619 * interp.c: Fix bugs in 64-bit port.
2620 Use ansi function declarations for msvc compiler.
2621 Initialize and test file pointer in trace code.
2622 Prevent duplicate definition of LAST_EMED_REGNUM.
2623
2624Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2625
2626 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2627
2628Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2629
2630 * interp.c (SignalException): Check for explicit terminating
2631 breakpoint value.
2632 * gencode.c: Pass instruction value through SignalException()
2633 calls for Trap, Breakpoint and Syscall.
2634
2635Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2636
2637 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2638 only used on those hosts that provide it.
2639 * configure.in: Add sqrt() to list of functions to be checked for.
2640 * config.in: Re-generated.
2641 * configure: Re-generated.
2642
2643Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2644
2645 * gencode.c (process_instructions): Call build_endian_shift when
2646 expanding STORE RIGHT, to fix swr.
2647 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2648 clear the high bits.
2649 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2650 Fix float to int conversions to produce signed values.
2651
2652Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2653
2654 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2655 (process_instructions): Correct handling of nor instruction.
2656 Correct shift count for 32 bit shift instructions. Correct sign
2657 extension for arithmetic shifts to not shift the number of bits in
2658 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2659 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2660 Fix madd.
2661 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2662 It's OK to have a mult follow a mult. What's not OK is to have a
2663 mult follow an mfhi.
2664 (Convert): Comment out incorrect rounding code.
2665
2666Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2667
2668 * interp.c (sim_monitor): Improved monitor printf
2669 simulation. Tidied up simulator warnings, and added "--log" option
2670 for directing warning message output.
2671 * gencode.c: Use sim_warning() rather than WARNING macro.
2672
2673Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2674
2675 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2676 getopt1.o, rather than on gencode.c. Link objects together.
2677 Don't link against -liberty.
2678 (gencode.o, getopt.o, getopt1.o): New targets.
2679 * gencode.c: Include <ctype.h> and "ansidecl.h".
2680 (AND): Undefine after including "ansidecl.h".
2681 (ULONG_MAX): Define if not defined.
2682 (OP_*): Don't define macros; now defined in opcode/mips.h.
2683 (main): Call my_strtoul rather than strtoul.
2684 (my_strtoul): New static function.
2685
2686Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2687
2688 * gencode.c (process_instructions): Generate word64 and uword64
2689 instead of `long long' and `unsigned long long' data types.
2690 * interp.c: #include sysdep.h to get signals, and define default
2691 for SIGBUS.
2692 * (Convert): Work around for Visual-C++ compiler bug with type
2693 conversion.
2694 * support.h: Make things compile under Visual-C++ by using
2695 __int64 instead of `long long'. Change many refs to long long
2696 into word64/uword64 typedefs.
2697
2698Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2699
2700 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2701 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2702 (docdir): Removed.
2703 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2704 (AC_PROG_INSTALL): Added.
2705 (AC_PROG_CC): Moved to before configure.host call.
2706 * configure: Rebuilt.
2707
2708Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2709
2710 * configure.in: Define @SIMCONF@ depending on mips target.
2711 * configure: Rebuild.
2712 * Makefile.in (run): Add @SIMCONF@ to control simulator
2713 construction.
2714 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2715 * interp.c: Remove some debugging, provide more detailed error
2716 messages, update memory accesses to use LOADDRMASK.
2717
2718Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2719
2720 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2721 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2722 stamp-h.
2723 * configure: Rebuild.
2724 * config.in: New file, generated by autoheader.
2725 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2726 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2727 HAVE_ANINT and HAVE_AINT, as appropriate.
2728 * Makefile.in (run): Use @LIBS@ rather than -lm.
2729 (interp.o): Depend upon config.h.
2730 (Makefile): Just rebuild Makefile.
2731 (clean): Remove stamp-h.
2732 (mostlyclean): Make the same as clean, not as distclean.
2733 (config.h, stamp-h): New targets.
2734
2735Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2736
2737 * interp.c (ColdReset): Fix boolean test. Make all simulator
2738 globals static.
2739
2740Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2741
2742 * interp.c (xfer_direct_word, xfer_direct_long,
2743 swap_direct_word, swap_direct_long, xfer_big_word,
2744 xfer_big_long, xfer_little_word, xfer_little_long,
2745 swap_word,swap_long): Added.
2746 * interp.c (ColdReset): Provide function indirection to
2747 host<->simulated_target transfer routines.
2748 * interp.c (sim_store_register, sim_fetch_register): Updated to
2749 make use of indirected transfer routines.
2750
2751Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2752
2753 * gencode.c (process_instructions): Ensure FP ABS instruction
2754 recognised.
2755 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2756 system call support.
2757
2758Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2759
2760 * interp.c (sim_do_command): Complain if callback structure not
2761 initialised.
2762
2763Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2764
2765 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2766 support for Sun hosts.
2767 * Makefile.in (gencode): Ensure the host compiler and libraries
2768 used for cross-hosted build.
2769
2770Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2771
2772 * interp.c, gencode.c: Some more (TODO) tidying.
2773
2774Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2775
2776 * gencode.c, interp.c: Replaced explicit long long references with
2777 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2778 * support.h (SET64LO, SET64HI): Macros added.
2779
2780Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2781
2782 * configure: Regenerate with autoconf 2.7.
2783
2784Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2785
2786 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2787 * support.h: Remove superfluous "1" from #if.
2788 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2789
2790Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2791
2792 * interp.c (StoreFPR): Control UndefinedResult() call on
2793 WARN_RESULT manifest.
2794
2795Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2796
2797 * gencode.c: Tidied instruction decoding, and added FP instruction
2798 support.
2799
2800 * interp.c: Added dineroIII, and BSD profiling support. Also
2801 run-time FP handling.
2802
2803Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2804
2805 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2806 gencode.c, interp.c, support.h: created.
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