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sim: clean up redundant objects
[deliverable/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
6e4f085c
MF		 12015-11-14 Mike Frysinger <vapier@gentoo.org>
2
3 * interp.c (sim_close): Rename to ...
4 (mips_sim_close): ... this. Delete calls to sim_module_uninstall and
5 sim_io_shutdown.
6 * sim-main.h (mips_sim_close): Declare.
7 (SIM_CLOSE_HOOK): Define.
8
8e394ffc
AB		 92015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
10 Ali Lown <ali.lown@imgtec.com>
11
12 * Makefile.in (tmp-micromips): New rule.
13 (tmp-mach-multi): Add support for micromips.
14 * configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
15 that works for both mips64 and micromips64.
16 (mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
17 micromips32.
18 Add build support for micromips.
19 * dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
20 do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
21 do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
22 do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
23 do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
24 do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
25 do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
26 do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
27 Refactored instruction code to use these functions.
28 * dsp2.igen: Refactored instruction code to use the new functions.
29 * interp.c (decode_coproc): Refactored to work with any instruction
30 encoding.
31 (isa_mode): New variable
32 (RSVD_INSTRUCTION): Changed to 0x00000039.
33 * m16.igen (BREAK16): Refactored instruction to use do_break16.
34 (JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
35 * micromips.dc: New file.
36 * micromips.igen: New file.
37 * micromips16.dc: New file.
38 * micromipsdsp.igen: New file.
39 * micromipsrun.c: New file.
40 * mips.igen (do_swc1): Changed to work with any instruction encoding.
41 (do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
42 do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo,
43 do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu,
44 do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu,
45 do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub,
46 do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo,
47 do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc,
48 do_scd, do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu,
49 do_tgeu, do_tlt do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt,
50 do_add_fmt, do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1,
51 do_cvt_d_fmt, do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl,
52 do_cvt_s_pu, do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt,
53 do_luxc1_32, do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b,
54 do_mov_fmt, do_movtf, do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt,
55 do_mtc1b, do_mul_fmt, do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps,
56 do_plu_ps, do_pul_ps, do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt,
57 do_prefx, do_sdc1, do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt,
58 do_swc1, do_swxc1, do_trunc_fmt): New functions, refactored from existing
59 instructions.
60 Refactored instruction code to use these functions.
61 (RSVD): Changed to use new reserved instruction.
62 (loadstore_ea, not_word_value, unpredictable, check_mt_hilo,
63 check_mf_hilo, check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32,
64 do_sdc1, do_suxc1_32, check_fmt_p, check_fpu, do_load_double,
65 do_store_double): Added micromips32 and micromips64 models.
66 Added include for micromips.igen and micromipsdsp.igen
67 Add micromips32 and micromips64 models.
68 (DecodeCoproc): Updated to use new macro definition.
69 * mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
70 do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
71 do_seb, do_seh do_rdhwr, do_wsbh): New functions.
72 Refactored instruction code to use these functions.
73 * sim-main.h (CP0_operation): New enum.
74 (DecodeCoproc): Updated macro.
75 (IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
76 MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16,
77 MICROMIPS_DELAYSLOT_SIZE_32, ISA_MODE_MIPS32 and
78 ISA_MODE_MICROMIPS): New defines.
79 (sim_state): Add isa_mode field.
80
8d0978fb
MF		 812015-06-23 Mike Frysinger <vapier@gentoo.org>
82
83 * configure: Regenerate.
84
306f4178
MF		 852015-06-12 Mike Frysinger <vapier@gentoo.org>
86
87 * configure.ac: Change configure.in to configure.ac.
88 * configure: Regenerate.
89
a3487082
MF		 902015-06-12 Mike Frysinger <vapier@gentoo.org>
91
92 * configure: Regenerate.
93
29bc024d
MF		 942015-06-12 Mike Frysinger <vapier@gentoo.org>
95
96 * interp.c [TRACE]: Delete.
97 (TRACE): Change to WITH_TRACE_ANY_P.
98 [!WITH_TRACE_ANY_P] (open_trace): Define.
99 (mips_option_handler, open_trace, sim_close, dotrace):
100 Change defined(TRACE) to WITH_TRACE_ANY_P.
101 (sim_open): Delete TRACE ifdef check.
102 * sim-main.c (load_memory): Delete TRACE ifdef check.
103 (store_memory): Likewise.
104 * sim-main.h [WITH_TRACE_ANY_P] (dotrace, tracefh): Protect decls.
105 [!WITH_TRACE_ANY_P] (dotrace): Define.
106
3ebe2863
MF		 1072015-04-18 Mike Frysinger <vapier@gentoo.org>
108
109 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESTART_HOOK): Delete
110 comments.
111
20bca71d
MF		 1122015-04-18 Mike Frysinger <vapier@gentoo.org>
113
114 * sim-main.h (SIM_CPU): Delete.
115
7e83aa92
MF		 1162015-04-18 Mike Frysinger <vapier@gentoo.org>
117
118 * sim-main.h (sim_cia): Delete.
119
034685f9
MF		 1202015-04-17 Mike Frysinger <vapier@gentoo.org>
121
122 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Change CIA_GET to
123 PU_PC_GET.
124 * interp.c (interrupt_event): Change CIA_GET to CPU_PC_GET.
125 (sim_create_inferior): Change CIA_SET to CPU_PC_SET.
126 * m16run.c (sim_engine_run): Change CIA_GET to CPU_PC_GET and
127 CIA_SET to CPU_PC_SET.
128 * sim-main.h (CIA_GET, CIA_SET): Delete.
129
78e9aa70
MF		 1302015-04-15 Mike Frysinger <vapier@gentoo.org>
131
132 * Makefile.in (SIM_OBJS): Delete sim-cpu.o.
133 * sim-main.h (STATE_CPU): Delete.
134
bf12d44e
MF		 1352015-04-13 Mike Frysinger <vapier@gentoo.org>
136
137 * configure: Regenerate.
138
7bebb329
MF		 1392015-04-13 Mike Frysinger <vapier@gentoo.org>
140
141 * Makefile.in (SIM_OBJS): Add sim-cpu.o.
142 * interp.c (mips_pc_get, mips_pc_set): New functions.
143 (sim_open): Declare new local var i. Call sim_cpu_alloc_all.
144 Call CPU_PC_FETCH & CPU_PC_STORE for all cpus.
145 (sim_pc_get): Delete.
146 * sim-main.h (SIM_CPU): Define.
147 (struct sim_state): Change cpu to an array of pointers.
148 (STATE_CPU): Drop &.
149
8ac57fbd
MF		 1502015-04-13 Mike Frysinger <vapier@gentoo.org>
151
152 * interp.c (mips_option_handler, open_trace, sim_close,
153 sim_write, sim_read, sim_store_register, sim_fetch_register,
154 sim_create_inferior, pr_addr, pr_uword64): Convert old style
155 prototypes.
156 (sim_open): Convert old style prototype. Change casts with
157 sim_write to unsigned char *.
158 (fetch_str): Change null to unsigned char, and change cast to
159 unsigned char *.
160 (sim_monitor): Change c & ch to unsigned char. Change cast to
161 unsigned char *.
162
e787f858
MF		 1632015-04-12 Mike Frysinger <vapier@gentoo.org>
164
165 * Makefile.in (SIM_OBJS): Move interp.o to the start of the list.
166
122bbfb5
MF		 1672015-04-06 Mike Frysinger <vapier@gentoo.org>
168
169 * Makefile.in (SIM_OBJS): Delete sim-engine.o.
170
0fe84f3f
MF		 1712015-04-01 Mike Frysinger <vapier@gentoo.org>
172
173 * tconfig.h (SIM_HAVE_PROFILE): Delete.
174
aadc9410
MF		 1752015-03-31 Mike Frysinger <vapier@gentoo.org>
176
177 * config.in, configure: Regenerate.
178
05f53ed6
MF		 1792015-03-24 Mike Frysinger <vapier@gentoo.org>
180
181 * interp.c (sim_pc_get): New function.
182
c0931f26
MF		 1832015-03-24 Mike Frysinger <vapier@gentoo.org>
184
185 * sim-main.h (SIM_HAVE_BIENDIAN): Delete.
186 * tconfig.h (SIM_HAVE_BIENDIAN): Delete.
187
30452bbe
MF		 1882015-03-24 Mike Frysinger <vapier@gentoo.org>
189
190 * configure: Regenerate.
191
64dd13df
MF		 1922015-03-23 Mike Frysinger <vapier@gentoo.org>
193
194 * configure: Regenerate.
195
49cd1634
MF		 1962015-03-23 Mike Frysinger <vapier@gentoo.org>
197
198 * configure: Regenerate.
199 * configure.ac (mips_extra_objs): Delete.
200 * Makefile.in (MIPS_EXTRA_OBJS): Delete.
201 (SIM_OBJS): Delete MIPS_EXTRA_OBJS.
202
3649cb06
MF		 2032015-03-23 Mike Frysinger <vapier@gentoo.org>
204
205 * configure: Regenerate.
206 * configure.ac: Delete sim_hw checks for dv-sockser.
207
ae7d0cac
MF		 2082015-03-16 Mike Frysinger <vapier@gentoo.org>
209
210 * config.in, configure: Regenerate.
211 * tconfig.in: Rename file ...
212 * tconfig.h: ... here.
213
8406bb59
MF		 2142015-03-15 Mike Frysinger <vapier@gentoo.org>
215
216 * tconfig.in: Delete includes.
217 [HAVE_DV_SOCKSER]: Delete.
218
465fb143
MF		 2192015-03-14 Mike Frysinger <vapier@gentoo.org>
220
221 * Makefile.in (SIM_RUN_OBJS): Delete.
222
5cddc23a
MF		 2232015-03-14 Mike Frysinger <vapier@gentoo.org>
224
225 * configure.ac (AC_CHECK_HEADERS): Delete.
226 * aclocal.m4, configure: Regenerate.
227
2974be62
AM		 2282014-08-19 Alan Modra <amodra@gmail.com>
229
230 * configure: Regenerate.
231
faa743bb
RM		 2322014-08-15 Roland McGrath <mcgrathr@google.com>
233
234 * configure: Regenerate.
235 * config.in: Regenerate.
236
1a8a700e
MF		 2372014-03-04 Mike Frysinger <vapier@gentoo.org>
238
239 * configure: Regenerate.
240
bf3d9781
AM		 2412013-09-23 Alan Modra <amodra@gmail.com>
242
243 * configure: Regenerate.
244
31e6ad7d
MF		 2452013-06-03 Mike Frysinger <vapier@gentoo.org>
246
247 * aclocal.m4, configure: Regenerate.
248
d3685d60
TT		 2492013-05-10 Freddie Chopin <freddie_chopin@op.pl>
250
251 * configure: Rebuild.
252
1517bd27
MF		 2532013-03-26 Mike Frysinger <vapier@gentoo.org>
254
255 * configure: Regenerate.
256
3be31516
JS		 2572013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
258
259 * configure.ac: Address use of dv-sockser.o.
260 * tconfig.in: Conditionalize use of dv_sockser_install.
261 * configure: Regenerated.
262 * config.in: Regenerated.
263
37cb8f8e
SE		 2642012-10-04 Chao-ying Fu <fu@mips.com>
265 Steve Ellcey <sellcey@mips.com>
266
267 * mips/mips3264r2.igen (rdhwr): New.
268
87c8644f
JS		 2692012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
270
271 * configure.ac: Always link against dv-sockser.o.
272 * configure: Regenerate.
273
5f3ef9d0
JB		 2742012-06-15 Joel Brobecker <brobecker@adacore.com>
275
276 * config.in, configure: Regenerate.
277
a6ff997c
NC		 2782012-05-18 Nick Clifton <nickc@redhat.com>
279
280 PR 14072
281 * interp.c: Include config.h before system header files.
282
2232061b
MF		 2832012-03-24 Mike Frysinger <vapier@gentoo.org>
284
285 * aclocal.m4, config.in, configure: Regenerate.
286
db2e4d67
MF		 2872011-12-03 Mike Frysinger <vapier@gentoo.org>
288
289 * aclocal.m4: New file.
290 * configure: Regenerate.
291
4399a56b
MF		 2922011-10-19 Mike Frysinger <vapier@gentoo.org>
293
294 * configure: Regenerate after common/acinclude.m4 update.
295
9c082ca8
MF		 2962011-10-17 Mike Frysinger <vapier@gentoo.org>
297
298 * configure.ac: Change include to common/acinclude.m4.
299
6ffe910a
MF		 3002011-10-17 Mike Frysinger <vapier@gentoo.org>
301
302 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
303 call. Replace common.m4 include with SIM_AC_COMMON.
304 * configure: Regenerate.
305
31b28250
HPN		 3062011-07-08 Hans-Peter Nilsson <hp@axis.com>
307
3faa01e3
HPN		 308 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
309 $(SIM_EXTRA_DEPS).
310 (tmp-mach-multi): Exit early when igen fails.
31b28250 311
2419798b
MF		 3122011-07-05 Mike Frysinger <vapier@gentoo.org>
313
314 * interp.c (sim_do_command): Delete.
315
d79fe0d6
MF		 3162011-02-14 Mike Frysinger <vapier@gentoo.org>
317
318 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
319 (tx3904sio_fifo_reset): Likewise.
320 * interp.c (sim_monitor): Likewise.
321
5558e7e6
MF		 3222010-04-14 Mike Frysinger <vapier@gentoo.org>
323
324 * interp.c (sim_write): Add const to buffer arg.
325
35aafff4
JB		 3262010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
327
328 * interp.c: Don't include sysdep.h
329
3725885a
RW		 3302010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
331
332 * configure: Regenerate.
333
d6416cdc
RW		 3342009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
335
81ecdfbb
RW		 336 * config.in: Regenerate.
337 * configure: Likewise.
338
d6416cdc
RW		 339 * configure: Regenerate.
340
b5bd9624
HPN		 3412008-07-11 Hans-Peter Nilsson <hp@axis.com>
342
343 * configure: Regenerate to track ../common/common.m4 changes.
344 * config.in: Ditto.
345
6efef468 3462008-06-06 Vladimir Prus <vladimir@codesourcery.com>
72f4393d
L		 347 Daniel Jacobowitz <dan@codesourcery.com>
348 Joseph Myers <joseph@codesourcery.com>
6efef468
JM		 349
350 * configure: Regenerate.
351
60dc88db
RS		 3522007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
353
354 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
355 that unconditionally allows fmt_ps.
356 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
357 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
358 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
359 filter from 64,f to 32,f.
360 (PREFX): Change filter from 64 to 32.
361 (LDXC1, LUXC1): Provide separate mips32r2 implementations
362 that use do_load_double instead of do_load. Make both LUXC1
363 versions unpredictable if SizeFGR () != 64.
364 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
365 instead of do_store. Remove unused variable. Make both SUXC1
366 versions unpredictable if SizeFGR () != 64.
367
599ca73e
RS		 3682007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
369
370 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
371 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
372 shifts for that case.
373
2525df03
NC		 3742007-09-04 Nick Clifton <nickc@redhat.com>
375
376 * interp.c (options enum): Add OPTION_INFO_MEMORY.
377 (display_mem_info): New static variable.
378 (mips_option_handler): Handle OPTION_INFO_MEMORY.
379 (mips_options): Add info-memory and memory-info.
380 (sim_open): After processing the command line and board
381 specification, check display_mem_info. If it is set then
382 call the real handler for the --memory-info command line
383 switch.
384
35ee6e1e
JB		 3852007-08-24 Joel Brobecker <brobecker@adacore.com>
386
387 * configure.ac: Change license of multi-run.c to GPL version 3.
388 * configure: Regenerate.
389
d5fb0879
RS		 3902007-06-28 Richard Sandiford <richard@codesourcery.com>
391
392 * configure.ac, configure: Revert last patch.
393
2a2ce21b
RS		 3942007-06-26 Richard Sandiford <richard@codesourcery.com>
395
396 * configure.ac (sim_mipsisa3264_configs): New variable.
397 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
398 every configuration support all four targets, using the triplet to
399 determine the default.
400 * configure: Regenerate.
401
efdcccc9
RS		 4022007-06-25 Richard Sandiford <richard@codesourcery.com>
403
0a7692b2 404 * Makefile.in (m16run.o): New rule.
efdcccc9 405
f532a356
TS		 4062007-05-15 Thiemo Seufer <ths@mips.com>
407
408 * mips3264r2.igen (DSHD): Fix compile warning.
409
bfe9c90b
TS		 4102007-05-14 Thiemo Seufer <ths@mips.com>
411
412 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
413 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
414 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
415 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
416 for mips32r2.
417
53f4826b
TS		 4182007-03-01 Thiemo Seufer <ths@mips.com>
419
420 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
421 and mips64.
422
8bf3ddc8
TS		 4232007-02-20 Thiemo Seufer <ths@mips.com>
424
425 * dsp.igen: Update copyright notice.
426 * dsp2.igen: Fix copyright notice.
427
8b082fb1 4282007-02-20 Thiemo Seufer <ths@mips.com>
72f4393d 429 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 430
431 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
432 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
433 Add dsp2 to sim_igen_machine.
434 * configure: Regenerate.
435 * dsp.igen (do_ph_op): Add MUL support when op = 2.
436 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
437 (mulq_rs.ph): Use do_ph_mulq.
438 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
439 * mips.igen: Add dsp2 model and include dsp2.igen.
440 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
441 for *mips32r2, *mips64r2, *dsp.
442 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
443 for *mips32r2, *mips64r2, *dsp2.
444 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
445
b1004875 4462007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 447 Nigel Stephens <nigel@mips.com>
b1004875
TS		 448
449 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
450 jumps with hazard barrier.
451
f8df4c77 4522007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 453 Nigel Stephens <nigel@mips.com>
f8df4c77
TS		 454
455 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
456 after each call to sim_io_write.
457
b1004875 4582007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 459 Nigel Stephens <nigel@mips.com>
b1004875
TS		 460
461 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
462 supported by this simulator.
07802d98
TS		 463 (decode_coproc): Recognise additional CP0 Config registers
464 correctly.
465
14fb6c5a 4662007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d
L		 467 Nigel Stephens <nigel@mips.com>
468 David Ung <davidu@mips.com>
14fb6c5a
TS		 469
470 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
471 uninterpreted formats. If fmt is one of the uninterpreted types
472 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
473 fmt_word, and fmt_uninterpreted_64 like fmt_long.
474 (store_fpr): When writing an invalid odd register, set the
475 matching even register to fmt_unknown, not the following register.
476 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
477 the the memory window at offset 0 set by --memory-size command
478 line option.
479 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
480 point register.
481 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
482 register.
483 (sim_monitor): When returning the memory size to the MIPS
484 application, use the value in STATE_MEM_SIZE, not an arbitrary
485 hardcoded value.
486 (cop_lw): Don' mess around with FPR_STATE, just pass
487 fmt_uninterpreted_32 to StoreFPR.
488 (cop_sw): Similarly.
489 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
490 (cop_sd): Similarly.
491 * mips.igen (not_word_value): Single version for mips32, mips64
492 and mips16.
493
c8847145 4942007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 495 Nigel Stephens <nigel@mips.com>
c8847145
TS		 496
497 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
498 MBytes.
499
4b5d35ee
TS		 5002007-02-17 Thiemo Seufer <ths@mips.com>
501
502 * configure.ac (mips*-sde-elf*): Move in front of generic machine
503 configuration.
504 * configure: Regenerate.
505
3669427c
TS		 5062007-02-17 Thiemo Seufer <ths@mips.com>
507
508 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
509 Add mdmx to sim_igen_machine.
510 (mipsisa64*-*-*): Likewise. Remove dsp.
511 (mipsisa32*-*-*): Remove dsp.
512 * configure: Regenerate.
513
109ad085
TS		 5142007-02-13 Thiemo Seufer <ths@mips.com>
515
516 * configure.ac: Add mips*-sde-elf* target.
517 * configure: Regenerate.
518
921d7ad3
HPN		 5192006-12-21 Hans-Peter Nilsson <hp@axis.com>
520
521 * acconfig.h: Remove.
522 * config.in, configure: Regenerate.
523
02f97da7
TS		 5242006-11-07 Thiemo Seufer <ths@mips.com>
525
526 * dsp.igen (do_w_op): Fix compiler warning.
527
2d2733fc 5282006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 529 David Ung <davidu@mips.com>
2d2733fc
TS		 530
531 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
532 sim_igen_machine.
533 * configure: Regenerate.
534 * mips.igen (model): Add smartmips.
535 (MADDU): Increment ACX if carry.
536 (do_mult): Clear ACX.
537 (ROR,RORV): Add smartmips.
72f4393d 538 (include): Include smartmips.igen.
2d2733fc
TS		 539 * sim-main.h (ACX): Set to REGISTERS[89].
540 * smartmips.igen: New file.
541
d85c3a10 5422006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 543 David Ung <davidu@mips.com>
d85c3a10
TS		 544
545 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
546 mips3264r2.igen. Add missing dependency rules.
547 * m16e.igen: Support for mips16e save/restore instructions.
548
e85e3205
RE		 5492006-06-13 Richard Earnshaw <rearnsha@arm.com>
550
551 * configure: Regenerated.
552
2f0122dc
DJ		 5532006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
554
555 * configure: Regenerated.
556
20e95c23
DJ		 5572006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
558
559 * configure: Regenerated.
560
69088b17
CF		 5612006-05-15 Chao-ying Fu <fu@mips.com>
562
563 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
564
0275de4e
NC		 5652006-04-18 Nick Clifton <nickc@redhat.com>
566
567 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
568 statement.
569
b3a3ffef
HPN		 5702006-03-29 Hans-Peter Nilsson <hp@axis.com>
571
572 * configure: Regenerate.
573
40a5538e
CF		 5742005-12-14 Chao-ying Fu <fu@mips.com>
575
576 * Makefile.in (SIM_OBJS): Add dsp.o.
577 (dsp.o): New dependency.
578 (IGEN_INCLUDE): Add dsp.igen.
579 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
580 mipsisa64*-*-*): Add dsp to sim_igen_machine.
581 * configure: Regenerate.
582 * mips.igen: Add dsp model and include dsp.igen.
583 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
584 because these instructions are extended in DSP ASE.
585 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
586 adding 6 DSP accumulator registers and 1 DSP control register.
587 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
588 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
589 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
590 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
591 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
592 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
593 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
594 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
595 DSPCR_CCOND_SMASK): New define.
596 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
597 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
598
21d14896
ILT		 5992005-07-08 Ian Lance Taylor <ian@airs.com>
600
601 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
602
b16d63da 6032005-06-16 David Ung <davidu@mips.com>
72f4393d
L		 604 Nigel Stephens <nigel@mips.com>
605
606 * mips.igen: New mips16e model and include m16e.igen.
607 (check_u64): Add mips16e tag.
608 * m16e.igen: New file for MIPS16e instructions.
609 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
610 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
611 models.
612 * configure: Regenerate.
b16d63da 613
e70cb6cd 6142005-05-26 David Ung <davidu@mips.com>
72f4393d 615
e70cb6cd
CD		 616 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
617 tags to all instructions which are applicable to the new ISAs.
618 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
619 vr.igen.
620 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
72f4393d 621 instructions.
e70cb6cd
CD		 622 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
623 to mips.igen.
624 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
625 * configure: Regenerate.
72f4393d 626
2b193c4a
MK		 6272005-03-23 Mark Kettenis <kettenis@gnu.org>
628
629 * configure: Regenerate.
630
35695fd6
AC		 6312005-01-14 Andrew Cagney <cagney@gnu.org>
632
633 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
634 explicit call to AC_CONFIG_HEADER.
635 * configure: Regenerate.
636
f0569246
AC		 6372005-01-12 Andrew Cagney <cagney@gnu.org>
638
639 * configure.ac: Update to use ../common/common.m4.
640 * configure: Re-generate.
641
38f48d72
AC		 6422005-01-11 Andrew Cagney <cagney@localhost.localdomain>
643
644 * configure: Regenerated to track ../common/aclocal.m4 changes.
645
b7026657
AC		 6462005-01-07 Andrew Cagney <cagney@gnu.org>
647
648 * configure.ac: Rename configure.in, require autoconf 2.59.
649 * configure: Re-generate.
650
379832de
HPN		 6512004-12-08 Hans-Peter Nilsson <hp@axis.com>
652
653 * configure: Regenerate for ../common/aclocal.m4 update.
654
cd62154c 6552004-09-24 Monika Chaddha <monika@acmet.com>
72f4393d 656
cd62154c
AC		 657 Committed by Andrew Cagney.
658 * m16.igen (CMP, CMPI): Fix assembler.
659
e5da76ec
CD		 6602004-08-18 Chris Demetriou <cgd@broadcom.com>
661
662 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
663 * configure: Regenerate.
664
139181c8
CD		 6652004-06-25 Chris Demetriou <cgd@broadcom.com>
666
667 * configure.in (sim_m16_machine): Include mipsIII.
668 * configure: Regenerate.
669
1a27f959
CD		 6702004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
671
72f4393d 672 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
1a27f959
CD		 673 from COP0_BADVADDR.
674 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
675
5dbb7b5a
CD		 6762004-04-10 Chris Demetriou <cgd@broadcom.com>
677
678 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
679
14234056
CD		 6802004-04-09 Chris Demetriou <cgd@broadcom.com>
681
682 * mips.igen (check_fmt): Remove.
683 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
684 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
685 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
686 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
687 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
688 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
689 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
690 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
691 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
692 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
693
c6f9085c
CD		 6942004-04-09 Chris Demetriou <cgd@broadcom.com>
695
696 * sb1.igen (check_sbx): New function.
697 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
698
11d66e66 6992004-03-29 Chris Demetriou <cgd@broadcom.com>
0e1b7197
RS		 700 Richard Sandiford <rsandifo@redhat.com>
701
702 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
703 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
704 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
705 separate implementations for mipsIV and mipsV. Use new macros to
706 determine whether the restrictions apply.
707
b3208fb8
CD		 7082004-01-19 Chris Demetriou <cgd@broadcom.com>
709
710 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
711 (check_mult_hilo): Improve comments.
712 (check_div_hilo): Likewise. Also, fork off a new version
713 to handle mips32/mips64 (since there are no hazards to check
714 in MIPS32/MIPS64).
715
9a1d84fb
CD		 7162003-06-17 Richard Sandiford <rsandifo@redhat.com>
717
718 * mips.igen (do_dmultx): Fix check for negative operands.
719
ae451ac6
ILT		 7202003-05-16 Ian Lance Taylor <ian@airs.com>
721
722 * Makefile.in (SHELL): Make sure this is defined.
723 (various): Use $(SHELL) whenever we invoke move-if-change.
724
dd69d292
CD		 7252003-05-03 Chris Demetriou <cgd@broadcom.com>
726
727 * cp1.c: Tweak attribution slightly.
728 * cp1.h: Likewise.
729 * mdmx.c: Likewise.
730 * mdmx.igen: Likewise.
731 * mips3d.igen: Likewise.
732 * sb1.igen: Likewise.
733
bcd0068e
CD		 7342003-04-15 Richard Sandiford <rsandifo@redhat.com>
735
736 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
737 unsigned operands.
738
6b4a8935
AC		 7392003-02-27 Andrew Cagney <cagney@redhat.com>
740
601da316
AC		 741 * interp.c (sim_open): Rename _bfd to bfd.
742 (sim_create_inferior): Ditto.
6b4a8935 743
d29e330f
CD		 7442003-01-14 Chris Demetriou <cgd@broadcom.com>
745
746 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
747
a2353a08
CD		 7482003-01-14 Chris Demetriou <cgd@broadcom.com>
749
750 * mips.igen (EI, DI): Remove.
751
80551777
CD		 7522003-01-05 Richard Sandiford <rsandifo@redhat.com>
753
754 * Makefile.in (tmp-run-multi): Fix mips16 filter.
755
4c54fc26
CD		 7562003-01-04 Richard Sandiford <rsandifo@redhat.com>
757 Andrew Cagney <ac131313@redhat.com>
758 Gavin Romig-Koch <gavin@redhat.com>
759 Graydon Hoare <graydon@redhat.com>
760 Aldy Hernandez <aldyh@redhat.com>
761 Dave Brolley <brolley@redhat.com>
762 Chris Demetriou <cgd@broadcom.com>
763
764 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
765 (sim_mach_default): New variable.
766 (mips64vr-*-*, mips64vrel-*-*): New configurations.
767 Add a new simulator generator, MULTI.
768 * configure: Regenerate.
769 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
770 (multi-run.o): New dependency.
771 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
772 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
773 (tmp-multi): Combine them.
774 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
775 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
776 (distclean-extra): New rule.
777 * sim-main.h: Include bfd.h.
778 (MIPS_MACH): New macro.
779 * mips.igen (vr4120, vr5400, vr5500): New models.
780 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
781 * vr.igen: Replace with new version.
782
e6c674b8
CD		 7832003-01-04 Chris Demetriou <cgd@broadcom.com>
784
785 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
786 * configure: Regenerate.
787
28f50ac8
CD		 7882002-12-31 Chris Demetriou <cgd@broadcom.com>
789
790 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
791 * mips.igen: Remove all invocations of check_branch_bug and
792 mark_branch_bug.
793
5071ffe6
CD		 7942002-12-16 Chris Demetriou <cgd@broadcom.com>
795
72f4393d 796 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
5071ffe6 797
06e7837e
CD		 7982002-07-30 Chris Demetriou <cgd@broadcom.com>
799
800 * mips.igen (do_load_double, do_store_double): New functions.
801 (LDC1, SDC1): Rename to...
802 (LDC1b, SDC1b): respectively.
803 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
804
2265c243
MS		 8052002-07-29 Michael Snyder <msnyder@redhat.com>
806
807 * cp1.c (fp_recip2): Modify initialization expression so that
808 GCC will recognize it as constant.
809
a2f8b4f3
CD		 8102002-06-18 Chris Demetriou <cgd@broadcom.com>
811
812 * mdmx.c (SD_): Delete.
813 (Unpredictable): Re-define, for now, to directly invoke
814 unpredictable_action().
815 (mdmx_acc_op): Fix error in .ob immediate handling.
816
b4b6c939
AC		 8172002-06-18 Andrew Cagney <cagney@redhat.com>
818
819 * interp.c (sim_firmware_command): Initialize `address'.
820
c8cca39f
AC		 8212002-06-16 Andrew Cagney <ac131313@redhat.com>
822
823 * configure: Regenerated to track ../common/aclocal.m4 changes.
824
e7e81181 8252002-06-14 Chris Demetriou <cgd@broadcom.com>
72f4393d 826 Ed Satterthwaite <ehs@broadcom.com>
e7e81181
CD		 827
828 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
829 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
830 * mips.igen: Include mips3d.igen.
831 (mips3d): New model name for MIPS-3D ASE instructions.
832 (CVT.W.fmt): Don't use this instruction for word (source) format
72f4393d 833 instructions.
e7e81181
CD		 834 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
835 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
836 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
837 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
838 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
839 (RSquareRoot1, RSquareRoot2): New macros.
840 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
841 (fp_rsqrt2): New functions.
842 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
843 * configure: Regenerate.
844
3a2b820e 8452002-06-13 Chris Demetriou <cgd@broadcom.com>
72f4393d 846 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 847
848 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
849 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
850 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
851 (convert): Note that this function is not used for paired-single
852 format conversions.
853 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
854 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
855 (check_fmt_p): Enable paired-single support.
856 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
857 (PUU.PS): New instructions.
858 (CVT.S.fmt): Don't use this instruction for paired-single format
859 destinations.
860 * sim-main.h (FP_formats): New value 'fmt_ps.'
861 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
862 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
863
d18ea9c2
CD		 8642002-06-12 Chris Demetriou <cgd@broadcom.com>
865
866 * mips.igen: Fix formatting of function calls in
867 many FP operations.
868
95fd5cee
CD		 8692002-06-12 Chris Demetriou <cgd@broadcom.com>
870
871 * mips.igen (MOVN, MOVZ): Trace result.
872 (TNEI): Print "tnei" as the opcode name in traces.
873 (CEIL.W): Add disassembly string for traces.
874 (RSQRT.fmt): Make location of disassembly string consistent
875 with other instructions.
876
4f0d55ae
CD		 8772002-06-12 Chris Demetriou <cgd@broadcom.com>
878
879 * mips.igen (X): Delete unused function.
880
3c25f8c7
AC		 8812002-06-08 Andrew Cagney <cagney@redhat.com>
882
883 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
884
f3c08b7e 8852002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 886 Ed Satterthwaite <ehs@broadcom.com>
f3c08b7e
CD		 887
888 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
889 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
890 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
891 (fp_nmsub): New prototypes.
892 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
893 (NegMultiplySub): New defines.
894 * mips.igen (RSQRT.fmt): Use RSquareRoot().
895 (MADD.D, MADD.S): Replace with...
896 (MADD.fmt): New instruction.
897 (MSUB.D, MSUB.S): Replace with...
898 (MSUB.fmt): New instruction.
899 (NMADD.D, NMADD.S): Replace with...
900 (NMADD.fmt): New instruction.
901 (NMSUB.D, MSUB.S): Replace with...
902 (NMSUB.fmt): New instruction.
903
52714ff9 9042002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 905 Ed Satterthwaite <ehs@broadcom.com>
52714ff9
CD		 906
907 * cp1.c: Fix more comment spelling and formatting.
908 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
909 (denorm_mode): New function.
910 (fpu_unary, fpu_binary): Round results after operation, collect
911 status from rounding operations, and update the FCSR.
912 (convert): Collect status from integer conversions and rounding
913 operations, and update the FCSR. Adjust NaN values that result
914 from conversions. Convert to use sim_io_eprintf rather than
915 fprintf, and remove some debugging code.
916 * cp1.h (fenr_FS): New define.
917
577d8c4b
CD		 9182002-06-07 Chris Demetriou <cgd@broadcom.com>
919
920 * cp1.c (convert): Remove unusable debugging code, and move MIPS
921 rounding mode to sim FP rounding mode flag conversion code into...
922 (rounding_mode): New function.
923
196496ed
CD		 9242002-06-07 Chris Demetriou <cgd@broadcom.com>
925
926 * cp1.c: Clean up formatting of a few comments.
927 (value_fpr): Reformat switch statement.
928
cfe9ea23 9292002-06-06 Chris Demetriou <cgd@broadcom.com>
72f4393d 930 Ed Satterthwaite <ehs@broadcom.com>
cfe9ea23
CD		 931
932 * cp1.h: New file.
933 * sim-main.h: Include cp1.h.
934 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
935 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
936 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
937 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
938 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
939 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
940 * cp1.c: Don't include sim-fpu.h; already included by
941 sim-main.h. Clean up formatting of some comments.
942 (NaN, Equal, Less): Remove.
943 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
944 (fp_cmp): New functions.
945 * mips.igen (do_c_cond_fmt): Remove.
946 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
947 Compare. Add result tracing.
948 (CxC1): Remove, replace with...
949 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
950 (DMxC1): Remove, replace with...
951 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
72f4393d
L		 952 (MxC1): Remove, replace with...
953 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
cfe9ea23 954
ee7254b0
CD		 9552002-06-04 Chris Demetriou <cgd@broadcom.com>
956
957 * sim-main.h (FGRIDX): Remove, replace all uses with...
958 (FGR_BASE): New macro.
959 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
960 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
961 (NR_FGR, FGR): Likewise.
962 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
963 * mips.igen: Likewise.
964
d3eb724f
CD		 9652002-06-04 Chris Demetriou <cgd@broadcom.com>
966
967 * cp1.c: Add an FSF Copyright notice to this file.
968
ba46ddd0 9692002-06-04 Chris Demetriou <cgd@broadcom.com>
72f4393d 970 Ed Satterthwaite <ehs@broadcom.com>
ba46ddd0
CD		 971
972 * cp1.c (Infinity): Remove.
973 * sim-main.h (Infinity): Likewise.
974
975 * cp1.c (fp_unary, fp_binary): New functions.
976 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
977 (fp_sqrt): New functions, implemented in terms of the above.
978 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
979 (Recip, SquareRoot): Remove (replaced by functions above).
980 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
981 (fp_recip, fp_sqrt): New prototypes.
982 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
983 (Recip, SquareRoot): Replace prototypes with #defines which
984 invoke the functions above.
72f4393d 985
18d8a52d
CD		 9862002-06-03 Chris Demetriou <cgd@broadcom.com>
987
988 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
989 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
990 file, remove PARAMS from prototypes.
991 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
992 simulator state arguments.
993 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
994 pass simulator state arguments.
995 * cp1.c (SD): Redefine as CPU_STATE(cpu).
996 (store_fpr, convert): Remove 'sd' argument.
997 (value_fpr): Likewise. Convert to use 'SD' instead.
998
0f154cbd
CD		 9992002-06-03 Chris Demetriou <cgd@broadcom.com>
1000
1001 * cp1.c (Min, Max): Remove #if 0'd functions.
1002 * sim-main.h (Min, Max): Remove.
1003
e80fc152
CD		 10042002-06-03 Chris Demetriou <cgd@broadcom.com>
1005
1006 * cp1.c: fix formatting of switch case and default labels.
1007 * interp.c: Likewise.
1008 * sim-main.c: Likewise.
1009
bad673a9
CD		 10102002-06-03 Chris Demetriou <cgd@broadcom.com>
1011
1012 * cp1.c: Clean up comments which describe FP formats.
1013 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
1014
7cbea089 10152002-06-03 Chris Demetriou <cgd@broadcom.com>
72f4393d 1016 Ed Satterthwaite <ehs@broadcom.com>
7cbea089
CD		 1017
1018 * configure.in (mipsisa64sb1*-*-*): New target for supporting
1019 Broadcom SiByte SB-1 processor configurations.
1020 * configure: Regenerate.
1021 * sb1.igen: New file.
1022 * mips.igen: Include sb1.igen.
1023 (sb1): New model.
1024 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
1025 * mdmx.igen: Add "sb1" model to all appropriate functions and
1026 instructions.
1027 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
1028 (ob_func, ob_acc): Reference the above.
1029 (qh_acc): Adjust to keep the same size as ob_acc.
1030 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
1031 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
1032
909daa82
CD		 10332002-06-03 Chris Demetriou <cgd@broadcom.com>
1034
1035 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
1036
f4f1b9f1 10372002-06-02 Chris Demetriou <cgd@broadcom.com>
72f4393d 1038 Ed Satterthwaite <ehs@broadcom.com>
f4f1b9f1
CD		 1039
1040 * mips.igen (mdmx): New (pseudo-)model.
1041 * mdmx.c, mdmx.igen: New files.
1042 * Makefile.in (SIM_OBJS): Add mdmx.o.
1043 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
1044 New typedefs.
1045 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
1046 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
1047 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
1048 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
1049 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
1050 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
1051 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
1052 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
1053 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
1054 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
1055 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
1056 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
1057 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
1058 (qh_fmtsel): New macros.
1059 (_sim_cpu): New member "acc".
1060 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
1061 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
1062
5accf1ff
CD		 10632002-05-01 Chris Demetriou <cgd@broadcom.com>
1064
1065 * interp.c: Use 'deprecated' rather than 'depreciated.'
1066 * sim-main.h: Likewise.
1067
402586aa
CD		 10682002-05-01 Chris Demetriou <cgd@broadcom.com>
1069
1070 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
1071 which wouldn't compile anyway.
1072 * sim-main.h (unpredictable_action): New function prototype.
1073 (Unpredictable): Define to call igen function unpredictable().
1074 (NotWordValue): New macro to call igen function not_word_value().
1075 (UndefinedResult): Remove.
1076 * interp.c (undefined_result): Remove.
1077 (unpredictable_action): New function.
1078 * mips.igen (not_word_value, unpredictable): New functions.
1079 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
1080 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
1081 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
1082 NotWordValue() to check for unpredictable inputs, then
1083 Unpredictable() to handle them.
1084
c9b9995a
CD		 10852002-02-24 Chris Demetriou <cgd@broadcom.com>
1086
1087 * mips.igen: Fix formatting of calls to Unpredictable().
1088
e1015982
AC		 10892002-04-20 Andrew Cagney <ac131313@redhat.com>
1090
1091 * interp.c (sim_open): Revert previous change.
1092
b882a66b
AO		 10932002-04-18 Alexandre Oliva <aoliva@redhat.com>
1094
1095 * interp.c (sim_open): Disable chunk of code that wrote code in
1096 vector table entries.
1097
c429b7dd
CD		 10982002-03-19 Chris Demetriou <cgd@broadcom.com>
1099
1100 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
1101 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
1102 unused definitions.
1103
37d146fa
CD		 11042002-03-19 Chris Demetriou <cgd@broadcom.com>
1105
1106 * cp1.c: Fix many formatting issues.
1107
07892c0b
CD		 11082002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1109
1110 * cp1.c (fpu_format_name): New function to replace...
1111 (DOFMT): This. Delete, and update all callers.
1112 (fpu_rounding_mode_name): New function to replace...
1113 (RMMODE): This. Delete, and update all callers.
1114
487f79b7
CD		 11152002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1116
1117 * interp.c: Move FPU support routines from here to...
1118 * cp1.c: Here. New file.
1119 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
1120 (cp1.o): New target.
1121
1e799e28
CD		 11222002-03-12 Chris Demetriou <cgd@broadcom.com>
1123
1124 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
1125 * mips.igen (mips32, mips64): New models, add to all instructions
1126 and functions as appropriate.
1127 (loadstore_ea, check_u64): New variant for model mips64.
1128 (check_fmt_p): New variant for models mipsV and mips64, remove
1129 mipsV model marking fro other variant.
1130 (SLL) Rename to...
1131 (SLLa) this.
1132 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
1133 for mips32 and mips64.
1134 (DCLO, DCLZ): New instructions for mips64.
1135
82f728db
CD		 11362002-03-07 Chris Demetriou <cgd@broadcom.com>
1137
1138 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
1139 immediate or code as a hex value with the "%#lx" format.
1140 (ANDI): Likewise, and fix printed instruction name.
1141
b96e7ef1
CD		 11422002-03-05 Chris Demetriou <cgd@broadcom.com>
1143
1144 * sim-main.h (UndefinedResult, Unpredictable): New macros
1145 which currently do nothing.
1146
d35d4f70
CD		 11472002-03-05 Chris Demetriou <cgd@broadcom.com>
1148
1149 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
1150 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
1151 (status_CU3): New definitions.
1152
1153 * sim-main.h (ExceptionCause): Add new values for MIPS32
1154 and MIPS64: MDMX, MCheck, CacheErr. Update comments
1155 for DebugBreakPoint and NMIReset to note their status in
1156 MIPS32 and MIPS64.
1157 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
1158 (SignalExceptionCacheErr): New exception macros.
1159
3ad6f714
CD		 11602002-03-05 Chris Demetriou <cgd@broadcom.com>
1161
1162 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
1163 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
1164 is always enabled.
1165 (SignalExceptionCoProcessorUnusable): Take as argument the
1166 unusable coprocessor number.
1167
86b77b47
CD		 11682002-03-05 Chris Demetriou <cgd@broadcom.com>
1169
1170 * mips.igen: Fix formatting of all SignalException calls.
1171
97a88e93 11722002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 1173
1174 * sim-main.h (SIGNEXTEND): Remove.
1175
97a88e93 11762002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 1177
1178 * mips.igen: Remove gencode comment from top of file, fix
1179 spelling in another comment.
1180
97a88e93 11812002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 1182
1183 * mips.igen (check_fmt, check_fmt_p): New functions to check
1184 whether specific floating point formats are usable.
1185 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1186 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
1187 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
1188 Use the new functions.
1189 (do_c_cond_fmt): Remove format checks...
1190 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
1191
97a88e93 11922002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 1193
1194 * mips.igen: Fix formatting of check_fpu calls.
1195
41774c9d
CD		 11962002-03-03 Chris Demetriou <cgd@broadcom.com>
1197
1198 * mips.igen (FLOOR.L.fmt): Store correct destination register.
1199
4a0bd876
CD		 12002002-03-03 Chris Demetriou <cgd@broadcom.com>
1201
1202 * mips.igen: Remove whitespace at end of lines.
1203
09297648
CD		 12042002-03-02 Chris Demetriou <cgd@broadcom.com>
1205
1206 * mips.igen (loadstore_ea): New function to do effective
1207 address calculations.
1208 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
1209 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
1210 CACHE): Use loadstore_ea to do effective address computations.
1211
043b7057
CD		 12122002-03-02 Chris Demetriou <cgd@broadcom.com>
1213
1214 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
1215 * mips.igen (LL, CxC1, MxC1): Likewise.
1216
c1e8ada4
CD		 12172002-03-02 Chris Demetriou <cgd@broadcom.com>
1218
1219 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
1220 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
1221 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
1222 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
1223 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
1224 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
1225 Don't split opcode fields by hand, use the opcode field values
1226 provided by igen.
1227
3e1dca16
CD		 12282002-03-01 Chris Demetriou <cgd@broadcom.com>
1229
1230 * mips.igen (do_divu): Fix spacing.
1231
1232 * mips.igen (do_dsllv): Move to be right before DSLLV,
1233 to match the rest of the do_<shift> functions.
1234
fff8d27d
CD		 12352002-03-01 Chris Demetriou <cgd@broadcom.com>
1236
1237 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
1238 DSRL32, do_dsrlv): Trace inputs and results.
1239
0d3e762b
CD		 12402002-03-01 Chris Demetriou <cgd@broadcom.com>
1241
1242 * mips.igen (CACHE): Provide instruction-printing string.
1243
1244 * interp.c (signal_exception): Comment tokens after #endif.
1245
eb5fcf93
CD		 12462002-02-28 Chris Demetriou <cgd@broadcom.com>
1247
1248 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
72f4393d
L		 1249 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
1250 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
1251 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
1252 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
1253 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
1254 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
eb5fcf93
CD		 1255 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
1256
bb22bd7d
CD		 12572002-02-28 Chris Demetriou <cgd@broadcom.com>
1258
1259 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
1260 instruction-printing string.
1261 (LWU): Use '64' as the filter flag.
1262
91a177cf
CD		 12632002-02-28 Chris Demetriou <cgd@broadcom.com>
1264
1265 * mips.igen (SDXC1): Fix instruction-printing string.
1266
387f484a
CD		 12672002-02-28 Chris Demetriou <cgd@broadcom.com>
1268
1269 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
1270 filter flags "32,f".
1271
3d81f391
CD		 12722002-02-27 Chris Demetriou <cgd@broadcom.com>
1273
1274 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1275 as the filter flag.
1276
af5107af
CD		 12772002-02-27 Chris Demetriou <cgd@broadcom.com>
1278
1279 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1280 add a comma) so that it more closely match the MIPS ISA
1281 documentation opcode partitioning.
1282 (PREF): Put useful names on opcode fields, and include
1283 instruction-printing string.
1284
ca971540
CD		 12852002-02-27 Chris Demetriou <cgd@broadcom.com>
1286
1287 * mips.igen (check_u64): New function which in the future will
1288 check whether 64-bit instructions are usable and signal an
1289 exception if not. Currently a no-op.
1290 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1291 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1292 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1293 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1294
1295 * mips.igen (check_fpu): New function which in the future will
1296 check whether FPU instructions are usable and signal an exception
1297 if not. Currently a no-op.
1298 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1299 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1300 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1301 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1302 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1303 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1304 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1305 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1306
1c47a468
CD		 13072002-02-27 Chris Demetriou <cgd@broadcom.com>
1308
1309 * mips.igen (do_load_left, do_load_right): Move to be immediately
1310 following do_load.
1311 (do_store_left, do_store_right): Move to be immediately following
1312 do_store.
1313
603a98e7
CD		 13142002-02-27 Chris Demetriou <cgd@broadcom.com>
1315
1316 * mips.igen (mipsV): New model name. Also, add it to
1317 all instructions and functions where it is appropriate.
1318
c5d00cc7
CD		 13192002-02-18 Chris Demetriou <cgd@broadcom.com>
1320
1321 * mips.igen: For all functions and instructions, list model
1322 names that support that instruction one per line.
1323
074e9cb8
CD		 13242002-02-11 Chris Demetriou <cgd@broadcom.com>
1325
1326 * mips.igen: Add some additional comments about supported
1327 models, and about which instructions go where.
1328 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1329 order as is used in the rest of the file.
1330
9805e229
CD		 13312002-02-11 Chris Demetriou <cgd@broadcom.com>
1332
1333 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1334 indicating that ALU32_END or ALU64_END are there to check
1335 for overflow.
1336 (DADD): Likewise, but also remove previous comment about
1337 overflow checking.
1338
f701dad2
CD		 13392002-02-10 Chris Demetriou <cgd@broadcom.com>
1340
1341 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1342 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1343 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1344 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1345 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1346 fields (i.e., add and move commas) so that they more closely
1347 match the MIPS ISA documentation opcode partitioning.
1348
13492002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098 1350
72f4393d
L		 1351 * mips.igen (ADDI): Print immediate value.
1352 (BREAK): Print code.
1353 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1354 (SLL): Print "nop" specially, and don't run the code
1355 that does the shift for the "nop" case.
20ae0098 1356
9e52972e
FF		 13572001-11-17 Fred Fish <fnf@redhat.com>
1358
1359 * sim-main.h (float_operation): Move enum declaration outside
1360 of _sim_cpu struct declaration.
1361
c0efbca4
JB		 13622001-04-12 Jim Blandy <jimb@redhat.com>
1363
1364 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1365 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1366 set of the FCSR.
1367 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1368 PENDING_FILL, and you can get the intended effect gracefully by
1369 calling PENDING_SCHED directly.
1370
fb891446
BE		 13712001-02-23 Ben Elliston <bje@redhat.com>
1372
1373 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1374 already defined elsewhere.
1375
8030f857
BE		 13762001-02-19 Ben Elliston <bje@redhat.com>
1377
1378 * sim-main.h (sim_monitor): Return an int.
1379 * interp.c (sim_monitor): Add return values.
1380 (signal_exception): Handle error conditions from sim_monitor.
1381
56b48a7a
CD		 13822001-02-08 Ben Elliston <bje@redhat.com>
1383
1384 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1385 (store_memory): Likewise, pass cia to sim_core_write*.
1386
d3ee60d9
FCE		 13872000-10-19 Frank Ch. Eigler <fche@redhat.com>
1388
1389 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1390 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1391
071da002
AC		 1392Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1393
1394 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1395 * Makefile.in: Don't delete *.igen when cleaning directory.
1396
a28c02cd
AC		 1397Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1398
1399 * m16.igen (break): Call SignalException not sim_engine_halt.
1400
80ee11fa
AC		 1401Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1402
1403 From Jason Eckhardt:
1404 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1405
673388c0
AC		 1406Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1407
1408 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1409
4c0deff4
NC		 14102000-05-24 Michael Hayes <mhayes@cygnus.com>
1411
1412 * mips.igen (do_dmultx): Fix typo.
1413
eb2d80b4
AC		 1414Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1415
1416 * configure: Regenerated to track ../common/aclocal.m4 changes.
1417
dd37a34b
AC		 1418Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1419
1420 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1421
4c0deff4
NC		 14222000-04-12 Frank Ch. Eigler <fche@redhat.com>
1423
1424 * sim-main.h (GPR_CLEAR): Define macro.
1425
e30db738
AC		 1426Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1427
1428 * interp.c (decode_coproc): Output long using %lx and not %s.
1429
cb7450ea
FCE		 14302000-03-21 Frank Ch. Eigler <fche@redhat.com>
1431
1432 * interp.c (sim_open): Sort & extend dummy memory regions for
1433 --board=jmr3904 for eCos.
1434
a3027dd7
FCE		 14352000-03-02 Frank Ch. Eigler <fche@redhat.com>
1436
1437 * configure: Regenerated.
1438
1439Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1440
1441 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1442 calls, conditional on the simulator being in verbose mode.
1443
dfcd3bfb
JM		 1444Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1445
1446 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1447 cache don't get ReservedInstruction traps.
1448
c2d11a7d
JM		 14491999-11-29 Mark Salter <msalter@cygnus.com>
1450
1451 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1452 to clear status bits in sdisr register. This is how the hardware works.
1453
1454 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1455 being used by cygmon.
1456
4ce44c66
JM		 14571999-11-11 Andrew Haley <aph@cygnus.com>
1458
1459 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1460 instructions.
1461
cff3e48b
JM		 1462Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1463
1464 * mips.igen (MULT): Correct previous mis-applied patch.
1465
d4f3574e
SS		 1466Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1467
1468 * mips.igen (delayslot32): Handle sequence like
1469 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1470 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1471 (MULT): Actually pass the third register...
1472
14731999-09-03 Mark Salter <msalter@cygnus.com>
1474
1475 * interp.c (sim_open): Added more memory aliases for additional
1476 hardware being touched by cygmon on jmr3904 board.
1477
1478Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1479
1480 * configure: Regenerated to track ../common/aclocal.m4 changes.
1481
a0b3c4fd
JM		 1482Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1483
1484 * interp.c (sim_store_register): Handle case where client - GDB -
1485 specifies that a 4 byte register is 8 bytes in size.
1486 (sim_fetch_register): Ditto.
72f4393d 1487
adf40b2e
JM		 14881999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1489
1490 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1491 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1492 (idt_monitor_base): Base address for IDT monitor traps.
1493 (pmon_monitor_base): Ditto for PMON.
1494 (lsipmon_monitor_base): Ditto for LSI PMON.
1495 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1496 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1497 (sim_firmware_command): New function.
1498 (mips_option_handler): Call it for OPTION_FIRMWARE.
1499 (sim_open): Allocate memory for idt_monitor region. If "--board"
1500 option was given, add no monitor by default. Add BREAK hooks only if
1501 monitors are also there.
72f4393d 1502
43e526b9
JM		 1503Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1504
1505 * interp.c (sim_monitor): Flush output before reading input.
1506
1507Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1508
1509 * tconfig.in (SIM_HANDLES_LMA): Always define.
1510
1511Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1512
1513 From Mark Salter <msalter@cygnus.com>:
1514 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1515 (sim_open): Add setup for BSP board.
1516
9846de1b
JM		 1517Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1518
1519 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1520 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1521 them as unimplemented.
1522
cd0fc7c3
SS		 15231999-05-08 Felix Lee <flee@cygnus.com>
1524
1525 * configure: Regenerated to track ../common/aclocal.m4 changes.
72f4393d 1526
7a292a7a
SS		 15271999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1528
1529 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1530
1531Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1532
1533 * configure.in: Any mips64vr5*-*-* target should have
1534 -DTARGET_ENABLE_FR=1.
1535 (default_endian): Any mips64vr*el-*-* target should default to
1536 LITTLE_ENDIAN.
1537 * configure: Re-generate.
1538
15391999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1540
1541 * mips.igen (ldl): Extend from _16_, not 32.
1542
1543Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1544
1545 * interp.c (sim_store_register): Force registers written to by GDB
1546 into an un-interpreted state.
1547
c906108c
SS		 15481999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1549
1550 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1551 CPU, start periodic background I/O polls.
72f4393d 1552 (tx3904sio_poll): New function: periodic I/O poller.
c906108c
SS		 1553
15541998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1555
1556 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
72f4393d 1557
c906108c
SS		 1558Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1559
1560 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1561 case statement.
1562
15631998-12-29 Frank Ch. Eigler <fche@cygnus.com>
72f4393d
L		 1564
1565 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
c906108c
SS		 1566 (load_word): Call SIM_CORE_SIGNAL hook on error.
1567 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1568 starting. For exception dispatching, pass PC instead of NULL_CIA.
1569 (decode_coproc): Use COP0_BADVADDR to store faulting address.
72f4393d 1570 * sim-main.h (COP0_BADVADDR): Define.
c906108c
SS		 1571 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1572 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
72f4393d 1573 (_sim_cpu): Add exc_* fields to store register value snapshots.
c906108c
SS		 1574 * mips.igen (*): Replace memory-related SignalException* calls
1575 with references to SIM_CORE_SIGNAL hook.
72f4393d 1576
c906108c
SS		 1577 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1578 fix.
1579 * sim-main.c (*): Minor warning cleanups.
72f4393d 1580
c906108c
SS		 15811998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1582
1583 * m16.igen (DADDIU5): Correct type-o.
1584
1585Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1586
1587 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1588 variables.
1589
1590Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1591
1592 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1593 to include path.
1594 (interp.o): Add dependency on itable.h
1595 (oengine.c, gencode): Delete remaining references.
1596 (BUILT_SRC_FROM_GEN): Clean up.
72f4393d 1597
c906108c 15981998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
72f4393d 1599
c906108c
SS		 1600 * vr4run.c: New.
1601 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1602 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1603 tmp-run-hack) : New.
1604 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
72f4393d 1605 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
c906108c
SS		 1606 Drop the "64" qualifier to get the HACK generator working.
1607 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1608 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1609 qualifier to get the hack generator working.
1610 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1611 (DSLL): Use do_dsll.
1612 (DSLLV): Use do_dsllv.
1613 (DSRA): Use do_dsra.
1614 (DSRL): Use do_dsrl.
1615 (DSRLV): Use do_dsrlv.
1616 (BC1): Move *vr4100 to get the HACK generator working.
72f4393d 1617 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
c906108c
SS		 1618 get the HACK generator working.
1619 (MACC) Rename to get the HACK generator working.
1620 (DMACC,MACCS,DMACCS): Add the 64.
72f4393d 1621
c906108c
SS		 16221998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1623
1624 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1625 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
72f4393d 1626
c906108c
SS		 16271998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1628
1629 * mips/interp.c (DEBUG): Cleanups.
1630
16311998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1632
1633 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1634 (tx3904sio_tickle): fflush after a stdout character output.
72f4393d 1635
c906108c
SS		 16361998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1637
1638 * interp.c (sim_close): Uninstall modules.
1639
1640Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1641
1642 * sim-main.h, interp.c (sim_monitor): Change to global
1643 function.
1644
1645Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1646
1647 * configure.in (vr4100): Only include vr4100 instructions in
1648 simulator.
1649 * configure: Re-generate.
1650 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1651
1652Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1653
1654 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1655 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1656 true alternative.
1657
1658 * configure.in (sim_default_gen, sim_use_gen): Replace with
1659 sim_gen.
1660 (--enable-sim-igen): Delete config option. Always using IGEN.
1661 * configure: Re-generate.
72f4393d 1662
c906108c
SS		 1663 * Makefile.in (gencode): Kill, kill, kill.
1664 * gencode.c: Ditto.
72f4393d 1665
c906108c
SS		 1666Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1667
1668 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1669 bit mips16 igen simulator.
1670 * configure: Re-generate.
1671
1672 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1673 as part of vr4100 ISA.
1674 * vr.igen: Mark all instructions as 64 bit only.
1675
1676Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1677
1678 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1679 Pacify GCC.
1680
1681Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1682
1683 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1684 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1685 * configure: Re-generate.
1686
1687 * m16.igen (BREAK): Define breakpoint instruction.
1688 (JALX32): Mark instruction as mips16 and not r3900.
1689 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1690
1691 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1692
1693Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1694
1695 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1696 insn as a debug breakpoint.
1697
1698 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1699 pending.slot_size.
1700 (PENDING_SCHED): Clean up trace statement.
1701 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1702 (PENDING_FILL): Delay write by only one cycle.
1703 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1704
1705 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1706 of pending writes.
1707 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1708 32 & 64.
1709 (pending_tick): Move incrementing of index to FOR statement.
1710 (pending_tick): Only update PENDING_OUT after a write has occured.
72f4393d 1711
c906108c
SS		 1712 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1713 build simulator.
1714 * configure: Re-generate.
72f4393d 1715
c906108c
SS		 1716 * interp.c (sim_engine_run OLD): Delete explicit call to
1717 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
72f4393d 1718
c906108c
SS		 1719Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1720
1721 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1722 interrupt level number to match changed SignalExceptionInterrupt
1723 macro.
1724
1725Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1726
1727 * interp.c: #include "itable.h" if WITH_IGEN.
1728 (get_insn_name): New function.
1729 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1730 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1731
1732Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1733
1734 * configure: Rebuilt to inhale new common/aclocal.m4.
1735
1736Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1737
1738 * dv-tx3904sio.c: Include sim-assert.h.
1739
1740Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1741
1742 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1743 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1744 Reorganize target-specific sim-hardware checks.
1745 * configure: rebuilt.
1746 * interp.c (sim_open): For tx39 target boards, set
1747 OPERATING_ENVIRONMENT, add tx3904sio devices.
1748 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1749 ROM executables. Install dv-sockser into sim-modules list.
72f4393d 1750
c906108c
SS		 1751 * dv-tx3904irc.c: Compiler warning clean-up.
1752 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1753 frequent hw-trace messages.
1754
1755Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1756
1757 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1758
1759Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1760
1761 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1762
1763 * vr.igen: New file.
1764 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1765 * mips.igen: Define vr4100 model. Include vr.igen.
1766Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1767
1768 * mips.igen (check_mf_hilo): Correct check.
1769
1770Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1771
1772 * sim-main.h (interrupt_event): Add prototype.
1773
1774 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1775 register_ptr, register_value.
1776 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1777
1778 * sim-main.h (tracefh): Make extern.
1779
1780Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1781
1782 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
72f4393d 1783 Reduce unnecessarily high timer event frequency.
c906108c 1784 * dv-tx3904cpu.c: Ditto for interrupt event.
72f4393d 1785
c906108c
SS		 1786Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1787
1788 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1789 to allay warnings.
1790 (interrupt_event): Made non-static.
72f4393d 1791
c906108c
SS		 1792 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1793 interchange of configuration values for external vs. internal
1794 clock dividers.
72f4393d 1795
c906108c
SS		 1796Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1797
72f4393d 1798 * mips.igen (BREAK): Moved code to here for
c906108c
SS		 1799 simulator-reserved break instructions.
1800 * gencode.c (build_instruction): Ditto.
1801 * interp.c (signal_exception): Code moved from here. Non-
72f4393d 1802 reserved instructions now use exception vector, rather
c906108c
SS		 1803 than halting sim.
1804 * sim-main.h: Moved magic constants to here.
1805
1806Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1807
1808 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1809 register upon non-zero interrupt event level, clear upon zero
1810 event value.
1811 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1812 by passing zero event value.
1813 (*_io_{read,write}_buffer): Endianness fixes.
1814 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1815 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1816
1817 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1818 serial I/O and timer module at base address 0xFFFF0000.
72f4393d 1819
c906108c
SS		 1820Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1821
72f4393d 1822 * mips.igen (SWC1) : Correct the handling of ReverseEndian
c906108c
SS		 1823 and BigEndianCPU.
1824
1825Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1826
1827 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1828 parts.
1829 * configure: Update.
1830
1831Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1832
1833 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1834 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1835 * configure.in: Include tx3904tmr in hw_device list.
1836 * configure: Rebuilt.
1837 * interp.c (sim_open): Instantiate three timer instances.
1838 Fix address typo of tx3904irc instance.
1839
1840Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1841
1842 * interp.c (signal_exception): SystemCall exception now uses
1843 the exception vector.
1844
1845Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1846
1847 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1848 to allay warnings.
1849
1850Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1851
1852 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1853
1854Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1855
1856 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1857
1858 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1859 sim-main.h. Declare a struct hw_descriptor instead of struct
1860 hw_device_descriptor.
1861
1862Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1863
1864 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1865 right bits and then re-align left hand bytes to correct byte
1866 lanes. Fix incorrect computation in do_store_left when loading
1867 bytes from second word.
1868
1869Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1870
1871 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1872 * interp.c (sim_open): Only create a device tree when HW is
1873 enabled.
1874
1875 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1876 * interp.c (signal_exception): Ditto.
1877
1878Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1879
1880 * gencode.c: Mark BEGEZALL as LIKELY.
1881
1882Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1883
1884 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1885 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
72f4393d 1886
c906108c
SS		 1887Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1888
1889 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1890 modules. Recognize TX39 target with "mips*tx39" pattern.
1891 * configure: Rebuilt.
1892 * sim-main.h (*): Added many macros defining bits in
1893 TX39 control registers.
1894 (SignalInterrupt): Send actual PC instead of NULL.
1895 (SignalNMIReset): New exception type.
1896 * interp.c (board): New variable for future use to identify
1897 a particular board being simulated.
1898 (mips_option_handler,mips_options): Added "--board" option.
1899 (interrupt_event): Send actual PC.
1900 (sim_open): Make memory layout conditional on board setting.
1901 (signal_exception): Initial implementation of hardware interrupt
1902 handling. Accept another break instruction variant for simulator
1903 exit.
1904 (decode_coproc): Implement RFE instruction for TX39.
1905 (mips.igen): Decode RFE instruction as such.
1906 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1907 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1908 bbegin to implement memory map.
1909 * dv-tx3904cpu.c: New file.
1910 * dv-tx3904irc.c: New file.
1911
1912Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1913
1914 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1915
1916Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1917
1918 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1919 with calls to check_div_hilo.
1920
1921Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1922
1923 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1924 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
72f4393d 1925 Add special r3900 version of do_mult_hilo.
c906108c
SS		 1926 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1927 with calls to check_mult_hilo.
1928 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1929 with calls to check_div_hilo.
1930
1931Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1932
1933 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1934 Document a replacement.
1935
1936Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1937
1938 * interp.c (sim_monitor): Make mon_printf work.
1939
1940Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1941
1942 * sim-main.h (INSN_NAME): New arg `cpu'.
1943
1944Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1945
72f4393d 1946 * configure: Regenerated to track ../common/aclocal.m4 changes.
c906108c
SS		 1947
1948Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1949
1950 * configure: Regenerated to track ../common/aclocal.m4 changes.
1951 * config.in: Ditto.
1952
1953Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1954
1955 * acconfig.h: New file.
1956 * configure.in: Reverted change of Apr 24; use sinclude again.
1957
1958Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1959
1960 * configure: Regenerated to track ../common/aclocal.m4 changes.
1961 * config.in: Ditto.
1962
1963Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1964
1965 * configure.in: Don't call sinclude.
1966
1967Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1968
1969 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1970
1971Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1972
1973 * mips.igen (ERET): Implement.
1974
1975 * interp.c (decode_coproc): Return sign-extended EPC.
1976
1977 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1978
1979 * interp.c (signal_exception): Do not ignore Trap.
1980 (signal_exception): On TRAP, restart at exception address.
1981 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1982 (signal_exception): Update.
1983 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1984 so that TRAP instructions are caught.
1985
1986Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1987
1988 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1989 contains HI/LO access history.
1990 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1991 (HIACCESS, LOACCESS): Delete, replace with
1992 (HIHISTORY, LOHISTORY): New macros.
1993 (CHECKHILO): Delete all, moved to mips.igen
72f4393d 1994
c906108c
SS		 1995 * gencode.c (build_instruction): Do not generate checks for
1996 correct HI/LO register usage.
1997
1998 * interp.c (old_engine_run): Delete checks for correct HI/LO
1999 register usage.
2000
2001 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
2002 check_mf_cycles): New functions.
2003 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
2004 do_divu, domultx, do_mult, do_multu): Use.
2005
2006 * tx.igen ("madd", "maddu"): Use.
72f4393d 2007
c906108c
SS		 2008Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
2009
2010 * mips.igen (DSRAV): Use function do_dsrav.
2011 (SRAV): Use new function do_srav.
2012
2013 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
2014 (B): Sign extend 11 bit immediate.
2015 (EXT-B*): Shift 16 bit immediate left by 1.
2016 (ADDIU*): Don't sign extend immediate value.
2017
2018Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2019
2020 * m16run.c (sim_engine_run): Restore CIA after handling an event.
2021
2022 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
2023 functions.
2024
2025 * mips.igen (delayslot32, nullify_next_insn): New functions.
2026 (m16.igen): Always include.
2027 (do_*): Add more tracing.
2028
2029 * m16.igen (delayslot16): Add NIA argument, could be called by a
2030 32 bit MIPS16 instruction.
72f4393d 2031
c906108c
SS		 2032 * interp.c (ifetch16): Move function from here.
2033 * sim-main.c (ifetch16): To here.
72f4393d 2034
c906108c
SS		 2035 * sim-main.c (ifetch16, ifetch32): Update to match current
2036 implementations of LH, LW.
2037 (signal_exception): Don't print out incorrect hex value of illegal
2038 instruction.
2039
2040Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2041
2042 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
2043 instruction.
2044
2045 * m16.igen: Implement MIPS16 instructions.
72f4393d 2046
c906108c
SS		 2047 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
2048 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
2049 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
2050 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
2051 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
2052 bodies of corresponding code from 32 bit insn to these. Also used
2053 by MIPS16 versions of functions.
72f4393d 2054
c906108c
SS		 2055 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
2056 (IMEM16): Drop NR argument from macro.
2057
2058Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2059
2060 * Makefile.in (SIM_OBJS): Add sim-main.o.
2061
2062 * sim-main.h (address_translation, load_memory, store_memory,
2063 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
2064 as INLINE_SIM_MAIN.
2065 (pr_addr, pr_uword64): Declare.
2066 (sim-main.c): Include when H_REVEALS_MODULE_P.
72f4393d 2067
c906108c
SS		 2068 * interp.c (address_translation, load_memory, store_memory,
2069 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
2070 from here.
2071 * sim-main.c: To here. Fix compilation problems.
72f4393d 2072
c906108c
SS		 2073 * configure.in: Enable inlining.
2074 * configure: Re-config.
2075
2076Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2077
2078 * configure: Regenerated to track ../common/aclocal.m4 changes.
2079
2080Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2081
2082 * mips.igen: Include tx.igen.
2083 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
2084 * tx.igen: New file, contains MADD and MADDU.
2085
2086 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
2087 the hardwired constant `7'.
2088 (store_memory): Ditto.
2089 (LOADDRMASK): Move definition to sim-main.h.
2090
2091 mips.igen (MTC0): Enable for r3900.
2092 (ADDU): Add trace.
2093
2094 mips.igen (do_load_byte): Delete.
2095 (do_load, do_store, do_load_left, do_load_write, do_store_left,
2096 do_store_right): New functions.
2097 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
2098
2099 configure.in: Let the tx39 use igen again.
2100 configure: Update.
72f4393d 2101
c906108c
SS		 2102Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2103
2104 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
2105 not an address sized quantity. Return zero for cache sizes.
2106
2107Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
2108
2109 * mips.igen (r3900): r3900 does not support 64 bit integer
2110 operations.
2111
2112Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
2113
2114 * configure.in (mipstx39*-*-*): Use gencode simulator rather
2115 than igen one.
2116 * configure : Rebuild.
72f4393d 2117
c906108c
SS		 2118Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
2119
2120 * configure: Regenerated to track ../common/aclocal.m4 changes.
2121
2122Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2123
2124 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
2125
2126Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
2127
2128 * configure: Regenerated to track ../common/aclocal.m4 changes.
2129 * config.in: Regenerated to track ../common/aclocal.m4 changes.
2130
2131Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2132
2133 * configure: Regenerated to track ../common/aclocal.m4 changes.
2134
2135Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
2136
2137 * interp.c (Max, Min): Comment out functions. Not yet used.
2138
2139Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
2140
2141 * configure: Regenerated to track ../common/aclocal.m4 changes.
2142
2143Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
2144
2145 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
2146 configurable settings for stand-alone simulator.
72f4393d 2147
c906108c 2148 * configure.in: Added X11 search, just in case.
72f4393d 2149
c906108c
SS		 2150 * configure: Regenerated.
2151
2152Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
2153
2154 * interp.c (sim_write, sim_read, load_memory, store_memory):
2155 Replace sim_core_*_map with read_map, write_map, exec_map resp.
2156
2157Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
2158
2159 * sim-main.h (GETFCC): Return an unsigned value.
2160
2161Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2162
2163 * mips.igen (DIV): Fix check for -1 / MIN_INT.
2164 (DADD): Result destination is RD not RT.
2165
2166Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2167
2168 * sim-main.h (HIACCESS, LOACCESS): Always define.
2169
2170 * mdmx.igen (Maxi, Mini): Rename Max, Min.
2171
2172 * interp.c (sim_info): Delete.
2173
2174Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
2175
2176 * interp.c (DECLARE_OPTION_HANDLER): Use it.
2177 (mips_option_handler): New argument `cpu'.
2178 (sim_open): Update call to sim_add_option_table.
2179
2180Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
2181
2182 * mips.igen (CxC1): Add tracing.
2183
2184Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
2185
2186 * sim-main.h (Max, Min): Declare.
2187
2188 * interp.c (Max, Min): New functions.
2189
2190 * mips.igen (BC1): Add tracing.
72f4393d 2191
c906108c 2192Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
72f4393d 2193
c906108c 2194 * interp.c Added memory map for stack in vr4100
72f4393d 2195
c906108c
SS		 2196Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
2197
2198 * interp.c (load_memory): Add missing "break"'s.
2199
2200Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2201
2202 * interp.c (sim_store_register, sim_fetch_register): Pass in
2203 length parameter. Return -1.
2204
2205Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
2206
2207 * interp.c: Added hardware init hook, fixed warnings.
2208
2209Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2210
2211 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
2212
2213Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
2214
2215 * interp.c (ifetch16): New function.
2216
2217 * sim-main.h (IMEM32): Rename IMEM.
2218 (IMEM16_IMMED): Define.
2219 (IMEM16): Define.
2220 (DELAY_SLOT): Update.
72f4393d 2221
c906108c 2222 * m16run.c (sim_engine_run): New file.
72f4393d 2223
c906108c
SS		 2224 * m16.igen: All instructions except LB.
2225 (LB): Call do_load_byte.
2226 * mips.igen (do_load_byte): New function.
2227 (LB): Call do_load_byte.
2228
2229 * mips.igen: Move spec for insn bit size and high bit from here.
2230 * Makefile.in (tmp-igen, tmp-m16): To here.
2231
2232 * m16.dc: New file, decode mips16 instructions.
2233
2234 * Makefile.in (SIM_NO_ALL): Define.
2235 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
2236
2237Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
2238
2239 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
2240 point unit to 32 bit registers.
2241 * configure: Re-generate.
2242
2243Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2244
2245 * configure.in (sim_use_gen): Make IGEN the default simulator
2246 generator for generic 32 and 64 bit mips targets.
2247 * configure: Re-generate.
2248
2249Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2250
2251 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
2252 bitsize.
2253
2254 * interp.c (sim_fetch_register, sim_store_register): Read/write
2255 FGR from correct location.
2256 (sim_open): Set size of FGR's according to
2257 WITH_TARGET_FLOATING_POINT_BITSIZE.
72f4393d 2258
c906108c
SS		 2259 * sim-main.h (FGR): Store floating point registers in a separate
2260 array.
2261
2262Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
2263
2264 * configure: Regenerated to track ../common/aclocal.m4 changes.
2265
2266Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2267
2268 * interp.c (ColdReset): Call PENDING_INVALIDATE.
2269
2270 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
2271
2272 * interp.c (pending_tick): New function. Deliver pending writes.
2273
2274 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2275 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2276 it can handle mixed sized quantites and single bits.
72f4393d 2277
c906108c
SS		 2278Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2279
2280 * interp.c (oengine.h): Do not include when building with IGEN.
2281 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2282 (sim_info): Ditto for PROCESSOR_64BIT.
2283 (sim_monitor): Replace ut_reg with unsigned_word.
2284 (*): Ditto for t_reg.
2285 (LOADDRMASK): Define.
2286 (sim_open): Remove defunct check that host FP is IEEE compliant,
2287 using software to emulate floating point.
2288 (value_fpr, ...): Always compile, was conditional on HASFPU.
2289
2290Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2291
2292 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2293 size.
2294
2295 * interp.c (SD, CPU): Define.
2296 (mips_option_handler): Set flags in each CPU.
2297 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2298 (sim_close): Do not clear STATE, deleted anyway.
2299 (sim_write, sim_read): Assume CPU zero's vm should be used for
2300 data transfers.
2301 (sim_create_inferior): Set the PC for all processors.
2302 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2303 argument.
2304 (mips16_entry): Pass correct nr of args to store_word, load_word.
2305 (ColdReset): Cold reset all cpu's.
2306 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2307 (sim_monitor, load_memory, store_memory, signal_exception): Use
2308 `CPU' instead of STATE_CPU.
2309
2310
2311 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2312 SD or CPU_.
72f4393d 2313
c906108c
SS		 2314 * sim-main.h (signal_exception): Add sim_cpu arg.
2315 (SignalException*): Pass both SD and CPU to signal_exception.
2316 * interp.c (signal_exception): Update.
72f4393d 2317
c906108c
SS		 2318 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2319 Ditto
2320 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2321 address_translation): Ditto
2322 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
72f4393d 2323
c906108c
SS		 2324Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2325
2326 * configure: Regenerated to track ../common/aclocal.m4 changes.
2327
2328Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2329
2330 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2331
72f4393d 2332 * mips.igen (model): Map processor names onto BFD name.
c906108c
SS		 2333
2334 * sim-main.h (CPU_CIA): Delete.
2335 (SET_CIA, GET_CIA): Define
2336
2337Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2338
2339 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2340 regiser.
2341
2342 * configure.in (default_endian): Configure a big-endian simulator
2343 by default.
2344 * configure: Re-generate.
72f4393d 2345
c906108c
SS		 2346Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2347
2348 * configure: Regenerated to track ../common/aclocal.m4 changes.
2349
2350Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2351
2352 * interp.c (sim_monitor): Handle Densan monitor outbyte
2353 and inbyte functions.
2354
23551997-12-29 Felix Lee <flee@cygnus.com>
2356
2357 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2358
2359Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2360
2361 * Makefile.in (tmp-igen): Arrange for $zero to always be
2362 reset to zero after every instruction.
2363
2364Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2365
2366 * configure: Regenerated to track ../common/aclocal.m4 changes.
2367 * config.in: Ditto.
2368
2369Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2370
2371 * mips.igen (MSUB): Fix to work like MADD.
2372 * gencode.c (MSUB): Similarly.
2373
2374Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2375
2376 * configure: Regenerated to track ../common/aclocal.m4 changes.
2377
2378Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2379
2380 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2381
2382Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2383
2384 * sim-main.h (sim-fpu.h): Include.
2385
2386 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2387 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2388 using host independant sim_fpu module.
2389
2390Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2391
2392 * interp.c (signal_exception): Report internal errors with SIGABRT
2393 not SIGQUIT.
2394
2395 * sim-main.h (C0_CONFIG): New register.
2396 (signal.h): No longer include.
2397
2398 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2399
2400Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2401
2402 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2403
2404Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2405
2406 * mips.igen: Tag vr5000 instructions.
2407 (ANDI): Was missing mipsIV model, fix assembler syntax.
2408 (do_c_cond_fmt): New function.
2409 (C.cond.fmt): Handle mips I-III which do not support CC field
2410 separatly.
2411 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2412 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2413 in IV3.2 spec.
2414 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2415 vr5000 which saves LO in a GPR separatly.
72f4393d 2416
c906108c
SS		 2417 * configure.in (enable-sim-igen): For vr5000, select vr5000
2418 specific instructions.
2419 * configure: Re-generate.
72f4393d 2420
c906108c
SS		 2421Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2422
2423 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2424
2425 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2426 fmt_uninterpreted_64 bit cases to switch. Convert to
2427 fmt_formatted,
2428
2429 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2430
2431 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2432 as specified in IV3.2 spec.
2433 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2434
2435Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2436
2437 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2438 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2439 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2440 PENDING_FILL versions of instructions. Simplify.
2441 (X): New function.
2442 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2443 instructions.
2444 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2445 a signed value.
2446 (MTHI, MFHI): Disable code checking HI-LO.
72f4393d 2447
c906108c
SS		 2448 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2449 global.
2450 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2451
2452Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2453
2454 * gencode.c (build_mips16_operands): Replace IPC with cia.
2455
2456 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2457 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2458 IPC to `cia'.
2459 (UndefinedResult): Replace function with macro/function
2460 combination.
2461 (sim_engine_run): Don't save PC in IPC.
2462
2463 * sim-main.h (IPC): Delete.
2464
2465
2466 * interp.c (signal_exception, store_word, load_word,
2467 address_translation, load_memory, store_memory, cache_op,
2468 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2469 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2470 current instruction address - cia - argument.
2471 (sim_read, sim_write): Call address_translation directly.
2472 (sim_engine_run): Rename variable vaddr to cia.
2473 (signal_exception): Pass cia to sim_monitor
72f4393d 2474
c906108c
SS		 2475 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2476 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2477 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2478
2479 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2480 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2481 SIM_ASSERT.
72f4393d 2482
c906108c
SS		 2483 * interp.c (signal_exception): Pass restart address to
2484 sim_engine_restart.
2485
2486 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2487 idecode.o): Add dependency.
2488
2489 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2490 Delete definitions
2491 (DELAY_SLOT): Update NIA not PC with branch address.
2492 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2493
2494 * mips.igen: Use CIA not PC in branch calculations.
2495 (illegal): Call SignalException.
2496 (BEQ, ADDIU): Fix assembler.
2497
2498Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2499
2500 * m16.igen (JALX): Was missing.
2501
2502 * configure.in (enable-sim-igen): New configuration option.
2503 * configure: Re-generate.
72f4393d 2504
c906108c
SS		 2505 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2506
2507 * interp.c (load_memory, store_memory): Delete parameter RAW.
2508 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2509 bypassing {load,store}_memory.
2510
2511 * sim-main.h (ByteSwapMem): Delete definition.
2512
2513 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2514
2515 * interp.c (sim_do_command, sim_commands): Delete mips specific
2516 commands. Handled by module sim-options.
72f4393d 2517
c906108c
SS		 2518 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2519 (WITH_MODULO_MEMORY): Define.
2520
2521 * interp.c (sim_info): Delete code printing memory size.
2522
2523 * interp.c (mips_size): Nee sim_size, delete function.
2524 (power2): Delete.
2525 (monitor, monitor_base, monitor_size): Delete global variables.
2526 (sim_open, sim_close): Delete code creating monitor and other
2527 memory regions. Use sim-memopts module, via sim_do_commandf, to
2528 manage memory regions.
2529 (load_memory, store_memory): Use sim-core for memory model.
72f4393d 2530
c906108c
SS		 2531 * interp.c (address_translation): Delete all memory map code
2532 except line forcing 32 bit addresses.
2533
2534Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2535
2536 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2537 trace options.
2538
2539 * interp.c (logfh, logfile): Delete globals.
2540 (sim_open, sim_close): Delete code opening & closing log file.
2541 (mips_option_handler): Delete -l and -n options.
2542 (OPTION mips_options): Ditto.
2543
2544 * interp.c (OPTION mips_options): Rename option trace to dinero.
2545 (mips_option_handler): Update.
2546
2547Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2548
2549 * interp.c (fetch_str): New function.
2550 (sim_monitor): Rewrite using sim_read & sim_write.
2551 (sim_open): Check magic number.
2552 (sim_open): Write monitor vectors into memory using sim_write.
2553 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2554 (sim_read, sim_write): Simplify - transfer data one byte at a
2555 time.
2556 (load_memory, store_memory): Clarify meaning of parameter RAW.
2557
2558 * sim-main.h (isHOST): Defete definition.
2559 (isTARGET): Mark as depreciated.
2560 (address_translation): Delete parameter HOST.
2561
2562 * interp.c (address_translation): Delete parameter HOST.
2563
2564Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2565
72f4393d 2566 * mips.igen:
c906108c
SS		 2567
2568 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2569 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2570
2571Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2572
2573 * mips.igen: Add model filter field to records.
2574
2575Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2576
2577 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
72f4393d 2578
c906108c
SS		 2579 interp.c (sim_engine_run): Do not compile function sim_engine_run
2580 when WITH_IGEN == 1.
2581
2582 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2583 target architecture.
2584
2585 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2586 igen. Replace with configuration variables sim_igen_flags /
2587 sim_m16_flags.
2588
2589 * m16.igen: New file. Copy mips16 insns here.
2590 * mips.igen: From here.
2591
2592Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2593
2594 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2595 to top.
2596 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2597
2598Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2599
2600 * gencode.c (build_instruction): Follow sim_write's lead in using
2601 BigEndianMem instead of !ByteSwapMem.
2602
2603Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2604
2605 * configure.in (sim_gen): Dependent on target, select type of
2606 generator. Always select old style generator.
2607
2608 configure: Re-generate.
2609
2610 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2611 targets.
2612 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2613 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2614 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2615 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2616 SIM_@sim_gen@_*, set by autoconf.
72f4393d 2617
c906108c
SS		 2618Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2619
2620 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2621
2622 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2623 CURRENT_FLOATING_POINT instead.
2624
2625 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2626 (address_translation): Raise exception InstructionFetch when
2627 translation fails and isINSTRUCTION.
72f4393d 2628
c906108c
SS		 2629 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2630 sim_engine_run): Change type of of vaddr and paddr to
2631 address_word.
2632 (address_translation, prefetch, load_memory, store_memory,
2633 cache_op): Change type of vAddr and pAddr to address_word.
2634
2635 * gencode.c (build_instruction): Change type of vaddr and paddr to
2636 address_word.
2637
2638Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2639
2640 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2641 macro to obtain result of ALU op.
2642
2643Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2644
2645 * interp.c (sim_info): Call profile_print.
2646
2647Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2648
2649 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2650
2651 * sim-main.h (WITH_PROFILE): Do not define, defined in
2652 common/sim-config.h. Use sim-profile module.
2653 (simPROFILE): Delete defintion.
2654
2655 * interp.c (PROFILE): Delete definition.
2656 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2657 (sim_close): Delete code writing profile histogram.
2658 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2659 Delete.
2660 (sim_engine_run): Delete code profiling the PC.
2661
2662Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2663
2664 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2665
2666 * interp.c (sim_monitor): Make register pointers of type
2667 unsigned_word*.
2668
2669 * sim-main.h: Make registers of type unsigned_word not
2670 signed_word.
2671
2672Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2673
2674 * interp.c (sync_operation): Rename from SyncOperation, make
2675 global, add SD argument.
2676 (prefetch): Rename from Prefetch, make global, add SD argument.
2677 (decode_coproc): Make global.
2678
2679 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2680
2681 * gencode.c (build_instruction): Generate DecodeCoproc not
2682 decode_coproc calls.
2683
2684 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2685 (SizeFGR): Move to sim-main.h
2686 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2687 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2688 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2689 sim-main.h.
2690 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2691 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2692 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2693 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2694 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2695 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
72f4393d 2696
c906108c
SS		 2697 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2698 exception.
2699 (sim-alu.h): Include.
2700 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2701 (sim_cia): Typedef to instruction_address.
72f4393d 2702
c906108c
SS		 2703Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2704
2705 * Makefile.in (interp.o): Rename generated file engine.c to
2706 oengine.c.
72f4393d 2707
c906108c 2708 * interp.c: Update.
72f4393d 2709
c906108c
SS		 2710Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2711
2712 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
72f4393d 2713
c906108c
SS		 2714Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2715
2716 * gencode.c (build_instruction): For "FPSQRT", output correct
2717 number of arguments to Recip.
72f4393d 2718
c906108c
SS		 2719Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2720
2721 * Makefile.in (interp.o): Depends on sim-main.h
2722
2723 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2724
2725 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2726 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2727 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2728 STATE, DSSTATE): Define
2729 (GPR, FGRIDX, ..): Define.
2730
2731 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2732 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2733 (GPR, FGRIDX, ...): Delete macros.
72f4393d 2734
c906108c 2735 * interp.c: Update names to match defines from sim-main.h
72f4393d 2736
c906108c
SS		 2737Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2738
2739 * interp.c (sim_monitor): Add SD argument.
2740 (sim_warning): Delete. Replace calls with calls to
2741 sim_io_eprintf.
2742 (sim_error): Delete. Replace calls with sim_io_error.
2743 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2744 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2745 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2746 argument.
2747 (mips_size): Rename from sim_size. Add SD argument.
2748
2749 * interp.c (simulator): Delete global variable.
2750 (callback): Delete global variable.
2751 (mips_option_handler, sim_open, sim_write, sim_read,
2752 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2753 sim_size,sim_monitor): Use sim_io_* not callback->*.
2754 (sim_open): ZALLOC simulator struct.
2755 (PROFILE): Do not define.
2756
2757Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2758
2759 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2760 support.h with corresponding code.
2761
2762 * sim-main.h (word64, uword64), support.h: Move definition to
2763 sim-main.h.
2764 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2765
2766 * support.h: Delete
2767 * Makefile.in: Update dependencies
2768 * interp.c: Do not include.
72f4393d 2769
c906108c
SS		 2770Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2771
2772 * interp.c (address_translation, load_memory, store_memory,
2773 cache_op): Rename to from AddressTranslation et.al., make global,
2774 add SD argument
72f4393d 2775
c906108c
SS		 2776 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2777 CacheOp): Define.
72f4393d 2778
c906108c
SS		 2779 * interp.c (SignalException): Rename to signal_exception, make
2780 global.
2781
2782 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
72f4393d 2783
c906108c
SS		 2784 * sim-main.h (SignalException, SignalExceptionInterrupt,
2785 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2786 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2787 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2788 Define.
72f4393d 2789
c906108c 2790 * interp.c, support.h: Use.
72f4393d 2791
c906108c
SS		 2792Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2793
2794 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2795 to value_fpr / store_fpr. Add SD argument.
2796 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2797 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2798
2799 * sim-main.h (ValueFPR, StoreFPR): Define.
72f4393d 2800
c906108c
SS		 2801Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2802
2803 * interp.c (sim_engine_run): Check consistency between configure
2804 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2805 and HASFPU.
2806
2807 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
72f4393d 2808 (mips_fpu): Configure WITH_FLOATING_POINT.
c906108c
SS		 2809 (mips_endian): Configure WITH_TARGET_ENDIAN.
2810 * configure: Update.
2811
2812Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2813
2814 * configure: Regenerated to track ../common/aclocal.m4 changes.
2815
2816Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2817
2818 * configure: Regenerated.
2819
2820Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2821
2822 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2823
2824Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2825
2826 * gencode.c (print_igen_insn_models): Assume certain architectures
2827 include all mips* instructions.
2828 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2829 instruction.
2830
2831 * Makefile.in (tmp.igen): Add target. Generate igen input from
2832 gencode file.
2833
2834 * gencode.c (FEATURE_IGEN): Define.
2835 (main): Add --igen option. Generate output in igen format.
2836 (process_instructions): Format output according to igen option.
2837 (print_igen_insn_format): New function.
2838 (print_igen_insn_models): New function.
2839 (process_instructions): Only issue warnings and ignore
2840 instructions when no FEATURE_IGEN.
2841
2842Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2843
2844 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2845 MIPS targets.
2846
2847Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2848
2849 * configure: Regenerated to track ../common/aclocal.m4 changes.
2850
2851Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2852
2853 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2854 SIM_RESERVED_BITS): Delete, moved to common.
2855 (SIM_EXTRA_CFLAGS): Update.
72f4393d 2856
c906108c
SS		 2857Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2858
2859 * configure.in: Configure non-strict memory alignment.
2860 * configure: Regenerated to track ../common/aclocal.m4 changes.
2861
2862Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2863
2864 * configure: Regenerated to track ../common/aclocal.m4 changes.
2865
2866Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2867
2868 * gencode.c (SDBBP,DERET): Added (3900) insns.
2869 (RFE): Turn on for 3900.
2870 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2871 (dsstate): Made global.
2872 (SUBTARGET_R3900): Added.
2873 (CANCELDELAYSLOT): New.
2874 (SignalException): Ignore SystemCall rather than ignore and
2875 terminate. Add DebugBreakPoint handling.
2876 (decode_coproc): New insns RFE, DERET; and new registers Debug
2877 and DEPC protected by SUBTARGET_R3900.
2878 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2879 bits explicitly.
2880 * Makefile.in,configure.in: Add mips subtarget option.
72f4393d 2881 * configure: Update.
c906108c
SS		 2882
2883Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2884
2885 * gencode.c: Add r3900 (tx39).
72f4393d 2886
c906108c
SS		 2887
2888Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2889
2890 * gencode.c (build_instruction): Don't need to subtract 4 for
2891 JALR, just 2.
2892
2893Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2894
2895 * interp.c: Correct some HASFPU problems.
2896
2897Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2898
2899 * configure: Regenerated to track ../common/aclocal.m4 changes.
2900
2901Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2902
2903 * interp.c (mips_options): Fix samples option short form, should
2904 be `x'.
2905
2906Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2907
2908 * interp.c (sim_info): Enable info code. Was just returning.
2909
2910Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2911
2912 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2913 MFC0.
2914
2915Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2916
2917 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2918 constants.
2919 (build_instruction): Ditto for LL.
2920
2921Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2922
2923 * configure: Regenerated to track ../common/aclocal.m4 changes.
2924
2925Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2926
2927 * configure: Regenerated to track ../common/aclocal.m4 changes.
2928 * config.in: Ditto.
2929
2930Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2931
2932 * interp.c (sim_open): Add call to sim_analyze_program, update
2933 call to sim_config.
2934
2935Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2936
2937 * interp.c (sim_kill): Delete.
2938 (sim_create_inferior): Add ABFD argument. Set PC from same.
2939 (sim_load): Move code initializing trap handlers from here.
2940 (sim_open): To here.
2941 (sim_load): Delete, use sim-hload.c.
2942
2943 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2944
2945Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2946
2947 * configure: Regenerated to track ../common/aclocal.m4 changes.
2948 * config.in: Ditto.
2949
2950Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2951
2952 * interp.c (sim_open): Add ABFD argument.
2953 (sim_load): Move call to sim_config from here.
2954 (sim_open): To here. Check return status.
2955
2956Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
72f4393d 2957
c906108c
SS		 2958 * gencode.c (build_instruction): Two arg MADD should
2959 not assign result to $0.
72f4393d 2960
c906108c
SS		 2961Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2962
2963 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2964 * sim/mips/configure.in: Regenerate.
2965
2966Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2967
2968 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2969 signed8, unsigned8 et.al. types.
2970
2971 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2972 hosts when selecting subreg.
2973
2974Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2975
2976 * interp.c (sim_engine_run): Reset the ZERO register to zero
2977 regardless of FEATURE_WARN_ZERO.
2978 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2979
2980Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2981
2982 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2983 (SignalException): For BreakPoints ignore any mode bits and just
2984 save the PC.
2985 (SignalException): Always set the CAUSE register.
2986
2987Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2988
2989 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2990 exception has been taken.
2991
2992 * interp.c: Implement the ERET and mt/f sr instructions.
2993
2994Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2995
2996 * interp.c (SignalException): Don't bother restarting an
2997 interrupt.
2998
2999Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3000
3001 * interp.c (SignalException): Really take an interrupt.
3002 (interrupt_event): Only deliver interrupts when enabled.
3003
3004Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
3005
3006 * interp.c (sim_info): Only print info when verbose.
3007 (sim_info) Use sim_io_printf for output.
72f4393d 3008
c906108c
SS		 3009Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3010
3011 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
3012 mips architectures.
3013
3014Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3015
3016 * interp.c (sim_do_command): Check for common commands if a
3017 simulator specific command fails.
3018
3019Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
3020
3021 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
3022 and simBE when DEBUG is defined.
3023
3024Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
3025
3026 * interp.c (interrupt_event): New function. Pass exception event
3027 onto exception handler.
3028
3029 * configure.in: Check for stdlib.h.
3030 * configure: Regenerate.
3031
3032 * gencode.c (build_instruction): Add UNUSED attribute to tempS
3033 variable declaration.
3034 (build_instruction): Initialize memval1.
3035 (build_instruction): Add UNUSED attribute to byte, bigend,
3036 reverse.
3037 (build_operands): Ditto.
3038
3039 * interp.c: Fix GCC warnings.
3040 (sim_get_quit_code): Delete.
3041
3042 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
3043 * Makefile.in: Ditto.
3044 * configure: Re-generate.
72f4393d 3045
c906108c
SS		 3046 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
3047
3048Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
3049
3050 * interp.c (mips_option_handler): New function parse argumes using
3051 sim-options.
3052 (myname): Replace with STATE_MY_NAME.
3053 (sim_open): Delete check for host endianness - performed by
3054 sim_config.
3055 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
3056 (sim_open): Move much of the initialization from here.
3057 (sim_load): To here. After the image has been loaded and
3058 endianness set.
3059 (sim_open): Move ColdReset from here.
3060 (sim_create_inferior): To here.
3061 (sim_open): Make FP check less dependant on host endianness.
3062
3063 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
3064 run.
3065 * interp.c (sim_set_callbacks): Delete.
3066
3067 * interp.c (membank, membank_base, membank_size): Replace with
3068 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
3069 (sim_open): Remove call to callback->init. gdb/run do this.
3070
3071 * interp.c: Update
3072
3073 * sim-main.h (SIM_HAVE_FLATMEM): Define.
3074
3075 * interp.c (big_endian_p): Delete, replaced by
3076 current_target_byte_order.
3077
3078Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3079
3080 * interp.c (host_read_long, host_read_word, host_swap_word,
3081 host_swap_long): Delete. Using common sim-endian.
3082 (sim_fetch_register, sim_store_register): Use H2T.
3083 (pipeline_ticks): Delete. Handled by sim-events.
3084 (sim_info): Update.
3085 (sim_engine_run): Update.
3086
3087Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
3088
3089 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
3090 reason from here.
3091 (SignalException): To here. Signal using sim_engine_halt.
3092 (sim_stop_reason): Delete, moved to common.
72f4393d 3093
c906108c
SS		 3094Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
3095
3096 * interp.c (sim_open): Add callback argument.
3097 (sim_set_callbacks): Delete SIM_DESC argument.
3098 (sim_size): Ditto.
3099
3100Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3101
3102 * Makefile.in (SIM_OBJS): Add common modules.
3103
3104 * interp.c (sim_set_callbacks): Also set SD callback.
3105 (set_endianness, xfer_*, swap_*): Delete.
3106 (host_read_word, host_read_long, host_swap_word, host_swap_long):
3107 Change to functions using sim-endian macros.
3108 (control_c, sim_stop): Delete, use common version.
3109 (simulate): Convert into.
3110 (sim_engine_run): This function.
3111 (sim_resume): Delete.
72f4393d 3112
c906108c
SS		 3113 * interp.c (simulation): New variable - the simulator object.
3114 (sim_kind): Delete global - merged into simulation.
3115 (sim_load): Cleanup. Move PC assignment from here.
3116 (sim_create_inferior): To here.
3117
3118 * sim-main.h: New file.
3119 * interp.c (sim-main.h): Include.
72f4393d 3120
c906108c
SS		 3121Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
3122
3123 * configure: Regenerated to track ../common/aclocal.m4 changes.
3124
3125Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
3126
3127 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
3128
3129Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
3130
72f4393d
L		 3131 * gencode.c (build_instruction): DIV instructions: check
3132 for division by zero and integer overflow before using
c906108c
SS		 3133 host's division operation.
3134
3135Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
3136
3137 * Makefile.in (SIM_OBJS): Add sim-load.o.
3138 * interp.c: #include bfd.h.
3139 (target_byte_order): Delete.
3140 (sim_kind, myname, big_endian_p): New static locals.
3141 (sim_open): Set sim_kind, myname. Move call to set_endianness to
3142 after argument parsing. Recognize -E arg, set endianness accordingly.
3143 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
3144 load file into simulator. Set PC from bfd.
3145 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
3146 (set_endianness): Use big_endian_p instead of target_byte_order.
3147
3148Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
3149
3150 * interp.c (sim_size): Delete prototype - conflicts with
3151 definition in remote-sim.h. Correct definition.
3152
3153Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3154
3155 * configure: Regenerated to track ../common/aclocal.m4 changes.
3156 * config.in: Ditto.
3157
3158Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
3159
3160 * interp.c (sim_open): New arg `kind'.
3161
3162 * configure: Regenerated to track ../common/aclocal.m4 changes.
3163
3164Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3165
3166 * configure: Regenerated to track ../common/aclocal.m4 changes.
3167
3168Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
3169
3170 * interp.c (sim_open): Set optind to 0 before calling getopt.
3171
3172Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3173
3174 * configure: Regenerated to track ../common/aclocal.m4 changes.
3175
3176Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
3177
3178 * interp.c : Replace uses of pr_addr with pr_uword64
3179 where the bit length is always 64 independent of SIM_ADDR.
3180 (pr_uword64) : added.
3181
3182Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3183
3184 * configure: Re-generate.
3185
3186Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
3187
3188 * configure: Regenerate to track ../common/aclocal.m4 changes.
3189
3190Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
3191
3192 * interp.c (sim_open): New SIM_DESC result. Argument is now
3193 in argv form.
3194 (other sim_*): New SIM_DESC argument.
3195
3196Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
3197
3198 * interp.c: Fix printing of addresses for non-64-bit targets.
3199 (pr_addr): Add function to print address based on size.
3200
3201Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
3202
3203 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
3204
3205Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
3206
3207 * gencode.c (build_mips16_operands): Correct computation of base
3208 address for extended PC relative instruction.
3209
3210Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
3211
3212 * interp.c (mips16_entry): Add support for floating point cases.
3213 (SignalException): Pass floating point cases to mips16_entry.
3214 (ValueFPR): Don't restrict fmt_single and fmt_word to even
3215 registers.
3216 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
3217 or fmt_word.
3218 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
3219 and then set the state to fmt_uninterpreted.
3220 (COP_SW): Temporarily set the state to fmt_word while calling
3221 ValueFPR.
3222
3223Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
3224
3225 * gencode.c (build_instruction): The high order may be set in the
3226 comparison flags at any ISA level, not just ISA 4.
3227
3228Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
3229
3230 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
3231 COMMON_{PRE,POST}_CONFIG_FRAG instead.
3232 * configure.in: sinclude ../common/aclocal.m4.
3233 * configure: Regenerated.
3234
3235Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
3236
3237 * configure: Rebuild after change to aclocal.m4.
3238
3239Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
3240
3241 * configure configure.in Makefile.in: Update to new configure
3242 scheme which is more compatible with WinGDB builds.
3243 * configure.in: Improve comment on how to run autoconf.
3244 * configure: Re-run autoconf to get new ../common/aclocal.m4.
3245 * Makefile.in: Use autoconf substitution to install common
3246 makefile fragment.
3247
3248Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
3249
3250 * gencode.c (build_instruction): Use BigEndianCPU instead of
3251 ByteSwapMem.
3252
3253Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
3254
3255 * interp.c (sim_monitor): Make output to stdout visible in
3256 wingdb's I/O log window.
3257
3258Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
3259
3260 * support.h: Undo previous change to SIGTRAP
3261 and SIGQUIT values.
3262
3263Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
3264
3265 * interp.c (store_word, load_word): New static functions.
3266 (mips16_entry): New static function.
3267 (SignalException): Look for mips16 entry and exit instructions.
3268 (simulate): Use the correct index when setting fpr_state after
3269 doing a pending move.
3270
3271Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
3272
3273 * interp.c: Fix byte-swapping code throughout to work on
3274 both little- and big-endian hosts.
3275
3276Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
3277
3278 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3279 with gdb/config/i386/xm-windows.h.
3280
3281Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
3282
3283 * gencode.c (build_instruction): Work around MSVC++ code gen bug
3284 that messes up arithmetic shifts.
3285
3286Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
3287
3288 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
3289 SIGTRAP and SIGQUIT for _WIN32.
3290
3291Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3292
3293 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3294 force a 64 bit multiplication.
3295 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3296 destination register is 0, since that is the default mips16 nop
3297 instruction.
3298
3299Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3300
3301 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3302 (build_endian_shift): Don't check proc64.
3303 (build_instruction): Always set memval to uword64. Cast op2 to
3304 uword64 when shifting it left in memory instructions. Always use
3305 the same code for stores--don't special case proc64.
3306
3307 * gencode.c (build_mips16_operands): Fix base PC value for PC
3308 relative operands.
3309 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3310 jal instruction.
3311 * interp.c (simJALDELAYSLOT): Define.
3312 (JALDELAYSLOT): Define.
3313 (INDELAYSLOT, INJALDELAYSLOT): Define.
3314 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3315
3316Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3317
3318 * interp.c (sim_open): add flush_cache as a PMON routine
3319 (sim_monitor): handle flush_cache by ignoring it
3320
3321Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3322
3323 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3324 BigEndianMem.
3325 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3326 (BigEndianMem): Rename to ByteSwapMem and change sense.
3327 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3328 BigEndianMem references to !ByteSwapMem.
3329 (set_endianness): New function, with prototype.
3330 (sim_open): Call set_endianness.
3331 (sim_info): Use simBE instead of BigEndianMem.
3332 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3333 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3334 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3335 ifdefs, keeping the prototype declaration.
3336 (swap_word): Rewrite correctly.
3337 (ColdReset): Delete references to CONFIG. Delete endianness related
3338 code; moved to set_endianness.
72f4393d 3339
c906108c
SS		 3340Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3341
3342 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3343 * interp.c (CHECKHILO): Define away.
3344 (simSIGINT): New macro.
3345 (membank_size): Increase from 1MB to 2MB.
3346 (control_c): New function.
3347 (sim_resume): Rename parameter signal to signal_number. Add local
3348 variable prev. Call signal before and after simulate.
3349 (sim_stop_reason): Add simSIGINT support.
3350 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3351 functions always.
3352 (sim_warning): Delete call to SignalException. Do call printf_filtered
3353 if logfh is NULL.
3354 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3355 a call to sim_warning.
3356
3357Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3358
3359 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3360 16 bit instructions.
3361
3362Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3363
3364 Add support for mips16 (16 bit MIPS implementation):
3365 * gencode.c (inst_type): Add mips16 instruction encoding types.
3366 (GETDATASIZEINSN): Define.
3367 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3368 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3369 mtlo.
3370 (MIPS16_DECODE): New table, for mips16 instructions.
3371 (bitmap_val): New static function.
3372 (struct mips16_op): Define.
3373 (mips16_op_table): New table, for mips16 operands.
3374 (build_mips16_operands): New static function.
3375 (process_instructions): If PC is odd, decode a mips16
3376 instruction. Break out instruction handling into new
3377 build_instruction function.
3378 (build_instruction): New static function, broken out of
3379 process_instructions. Check modifiers rather than flags for SHIFT
3380 bit count and m[ft]{hi,lo} direction.
3381 (usage): Pass program name to fprintf.
3382 (main): Remove unused variable this_option_optind. Change
3383 ``*loptarg++'' to ``loptarg++''.
3384 (my_strtoul): Parenthesize && within ||.
3385 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3386 (simulate): If PC is odd, fetch a 16 bit instruction, and
3387 increment PC by 2 rather than 4.
3388 * configure.in: Add case for mips16*-*-*.
3389 * configure: Rebuild.
3390
3391Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3392
3393 * interp.c: Allow -t to enable tracing in standalone simulator.
3394 Fix garbage output in trace file and error messages.
3395
3396Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3397
3398 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3399 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3400 * configure.in: Simplify using macros in ../common/aclocal.m4.
3401 * configure: Regenerated.
3402 * tconfig.in: New file.
3403
3404Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3405
3406 * interp.c: Fix bugs in 64-bit port.
3407 Use ansi function declarations for msvc compiler.
3408 Initialize and test file pointer in trace code.
3409 Prevent duplicate definition of LAST_EMED_REGNUM.
3410
3411Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3412
3413 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3414
3415Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3416
3417 * interp.c (SignalException): Check for explicit terminating
3418 breakpoint value.
3419 * gencode.c: Pass instruction value through SignalException()
3420 calls for Trap, Breakpoint and Syscall.
3421
3422Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3423
3424 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3425 only used on those hosts that provide it.
3426 * configure.in: Add sqrt() to list of functions to be checked for.
3427 * config.in: Re-generated.
3428 * configure: Re-generated.
3429
3430Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3431
3432 * gencode.c (process_instructions): Call build_endian_shift when
3433 expanding STORE RIGHT, to fix swr.
3434 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3435 clear the high bits.
3436 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3437 Fix float to int conversions to produce signed values.
3438
3439Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3440
3441 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3442 (process_instructions): Correct handling of nor instruction.
3443 Correct shift count for 32 bit shift instructions. Correct sign
3444 extension for arithmetic shifts to not shift the number of bits in
3445 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3446 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3447 Fix madd.
3448 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3449 It's OK to have a mult follow a mult. What's not OK is to have a
3450 mult follow an mfhi.
3451 (Convert): Comment out incorrect rounding code.
3452
3453Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3454
3455 * interp.c (sim_monitor): Improved monitor printf
3456 simulation. Tidied up simulator warnings, and added "--log" option
3457 for directing warning message output.
3458 * gencode.c: Use sim_warning() rather than WARNING macro.
3459
3460Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3461
3462 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3463 getopt1.o, rather than on gencode.c. Link objects together.
3464 Don't link against -liberty.
3465 (gencode.o, getopt.o, getopt1.o): New targets.
3466 * gencode.c: Include <ctype.h> and "ansidecl.h".
3467 (AND): Undefine after including "ansidecl.h".
3468 (ULONG_MAX): Define if not defined.
3469 (OP_*): Don't define macros; now defined in opcode/mips.h.
3470 (main): Call my_strtoul rather than strtoul.
3471 (my_strtoul): New static function.
3472
3473Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3474
3475 * gencode.c (process_instructions): Generate word64 and uword64
3476 instead of `long long' and `unsigned long long' data types.
3477 * interp.c: #include sysdep.h to get signals, and define default
3478 for SIGBUS.
3479 * (Convert): Work around for Visual-C++ compiler bug with type
3480 conversion.
3481 * support.h: Make things compile under Visual-C++ by using
3482 __int64 instead of `long long'. Change many refs to long long
3483 into word64/uword64 typedefs.
3484
3485Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3486
72f4393d
L		 3487 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3488 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3489 (docdir): Removed.
3490 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3491 (AC_PROG_INSTALL): Added.
c906108c 3492 (AC_PROG_CC): Moved to before configure.host call.
72f4393d
L		 3493 * configure: Rebuilt.
3494
c906108c
SS		 3495Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3496
3497 * configure.in: Define @SIMCONF@ depending on mips target.
3498 * configure: Rebuild.
3499 * Makefile.in (run): Add @SIMCONF@ to control simulator
3500 construction.
3501 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3502 * interp.c: Remove some debugging, provide more detailed error
3503 messages, update memory accesses to use LOADDRMASK.
72f4393d 3504
c906108c
SS		 3505Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3506
3507 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3508 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3509 stamp-h.
3510 * configure: Rebuild.
3511 * config.in: New file, generated by autoheader.
3512 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3513 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3514 HAVE_ANINT and HAVE_AINT, as appropriate.
3515 * Makefile.in (run): Use @LIBS@ rather than -lm.
3516 (interp.o): Depend upon config.h.
3517 (Makefile): Just rebuild Makefile.
3518 (clean): Remove stamp-h.
3519 (mostlyclean): Make the same as clean, not as distclean.
3520 (config.h, stamp-h): New targets.
3521
3522Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3523
3524 * interp.c (ColdReset): Fix boolean test. Make all simulator
3525 globals static.
3526
3527Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3528
3529 * interp.c (xfer_direct_word, xfer_direct_long,
3530 swap_direct_word, swap_direct_long, xfer_big_word,
3531 xfer_big_long, xfer_little_word, xfer_little_long,
3532 swap_word,swap_long): Added.
3533 * interp.c (ColdReset): Provide function indirection to
3534 host<->simulated_target transfer routines.
3535 * interp.c (sim_store_register, sim_fetch_register): Updated to
3536 make use of indirected transfer routines.
3537
3538Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3539
3540 * gencode.c (process_instructions): Ensure FP ABS instruction
3541 recognised.
3542 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3543 system call support.
3544
3545Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3546
3547 * interp.c (sim_do_command): Complain if callback structure not
3548 initialised.
3549
3550Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3551
3552 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3553 support for Sun hosts.
3554 * Makefile.in (gencode): Ensure the host compiler and libraries
3555 used for cross-hosted build.
3556
3557Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3558
3559 * interp.c, gencode.c: Some more (TODO) tidying.
3560
3561Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3562
3563 * gencode.c, interp.c: Replaced explicit long long references with
3564 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3565 * support.h (SET64LO, SET64HI): Macros added.
3566
3567Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3568
3569 * configure: Regenerate with autoconf 2.7.
3570
3571Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3572
3573 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3574 * support.h: Remove superfluous "1" from #if.
3575 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3576
3577Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3578
3579 * interp.c (StoreFPR): Control UndefinedResult() call on
3580 WARN_RESULT manifest.
3581
3582Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3583
3584 * gencode.c: Tidied instruction decoding, and added FP instruction
3585 support.
3586
3587 * interp.c: Added dineroIII, and BSD profiling support. Also
3588 run-time FP handling.
3589
3590Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3591
3592 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3593 gencode.c, interp.c, support.h: created.
GDB Binutils - Deliverables
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