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* autoconf correction
[deliverable/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
a3027dd7
FCE		 12000-03-02 Frank Ch. Eigler <fche@redhat.com>
2
3 * configure: Regenerated.
4
5Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
6
7 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
8 calls, conditional on the simulator being in verbose mode.
9
dfcd3bfb
JM		 10Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
11
12 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
13 cache don't get ReservedInstruction traps.
14
c2d11a7d
JM		 151999-11-29 Mark Salter <msalter@cygnus.com>
16
17 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
18 to clear status bits in sdisr register. This is how the hardware works.
19
20 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
21 being used by cygmon.
22
4ce44c66
JM		 231999-11-11 Andrew Haley <aph@cygnus.com>
24
25 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
26 instructions.
27
cff3e48b
JM		 28Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
29
30 * mips.igen (MULT): Correct previous mis-applied patch.
31
d4f3574e
SS		 32Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
33
34 * mips.igen (delayslot32): Handle sequence like
35 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
36 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
37 (MULT): Actually pass the third register...
38
391999-09-03 Mark Salter <msalter@cygnus.com>
40
41 * interp.c (sim_open): Added more memory aliases for additional
42 hardware being touched by cygmon on jmr3904 board.
43
44Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
45
46 * configure: Regenerated to track ../common/aclocal.m4 changes.
47
a0b3c4fd
JM		 48Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
49
50 * interp.c (sim_store_register): Handle case where client - GDB -
51 specifies that a 4 byte register is 8 bytes in size.
52 (sim_fetch_register): Ditto.
53
adf40b2e
JM		 541999-07-14 Frank Ch. Eigler <fche@cygnus.com>
55
56 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
57 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
58 (idt_monitor_base): Base address for IDT monitor traps.
59 (pmon_monitor_base): Ditto for PMON.
60 (lsipmon_monitor_base): Ditto for LSI PMON.
61 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
62 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
63 (sim_firmware_command): New function.
64 (mips_option_handler): Call it for OPTION_FIRMWARE.
65 (sim_open): Allocate memory for idt_monitor region. If "--board"
66 option was given, add no monitor by default. Add BREAK hooks only if
67 monitors are also there.
68
43e526b9
JM		 69Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
70
71 * interp.c (sim_monitor): Flush output before reading input.
72
73Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
74
75 * tconfig.in (SIM_HANDLES_LMA): Always define.
76
77Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
78
79 From Mark Salter <msalter@cygnus.com>:
80 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
81 (sim_open): Add setup for BSP board.
82
9846de1b
JM		 83Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
84
85 * mips.igen (MULT, MULTU): Add syntax for two operand version.
86 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
87 them as unimplemented.
88
cd0fc7c3
SS		 891999-05-08 Felix Lee <flee@cygnus.com>
90
91 * configure: Regenerated to track ../common/aclocal.m4 changes.
92
7a292a7a
SS		 931999-04-21 Frank Ch. Eigler <fche@cygnus.com>
94
95 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
96
97Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
98
99 * configure.in: Any mips64vr5*-*-* target should have
100 -DTARGET_ENABLE_FR=1.
101 (default_endian): Any mips64vr*el-*-* target should default to
102 LITTLE_ENDIAN.
103 * configure: Re-generate.
104
1051999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
106
107 * mips.igen (ldl): Extend from _16_, not 32.
108
109Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
110
111 * interp.c (sim_store_register): Force registers written to by GDB
112 into an un-interpreted state.
113
c906108c
SS		 1141999-02-05 Frank Ch. Eigler <fche@cygnus.com>
115
116 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
117 CPU, start periodic background I/O polls.
118 (tx3904sio_poll): New function: periodic I/O poller.
119
1201998-12-30 Frank Ch. Eigler <fche@cygnus.com>
121
122 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
123
124Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
125
126 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
127 case statement.
128
1291998-12-29 Frank Ch. Eigler <fche@cygnus.com>
130
131 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
132 (load_word): Call SIM_CORE_SIGNAL hook on error.
133 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
134 starting. For exception dispatching, pass PC instead of NULL_CIA.
135 (decode_coproc): Use COP0_BADVADDR to store faulting address.
136 * sim-main.h (COP0_BADVADDR): Define.
137 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
138 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
139 (_sim_cpu): Add exc_* fields to store register value snapshots.
140 * mips.igen (*): Replace memory-related SignalException* calls
141 with references to SIM_CORE_SIGNAL hook.
142
143 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
144 fix.
145 * sim-main.c (*): Minor warning cleanups.
146
1471998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
148
149 * m16.igen (DADDIU5): Correct type-o.
150
151Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
152
153 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
154 variables.
155
156Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
157
158 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
159 to include path.
160 (interp.o): Add dependency on itable.h
161 (oengine.c, gencode): Delete remaining references.
162 (BUILT_SRC_FROM_GEN): Clean up.
163
1641998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
165
166 * vr4run.c: New.
167 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
168 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
169 tmp-run-hack) : New.
170 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
171 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
172 Drop the "64" qualifier to get the HACK generator working.
173 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
174 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
175 qualifier to get the hack generator working.
176 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
177 (DSLL): Use do_dsll.
178 (DSLLV): Use do_dsllv.
179 (DSRA): Use do_dsra.
180 (DSRL): Use do_dsrl.
181 (DSRLV): Use do_dsrlv.
182 (BC1): Move *vr4100 to get the HACK generator working.
183 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
184 get the HACK generator working.
185 (MACC) Rename to get the HACK generator working.
186 (DMACC,MACCS,DMACCS): Add the 64.
187
1881998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
189
190 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
191 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
192
1931998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
194
195 * mips/interp.c (DEBUG): Cleanups.
196
1971998-12-10 Frank Ch. Eigler <fche@cygnus.com>
198
199 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
200 (tx3904sio_tickle): fflush after a stdout character output.
201
2021998-12-03 Frank Ch. Eigler <fche@cygnus.com>
203
204 * interp.c (sim_close): Uninstall modules.
205
206Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
207
208 * sim-main.h, interp.c (sim_monitor): Change to global
209 function.
210
211Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
212
213 * configure.in (vr4100): Only include vr4100 instructions in
214 simulator.
215 * configure: Re-generate.
216 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
217
218Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
219
220 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
221 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
222 true alternative.
223
224 * configure.in (sim_default_gen, sim_use_gen): Replace with
225 sim_gen.
226 (--enable-sim-igen): Delete config option. Always using IGEN.
227 * configure: Re-generate.
228
229 * Makefile.in (gencode): Kill, kill, kill.
230 * gencode.c: Ditto.
231
232Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
233
234 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
235 bit mips16 igen simulator.
236 * configure: Re-generate.
237
238 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
239 as part of vr4100 ISA.
240 * vr.igen: Mark all instructions as 64 bit only.
241
242Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
243
244 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
245 Pacify GCC.
246
247Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
248
249 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
250 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
251 * configure: Re-generate.
252
253 * m16.igen (BREAK): Define breakpoint instruction.
254 (JALX32): Mark instruction as mips16 and not r3900.
255 * mips.igen (C.cond.fmt): Fix typo in instruction format.
256
257 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
258
259Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
260
261 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
262 insn as a debug breakpoint.
263
264 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
265 pending.slot_size.
266 (PENDING_SCHED): Clean up trace statement.
267 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
268 (PENDING_FILL): Delay write by only one cycle.
269 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
270
271 * sim-main.c (pending_tick): Clean up trace statements. Add trace
272 of pending writes.
273 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
274 32 & 64.
275 (pending_tick): Move incrementing of index to FOR statement.
276 (pending_tick): Only update PENDING_OUT after a write has occured.
277
278 * configure.in: Add explicit mips-lsi-* target. Use gencode to
279 build simulator.
280 * configure: Re-generate.
281
282 * interp.c (sim_engine_run OLD): Delete explicit call to
283 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
284
285Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
286
287 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
288 interrupt level number to match changed SignalExceptionInterrupt
289 macro.
290
291Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
292
293 * interp.c: #include "itable.h" if WITH_IGEN.
294 (get_insn_name): New function.
295 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
296 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
297
298Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
299
300 * configure: Rebuilt to inhale new common/aclocal.m4.
301
302Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
303
304 * dv-tx3904sio.c: Include sim-assert.h.
305
306Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
307
308 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
309 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
310 Reorganize target-specific sim-hardware checks.
311 * configure: rebuilt.
312 * interp.c (sim_open): For tx39 target boards, set
313 OPERATING_ENVIRONMENT, add tx3904sio devices.
314 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
315 ROM executables. Install dv-sockser into sim-modules list.
316
317 * dv-tx3904irc.c: Compiler warning clean-up.
318 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
319 frequent hw-trace messages.
320
321Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
322
323 * vr.igen (MulAcc): Identify as a vr4100 specific function.
324
325Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
326
327 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
328
329 * vr.igen: New file.
330 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
331 * mips.igen: Define vr4100 model. Include vr.igen.
332Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
333
334 * mips.igen (check_mf_hilo): Correct check.
335
336Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
337
338 * sim-main.h (interrupt_event): Add prototype.
339
340 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
341 register_ptr, register_value.
342 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
343
344 * sim-main.h (tracefh): Make extern.
345
346Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
347
348 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
349 Reduce unnecessarily high timer event frequency.
350 * dv-tx3904cpu.c: Ditto for interrupt event.
351
352Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
353
354 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
355 to allay warnings.
356 (interrupt_event): Made non-static.
357
358 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
359 interchange of configuration values for external vs. internal
360 clock dividers.
361
362Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
363
364 * mips.igen (BREAK): Moved code to here for
365 simulator-reserved break instructions.
366 * gencode.c (build_instruction): Ditto.
367 * interp.c (signal_exception): Code moved from here. Non-
368 reserved instructions now use exception vector, rather
369 than halting sim.
370 * sim-main.h: Moved magic constants to here.
371
372Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
373
374 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
375 register upon non-zero interrupt event level, clear upon zero
376 event value.
377 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
378 by passing zero event value.
379 (*_io_{read,write}_buffer): Endianness fixes.
380 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
381 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
382
383 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
384 serial I/O and timer module at base address 0xFFFF0000.
385
386Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
387
388 * mips.igen (SWC1) : Correct the handling of ReverseEndian
389 and BigEndianCPU.
390
391Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
392
393 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
394 parts.
395 * configure: Update.
396
397Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
398
399 * dv-tx3904tmr.c: New file - implements tx3904 timer.
400 * dv-tx3904{irc,cpu}.c: Mild reformatting.
401 * configure.in: Include tx3904tmr in hw_device list.
402 * configure: Rebuilt.
403 * interp.c (sim_open): Instantiate three timer instances.
404 Fix address typo of tx3904irc instance.
405
406Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
407
408 * interp.c (signal_exception): SystemCall exception now uses
409 the exception vector.
410
411Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
412
413 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
414 to allay warnings.
415
416Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
417
418 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
419
420Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
421
422 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
423
424 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
425 sim-main.h. Declare a struct hw_descriptor instead of struct
426 hw_device_descriptor.
427
428Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
429
430 * mips.igen (do_store_left, do_load_left): Compute nr of left and
431 right bits and then re-align left hand bytes to correct byte
432 lanes. Fix incorrect computation in do_store_left when loading
433 bytes from second word.
434
435Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
436
437 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
438 * interp.c (sim_open): Only create a device tree when HW is
439 enabled.
440
441 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
442 * interp.c (signal_exception): Ditto.
443
444Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
445
446 * gencode.c: Mark BEGEZALL as LIKELY.
447
448Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
449
450 * sim-main.h (ALU32_END): Sign extend 32 bit results.
451 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
452
453Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
454
455 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
456 modules. Recognize TX39 target with "mips*tx39" pattern.
457 * configure: Rebuilt.
458 * sim-main.h (*): Added many macros defining bits in
459 TX39 control registers.
460 (SignalInterrupt): Send actual PC instead of NULL.
461 (SignalNMIReset): New exception type.
462 * interp.c (board): New variable for future use to identify
463 a particular board being simulated.
464 (mips_option_handler,mips_options): Added "--board" option.
465 (interrupt_event): Send actual PC.
466 (sim_open): Make memory layout conditional on board setting.
467 (signal_exception): Initial implementation of hardware interrupt
468 handling. Accept another break instruction variant for simulator
469 exit.
470 (decode_coproc): Implement RFE instruction for TX39.
471 (mips.igen): Decode RFE instruction as such.
472 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
473 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
474 bbegin to implement memory map.
475 * dv-tx3904cpu.c: New file.
476 * dv-tx3904irc.c: New file.
477
478Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
479
480 * mips.igen (check_mt_hilo): Create a separate r3900 version.
481
482Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
483
484 * tx.igen (madd,maddu): Replace calls to check_op_hilo
485 with calls to check_div_hilo.
486
487Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
488
489 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
490 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
491 Add special r3900 version of do_mult_hilo.
492 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
493 with calls to check_mult_hilo.
494 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
495 with calls to check_div_hilo.
496
497Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
498
499 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
500 Document a replacement.
501
502Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
503
504 * interp.c (sim_monitor): Make mon_printf work.
505
506Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
507
508 * sim-main.h (INSN_NAME): New arg `cpu'.
509
510Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
511
512 * configure: Regenerated to track ../common/aclocal.m4 changes.
513
514Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
515
516 * configure: Regenerated to track ../common/aclocal.m4 changes.
517 * config.in: Ditto.
518
519Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
520
521 * acconfig.h: New file.
522 * configure.in: Reverted change of Apr 24; use sinclude again.
523
524Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
525
526 * configure: Regenerated to track ../common/aclocal.m4 changes.
527 * config.in: Ditto.
528
529Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
530
531 * configure.in: Don't call sinclude.
532
533Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
534
535 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
536
537Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
538
539 * mips.igen (ERET): Implement.
540
541 * interp.c (decode_coproc): Return sign-extended EPC.
542
543 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
544
545 * interp.c (signal_exception): Do not ignore Trap.
546 (signal_exception): On TRAP, restart at exception address.
547 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
548 (signal_exception): Update.
549 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
550 so that TRAP instructions are caught.
551
552Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
553
554 * sim-main.h (struct hilo_access, struct hilo_history): Define,
555 contains HI/LO access history.
556 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
557 (HIACCESS, LOACCESS): Delete, replace with
558 (HIHISTORY, LOHISTORY): New macros.
559 (CHECKHILO): Delete all, moved to mips.igen
560
561 * gencode.c (build_instruction): Do not generate checks for
562 correct HI/LO register usage.
563
564 * interp.c (old_engine_run): Delete checks for correct HI/LO
565 register usage.
566
567 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
568 check_mf_cycles): New functions.
569 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
570 do_divu, domultx, do_mult, do_multu): Use.
571
572 * tx.igen ("madd", "maddu"): Use.
573
574Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
575
576 * mips.igen (DSRAV): Use function do_dsrav.
577 (SRAV): Use new function do_srav.
578
579 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
580 (B): Sign extend 11 bit immediate.
581 (EXT-B*): Shift 16 bit immediate left by 1.
582 (ADDIU*): Don't sign extend immediate value.
583
584Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
585
586 * m16run.c (sim_engine_run): Restore CIA after handling an event.
587
588 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
589 functions.
590
591 * mips.igen (delayslot32, nullify_next_insn): New functions.
592 (m16.igen): Always include.
593 (do_*): Add more tracing.
594
595 * m16.igen (delayslot16): Add NIA argument, could be called by a
596 32 bit MIPS16 instruction.
597
598 * interp.c (ifetch16): Move function from here.
599 * sim-main.c (ifetch16): To here.
600
601 * sim-main.c (ifetch16, ifetch32): Update to match current
602 implementations of LH, LW.
603 (signal_exception): Don't print out incorrect hex value of illegal
604 instruction.
605
606Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
607
608 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
609 instruction.
610
611 * m16.igen: Implement MIPS16 instructions.
612
613 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
614 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
615 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
616 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
617 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
618 bodies of corresponding code from 32 bit insn to these. Also used
619 by MIPS16 versions of functions.
620
621 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
622 (IMEM16): Drop NR argument from macro.
623
624Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
625
626 * Makefile.in (SIM_OBJS): Add sim-main.o.
627
628 * sim-main.h (address_translation, load_memory, store_memory,
629 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
630 as INLINE_SIM_MAIN.
631 (pr_addr, pr_uword64): Declare.
632 (sim-main.c): Include when H_REVEALS_MODULE_P.
633
634 * interp.c (address_translation, load_memory, store_memory,
635 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
636 from here.
637 * sim-main.c: To here. Fix compilation problems.
638
639 * configure.in: Enable inlining.
640 * configure: Re-config.
641
642Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
643
644 * configure: Regenerated to track ../common/aclocal.m4 changes.
645
646Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
647
648 * mips.igen: Include tx.igen.
649 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
650 * tx.igen: New file, contains MADD and MADDU.
651
652 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
653 the hardwired constant `7'.
654 (store_memory): Ditto.
655 (LOADDRMASK): Move definition to sim-main.h.
656
657 mips.igen (MTC0): Enable for r3900.
658 (ADDU): Add trace.
659
660 mips.igen (do_load_byte): Delete.
661 (do_load, do_store, do_load_left, do_load_write, do_store_left,
662 do_store_right): New functions.
663 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
664
665 configure.in: Let the tx39 use igen again.
666 configure: Update.
667
668Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
669
670 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
671 not an address sized quantity. Return zero for cache sizes.
672
673Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
674
675 * mips.igen (r3900): r3900 does not support 64 bit integer
676 operations.
677
678Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
679
680 * configure.in (mipstx39*-*-*): Use gencode simulator rather
681 than igen one.
682 * configure : Rebuild.
683
684Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
685
686 * configure: Regenerated to track ../common/aclocal.m4 changes.
687
688Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
689
690 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
691
692Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
693
694 * configure: Regenerated to track ../common/aclocal.m4 changes.
695 * config.in: Regenerated to track ../common/aclocal.m4 changes.
696
697Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
698
699 * configure: Regenerated to track ../common/aclocal.m4 changes.
700
701Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
702
703 * interp.c (Max, Min): Comment out functions. Not yet used.
704
705Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
706
707 * configure: Regenerated to track ../common/aclocal.m4 changes.
708
709Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
710
711 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
712 configurable settings for stand-alone simulator.
713
714 * configure.in: Added X11 search, just in case.
715
716 * configure: Regenerated.
717
718Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
719
720 * interp.c (sim_write, sim_read, load_memory, store_memory):
721 Replace sim_core_*_map with read_map, write_map, exec_map resp.
722
723Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
724
725 * sim-main.h (GETFCC): Return an unsigned value.
726
727Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
728
729 * mips.igen (DIV): Fix check for -1 / MIN_INT.
730 (DADD): Result destination is RD not RT.
731
732Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
733
734 * sim-main.h (HIACCESS, LOACCESS): Always define.
735
736 * mdmx.igen (Maxi, Mini): Rename Max, Min.
737
738 * interp.c (sim_info): Delete.
739
740Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
741
742 * interp.c (DECLARE_OPTION_HANDLER): Use it.
743 (mips_option_handler): New argument `cpu'.
744 (sim_open): Update call to sim_add_option_table.
745
746Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
747
748 * mips.igen (CxC1): Add tracing.
749
750Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
751
752 * sim-main.h (Max, Min): Declare.
753
754 * interp.c (Max, Min): New functions.
755
756 * mips.igen (BC1): Add tracing.
757
758Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
759
760 * interp.c Added memory map for stack in vr4100
761
762Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
763
764 * interp.c (load_memory): Add missing "break"'s.
765
766Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
767
768 * interp.c (sim_store_register, sim_fetch_register): Pass in
769 length parameter. Return -1.
770
771Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
772
773 * interp.c: Added hardware init hook, fixed warnings.
774
775Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
776
777 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
778
779Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
780
781 * interp.c (ifetch16): New function.
782
783 * sim-main.h (IMEM32): Rename IMEM.
784 (IMEM16_IMMED): Define.
785 (IMEM16): Define.
786 (DELAY_SLOT): Update.
787
788 * m16run.c (sim_engine_run): New file.
789
790 * m16.igen: All instructions except LB.
791 (LB): Call do_load_byte.
792 * mips.igen (do_load_byte): New function.
793 (LB): Call do_load_byte.
794
795 * mips.igen: Move spec for insn bit size and high bit from here.
796 * Makefile.in (tmp-igen, tmp-m16): To here.
797
798 * m16.dc: New file, decode mips16 instructions.
799
800 * Makefile.in (SIM_NO_ALL): Define.
801 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
802
803Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
804
805 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
806 point unit to 32 bit registers.
807 * configure: Re-generate.
808
809Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
810
811 * configure.in (sim_use_gen): Make IGEN the default simulator
812 generator for generic 32 and 64 bit mips targets.
813 * configure: Re-generate.
814
815Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
816
817 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
818 bitsize.
819
820 * interp.c (sim_fetch_register, sim_store_register): Read/write
821 FGR from correct location.
822 (sim_open): Set size of FGR's according to
823 WITH_TARGET_FLOATING_POINT_BITSIZE.
824
825 * sim-main.h (FGR): Store floating point registers in a separate
826 array.
827
828Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
829
830 * configure: Regenerated to track ../common/aclocal.m4 changes.
831
832Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
833
834 * interp.c (ColdReset): Call PENDING_INVALIDATE.
835
836 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
837
838 * interp.c (pending_tick): New function. Deliver pending writes.
839
840 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
841 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
842 it can handle mixed sized quantites and single bits.
843
844Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
845
846 * interp.c (oengine.h): Do not include when building with IGEN.
847 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
848 (sim_info): Ditto for PROCESSOR_64BIT.
849 (sim_monitor): Replace ut_reg with unsigned_word.
850 (*): Ditto for t_reg.
851 (LOADDRMASK): Define.
852 (sim_open): Remove defunct check that host FP is IEEE compliant,
853 using software to emulate floating point.
854 (value_fpr, ...): Always compile, was conditional on HASFPU.
855
856Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
857
858 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
859 size.
860
861 * interp.c (SD, CPU): Define.
862 (mips_option_handler): Set flags in each CPU.
863 (interrupt_event): Assume CPU 0 is the one being iterrupted.
864 (sim_close): Do not clear STATE, deleted anyway.
865 (sim_write, sim_read): Assume CPU zero's vm should be used for
866 data transfers.
867 (sim_create_inferior): Set the PC for all processors.
868 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
869 argument.
870 (mips16_entry): Pass correct nr of args to store_word, load_word.
871 (ColdReset): Cold reset all cpu's.
872 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
873 (sim_monitor, load_memory, store_memory, signal_exception): Use
874 `CPU' instead of STATE_CPU.
875
876
877 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
878 SD or CPU_.
879
880 * sim-main.h (signal_exception): Add sim_cpu arg.
881 (SignalException*): Pass both SD and CPU to signal_exception.
882 * interp.c (signal_exception): Update.
883
884 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
885 Ditto
886 (sync_operation, prefetch, cache_op, store_memory, load_memory,
887 address_translation): Ditto
888 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
889
890Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
891
892 * configure: Regenerated to track ../common/aclocal.m4 changes.
893
894Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
895
896 * interp.c (sim_engine_run): Add `nr_cpus' argument.
897
898 * mips.igen (model): Map processor names onto BFD name.
899
900 * sim-main.h (CPU_CIA): Delete.
901 (SET_CIA, GET_CIA): Define
902
903Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
904
905 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
906 regiser.
907
908 * configure.in (default_endian): Configure a big-endian simulator
909 by default.
910 * configure: Re-generate.
911
912Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
913
914 * configure: Regenerated to track ../common/aclocal.m4 changes.
915
916Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
917
918 * interp.c (sim_monitor): Handle Densan monitor outbyte
919 and inbyte functions.
920
9211997-12-29 Felix Lee <flee@cygnus.com>
922
923 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
924
925Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
926
927 * Makefile.in (tmp-igen): Arrange for $zero to always be
928 reset to zero after every instruction.
929
930Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
931
932 * configure: Regenerated to track ../common/aclocal.m4 changes.
933 * config.in: Ditto.
934
935Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
936
937 * mips.igen (MSUB): Fix to work like MADD.
938 * gencode.c (MSUB): Similarly.
939
940Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
941
942 * configure: Regenerated to track ../common/aclocal.m4 changes.
943
944Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
945
946 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
947
948Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
949
950 * sim-main.h (sim-fpu.h): Include.
951
952 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
953 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
954 using host independant sim_fpu module.
955
956Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
957
958 * interp.c (signal_exception): Report internal errors with SIGABRT
959 not SIGQUIT.
960
961 * sim-main.h (C0_CONFIG): New register.
962 (signal.h): No longer include.
963
964 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
965
966Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
967
968 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
969
970Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
971
972 * mips.igen: Tag vr5000 instructions.
973 (ANDI): Was missing mipsIV model, fix assembler syntax.
974 (do_c_cond_fmt): New function.
975 (C.cond.fmt): Handle mips I-III which do not support CC field
976 separatly.
977 (bc1): Handle mips IV which do not have a delaed FCC separatly.
978 (SDR): Mask paddr when BigEndianMem, not the converse as specified
979 in IV3.2 spec.
980 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
981 vr5000 which saves LO in a GPR separatly.
982
983 * configure.in (enable-sim-igen): For vr5000, select vr5000
984 specific instructions.
985 * configure: Re-generate.
986
987Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
988
989 * Makefile.in (SIM_OBJS): Add sim-fpu module.
990
991 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
992 fmt_uninterpreted_64 bit cases to switch. Convert to
993 fmt_formatted,
994
995 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
996
997 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
998 as specified in IV3.2 spec.
999 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1000
1001Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1002
1003 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1004 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1005 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1006 PENDING_FILL versions of instructions. Simplify.
1007 (X): New function.
1008 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1009 instructions.
1010 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1011 a signed value.
1012 (MTHI, MFHI): Disable code checking HI-LO.
1013
1014 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1015 global.
1016 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1017
1018Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1019
1020 * gencode.c (build_mips16_operands): Replace IPC with cia.
1021
1022 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1023 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1024 IPC to `cia'.
1025 (UndefinedResult): Replace function with macro/function
1026 combination.
1027 (sim_engine_run): Don't save PC in IPC.
1028
1029 * sim-main.h (IPC): Delete.
1030
1031
1032 * interp.c (signal_exception, store_word, load_word,
1033 address_translation, load_memory, store_memory, cache_op,
1034 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1035 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1036 current instruction address - cia - argument.
1037 (sim_read, sim_write): Call address_translation directly.
1038 (sim_engine_run): Rename variable vaddr to cia.
1039 (signal_exception): Pass cia to sim_monitor
1040
1041 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1042 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1043 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1044
1045 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1046 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1047 SIM_ASSERT.
1048
1049 * interp.c (signal_exception): Pass restart address to
1050 sim_engine_restart.
1051
1052 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1053 idecode.o): Add dependency.
1054
1055 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1056 Delete definitions
1057 (DELAY_SLOT): Update NIA not PC with branch address.
1058 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1059
1060 * mips.igen: Use CIA not PC in branch calculations.
1061 (illegal): Call SignalException.
1062 (BEQ, ADDIU): Fix assembler.
1063
1064Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1065
1066 * m16.igen (JALX): Was missing.
1067
1068 * configure.in (enable-sim-igen): New configuration option.
1069 * configure: Re-generate.
1070
1071 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1072
1073 * interp.c (load_memory, store_memory): Delete parameter RAW.
1074 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1075 bypassing {load,store}_memory.
1076
1077 * sim-main.h (ByteSwapMem): Delete definition.
1078
1079 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1080
1081 * interp.c (sim_do_command, sim_commands): Delete mips specific
1082 commands. Handled by module sim-options.
1083
1084 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1085 (WITH_MODULO_MEMORY): Define.
1086
1087 * interp.c (sim_info): Delete code printing memory size.
1088
1089 * interp.c (mips_size): Nee sim_size, delete function.
1090 (power2): Delete.
1091 (monitor, monitor_base, monitor_size): Delete global variables.
1092 (sim_open, sim_close): Delete code creating monitor and other
1093 memory regions. Use sim-memopts module, via sim_do_commandf, to
1094 manage memory regions.
1095 (load_memory, store_memory): Use sim-core for memory model.
1096
1097 * interp.c (address_translation): Delete all memory map code
1098 except line forcing 32 bit addresses.
1099
1100Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1101
1102 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1103 trace options.
1104
1105 * interp.c (logfh, logfile): Delete globals.
1106 (sim_open, sim_close): Delete code opening & closing log file.
1107 (mips_option_handler): Delete -l and -n options.
1108 (OPTION mips_options): Ditto.
1109
1110 * interp.c (OPTION mips_options): Rename option trace to dinero.
1111 (mips_option_handler): Update.
1112
1113Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1114
1115 * interp.c (fetch_str): New function.
1116 (sim_monitor): Rewrite using sim_read & sim_write.
1117 (sim_open): Check magic number.
1118 (sim_open): Write monitor vectors into memory using sim_write.
1119 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1120 (sim_read, sim_write): Simplify - transfer data one byte at a
1121 time.
1122 (load_memory, store_memory): Clarify meaning of parameter RAW.
1123
1124 * sim-main.h (isHOST): Defete definition.
1125 (isTARGET): Mark as depreciated.
1126 (address_translation): Delete parameter HOST.
1127
1128 * interp.c (address_translation): Delete parameter HOST.
1129
1130Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1131
1132 * mips.igen:
1133
1134 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1135 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1136
1137Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1138
1139 * mips.igen: Add model filter field to records.
1140
1141Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1142
1143 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1144
1145 interp.c (sim_engine_run): Do not compile function sim_engine_run
1146 when WITH_IGEN == 1.
1147
1148 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1149 target architecture.
1150
1151 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1152 igen. Replace with configuration variables sim_igen_flags /
1153 sim_m16_flags.
1154
1155 * m16.igen: New file. Copy mips16 insns here.
1156 * mips.igen: From here.
1157
1158Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1159
1160 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1161 to top.
1162 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1163
1164Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1165
1166 * gencode.c (build_instruction): Follow sim_write's lead in using
1167 BigEndianMem instead of !ByteSwapMem.
1168
1169Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1170
1171 * configure.in (sim_gen): Dependent on target, select type of
1172 generator. Always select old style generator.
1173
1174 configure: Re-generate.
1175
1176 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1177 targets.
1178 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1179 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1180 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1181 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1182 SIM_@sim_gen@_*, set by autoconf.
1183
1184Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1185
1186 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1187
1188 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1189 CURRENT_FLOATING_POINT instead.
1190
1191 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1192 (address_translation): Raise exception InstructionFetch when
1193 translation fails and isINSTRUCTION.
1194
1195 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1196 sim_engine_run): Change type of of vaddr and paddr to
1197 address_word.
1198 (address_translation, prefetch, load_memory, store_memory,
1199 cache_op): Change type of vAddr and pAddr to address_word.
1200
1201 * gencode.c (build_instruction): Change type of vaddr and paddr to
1202 address_word.
1203
1204Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1205
1206 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1207 macro to obtain result of ALU op.
1208
1209Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1210
1211 * interp.c (sim_info): Call profile_print.
1212
1213Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1214
1215 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1216
1217 * sim-main.h (WITH_PROFILE): Do not define, defined in
1218 common/sim-config.h. Use sim-profile module.
1219 (simPROFILE): Delete defintion.
1220
1221 * interp.c (PROFILE): Delete definition.
1222 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1223 (sim_close): Delete code writing profile histogram.
1224 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1225 Delete.
1226 (sim_engine_run): Delete code profiling the PC.
1227
1228Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1229
1230 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1231
1232 * interp.c (sim_monitor): Make register pointers of type
1233 unsigned_word*.
1234
1235 * sim-main.h: Make registers of type unsigned_word not
1236 signed_word.
1237
1238Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1239
1240 * interp.c (sync_operation): Rename from SyncOperation, make
1241 global, add SD argument.
1242 (prefetch): Rename from Prefetch, make global, add SD argument.
1243 (decode_coproc): Make global.
1244
1245 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1246
1247 * gencode.c (build_instruction): Generate DecodeCoproc not
1248 decode_coproc calls.
1249
1250 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1251 (SizeFGR): Move to sim-main.h
1252 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1253 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1254 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1255 sim-main.h.
1256 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1257 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1258 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1259 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1260 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1261 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1262
1263 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1264 exception.
1265 (sim-alu.h): Include.
1266 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1267 (sim_cia): Typedef to instruction_address.
1268
1269Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1270
1271 * Makefile.in (interp.o): Rename generated file engine.c to
1272 oengine.c.
1273
1274 * interp.c: Update.
1275
1276Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1277
1278 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1279
1280Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1281
1282 * gencode.c (build_instruction): For "FPSQRT", output correct
1283 number of arguments to Recip.
1284
1285Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1286
1287 * Makefile.in (interp.o): Depends on sim-main.h
1288
1289 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1290
1291 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1292 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1293 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1294 STATE, DSSTATE): Define
1295 (GPR, FGRIDX, ..): Define.
1296
1297 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1298 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1299 (GPR, FGRIDX, ...): Delete macros.
1300
1301 * interp.c: Update names to match defines from sim-main.h
1302
1303Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1304
1305 * interp.c (sim_monitor): Add SD argument.
1306 (sim_warning): Delete. Replace calls with calls to
1307 sim_io_eprintf.
1308 (sim_error): Delete. Replace calls with sim_io_error.
1309 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1310 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1311 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1312 argument.
1313 (mips_size): Rename from sim_size. Add SD argument.
1314
1315 * interp.c (simulator): Delete global variable.
1316 (callback): Delete global variable.
1317 (mips_option_handler, sim_open, sim_write, sim_read,
1318 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1319 sim_size,sim_monitor): Use sim_io_* not callback->*.
1320 (sim_open): ZALLOC simulator struct.
1321 (PROFILE): Do not define.
1322
1323Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1324
1325 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1326 support.h with corresponding code.
1327
1328 * sim-main.h (word64, uword64), support.h: Move definition to
1329 sim-main.h.
1330 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1331
1332 * support.h: Delete
1333 * Makefile.in: Update dependencies
1334 * interp.c: Do not include.
1335
1336Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1337
1338 * interp.c (address_translation, load_memory, store_memory,
1339 cache_op): Rename to from AddressTranslation et.al., make global,
1340 add SD argument
1341
1342 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1343 CacheOp): Define.
1344
1345 * interp.c (SignalException): Rename to signal_exception, make
1346 global.
1347
1348 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1349
1350 * sim-main.h (SignalException, SignalExceptionInterrupt,
1351 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1352 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1353 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1354 Define.
1355
1356 * interp.c, support.h: Use.
1357
1358Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1359
1360 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1361 to value_fpr / store_fpr. Add SD argument.
1362 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1363 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1364
1365 * sim-main.h (ValueFPR, StoreFPR): Define.
1366
1367Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1368
1369 * interp.c (sim_engine_run): Check consistency between configure
1370 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1371 and HASFPU.
1372
1373 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1374 (mips_fpu): Configure WITH_FLOATING_POINT.
1375 (mips_endian): Configure WITH_TARGET_ENDIAN.
1376 * configure: Update.
1377
1378Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1379
1380 * configure: Regenerated to track ../common/aclocal.m4 changes.
1381
1382Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1383
1384 * configure: Regenerated.
1385
1386Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1387
1388 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1389
1390Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1391
1392 * gencode.c (print_igen_insn_models): Assume certain architectures
1393 include all mips* instructions.
1394 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1395 instruction.
1396
1397 * Makefile.in (tmp.igen): Add target. Generate igen input from
1398 gencode file.
1399
1400 * gencode.c (FEATURE_IGEN): Define.
1401 (main): Add --igen option. Generate output in igen format.
1402 (process_instructions): Format output according to igen option.
1403 (print_igen_insn_format): New function.
1404 (print_igen_insn_models): New function.
1405 (process_instructions): Only issue warnings and ignore
1406 instructions when no FEATURE_IGEN.
1407
1408Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1409
1410 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1411 MIPS targets.
1412
1413Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1414
1415 * configure: Regenerated to track ../common/aclocal.m4 changes.
1416
1417Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1418
1419 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1420 SIM_RESERVED_BITS): Delete, moved to common.
1421 (SIM_EXTRA_CFLAGS): Update.
1422
1423Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1424
1425 * configure.in: Configure non-strict memory alignment.
1426 * configure: Regenerated to track ../common/aclocal.m4 changes.
1427
1428Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1429
1430 * configure: Regenerated to track ../common/aclocal.m4 changes.
1431
1432Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1433
1434 * gencode.c (SDBBP,DERET): Added (3900) insns.
1435 (RFE): Turn on for 3900.
1436 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1437 (dsstate): Made global.
1438 (SUBTARGET_R3900): Added.
1439 (CANCELDELAYSLOT): New.
1440 (SignalException): Ignore SystemCall rather than ignore and
1441 terminate. Add DebugBreakPoint handling.
1442 (decode_coproc): New insns RFE, DERET; and new registers Debug
1443 and DEPC protected by SUBTARGET_R3900.
1444 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1445 bits explicitly.
1446 * Makefile.in,configure.in: Add mips subtarget option.
1447 * configure: Update.
1448
1449Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1450
1451 * gencode.c: Add r3900 (tx39).
1452
1453
1454Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1455
1456 * gencode.c (build_instruction): Don't need to subtract 4 for
1457 JALR, just 2.
1458
1459Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1460
1461 * interp.c: Correct some HASFPU problems.
1462
1463Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1464
1465 * configure: Regenerated to track ../common/aclocal.m4 changes.
1466
1467Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1468
1469 * interp.c (mips_options): Fix samples option short form, should
1470 be `x'.
1471
1472Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1473
1474 * interp.c (sim_info): Enable info code. Was just returning.
1475
1476Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1477
1478 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1479 MFC0.
1480
1481Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1482
1483 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1484 constants.
1485 (build_instruction): Ditto for LL.
1486
1487Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1488
1489 * configure: Regenerated to track ../common/aclocal.m4 changes.
1490
1491Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1492
1493 * configure: Regenerated to track ../common/aclocal.m4 changes.
1494 * config.in: Ditto.
1495
1496Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1497
1498 * interp.c (sim_open): Add call to sim_analyze_program, update
1499 call to sim_config.
1500
1501Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1502
1503 * interp.c (sim_kill): Delete.
1504 (sim_create_inferior): Add ABFD argument. Set PC from same.
1505 (sim_load): Move code initializing trap handlers from here.
1506 (sim_open): To here.
1507 (sim_load): Delete, use sim-hload.c.
1508
1509 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1510
1511Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1512
1513 * configure: Regenerated to track ../common/aclocal.m4 changes.
1514 * config.in: Ditto.
1515
1516Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1517
1518 * interp.c (sim_open): Add ABFD argument.
1519 (sim_load): Move call to sim_config from here.
1520 (sim_open): To here. Check return status.
1521
1522Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1523
1524 * gencode.c (build_instruction): Two arg MADD should
1525 not assign result to $0.
1526
1527Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1528
1529 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1530 * sim/mips/configure.in: Regenerate.
1531
1532Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1533
1534 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1535 signed8, unsigned8 et.al. types.
1536
1537 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1538 hosts when selecting subreg.
1539
1540Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1541
1542 * interp.c (sim_engine_run): Reset the ZERO register to zero
1543 regardless of FEATURE_WARN_ZERO.
1544 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1545
1546Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1547
1548 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1549 (SignalException): For BreakPoints ignore any mode bits and just
1550 save the PC.
1551 (SignalException): Always set the CAUSE register.
1552
1553Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1554
1555 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1556 exception has been taken.
1557
1558 * interp.c: Implement the ERET and mt/f sr instructions.
1559
1560Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1561
1562 * interp.c (SignalException): Don't bother restarting an
1563 interrupt.
1564
1565Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1566
1567 * interp.c (SignalException): Really take an interrupt.
1568 (interrupt_event): Only deliver interrupts when enabled.
1569
1570Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1571
1572 * interp.c (sim_info): Only print info when verbose.
1573 (sim_info) Use sim_io_printf for output.
1574
1575Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1576
1577 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1578 mips architectures.
1579
1580Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1581
1582 * interp.c (sim_do_command): Check for common commands if a
1583 simulator specific command fails.
1584
1585Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
1586
1587 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1588 and simBE when DEBUG is defined.
1589
1590Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
1591
1592 * interp.c (interrupt_event): New function. Pass exception event
1593 onto exception handler.
1594
1595 * configure.in: Check for stdlib.h.
1596 * configure: Regenerate.
1597
1598 * gencode.c (build_instruction): Add UNUSED attribute to tempS
1599 variable declaration.
1600 (build_instruction): Initialize memval1.
1601 (build_instruction): Add UNUSED attribute to byte, bigend,
1602 reverse.
1603 (build_operands): Ditto.
1604
1605 * interp.c: Fix GCC warnings.
1606 (sim_get_quit_code): Delete.
1607
1608 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1609 * Makefile.in: Ditto.
1610 * configure: Re-generate.
1611
1612 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1613
1614Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1615
1616 * interp.c (mips_option_handler): New function parse argumes using
1617 sim-options.
1618 (myname): Replace with STATE_MY_NAME.
1619 (sim_open): Delete check for host endianness - performed by
1620 sim_config.
1621 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1622 (sim_open): Move much of the initialization from here.
1623 (sim_load): To here. After the image has been loaded and
1624 endianness set.
1625 (sim_open): Move ColdReset from here.
1626 (sim_create_inferior): To here.
1627 (sim_open): Make FP check less dependant on host endianness.
1628
1629 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1630 run.
1631 * interp.c (sim_set_callbacks): Delete.
1632
1633 * interp.c (membank, membank_base, membank_size): Replace with
1634 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1635 (sim_open): Remove call to callback->init. gdb/run do this.
1636
1637 * interp.c: Update
1638
1639 * sim-main.h (SIM_HAVE_FLATMEM): Define.
1640
1641 * interp.c (big_endian_p): Delete, replaced by
1642 current_target_byte_order.
1643
1644Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1645
1646 * interp.c (host_read_long, host_read_word, host_swap_word,
1647 host_swap_long): Delete. Using common sim-endian.
1648 (sim_fetch_register, sim_store_register): Use H2T.
1649 (pipeline_ticks): Delete. Handled by sim-events.
1650 (sim_info): Update.
1651 (sim_engine_run): Update.
1652
1653Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
1654
1655 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1656 reason from here.
1657 (SignalException): To here. Signal using sim_engine_halt.
1658 (sim_stop_reason): Delete, moved to common.
1659
1660Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
1661
1662 * interp.c (sim_open): Add callback argument.
1663 (sim_set_callbacks): Delete SIM_DESC argument.
1664 (sim_size): Ditto.
1665
1666Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1667
1668 * Makefile.in (SIM_OBJS): Add common modules.
1669
1670 * interp.c (sim_set_callbacks): Also set SD callback.
1671 (set_endianness, xfer_*, swap_*): Delete.
1672 (host_read_word, host_read_long, host_swap_word, host_swap_long):
1673 Change to functions using sim-endian macros.
1674 (control_c, sim_stop): Delete, use common version.
1675 (simulate): Convert into.
1676 (sim_engine_run): This function.
1677 (sim_resume): Delete.
1678
1679 * interp.c (simulation): New variable - the simulator object.
1680 (sim_kind): Delete global - merged into simulation.
1681 (sim_load): Cleanup. Move PC assignment from here.
1682 (sim_create_inferior): To here.
1683
1684 * sim-main.h: New file.
1685 * interp.c (sim-main.h): Include.
1686
1687Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
1688
1689 * configure: Regenerated to track ../common/aclocal.m4 changes.
1690
1691Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
1692
1693 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
1694
1695Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
1696
1697 * gencode.c (build_instruction): DIV instructions: check
1698 for division by zero and integer overflow before using
1699 host's division operation.
1700
1701Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
1702
1703 * Makefile.in (SIM_OBJS): Add sim-load.o.
1704 * interp.c: #include bfd.h.
1705 (target_byte_order): Delete.
1706 (sim_kind, myname, big_endian_p): New static locals.
1707 (sim_open): Set sim_kind, myname. Move call to set_endianness to
1708 after argument parsing. Recognize -E arg, set endianness accordingly.
1709 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
1710 load file into simulator. Set PC from bfd.
1711 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
1712 (set_endianness): Use big_endian_p instead of target_byte_order.
1713
1714Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
1715
1716 * interp.c (sim_size): Delete prototype - conflicts with
1717 definition in remote-sim.h. Correct definition.
1718
1719Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1720
1721 * configure: Regenerated to track ../common/aclocal.m4 changes.
1722 * config.in: Ditto.
1723
1724Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
1725
1726 * interp.c (sim_open): New arg `kind'.
1727
1728 * configure: Regenerated to track ../common/aclocal.m4 changes.
1729
1730Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1731
1732 * configure: Regenerated to track ../common/aclocal.m4 changes.
1733
1734Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
1735
1736 * interp.c (sim_open): Set optind to 0 before calling getopt.
1737
1738Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1739
1740 * configure: Regenerated to track ../common/aclocal.m4 changes.
1741
1742Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
1743
1744 * interp.c : Replace uses of pr_addr with pr_uword64
1745 where the bit length is always 64 independent of SIM_ADDR.
1746 (pr_uword64) : added.
1747
1748Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1749
1750 * configure: Re-generate.
1751
1752Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
1753
1754 * configure: Regenerate to track ../common/aclocal.m4 changes.
1755
1756Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
1757
1758 * interp.c (sim_open): New SIM_DESC result. Argument is now
1759 in argv form.
1760 (other sim_*): New SIM_DESC argument.
1761
1762Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
1763
1764 * interp.c: Fix printing of addresses for non-64-bit targets.
1765 (pr_addr): Add function to print address based on size.
1766
1767Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
1768
1769 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
1770
1771Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
1772
1773 * gencode.c (build_mips16_operands): Correct computation of base
1774 address for extended PC relative instruction.
1775
1776Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
1777
1778 * interp.c (mips16_entry): Add support for floating point cases.
1779 (SignalException): Pass floating point cases to mips16_entry.
1780 (ValueFPR): Don't restrict fmt_single and fmt_word to even
1781 registers.
1782 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
1783 or fmt_word.
1784 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
1785 and then set the state to fmt_uninterpreted.
1786 (COP_SW): Temporarily set the state to fmt_word while calling
1787 ValueFPR.
1788
1789Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
1790
1791 * gencode.c (build_instruction): The high order may be set in the
1792 comparison flags at any ISA level, not just ISA 4.
1793
1794Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
1795
1796 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
1797 COMMON_{PRE,POST}_CONFIG_FRAG instead.
1798 * configure.in: sinclude ../common/aclocal.m4.
1799 * configure: Regenerated.
1800
1801Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
1802
1803 * configure: Rebuild after change to aclocal.m4.
1804
1805Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
1806
1807 * configure configure.in Makefile.in: Update to new configure
1808 scheme which is more compatible with WinGDB builds.
1809 * configure.in: Improve comment on how to run autoconf.
1810 * configure: Re-run autoconf to get new ../common/aclocal.m4.
1811 * Makefile.in: Use autoconf substitution to install common
1812 makefile fragment.
1813
1814Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
1815
1816 * gencode.c (build_instruction): Use BigEndianCPU instead of
1817 ByteSwapMem.
1818
1819Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
1820
1821 * interp.c (sim_monitor): Make output to stdout visible in
1822 wingdb's I/O log window.
1823
1824Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
1825
1826 * support.h: Undo previous change to SIGTRAP
1827 and SIGQUIT values.
1828
1829Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
1830
1831 * interp.c (store_word, load_word): New static functions.
1832 (mips16_entry): New static function.
1833 (SignalException): Look for mips16 entry and exit instructions.
1834 (simulate): Use the correct index when setting fpr_state after
1835 doing a pending move.
1836
1837Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
1838
1839 * interp.c: Fix byte-swapping code throughout to work on
1840 both little- and big-endian hosts.
1841
1842Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
1843
1844 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
1845 with gdb/config/i386/xm-windows.h.
1846
1847Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
1848
1849 * gencode.c (build_instruction): Work around MSVC++ code gen bug
1850 that messes up arithmetic shifts.
1851
1852Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
1853
1854 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
1855 SIGTRAP and SIGQUIT for _WIN32.
1856
1857Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
1858
1859 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
1860 force a 64 bit multiplication.
1861 (build_instruction) [OR]: In mips16 mode, don't do anything if the
1862 destination register is 0, since that is the default mips16 nop
1863 instruction.
1864
1865Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
1866
1867 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
1868 (build_endian_shift): Don't check proc64.
1869 (build_instruction): Always set memval to uword64. Cast op2 to
1870 uword64 when shifting it left in memory instructions. Always use
1871 the same code for stores--don't special case proc64.
1872
1873 * gencode.c (build_mips16_operands): Fix base PC value for PC
1874 relative operands.
1875 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
1876 jal instruction.
1877 * interp.c (simJALDELAYSLOT): Define.
1878 (JALDELAYSLOT): Define.
1879 (INDELAYSLOT, INJALDELAYSLOT): Define.
1880 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
1881
1882Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
1883
1884 * interp.c (sim_open): add flush_cache as a PMON routine
1885 (sim_monitor): handle flush_cache by ignoring it
1886
1887Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
1888
1889 * gencode.c (build_instruction): Use !ByteSwapMem instead of
1890 BigEndianMem.
1891 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
1892 (BigEndianMem): Rename to ByteSwapMem and change sense.
1893 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
1894 BigEndianMem references to !ByteSwapMem.
1895 (set_endianness): New function, with prototype.
1896 (sim_open): Call set_endianness.
1897 (sim_info): Use simBE instead of BigEndianMem.
1898 (xfer_direct_word, xfer_direct_long, swap_direct_word,
1899 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
1900 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
1901 ifdefs, keeping the prototype declaration.
1902 (swap_word): Rewrite correctly.
1903 (ColdReset): Delete references to CONFIG. Delete endianness related
1904 code; moved to set_endianness.
1905
1906Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
1907
1908 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
1909 * interp.c (CHECKHILO): Define away.
1910 (simSIGINT): New macro.
1911 (membank_size): Increase from 1MB to 2MB.
1912 (control_c): New function.
1913 (sim_resume): Rename parameter signal to signal_number. Add local
1914 variable prev. Call signal before and after simulate.
1915 (sim_stop_reason): Add simSIGINT support.
1916 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
1917 functions always.
1918 (sim_warning): Delete call to SignalException. Do call printf_filtered
1919 if logfh is NULL.
1920 (AddressTranslation): Add #ifdef DEBUG around debugging message and
1921 a call to sim_warning.
1922
1923Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
1924
1925 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
1926 16 bit instructions.
1927
1928Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
1929
1930 Add support for mips16 (16 bit MIPS implementation):
1931 * gencode.c (inst_type): Add mips16 instruction encoding types.
1932 (GETDATASIZEINSN): Define.
1933 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
1934 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
1935 mtlo.
1936 (MIPS16_DECODE): New table, for mips16 instructions.
1937 (bitmap_val): New static function.
1938 (struct mips16_op): Define.
1939 (mips16_op_table): New table, for mips16 operands.
1940 (build_mips16_operands): New static function.
1941 (process_instructions): If PC is odd, decode a mips16
1942 instruction. Break out instruction handling into new
1943 build_instruction function.
1944 (build_instruction): New static function, broken out of
1945 process_instructions. Check modifiers rather than flags for SHIFT
1946 bit count and m[ft]{hi,lo} direction.
1947 (usage): Pass program name to fprintf.
1948 (main): Remove unused variable this_option_optind. Change
1949 ``*loptarg++'' to ``loptarg++''.
1950 (my_strtoul): Parenthesize && within ||.
1951 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
1952 (simulate): If PC is odd, fetch a 16 bit instruction, and
1953 increment PC by 2 rather than 4.
1954 * configure.in: Add case for mips16*-*-*.
1955 * configure: Rebuild.
1956
1957Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
1958
1959 * interp.c: Allow -t to enable tracing in standalone simulator.
1960 Fix garbage output in trace file and error messages.
1961
1962Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
1963
1964 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
1965 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
1966 * configure.in: Simplify using macros in ../common/aclocal.m4.
1967 * configure: Regenerated.
1968 * tconfig.in: New file.
1969
1970Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
1971
1972 * interp.c: Fix bugs in 64-bit port.
1973 Use ansi function declarations for msvc compiler.
1974 Initialize and test file pointer in trace code.
1975 Prevent duplicate definition of LAST_EMED_REGNUM.
1976
1977Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
1978
1979 * interp.c (xfer_big_long): Prevent unwanted sign extension.
1980
1981Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
1982
1983 * interp.c (SignalException): Check for explicit terminating
1984 breakpoint value.
1985 * gencode.c: Pass instruction value through SignalException()
1986 calls for Trap, Breakpoint and Syscall.
1987
1988Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
1989
1990 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
1991 only used on those hosts that provide it.
1992 * configure.in: Add sqrt() to list of functions to be checked for.
1993 * config.in: Re-generated.
1994 * configure: Re-generated.
1995
1996Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
1997
1998 * gencode.c (process_instructions): Call build_endian_shift when
1999 expanding STORE RIGHT, to fix swr.
2000 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2001 clear the high bits.
2002 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2003 Fix float to int conversions to produce signed values.
2004
2005Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2006
2007 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2008 (process_instructions): Correct handling of nor instruction.
2009 Correct shift count for 32 bit shift instructions. Correct sign
2010 extension for arithmetic shifts to not shift the number of bits in
2011 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2012 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2013 Fix madd.
2014 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2015 It's OK to have a mult follow a mult. What's not OK is to have a
2016 mult follow an mfhi.
2017 (Convert): Comment out incorrect rounding code.
2018
2019Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2020
2021 * interp.c (sim_monitor): Improved monitor printf
2022 simulation. Tidied up simulator warnings, and added "--log" option
2023 for directing warning message output.
2024 * gencode.c: Use sim_warning() rather than WARNING macro.
2025
2026Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2027
2028 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2029 getopt1.o, rather than on gencode.c. Link objects together.
2030 Don't link against -liberty.
2031 (gencode.o, getopt.o, getopt1.o): New targets.
2032 * gencode.c: Include <ctype.h> and "ansidecl.h".
2033 (AND): Undefine after including "ansidecl.h".
2034 (ULONG_MAX): Define if not defined.
2035 (OP_*): Don't define macros; now defined in opcode/mips.h.
2036 (main): Call my_strtoul rather than strtoul.
2037 (my_strtoul): New static function.
2038
2039Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2040
2041 * gencode.c (process_instructions): Generate word64 and uword64
2042 instead of `long long' and `unsigned long long' data types.
2043 * interp.c: #include sysdep.h to get signals, and define default
2044 for SIGBUS.
2045 * (Convert): Work around for Visual-C++ compiler bug with type
2046 conversion.
2047 * support.h: Make things compile under Visual-C++ by using
2048 __int64 instead of `long long'. Change many refs to long long
2049 into word64/uword64 typedefs.
2050
2051Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2052
2053 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2054 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2055 (docdir): Removed.
2056 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2057 (AC_PROG_INSTALL): Added.
2058 (AC_PROG_CC): Moved to before configure.host call.
2059 * configure: Rebuilt.
2060
2061Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2062
2063 * configure.in: Define @SIMCONF@ depending on mips target.
2064 * configure: Rebuild.
2065 * Makefile.in (run): Add @SIMCONF@ to control simulator
2066 construction.
2067 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2068 * interp.c: Remove some debugging, provide more detailed error
2069 messages, update memory accesses to use LOADDRMASK.
2070
2071Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2072
2073 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2074 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2075 stamp-h.
2076 * configure: Rebuild.
2077 * config.in: New file, generated by autoheader.
2078 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2079 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2080 HAVE_ANINT and HAVE_AINT, as appropriate.
2081 * Makefile.in (run): Use @LIBS@ rather than -lm.
2082 (interp.o): Depend upon config.h.
2083 (Makefile): Just rebuild Makefile.
2084 (clean): Remove stamp-h.
2085 (mostlyclean): Make the same as clean, not as distclean.
2086 (config.h, stamp-h): New targets.
2087
2088Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2089
2090 * interp.c (ColdReset): Fix boolean test. Make all simulator
2091 globals static.
2092
2093Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2094
2095 * interp.c (xfer_direct_word, xfer_direct_long,
2096 swap_direct_word, swap_direct_long, xfer_big_word,
2097 xfer_big_long, xfer_little_word, xfer_little_long,
2098 swap_word,swap_long): Added.
2099 * interp.c (ColdReset): Provide function indirection to
2100 host<->simulated_target transfer routines.
2101 * interp.c (sim_store_register, sim_fetch_register): Updated to
2102 make use of indirected transfer routines.
2103
2104Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2105
2106 * gencode.c (process_instructions): Ensure FP ABS instruction
2107 recognised.
2108 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2109 system call support.
2110
2111Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2112
2113 * interp.c (sim_do_command): Complain if callback structure not
2114 initialised.
2115
2116Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2117
2118 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2119 support for Sun hosts.
2120 * Makefile.in (gencode): Ensure the host compiler and libraries
2121 used for cross-hosted build.
2122
2123Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2124
2125 * interp.c, gencode.c: Some more (TODO) tidying.
2126
2127Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2128
2129 * gencode.c, interp.c: Replaced explicit long long references with
2130 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2131 * support.h (SET64LO, SET64HI): Macros added.
2132
2133Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2134
2135 * configure: Regenerate with autoconf 2.7.
2136
2137Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2138
2139 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2140 * support.h: Remove superfluous "1" from #if.
2141 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2142
2143Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2144
2145 * interp.c (StoreFPR): Control UndefinedResult() call on
2146 WARN_RESULT manifest.
2147
2148Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2149
2150 * gencode.c: Tidied instruction decoding, and added FP instruction
2151 support.
2152
2153 * interp.c: Added dineroIII, and BSD profiling support. Also
2154 run-time FP handling.
2155
2156Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2157
2158 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2159 gencode.c, interp.c, support.h: created.
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