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PR sim/12737
[deliverable/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
d79fe0d6
MF		 12011-02-14 Mike Frysinger <vapier@gentoo.org>
2
3 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
4 (tx3904sio_fifo_reset): Likewise.
5 * interp.c (sim_monitor): Likewise.
6
5558e7e6
MF		 72010-04-14 Mike Frysinger <vapier@gentoo.org>
8
9 * interp.c (sim_write): Add const to buffer arg.
10
35aafff4
JB		 112010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
12
13 * interp.c: Don't include sysdep.h
14
3725885a
RW		 152010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
16
17 * configure: Regenerate.
18
d6416cdc
RW		 192009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
20
81ecdfbb
RW		 21 * config.in: Regenerate.
22 * configure: Likewise.
23
d6416cdc
RW		 24 * configure: Regenerate.
25
b5bd9624
HPN		 262008-07-11 Hans-Peter Nilsson <hp@axis.com>
27
28 * configure: Regenerate to track ../common/common.m4 changes.
29 * config.in: Ditto.
30
6efef468
JM		 312008-06-06 Vladimir Prus <vladimir@codesourcery.com>
32 Daniel Jacobowitz <dan@codesourcery.com>
33 Joseph Myers <joseph@codesourcery.com>
34
35 * configure: Regenerate.
36
60dc88db
RS		 372007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
38
39 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
40 that unconditionally allows fmt_ps.
41 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
42 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
43 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
44 filter from 64,f to 32,f.
45 (PREFX): Change filter from 64 to 32.
46 (LDXC1, LUXC1): Provide separate mips32r2 implementations
47 that use do_load_double instead of do_load. Make both LUXC1
48 versions unpredictable if SizeFGR () != 64.
49 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
50 instead of do_store. Remove unused variable. Make both SUXC1
51 versions unpredictable if SizeFGR () != 64.
52
599ca73e
RS		 532007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
54
55 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
56 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
57 shifts for that case.
58
2525df03
NC		 592007-09-04 Nick Clifton <nickc@redhat.com>
60
61 * interp.c (options enum): Add OPTION_INFO_MEMORY.
62 (display_mem_info): New static variable.
63 (mips_option_handler): Handle OPTION_INFO_MEMORY.
64 (mips_options): Add info-memory and memory-info.
65 (sim_open): After processing the command line and board
66 specification, check display_mem_info. If it is set then
67 call the real handler for the --memory-info command line
68 switch.
69
35ee6e1e
JB		 702007-08-24 Joel Brobecker <brobecker@adacore.com>
71
72 * configure.ac: Change license of multi-run.c to GPL version 3.
73 * configure: Regenerate.
74
d5fb0879
RS		 752007-06-28 Richard Sandiford <richard@codesourcery.com>
76
77 * configure.ac, configure: Revert last patch.
78
2a2ce21b
RS		 792007-06-26 Richard Sandiford <richard@codesourcery.com>
80
81 * configure.ac (sim_mipsisa3264_configs): New variable.
82 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
83 every configuration support all four targets, using the triplet to
84 determine the default.
85 * configure: Regenerate.
86
efdcccc9
RS		 872007-06-25 Richard Sandiford <richard@codesourcery.com>
88
0a7692b2 89 * Makefile.in (m16run.o): New rule.
efdcccc9 90
f532a356
TS		 912007-05-15 Thiemo Seufer <ths@mips.com>
92
93 * mips3264r2.igen (DSHD): Fix compile warning.
94
bfe9c90b
TS		 952007-05-14 Thiemo Seufer <ths@mips.com>
96
97 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
98 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
99 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
100 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
101 for mips32r2.
102
53f4826b
TS		 1032007-03-01 Thiemo Seufer <ths@mips.com>
104
105 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
106 and mips64.
107
8bf3ddc8
TS		 1082007-02-20 Thiemo Seufer <ths@mips.com>
109
110 * dsp.igen: Update copyright notice.
111 * dsp2.igen: Fix copyright notice.
112
8b082fb1
TS		 1132007-02-20 Thiemo Seufer <ths@mips.com>
114 Chao-Ying Fu <fu@mips.com>
115
116 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
117 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
118 Add dsp2 to sim_igen_machine.
119 * configure: Regenerate.
120 * dsp.igen (do_ph_op): Add MUL support when op = 2.
121 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
122 (mulq_rs.ph): Use do_ph_mulq.
123 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
124 * mips.igen: Add dsp2 model and include dsp2.igen.
125 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
126 for *mips32r2, *mips64r2, *dsp.
127 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
128 for *mips32r2, *mips64r2, *dsp2.
129 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
130
b1004875
TS		 1312007-02-19 Thiemo Seufer <ths@mips.com>
132 Nigel Stephens <nigel@mips.com>
133
134 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
135 jumps with hazard barrier.
136
f8df4c77
TS		 1372007-02-19 Thiemo Seufer <ths@mips.com>
138 Nigel Stephens <nigel@mips.com>
139
140 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
141 after each call to sim_io_write.
142
b1004875 1432007-02-19 Thiemo Seufer <ths@mips.com>
07802d98 144 Nigel Stephens <nigel@mips.com>
b1004875
TS		 145
146 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
147 supported by this simulator.
07802d98
TS		 148 (decode_coproc): Recognise additional CP0 Config registers
149 correctly.
150
14fb6c5a
TS		 1512007-02-19 Thiemo Seufer <ths@mips.com>
152 Nigel Stephens <nigel@mips.com>
153 David Ung <davidu@mips.com>
154
155 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
156 uninterpreted formats. If fmt is one of the uninterpreted types
157 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
158 fmt_word, and fmt_uninterpreted_64 like fmt_long.
159 (store_fpr): When writing an invalid odd register, set the
160 matching even register to fmt_unknown, not the following register.
161 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
162 the the memory window at offset 0 set by --memory-size command
163 line option.
164 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
165 point register.
166 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
167 register.
168 (sim_monitor): When returning the memory size to the MIPS
169 application, use the value in STATE_MEM_SIZE, not an arbitrary
170 hardcoded value.
171 (cop_lw): Don' mess around with FPR_STATE, just pass
172 fmt_uninterpreted_32 to StoreFPR.
173 (cop_sw): Similarly.
174 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
175 (cop_sd): Similarly.
176 * mips.igen (not_word_value): Single version for mips32, mips64
177 and mips16.
178
c8847145
TS		 1792007-02-19 Thiemo Seufer <ths@mips.com>
180 Nigel Stephens <nigel@mips.com>
181
182 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
183 MBytes.
184
4b5d35ee
TS		 1852007-02-17 Thiemo Seufer <ths@mips.com>
186
187 * configure.ac (mips*-sde-elf*): Move in front of generic machine
188 configuration.
189 * configure: Regenerate.
190
3669427c
TS		 1912007-02-17 Thiemo Seufer <ths@mips.com>
192
193 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
194 Add mdmx to sim_igen_machine.
195 (mipsisa64*-*-*): Likewise. Remove dsp.
196 (mipsisa32*-*-*): Remove dsp.
197 * configure: Regenerate.
198
109ad085
TS		 1992007-02-13 Thiemo Seufer <ths@mips.com>
200
201 * configure.ac: Add mips*-sde-elf* target.
202 * configure: Regenerate.
203
921d7ad3
HPN		 2042006-12-21 Hans-Peter Nilsson <hp@axis.com>
205
206 * acconfig.h: Remove.
207 * config.in, configure: Regenerate.
208
02f97da7
TS		 2092006-11-07 Thiemo Seufer <ths@mips.com>
210
211 * dsp.igen (do_w_op): Fix compiler warning.
212
2d2733fc
TS		 2132006-08-29 Thiemo Seufer <ths@mips.com>
214 David Ung <davidu@mips.com>
215
216 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
217 sim_igen_machine.
218 * configure: Regenerate.
219 * mips.igen (model): Add smartmips.
220 (MADDU): Increment ACX if carry.
221 (do_mult): Clear ACX.
222 (ROR,RORV): Add smartmips.
223 (include): Include smartmips.igen.
224 * sim-main.h (ACX): Set to REGISTERS[89].
225 * smartmips.igen: New file.
226
d85c3a10
TS		 2272006-08-29 Thiemo Seufer <ths@mips.com>
228 David Ung <davidu@mips.com>
229
230 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
231 mips3264r2.igen. Add missing dependency rules.
232 * m16e.igen: Support for mips16e save/restore instructions.
233
e85e3205
RE		 2342006-06-13 Richard Earnshaw <rearnsha@arm.com>
235
236 * configure: Regenerated.
237
2f0122dc
DJ		 2382006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
239
240 * configure: Regenerated.
241
20e95c23
DJ		 2422006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
243
244 * configure: Regenerated.
245
69088b17
CF		 2462006-05-15 Chao-ying Fu <fu@mips.com>
247
248 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
249
0275de4e
NC		 2502006-04-18 Nick Clifton <nickc@redhat.com>
251
252 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
253 statement.
254
b3a3ffef
HPN		 2552006-03-29 Hans-Peter Nilsson <hp@axis.com>
256
257 * configure: Regenerate.
258
40a5538e
CF		 2592005-12-14 Chao-ying Fu <fu@mips.com>
260
261 * Makefile.in (SIM_OBJS): Add dsp.o.
262 (dsp.o): New dependency.
263 (IGEN_INCLUDE): Add dsp.igen.
264 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
265 mipsisa64*-*-*): Add dsp to sim_igen_machine.
266 * configure: Regenerate.
267 * mips.igen: Add dsp model and include dsp.igen.
268 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
269 because these instructions are extended in DSP ASE.
270 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
271 adding 6 DSP accumulator registers and 1 DSP control register.
272 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
273 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
274 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
275 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
276 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
277 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
278 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
279 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
280 DSPCR_CCOND_SMASK): New define.
281 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
282 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
283
21d14896
ILT		 2842005-07-08 Ian Lance Taylor <ian@airs.com>
285
286 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
287
b16d63da
DU		 2882005-06-16 David Ung <davidu@mips.com>
289 Nigel Stephens <nigel@mips.com>
290
291 * mips.igen: New mips16e model and include m16e.igen.
292 (check_u64): Add mips16e tag.
293 * m16e.igen: New file for MIPS16e instructions.
294 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
295 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
296 models.
297 * configure: Regenerate.
298
e70cb6cd
CD		 2992005-05-26 David Ung <davidu@mips.com>
300
301 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
302 tags to all instructions which are applicable to the new ISAs.
303 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
304 vr.igen.
305 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
306 instructions.
307 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
308 to mips.igen.
309 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
310 * configure: Regenerate.
311
2b193c4a
MK		 3122005-03-23 Mark Kettenis <kettenis@gnu.org>
313
314 * configure: Regenerate.
315
35695fd6
AC		 3162005-01-14 Andrew Cagney <cagney@gnu.org>
317
318 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
319 explicit call to AC_CONFIG_HEADER.
320 * configure: Regenerate.
321
f0569246
AC		 3222005-01-12 Andrew Cagney <cagney@gnu.org>
323
324 * configure.ac: Update to use ../common/common.m4.
325 * configure: Re-generate.
326
38f48d72
AC		 3272005-01-11 Andrew Cagney <cagney@localhost.localdomain>
328
329 * configure: Regenerated to track ../common/aclocal.m4 changes.
330
b7026657
AC		 3312005-01-07 Andrew Cagney <cagney@gnu.org>
332
333 * configure.ac: Rename configure.in, require autoconf 2.59.
334 * configure: Re-generate.
335
379832de
HPN		 3362004-12-08 Hans-Peter Nilsson <hp@axis.com>
337
338 * configure: Regenerate for ../common/aclocal.m4 update.
339
cd62154c
AC		 3402004-09-24 Monika Chaddha <monika@acmet.com>
341
342 Committed by Andrew Cagney.
343 * m16.igen (CMP, CMPI): Fix assembler.
344
e5da76ec
CD		 3452004-08-18 Chris Demetriou <cgd@broadcom.com>
346
347 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
348 * configure: Regenerate.
349
139181c8
CD		 3502004-06-25 Chris Demetriou <cgd@broadcom.com>
351
352 * configure.in (sim_m16_machine): Include mipsIII.
353 * configure: Regenerate.
354
1a27f959
CD		 3552004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
356
357 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
358 from COP0_BADVADDR.
359 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
360
5dbb7b5a
CD		 3612004-04-10 Chris Demetriou <cgd@broadcom.com>
362
363 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
364
14234056
CD		 3652004-04-09 Chris Demetriou <cgd@broadcom.com>
366
367 * mips.igen (check_fmt): Remove.
368 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
369 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
370 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
371 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
372 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
373 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
374 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
375 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
376 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
377 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
378
c6f9085c
CD		 3792004-04-09 Chris Demetriou <cgd@broadcom.com>
380
381 * sb1.igen (check_sbx): New function.
382 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
383
11d66e66 3842004-03-29 Chris Demetriou <cgd@broadcom.com>
0e1b7197
RS		 385 Richard Sandiford <rsandifo@redhat.com>
386
387 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
388 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
389 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
390 separate implementations for mipsIV and mipsV. Use new macros to
391 determine whether the restrictions apply.
392
b3208fb8
CD		 3932004-01-19 Chris Demetriou <cgd@broadcom.com>
394
395 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
396 (check_mult_hilo): Improve comments.
397 (check_div_hilo): Likewise. Also, fork off a new version
398 to handle mips32/mips64 (since there are no hazards to check
399 in MIPS32/MIPS64).
400
9a1d84fb
CD		 4012003-06-17 Richard Sandiford <rsandifo@redhat.com>
402
403 * mips.igen (do_dmultx): Fix check for negative operands.
404
ae451ac6
ILT		 4052003-05-16 Ian Lance Taylor <ian@airs.com>
406
407 * Makefile.in (SHELL): Make sure this is defined.
408 (various): Use $(SHELL) whenever we invoke move-if-change.
409
dd69d292
CD		 4102003-05-03 Chris Demetriou <cgd@broadcom.com>
411
412 * cp1.c: Tweak attribution slightly.
413 * cp1.h: Likewise.
414 * mdmx.c: Likewise.
415 * mdmx.igen: Likewise.
416 * mips3d.igen: Likewise.
417 * sb1.igen: Likewise.
418
bcd0068e
CD		 4192003-04-15 Richard Sandiford <rsandifo@redhat.com>
420
421 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
422 unsigned operands.
423
6b4a8935
AC		 4242003-02-27 Andrew Cagney <cagney@redhat.com>
425
601da316
AC		 426 * interp.c (sim_open): Rename _bfd to bfd.
427 (sim_create_inferior): Ditto.
6b4a8935 428
d29e330f
CD		 4292003-01-14 Chris Demetriou <cgd@broadcom.com>
430
431 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
432
a2353a08
CD		 4332003-01-14 Chris Demetriou <cgd@broadcom.com>
434
435 * mips.igen (EI, DI): Remove.
436
80551777
CD		 4372003-01-05 Richard Sandiford <rsandifo@redhat.com>
438
439 * Makefile.in (tmp-run-multi): Fix mips16 filter.
440
4c54fc26
CD		 4412003-01-04 Richard Sandiford <rsandifo@redhat.com>
442 Andrew Cagney <ac131313@redhat.com>
443 Gavin Romig-Koch <gavin@redhat.com>
444 Graydon Hoare <graydon@redhat.com>
445 Aldy Hernandez <aldyh@redhat.com>
446 Dave Brolley <brolley@redhat.com>
447 Chris Demetriou <cgd@broadcom.com>
448
449 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
450 (sim_mach_default): New variable.
451 (mips64vr-*-*, mips64vrel-*-*): New configurations.
452 Add a new simulator generator, MULTI.
453 * configure: Regenerate.
454 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
455 (multi-run.o): New dependency.
456 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
457 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
458 (tmp-multi): Combine them.
459 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
460 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
461 (distclean-extra): New rule.
462 * sim-main.h: Include bfd.h.
463 (MIPS_MACH): New macro.
464 * mips.igen (vr4120, vr5400, vr5500): New models.
465 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
466 * vr.igen: Replace with new version.
467
e6c674b8
CD		 4682003-01-04 Chris Demetriou <cgd@broadcom.com>
469
470 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
471 * configure: Regenerate.
472
28f50ac8
CD		 4732002-12-31 Chris Demetriou <cgd@broadcom.com>
474
475 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
476 * mips.igen: Remove all invocations of check_branch_bug and
477 mark_branch_bug.
478
5071ffe6
CD		 4792002-12-16 Chris Demetriou <cgd@broadcom.com>
480
481 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
482
06e7837e
CD		 4832002-07-30 Chris Demetriou <cgd@broadcom.com>
484
485 * mips.igen (do_load_double, do_store_double): New functions.
486 (LDC1, SDC1): Rename to...
487 (LDC1b, SDC1b): respectively.
488 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
489
2265c243
MS		 4902002-07-29 Michael Snyder <msnyder@redhat.com>
491
492 * cp1.c (fp_recip2): Modify initialization expression so that
493 GCC will recognize it as constant.
494
a2f8b4f3
CD		 4952002-06-18 Chris Demetriou <cgd@broadcom.com>
496
497 * mdmx.c (SD_): Delete.
498 (Unpredictable): Re-define, for now, to directly invoke
499 unpredictable_action().
500 (mdmx_acc_op): Fix error in .ob immediate handling.
501
b4b6c939
AC		 5022002-06-18 Andrew Cagney <cagney@redhat.com>
503
504 * interp.c (sim_firmware_command): Initialize `address'.
505
c8cca39f
AC		 5062002-06-16 Andrew Cagney <ac131313@redhat.com>
507
508 * configure: Regenerated to track ../common/aclocal.m4 changes.
509
e7e81181
CD		 5102002-06-14 Chris Demetriou <cgd@broadcom.com>
511 Ed Satterthwaite <ehs@broadcom.com>
512
513 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
514 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
515 * mips.igen: Include mips3d.igen.
516 (mips3d): New model name for MIPS-3D ASE instructions.
517 (CVT.W.fmt): Don't use this instruction for word (source) format
518 instructions.
519 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
520 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
521 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
522 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
523 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
524 (RSquareRoot1, RSquareRoot2): New macros.
525 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
526 (fp_rsqrt2): New functions.
527 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
528 * configure: Regenerate.
529
3a2b820e 5302002-06-13 Chris Demetriou <cgd@broadcom.com>
eab54952 531 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 532
533 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
534 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
535 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
536 (convert): Note that this function is not used for paired-single
537 format conversions.
538 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
539 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
540 (check_fmt_p): Enable paired-single support.
541 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
542 (PUU.PS): New instructions.
543 (CVT.S.fmt): Don't use this instruction for paired-single format
544 destinations.
545 * sim-main.h (FP_formats): New value 'fmt_ps.'
546 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
547 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
548
d18ea9c2
CD		 5492002-06-12 Chris Demetriou <cgd@broadcom.com>
550
551 * mips.igen: Fix formatting of function calls in
552 many FP operations.
553
95fd5cee
CD		 5542002-06-12 Chris Demetriou <cgd@broadcom.com>
555
556 * mips.igen (MOVN, MOVZ): Trace result.
557 (TNEI): Print "tnei" as the opcode name in traces.
558 (CEIL.W): Add disassembly string for traces.
559 (RSQRT.fmt): Make location of disassembly string consistent
560 with other instructions.
561
4f0d55ae
CD		 5622002-06-12 Chris Demetriou <cgd@broadcom.com>
563
564 * mips.igen (X): Delete unused function.
565
3c25f8c7
AC		 5662002-06-08 Andrew Cagney <cagney@redhat.com>
567
568 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
569
f3c08b7e
CD		 5702002-06-07 Chris Demetriou <cgd@broadcom.com>
571 Ed Satterthwaite <ehs@broadcom.com>
572
573 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
574 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
575 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
576 (fp_nmsub): New prototypes.
577 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
578 (NegMultiplySub): New defines.
579 * mips.igen (RSQRT.fmt): Use RSquareRoot().
580 (MADD.D, MADD.S): Replace with...
581 (MADD.fmt): New instruction.
582 (MSUB.D, MSUB.S): Replace with...
583 (MSUB.fmt): New instruction.
584 (NMADD.D, NMADD.S): Replace with...
585 (NMADD.fmt): New instruction.
586 (NMSUB.D, MSUB.S): Replace with...
587 (NMSUB.fmt): New instruction.
588
52714ff9
CD		 5892002-06-07 Chris Demetriou <cgd@broadcom.com>
590 Ed Satterthwaite <ehs@broadcom.com>
591
592 * cp1.c: Fix more comment spelling and formatting.
593 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
594 (denorm_mode): New function.
595 (fpu_unary, fpu_binary): Round results after operation, collect
596 status from rounding operations, and update the FCSR.
597 (convert): Collect status from integer conversions and rounding
598 operations, and update the FCSR. Adjust NaN values that result
599 from conversions. Convert to use sim_io_eprintf rather than
600 fprintf, and remove some debugging code.
601 * cp1.h (fenr_FS): New define.
602
577d8c4b
CD		 6032002-06-07 Chris Demetriou <cgd@broadcom.com>
604
605 * cp1.c (convert): Remove unusable debugging code, and move MIPS
606 rounding mode to sim FP rounding mode flag conversion code into...
607 (rounding_mode): New function.
608
196496ed
CD		 6092002-06-07 Chris Demetriou <cgd@broadcom.com>
610
611 * cp1.c: Clean up formatting of a few comments.
612 (value_fpr): Reformat switch statement.
613
cfe9ea23
CD		 6142002-06-06 Chris Demetriou <cgd@broadcom.com>
615 Ed Satterthwaite <ehs@broadcom.com>
616
617 * cp1.h: New file.
618 * sim-main.h: Include cp1.h.
619 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
620 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
621 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
622 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
623 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
624 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
625 * cp1.c: Don't include sim-fpu.h; already included by
626 sim-main.h. Clean up formatting of some comments.
627 (NaN, Equal, Less): Remove.
628 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
629 (fp_cmp): New functions.
630 * mips.igen (do_c_cond_fmt): Remove.
631 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
632 Compare. Add result tracing.
633 (CxC1): Remove, replace with...
634 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
635 (DMxC1): Remove, replace with...
636 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
637 (MxC1): Remove, replace with...
638 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
639
ee7254b0
CD		 6402002-06-04 Chris Demetriou <cgd@broadcom.com>
641
642 * sim-main.h (FGRIDX): Remove, replace all uses with...
643 (FGR_BASE): New macro.
644 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
645 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
646 (NR_FGR, FGR): Likewise.
647 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
648 * mips.igen: Likewise.
649
d3eb724f
CD		 6502002-06-04 Chris Demetriou <cgd@broadcom.com>
651
652 * cp1.c: Add an FSF Copyright notice to this file.
653
ba46ddd0
CD		 6542002-06-04 Chris Demetriou <cgd@broadcom.com>
655 Ed Satterthwaite <ehs@broadcom.com>
656
657 * cp1.c (Infinity): Remove.
658 * sim-main.h (Infinity): Likewise.
659
660 * cp1.c (fp_unary, fp_binary): New functions.
661 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
662 (fp_sqrt): New functions, implemented in terms of the above.
663 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
664 (Recip, SquareRoot): Remove (replaced by functions above).
665 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
666 (fp_recip, fp_sqrt): New prototypes.
667 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
668 (Recip, SquareRoot): Replace prototypes with #defines which
669 invoke the functions above.
670
18d8a52d
CD		 6712002-06-03 Chris Demetriou <cgd@broadcom.com>
672
673 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
674 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
675 file, remove PARAMS from prototypes.
676 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
677 simulator state arguments.
678 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
679 pass simulator state arguments.
680 * cp1.c (SD): Redefine as CPU_STATE(cpu).
681 (store_fpr, convert): Remove 'sd' argument.
682 (value_fpr): Likewise. Convert to use 'SD' instead.
683
0f154cbd
CD		 6842002-06-03 Chris Demetriou <cgd@broadcom.com>
685
686 * cp1.c (Min, Max): Remove #if 0'd functions.
687 * sim-main.h (Min, Max): Remove.
688
e80fc152
CD		 6892002-06-03 Chris Demetriou <cgd@broadcom.com>
690
691 * cp1.c: fix formatting of switch case and default labels.
692 * interp.c: Likewise.
693 * sim-main.c: Likewise.
694
bad673a9
CD		 6952002-06-03 Chris Demetriou <cgd@broadcom.com>
696
697 * cp1.c: Clean up comments which describe FP formats.
698 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
699
7cbea089
CD		 7002002-06-03 Chris Demetriou <cgd@broadcom.com>
701 Ed Satterthwaite <ehs@broadcom.com>
702
703 * configure.in (mipsisa64sb1*-*-*): New target for supporting
704 Broadcom SiByte SB-1 processor configurations.
705 * configure: Regenerate.
706 * sb1.igen: New file.
707 * mips.igen: Include sb1.igen.
708 (sb1): New model.
709 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
710 * mdmx.igen: Add "sb1" model to all appropriate functions and
711 instructions.
712 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
713 (ob_func, ob_acc): Reference the above.
714 (qh_acc): Adjust to keep the same size as ob_acc.
715 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
716 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
717
909daa82
CD		 7182002-06-03 Chris Demetriou <cgd@broadcom.com>
719
720 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
721
f4f1b9f1
CD		 7222002-06-02 Chris Demetriou <cgd@broadcom.com>
723 Ed Satterthwaite <ehs@broadcom.com>
724
725 * mips.igen (mdmx): New (pseudo-)model.
726 * mdmx.c, mdmx.igen: New files.
727 * Makefile.in (SIM_OBJS): Add mdmx.o.
728 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
729 New typedefs.
730 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
731 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
732 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
733 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
734 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
735 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
736 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
737 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
738 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
739 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
740 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
741 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
742 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
743 (qh_fmtsel): New macros.
744 (_sim_cpu): New member "acc".
745 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
746 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
747
5accf1ff
CD		 7482002-05-01 Chris Demetriou <cgd@broadcom.com>
749
750 * interp.c: Use 'deprecated' rather than 'depreciated.'
751 * sim-main.h: Likewise.
752
402586aa
CD		 7532002-05-01 Chris Demetriou <cgd@broadcom.com>
754
755 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
756 which wouldn't compile anyway.
757 * sim-main.h (unpredictable_action): New function prototype.
758 (Unpredictable): Define to call igen function unpredictable().
759 (NotWordValue): New macro to call igen function not_word_value().
760 (UndefinedResult): Remove.
761 * interp.c (undefined_result): Remove.
762 (unpredictable_action): New function.
763 * mips.igen (not_word_value, unpredictable): New functions.
764 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
765 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
766 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
767 NotWordValue() to check for unpredictable inputs, then
768 Unpredictable() to handle them.
769
c9b9995a
CD		 7702002-02-24 Chris Demetriou <cgd@broadcom.com>
771
772 * mips.igen: Fix formatting of calls to Unpredictable().
773
e1015982
AC		 7742002-04-20 Andrew Cagney <ac131313@redhat.com>
775
776 * interp.c (sim_open): Revert previous change.
777
b882a66b
AO		 7782002-04-18 Alexandre Oliva <aoliva@redhat.com>
779
780 * interp.c (sim_open): Disable chunk of code that wrote code in
781 vector table entries.
782
c429b7dd
CD		 7832002-03-19 Chris Demetriou <cgd@broadcom.com>
784
785 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
786 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
787 unused definitions.
788
37d146fa
CD		 7892002-03-19 Chris Demetriou <cgd@broadcom.com>
790
791 * cp1.c: Fix many formatting issues.
792
07892c0b
CD		 7932002-03-19 Chris G. Demetriou <cgd@broadcom.com>
794
795 * cp1.c (fpu_format_name): New function to replace...
796 (DOFMT): This. Delete, and update all callers.
797 (fpu_rounding_mode_name): New function to replace...
798 (RMMODE): This. Delete, and update all callers.
799
487f79b7
CD		 8002002-03-19 Chris G. Demetriou <cgd@broadcom.com>
801
802 * interp.c: Move FPU support routines from here to...
803 * cp1.c: Here. New file.
804 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
805 (cp1.o): New target.
806
1e799e28
CD		 8072002-03-12 Chris Demetriou <cgd@broadcom.com>
808
809 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
810 * mips.igen (mips32, mips64): New models, add to all instructions
811 and functions as appropriate.
812 (loadstore_ea, check_u64): New variant for model mips64.
813 (check_fmt_p): New variant for models mipsV and mips64, remove
814 mipsV model marking fro other variant.
815 (SLL) Rename to...
816 (SLLa) this.
817 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
818 for mips32 and mips64.
819 (DCLO, DCLZ): New instructions for mips64.
820
82f728db
CD		 8212002-03-07 Chris Demetriou <cgd@broadcom.com>
822
823 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
824 immediate or code as a hex value with the "%#lx" format.
825 (ANDI): Likewise, and fix printed instruction name.
826
b96e7ef1
CD		 8272002-03-05 Chris Demetriou <cgd@broadcom.com>
828
829 * sim-main.h (UndefinedResult, Unpredictable): New macros
830 which currently do nothing.
831
d35d4f70
CD		 8322002-03-05 Chris Demetriou <cgd@broadcom.com>
833
834 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
835 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
836 (status_CU3): New definitions.
837
838 * sim-main.h (ExceptionCause): Add new values for MIPS32
839 and MIPS64: MDMX, MCheck, CacheErr. Update comments
840 for DebugBreakPoint and NMIReset to note their status in
841 MIPS32 and MIPS64.
842 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
843 (SignalExceptionCacheErr): New exception macros.
844
3ad6f714
CD		 8452002-03-05 Chris Demetriou <cgd@broadcom.com>
846
847 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
848 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
849 is always enabled.
850 (SignalExceptionCoProcessorUnusable): Take as argument the
851 unusable coprocessor number.
852
86b77b47
CD		 8532002-03-05 Chris Demetriou <cgd@broadcom.com>
854
855 * mips.igen: Fix formatting of all SignalException calls.
856
97a88e93 8572002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 858
859 * sim-main.h (SIGNEXTEND): Remove.
860
97a88e93 8612002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 862
863 * mips.igen: Remove gencode comment from top of file, fix
864 spelling in another comment.
865
97a88e93 8662002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 867
868 * mips.igen (check_fmt, check_fmt_p): New functions to check
869 whether specific floating point formats are usable.
870 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
871 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
872 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
873 Use the new functions.
874 (do_c_cond_fmt): Remove format checks...
875 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
876
97a88e93 8772002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 878
879 * mips.igen: Fix formatting of check_fpu calls.
880
41774c9d
CD		 8812002-03-03 Chris Demetriou <cgd@broadcom.com>
882
883 * mips.igen (FLOOR.L.fmt): Store correct destination register.
884
4a0bd876
CD		 8852002-03-03 Chris Demetriou <cgd@broadcom.com>
886
887 * mips.igen: Remove whitespace at end of lines.
888
09297648
CD		 8892002-03-02 Chris Demetriou <cgd@broadcom.com>
890
891 * mips.igen (loadstore_ea): New function to do effective
892 address calculations.
893 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
894 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
895 CACHE): Use loadstore_ea to do effective address computations.
896
043b7057
CD		 8972002-03-02 Chris Demetriou <cgd@broadcom.com>
898
899 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
900 * mips.igen (LL, CxC1, MxC1): Likewise.
901
c1e8ada4
CD		 9022002-03-02 Chris Demetriou <cgd@broadcom.com>
903
904 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
905 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
906 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
907 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
908 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
909 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
910 Don't split opcode fields by hand, use the opcode field values
911 provided by igen.
912
3e1dca16
CD		 9132002-03-01 Chris Demetriou <cgd@broadcom.com>
914
915 * mips.igen (do_divu): Fix spacing.
916
917 * mips.igen (do_dsllv): Move to be right before DSLLV,
918 to match the rest of the do_<shift> functions.
919
fff8d27d
CD		 9202002-03-01 Chris Demetriou <cgd@broadcom.com>
921
922 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
923 DSRL32, do_dsrlv): Trace inputs and results.
924
0d3e762b
CD		 9252002-03-01 Chris Demetriou <cgd@broadcom.com>
926
927 * mips.igen (CACHE): Provide instruction-printing string.
928
929 * interp.c (signal_exception): Comment tokens after #endif.
930
eb5fcf93
CD		 9312002-02-28 Chris Demetriou <cgd@broadcom.com>
932
933 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
934 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
935 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
936 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
937 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
938 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
939 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
940 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
941
bb22bd7d
CD		 9422002-02-28 Chris Demetriou <cgd@broadcom.com>
943
944 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
945 instruction-printing string.
946 (LWU): Use '64' as the filter flag.
947
91a177cf
CD		 9482002-02-28 Chris Demetriou <cgd@broadcom.com>
949
950 * mips.igen (SDXC1): Fix instruction-printing string.
951
387f484a
CD		 9522002-02-28 Chris Demetriou <cgd@broadcom.com>
953
954 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
955 filter flags "32,f".
956
3d81f391
CD		 9572002-02-27 Chris Demetriou <cgd@broadcom.com>
958
959 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
960 as the filter flag.
961
af5107af
CD		 9622002-02-27 Chris Demetriou <cgd@broadcom.com>
963
964 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
965 add a comma) so that it more closely match the MIPS ISA
966 documentation opcode partitioning.
967 (PREF): Put useful names on opcode fields, and include
968 instruction-printing string.
969
ca971540
CD		 9702002-02-27 Chris Demetriou <cgd@broadcom.com>
971
972 * mips.igen (check_u64): New function which in the future will
973 check whether 64-bit instructions are usable and signal an
974 exception if not. Currently a no-op.
975 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
976 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
977 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
978 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
979
980 * mips.igen (check_fpu): New function which in the future will
981 check whether FPU instructions are usable and signal an exception
982 if not. Currently a no-op.
983 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
984 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
985 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
986 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
987 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
988 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
989 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
990 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
991
1c47a468
CD		 9922002-02-27 Chris Demetriou <cgd@broadcom.com>
993
994 * mips.igen (do_load_left, do_load_right): Move to be immediately
995 following do_load.
996 (do_store_left, do_store_right): Move to be immediately following
997 do_store.
998
603a98e7
CD		 9992002-02-27 Chris Demetriou <cgd@broadcom.com>
1000
1001 * mips.igen (mipsV): New model name. Also, add it to
1002 all instructions and functions where it is appropriate.
1003
c5d00cc7
CD		 10042002-02-18 Chris Demetriou <cgd@broadcom.com>
1005
1006 * mips.igen: For all functions and instructions, list model
1007 names that support that instruction one per line.
1008
074e9cb8
CD		 10092002-02-11 Chris Demetriou <cgd@broadcom.com>
1010
1011 * mips.igen: Add some additional comments about supported
1012 models, and about which instructions go where.
1013 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1014 order as is used in the rest of the file.
1015
9805e229
CD		 10162002-02-11 Chris Demetriou <cgd@broadcom.com>
1017
1018 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1019 indicating that ALU32_END or ALU64_END are there to check
1020 for overflow.
1021 (DADD): Likewise, but also remove previous comment about
1022 overflow checking.
1023
f701dad2
CD		 10242002-02-10 Chris Demetriou <cgd@broadcom.com>
1025
1026 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1027 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1028 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1029 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1030 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1031 fields (i.e., add and move commas) so that they more closely
1032 match the MIPS ISA documentation opcode partitioning.
1033
10342002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098
CD		 1035
1036 * mips.igen (ADDI): Print immediate value.
1037 (BREAK): Print code.
1038 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1039 (SLL): Print "nop" specially, and don't run the code
1040 that does the shift for the "nop" case.
1041
9e52972e
FF		 10422001-11-17 Fred Fish <fnf@redhat.com>
1043
1044 * sim-main.h (float_operation): Move enum declaration outside
1045 of _sim_cpu struct declaration.
1046
c0efbca4
JB		 10472001-04-12 Jim Blandy <jimb@redhat.com>
1048
1049 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1050 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1051 set of the FCSR.
1052 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1053 PENDING_FILL, and you can get the intended effect gracefully by
1054 calling PENDING_SCHED directly.
1055
fb891446
BE		 10562001-02-23 Ben Elliston <bje@redhat.com>
1057
1058 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1059 already defined elsewhere.
1060
8030f857
BE		 10612001-02-19 Ben Elliston <bje@redhat.com>
1062
1063 * sim-main.h (sim_monitor): Return an int.
1064 * interp.c (sim_monitor): Add return values.
1065 (signal_exception): Handle error conditions from sim_monitor.
1066
56b48a7a
CD		 10672001-02-08 Ben Elliston <bje@redhat.com>
1068
1069 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1070 (store_memory): Likewise, pass cia to sim_core_write*.
1071
d3ee60d9
FCE		 10722000-10-19 Frank Ch. Eigler <fche@redhat.com>
1073
1074 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1075 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1076
071da002
AC		 1077Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1078
1079 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1080 * Makefile.in: Don't delete *.igen when cleaning directory.
1081
a28c02cd
AC		 1082Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1083
1084 * m16.igen (break): Call SignalException not sim_engine_halt.
1085
80ee11fa
AC		 1086Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1087
1088 From Jason Eckhardt:
1089 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1090
673388c0
AC		 1091Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1092
1093 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1094
4c0deff4
NC		 10952000-05-24 Michael Hayes <mhayes@cygnus.com>
1096
1097 * mips.igen (do_dmultx): Fix typo.
1098
eb2d80b4
AC		 1099Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1100
1101 * configure: Regenerated to track ../common/aclocal.m4 changes.
1102
dd37a34b
AC		 1103Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1104
1105 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1106
4c0deff4
NC		 11072000-04-12 Frank Ch. Eigler <fche@redhat.com>
1108
1109 * sim-main.h (GPR_CLEAR): Define macro.
1110
e30db738
AC		 1111Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1112
1113 * interp.c (decode_coproc): Output long using %lx and not %s.
1114
cb7450ea
FCE		 11152000-03-21 Frank Ch. Eigler <fche@redhat.com>
1116
1117 * interp.c (sim_open): Sort & extend dummy memory regions for
1118 --board=jmr3904 for eCos.
1119
a3027dd7
FCE		 11202000-03-02 Frank Ch. Eigler <fche@redhat.com>
1121
1122 * configure: Regenerated.
1123
1124Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1125
1126 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1127 calls, conditional on the simulator being in verbose mode.
1128
dfcd3bfb
JM		 1129Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1130
1131 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1132 cache don't get ReservedInstruction traps.
1133
c2d11a7d
JM		 11341999-11-29 Mark Salter <msalter@cygnus.com>
1135
1136 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1137 to clear status bits in sdisr register. This is how the hardware works.
1138
1139 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1140 being used by cygmon.
1141
4ce44c66
JM		 11421999-11-11 Andrew Haley <aph@cygnus.com>
1143
1144 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1145 instructions.
1146
cff3e48b
JM		 1147Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1148
1149 * mips.igen (MULT): Correct previous mis-applied patch.
1150
d4f3574e
SS		 1151Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1152
1153 * mips.igen (delayslot32): Handle sequence like
1154 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1155 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1156 (MULT): Actually pass the third register...
1157
11581999-09-03 Mark Salter <msalter@cygnus.com>
1159
1160 * interp.c (sim_open): Added more memory aliases for additional
1161 hardware being touched by cygmon on jmr3904 board.
1162
1163Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1164
1165 * configure: Regenerated to track ../common/aclocal.m4 changes.
1166
a0b3c4fd
JM		 1167Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1168
1169 * interp.c (sim_store_register): Handle case where client - GDB -
1170 specifies that a 4 byte register is 8 bytes in size.
1171 (sim_fetch_register): Ditto.
1172
adf40b2e
JM		 11731999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1174
1175 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1176 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1177 (idt_monitor_base): Base address for IDT monitor traps.
1178 (pmon_monitor_base): Ditto for PMON.
1179 (lsipmon_monitor_base): Ditto for LSI PMON.
1180 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1181 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1182 (sim_firmware_command): New function.
1183 (mips_option_handler): Call it for OPTION_FIRMWARE.
1184 (sim_open): Allocate memory for idt_monitor region. If "--board"
1185 option was given, add no monitor by default. Add BREAK hooks only if
1186 monitors are also there.
1187
43e526b9
JM		 1188Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1189
1190 * interp.c (sim_monitor): Flush output before reading input.
1191
1192Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1193
1194 * tconfig.in (SIM_HANDLES_LMA): Always define.
1195
1196Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1197
1198 From Mark Salter <msalter@cygnus.com>:
1199 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1200 (sim_open): Add setup for BSP board.
1201
9846de1b
JM		 1202Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1203
1204 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1205 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1206 them as unimplemented.
1207
cd0fc7c3
SS		 12081999-05-08 Felix Lee <flee@cygnus.com>
1209
1210 * configure: Regenerated to track ../common/aclocal.m4 changes.
1211
7a292a7a
SS		 12121999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1213
1214 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1215
1216Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1217
1218 * configure.in: Any mips64vr5*-*-* target should have
1219 -DTARGET_ENABLE_FR=1.
1220 (default_endian): Any mips64vr*el-*-* target should default to
1221 LITTLE_ENDIAN.
1222 * configure: Re-generate.
1223
12241999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1225
1226 * mips.igen (ldl): Extend from _16_, not 32.
1227
1228Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1229
1230 * interp.c (sim_store_register): Force registers written to by GDB
1231 into an un-interpreted state.
1232
c906108c
SS		 12331999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1234
1235 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1236 CPU, start periodic background I/O polls.
1237 (tx3904sio_poll): New function: periodic I/O poller.
1238
12391998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1240
1241 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
1242
1243Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1244
1245 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1246 case statement.
1247
12481998-12-29 Frank Ch. Eigler <fche@cygnus.com>
1249
1250 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
1251 (load_word): Call SIM_CORE_SIGNAL hook on error.
1252 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1253 starting. For exception dispatching, pass PC instead of NULL_CIA.
1254 (decode_coproc): Use COP0_BADVADDR to store faulting address.
1255 * sim-main.h (COP0_BADVADDR): Define.
1256 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1257 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
1258 (_sim_cpu): Add exc_* fields to store register value snapshots.
1259 * mips.igen (*): Replace memory-related SignalException* calls
1260 with references to SIM_CORE_SIGNAL hook.
1261
1262 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1263 fix.
1264 * sim-main.c (*): Minor warning cleanups.
1265
12661998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1267
1268 * m16.igen (DADDIU5): Correct type-o.
1269
1270Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1271
1272 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1273 variables.
1274
1275Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1276
1277 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1278 to include path.
1279 (interp.o): Add dependency on itable.h
1280 (oengine.c, gencode): Delete remaining references.
1281 (BUILT_SRC_FROM_GEN): Clean up.
1282
12831998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
1284
1285 * vr4run.c: New.
1286 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1287 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1288 tmp-run-hack) : New.
1289 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
1290 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
1291 Drop the "64" qualifier to get the HACK generator working.
1292 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1293 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1294 qualifier to get the hack generator working.
1295 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1296 (DSLL): Use do_dsll.
1297 (DSLLV): Use do_dsllv.
1298 (DSRA): Use do_dsra.
1299 (DSRL): Use do_dsrl.
1300 (DSRLV): Use do_dsrlv.
1301 (BC1): Move *vr4100 to get the HACK generator working.
1302 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
1303 get the HACK generator working.
1304 (MACC) Rename to get the HACK generator working.
1305 (DMACC,MACCS,DMACCS): Add the 64.
1306
13071998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1308
1309 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1310 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1311
13121998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1313
1314 * mips/interp.c (DEBUG): Cleanups.
1315
13161998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1317
1318 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1319 (tx3904sio_tickle): fflush after a stdout character output.
1320
13211998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1322
1323 * interp.c (sim_close): Uninstall modules.
1324
1325Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1326
1327 * sim-main.h, interp.c (sim_monitor): Change to global
1328 function.
1329
1330Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1331
1332 * configure.in (vr4100): Only include vr4100 instructions in
1333 simulator.
1334 * configure: Re-generate.
1335 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1336
1337Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1338
1339 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1340 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1341 true alternative.
1342
1343 * configure.in (sim_default_gen, sim_use_gen): Replace with
1344 sim_gen.
1345 (--enable-sim-igen): Delete config option. Always using IGEN.
1346 * configure: Re-generate.
1347
1348 * Makefile.in (gencode): Kill, kill, kill.
1349 * gencode.c: Ditto.
1350
1351Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1352
1353 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1354 bit mips16 igen simulator.
1355 * configure: Re-generate.
1356
1357 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1358 as part of vr4100 ISA.
1359 * vr.igen: Mark all instructions as 64 bit only.
1360
1361Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1362
1363 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1364 Pacify GCC.
1365
1366Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1367
1368 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1369 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1370 * configure: Re-generate.
1371
1372 * m16.igen (BREAK): Define breakpoint instruction.
1373 (JALX32): Mark instruction as mips16 and not r3900.
1374 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1375
1376 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1377
1378Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1379
1380 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1381 insn as a debug breakpoint.
1382
1383 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1384 pending.slot_size.
1385 (PENDING_SCHED): Clean up trace statement.
1386 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1387 (PENDING_FILL): Delay write by only one cycle.
1388 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1389
1390 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1391 of pending writes.
1392 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1393 32 & 64.
1394 (pending_tick): Move incrementing of index to FOR statement.
1395 (pending_tick): Only update PENDING_OUT after a write has occured.
1396
1397 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1398 build simulator.
1399 * configure: Re-generate.
1400
1401 * interp.c (sim_engine_run OLD): Delete explicit call to
1402 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1403
1404Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1405
1406 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1407 interrupt level number to match changed SignalExceptionInterrupt
1408 macro.
1409
1410Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1411
1412 * interp.c: #include "itable.h" if WITH_IGEN.
1413 (get_insn_name): New function.
1414 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1415 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1416
1417Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1418
1419 * configure: Rebuilt to inhale new common/aclocal.m4.
1420
1421Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1422
1423 * dv-tx3904sio.c: Include sim-assert.h.
1424
1425Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1426
1427 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1428 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1429 Reorganize target-specific sim-hardware checks.
1430 * configure: rebuilt.
1431 * interp.c (sim_open): For tx39 target boards, set
1432 OPERATING_ENVIRONMENT, add tx3904sio devices.
1433 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1434 ROM executables. Install dv-sockser into sim-modules list.
1435
1436 * dv-tx3904irc.c: Compiler warning clean-up.
1437 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1438 frequent hw-trace messages.
1439
1440Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1441
1442 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1443
1444Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1445
1446 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1447
1448 * vr.igen: New file.
1449 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1450 * mips.igen: Define vr4100 model. Include vr.igen.
1451Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1452
1453 * mips.igen (check_mf_hilo): Correct check.
1454
1455Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1456
1457 * sim-main.h (interrupt_event): Add prototype.
1458
1459 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1460 register_ptr, register_value.
1461 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1462
1463 * sim-main.h (tracefh): Make extern.
1464
1465Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1466
1467 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1468 Reduce unnecessarily high timer event frequency.
1469 * dv-tx3904cpu.c: Ditto for interrupt event.
1470
1471Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1472
1473 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1474 to allay warnings.
1475 (interrupt_event): Made non-static.
1476
1477 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1478 interchange of configuration values for external vs. internal
1479 clock dividers.
1480
1481Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1482
1483 * mips.igen (BREAK): Moved code to here for
1484 simulator-reserved break instructions.
1485 * gencode.c (build_instruction): Ditto.
1486 * interp.c (signal_exception): Code moved from here. Non-
1487 reserved instructions now use exception vector, rather
1488 than halting sim.
1489 * sim-main.h: Moved magic constants to here.
1490
1491Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1492
1493 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1494 register upon non-zero interrupt event level, clear upon zero
1495 event value.
1496 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1497 by passing zero event value.
1498 (*_io_{read,write}_buffer): Endianness fixes.
1499 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1500 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1501
1502 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1503 serial I/O and timer module at base address 0xFFFF0000.
1504
1505Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1506
1507 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1508 and BigEndianCPU.
1509
1510Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1511
1512 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1513 parts.
1514 * configure: Update.
1515
1516Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1517
1518 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1519 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1520 * configure.in: Include tx3904tmr in hw_device list.
1521 * configure: Rebuilt.
1522 * interp.c (sim_open): Instantiate three timer instances.
1523 Fix address typo of tx3904irc instance.
1524
1525Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1526
1527 * interp.c (signal_exception): SystemCall exception now uses
1528 the exception vector.
1529
1530Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1531
1532 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1533 to allay warnings.
1534
1535Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1536
1537 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1538
1539Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1540
1541 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1542
1543 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1544 sim-main.h. Declare a struct hw_descriptor instead of struct
1545 hw_device_descriptor.
1546
1547Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1548
1549 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1550 right bits and then re-align left hand bytes to correct byte
1551 lanes. Fix incorrect computation in do_store_left when loading
1552 bytes from second word.
1553
1554Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1555
1556 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1557 * interp.c (sim_open): Only create a device tree when HW is
1558 enabled.
1559
1560 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1561 * interp.c (signal_exception): Ditto.
1562
1563Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1564
1565 * gencode.c: Mark BEGEZALL as LIKELY.
1566
1567Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1568
1569 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1570 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1571
1572Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1573
1574 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1575 modules. Recognize TX39 target with "mips*tx39" pattern.
1576 * configure: Rebuilt.
1577 * sim-main.h (*): Added many macros defining bits in
1578 TX39 control registers.
1579 (SignalInterrupt): Send actual PC instead of NULL.
1580 (SignalNMIReset): New exception type.
1581 * interp.c (board): New variable for future use to identify
1582 a particular board being simulated.
1583 (mips_option_handler,mips_options): Added "--board" option.
1584 (interrupt_event): Send actual PC.
1585 (sim_open): Make memory layout conditional on board setting.
1586 (signal_exception): Initial implementation of hardware interrupt
1587 handling. Accept another break instruction variant for simulator
1588 exit.
1589 (decode_coproc): Implement RFE instruction for TX39.
1590 (mips.igen): Decode RFE instruction as such.
1591 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1592 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1593 bbegin to implement memory map.
1594 * dv-tx3904cpu.c: New file.
1595 * dv-tx3904irc.c: New file.
1596
1597Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1598
1599 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1600
1601Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1602
1603 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1604 with calls to check_div_hilo.
1605
1606Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1607
1608 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1609 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1610 Add special r3900 version of do_mult_hilo.
1611 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1612 with calls to check_mult_hilo.
1613 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1614 with calls to check_div_hilo.
1615
1616Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1617
1618 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1619 Document a replacement.
1620
1621Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1622
1623 * interp.c (sim_monitor): Make mon_printf work.
1624
1625Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1626
1627 * sim-main.h (INSN_NAME): New arg `cpu'.
1628
1629Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1630
1631 * configure: Regenerated to track ../common/aclocal.m4 changes.
1632
1633Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1634
1635 * configure: Regenerated to track ../common/aclocal.m4 changes.
1636 * config.in: Ditto.
1637
1638Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1639
1640 * acconfig.h: New file.
1641 * configure.in: Reverted change of Apr 24; use sinclude again.
1642
1643Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1644
1645 * configure: Regenerated to track ../common/aclocal.m4 changes.
1646 * config.in: Ditto.
1647
1648Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1649
1650 * configure.in: Don't call sinclude.
1651
1652Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1653
1654 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1655
1656Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1657
1658 * mips.igen (ERET): Implement.
1659
1660 * interp.c (decode_coproc): Return sign-extended EPC.
1661
1662 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1663
1664 * interp.c (signal_exception): Do not ignore Trap.
1665 (signal_exception): On TRAP, restart at exception address.
1666 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1667 (signal_exception): Update.
1668 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1669 so that TRAP instructions are caught.
1670
1671Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1672
1673 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1674 contains HI/LO access history.
1675 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1676 (HIACCESS, LOACCESS): Delete, replace with
1677 (HIHISTORY, LOHISTORY): New macros.
1678 (CHECKHILO): Delete all, moved to mips.igen
1679
1680 * gencode.c (build_instruction): Do not generate checks for
1681 correct HI/LO register usage.
1682
1683 * interp.c (old_engine_run): Delete checks for correct HI/LO
1684 register usage.
1685
1686 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1687 check_mf_cycles): New functions.
1688 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1689 do_divu, domultx, do_mult, do_multu): Use.
1690
1691 * tx.igen ("madd", "maddu"): Use.
1692
1693Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1694
1695 * mips.igen (DSRAV): Use function do_dsrav.
1696 (SRAV): Use new function do_srav.
1697
1698 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1699 (B): Sign extend 11 bit immediate.
1700 (EXT-B*): Shift 16 bit immediate left by 1.
1701 (ADDIU*): Don't sign extend immediate value.
1702
1703Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1704
1705 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1706
1707 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1708 functions.
1709
1710 * mips.igen (delayslot32, nullify_next_insn): New functions.
1711 (m16.igen): Always include.
1712 (do_*): Add more tracing.
1713
1714 * m16.igen (delayslot16): Add NIA argument, could be called by a
1715 32 bit MIPS16 instruction.
1716
1717 * interp.c (ifetch16): Move function from here.
1718 * sim-main.c (ifetch16): To here.
1719
1720 * sim-main.c (ifetch16, ifetch32): Update to match current
1721 implementations of LH, LW.
1722 (signal_exception): Don't print out incorrect hex value of illegal
1723 instruction.
1724
1725Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1726
1727 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1728 instruction.
1729
1730 * m16.igen: Implement MIPS16 instructions.
1731
1732 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1733 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1734 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1735 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1736 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1737 bodies of corresponding code from 32 bit insn to these. Also used
1738 by MIPS16 versions of functions.
1739
1740 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1741 (IMEM16): Drop NR argument from macro.
1742
1743Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1744
1745 * Makefile.in (SIM_OBJS): Add sim-main.o.
1746
1747 * sim-main.h (address_translation, load_memory, store_memory,
1748 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1749 as INLINE_SIM_MAIN.
1750 (pr_addr, pr_uword64): Declare.
1751 (sim-main.c): Include when H_REVEALS_MODULE_P.
1752
1753 * interp.c (address_translation, load_memory, store_memory,
1754 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1755 from here.
1756 * sim-main.c: To here. Fix compilation problems.
1757
1758 * configure.in: Enable inlining.
1759 * configure: Re-config.
1760
1761Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1762
1763 * configure: Regenerated to track ../common/aclocal.m4 changes.
1764
1765Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1766
1767 * mips.igen: Include tx.igen.
1768 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1769 * tx.igen: New file, contains MADD and MADDU.
1770
1771 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1772 the hardwired constant `7'.
1773 (store_memory): Ditto.
1774 (LOADDRMASK): Move definition to sim-main.h.
1775
1776 mips.igen (MTC0): Enable for r3900.
1777 (ADDU): Add trace.
1778
1779 mips.igen (do_load_byte): Delete.
1780 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1781 do_store_right): New functions.
1782 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1783
1784 configure.in: Let the tx39 use igen again.
1785 configure: Update.
1786
1787Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1788
1789 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1790 not an address sized quantity. Return zero for cache sizes.
1791
1792Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1793
1794 * mips.igen (r3900): r3900 does not support 64 bit integer
1795 operations.
1796
1797Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1798
1799 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1800 than igen one.
1801 * configure : Rebuild.
1802
1803Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1804
1805 * configure: Regenerated to track ../common/aclocal.m4 changes.
1806
1807Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1808
1809 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1810
1811Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1812
1813 * configure: Regenerated to track ../common/aclocal.m4 changes.
1814 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1815
1816Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1817
1818 * configure: Regenerated to track ../common/aclocal.m4 changes.
1819
1820Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1821
1822 * interp.c (Max, Min): Comment out functions. Not yet used.
1823
1824Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1825
1826 * configure: Regenerated to track ../common/aclocal.m4 changes.
1827
1828Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1829
1830 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1831 configurable settings for stand-alone simulator.
1832
1833 * configure.in: Added X11 search, just in case.
1834
1835 * configure: Regenerated.
1836
1837Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1838
1839 * interp.c (sim_write, sim_read, load_memory, store_memory):
1840 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1841
1842Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1843
1844 * sim-main.h (GETFCC): Return an unsigned value.
1845
1846Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1847
1848 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1849 (DADD): Result destination is RD not RT.
1850
1851Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1852
1853 * sim-main.h (HIACCESS, LOACCESS): Always define.
1854
1855 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1856
1857 * interp.c (sim_info): Delete.
1858
1859Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1860
1861 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1862 (mips_option_handler): New argument `cpu'.
1863 (sim_open): Update call to sim_add_option_table.
1864
1865Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1866
1867 * mips.igen (CxC1): Add tracing.
1868
1869Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1870
1871 * sim-main.h (Max, Min): Declare.
1872
1873 * interp.c (Max, Min): New functions.
1874
1875 * mips.igen (BC1): Add tracing.
1876
1877Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1878
1879 * interp.c Added memory map for stack in vr4100
1880
1881Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1882
1883 * interp.c (load_memory): Add missing "break"'s.
1884
1885Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1886
1887 * interp.c (sim_store_register, sim_fetch_register): Pass in
1888 length parameter. Return -1.
1889
1890Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1891
1892 * interp.c: Added hardware init hook, fixed warnings.
1893
1894Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1895
1896 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1897
1898Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1899
1900 * interp.c (ifetch16): New function.
1901
1902 * sim-main.h (IMEM32): Rename IMEM.
1903 (IMEM16_IMMED): Define.
1904 (IMEM16): Define.
1905 (DELAY_SLOT): Update.
1906
1907 * m16run.c (sim_engine_run): New file.
1908
1909 * m16.igen: All instructions except LB.
1910 (LB): Call do_load_byte.
1911 * mips.igen (do_load_byte): New function.
1912 (LB): Call do_load_byte.
1913
1914 * mips.igen: Move spec for insn bit size and high bit from here.
1915 * Makefile.in (tmp-igen, tmp-m16): To here.
1916
1917 * m16.dc: New file, decode mips16 instructions.
1918
1919 * Makefile.in (SIM_NO_ALL): Define.
1920 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1921
1922Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1923
1924 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1925 point unit to 32 bit registers.
1926 * configure: Re-generate.
1927
1928Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1929
1930 * configure.in (sim_use_gen): Make IGEN the default simulator
1931 generator for generic 32 and 64 bit mips targets.
1932 * configure: Re-generate.
1933
1934Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1935
1936 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1937 bitsize.
1938
1939 * interp.c (sim_fetch_register, sim_store_register): Read/write
1940 FGR from correct location.
1941 (sim_open): Set size of FGR's according to
1942 WITH_TARGET_FLOATING_POINT_BITSIZE.
1943
1944 * sim-main.h (FGR): Store floating point registers in a separate
1945 array.
1946
1947Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1948
1949 * configure: Regenerated to track ../common/aclocal.m4 changes.
1950
1951Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1952
1953 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1954
1955 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1956
1957 * interp.c (pending_tick): New function. Deliver pending writes.
1958
1959 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1960 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1961 it can handle mixed sized quantites and single bits.
1962
1963Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1964
1965 * interp.c (oengine.h): Do not include when building with IGEN.
1966 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1967 (sim_info): Ditto for PROCESSOR_64BIT.
1968 (sim_monitor): Replace ut_reg with unsigned_word.
1969 (*): Ditto for t_reg.
1970 (LOADDRMASK): Define.
1971 (sim_open): Remove defunct check that host FP is IEEE compliant,
1972 using software to emulate floating point.
1973 (value_fpr, ...): Always compile, was conditional on HASFPU.
1974
1975Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1976
1977 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1978 size.
1979
1980 * interp.c (SD, CPU): Define.
1981 (mips_option_handler): Set flags in each CPU.
1982 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1983 (sim_close): Do not clear STATE, deleted anyway.
1984 (sim_write, sim_read): Assume CPU zero's vm should be used for
1985 data transfers.
1986 (sim_create_inferior): Set the PC for all processors.
1987 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1988 argument.
1989 (mips16_entry): Pass correct nr of args to store_word, load_word.
1990 (ColdReset): Cold reset all cpu's.
1991 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1992 (sim_monitor, load_memory, store_memory, signal_exception): Use
1993 `CPU' instead of STATE_CPU.
1994
1995
1996 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1997 SD or CPU_.
1998
1999 * sim-main.h (signal_exception): Add sim_cpu arg.
2000 (SignalException*): Pass both SD and CPU to signal_exception.
2001 * interp.c (signal_exception): Update.
2002
2003 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2004 Ditto
2005 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2006 address_translation): Ditto
2007 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
2008
2009Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2010
2011 * configure: Regenerated to track ../common/aclocal.m4 changes.
2012
2013Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2014
2015 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2016
2017 * mips.igen (model): Map processor names onto BFD name.
2018
2019 * sim-main.h (CPU_CIA): Delete.
2020 (SET_CIA, GET_CIA): Define
2021
2022Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2023
2024 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2025 regiser.
2026
2027 * configure.in (default_endian): Configure a big-endian simulator
2028 by default.
2029 * configure: Re-generate.
2030
2031Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2032
2033 * configure: Regenerated to track ../common/aclocal.m4 changes.
2034
2035Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2036
2037 * interp.c (sim_monitor): Handle Densan monitor outbyte
2038 and inbyte functions.
2039
20401997-12-29 Felix Lee <flee@cygnus.com>
2041
2042 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2043
2044Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2045
2046 * Makefile.in (tmp-igen): Arrange for $zero to always be
2047 reset to zero after every instruction.
2048
2049Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2050
2051 * configure: Regenerated to track ../common/aclocal.m4 changes.
2052 * config.in: Ditto.
2053
2054Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2055
2056 * mips.igen (MSUB): Fix to work like MADD.
2057 * gencode.c (MSUB): Similarly.
2058
2059Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2060
2061 * configure: Regenerated to track ../common/aclocal.m4 changes.
2062
2063Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2064
2065 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2066
2067Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2068
2069 * sim-main.h (sim-fpu.h): Include.
2070
2071 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2072 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2073 using host independant sim_fpu module.
2074
2075Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2076
2077 * interp.c (signal_exception): Report internal errors with SIGABRT
2078 not SIGQUIT.
2079
2080 * sim-main.h (C0_CONFIG): New register.
2081 (signal.h): No longer include.
2082
2083 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2084
2085Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2086
2087 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2088
2089Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2090
2091 * mips.igen: Tag vr5000 instructions.
2092 (ANDI): Was missing mipsIV model, fix assembler syntax.
2093 (do_c_cond_fmt): New function.
2094 (C.cond.fmt): Handle mips I-III which do not support CC field
2095 separatly.
2096 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2097 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2098 in IV3.2 spec.
2099 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2100 vr5000 which saves LO in a GPR separatly.
2101
2102 * configure.in (enable-sim-igen): For vr5000, select vr5000
2103 specific instructions.
2104 * configure: Re-generate.
2105
2106Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2107
2108 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2109
2110 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2111 fmt_uninterpreted_64 bit cases to switch. Convert to
2112 fmt_formatted,
2113
2114 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2115
2116 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2117 as specified in IV3.2 spec.
2118 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2119
2120Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2121
2122 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2123 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2124 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2125 PENDING_FILL versions of instructions. Simplify.
2126 (X): New function.
2127 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2128 instructions.
2129 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2130 a signed value.
2131 (MTHI, MFHI): Disable code checking HI-LO.
2132
2133 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2134 global.
2135 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2136
2137Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2138
2139 * gencode.c (build_mips16_operands): Replace IPC with cia.
2140
2141 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2142 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2143 IPC to `cia'.
2144 (UndefinedResult): Replace function with macro/function
2145 combination.
2146 (sim_engine_run): Don't save PC in IPC.
2147
2148 * sim-main.h (IPC): Delete.
2149
2150
2151 * interp.c (signal_exception, store_word, load_word,
2152 address_translation, load_memory, store_memory, cache_op,
2153 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2154 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2155 current instruction address - cia - argument.
2156 (sim_read, sim_write): Call address_translation directly.
2157 (sim_engine_run): Rename variable vaddr to cia.
2158 (signal_exception): Pass cia to sim_monitor
2159
2160 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2161 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2162 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2163
2164 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2165 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2166 SIM_ASSERT.
2167
2168 * interp.c (signal_exception): Pass restart address to
2169 sim_engine_restart.
2170
2171 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2172 idecode.o): Add dependency.
2173
2174 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2175 Delete definitions
2176 (DELAY_SLOT): Update NIA not PC with branch address.
2177 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2178
2179 * mips.igen: Use CIA not PC in branch calculations.
2180 (illegal): Call SignalException.
2181 (BEQ, ADDIU): Fix assembler.
2182
2183Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2184
2185 * m16.igen (JALX): Was missing.
2186
2187 * configure.in (enable-sim-igen): New configuration option.
2188 * configure: Re-generate.
2189
2190 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2191
2192 * interp.c (load_memory, store_memory): Delete parameter RAW.
2193 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2194 bypassing {load,store}_memory.
2195
2196 * sim-main.h (ByteSwapMem): Delete definition.
2197
2198 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2199
2200 * interp.c (sim_do_command, sim_commands): Delete mips specific
2201 commands. Handled by module sim-options.
2202
2203 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2204 (WITH_MODULO_MEMORY): Define.
2205
2206 * interp.c (sim_info): Delete code printing memory size.
2207
2208 * interp.c (mips_size): Nee sim_size, delete function.
2209 (power2): Delete.
2210 (monitor, monitor_base, monitor_size): Delete global variables.
2211 (sim_open, sim_close): Delete code creating monitor and other
2212 memory regions. Use sim-memopts module, via sim_do_commandf, to
2213 manage memory regions.
2214 (load_memory, store_memory): Use sim-core for memory model.
2215
2216 * interp.c (address_translation): Delete all memory map code
2217 except line forcing 32 bit addresses.
2218
2219Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2220
2221 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2222 trace options.
2223
2224 * interp.c (logfh, logfile): Delete globals.
2225 (sim_open, sim_close): Delete code opening & closing log file.
2226 (mips_option_handler): Delete -l and -n options.
2227 (OPTION mips_options): Ditto.
2228
2229 * interp.c (OPTION mips_options): Rename option trace to dinero.
2230 (mips_option_handler): Update.
2231
2232Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2233
2234 * interp.c (fetch_str): New function.
2235 (sim_monitor): Rewrite using sim_read & sim_write.
2236 (sim_open): Check magic number.
2237 (sim_open): Write monitor vectors into memory using sim_write.
2238 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2239 (sim_read, sim_write): Simplify - transfer data one byte at a
2240 time.
2241 (load_memory, store_memory): Clarify meaning of parameter RAW.
2242
2243 * sim-main.h (isHOST): Defete definition.
2244 (isTARGET): Mark as depreciated.
2245 (address_translation): Delete parameter HOST.
2246
2247 * interp.c (address_translation): Delete parameter HOST.
2248
2249Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2250
2251 * mips.igen:
2252
2253 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2254 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2255
2256Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2257
2258 * mips.igen: Add model filter field to records.
2259
2260Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2261
2262 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
2263
2264 interp.c (sim_engine_run): Do not compile function sim_engine_run
2265 when WITH_IGEN == 1.
2266
2267 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2268 target architecture.
2269
2270 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2271 igen. Replace with configuration variables sim_igen_flags /
2272 sim_m16_flags.
2273
2274 * m16.igen: New file. Copy mips16 insns here.
2275 * mips.igen: From here.
2276
2277Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2278
2279 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2280 to top.
2281 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2282
2283Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2284
2285 * gencode.c (build_instruction): Follow sim_write's lead in using
2286 BigEndianMem instead of !ByteSwapMem.
2287
2288Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2289
2290 * configure.in (sim_gen): Dependent on target, select type of
2291 generator. Always select old style generator.
2292
2293 configure: Re-generate.
2294
2295 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2296 targets.
2297 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2298 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2299 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2300 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2301 SIM_@sim_gen@_*, set by autoconf.
2302
2303Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2304
2305 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2306
2307 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2308 CURRENT_FLOATING_POINT instead.
2309
2310 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2311 (address_translation): Raise exception InstructionFetch when
2312 translation fails and isINSTRUCTION.
2313
2314 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2315 sim_engine_run): Change type of of vaddr and paddr to
2316 address_word.
2317 (address_translation, prefetch, load_memory, store_memory,
2318 cache_op): Change type of vAddr and pAddr to address_word.
2319
2320 * gencode.c (build_instruction): Change type of vaddr and paddr to
2321 address_word.
2322
2323Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2324
2325 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2326 macro to obtain result of ALU op.
2327
2328Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2329
2330 * interp.c (sim_info): Call profile_print.
2331
2332Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2333
2334 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2335
2336 * sim-main.h (WITH_PROFILE): Do not define, defined in
2337 common/sim-config.h. Use sim-profile module.
2338 (simPROFILE): Delete defintion.
2339
2340 * interp.c (PROFILE): Delete definition.
2341 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2342 (sim_close): Delete code writing profile histogram.
2343 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2344 Delete.
2345 (sim_engine_run): Delete code profiling the PC.
2346
2347Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2348
2349 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2350
2351 * interp.c (sim_monitor): Make register pointers of type
2352 unsigned_word*.
2353
2354 * sim-main.h: Make registers of type unsigned_word not
2355 signed_word.
2356
2357Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2358
2359 * interp.c (sync_operation): Rename from SyncOperation, make
2360 global, add SD argument.
2361 (prefetch): Rename from Prefetch, make global, add SD argument.
2362 (decode_coproc): Make global.
2363
2364 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2365
2366 * gencode.c (build_instruction): Generate DecodeCoproc not
2367 decode_coproc calls.
2368
2369 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2370 (SizeFGR): Move to sim-main.h
2371 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2372 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2373 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2374 sim-main.h.
2375 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2376 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2377 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2378 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2379 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2380 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2381
2382 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2383 exception.
2384 (sim-alu.h): Include.
2385 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2386 (sim_cia): Typedef to instruction_address.
2387
2388Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2389
2390 * Makefile.in (interp.o): Rename generated file engine.c to
2391 oengine.c.
2392
2393 * interp.c: Update.
2394
2395Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2396
2397 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2398
2399Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2400
2401 * gencode.c (build_instruction): For "FPSQRT", output correct
2402 number of arguments to Recip.
2403
2404Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2405
2406 * Makefile.in (interp.o): Depends on sim-main.h
2407
2408 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2409
2410 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2411 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2412 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2413 STATE, DSSTATE): Define
2414 (GPR, FGRIDX, ..): Define.
2415
2416 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2417 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2418 (GPR, FGRIDX, ...): Delete macros.
2419
2420 * interp.c: Update names to match defines from sim-main.h
2421
2422Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2423
2424 * interp.c (sim_monitor): Add SD argument.
2425 (sim_warning): Delete. Replace calls with calls to
2426 sim_io_eprintf.
2427 (sim_error): Delete. Replace calls with sim_io_error.
2428 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2429 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2430 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2431 argument.
2432 (mips_size): Rename from sim_size. Add SD argument.
2433
2434 * interp.c (simulator): Delete global variable.
2435 (callback): Delete global variable.
2436 (mips_option_handler, sim_open, sim_write, sim_read,
2437 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2438 sim_size,sim_monitor): Use sim_io_* not callback->*.
2439 (sim_open): ZALLOC simulator struct.
2440 (PROFILE): Do not define.
2441
2442Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2443
2444 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2445 support.h with corresponding code.
2446
2447 * sim-main.h (word64, uword64), support.h: Move definition to
2448 sim-main.h.
2449 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2450
2451 * support.h: Delete
2452 * Makefile.in: Update dependencies
2453 * interp.c: Do not include.
2454
2455Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2456
2457 * interp.c (address_translation, load_memory, store_memory,
2458 cache_op): Rename to from AddressTranslation et.al., make global,
2459 add SD argument
2460
2461 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2462 CacheOp): Define.
2463
2464 * interp.c (SignalException): Rename to signal_exception, make
2465 global.
2466
2467 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2468
2469 * sim-main.h (SignalException, SignalExceptionInterrupt,
2470 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2471 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2472 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2473 Define.
2474
2475 * interp.c, support.h: Use.
2476
2477Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2478
2479 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2480 to value_fpr / store_fpr. Add SD argument.
2481 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2482 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2483
2484 * sim-main.h (ValueFPR, StoreFPR): Define.
2485
2486Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2487
2488 * interp.c (sim_engine_run): Check consistency between configure
2489 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2490 and HASFPU.
2491
2492 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2493 (mips_fpu): Configure WITH_FLOATING_POINT.
2494 (mips_endian): Configure WITH_TARGET_ENDIAN.
2495 * configure: Update.
2496
2497Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2498
2499 * configure: Regenerated to track ../common/aclocal.m4 changes.
2500
2501Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2502
2503 * configure: Regenerated.
2504
2505Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2506
2507 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2508
2509Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2510
2511 * gencode.c (print_igen_insn_models): Assume certain architectures
2512 include all mips* instructions.
2513 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2514 instruction.
2515
2516 * Makefile.in (tmp.igen): Add target. Generate igen input from
2517 gencode file.
2518
2519 * gencode.c (FEATURE_IGEN): Define.
2520 (main): Add --igen option. Generate output in igen format.
2521 (process_instructions): Format output according to igen option.
2522 (print_igen_insn_format): New function.
2523 (print_igen_insn_models): New function.
2524 (process_instructions): Only issue warnings and ignore
2525 instructions when no FEATURE_IGEN.
2526
2527Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2528
2529 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2530 MIPS targets.
2531
2532Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2533
2534 * configure: Regenerated to track ../common/aclocal.m4 changes.
2535
2536Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2537
2538 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2539 SIM_RESERVED_BITS): Delete, moved to common.
2540 (SIM_EXTRA_CFLAGS): Update.
2541
2542Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2543
2544 * configure.in: Configure non-strict memory alignment.
2545 * configure: Regenerated to track ../common/aclocal.m4 changes.
2546
2547Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2548
2549 * configure: Regenerated to track ../common/aclocal.m4 changes.
2550
2551Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2552
2553 * gencode.c (SDBBP,DERET): Added (3900) insns.
2554 (RFE): Turn on for 3900.
2555 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2556 (dsstate): Made global.
2557 (SUBTARGET_R3900): Added.
2558 (CANCELDELAYSLOT): New.
2559 (SignalException): Ignore SystemCall rather than ignore and
2560 terminate. Add DebugBreakPoint handling.
2561 (decode_coproc): New insns RFE, DERET; and new registers Debug
2562 and DEPC protected by SUBTARGET_R3900.
2563 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2564 bits explicitly.
2565 * Makefile.in,configure.in: Add mips subtarget option.
2566 * configure: Update.
2567
2568Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2569
2570 * gencode.c: Add r3900 (tx39).
2571
2572
2573Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2574
2575 * gencode.c (build_instruction): Don't need to subtract 4 for
2576 JALR, just 2.
2577
2578Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2579
2580 * interp.c: Correct some HASFPU problems.
2581
2582Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2583
2584 * configure: Regenerated to track ../common/aclocal.m4 changes.
2585
2586Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2587
2588 * interp.c (mips_options): Fix samples option short form, should
2589 be `x'.
2590
2591Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2592
2593 * interp.c (sim_info): Enable info code. Was just returning.
2594
2595Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2596
2597 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2598 MFC0.
2599
2600Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2601
2602 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2603 constants.
2604 (build_instruction): Ditto for LL.
2605
2606Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2607
2608 * configure: Regenerated to track ../common/aclocal.m4 changes.
2609
2610Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2611
2612 * configure: Regenerated to track ../common/aclocal.m4 changes.
2613 * config.in: Ditto.
2614
2615Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2616
2617 * interp.c (sim_open): Add call to sim_analyze_program, update
2618 call to sim_config.
2619
2620Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2621
2622 * interp.c (sim_kill): Delete.
2623 (sim_create_inferior): Add ABFD argument. Set PC from same.
2624 (sim_load): Move code initializing trap handlers from here.
2625 (sim_open): To here.
2626 (sim_load): Delete, use sim-hload.c.
2627
2628 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2629
2630Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2631
2632 * configure: Regenerated to track ../common/aclocal.m4 changes.
2633 * config.in: Ditto.
2634
2635Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2636
2637 * interp.c (sim_open): Add ABFD argument.
2638 (sim_load): Move call to sim_config from here.
2639 (sim_open): To here. Check return status.
2640
2641Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2642
2643 * gencode.c (build_instruction): Two arg MADD should
2644 not assign result to $0.
2645
2646Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2647
2648 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2649 * sim/mips/configure.in: Regenerate.
2650
2651Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2652
2653 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2654 signed8, unsigned8 et.al. types.
2655
2656 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2657 hosts when selecting subreg.
2658
2659Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2660
2661 * interp.c (sim_engine_run): Reset the ZERO register to zero
2662 regardless of FEATURE_WARN_ZERO.
2663 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2664
2665Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2666
2667 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2668 (SignalException): For BreakPoints ignore any mode bits and just
2669 save the PC.
2670 (SignalException): Always set the CAUSE register.
2671
2672Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2673
2674 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2675 exception has been taken.
2676
2677 * interp.c: Implement the ERET and mt/f sr instructions.
2678
2679Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2680
2681 * interp.c (SignalException): Don't bother restarting an
2682 interrupt.
2683
2684Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2685
2686 * interp.c (SignalException): Really take an interrupt.
2687 (interrupt_event): Only deliver interrupts when enabled.
2688
2689Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2690
2691 * interp.c (sim_info): Only print info when verbose.
2692 (sim_info) Use sim_io_printf for output.
2693
2694Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2695
2696 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2697 mips architectures.
2698
2699Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2700
2701 * interp.c (sim_do_command): Check for common commands if a
2702 simulator specific command fails.
2703
2704Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2705
2706 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2707 and simBE when DEBUG is defined.
2708
2709Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2710
2711 * interp.c (interrupt_event): New function. Pass exception event
2712 onto exception handler.
2713
2714 * configure.in: Check for stdlib.h.
2715 * configure: Regenerate.
2716
2717 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2718 variable declaration.
2719 (build_instruction): Initialize memval1.
2720 (build_instruction): Add UNUSED attribute to byte, bigend,
2721 reverse.
2722 (build_operands): Ditto.
2723
2724 * interp.c: Fix GCC warnings.
2725 (sim_get_quit_code): Delete.
2726
2727 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2728 * Makefile.in: Ditto.
2729 * configure: Re-generate.
2730
2731 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2732
2733Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2734
2735 * interp.c (mips_option_handler): New function parse argumes using
2736 sim-options.
2737 (myname): Replace with STATE_MY_NAME.
2738 (sim_open): Delete check for host endianness - performed by
2739 sim_config.
2740 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2741 (sim_open): Move much of the initialization from here.
2742 (sim_load): To here. After the image has been loaded and
2743 endianness set.
2744 (sim_open): Move ColdReset from here.
2745 (sim_create_inferior): To here.
2746 (sim_open): Make FP check less dependant on host endianness.
2747
2748 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2749 run.
2750 * interp.c (sim_set_callbacks): Delete.
2751
2752 * interp.c (membank, membank_base, membank_size): Replace with
2753 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2754 (sim_open): Remove call to callback->init. gdb/run do this.
2755
2756 * interp.c: Update
2757
2758 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2759
2760 * interp.c (big_endian_p): Delete, replaced by
2761 current_target_byte_order.
2762
2763Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2764
2765 * interp.c (host_read_long, host_read_word, host_swap_word,
2766 host_swap_long): Delete. Using common sim-endian.
2767 (sim_fetch_register, sim_store_register): Use H2T.
2768 (pipeline_ticks): Delete. Handled by sim-events.
2769 (sim_info): Update.
2770 (sim_engine_run): Update.
2771
2772Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2773
2774 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2775 reason from here.
2776 (SignalException): To here. Signal using sim_engine_halt.
2777 (sim_stop_reason): Delete, moved to common.
2778
2779Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2780
2781 * interp.c (sim_open): Add callback argument.
2782 (sim_set_callbacks): Delete SIM_DESC argument.
2783 (sim_size): Ditto.
2784
2785Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2786
2787 * Makefile.in (SIM_OBJS): Add common modules.
2788
2789 * interp.c (sim_set_callbacks): Also set SD callback.
2790 (set_endianness, xfer_*, swap_*): Delete.
2791 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2792 Change to functions using sim-endian macros.
2793 (control_c, sim_stop): Delete, use common version.
2794 (simulate): Convert into.
2795 (sim_engine_run): This function.
2796 (sim_resume): Delete.
2797
2798 * interp.c (simulation): New variable - the simulator object.
2799 (sim_kind): Delete global - merged into simulation.
2800 (sim_load): Cleanup. Move PC assignment from here.
2801 (sim_create_inferior): To here.
2802
2803 * sim-main.h: New file.
2804 * interp.c (sim-main.h): Include.
2805
2806Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2807
2808 * configure: Regenerated to track ../common/aclocal.m4 changes.
2809
2810Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2811
2812 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2813
2814Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2815
2816 * gencode.c (build_instruction): DIV instructions: check
2817 for division by zero and integer overflow before using
2818 host's division operation.
2819
2820Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2821
2822 * Makefile.in (SIM_OBJS): Add sim-load.o.
2823 * interp.c: #include bfd.h.
2824 (target_byte_order): Delete.
2825 (sim_kind, myname, big_endian_p): New static locals.
2826 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2827 after argument parsing. Recognize -E arg, set endianness accordingly.
2828 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2829 load file into simulator. Set PC from bfd.
2830 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2831 (set_endianness): Use big_endian_p instead of target_byte_order.
2832
2833Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2834
2835 * interp.c (sim_size): Delete prototype - conflicts with
2836 definition in remote-sim.h. Correct definition.
2837
2838Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2839
2840 * configure: Regenerated to track ../common/aclocal.m4 changes.
2841 * config.in: Ditto.
2842
2843Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2844
2845 * interp.c (sim_open): New arg `kind'.
2846
2847 * configure: Regenerated to track ../common/aclocal.m4 changes.
2848
2849Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2850
2851 * configure: Regenerated to track ../common/aclocal.m4 changes.
2852
2853Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2854
2855 * interp.c (sim_open): Set optind to 0 before calling getopt.
2856
2857Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2858
2859 * configure: Regenerated to track ../common/aclocal.m4 changes.
2860
2861Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2862
2863 * interp.c : Replace uses of pr_addr with pr_uword64
2864 where the bit length is always 64 independent of SIM_ADDR.
2865 (pr_uword64) : added.
2866
2867Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2868
2869 * configure: Re-generate.
2870
2871Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2872
2873 * configure: Regenerate to track ../common/aclocal.m4 changes.
2874
2875Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2876
2877 * interp.c (sim_open): New SIM_DESC result. Argument is now
2878 in argv form.
2879 (other sim_*): New SIM_DESC argument.
2880
2881Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2882
2883 * interp.c: Fix printing of addresses for non-64-bit targets.
2884 (pr_addr): Add function to print address based on size.
2885
2886Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2887
2888 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2889
2890Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2891
2892 * gencode.c (build_mips16_operands): Correct computation of base
2893 address for extended PC relative instruction.
2894
2895Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2896
2897 * interp.c (mips16_entry): Add support for floating point cases.
2898 (SignalException): Pass floating point cases to mips16_entry.
2899 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2900 registers.
2901 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2902 or fmt_word.
2903 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2904 and then set the state to fmt_uninterpreted.
2905 (COP_SW): Temporarily set the state to fmt_word while calling
2906 ValueFPR.
2907
2908Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2909
2910 * gencode.c (build_instruction): The high order may be set in the
2911 comparison flags at any ISA level, not just ISA 4.
2912
2913Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2914
2915 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2916 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2917 * configure.in: sinclude ../common/aclocal.m4.
2918 * configure: Regenerated.
2919
2920Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2921
2922 * configure: Rebuild after change to aclocal.m4.
2923
2924Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2925
2926 * configure configure.in Makefile.in: Update to new configure
2927 scheme which is more compatible with WinGDB builds.
2928 * configure.in: Improve comment on how to run autoconf.
2929 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2930 * Makefile.in: Use autoconf substitution to install common
2931 makefile fragment.
2932
2933Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2934
2935 * gencode.c (build_instruction): Use BigEndianCPU instead of
2936 ByteSwapMem.
2937
2938Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2939
2940 * interp.c (sim_monitor): Make output to stdout visible in
2941 wingdb's I/O log window.
2942
2943Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2944
2945 * support.h: Undo previous change to SIGTRAP
2946 and SIGQUIT values.
2947
2948Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2949
2950 * interp.c (store_word, load_word): New static functions.
2951 (mips16_entry): New static function.
2952 (SignalException): Look for mips16 entry and exit instructions.
2953 (simulate): Use the correct index when setting fpr_state after
2954 doing a pending move.
2955
2956Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2957
2958 * interp.c: Fix byte-swapping code throughout to work on
2959 both little- and big-endian hosts.
2960
2961Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2962
2963 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2964 with gdb/config/i386/xm-windows.h.
2965
2966Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2967
2968 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2969 that messes up arithmetic shifts.
2970
2971Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2972
2973 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2974 SIGTRAP and SIGQUIT for _WIN32.
2975
2976Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2977
2978 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2979 force a 64 bit multiplication.
2980 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2981 destination register is 0, since that is the default mips16 nop
2982 instruction.
2983
2984Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2985
2986 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2987 (build_endian_shift): Don't check proc64.
2988 (build_instruction): Always set memval to uword64. Cast op2 to
2989 uword64 when shifting it left in memory instructions. Always use
2990 the same code for stores--don't special case proc64.
2991
2992 * gencode.c (build_mips16_operands): Fix base PC value for PC
2993 relative operands.
2994 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2995 jal instruction.
2996 * interp.c (simJALDELAYSLOT): Define.
2997 (JALDELAYSLOT): Define.
2998 (INDELAYSLOT, INJALDELAYSLOT): Define.
2999 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3000
3001Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3002
3003 * interp.c (sim_open): add flush_cache as a PMON routine
3004 (sim_monitor): handle flush_cache by ignoring it
3005
3006Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3007
3008 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3009 BigEndianMem.
3010 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3011 (BigEndianMem): Rename to ByteSwapMem and change sense.
3012 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3013 BigEndianMem references to !ByteSwapMem.
3014 (set_endianness): New function, with prototype.
3015 (sim_open): Call set_endianness.
3016 (sim_info): Use simBE instead of BigEndianMem.
3017 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3018 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3019 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3020 ifdefs, keeping the prototype declaration.
3021 (swap_word): Rewrite correctly.
3022 (ColdReset): Delete references to CONFIG. Delete endianness related
3023 code; moved to set_endianness.
3024
3025Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3026
3027 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3028 * interp.c (CHECKHILO): Define away.
3029 (simSIGINT): New macro.
3030 (membank_size): Increase from 1MB to 2MB.
3031 (control_c): New function.
3032 (sim_resume): Rename parameter signal to signal_number. Add local
3033 variable prev. Call signal before and after simulate.
3034 (sim_stop_reason): Add simSIGINT support.
3035 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3036 functions always.
3037 (sim_warning): Delete call to SignalException. Do call printf_filtered
3038 if logfh is NULL.
3039 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3040 a call to sim_warning.
3041
3042Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3043
3044 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3045 16 bit instructions.
3046
3047Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3048
3049 Add support for mips16 (16 bit MIPS implementation):
3050 * gencode.c (inst_type): Add mips16 instruction encoding types.
3051 (GETDATASIZEINSN): Define.
3052 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3053 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3054 mtlo.
3055 (MIPS16_DECODE): New table, for mips16 instructions.
3056 (bitmap_val): New static function.
3057 (struct mips16_op): Define.
3058 (mips16_op_table): New table, for mips16 operands.
3059 (build_mips16_operands): New static function.
3060 (process_instructions): If PC is odd, decode a mips16
3061 instruction. Break out instruction handling into new
3062 build_instruction function.
3063 (build_instruction): New static function, broken out of
3064 process_instructions. Check modifiers rather than flags for SHIFT
3065 bit count and m[ft]{hi,lo} direction.
3066 (usage): Pass program name to fprintf.
3067 (main): Remove unused variable this_option_optind. Change
3068 ``*loptarg++'' to ``loptarg++''.
3069 (my_strtoul): Parenthesize && within ||.
3070 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3071 (simulate): If PC is odd, fetch a 16 bit instruction, and
3072 increment PC by 2 rather than 4.
3073 * configure.in: Add case for mips16*-*-*.
3074 * configure: Rebuild.
3075
3076Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3077
3078 * interp.c: Allow -t to enable tracing in standalone simulator.
3079 Fix garbage output in trace file and error messages.
3080
3081Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3082
3083 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3084 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3085 * configure.in: Simplify using macros in ../common/aclocal.m4.
3086 * configure: Regenerated.
3087 * tconfig.in: New file.
3088
3089Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3090
3091 * interp.c: Fix bugs in 64-bit port.
3092 Use ansi function declarations for msvc compiler.
3093 Initialize and test file pointer in trace code.
3094 Prevent duplicate definition of LAST_EMED_REGNUM.
3095
3096Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3097
3098 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3099
3100Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3101
3102 * interp.c (SignalException): Check for explicit terminating
3103 breakpoint value.
3104 * gencode.c: Pass instruction value through SignalException()
3105 calls for Trap, Breakpoint and Syscall.
3106
3107Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3108
3109 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3110 only used on those hosts that provide it.
3111 * configure.in: Add sqrt() to list of functions to be checked for.
3112 * config.in: Re-generated.
3113 * configure: Re-generated.
3114
3115Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3116
3117 * gencode.c (process_instructions): Call build_endian_shift when
3118 expanding STORE RIGHT, to fix swr.
3119 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3120 clear the high bits.
3121 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3122 Fix float to int conversions to produce signed values.
3123
3124Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3125
3126 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3127 (process_instructions): Correct handling of nor instruction.
3128 Correct shift count for 32 bit shift instructions. Correct sign
3129 extension for arithmetic shifts to not shift the number of bits in
3130 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3131 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3132 Fix madd.
3133 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3134 It's OK to have a mult follow a mult. What's not OK is to have a
3135 mult follow an mfhi.
3136 (Convert): Comment out incorrect rounding code.
3137
3138Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3139
3140 * interp.c (sim_monitor): Improved monitor printf
3141 simulation. Tidied up simulator warnings, and added "--log" option
3142 for directing warning message output.
3143 * gencode.c: Use sim_warning() rather than WARNING macro.
3144
3145Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3146
3147 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3148 getopt1.o, rather than on gencode.c. Link objects together.
3149 Don't link against -liberty.
3150 (gencode.o, getopt.o, getopt1.o): New targets.
3151 * gencode.c: Include <ctype.h> and "ansidecl.h".
3152 (AND): Undefine after including "ansidecl.h".
3153 (ULONG_MAX): Define if not defined.
3154 (OP_*): Don't define macros; now defined in opcode/mips.h.
3155 (main): Call my_strtoul rather than strtoul.
3156 (my_strtoul): New static function.
3157
3158Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3159
3160 * gencode.c (process_instructions): Generate word64 and uword64
3161 instead of `long long' and `unsigned long long' data types.
3162 * interp.c: #include sysdep.h to get signals, and define default
3163 for SIGBUS.
3164 * (Convert): Work around for Visual-C++ compiler bug with type
3165 conversion.
3166 * support.h: Make things compile under Visual-C++ by using
3167 __int64 instead of `long long'. Change many refs to long long
3168 into word64/uword64 typedefs.
3169
3170Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3171
3172 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3173 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3174 (docdir): Removed.
3175 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3176 (AC_PROG_INSTALL): Added.
3177 (AC_PROG_CC): Moved to before configure.host call.
3178 * configure: Rebuilt.
3179
3180Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3181
3182 * configure.in: Define @SIMCONF@ depending on mips target.
3183 * configure: Rebuild.
3184 * Makefile.in (run): Add @SIMCONF@ to control simulator
3185 construction.
3186 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3187 * interp.c: Remove some debugging, provide more detailed error
3188 messages, update memory accesses to use LOADDRMASK.
3189
3190Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3191
3192 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3193 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3194 stamp-h.
3195 * configure: Rebuild.
3196 * config.in: New file, generated by autoheader.
3197 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3198 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3199 HAVE_ANINT and HAVE_AINT, as appropriate.
3200 * Makefile.in (run): Use @LIBS@ rather than -lm.
3201 (interp.o): Depend upon config.h.
3202 (Makefile): Just rebuild Makefile.
3203 (clean): Remove stamp-h.
3204 (mostlyclean): Make the same as clean, not as distclean.
3205 (config.h, stamp-h): New targets.
3206
3207Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3208
3209 * interp.c (ColdReset): Fix boolean test. Make all simulator
3210 globals static.
3211
3212Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3213
3214 * interp.c (xfer_direct_word, xfer_direct_long,
3215 swap_direct_word, swap_direct_long, xfer_big_word,
3216 xfer_big_long, xfer_little_word, xfer_little_long,
3217 swap_word,swap_long): Added.
3218 * interp.c (ColdReset): Provide function indirection to
3219 host<->simulated_target transfer routines.
3220 * interp.c (sim_store_register, sim_fetch_register): Updated to
3221 make use of indirected transfer routines.
3222
3223Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3224
3225 * gencode.c (process_instructions): Ensure FP ABS instruction
3226 recognised.
3227 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3228 system call support.
3229
3230Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3231
3232 * interp.c (sim_do_command): Complain if callback structure not
3233 initialised.
3234
3235Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3236
3237 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3238 support for Sun hosts.
3239 * Makefile.in (gencode): Ensure the host compiler and libraries
3240 used for cross-hosted build.
3241
3242Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3243
3244 * interp.c, gencode.c: Some more (TODO) tidying.
3245
3246Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3247
3248 * gencode.c, interp.c: Replaced explicit long long references with
3249 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3250 * support.h (SET64LO, SET64HI): Macros added.
3251
3252Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3253
3254 * configure: Regenerate with autoconf 2.7.
3255
3256Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3257
3258 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3259 * support.h: Remove superfluous "1" from #if.
3260 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3261
3262Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3263
3264 * interp.c (StoreFPR): Control UndefinedResult() call on
3265 WARN_RESULT manifest.
3266
3267Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3268
3269 * gencode.c: Tidied instruction decoding, and added FP instruction
3270 support.
3271
3272 * interp.c: Added dineroIII, and BSD profiling support. Also
3273 run-time FP handling.
3274
3275Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3276
3277 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3278 gencode.c, interp.c, support.h: created.
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