projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| 08f758df FCE |
1 | 1998-12-30 Frank Ch. Eigler <fche@cygnus.com> |
| 2 | ||
| 3 | * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt. | |
| 4 | start-sanitize-sky | |
| 5 | * interp.c (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook. | |
| 6 | Call sim_engine_halt on BreakPoint. | |
| 7 | end-sanitize-sky | |
| 8 | ||
| bd164e28 SS |
9 | Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE> |
| 10 | ||
| 11 | * configure.in, configure (mips64vr5*-*-*): Added missing ;; in | |
| 12 | case statement. | |
| 13 | ||
| 14bbac66 FCE |
14 | 1998-12-29 Frank Ch. Eigler <fche@cygnus.com> |
| 15 | ||
| 16 | * interp.c (sim_open): Allocate jm3904 memory in smaller chunks. | |
| 17 | (load_word): Call SIM_CORE_SIGNAL hook on error. | |
| 18 | (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before | |
| 19 | starting. For exception dispatching, pass PC instead of NULL_CIA. | |
| 20 | (decode_coproc): Use COP0_BADVADDR to store faulting address. | |
| 21 | * sim-main.h (COP0_BADVADDR): Define. | |
| 22 | (SIM_CORE_SIGNAL): Define hook to call mips_core_signal. | |
| 23 | (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*(). | |
| 24 | (_sim_cpu): Add exc_* fields to store register value snapshots. | |
| 25 | * mips.igen (*): Replace memory-related SignalException* calls | |
| 26 | with references to SIM_CORE_SIGNAL hook. | |
| 27 | ||
| 28 | * dv-tx3904irc.c (tx3904irc_port_event): printf format warning | |
| 29 | fix. | |
| 30 | * sim-main.c (*): Minor warning cleanups. | |
| 31 | ||
| 35d6075a GRK |
32 | 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com> |
| 33 | ||
| 34 | * m16.igen (DADDIU5): Correct type-o. | |
| 35 | ||
| 36 | Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook> | |
| 37 | ||
| 38 | * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp | |
| 39 | variables. | |
| 40 | ||
| f87366ec | 41 | start-sanitize-vr4xxx |
| 35d6075a GRK |
42 | 1998-12-17 Gavin Romig-Koch <gavin@cygnus.com> |
| 43 | ||
| 44 | * vr4run.c (sim_engine_run): Enable the 4111. | |
| 45 | ||
| 46 | end-sanitize-vr4xxx | |
| 47 | Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook> | |
| 48 | ||
| 49 | * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib | |
| 50 | to include path. | |
| 51 | (interp.o): Add dependency on itable.h | |
| 52 | (oengine.c, gencode): Delete remaining references. | |
| 53 | (BUILT_SRC_FROM_GEN): Clean up. | |
| 54 | start-sanitize-vr4xxx | |
| 55 | (SIM_HACK_ALL): Define. | |
| 56 | (hack, libhack.a): Do not build. | |
| 57 | end-sanitize-vr4xxx | |
| 58 | ||
| f87366ec GRK |
59 | 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com> |
| 60 | ||
| 61 | * vr4run.c: New. | |
| 62 | * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a, | |
| 63 | tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack, | |
| 64 | tmp-run-hack) : New. | |
| 65 | * configure.in (mips64vr4xxx): Switch to using the HACK | |
| 66 | generator. Set TARGET_ENABLE_FR. | |
| 67 | * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU, | |
| 68 | DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX): | |
| 69 | Drop the "64" qualifier to get the HACK generator working. | |
| 70 | Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT. | |
| 71 | Add vr4121 where necessary. | |
| 72 | * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only | |
| 73 | qualifier to get the hack generator working. | |
| 74 | (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New. | |
| 75 | (DSLL): Use do_dsll. | |
| 76 | (DSLLV): Use do_dsllv. | |
| 77 | (DSRA): Use do_dsra. | |
| 78 | (DSRL): Use do_dsrl. | |
| 79 | (DSRLV): Use do_dsrlv. | |
| 80 | (BC1): Move *vr4100,*vr4111, and *vr4121 to get the HACK | |
| 81 | generator working. | |
| 82 | (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to | |
| 83 | get the HACK generator working. | |
| 84 | * vr.igen: Add *vr4320 where missing. | |
| 85 | (MACC) Rename to get the HACK generator working. | |
| 86 | (DMACC,MACCS,DMACCS): Add the 64. | |
| 87 | ||
| 7d2ec607 GRK |
88 | start-sanitize-vr4320 |
| 89 | 1998-12-14 Gavin Romig-Koch <gavin@cygnus.com> | |
| 90 | ||
| 91 | * vr.igen (Low32Bits): Add vr4320. | |
| 92 | ||
| 93 | end-sanitize-vr4320 | |
| bff2d368 GRK |
94 | 1998-12-14 Gavin Romig-Koch <gavin@cygnus.com> |
| 95 | ||
| 96 | * configure.in: Add support for 5xxx and "el". | |
| 97 | * configure: Rebuild. | |
| 98 | ||
| f14397f0 GRK |
99 | start-sanitize-vr4xxx |
| 100 | 1998-12-13 Gavin Romig-Koch <gavin@cygnus.com> | |
| 101 | ||
| 102 | * configure.in,mips.igen,vr.igen: Add vr4121. | |
| 103 | * configure: Rebuilt. | |
| 104 | ||
| 105 | end-sanitize-vr4xxx | |
| 82aeada7 GRK |
106 | 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com> |
| 107 | ||
| 108 | start-sanitize-vr4xxx | |
| 109 | * configure.in (mips64vr4xxx): Enable TARGET_ENABLE_FR. | |
| 110 | Set mips_fpu, and mips_fpu_bitsize. | |
| 111 | Set sim_gen, and sim_igen_machine. | |
| 112 | * configure: Rebuild. | |
| 113 | ||
| 114 | end-sanitize-vr4xxx | |
| 115 | * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts. | |
| 116 | * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR. | |
| 117 | ||
| eac6dec5 GRK |
118 | 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com> |
| 119 | ||
| 120 | * mips/interp.c (DEBUG): Cleanups. | |
| 121 | ||
| c426ee5d FCE |
122 | 1998-12-10 Frank Ch. Eigler <fche@cygnus.com> |
| 123 | ||
| 124 | * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes. | |
| 125 | (tx3904sio_tickle): fflush after a stdout character output. | |
| 126 | ||
| 3314a50a JL |
127 | 1998-12-03 Frank Ch. Eigler <fche@cygnus.com> |
| 128 | ||
| 129 | * interp.c (sim_close): Uninstall modules. | |
| 130 | ||
| 131 | start-sanitize-sky | |
| 132 | Tue Dec 1 18:40:30 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 133 | ||
| 134 | * sky-libvpe.c (FCmp): Abort when no result. | |
| 135 | ||
| 136 | end-sanitize-sky | |
| a6a5d349 AC |
137 | Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com> |
| 138 | ||
| 139 | * sim-main.h, interp.c (sim_monitor): Change to global | |
| 140 | function. | |
| 141 | ||
| baa1a488 AC |
142 | Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com> |
| 143 | ||
| 144 | * configure.in (vr4100): Only include vr4100 instructions in | |
| 145 | simulator. | |
| 146 | * configure: Re-generate. | |
| 147 | * m16.igen (*): Tag all mips16 instructions as also being vr4100. | |
| 148 | ||
| 149 | Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 150 | ||
| 151 | * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN. | |
| 152 | * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping | |
| 153 | true alternative. | |
| 154 | ||
| 155 | * configure.in (sim_default_gen, sim_use_gen): Replace with | |
| 156 | sim_gen. | |
| 157 | (--enable-sim-igen): Delete config option. Always using IGEN. | |
| 158 | * configure: Re-generate. | |
| 159 | ||
| 160 | * Makefile.in (gencode): Kill, kill, kill. | |
| 161 | * gencode.c: Ditto. | |
| 162 | ||
| 57791952 AC |
163 | Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com> |
| 164 | ||
| 165 | * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64 | |
| 166 | bit mips16 igen simulator. | |
| 167 | * configure: Re-generate. | |
| 168 | ||
| 169 | * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark | |
| 170 | as part of vr4100 ISA. | |
| 171 | * vr.igen: Mark all instructions as 64 bit only. | |
| 172 | ||
| 5a581ea6 AC |
173 | Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com> |
| 174 | ||
| 175 | * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent): | |
| 176 | Pacify GCC. | |
| 177 | ||
| ee562da4 AC |
178 | start-sanitize-tx19 |
| 179 | Mon Nov 23 16:51:02 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 180 | ||
| 181 | * configure.in (tx19): Reconize target mips-tx19-elf. | |
| 182 | * configure: Re-generate. | |
| 183 | ||
| 184 | end-sanitize-tx19 | |
| a83d7d87 AC |
185 | Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com> |
| 186 | ||
| 187 | * configure.in: Configure mips-lsi-elf nee mips*lsi* as a | |
| 188 | mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos. | |
| 189 | * configure: Re-generate. | |
| 190 | ||
| 191 | * m16.igen (BREAK): Define breakpoint instruction. | |
| 192 | (JALX32): Mark instruction as mips16 and not r3900. | |
| 193 | * mips.igen (C.cond.fmt): Fix typo in instruction format. | |
| 194 | ||
| 195 | * sim-main.h (PENDING_FILL): Wrap C statements in do/while. | |
| 196 | ||
| 821b702f AC |
197 | start-sanitize-r5900 |
| 198 | Mon Nov 16 11:44:24 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 199 | ||
| 200 | * r5900.igen (CVT.W.S): Always round towards zero. | |
| 201 | ||
| 202 | end-sanitize-r5900 | |
| d1cbd70a AC |
203 | Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com> |
| 204 | ||
| 205 | * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK | |
| 206 | insn as a debug breakpoint. | |
| 207 | ||
| 208 | * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as | |
| 209 | pending.slot_size. | |
| 210 | (PENDING_SCHED): Clean up trace statement. | |
| 211 | (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL. | |
| 212 | (PENDING_FILL): Delay write by only one cycle. | |
| 213 | (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE. | |
| 214 | ||
| 215 | * sim-main.c (pending_tick): Clean up trace statements. Add trace | |
| 216 | of pending writes. | |
| 217 | (pending_tick): Fix sizes in switch statements, 4 & 8 instead of | |
| 218 | 32 & 64. | |
| 219 | (pending_tick): Move incrementing of index to FOR statement. | |
| 220 | (pending_tick): Only update PENDING_OUT after a write has occured. | |
| 221 | ||
| 222 | * configure.in: Add explicit mips-lsi-* target. Use gencode to | |
| 223 | build simulator. | |
| 224 | * configure: Re-generate. | |
| 225 | ||
| 226 | * interp.c (sim_engine_run OLD): Delete explicit call to | |
| 227 | PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK. | |
| 228 | ||
| dd0f6109 | 229 | start-sanitize-r5900 |
| 7d88afe6 AC |
230 | Wed Nov 11 16:53:57 1998 Andrew Cagney <cagney@b1.cygnus.com> |
| 231 | ||
| 232 | * r5900.igen (RSQRT): Set both I/SI and D/SD when div-0. | |
| 233 | ||
| 210a903b FCE |
234 | Thu Nov 5 10:29:42 EST 1998 Frank Ch. Eigler <fche@cygnus.com> |
| 235 | ||
| 236 | * r5900.igen (r59fp_opdiv): Correct erroneous FGR[FD] reference. | |
| 237 | ||
| dd0f6109 AC |
238 | Thu Nov 5 19:40:12 1998 Andrew Cagney <cagney@b1.cygnus.com> |
| 239 | ||
| 240 | * r5900.igen (DIV): Do not clear clear SO/SU when already set. | |
| 241 | ||
| 242 | * r5900.igen (RSQRT.S): Do not compute 1/srqt(abs(T)) when T | |
| 243 | negative, compute S/sqrt(abs(T)) instead. Correctly set FCSR | |
| 244 | bits. | |
| 245 | ||
| 246 | * r5900.igen (RSQRT.S): Handle overflow/underflow better. Check | |
| 247 | sign of FT not FS. | |
| 248 | (r59fp_store): Clarify "bad value" abort messages. | |
| 249 | ||
| 250 | end-sanitize-r5900 | |
| fd0e83b6 | 251 | Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com> |
| 0ec51df9 FCE |
252 | |
| 253 | * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy | |
| 254 | interrupt level number to match changed SignalExceptionInterrupt | |
| 255 | macro. | |
| 256 | ||
| fd6e6422 FCE |
257 | start-sanitize-sky |
| 258 | Thu Oct 29 12:47:46 1998 Frank Ch. Eigler <fche@cygnus.com> | |
| 259 | ||
| 260 | * sim-main.c (tlb_try_match): Include physical address in | |
| 261 | scratchpad non-mapping warning. | |
| 262 | ||
| 263 | end-sanitize-sky | |
| 3ac7980b FCE |
264 | start-sanitize-r5900 |
| 265 | Thu Oct 29 11:06:30 EST 1998 Frank Ch. Eigler <fche@cygnus.com> | |
| 266 | ||
| 267 | * r5900.igen: Fix PSRLVW, MULTU1, PADSBH instructions, | |
| 268 | as per customer patch. | |
| 269 | ||
| 270 | end-sanitize-r5900 | |
| 3b5f4257 DE |
271 | Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com> |
| 272 | ||
| 273 | * interp.c: #include "itable.h" if WITH_IGEN. | |
| 274 | (get_insn_name): New function. | |
| 275 | (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS. | |
| fda83b67 | 276 | * sim-main.h (MAX_INSNS,INSN_NAME): Delete. |
| 3b5f4257 | 277 | |
| fda83b67 FCE |
278 | start-sanitize-sky |
| 279 | Tue Sep 22 10:35:37 1998 Frank Ch. Eigler <fche@cygnus.com> | |
| 280 | ||
| 281 | * sim-main.c (tlb_try_match): Specially match virtual | |
| 282 | pages mapped to scratchpad RAM, an unimplemented feature. | |
| 283 | ||
| 284 | end-sanitize-sky | |
| 285 | start-sanitize-r5900 | |
| 286 | Fri Sep 18 11:31:16 1998 Frank Ch. Eigler <fche@cygnus.com> | |
| 287 | ||
| 288 | * r5900.igen (prot3w): Correct rotation sequence; patch | |
| 289 | from customer. | |
| 290 | ||
| 291 | end-sanitize-r5900 | |
| 3b5f4257 DE |
292 | Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com> |
| 293 | ||
| 294 | * configure: Rebuilt to inhale new common/aclocal.m4. | |
| 295 | ||
| 9ade226a | 296 | start-sanitize-r5900 |
| 4d87923e DE |
297 | Thu Sep 10 11:50:54 1998 Doug Evans <devans@canuck.cygnus.com> |
| 298 | ||
| 299 | * r5900.igen (plzcw): Make `i' signed. | |
| 300 | ||
| fda83b67 FCE |
301 | Wed Sep 9 15:02:10 1998 Doug Evans <devans@canuck.cygnus.com> |
| 302 | ||
| 303 | * sim-main.h (COP0_COUNT,COP0_COMPARE,status_IM7): New macros. | |
| 304 | * sky-engine.c (cpu_issue): Increment COP0_COUNT and signal an | |
| 305 | interrupt if == COP0_COMPARE and interrupt masks/enables allow it. | |
| 306 | * interp.c (signal_exception, sky version): Handle INT 2. | |
| 307 | ||
| 323f833d RU |
308 | Wed Sep 9 11:28:20 1998 Ron Unrau <runrau@cygnus.com> |
| 309 | ||
| 310 | * sim-main.h: track COP0 registers | |
| 311 | * interp.c (sim_{fetch,store}_register): read/write COP0 registers | |
| 312 | ||
| 9ade226a FCE |
313 | Fri Sep 4 10:37:57 1998 Frank Ch. Eigler <fche@cygnus.com> |
| 314 | ||
| 315 | * r5900.igen (mtsab): Correct typo in input register. | |
| 316 | ||
| 317 | * sim-main.h (TMP_*): New macros for accessing local 128-bit | |
| 318 | temporary for multimedia instructions. | |
| 319 | * r5900.igen (*): Convert most instructions to use new TMP | |
| 320 | macros to store output result during computation. | |
| 321 | ||
| 322 | end-sanitize-r5900 | |
| 78b871ec FCE |
323 | Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com> |
| 324 | ||
| 325 | * dv-tx3904sio.c: Include sim-assert.h. | |
| 326 | ||
| 327 | Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com> | |
| 328 | ||
| 329 | * dv-tx3904sio.c: New file: tx3904 serial I/O module. | |
| 330 | * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target. | |
| 331 | Reorganize target-specific sim-hardware checks. | |
| 332 | * configure: rebuilt. | |
| 333 | * interp.c (sim_open): For tx39 target boards, set | |
| 334 | OPERATING_ENVIRONMENT, add tx3904sio devices. | |
| 335 | * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading | |
| 336 | ROM executables. Install dv-sockser into sim-modules list. | |
| 337 | ||
| 338 | * dv-tx3904irc.c: Compiler warning clean-up. | |
| 339 | * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly | |
| 340 | frequent hw-trace messages. | |
| 341 | ||
| fda83b67 FCE |
342 | start-sanitize-sky |
| 343 | Tue Aug 11 13:52:16 1998 Frank Ch. Eigler <fche@cygnus.com> | |
| 344 | ||
| 345 | * interp.c (signal_exception): Set IP3 bit in CAUSE on | |
| 346 | sky interrupt. | |
| 347 | ||
| 348 | end-sanitize-sky | |
| 78b871ec FCE |
349 | Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com> |
| 350 | ||
| 351 | * vr.igen (MulAcc): Identify as a vr4100 specific function. | |
| 352 | ||
| e1b20d30 AC |
353 | Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com> |
| 354 | ||
| 78b871ec FCE |
355 | * Makefile.in (IGEN_INCLUDE): Add vr.igen. |
| 356 | ||
| e1b20d30 AC |
357 | * vr.igen: New file. |
| 358 | (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c. | |
| 359 | * mips.igen: Define vr4100 model. Include vr.igen. | |
| 78b871ec FCE |
360 | start-sanitize-cygnus |
| 361 | * vr5400.igen: Move instructions to vr.igen | |
| 362 | * Makefile.in (IGEN_INCLUDE): Remove vr5400.igen. | |
| 363 | end-sanitize-cygnus | |
| 364 | start-sanitize-vr4320 | |
| 365 | * vr4320.igen: Move instructions to vr.igen. | |
| 366 | * Makefile.in (IGEN_INCLUDE): Remove vr5320.igen. | |
| fda83b67 | 367 | |
| 78b871ec | 368 | end-sanitize-vr4320 |
| fda83b67 FCE |
369 | start-sanitize-sky |
| 370 | Fri Jul 24 16:01:03 1998 Ian Carmichael <iancarm@cygnus.com> | |
| 371 | ||
| 372 | * interp.c (MONITOR_SIZE): Make 1MB monitor for SKY. | |
| 373 | * mips.igen (BREAK): Fix 0xffff2 monitor call. Slightly less | |
| 374 | confusing message if not enough --load-next options appear. | |
| 375 | ||
| 376 | * sky-pke.h (VUx_MEMx_SRCADDR_START): Move to 0x19800000 range. | |
| 377 | * sim-main.c (GDB_COMM_AREA): Move to 0x19810000. | |
| 378 | * sky-gdb.c (init_fifo_bp_cache): Use VIO_BASE when reading GDB area. | |
| 379 | (resume_handler): Same. | |
| 380 | (suspend_handler): Same. | |
| 381 | ||
| 382 | Wed Jul 22 13:04:13 1998 Frank Ch. Eigler <fche@cygnus.com> | |
| 383 | ||
| 384 | * mips.igen (break): Implement LOAD_INSTRUCTION ("break 0xffff1") | |
| 385 | to trigger multi-phase load. | |
| 386 | ||
| 387 | * sim-main.c: Include sim-assert.h for ASSERT macro. | |
| 388 | * sim-main.h (PRINTF_INSTRUCTION): Correct bit pattern for | |
| 389 | "break 0xffff2". | |
| 390 | ||
| 391 | Tue Jul 21 18:37:36 1998 Ian Carmichael <iancarm@cygnus.com> | |
| 392 | ||
| 393 | MMU support. | |
| 394 | * interp.c (sim_open): Initialize TLB. | |
| 395 | * interp.c (signal_exceptions): New 5900 handling. | |
| 396 | * r5900.igen (TLBWR, TLBWI, TLBR, TLBP): Make these work. | |
| 397 | * sim-main.c (tlb_try_match, tlb_lookup): New functions. | |
| 398 | (address_translation): Use the TLB. | |
| 399 | * sim-main.h (r4000_tlb_entry_t): New type. | |
| 400 | (TLB_*): New constants. | |
| 401 | (COP0_*): New register names. | |
| 402 | ||
| 403 | Sky character I/O device. | |
| 404 | * sky-psio.c: New file. | |
| 405 | * sky-psio.h: New file. | |
| 406 | * Makefile.in: Add sky-psio.o. | |
| e1b20d30 | 407 | |
| fda83b67 | 408 | end-sanitize-sky |
| e1b20d30 AC |
409 | start-sanitize-r5900 |
| 410 | Tue Jul 14 16:10:45 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 411 | ||
| 412 | * r5900.igen (r59fp_overflow): Replace argument ANS with argument | |
| 413 | SIGN_P. | |
| 414 | (r59fp_zero): Ditto. | |
| 415 | (r59fp_store): Update calls. | |
| 416 | (DIV.S): Compute 0/0 sign from inputs. Ditto for X/0. | |
| 417 | ||
| 418 | end-sanitize-r5900 | |
| 419 | start-sanitize-branchbug4011 | |
| 420 | Mon Jun 29 09:31:27 1998 Gavin Koch <gavin@cygnus.com> | |
| 421 | ||
| 422 | * interp.c (OPTION_BRANCH_BUG_4011): Add. | |
| 423 | (mips_option_handler): Handle OPTION_BRANCH_BUG_4011. | |
| 424 | (mips_options): Define the option. | |
| 425 | * mips.igen (check_4011_branch_bug): New. | |
| 426 | (mark_4011_branch_bug): New. | |
| 427 | (all branch insn): Call mark_branch_bug, and check_branch_bug. | |
| 428 | * sim-main.h (branchbug4011_option, branchbug4011_last_target, | |
| 429 | branchbug4011_last_cia, BRANCHBUG4011_OPTION, | |
| 430 | BRANCHBUG4011_LAST_TARGET, BRANCHBUG4011_LAST_CIA, | |
| 431 | check_branch_bug, mark_branch_bug): Define. | |
| 432 | ||
| 433 | end-sanitize-branchbug4011 | |
| aaa2c908 GRK |
434 | Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com> |
| 435 | ||
| 436 | * mips.igen (check_mf_hilo): Correct check. | |
| 437 | ||
| 438 | start-sanitize-r5900 | |
| 439 | Fri Jun 19 14:44:46 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 440 | ||
| 441 | * sim-main.h (NR_COP0_GPR, COP0_GPR, cop0_gpr, NR_COP0_BP, | |
| 442 | COP0_BP, cop0_bp, NR_COP0_P, COP0_P, cop0_p): Add 32 COP0 general | |
| 443 | purpose registers, add 8 COP0 break-point registers, add 64 COP0 | |
| 444 | performance registers. | |
| 445 | ||
| 446 | * interp.c (decode_coproc): Accept any MTC0/MFC0, MTBP/MFBP, MTP* | |
| 447 | MFP* instructions. Just transfer value to/from corresponding | |
| 448 | register. | |
| 449 | ||
| 450 | * r5900.igen (BC0F, BC0FL, BC0T, BC0TL): Implement, assume COP0 | |
| 451 | status is always true. | |
| 452 | (CACHE, TLBP, TPGWI, TLBWR): Treat as NOP. | |
| 453 | (EI, DI): Set/clear Status-EIE bit. | |
| 454 | ||
| 455 | end-sanitize-r5900 | |
| 456 | start-sanitize-sky | |
| 457 | Fri Jun 19 14:44:46 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 458 | ||
| 459 | * mips.igen (BC0F, BC0FL, BC0T, BC0TL): Move to sky code to | |
| 460 | r5900.igen. | |
| 461 | ||
| 462 | end-sanitize-sky | |
| 463 | Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 464 | ||
| 465 | start-sanitize-sky | |
| 466 | * sky-vu.c (vu0_read_cop2_register, vu0_write_cop2_register): Call | |
| 467 | ASSERT not assert. | |
| 468 | * sky-gdb.c: Include "sim-assert.h". | |
| 469 | ||
| 470 | end-sanitize-sky | |
| 471 | * sim-main.h (interrupt_event): Add prototype. | |
| 472 | ||
| aaa2c908 GRK |
473 | * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused |
| 474 | register_ptr, register_value. | |
| 475 | (deliver_tx3904tmr_tick): Fix types passed to printf fmt. | |
| 476 | ||
| aaa2c908 GRK |
477 | * sim-main.h (tracefh): Make extern. |
| 478 | ||
| 702968c5 FCE |
479 | Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com> |
| 480 | ||
| 481 | * dv-tx3904tmr.c: Deschedule timer event after dispatching. | |
| 482 | Reduce unnecessarily high timer event frequency. | |
| 483 | * dv-tx3904cpu.c: Ditto for interrupt event. | |
| 484 | ||
| 702968c5 FCE |
485 | start-sanitize-sky |
| 486 | Tue Jun 16 14:12:09 1998 Frank Ch. Eigler <fche@cygnus.com> | |
| 487 | ||
| 488 | * interp.c (decode_coproc): Removed COP2 branches. | |
| 489 | * r5900.igen: Moved COP2 branch instructions here. | |
| 490 | * mips.igen: Restricted COPz == COP2 bit pattern to | |
| 491 | exclude COP2 branches. | |
| 492 | ||
| 493 | end-sanitize-sky | |
| b8790963 FCE |
494 | Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com> |
| 495 | ||
| 496 | * interp.c (decode_coproc): For TX39, add stub COP0 register #7, | |
| 497 | to allay warnings. | |
| 498 | (interrupt_event): Made non-static. | |
| b8790963 FCE |
499 | |
| 500 | * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental | |
| 501 | interchange of configuration values for external vs. internal | |
| 502 | clock dividers. | |
| b8790963 | 503 | |
| 0001bce1 IC |
504 | Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com> |
| 505 | ||
| 506 | * mips.igen (BREAK): Moved code to here for | |
| 507 | simulator-reserved break instructions. | |
| 508 | * gencode.c (build_instruction): Ditto. | |
| 509 | * interp.c (signal_exception): Code moved from here. Non- | |
| 510 | reserved instructions now use exception vector, rather | |
| 511 | than halting sim. | |
| 512 | * sim-main.h: Moved magic constants to here. | |
| 513 | ||
| cc9bc932 FCE |
514 | Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com> |
| 515 | ||
| 516 | * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE | |
| 517 | register upon non-zero interrupt event level, clear upon zero | |
| 518 | event value. | |
| 519 | * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal | |
| 520 | by passing zero event value. | |
| 521 | (*_io_{read,write}_buffer): Endianness fixes. | |
| 522 | * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes. | |
| 523 | (deliver_*_tick): Reduce sim event interval to 75% of count interval. | |
| 524 | ||
| 525 | * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based | |
| 526 | serial I/O and timer module at base address 0xFFFF0000. | |
| 527 | ||
| 2b5d87df GRK |
528 | Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com> |
| 529 | ||
| 530 | * mips.igen (SWC1) : Correct the handling of ReverseEndian | |
| 531 | and BigEndianCPU. | |
| 532 | ||
| 55ad270f GRK |
533 | Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com> |
| 534 | ||
| 535 | * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips | |
| 536 | parts. | |
| 537 | * configure: Update. | |
| 538 | ||
| da040f2a FCE |
539 | Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com> |
| 540 | ||
| 541 | * dv-tx3904tmr.c: New file - implements tx3904 timer. | |
| 542 | * dv-tx3904{irc,cpu}.c: Mild reformatting. | |
| 543 | * configure.in: Include tx3904tmr in hw_device list. | |
| 544 | * configure: Rebuilt. | |
| 545 | * interp.c (sim_open): Instantiate three timer instances. | |
| 546 | Fix address typo of tx3904irc instance. | |
| 547 | ||
| 0e797366 AC |
548 | start-sanitize-r5900 |
| 549 | Thu Jun 4 16:47:27 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 550 | ||
| 551 | * mips.igen (check_mt_hilo): 2.1 of r5900 spec stalls for HILO. | |
| 552 | Select corresponding check_mt_hilo function. | |
| 553 | (check_mult_hilo, check_div_hilo, check_mf_hilo, check_mt_hilo): | |
| 554 | Ditto. | |
| 555 | ||
| 556 | * r5900.igen (check_mult_hilo_hi1lo1, check_div_hilo_hi1lo1): Mark | |
| 557 | as r5900 specific. | |
| 558 | ||
| 559 | end-sanitize-r5900 | |
| 8e3a0b59 IC |
560 | Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com> |
| 561 | ||
| 562 | * interp.c (signal_exception): SystemCall exception now uses | |
| 563 | the exception vector. | |
| 564 | ||
| 29b5afe9 FCE |
565 | Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com> |
| 566 | ||
| 567 | * interp.c (decode_coproc): For TX39, add stub COP0 register #3, | |
| 568 | to allay warnings. | |
| 569 | ||
| fb0ea2b9 JL |
570 | start-sanitize-r5900 |
| 571 | Mon Jun 1 10:28:25 1998 Jeffrey A Law (law@cygnus.com) | |
| 572 | ||
| 573 | * r5900.igen (rsqrt.s): Update based on r5900 ISA manual version 2.1. | |
| 574 | (sqrt.s): Likewise. | |
| 575 | ||
| 576 | end-sanitize-r5900 | |
| df26156d AC |
577 | Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com> |
| 578 | ||
| 579 | * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39. | |
| 580 | ||
| df26156d AC |
581 | Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com> |
| 582 | ||
| 583 | * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method. | |
| 584 | ||
| 585 | * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and | |
| 586 | sim-main.h. Declare a struct hw_descriptor instead of struct | |
| 587 | hw_device_descriptor. | |
| 588 | ||
| ce823781 AC |
589 | Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com> |
| 590 | ||
| 591 | * mips.igen (do_store_left, do_load_left): Compute nr of left and | |
| 592 | right bits and then re-align left hand bytes to correct byte | |
| 593 | lanes. Fix incorrect computation in do_store_left when loading | |
| 594 | bytes from second word. | |
| 595 | ||
| f872d0d6 AC |
596 | Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com> |
| 597 | ||
| 598 | * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904. | |
| 599 | * interp.c (sim_open): Only create a device tree when HW is | |
| 600 | enabled. | |
| 601 | ||
| 602 | * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC. | |
| 603 | * interp.c (signal_exception): Ditto. | |
| 604 | ||
| 5e34097b GRK |
605 | Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com> |
| 606 | ||
| 607 | * gencode.c: Mark BEGEZALL as LIKELY. | |
| 608 | ||
| 26feb3a8 AC |
609 | Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com> |
| 610 | ||
| 611 | * sim-main.h (ALU32_END): Sign extend 32 bit results. | |
| 612 | * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace. | |
| 613 | ||
| 84048259 AC |
614 | start-sanitize-r5900 |
| 615 | Thu May 21 17:15:39 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 616 | ||
| 617 | * interp.c (sim_fetch_register): Convert internal r5900 regs to | |
| 618 | target byte order | |
| 619 | ||
| 620 | end-sanitize-r5900 | |
| 3fa454e9 FCE |
621 | Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com> |
| 622 | ||
| 623 | * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware | |
| 624 | modules. Recognize TX39 target with "mips*tx39" pattern. | |
| 625 | * configure: Rebuilt. | |
| 626 | * sim-main.h (*): Added many macros defining bits in | |
| 627 | TX39 control registers. | |
| 628 | (SignalInterrupt): Send actual PC instead of NULL. | |
| 629 | (SignalNMIReset): New exception type. | |
| 630 | * interp.c (board): New variable for future use to identify | |
| 631 | a particular board being simulated. | |
| 632 | (mips_option_handler,mips_options): Added "--board" option. | |
| 633 | (interrupt_event): Send actual PC. | |
| 634 | (sim_open): Make memory layout conditional on board setting. | |
| 635 | (signal_exception): Initial implementation of hardware interrupt | |
| 636 | handling. Accept another break instruction variant for simulator | |
| 637 | exit. | |
| 638 | (decode_coproc): Implement RFE instruction for TX39. | |
| 639 | (mips.igen): Decode RFE instruction as such. | |
| 3fa454e9 FCE |
640 | * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904. |
| 641 | * interp.c: Define "jmr3904" and "jmr3904debug" board types and | |
| 642 | bbegin to implement memory map. | |
| 643 | * dv-tx3904cpu.c: New file. | |
| 644 | * dv-tx3904irc.c: New file. | |
| 3fa454e9 FCE |
645 | |
| 646 | Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com> | |
| 647 | ||
| 648 | * mips.igen (check_mt_hilo): Create a separate r3900 version. | |
| 649 | ||
| 32d41f6d | 650 | start-sanitize-r5900 |
| 7d2c0e8c GRK |
651 | Wed May 13 14:27:53 1998 Gavin Koch <gavin@cygnus.com> |
| 652 | ||
| 653 | * r5900.igen: Replace the calls and the definition of the | |
| 654 | function check_op_hilo_hi1lo1 with the pair | |
| 655 | check_mult_hilo_hi1lo1 and check_mult_hilo_hi1lo1. | |
| 656 | ||
| 32d41f6d | 657 | end-sanitize-r5900 |
| afc5e7f2 GRK |
658 | Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com> |
| 659 | ||
| 660 | * tx.igen (madd,maddu): Replace calls to check_op_hilo | |
| 661 | with calls to check_div_hilo. | |
| 662 | ||
| 94dda41a GRK |
663 | Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com> |
| 664 | ||
| 665 | * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo): | |
| 666 | Replace check_op_hilo with check_mult_hilo and check_div_hilo. | |
| 667 | Add special r3900 version of do_mult_hilo. | |
| 668 | (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo | |
| 669 | with calls to check_mult_hilo. | |
| 670 | (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo | |
| 671 | with calls to check_div_hilo. | |
| 672 | ||
| 1a89994e AC |
673 | Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com> |
| 674 | ||
| 675 | * configure.in (SUBTARGET_R3900): Define for mipstx39 target. | |
| 676 | Document a replacement. | |
| 677 | ||
| 678 | Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com> | |
| 679 | ||
| 680 | * interp.c (sim_monitor): Make mon_printf work. | |
| 681 | ||
| eb00d706 DE |
682 | Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com> |
| 683 | ||
| 684 | * sim-main.h (INSN_NAME): New arg `cpu'. | |
| 685 | ||
| 686 | start-sanitize-sky | |
| 687 | Thu Apr 30 18:51:26 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 688 | ||
| 689 | * sky-libvpe.c (FMAdd, FMSub): Replace r59fp_op3 call with | |
| 690 | r59fp_mula. | |
| 691 | ||
| 692 | end-sanitize-sky | |
| 693 | start-sanitize-r5900 | |
| 694 | Wed Apr 29 22:54:45 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 695 | ||
| 696 | * sim-main.h (R5900_FP_MAX, R5900_FP_MIN): Define. | |
| 697 | * r5900.igen (r59fp_overflow): Use. | |
| 698 | ||
| 699 | * r5900.igen (r59fp_op3): Rename to | |
| 700 | (r59fp_mula): This, delete opm argument. | |
| 701 | (MADD.S, MADDA.S, MSUB.S, MSUBS.S): Update. | |
| 702 | (r59fp_mula): Overflowing product propogates through to result. | |
| 703 | (r59fp_mula): ACC to the MAX propogates to result. | |
| 704 | (r59fp_mula): Underflow during multiply only sets SU. | |
| 705 | ||
| 706 | end-sanitize-r5900 | |
| 9d45df1b GN |
707 | Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com> |
| 708 | ||
| 709 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 710 | ||
| 5da9ce07 TT |
711 | Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche> |
| 712 | ||
| 713 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 714 | * config.in: Ditto. | |
| 715 | ||
| 716 | Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com> | |
| 717 | ||
| 718 | * acconfig.h: New file. | |
| 719 | * configure.in: Reverted change of Apr 24; use sinclude again. | |
| 720 | ||
| b1df34b9 TT |
721 | Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche> |
| 722 | ||
| 723 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 724 | * config.in: Ditto. | |
| 725 | ||
| 726 | Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com> | |
| 727 | ||
| 728 | * configure.in: Don't call sinclude. | |
| 729 | ||
| ca61710b AC |
730 | Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com> |
| 731 | ||
| 732 | * mips.igen (do_store_left): Pass 0 not NULL to store_memory. | |
| 733 | ||
| 97f4d183 AC |
734 | Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com> |
| 735 | ||
| 736 | * mips.igen (ERET): Implement. | |
| 737 | ||
| 738 | * interp.c (decode_coproc): Return sign-extended EPC. | |
| 739 | ||
| 740 | * mips.igen (ANDI, LUI, MFC0): Add tracing code. | |
| 741 | ||
| 742 | * interp.c (signal_exception): Do not ignore Trap. | |
| 743 | (signal_exception): On TRAP, restart at exception address. | |
| 744 | (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define. | |
| 745 | (signal_exception): Update. | |
| 515125b7 AC |
746 | (sim_open): Patch V_COMMON interrupt vector with an abort sequence |
| 747 | so that TRAP instructions are caught. | |
| 97f4d183 | 748 | |
| 421cbaae AC |
749 | Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com> |
| 750 | ||
| 751 | * sim-main.h (struct hilo_access, struct hilo_history): Define, | |
| 752 | contains HI/LO access history. | |
| 753 | (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access. | |
| 754 | (HIACCESS, LOACCESS): Delete, replace with | |
| 755 | (HIHISTORY, LOHISTORY): New macros. | |
| 756 | (start-sanitize-r5900): | |
| 757 | (struct sim_5900_cpu): Make hi1access, lo1access of type | |
| 758 | hilo_access. | |
| 759 | (HI1ACCESS, LO1ACCESS): Delete, replace with | |
| 760 | (HI1HISTORY, LO1HISTORY): New macros. | |
| 761 | (end-sanitize-r5900): | |
| 762 | (CHECKHILO): Delete all, moved to mips.igen | |
| 763 | ||
| 764 | * gencode.c (build_instruction): Do not generate checks for | |
| 765 | correct HI/LO register usage. | |
| 766 | ||
| 767 | * interp.c (old_engine_run): Delete checks for correct HI/LO | |
| 768 | register usage. | |
| 769 | ||
| 770 | * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo, | |
| 771 | check_mf_cycles): New functions. | |
| 772 | (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div, | |
| 773 | do_divu, domultx, do_mult, do_multu): Use. | |
| 774 | ||
| 775 | * tx.igen ("madd", "maddu"): Use. | |
| 776 | (start-sanitize-r5900): | |
| 777 | ||
| 778 | r5900.igen: Update all HI/LO checks. | |
| 779 | ("mfhi1", "mflo1", "mthi1", "mthi1", "pmfhi", "pmflo", "pmfhl", | |
| 780 | "pmthi", "pmtlo", "mpthl"): Check MF/MT HI/LO. | |
| 781 | ("mult1", "div1", "divu1", "multu1", "madd1", "maddu1", "pdivbw", | |
| 782 | "pdivuw", "pdivw", "phmaddh", "phmsubh", "pmaddh", "madduw", | |
| 783 | "pmaddw", "pmsubh", "pmsubw", "pmulth", "pmultuw", "pmultw"): | |
| 784 | Check HI/LO op. | |
| 785 | (end-sanitize-r5900): | |
| 786 | ||
| 787 | start-sanitize-sky | |
| 788 | Mon Apr 20 18:39:47 1998 Frank Ch. Eigler <fche@cygnus.com> | |
| 789 | ||
| 790 | * interp.c (decode_coproc): Correct CMFC2/QMTC2 | |
| 791 | GPR access. | |
| 792 | ||
| 793 | * r5900.igen (LQ,SQ): Use a pair of 64-bit accesses | |
| 794 | instead of a single 128-bit access. | |
| 795 | ||
| 796 | end-sanitize-sky | |
| fc4e5b84 | 797 | start-sanitize-sky |
| f8998e77 FCE |
798 | Fri Apr 17 14:50:39 1998 Frank Ch. Eigler <fche@cygnus.com> |
| 799 | ||
| 800 | * r5900.igen (COP_[LS]Q): Transfer COP2 quadwords. | |
| 801 | * interp.c (cop_[ls]q): Fixes corresponding to above. | |
| 802 | ||
| 803 | end-sanitize-sky | |
| 804 | start-sanitize-sky | |
| fc4e5b84 FCE |
805 | Thu Apr 16 15:24:14 1998 Frank Ch. Eigler <fche@cygnus.com> |
| 806 | ||
| 807 | * interp.c (decode_coproc): Adapt COP2 micro interlock to | |
| 808 | clarified specs. Reset "M" bit; exit also on "E" bit. | |
| 809 | ||
| 810 | end-sanitize-sky | |
| 7d93d538 AC |
811 | start-sanitize-r5900 |
| 812 | Thu Apr 16 10:40:29 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 813 | ||
| 814 | * r5900.igen (CFC1, CTC1): Implement R5900 specific version. | |
| 815 | * mips.igen (CFC1, CTC1): R5900 des not use generic version. | |
| 816 | ||
| 817 | * r5900.igen (r59fp_unpack): New function. | |
| 818 | (r59fp_op1, r59fp_op2, r59fp_op3, C.cond.S, CVT.S.W, DIV.S, | |
| 819 | RSQRT.S, SQRT.S): Use. | |
| 820 | (r59fp_zero): New function. | |
| 821 | (r59fp_overflow): Generate r5900 specific overflow value. | |
| 822 | (r59fp_store): Re-write, overflow to MAX_R5900_FP value, underflow | |
| 823 | to zero. | |
| 824 | (CVT.S.W, CVT.W.S): Exchange implementations. | |
| 825 | ||
| 826 | * sim-main.h (R5900_EXPMAX, R5900_EXPMIN, R5900_EXPBIAS): Defile. | |
| 827 | ||
| 828 | end-sanitize-r5900 | |
| c58fa2cc AC |
829 | start-sanitize-tx19 |
| 830 | Thu Apr 16 09:14:44 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 831 | ||
| 832 | * configure.in (tx19, sim_use_gen): Switch to igen. | |
| 833 | * configure: Re-build. | |
| 834 | ||
| 835 | end-sanitize-tx19 | |
| 836 | start-sanitize-sky | |
| 46399a00 FCE |
837 | Wed Apr 15 12:41:18 1998 Frank Ch. Eigler <fche@cygnus.com> |
| 838 | ||
| 839 | * interp.c (decode_coproc): Make COP2 branch code compile after | |
| 840 | igen signature changes. | |
| 841 | ||
| 842 | end-sanitize-sky | |
| 74025eee AC |
843 | Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com> |
| 844 | ||
| 845 | * mips.igen (DSRAV): Use function do_dsrav. | |
| 846 | (SRAV): Use new function do_srav. | |
| 847 | ||
| 848 | * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX]. | |
| 849 | (B): Sign extend 11 bit immediate. | |
| 850 | (EXT-B*): Shift 16 bit immediate left by 1. | |
| 851 | (ADDIU*): Don't sign extend immediate value. | |
| 852 | ||
| f3bdd368 AC |
853 | Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com> |
| 854 | ||
| 855 | * m16run.c (sim_engine_run): Restore CIA after handling an event. | |
| 856 | ||
| 857 | start-sanitize-tx19 | |
| 858 | * mips.igen (mtc0): Valid tx19 instruction. | |
| 859 | ||
| 860 | end-sanitize-tx19 | |
| 861 | * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use | |
| 862 | functions. | |
| 863 | ||
| 864 | * mips.igen (delayslot32, nullify_next_insn): New functions. | |
| 865 | (m16.igen): Always include. | |
| 866 | (do_*): Add more tracing. | |
| 867 | ||
| 868 | * m16.igen (delayslot16): Add NIA argument, could be called by a | |
| 869 | 32 bit MIPS16 instruction. | |
| 870 | ||
| 871 | * interp.c (ifetch16): Move function from here. | |
| 872 | * sim-main.c (ifetch16): To here. | |
| 873 | ||
| 874 | * sim-main.c (ifetch16, ifetch32): Update to match current | |
| 875 | implementations of LH, LW. | |
| 876 | (signal_exception): Don't print out incorrect hex value of illegal | |
| 877 | instruction. | |
| 878 | ||
| c0a4c3ba AC |
879 | Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com> |
| 880 | ||
| 881 | * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an | |
| 882 | instruction. | |
| 883 | ||
| 884 | * m16.igen: Implement MIPS16 instructions. | |
| 885 | ||
| 886 | * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu, | |
| 887 | do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav, | |
| 888 | do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or, | |
| 889 | do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra, | |
| 890 | do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move | |
| 891 | bodies of corresponding code from 32 bit insn to these. Also used | |
| 892 | by MIPS16 versions of functions. | |
| 893 | ||
| 894 | * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define. | |
| 895 | (IMEM16): Drop NR argument from macro. | |
| 896 | ||
| 96a4eb30 | 897 | start-sanitize-sky |
| c0a4c3ba | 898 | Mon Apr 13 16:28:52 1998 Frank Ch. Eigler <fche@cygnus.com> |
| 96a4eb30 FCE |
899 | |
| 900 | * interp.c (decode_coproc): Add proper 1000000 bit-string at top | |
| 901 | of VU lower instruction. | |
| 902 | ||
| 903 | end-sanitize-sky | |
| b0b39eb2 FCE |
904 | start-sanitize-sky |
| 905 | Thu Apr 9 16:38:23 1998 Frank Ch. Eigler <fche@cygnus.com> | |
| 906 | ||
| 907 | * r5900.igen (LQC,SQC): Adapted code to DOUBLEWORD accesses | |
| 908 | instead of QUADWORD. | |
| 909 | ||
| 910 | * sim-main.h: Removed attempt at allowing 128-bit access. | |
| 911 | ||
| 912 | end-sanitize-sky | |
| 11c47f31 | 913 | start-sanitize-sky |
| c0a4c3ba | 914 | Wed Apr 8 18:12:13 1998 Frank Ch. Eigler <fche@cygnus.com> |
| 11c47f31 FCE |
915 | |
| 916 | * Makefile.in (SIM_SKY_OBJS): Added sky-vudis.o. | |
| 917 | ||
| 918 | * interp.c (decode_coproc): Refer to VU CIA as a "special" | |
| 919 | register, not as a "misc" register. Aha. Add activity | |
| 920 | assertions after VCALLMS* instructions. | |
| 921 | ||
| 922 | end-sanitize-sky | |
| 174ff224 | 923 | start-sanitize-sky |
| c0a4c3ba | 924 | Tue Apr 7 18:32:49 1998 Frank Ch. Eigler <fche@cygnus.com> |
| 174ff224 FCE |
925 | |
| 926 | * interp.c (decode_coproc): Do not apply superfluous E (end) flag | |
| 927 | to upper code of generated VU instruction. | |
| 928 | ||
| 929 | end-sanitize-sky | |
| 2ebb2a68 FCE |
930 | start-sanitize-sky |
| 931 | Mon Apr 6 19:55:56 1998 Frank Ch. Eigler <fche@cygnus.com> | |
| 932 | ||
| 933 | * interp.c (cop_[ls]q): Replaced stub with proper COP2 code. | |
| 934 | ||
| 935 | * sim-main.h (LOADADDRMASK): Redefine to allow 128-bit accesses | |
| 936 | for TARGET_SKY. | |
| 937 | ||
| 938 | * r5900.igen (SQC2): Thinko. | |
| 939 | ||
| 940 | end-sanitize-sky | |
| ebcfd86a FCE |
941 | start-sanitize-sky |
| 942 | Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> | |
| 943 | ||
| 944 | * interp.c (*): Adapt code to merged VU device & state structs. | |
| 945 | (decode_coproc): Execute COP2 each macroinstruction without | |
| 946 | pipelining, by stepping VU to completion state. Adapted to | |
| 947 | read_vu_*_reg style of register access. | |
| 948 | ||
| 949 | * mips.igen ([SL]QC2): Removed these COP2 instructions. | |
| 950 | ||
| 951 | * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. | |
| 952 | ||
| 953 | * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. | |
| 954 | ||
| 955 | end-sanitize-sky | |
| 64ed8b6a AC |
956 | Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com> |
| 957 | ||
| 958 | * Makefile.in (SIM_OBJS): Add sim-main.o. | |
| 959 | ||
| 960 | * sim-main.h (address_translation, load_memory, store_memory, | |
| 961 | cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark | |
| 962 | as INLINE_SIM_MAIN. | |
| 963 | (pr_addr, pr_uword64): Declare. | |
| 964 | (sim-main.c): Include when H_REVEALS_MODULE_P. | |
| 965 | ||
| 966 | * interp.c (address_translation, load_memory, store_memory, | |
| 967 | cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move | |
| 968 | from here. | |
| 969 | * sim-main.c: To here. Fix compilation problems. | |
| 970 | ||
| 971 | * configure.in: Enable inlining. | |
| 972 | * configure: Re-config. | |
| 973 | ||
| 278bda40 AC |
974 | Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com> |
| 975 | ||
| 976 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 977 | ||
| 978 | Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 979 | ||
| 980 | * mips.igen: Include tx.igen. | |
| 981 | * Makefile.in (IGEN_INCLUDE): Add tx.igen. | |
| 982 | * tx.igen: New file, contains MADD and MADDU. | |
| 983 | ||
| 984 | * interp.c (load_memory): When shifting bytes, use LOADDRMASK not | |
| 985 | the hardwired constant `7'. | |
| 986 | (store_memory): Ditto. | |
| 987 | (LOADDRMASK): Move definition to sim-main.h. | |
| 988 | ||
| 989 | mips.igen (MTC0): Enable for r3900. | |
| 990 | (ADDU): Add trace. | |
| 991 | ||
| 992 | mips.igen (do_load_byte): Delete. | |
| 993 | (do_load, do_store, do_load_left, do_load_write, do_store_left, | |
| 994 | do_store_right): New functions. | |
| 995 | (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use. | |
| 996 | ||
| 997 | configure.in: Let the tx39 use igen again. | |
| 998 | configure: Update. | |
| 999 | ||
| 725fc5d9 AC |
1000 | Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com> |
| 1001 | ||
| 1002 | * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity, | |
| 1003 | not an address sized quantity. Return zero for cache sizes. | |
| 1004 | ||
| 1005 | Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1006 | ||
| 1007 | * mips.igen (r3900): r3900 does not support 64 bit integer | |
| 1008 | operations. | |
| 1009 | ||
| 6b0c51c9 FCE |
1010 | start-sanitize-sky |
| 1011 | Wed Apr 1 08:20:31 1998 Frank Ch. Eigler <fche@cygnus.com> | |
| 1012 | ||
| 1013 | * mips.igen (SQC2/LQC2): Make bodies sky-target-only also. | |
| 6b0c51c9 | 1014 | |
| 725fc5d9 | 1015 | end-sanitize-sky |
| 6ed00b06 FCE |
1016 | start-sanitize-sky |
| 1017 | Mon Mar 30 18:41:43 1998 Frank Ch. Eigler <fche@cygnus.com> | |
| 1018 | ||
| 1019 | * interp.c (decode_coproc): Continuing COP2 work. | |
| 6b0c51c9 | 1020 | (cop_[ls]q): Make sky-target-only. |
| 6ed00b06 | 1021 | |
| 6b0c51c9 | 1022 | * sim-main.h (COP_[LS]Q): Make sky-target-only. |
| 6ed00b06 | 1023 | end-sanitize-sky |
| 34f51d87 GRK |
1024 | Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com> |
| 1025 | ||
| 1026 | * configure.in (mipstx39*-*-*): Use gencode simulator rather | |
| 1027 | than igen one. | |
| 1028 | * configure : Rebuild. | |
| 1029 | ||
| 7dd4a466 FCE |
1030 | start-sanitize-sky |
| 1031 | Sun Mar 29 17:50:11 Frank Ch. Eigler <fche@cygnus.com> | |
| 1032 | ||
| 1033 | * interp.c (decode_coproc): Added a missing TARGET_SKY check | |
| 1034 | around COP2 implementation skeleton. | |
| 1035 | ||
| 1036 | end-sanitize-sky | |
| 7dba069e | 1037 | start-sanitize-sky |
| 15232df4 FCE |
1038 | Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com> |
| 1039 | ||
| 15232df4 FCE |
1040 | * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o. |
| 1041 | ||
| 1042 | * interp.c (sim_{load,store}_register): Use new vu[01]_device | |
| 1043 | static to access VU registers. | |
| 1044 | (decode_coproc): Added skeleton of sky COP2 (VU) instruction | |
| 1045 | decoding. Work in progress. | |
| 1046 | ||
| 1047 | * mips.igen (LDCzz, SDCzz): Removed *5900 case for this | |
| 1048 | overlapping/redundant bit pattern. | |
| 1049 | (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in | |
| 1050 | progress. | |
| 1051 | ||
| 1052 | * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for | |
| 1053 | status register. | |
| 1054 | ||
| 15232df4 FCE |
1055 | * interp.c (cop_lq, cop_sq): New functions for future 128-bit |
| 1056 | access to coprocessor registers. | |
| 1057 | ||
| 1058 | * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above. | |
| 6ed00b06 | 1059 | end-sanitize-sky |
| d8f53049 AC |
1060 | Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com> |
| 1061 | ||
| 1062 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 1063 | ||
| 82ea14fd AC |
1064 | Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com> |
| 1065 | ||
| 1066 | * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS. | |
| 1067 | ||
| 1068 | Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com> | |
| 1069 | ||
| 1070 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 1071 | * config.in: Regenerated to track ../common/aclocal.m4 changes. | |
| 1072 | ||
| d89fa2d8 AC |
1073 | Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com> |
| 1074 | ||
| 1075 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 1076 | ||
| 612a649e AC |
1077 | Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com> |
| 1078 | ||
| 1079 | * interp.c (Max, Min): Comment out functions. Not yet used. | |
| 1080 | ||
| 1081 | start-sanitize-vr4320 | |
| 1082 | Wed Mar 25 10:04:13 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1083 | ||
| 1084 | * vr4320.igen (DCLZ): Pacify GCC, 64 bit arg, int format. | |
| 1085 | ||
| 1086 | end-sanitize-vr4320 | |
| 1087 | Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1088 | ||
| 1089 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 1090 | ||
| 9b23b76d FCE |
1091 | Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com> |
| 1092 | ||
| 1093 | * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added | |
| 1094 | configurable settings for stand-alone simulator. | |
| 1095 | ||
| 1096 | start-sanitize-sky | |
| 1097 | * configure.in: Added --with-sim-gpu2 option to specify path of | |
| 1098 | sky GPU2 library. Triggers -DSKY_GPU2 for sky-gpuif.c, and | |
| 1099 | links/compiles stand-alone simulator with this library. | |
| 1100 | ||
| 1101 | * interp.c (MEM_SIZE): Increased default sky memory size to 16MB. | |
| 1102 | end-sanitize-sky | |
| 9b23b76d FCE |
1103 | * configure.in: Added X11 search, just in case. |
| 1104 | ||
| 1105 | * configure: Regenerated. | |
| 1106 | ||
| 1107 | Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1108 | ||
| 1109 | * interp.c (sim_write, sim_read, load_memory, store_memory): | |
| 1110 | Replace sim_core_*_map with read_map, write_map, exec_map resp. | |
| 1111 | ||
| 5fa71251 GRK |
1112 | start-sanitize-vr4320 |
| 1113 | Tue Mar 10 10:32:22 1998 Gavin Koch <gavin@cygnus.com> | |
| 1114 | ||
| 1115 | * vr4320.igen (clz,dclz) : Added. | |
| 1116 | (dmac): Replaced 99, with LO. | |
| 1117 | ||
| 1118 | end-sanitize-vr4320 | |
| 78b871ec | 1119 | start-sanitize-cygnus |
| 6ba4c153 AC |
1120 | Fri Mar 6 08:30:58 1998 Andrew Cagney <cagney@b1.cygnus.com> |
| 1121 | ||
| 1122 | * mdmx.igen (SHFL.REPA.fmt, SHFL.REPB.fmt): Fix bit fields. | |
| 1123 | ||
| 78b871ec | 1124 | end-sanitize-cygnus |
| dd15abd5 GRK |
1125 | start-sanitize-vr4320 |
| 1126 | Tue Mar 3 11:56:29 1998 Gavin Koch <gavin@cygnus.com> | |
| 1127 | ||
| 1128 | * vr4320.igen: New file. | |
| 1129 | * Makefile.in (vr4320.igen) : Added. | |
| 1130 | * configure.in (mips64vr4320-*-*): Added. | |
| 1131 | * configure : Rebuilt. | |
| 1132 | * mips.igen : Correct the bfd-names in the mips-ISA model entries. | |
| 1133 | Add the vr4320 model entry and mark the vr4320 insn as necessary. | |
| 1134 | ||
| 1135 | end-sanitize-vr4320 | |
| ca6f76d1 AC |
1136 | Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com> |
| 1137 | ||
| 1138 | * sim-main.h (GETFCC): Return an unsigned value. | |
| 1139 | ||
| 1140 | start-sanitize-r5900 | |
| 1141 | * r5900.igen: Use an unsigned array index variable `i'. | |
| 1142 | (QFSRV): Ditto for variable bytes. | |
| 1143 | ||
| 1144 | end-sanitize-r5900 | |
| 1145 | Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1146 | ||
| 1147 | * mips.igen (DIV): Fix check for -1 / MIN_INT. | |
| 1148 | (DADD): Result destination is RD not RT. | |
| 1149 | ||
| 1150 | start-sanitize-r5900 | |
| 1151 | * r5900.igen (DIV1): Fix check for -1 / MIN_INT. | |
| 1152 | (DIVU1): Don't check for MIN_INT / -1 as performing unsigned | |
| 1153 | divide. | |
| 1154 | ||
| 1155 | end-sanitize-r5900 | |
| 0e701ac3 AC |
1156 | Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com> |
| 1157 | ||
| 1158 | * sim-main.h (HIACCESS, LOACCESS): Always define. | |
| 1159 | ||
| 1160 | * mdmx.igen (Maxi, Mini): Rename Max, Min. | |
| 1161 | ||
| 1162 | * interp.c (sim_info): Delete. | |
| 1163 | ||
| 7c5d88c1 DE |
1164 | Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com> |
| 1165 | ||
| 1166 | * interp.c (DECLARE_OPTION_HANDLER): Use it. | |
| 1167 | (mips_option_handler): New argument `cpu'. | |
| 1168 | (sim_open): Update call to sim_add_option_table. | |
| 1169 | ||
| f89c0689 AC |
1170 | Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com> |
| 1171 | ||
| 1172 | * mips.igen (CxC1): Add tracing. | |
| 1173 | ||
| 1174 | start-sanitize-r5900 | |
| 1175 | Wed Feb 25 13:59:03 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1176 | ||
| 1177 | * r5900.igen (StoreFP): Delete. | |
| 1178 | (r59fp_store, r59fp_overflow, r59fp_op1, r59fp_op2, r59fp_op3): | |
| 1179 | New functions. | |
| 1180 | (rsqrt.s, sqrt.s): Implement. | |
| 1181 | (r59cond): New function. | |
| 1182 | (C.COND.S): Call r59cond in assembler line. | |
| 1183 | (cvt.w.s, cvt.s.w): Implement. | |
| 1184 | ||
| 1185 | * mips.igen (rsqrt.fmt, sqrt.fmt, cvt.*.*): Remove from r5900 | |
| 1186 | instruction set. | |
| 1187 | ||
| 1188 | * sim-main.h: Define an enum of r5900 FCSR bit fields. | |
| 1189 | ||
| 1190 | end-sanitize-r5900 | |
| a48e8c8d | 1191 | start-sanitize-r5900 |
| d3e1d594 AC |
1192 | Tue Feb 24 14:44:18 1998 Andrew Cagney <cagney@b1.cygnus.com> |
| 1193 | ||
| 1194 | * r5900.igen: Add tracing to all p* instructions. | |
| 1195 | ||
| a48e8c8d AC |
1196 | Tue Feb 24 02:47:33 1998 Andrew Cagney <cagney@b1.cygnus.com> |
| 1197 | ||
| 1198 | * interp.c (sim_store_register, sim_fetch_register): Pull swifty | |
| 1199 | to get gdb talking to re-aranged sim_cpu register structure. | |
| 1200 | ||
| 1201 | end-sanitize-r5900 | |
| 1202 | Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1203 | ||
| 1204 | * sim-main.h (Max, Min): Declare. | |
| 1205 | ||
| 1206 | * interp.c (Max, Min): New functions. | |
| 1207 | ||
| 1208 | * mips.igen (BC1): Add tracing. | |
| 1209 | ||
| 78b871ec | 1210 | start-sanitize-cygnus |
| a48e8c8d AC |
1211 | Fri Feb 20 16:27:17 1998 Andrew Cagney <cagney@b1.cygnus.com> |
| 1212 | ||
| 1213 | * mdmx.igen: Tag all functions as requiring either with mdmx or | |
| 1214 | vr5400 processor. | |
| 1215 | ||
| 78b871ec | 1216 | end-sanitize-cygnus |
| a48e8c8d AC |
1217 | start-sanitize-r5900 |
| 1218 | Fri Feb 20 15:55:51 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1219 | ||
| 1220 | * configure.in (SIM_AC_OPTION_FLOAT): For r5900, set FP bit size | |
| 1221 | to 32. | |
| 1222 | (SIM_AC_OPTION_BITSIZE): For r5900, set nr address bits to 32. | |
| 1223 | ||
| 1224 | * mips.igen (C.cond.fmt, ..): Not part of r5900 insn set. | |
| 1225 | ||
| 1226 | * r5900.igen: Rewrite. | |
| 1227 | ||
| 1228 | * sim-main.h: Move r5900 registers to a separate _sim_r5900_cpu | |
| 1229 | struct. | |
| 1230 | (GPR_SB, GPR_SH, GPR_SW, GPR_SD, GPR_UB, GPR_UH, GPR_UW, GPR_UD): | |
| 1231 | Define in terms of GPR/GPR1 instead of REGISTERS/REGISTERS.1 | |
| 1232 | ||
| 1233 | end-sanitize-r5900 | |
| 1234 | Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com> | |
| 1235 | ||
| 1236 | * interp.c Added memory map for stack in vr4100 | |
| 1237 | ||
| f319bab2 GRK |
1238 | Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com> |
| 1239 | ||
| 1240 | * interp.c (load_memory): Add missing "break"'s. | |
| 1241 | ||
| 1242 | Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1243 | ||
| 1244 | * interp.c (sim_store_register, sim_fetch_register): Pass in | |
| 1245 | length parameter. Return -1. | |
| 1246 | ||
| 1247 | Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com> | |
| 1248 | ||
| 1249 | * interp.c: Added hardware init hook, fixed warnings. | |
| 1250 | ||
| 452b3808 AC |
1251 | Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com> |
| 1252 | ||
| 1253 | * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL. | |
| 1254 | ||
| 37379a25 AC |
1255 | Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com> |
| 1256 | ||
| 1257 | * interp.c (ifetch16): New function. | |
| 1258 | ||
| 1259 | * sim-main.h (IMEM32): Rename IMEM. | |
| 1260 | (IMEM16_IMMED): Define. | |
| 1261 | (IMEM16): Define. | |
| 1262 | (DELAY_SLOT): Update. | |
| 1263 | ||
| 1264 | * m16run.c (sim_engine_run): New file. | |
| 1265 | ||
| 1266 | * m16.igen: All instructions except LB. | |
| 1267 | (LB): Call do_load_byte. | |
| 1268 | * mips.igen (do_load_byte): New function. | |
| 1269 | (LB): Call do_load_byte. | |
| 1270 | ||
| 1271 | * mips.igen: Move spec for insn bit size and high bit from here. | |
| 1272 | * Makefile.in (tmp-igen, tmp-m16): To here. | |
| 1273 | ||
| 1274 | * m16.dc: New file, decode mips16 instructions. | |
| 1275 | ||
| 1276 | * Makefile.in (SIM_NO_ALL): Define. | |
| 1277 | (tmp-m16): Generate both 16 bit and 32 bit simulator engines. | |
| 1278 | ||
| 1279 | start-sanitize-tx19 | |
| 1280 | * m16.igen: Mark all mips16 insns as being part of the tx19 insn | |
| 1281 | set. | |
| 1282 | ||
| 1283 | end-sanitize-tx19 | |
| 1284 | Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1285 | ||
| 1286 | * configure.in (mips_fpu_bitsize): For tx39, restrict floating | |
| 1287 | point unit to 32 bit registers. | |
| 1288 | * configure: Re-generate. | |
| 1289 | ||
| 1290 | Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1291 | ||
| 1292 | * configure.in (sim_use_gen): Make IGEN the default simulator | |
| 1293 | generator for generic 32 and 64 bit mips targets. | |
| 1294 | * configure: Re-generate. | |
| 1295 | ||
| a97f304b AC |
1296 | Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com> |
| 1297 | ||
| 1298 | * sim-main.h (SizeFGR): Determine from floating-point and not gpr | |
| 1299 | bitsize. | |
| 1300 | ||
| 1301 | * interp.c (sim_fetch_register, sim_store_register): Read/write | |
| 1302 | FGR from correct location. | |
| 1303 | (sim_open): Set size of FGR's according to | |
| 1304 | WITH_TARGET_FLOATING_POINT_BITSIZE. | |
| 1305 | ||
| 1306 | * sim-main.h (FGR): Store floating point registers in a separate | |
| 1307 | array. | |
| 1308 | ||
| 1309 | Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1310 | ||
| 1311 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 1312 | ||
| 78b871ec | 1313 | start-sanitize-cygnus |
| a97f304b AC |
1314 | * mdmx.igen: Mark all instructions as 64bit/fp specific. |
| 1315 | ||
| 78b871ec | 1316 | end-sanitize-cygnus |
| 2acd126a AC |
1317 | Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com> |
| 1318 | ||
| 1319 | * interp.c (ColdReset): Call PENDING_INVALIDATE. | |
| 1320 | ||
| 1321 | * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK. | |
| 1322 | ||
| 1323 | * interp.c (pending_tick): New function. Deliver pending writes. | |
| 1324 | ||
| 1325 | * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED, | |
| 1326 | PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that | |
| 1327 | it can handle mixed sized quantites and single bits. | |
| 1328 | ||
| 192ae475 AC |
1329 | Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com> |
| 1330 | ||
| 1331 | * interp.c (oengine.h): Do not include when building with IGEN. | |
| 1332 | (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE. | |
| 1333 | (sim_info): Ditto for PROCESSOR_64BIT. | |
| 1334 | (sim_monitor): Replace ut_reg with unsigned_word. | |
| 1335 | (*): Ditto for t_reg. | |
| 1336 | (LOADDRMASK): Define. | |
| 1337 | (sim_open): Remove defunct check that host FP is IEEE compliant, | |
| 1338 | using software to emulate floating point. | |
| 1339 | (value_fpr, ...): Always compile, was conditional on HASFPU. | |
| 1340 | ||
| 01737f42 AC |
1341 | Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com> |
| 1342 | ||
| 1343 | * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in | |
| 1344 | size. | |
| 1345 | ||
| 1346 | * interp.c (SD, CPU): Define. | |
| 1347 | (mips_option_handler): Set flags in each CPU. | |
| 1348 | (interrupt_event): Assume CPU 0 is the one being iterrupted. | |
| 1349 | (sim_close): Do not clear STATE, deleted anyway. | |
| 1350 | (sim_write, sim_read): Assume CPU zero's vm should be used for | |
| 1351 | data transfers. | |
| 1352 | (sim_create_inferior): Set the PC for all processors. | |
| 1353 | (sim_monitor, store_word, load_word, mips16_entry): Add cpu | |
| 1354 | argument. | |
| 1355 | (mips16_entry): Pass correct nr of args to store_word, load_word. | |
| 1356 | (ColdReset): Cold reset all cpu's. | |
| 1357 | (signal_exception): Pass cpu to sim_monitor & mips16_entry. | |
| 1358 | (sim_monitor, load_memory, store_memory, signal_exception): Use | |
| 1359 | `CPU' instead of STATE_CPU. | |
| 1360 | ||
| 1361 | ||
| 1362 | * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with | |
| 1363 | SD or CPU_. | |
| 1364 | ||
| 1365 | * sim-main.h (signal_exception): Add sim_cpu arg. | |
| 1366 | (SignalException*): Pass both SD and CPU to signal_exception. | |
| 1367 | * interp.c (signal_exception): Update. | |
| 1368 | ||
| 1369 | * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c: | |
| 1370 | Ditto | |
| 1371 | (sync_operation, prefetch, cache_op, store_memory, load_memory, | |
| 1372 | address_translation): Ditto | |
| 1373 | (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto. | |
| 1374 | ||
| 78b871ec | 1375 | start-sanitize-cygnus |
| 01737f42 AC |
1376 | * mdmx.igen (get_scale): Pass CPU_ to semantic_illegal instead of |
| 1377 | `sd'. | |
| 1378 | (ByteAlign): Use StoreFPR, pass args in correct order. | |
| 1379 | ||
| 78b871ec | 1380 | end-sanitize-cygnus |
| 01737f42 AC |
1381 | start-sanitize-r5900 |
| 1382 | Sun Feb 1 10:59:55 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1383 | ||
| 1384 | * configure.in (sim_igen_filter): For r5900, configure as SMP. | |
| 1385 | ||
| 1386 | end-sanitize-r5900 | |
| 412c4e94 AC |
1387 | Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com> |
| 1388 | ||
| 1389 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 1390 | ||
| 9ec6741b AC |
1391 | Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com> |
| 1392 | ||
| c4db5b04 AC |
1393 | start-sanitize-r5900 |
| 1394 | * configure.in (sim_igen_filter): For r5900, use igen. | |
| 1395 | * configure: Re-generate. | |
| 1396 | ||
| 1397 | end-sanitize-r5900 | |
| 9ec6741b AC |
1398 | * interp.c (sim_engine_run): Add `nr_cpus' argument. |
| 1399 | ||
| 1400 | * mips.igen (model): Map processor names onto BFD name. | |
| 1401 | ||
| 1402 | * sim-main.h (CPU_CIA): Delete. | |
| 1403 | (SET_CIA, GET_CIA): Define | |
| 1404 | ||
| 2d44e12a AC |
1405 | Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com> |
| 1406 | ||
| 1407 | * sim-main.h (GPR_SET): Define, used by igen when zeroing a | |
| 1408 | regiser. | |
| 1409 | ||
| 1410 | * configure.in (default_endian): Configure a big-endian simulator | |
| 1411 | by default. | |
| 1412 | * configure: Re-generate. | |
| 1413 | ||
| 462cfbc4 DE |
1414 | Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba> |
| 1415 | ||
| 1416 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 1417 | ||
| e0e0fc76 MA |
1418 | Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com> |
| 1419 | ||
| 1420 | * interp.c (sim_monitor): Handle Densan monitor outbyte | |
| 1421 | and inbyte functions. | |
| 1422 | ||
| 76ef4165 FL |
1423 | 1997-12-29 Felix Lee <flee@cygnus.com> |
| 1424 | ||
| 1425 | * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c). | |
| 1426 | ||
| 1427 | Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com) | |
| 1428 | ||
| 1429 | * Makefile.in (tmp-igen): Arrange for $zero to always be | |
| 1430 | reset to zero after every instruction. | |
| 1431 | ||
| 9c8ec16d AC |
1432 | Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com> |
| 1433 | ||
| 1434 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 1435 | * config.in: Ditto. | |
| 1436 | ||
| 78b871ec | 1437 | start-sanitize-cygnus |
| b17d2d14 AC |
1438 | Sat Dec 13 15:18:51 1997 Andrew Cagney <cagney@b1.cygnus.com> |
| 1439 | ||
| 1440 | * vr5400.igen (Low32Bits, High32Bits): Sign extend extracted 32 | |
| 1441 | bit values. | |
| 1442 | ||
| 255cbbf1 JL |
1443 | Fri Dec 12 12:26:07 1997 Jeffrey A Law (law@cygnus.com) |
| 1444 | ||
| 1445 | * configure.in (sim_igen_filter): Multi-sim vr5000 - vr5000 or | |
| 1446 | vr5400 with the vr5000 as the default. | |
| 1447 | ||
| 78b871ec | 1448 | end-sanitize-cygnus |
| 23850e92 JL |
1449 | Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com) |
| 1450 | ||
| 1451 | * mips.igen (MSUB): Fix to work like MADD. | |
| 1452 | * gencode.c (MSUB): Similarly. | |
| 1453 | ||
| 78b871ec | 1454 | start-sanitize-cygnus |
| c02ed6a8 AC |
1455 | Tue Dec 9 12:02:12 1997 Andrew Cagney <cagney@b1.cygnus.com> |
| 1456 | ||
| 1457 | * configure.in (sim_igen_filter): Multi-sim vr5400 - vr5000 or | |
| 1458 | vr5400. | |
| 1459 | ||
| 78b871ec | 1460 | end-sanitize-cygnus |
| 6e51f990 DE |
1461 | Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com> |
| 1462 | ||
| 1463 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 1464 | ||
| 35c246c9 AC |
1465 | Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com> |
| 1466 | ||
| 1467 | * mips.igen (LWC1): Correct assembler - lwc1 not swc1. | |
| 1468 | ||
| 78b871ec | 1469 | start-sanitize-cygnus |
| 0d5d0d10 | 1470 | * mdmx.igen (value_vr): Correct sim_io_eprintf format argument. |
| 0931ce5a | 1471 | (value_cc, store_cc): Implement. |
| 0d5d0d10 | 1472 | |
| 35c246c9 AC |
1473 | * sim-main.h: Add 8*3*8 bit accumulator. |
| 1474 | ||
| 1475 | * vr5400.igen: Move mdmx instructins from here | |
| 1476 | * mdmx.igen: To here - new file. Add/fix missing instructions. | |
| 1477 | * mips.igen: Include mdmx.igen. | |
| 0931ce5a | 1478 | * Makefile.in (IGEN_INCLUDE): Add mdmx.igen. |
| 35c246c9 | 1479 | |
| 78b871ec | 1480 | end-sanitize-cygnus |
| 58fb5d0a AC |
1481 | Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com> |
| 1482 | ||
| 1483 | * sim-main.h (sim-fpu.h): Include. | |
| 1484 | ||
| 1485 | * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub, | |
| 1486 | Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite | |
| 1487 | using host independant sim_fpu module. | |
| 1488 | ||
| a09a30d2 AC |
1489 | Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com> |
| 1490 | ||
| 232156de AC |
1491 | * interp.c (signal_exception): Report internal errors with SIGABRT |
| 1492 | not SIGQUIT. | |
| a09a30d2 | 1493 | |
| 232156de AC |
1494 | * sim-main.h (C0_CONFIG): New register. |
| 1495 | (signal.h): No longer include. | |
| 1496 | ||
| 1497 | * interp.c (decode_coproc): Allow access C0_CONFIG to register. | |
| a09a30d2 | 1498 | |
| 486740ce DE |
1499 | Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com> |
| 1500 | ||
| 1501 | * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS). | |
| 1502 | ||
| f23e93da AC |
1503 | Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com> |
| 1504 | ||
| 1505 | * mips.igen: Tag vr5000 instructions. | |
| 1506 | (ANDI): Was missing mipsIV model, fix assembler syntax. | |
| 1507 | (do_c_cond_fmt): New function. | |
| 1508 | (C.cond.fmt): Handle mips I-III which do not support CC field | |
| 1509 | separatly. | |
| 1510 | (bc1): Handle mips IV which do not have a delaed FCC separatly. | |
| 1511 | (SDR): Mask paddr when BigEndianMem, not the converse as specified | |
| 1512 | in IV3.2 spec. | |
| 1513 | (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle | |
| 1514 | vr5000 which saves LO in a GPR separatly. | |
| 1515 | ||
| 1516 | * configure.in (enable-sim-igen): For vr5000, select vr5000 | |
| 1517 | specific instructions. | |
| 1518 | * configure: Re-generate. | |
| 1519 | ||
| 1520 | Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1521 | ||
| 1522 | * Makefile.in (SIM_OBJS): Add sim-fpu module. | |
| 1523 | ||
| 1524 | * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and | |
| 1525 | fmt_uninterpreted_64 bit cases to switch. Convert to | |
| 1526 | fmt_formatted, | |
| 1527 | ||
| 1528 | * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define, | |
| 1529 | ||
| 1530 | * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse | |
| 1531 | as specified in IV3.2 spec. | |
| 1532 | (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR. | |
| 1533 | ||
| 030843d7 AC |
1534 | Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com> |
| 1535 | ||
| 1536 | * mips.igen: Delay slot branches add OFFSET to NIA not CIA. | |
| 1537 | (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement. | |
| 1538 | (start-sanitize-r5900): | |
| 1539 | (LWXC1, SWXC1): Delete from r5900 instruction set. | |
| 1540 | (end-sanitize-r5900): | |
| 1541 | (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non | |
| a94c5493 | 1542 | PENDING_FILL versions of instructions. Simplify. |
| 030843d7 AC |
1543 | (X): New function. |
| 1544 | (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of | |
| 1545 | instructions. | |
| a94c5493 AC |
1546 | (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to |
| 1547 | a signed value. | |
| 030843d7 AC |
1548 | (MTHI, MFHI): Disable code checking HI-LO. |
| 1549 | ||
| 1550 | * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh | |
| 1551 | global. | |
| 1552 | (NULLIFY_NEXT_INSTRUCTION): Call dotrace. | |
| 1553 | ||
| 7ce8b917 AC |
1554 | Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com> |
| 1555 | ||
| 95469ceb AC |
1556 | * gencode.c (build_mips16_operands): Replace IPC with cia. |
| 1557 | ||
| 1558 | * interp.c (sim_monitor, signal_exception, cache_op, store_fpr, | |
| 1559 | value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace | |
| 1560 | IPC to `cia'. | |
| 1561 | (UndefinedResult): Replace function with macro/function | |
| 1562 | combination. | |
| 1563 | (sim_engine_run): Don't save PC in IPC. | |
| 1564 | ||
| 1565 | * sim-main.h (IPC): Delete. | |
| 1566 | ||
| 78b871ec | 1567 | start-sanitize-cygnus |
| 95469ceb AC |
1568 | * vr5400.igen (vr): Add missing cia argument to value_fpr. |
| 1569 | (do_select): Rename function select. | |
| 78b871ec | 1570 | end-sanitize-cygnus |
| 95469ceb | 1571 | |
| 7ce8b917 AC |
1572 | * interp.c (signal_exception, store_word, load_word, |
| 1573 | address_translation, load_memory, store_memory, cache_op, | |
| 1574 | prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert, | |
| 95469ceb AC |
1575 | cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add |
| 1576 | current instruction address - cia - argument. | |
| 7ce8b917 AC |
1577 | (sim_read, sim_write): Call address_translation directly. |
| 1578 | (sim_engine_run): Rename variable vaddr to cia. | |
| 95469ceb AC |
1579 | (signal_exception): Pass cia to sim_monitor |
| 1580 | ||
| 7ce8b917 AC |
1581 | * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp, |
| 1582 | Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW, | |
| 1583 | COP_LD, COP_SW, COP_SD, DecodeCoproc): Update. | |
| 1584 | ||
| 1585 | * sim-main.h (SignalExceptionSimulatorFault): Delete definition. | |
| 1586 | * interp.c (sim_open): Replace SignalExceptionSimulatorFault with | |
| 1587 | SIM_ASSERT. | |
| 1588 | ||
| 1589 | * interp.c (signal_exception): Pass restart address to | |
| 1590 | sim_engine_restart. | |
| 1591 | ||
| 1592 | * Makefile.in (semantics.o, engine.o, support.o, itable.o, | |
| 1593 | idecode.o): Add dependency. | |
| 1594 | ||
| 1595 | * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK): | |
| 1596 | Delete definitions | |
| 1597 | (DELAY_SLOT): Update NIA not PC with branch address. | |
| 1598 | (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next. | |
| 1599 | ||
| 1600 | * mips.igen: Use CIA not PC in branch calculations. | |
| 1601 | (illegal): Call SignalException. | |
| 1602 | (BEQ, ADDIU): Fix assembler. | |
| 1603 | ||
| 63be8feb AC |
1604 | Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com> |
| 1605 | ||
| 44b8585a AC |
1606 | * m16.igen (JALX): Was missing. |
| 1607 | ||
| 1608 | * configure.in (enable-sim-igen): New configuration option. | |
| 1609 | * configure: Re-generate. | |
| 1610 | ||
| 63be8feb AC |
1611 | * sim-main.h (MAX_INSNS, INSN_NAME): Define. |
| 1612 | ||
| 1613 | * interp.c (load_memory, store_memory): Delete parameter RAW. | |
| 1614 | (sim_read, sim_write): Use sim_core_{read,write}_buffer directly | |
| 1615 | bypassing {load,store}_memory. | |
| 1616 | ||
| 1617 | * sim-main.h (ByteSwapMem): Delete definition. | |
| 1618 | ||
| 1619 | * Makefile.in (SIM_OBJS): Add sim-memopt module. | |
| 1620 | ||
| 1621 | * interp.c (sim_do_command, sim_commands): Delete mips specific | |
| 1622 | commands. Handled by module sim-options. | |
| 1623 | ||
| 1624 | * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module. | |
| 1625 | (WITH_MODULO_MEMORY): Define. | |
| 1626 | ||
| 1627 | * interp.c (sim_info): Delete code printing memory size. | |
| 1628 | ||
| 1629 | * interp.c (mips_size): Nee sim_size, delete function. | |
| 1630 | (power2): Delete. | |
| 1631 | (monitor, monitor_base, monitor_size): Delete global variables. | |
| 1632 | (sim_open, sim_close): Delete code creating monitor and other | |
| 1633 | memory regions. Use sim-memopts module, via sim_do_commandf, to | |
| 1634 | manage memory regions. | |
| 1635 | (load_memory, store_memory): Use sim-core for memory model. | |
| 1636 | ||
| 1637 | * interp.c (address_translation): Delete all memory map code | |
| 1638 | except line forcing 32 bit addresses. | |
| 1639 | ||
| 22de994d AC |
1640 | Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com> |
| 1641 | ||
| 1642 | * sim-main.h (WITH_TRACE): Delete definition. Enables common | |
| 1643 | trace options. | |
| 1644 | ||
| 1645 | * interp.c (logfh, logfile): Delete globals. | |
| 1646 | (sim_open, sim_close): Delete code opening & closing log file. | |
| 1647 | (mips_option_handler): Delete -l and -n options. | |
| 1648 | (OPTION mips_options): Ditto. | |
| 1649 | ||
| 1650 | * interp.c (OPTION mips_options): Rename option trace to dinero. | |
| 1651 | (mips_option_handler): Update. | |
| 1652 | ||
| 525d929e AC |
1653 | Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com> |
| 1654 | ||
| 1655 | * interp.c (fetch_str): New function. | |
| 1656 | (sim_monitor): Rewrite using sim_read & sim_write. | |
| 1657 | (sim_open): Check magic number. | |
| 1658 | (sim_open): Write monitor vectors into memory using sim_write. | |
| 1659 | (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define. | |
| 1660 | (sim_read, sim_write): Simplify - transfer data one byte at a | |
| 1661 | time. | |
| 1662 | (load_memory, store_memory): Clarify meaning of parameter RAW. | |
| 1663 | ||
| 1664 | * sim-main.h (isHOST): Defete definition. | |
| 1665 | (isTARGET): Mark as depreciated. | |
| 1666 | (address_translation): Delete parameter HOST. | |
| 1667 | ||
| 1668 | * interp.c (address_translation): Delete parameter HOST. | |
| 1669 | ||
| 6205f379 GRK |
1670 | start-sanitize-tx49 |
| 1671 | Wed Oct 29 14:21:32 1997 Gavin Koch <gavin@cygnus.com> | |
| 1672 | ||
| 1673 | * gencode.c: Add tx49 configury and insns. | |
| 1674 | * configure.in: Add tx49 configury. | |
| 1675 | * configure: Update. | |
| 1676 | ||
| 1677 | end-sanitize-tx49 | |
| 01b9cd49 AC |
1678 | Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com> |
| 1679 | ||
| 1680 | * mips.igen: | |
| 1681 | ||
| 1682 | * Makefile.in (IGEN_INCLUDE): Files included by mips.igen. | |
| 1683 | (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE. | |
| 1684 | ||
| 89d09738 AC |
1685 | Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com> |
| 1686 | ||
| 1687 | * mips.igen: Add model filter field to records. | |
| 1688 | ||
| 16bd5d6e AC |
1689 | Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com> |
| 1690 | ||
| 1691 | * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0. | |
| 1692 | ||
| 1693 | interp.c (sim_engine_run): Do not compile function sim_engine_run | |
| 1694 | when WITH_IGEN == 1. | |
| 1695 | ||
| 1696 | * configure.in (sim_igen_flags, sim_m16_flags): Set according to | |
| 1697 | target architecture. | |
| 1698 | ||
| 1699 | Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to | |
| 1700 | igen. Replace with configuration variables sim_igen_flags / | |
| 1701 | sim_m16_flags. | |
| 1702 | ||
| 16bd5d6e | 1703 | start-sanitize-r5900 |
| 8c31916d AC |
1704 | * r5900.igen: New file. Copy r5900 insns here. |
| 1705 | end-sanitize-r5900 | |
| 78b871ec | 1706 | start-sanitize-cygnus |
| 58fb5d0a | 1707 | * vr5400.igen: New file. |
| 78b871ec | 1708 | end-sanitize-cygnus |
| 16bd5d6e AC |
1709 | * m16.igen: New file. Copy mips16 insns here. |
| 1710 | * mips.igen: From here. | |
| 1711 | ||
| 90ad43b2 AC |
1712 | Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com> |
| 1713 | ||
| 78b871ec | 1714 | start-sanitize-cygnus |
| 90ad43b2 AC |
1715 | * mips.igen: Tag all mipsIV instructions with vr5400 model. |
| 1716 | ||
| 1717 | * configure.in: Add mips64vr5400 target. | |
| 1718 | * configure: Re-generate. | |
| 1719 | ||
| 78b871ec | 1720 | end-sanitize-cygnus |
| 90ad43b2 AC |
1721 | * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ |
| 1722 | to top. | |
| 1723 | (tmp-igen, tmp-m16): Pass -I srcdir to igen. | |
| 1724 | ||
| 635ae9cb GRK |
1725 | Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com> |
| 1726 | ||
| 1727 | * gencode.c (build_instruction): Follow sim_write's lead in using | |
| 1728 | BigEndianMem instead of !ByteSwapMem. | |
| 1729 | ||
| 122edc03 AC |
1730 | Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com> |
| 1731 | ||
| 1732 | * configure.in (sim_gen): Dependent on target, select type of | |
| 1733 | generator. Always select old style generator. | |
| 1734 | ||
| 1735 | configure: Re-generate. | |
| 1736 | ||
| 1737 | Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New | |
| 1738 | targets. | |
| 1739 | (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16, | |
| 1740 | SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN, | |
| 1741 | IGEN_TRACE, IGEN_INSN, IGEN_DC): Define | |
| 1742 | (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member | |
| 1743 | SIM_@sim_gen@_*, set by autoconf. | |
| 1744 | ||
| dad6f1f3 AC |
1745 | Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com> |
| 1746 | ||
| 1747 | * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define. | |
| 1748 | ||
| 1749 | * interp.c (ColdReset): Remove #ifdef HASFPU, check | |
| 1750 | CURRENT_FLOATING_POINT instead. | |
| 1751 | ||
| 1752 | * interp.c (ifetch32): New function. Fetch 32 bit instruction. | |
| 1753 | (address_translation): Raise exception InstructionFetch when | |
| 1754 | translation fails and isINSTRUCTION. | |
| 1755 | ||
| 1756 | * interp.c (sim_open, sim_write, sim_monitor, store_word, | |
| 1757 | sim_engine_run): Change type of of vaddr and paddr to | |
| 1758 | address_word. | |
| 1759 | (address_translation, prefetch, load_memory, store_memory, | |
| 1760 | cache_op): Change type of vAddr and pAddr to address_word. | |
| 1761 | ||
| 1762 | * gencode.c (build_instruction): Change type of vaddr and paddr to | |
| 1763 | address_word. | |
| 1764 | ||
| 92ad193b AC |
1765 | Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com> |
| 1766 | ||
| 1767 | * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT | |
| 1768 | macro to obtain result of ALU op. | |
| 1769 | ||
| aa324b9b AC |
1770 | Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com> |
| 1771 | ||
| 1772 | * interp.c (sim_info): Call profile_print. | |
| 1773 | ||
| e2f8ffb7 AC |
1774 | Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com> |
| 1775 | ||
| 1776 | * Makefile.in (SIM_OBJS): Add sim-profile.o module. | |
| 1777 | ||
| 1778 | * sim-main.h (WITH_PROFILE): Do not define, defined in | |
| 1779 | common/sim-config.h. Use sim-profile module. | |
| 1780 | (simPROFILE): Delete defintion. | |
| 1781 | ||
| 1782 | * interp.c (PROFILE): Delete definition. | |
| 1783 | (mips_option_handler): Delete 'p', 'y' and 'x' profile options. | |
| 1784 | (sim_close): Delete code writing profile histogram. | |
| 1785 | (mips_set_profile, mips_set_profile_size, writeout16, writeout32): | |
| 1786 | Delete. | |
| 1787 | (sim_engine_run): Delete code profiling the PC. | |
| 1788 | ||
| fb5a2a3e AC |
1789 | Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com> |
| 1790 | ||
| 1791 | * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word. | |
| 1792 | ||
| 1793 | * interp.c (sim_monitor): Make register pointers of type | |
| 1794 | unsigned_word*. | |
| 1795 | ||
| 1796 | * sim-main.h: Make registers of type unsigned_word not | |
| 1797 | signed_word. | |
| 1798 | ||
| ea985d24 AC |
1799 | Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com> |
| 1800 | ||
| 1801 | start-sanitize-r5900 | |
| 1802 | * sim-main.h (BYTES_IN_MMI_REGS, ..., SUB_REG_FETCH, ..., GPR_SB, | |
| 1803 | ...): Move to sim-main.h | |
| 1804 | ||
| 1805 | end-sanitize-r5900 | |
| 1806 | * interp.c (sync_operation): Rename from SyncOperation, make | |
| 1807 | global, add SD argument. | |
| 1808 | (prefetch): Rename from Prefetch, make global, add SD argument. | |
| 1809 | (decode_coproc): Make global. | |
| 1810 | ||
| 1811 | * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define. | |
| 1812 | ||
| 1813 | * gencode.c (build_instruction): Generate DecodeCoproc not | |
| 1814 | decode_coproc calls. | |
| 1815 | ||
| 1816 | * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h | |
| 1817 | (SizeFGR): Move to sim-main.h | |
| 1818 | (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT, | |
| 1819 | simSIGINT, simJALDELAYSLOT): Move to sim-main.h | |
| 1820 | (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to | |
| 1821 | sim-main.h. | |
| 1822 | (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF, | |
| 1823 | FP_RM_TOMINF, GETRM): Move to sim-main.h. | |
| 1824 | (Uncached, CachedNoncoherent, CachedCoherent, Cached, | |
| 1825 | isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h. | |
| 1826 | (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian, | |
| 1827 | BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h | |
| 1828 | ||
| 1829 | * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise | |
| 1830 | exception. | |
| 1831 | (sim-alu.h): Include. | |
| 1832 | (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define. | |
| 1833 | (sim_cia): Typedef to instruction_address. | |
| 1834 | ||
| 284e759d AC |
1835 | Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com> |
| 1836 | ||
| 1837 | * Makefile.in (interp.o): Rename generated file engine.c to | |
| 1838 | oengine.c. | |
| 1839 | ||
| 1840 | * interp.c: Update. | |
| 1841 | ||
| 339fb149 AC |
1842 | Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com> |
| 1843 | ||
| 1844 | * gencode.c (build_instruction): Use FPR_STATE not fpr_state. | |
| 1845 | ||
| 8b70f837 AC |
1846 | Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com> |
| 1847 | ||
| 1848 | * gencode.c (build_instruction): For "FPSQRT", output correct | |
| 1849 | number of arguments to Recip. | |
| 1850 | ||
| 0c2c5f61 AC |
1851 | Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com> |
| 1852 | ||
| 1853 | * Makefile.in (interp.o): Depends on sim-main.h | |
| 1854 | ||
| 1855 | * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers. | |
| 1856 | ||
| 1857 | * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state, | |
| 1858 | ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields. | |
| 1859 | (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*, | |
| 1860 | STATE, DSSTATE): Define | |
| 1861 | (GPR, FGRIDX, ..): Define. | |
| 1862 | ||
| 1863 | * interp.c (registers, register_widths, fpr_state, ipc, dspc, | |
| 1864 | pending_*, hiaccess, loaccess, state, dsstate): Delete globals. | |
| 1865 | (GPR, FGRIDX, ...): Delete macros. | |
| 1866 | ||
| 1867 | * interp.c: Update names to match defines from sim-main.h | |
| 1868 | ||
| 18c64df6 AC |
1869 | Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com> |
| 1870 | ||
| 1871 | * interp.c (sim_monitor): Add SD argument. | |
| 1872 | (sim_warning): Delete. Replace calls with calls to | |
| 1873 | sim_io_eprintf. | |
| 1874 | (sim_error): Delete. Replace calls with sim_io_error. | |
| 1875 | (open_trace, writeout32, writeout16, getnum): Add SD argument. | |
| 1876 | (mips_set_profile): Rename from sim_set_profile. Add SD argument. | |
| 1877 | (mips_set_profile_size): Rename from sim_set_profile_size. Add SD | |
| 1878 | argument. | |
| 1879 | (mips_size): Rename from sim_size. Add SD argument. | |
| 1880 | ||
| 1881 | * interp.c (simulator): Delete global variable. | |
| 1882 | (callback): Delete global variable. | |
| 1883 | (mips_option_handler, sim_open, sim_write, sim_read, | |
| 1884 | sim_store_register, sim_fetch_register, sim_info, sim_do_command, | |
| 1885 | sim_size,sim_monitor): Use sim_io_* not callback->*. | |
| 1886 | (sim_open): ZALLOC simulator struct. | |
| 1887 | (PROFILE): Do not define. | |
| 1888 | ||
| 1889 | Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1890 | ||
| 1891 | * interp.c (sim_open), support.h: Replace CHECKSIM macro found in | |
| 1892 | support.h with corresponding code. | |
| 1893 | ||
| 1894 | * sim-main.h (word64, uword64), support.h: Move definition to | |
| 1895 | sim-main.h. | |
| 1896 | (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto. | |
| 1897 | ||
| 1898 | * support.h: Delete | |
| 1899 | * Makefile.in: Update dependencies | |
| 1900 | * interp.c: Do not include. | |
| 1901 | ||
| 1902 | Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1903 | ||
| 1904 | * interp.c (address_translation, load_memory, store_memory, | |
| 1905 | cache_op): Rename to from AddressTranslation et.al., make global, | |
| 1906 | add SD argument | |
| 1907 | ||
| 1908 | * sim-main.h (AddressTranslation, LoadMemory, StoreMemory, | |
| 1909 | CacheOp): Define. | |
| 1910 | ||
| 1911 | * interp.c (SignalException): Rename to signal_exception, make | |
| 1912 | global. | |
| 1913 | ||
| 1914 | * interp.c (Interrupt, ...): Move definitions to sim-main.h. | |
| 1915 | ||
| 1916 | * sim-main.h (SignalException, SignalExceptionInterrupt, | |
| 1917 | SignalExceptionInstructionFetch, SignalExceptionAddressStore, | |
| 1918 | SignalExceptionAddressLoad, SignalExceptionSimulatorFault, | |
| 1919 | SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable): | |
| 1920 | Define. | |
| 1921 | ||
| 1922 | * interp.c, support.h: Use. | |
| 1923 | ||
| 1924 | Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1925 | ||
| 1926 | * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename | |
| 1927 | to value_fpr / store_fpr. Add SD argument. | |
| 1928 | (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub, | |
| 1929 | Multiply, Divide, Recip, SquareRoot, Convert): Make global. | |
| 1930 | ||
| 1931 | * sim-main.h (ValueFPR, StoreFPR): Define. | |
| 1932 | ||
| 1933 | Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1934 | ||
| 1935 | * interp.c (sim_engine_run): Check consistency between configure | |
| 1936 | WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN | |
| 1937 | and HASFPU. | |
| 1938 | ||
| 1939 | * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE. | |
| 1940 | (mips_fpu): Configure WITH_FLOATING_POINT. | |
| 1941 | (mips_endian): Configure WITH_TARGET_ENDIAN. | |
| 1942 | * configure: Update. | |
| 1943 | ||
| 1944 | Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1945 | ||
| 1946 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 1947 | ||
| adf4739e AC |
1948 | start-sanitize-r5900 |
| 1949 | Mon Aug 25 19:11:15 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1950 | ||
| 1951 | * interp.c (MAX_REG): Allow up-to 128 registers. | |
| 1952 | (LO1, HI1): Define value that matches REGISTER_NAMES in gdb. | |
| 1953 | (REGISTER_SA): Ditto. | |
| 1954 | (sim_open): Initialize register_widths for r5900 specific | |
| 1955 | registers. | |
| 1956 | (sim_fetch_register, sim_store_register): Check for request of | |
| 1957 | r5900 specific SA register. Check for request for hi 64 bits of | |
| 1958 | r5900 specific registers. | |
| 1959 | ||
| 1960 | end-sanitize-r5900 | |
| 26b20b0a BM |
1961 | Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com> |
| 1962 | ||
| 1963 | * configure: Regenerated. | |
| 1964 | ||
| 6eedf3f4 MA |
1965 | Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com> |
| 1966 | ||
| 1967 | * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB. | |
| 1968 | ||
| e63bc706 AC |
1969 | Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com> |
| 1970 | ||
| 6eedf3f4 MA |
1971 | * gencode.c (print_igen_insn_models): Assume certain architectures |
| 1972 | include all mips* instructions. | |
| 1973 | (print_igen_insn_format): Use data_size==-1 as marker for MIPS16 | |
| 1974 | instruction. | |
| 1975 | ||
| e63bc706 AC |
1976 | * Makefile.in (tmp.igen): Add target. Generate igen input from |
| 1977 | gencode file. | |
| 1978 | ||
| 1979 | * gencode.c (FEATURE_IGEN): Define. | |
| 1980 | (main): Add --igen option. Generate output in igen format. | |
| 1981 | (process_instructions): Format output according to igen option. | |
| 1982 | (print_igen_insn_format): New function. | |
| 1983 | (print_igen_insn_models): New function. | |
| 1984 | (process_instructions): Only issue warnings and ignore | |
| 1985 | instructions when no FEATURE_IGEN. | |
| 1986 | ||
| eb2e3c85 AC |
1987 | Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com> |
| 1988 | ||
| 1989 | * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some | |
| 1990 | MIPS targets. | |
| 1991 | ||
| 92f91d1f AC |
1992 | Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com> |
| 1993 | ||
| 1994 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 1995 | ||
| 1996 | Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1997 | ||
| 1998 | * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN, | |
| 1999 | SIM_RESERVED_BITS): Delete, moved to common. | |
| 2000 | (SIM_EXTRA_CFLAGS): Update. | |
| 2001 | ||
| 794e9ac9 AC |
2002 | Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com> |
| 2003 | ||
| 76a6247f | 2004 | * configure.in: Configure non-strict memory alignment. |
| 794e9ac9 AC |
2005 | * configure: Regenerated to track ../common/aclocal.m4 changes. |
| 2006 | ||
| b45caf05 AC |
2007 | Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com> |
| 2008 | ||
| 2009 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 2010 | ||
| 2011 | Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com> | |
| 2012 | ||
| 2013 | * gencode.c (SDBBP,DERET): Added (3900) insns. | |
| 2014 | (RFE): Turn on for 3900. | |
| 2015 | * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added. | |
| 2016 | (dsstate): Made global. | |
| 2017 | (SUBTARGET_R3900): Added. | |
| 2018 | (CANCELDELAYSLOT): New. | |
| 2019 | (SignalException): Ignore SystemCall rather than ignore and | |
| 2020 | terminate. Add DebugBreakPoint handling. | |
| 2021 | (decode_coproc): New insns RFE, DERET; and new registers Debug | |
| 2022 | and DEPC protected by SUBTARGET_R3900. | |
| 2023 | (sim_engine_run): Use CANCELDELAYSLOT rather than clearing | |
| 2024 | bits explicitly. | |
| 2025 | * Makefile.in,configure.in: Add mips subtarget option. | |
| 2026 | * configure: Update. | |
| 2027 | ||
| 7afa8d4e GRK |
2028 | Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com> |
| 2029 | ||
| 2030 | * gencode.c: Add r3900 (tx39). | |
| 2031 | ||
| 2032 | start-sanitize-tx19 | |
| 2033 | * gencode.c: Fix some configuration problems by improving | |
| 2034 | the relationship between tx19 and tx39. | |
| 2035 | end-sanitize-tx19 | |
| 2036 | ||
| 667065d0 GRK |
2037 | Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com> |
| 2038 | ||
| 2039 | * gencode.c (build_instruction): Don't need to subtract 4 for | |
| 2040 | JALR, just 2. | |
| 2041 | ||
| 9cb8397f GRK |
2042 | Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com> |
| 2043 | ||
| 2044 | * interp.c: Correct some HASFPU problems. | |
| 2045 | ||
| a2ab5e65 AC |
2046 | Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com> |
| 2047 | ||
| 2048 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 2049 | ||
| 11ac69e0 AC |
2050 | Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com> |
| 2051 | ||
| 2052 | * interp.c (mips_options): Fix samples option short form, should | |
| 2053 | be `x'. | |
| 2054 | ||
| 972f3a34 AC |
2055 | Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com> |
| 2056 | ||
| 2057 | * interp.c (sim_info): Enable info code. Was just returning. | |
| 2058 | ||
| 9eeaaefa AC |
2059 | Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com> |
| 2060 | ||
| 2061 | * interp.c (decode_coproc): Clarify warning about unsuported MTC0, | |
| 2062 | MFC0. | |
| 2063 | ||
| c31c13b4 AC |
2064 | Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com> |
| 2065 | ||
| 2066 | * gencode.c (build_instruction): Use SIGNED64 for 64 bit | |
| 2067 | constants. | |
| 2068 | (build_instruction): Ditto for LL. | |
| 2069 | ||
| b637f306 GRK |
2070 | start-sanitize-tx19 |
| 2071 | Sun Sep 7 16:05:46 1997 Gavin Koch <gavin@cygnus.com> | |
| 2072 | ||
| 2073 | * mips/configure.in, mips/gencode: Add tx19/r1900. | |
| 2074 | ||
| 2075 | end-sanitize-tx19 | |
| 6fea4763 DE |
2076 | Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba> |
| 2077 | ||
| 2078 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 2079 | ||
| 52352d38 AC |
2080 | start-sanitize-r5900 |
| 2081 | Mon Sep 1 18:43:30 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2082 | ||
| 2083 | * gencode.c (build_instruction): For "pabsw" and "pabsh", check | |
| 2084 | for overflow due to ABS of MININT, set result to MAXINT. | |
| 2085 | (build_instruction): For "psrlvw", signextend bit 31. | |
| 2086 | ||
| 2087 | end-sanitize-r5900 | |
| 88117054 AC |
2088 | Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com> |
| 2089 | ||
| 2090 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 2091 | * config.in: Ditto. | |
| 2092 | ||
| fafce69a AC |
2093 | Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com> |
| 2094 | ||
| 2095 | * interp.c (sim_open): Add call to sim_analyze_program, update | |
| 2096 | call to sim_config. | |
| 2097 | ||
| 7230ff0f AC |
2098 | Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com> |
| 2099 | ||
| 2100 | * interp.c (sim_kill): Delete. | |
| fafce69a AC |
2101 | (sim_create_inferior): Add ABFD argument. Set PC from same. |
| 2102 | (sim_load): Move code initializing trap handlers from here. | |
| 2103 | (sim_open): To here. | |
| 2104 | (sim_load): Delete, use sim-hload.c. | |
| 2105 | ||
| 2106 | * Makefile.in (SIM_OBJS): Add sim-hload.o module. | |
| 7230ff0f | 2107 | |
| 247fccde AC |
2108 | Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com> |
| 2109 | ||
| 2110 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 2111 | * config.in: Ditto. | |
| 2112 | ||
| 2113 | Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2114 | ||
| 2115 | * interp.c (sim_open): Add ABFD argument. | |
| 2116 | (sim_load): Move call to sim_config from here. | |
| 2117 | (sim_open): To here. Check return status. | |
| 2118 | ||
| 2119 | start-sanitize-r5900 | |
| 2120 | * gencode.c (build_instruction): Do not define x8000000000000000, | |
| 2121 | x7FFFFFFFFFFFFFFF, or xFFFFFFFF80000000. | |
| 2122 | ||
| 2123 | end-sanitize-r5900 | |
| 2124 | start-sanitize-r5900 | |
| 2125 | Mon Jul 28 19:49:29 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2126 | ||
| 2127 | * gencode.c (build_instruction): For "pdivw", "pdivbw" and | |
| 2128 | "pdivuw" check for overflow due to signed divide by -1. | |
| 2129 | ||
| 2130 | end-sanitize-r5900 | |
| c12e2e4c GRK |
2131 | Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com> |
| 2132 | ||
| 2133 | * gencode.c (build_instruction): Two arg MADD should | |
| 2134 | not assign result to $0. | |
| 2135 | ||
| 1e851d2c AC |
2136 | start-sanitize-r5900 |
| 2137 | Thu Jul 10 11:58:48 1997 Andrew Cagney <cagney@critters.cygnus.com> | |
| 2138 | ||
| 2139 | * gencode.c (build_instruction): For "ppac5" use unsigned | |
| 2140 | arrithmetic so that the sign bit doesn't smear when right shifted. | |
| 2141 | (build_instruction): For "pdiv" perform sign extension when | |
| 2142 | storing results in HI and LO. | |
| 2143 | (build_instructions): For "pdiv" and "pdivbw" check for | |
| 2144 | divide-by-zero. | |
| 2145 | (build_instruction): For "pmfhl.slw" update hi part of dest | |
| 2146 | register as well as low part. | |
| 2147 | (build_instruction): For "pmfhl" portably handle long long values. | |
| 2148 | (build_instruction): For "pmfhl.sh" correctly negative values. | |
| 2149 | Store half words 2 and three in the correct place. | |
| 2150 | (build_instruction): For "psllvw", sign extend value after shift. | |
| 2151 | ||
| 2152 | end-sanitize-r5900 | |
| 2153 | Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com) | |
| 2154 | ||
| 2155 | * sim/mips/configure: Change default_sim_endian to 0 (bi-endian) | |
| 2156 | * sim/mips/configure.in: Regenerate. | |
| 2157 | ||
| 2158 | Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com> | |
| 2159 | ||
| 2160 | * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit | |
| 2161 | signed8, unsigned8 et.al. types. | |
| 2162 | ||
| 2163 | start-sanitize-r5900 | |
| 2164 | * gencode.c (build_instruction): For PMULTU* do not sign extend | |
| 2165 | registers. Make generated code easier to debug. | |
| 2166 | ||
| 2167 | end-sanitize-r5900 | |
| 2168 | * interp.c (SUB_REG_FETCH): Handle both little and big endian | |
| 2169 | hosts when selecting subreg. | |
| 2170 | ||
| 2171 | start-sanitize-r5900 | |
| 2172 | Tue Jul 8 18:07:20 1997 Andrew Cagney <cagney@andros.cygnus.com> | |
| 2173 | ||
| 2174 | * gencode.c (type_for_data_len): For 32bit operations concerned | |
| 2175 | with overflow, perform op using 64bits. | |
| 2176 | (build_instruction): For PADD, always compute operation using type | |
| 2177 | returned by type_for_data_len. | |
| 2178 | (build_instruction): For PSUBU, when overflow, saturate to zero as | |
| 2179 | actually underflow. | |
| 2180 | ||
| 2181 | end-sanitize-r5900 | |
| ae19b07b JL |
2182 | Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com) |
| 2183 | ||
| 649625bb | 2184 | start-sanitize-r5900 |
| 64435234 JL |
2185 | * gencode.c (build_instruction): Handle "pext5" according to |
| 2186 | version 1.95 of the r5900 ISA. | |
| 2187 | ||
| 649625bb JL |
2188 | * gencode.c (build_instruction): Handle "ppac5" according to |
| 2189 | version 1.95 of the r5900 ISA. | |
| 649625bb | 2190 | |
| 1e851d2c | 2191 | end-sanitize-r5900 |
| 05d1322f JL |
2192 | * interp.c (sim_engine_run): Reset the ZERO register to zero |
| 2193 | regardless of FEATURE_WARN_ZERO. | |
| ae19b07b JL |
2194 | * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO. |
| 2195 | ||
| 2196 | Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2197 | ||
| 2198 | * interp.c (decode_coproc): Implement MTC0 N, CAUSE. | |
| 2199 | (SignalException): For BreakPoints ignore any mode bits and just | |
| 2200 | save the PC. | |
| 2201 | (SignalException): Always set the CAUSE register. | |
| 2202 | ||
| 56e7c849 AC |
2203 | Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com> |
| 2204 | ||
| 2205 | * interp.c (SignalException): Clear the simDELAYSLOT flag when an | |
| 2206 | exception has been taken. | |
| 2207 | ||
| 2208 | * interp.c: Implement the ERET and mt/f sr instructions. | |
| 2209 | ||
| ae19b07b | 2210 | start-sanitize-r5900 |
| 56e7c849 AC |
2211 | Mon Jun 2 23:28:19 1997 Andrew Cagney <cagney@b1.cygnus.com> |
| 2212 | ||
| 2213 | * gencode.c (build_instruction): For paddu, extract unsigned | |
| 2214 | sub-fields. | |
| 2215 | ||
| 2216 | * gencode.c (build_instruction): Saturate padds instead of padd | |
| 2217 | instructions. | |
| 2218 | ||
| 2219 | end-sanitize-r5900 | |
| 2220 | Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2221 | ||
| 2222 | * interp.c (SignalException): Don't bother restarting an | |
| 2223 | interrupt. | |
| 2224 | ||
| 2225 | Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2226 | ||
| 2227 | * interp.c (SignalException): Really take an interrupt. | |
| 2228 | (interrupt_event): Only deliver interrupts when enabled. | |
| 2229 | ||
| 2230 | Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2231 | ||
| 2232 | * interp.c (sim_info): Only print info when verbose. | |
| 2233 | (sim_info) Use sim_io_printf for output. | |
| 2234 | ||
| 2f2e6c5d AC |
2235 | Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com> |
| 2236 | ||
| 2237 | * interp.c (CoProcPresent): Add UNUSED attribute - not used by all | |
| 2238 | mips architectures. | |
| 2239 | ||
| 2240 | Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2241 | ||
| 2242 | * interp.c (sim_do_command): Check for common commands if a | |
| 2243 | simulator specific command fails. | |
| 2244 | ||
| d3d2a9f7 GRK |
2245 | Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com> |
| 2246 | ||
| 2247 | * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP | |
| 2248 | and simBE when DEBUG is defined. | |
| 2249 | ||
| 50a2a691 AC |
2250 | Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com> |
| 2251 | ||
| 2252 | * interp.c (interrupt_event): New function. Pass exception event | |
| 2253 | onto exception handler. | |
| 2254 | ||
| 2255 | * configure.in: Check for stdlib.h. | |
| 2256 | * configure: Regenerate. | |
| 2257 | ||
| 2258 | * gencode.c (build_instruction): Add UNUSED attribute to tempS | |
| 2259 | variable declaration. | |
| 2260 | (build_instruction): Initialize memval1. | |
| 2261 | (build_instruction): Add UNUSED attribute to byte, bigend, | |
| 2262 | reverse. | |
| 2263 | (build_operands): Ditto. | |
| 2264 | ||
| 2265 | * interp.c: Fix GCC warnings. | |
| 2266 | (sim_get_quit_code): Delete. | |
| 2267 | ||
| 2268 | * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS. | |
| 2269 | * Makefile.in: Ditto. | |
| 2270 | * configure: Re-generate. | |
| 2271 | ||
| 2272 | * Makefile.in (SIM_OBJS): Add sim-watch.o module. | |
| 2273 | ||
| 2274 | Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2275 | ||
| 2276 | * interp.c (mips_option_handler): New function parse argumes using | |
| 2277 | sim-options. | |
| 2278 | (myname): Replace with STATE_MY_NAME. | |
| 2279 | (sim_open): Delete check for host endianness - performed by | |
| 2280 | sim_config. | |
| 2281 | (simHOSTBE, simBE): Delete, replaced by sim-endian flags. | |
| 2282 | (sim_open): Move much of the initialization from here. | |
| 2283 | (sim_load): To here. After the image has been loaded and | |
| 2284 | endianness set. | |
| 2285 | (sim_open): Move ColdReset from here. | |
| 2286 | (sim_create_inferior): To here. | |
| 2287 | (sim_open): Make FP check less dependant on host endianness. | |
| 2288 | ||
| 2289 | * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or | |
| 2290 | run. | |
| 2291 | * interp.c (sim_set_callbacks): Delete. | |
| 2292 | ||
| 2293 | * interp.c (membank, membank_base, membank_size): Replace with | |
| 2294 | STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE. | |
| 2295 | (sim_open): Remove call to callback->init. gdb/run do this. | |
| 2296 | ||
| 2297 | * interp.c: Update | |
| 2298 | ||
| 2299 | * sim-main.h (SIM_HAVE_FLATMEM): Define. | |
| 2300 | ||
| 2301 | * interp.c (big_endian_p): Delete, replaced by | |
| 2302 | current_target_byte_order. | |
| 2303 | ||
| 2304 | Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2305 | ||
| 2306 | * interp.c (host_read_long, host_read_word, host_swap_word, | |
| 2307 | host_swap_long): Delete. Using common sim-endian. | |
| 2308 | (sim_fetch_register, sim_store_register): Use H2T. | |
| 2309 | (pipeline_ticks): Delete. Handled by sim-events. | |
| 2310 | (sim_info): Update. | |
| 2311 | (sim_engine_run): Update. | |
| 2312 | ||
| 2313 | Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2314 | ||
| 2315 | * interp.c (sim_stop_reason): Move code determining simEXCEPTION | |
| 2316 | reason from here. | |
| 2317 | (SignalException): To here. Signal using sim_engine_halt. | |
| 2318 | (sim_stop_reason): Delete, moved to common. | |
| 2319 | ||
| 2320 | Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com> | |
| 2321 | ||
| 2322 | * interp.c (sim_open): Add callback argument. | |
| 2323 | (sim_set_callbacks): Delete SIM_DESC argument. | |
| 2324 | (sim_size): Ditto. | |
| 2325 | ||
| 2e61a3ad AC |
2326 | Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com> |
| 2327 | ||
| 2328 | * Makefile.in (SIM_OBJS): Add common modules. | |
| 2329 | ||
| 2330 | * interp.c (sim_set_callbacks): Also set SD callback. | |
| 2331 | (set_endianness, xfer_*, swap_*): Delete. | |
| 2332 | (host_read_word, host_read_long, host_swap_word, host_swap_long): | |
| 2333 | Change to functions using sim-endian macros. | |
| 2334 | (control_c, sim_stop): Delete, use common version. | |
| 2335 | (simulate): Convert into. | |
| 2336 | (sim_engine_run): This function. | |
| 2337 | (sim_resume): Delete. | |
| 2338 | ||
| 2339 | * interp.c (simulation): New variable - the simulator object. | |
| 2340 | (sim_kind): Delete global - merged into simulation. | |
| 2341 | (sim_load): Cleanup. Move PC assignment from here. | |
| 2342 | (sim_create_inferior): To here. | |
| 2343 | ||
| 2344 | * sim-main.h: New file. | |
| 2345 | * interp.c (sim-main.h): Include. | |
| 2346 | ||
| 2347 | Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com> | |
| 2348 | ||
| 2349 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 2350 | ||
| 3be0e228 DE |
2351 | Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com> |
| 2352 | ||
| 2353 | * tconfig.in (SIM_HAVE_BIENDIAN): Define. | |
| 2354 | ||
| d654ba0a GRK |
2355 | Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com> |
| 2356 | ||
| 2357 | * gencode.c (build_instruction): DIV instructions: check | |
| 2358 | for division by zero and integer overflow before using | |
| 2359 | host's division operation. | |
| 2360 | ||
| 9d52bcb7 DE |
2361 | Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com> |
| 2362 | ||
| 2363 | * Makefile.in (SIM_OBJS): Add sim-load.o. | |
| 2364 | * interp.c: #include bfd.h. | |
| 2365 | (target_byte_order): Delete. | |
| 2366 | (sim_kind, myname, big_endian_p): New static locals. | |
| 2367 | (sim_open): Set sim_kind, myname. Move call to set_endianness to | |
| 2368 | after argument parsing. Recognize -E arg, set endianness accordingly. | |
| 2369 | (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to | |
| 2370 | load file into simulator. Set PC from bfd. | |
| 2371 | (sim_create_inferior): Return SIM_RC. Delete arg start_address. | |
| 2372 | (set_endianness): Use big_endian_p instead of target_byte_order. | |
| 2373 | ||
| 87e43259 AC |
2374 | Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com> |
| 2375 | ||
| 2376 | * interp.c (sim_size): Delete prototype - conflicts with | |
| 2377 | definition in remote-sim.h. Correct definition. | |
| 2378 | ||
| 2379 | Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com> | |
| 2380 | ||
| 2381 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 2382 | * config.in: Ditto. | |
| 2383 | ||
| fbda74b1 DE |
2384 | Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com> |
| 2385 | ||
| 8a7c3105 DE |
2386 | * interp.c (sim_open): New arg `kind'. |
| 2387 | ||
| fbda74b1 DE |
2388 | * configure: Regenerated to track ../common/aclocal.m4 changes. |
| 2389 | ||
| a35e91c3 AC |
2390 | Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com> |
| 2391 | ||
| 2392 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 2393 | ||
| 2394 | Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com> | |
| 2395 | ||
| 2396 | * interp.c (sim_open): Set optind to 0 before calling getopt. | |
| 2397 | ||
| 2398 | Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com> | |
| 2399 | ||
| 2400 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 2401 | ||
| 6efa34d8 GRK |
2402 | Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com> |
| 2403 | ||
| 2404 | * interp.c : Replace uses of pr_addr with pr_uword64 | |
| 2405 | where the bit length is always 64 independent of SIM_ADDR. | |
| 2406 | (pr_uword64) : added. | |
| 2407 | ||
| a77aa7ec AC |
2408 | Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com> |
| 2409 | ||
| 2410 | * configure: Re-generate. | |
| 2411 | ||
| 601fb8ae MM |
2412 | Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com> |
| 2413 | ||
| 2414 | * configure: Regenerate to track ../common/aclocal.m4 changes. | |
| 2415 | ||
| 53b9417e DE |
2416 | Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com> |
| 2417 | ||
| 2418 | * interp.c (sim_open): New SIM_DESC result. Argument is now | |
| 2419 | in argv form. | |
| 2420 | (other sim_*): New SIM_DESC argument. | |
| 2421 | ||
| 2422 | start-sanitize-r5900 | |
| 2423 | Wed Feb 26 18:32:21 1997 Gavin Koch <gavin@cygnus.com> | |
| 2424 | ||
| 2425 | * gencode.c (POP_AND,POP_OR,POP_NOR,POP_XOR): | |
| 2426 | Change values to avoid overloading DOUBLEWORD which is tested | |
| 2427 | for all insns. | |
| 2428 | * gencode.c: reinstate "offending code". | |
| 53b9417e | 2429 | |
| 56e7c849 | 2430 | end-sanitize-r5900 |
| 53b9417e DE |
2431 | Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com> |
| 2432 | ||
| 2433 | * interp.c: Fix printing of addresses for non-64-bit targets. | |
| 2434 | (pr_addr): Add function to print address based on size. | |
| 2435 | start-sanitize-r5900 | |
| 2436 | * gencode.c: #ifdef out offending code until a permanent fix | |
| 2437 | can be added. Code is causing build errors for non-5900 mips targets. | |
| 2438 | end-sanitize-r5900 | |
| 2439 | ||
| 2440 | start-sanitize-r5900 | |
| 2441 | Thu Feb 20 10:40:24 1997 Gavin Koch <gavin@cetus.cygnus.com> | |
| 2442 | ||
| 2443 | * gencode.c (process_instructions): Correct test for ISA dependent | |
| 2444 | architecture bits in isa field of MIPS_DECODE. | |
| 2445 | ||
| 2446 | end-sanitize-r5900 | |
| 7e05106d MA |
2447 | Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com> |
| 2448 | ||
| 2449 | * interp.c (simopen): Add support for LSI MiniRISC PMON vectors. | |
| 2450 | ||
| 2d18fbc6 | 2451 | start-sanitize-r5900 |
| 53b9417e | 2452 | Tue Feb 18 17:03:47 1997 Gavin Koch <gavin@cygnus.com> |
| 2d18fbc6 GRK |
2453 | |
| 2454 | * gencode.c (MIPS_DECODE): Correct instruction feature flags for | |
| 2455 | PMADDUW. | |
| 2456 | ||
| 2457 | end-sanitize-r5900 | |
| 2458 | Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com> | |
| 2459 | ||
| 2460 | * gencode.c (build_mips16_operands): Correct computation of base | |
| 2461 | address for extended PC relative instruction. | |
| 2462 | ||
| 276c2d7d GRK |
2463 | start-sanitize-r5900 |
| 2464 | Fri Feb 7 11:12:44 1997 Gavin Koch <gavin@cygnus.com> | |
| 2d18fbc6 GRK |
2465 | |
| 2466 | * Makefile.in, configure, configure.in, gencode.c, | |
| 2467 | interp.c, support.h: add r5900. | |
| 2468 | ||
| 276c2d7d | 2469 | end-sanitize-r5900 |
| da0bce9c ILT |
2470 | Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com> |
| 2471 | ||
| 2472 | * interp.c (mips16_entry): Add support for floating point cases. | |
| 2473 | (SignalException): Pass floating point cases to mips16_entry. | |
| 2474 | (ValueFPR): Don't restrict fmt_single and fmt_word to even | |
| 2475 | registers. | |
| 2476 | (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single | |
| 2477 | or fmt_word. | |
| 2478 | (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR, | |
| 2479 | and then set the state to fmt_uninterpreted. | |
| 2480 | (COP_SW): Temporarily set the state to fmt_word while calling | |
| 2481 | ValueFPR. | |
| 2482 | ||
| 6389d856 ILT |
2483 | Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com> |
| 2484 | ||
| 2485 | * gencode.c (build_instruction): The high order may be set in the | |
| 2486 | comparison flags at any ISA level, not just ISA 4. | |
| 2487 | ||
| 19c5af72 DE |
2488 | Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com> |
| 2489 | ||
| 2490 | * Makefile.in (@COMMON_MAKEFILE_FRAG): Use | |
| 2491 | COMMON_{PRE,POST}_CONFIG_FRAG instead. | |
| 2492 | * configure.in: sinclude ../common/aclocal.m4. | |
| 2493 | * configure: Regenerated. | |
| 2494 | ||
| 736a306c ILT |
2495 | Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com> |
| 2496 | ||
| 2497 | * configure: Rebuild after change to aclocal.m4. | |
| 2498 | ||
| 295dbbe4 SG |
2499 | Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com) |
| 2500 | ||
| 2501 | * configure configure.in Makefile.in: Update to new configure | |
| 2502 | scheme which is more compatible with WinGDB builds. | |
| 2503 | * configure.in: Improve comment on how to run autoconf. | |
| 2504 | * configure: Re-run autoconf to get new ../common/aclocal.m4. | |
| 2505 | * Makefile.in: Use autoconf substitution to install common | |
| 2506 | makefile fragment. | |
| 2507 | ||
| 2508 | Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com> | |
| 2509 | ||
| 2510 | * gencode.c (build_instruction): Use BigEndianCPU instead of | |
| 2511 | ByteSwapMem. | |
| 2512 | ||
| e1db0d47 MA |
2513 | Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com> |
| 2514 | ||
| 2515 | * interp.c (sim_monitor): Make output to stdout visible in | |
| 2516 | wingdb's I/O log window. | |
| 2517 | ||
| 2902e8ab MA |
2518 | Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com> |
| 2519 | ||
| 2520 | * support.h: Undo previous change to SIGTRAP | |
| 2521 | and SIGQUIT values. | |
| 2522 | ||
| 7e6c297e ILT |
2523 | Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com> |
| 2524 | ||
| 2525 | * interp.c (store_word, load_word): New static functions. | |
| 2526 | (mips16_entry): New static function. | |
| 2527 | (SignalException): Look for mips16 entry and exit instructions. | |
| 2528 | (simulate): Use the correct index when setting fpr_state after | |
| 2529 | doing a pending move. | |
| 2530 | ||
| 0049ba7a MA |
2531 | Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com> |
| 2532 | ||
| 2533 | * interp.c: Fix byte-swapping code throughout to work on | |
| 2534 | both little- and big-endian hosts. | |
| 2535 | ||
| 2510786b MA |
2536 | Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com> |
| 2537 | ||
| 2538 | * support.h: Make definitions of SIGTRAP and SIGQUIT consistent | |
| 2539 | with gdb/config/i386/xm-windows.h. | |
| 2540 | ||
| 39bf0ef4 MA |
2541 | Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com> |
| 2542 | ||
| 2543 | * gencode.c (build_instruction): Work around MSVC++ code gen bug | |
| 2544 | that messes up arithmetic shifts. | |
| 2545 | ||
| dbeec768 SG |
2546 | Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com) |
| 2547 | ||
| 2548 | * support.h: Use _WIN32 instead of __WIN32__. Also add defs for | |
| 2549 | SIGTRAP and SIGQUIT for _WIN32. | |
| 2550 | ||
| deffd638 ILT |
2551 | Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com> |
| 2552 | ||
| 2553 | * gencode.c (build_instruction) [MUL]: Cast operands to word64, to | |
| 2554 | force a 64 bit multiplication. | |
| 2555 | (build_instruction) [OR]: In mips16 mode, don't do anything if the | |
| 2556 | destination register is 0, since that is the default mips16 nop | |
| 2557 | instruction. | |
| 2558 | ||
| aaff8437 ILT |
2559 | Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com> |
| 2560 | ||
| 063443cf ILT |
2561 | * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI. |
| 2562 | (build_endian_shift): Don't check proc64. | |
| 2563 | (build_instruction): Always set memval to uword64. Cast op2 to | |
| 2564 | uword64 when shifting it left in memory instructions. Always use | |
| 2565 | the same code for stores--don't special case proc64. | |
| 2566 | ||
| aaff8437 ILT |
2567 | * gencode.c (build_mips16_operands): Fix base PC value for PC |
| 2568 | relative operands. | |
| 2569 | (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a | |
| 2570 | jal instruction. | |
| 2571 | * interp.c (simJALDELAYSLOT): Define. | |
| 2572 | (JALDELAYSLOT): Define. | |
| 2573 | (INDELAYSLOT, INJALDELAYSLOT): Define. | |
| 2574 | (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared. | |
| 2575 | ||
| 280f90e1 AMT |
2576 | Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com) |
| 2577 | ||
| 2578 | * interp.c (sim_open): add flush_cache as a PMON routine | |
| 2579 | (sim_monitor): handle flush_cache by ignoring it | |
| 2580 | ||
| aaff8437 ILT |
2581 | Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com> |
| 2582 | ||
| 2583 | * gencode.c (build_instruction): Use !ByteSwapMem instead of | |
| 2584 | BigEndianMem. | |
| 2585 | * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete. | |
| 2586 | (BigEndianMem): Rename to ByteSwapMem and change sense. | |
| 2587 | (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change | |
| 2588 | BigEndianMem references to !ByteSwapMem. | |
| 2589 | (set_endianness): New function, with prototype. | |
| 2590 | (sim_open): Call set_endianness. | |
| 2591 | (sim_info): Use simBE instead of BigEndianMem. | |
| 2592 | (xfer_direct_word, xfer_direct_long, swap_direct_word, | |
| 2593 | swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word, | |
| 2594 | xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER | |
| 2595 | ifdefs, keeping the prototype declaration. | |
| 2596 | (swap_word): Rewrite correctly. | |
| 2597 | (ColdReset): Delete references to CONFIG. Delete endianness related | |
| 2598 | code; moved to set_endianness. | |
| 2599 | ||
| 6429b296 JW |
2600 | Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com> |
| 2601 | ||
| 2602 | * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits. | |
| 2603 | * interp.c (CHECKHILO): Define away. | |
| 2604 | (simSIGINT): New macro. | |
| 2605 | (membank_size): Increase from 1MB to 2MB. | |
| 2606 | (control_c): New function. | |
| 2607 | (sim_resume): Rename parameter signal to signal_number. Add local | |
| 2608 | variable prev. Call signal before and after simulate. | |
| 2609 | (sim_stop_reason): Add simSIGINT support. | |
| 2610 | (sim_warning, sim_error, dotrace, SignalException): Define as stdarg | |
| 2611 | functions always. | |
| 2612 | (sim_warning): Delete call to SignalException. Do call printf_filtered | |
| 2613 | if logfh is NULL. | |
| 2614 | (AddressTranslation): Add #ifdef DEBUG around debugging message and | |
| 2615 | a call to sim_warning. | |
| 2616 | ||
| 2617 | Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com> | |
| 2618 | ||
| 2619 | * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD | |
| 2620 | 16 bit instructions. | |
| 2621 | ||
| 831f59a2 ILT |
2622 | Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com> |
| 2623 | ||
| 2624 | Add support for mips16 (16 bit MIPS implementation): | |
| 2625 | * gencode.c (inst_type): Add mips16 instruction encoding types. | |
| 2626 | (GETDATASIZEINSN): Define. | |
| 2627 | (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add | |
| 2628 | jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and | |
| 2629 | mtlo. | |
| 2630 | (MIPS16_DECODE): New table, for mips16 instructions. | |
| 2631 | (bitmap_val): New static function. | |
| 2632 | (struct mips16_op): Define. | |
| 2633 | (mips16_op_table): New table, for mips16 operands. | |
| 2634 | (build_mips16_operands): New static function. | |
| 2635 | (process_instructions): If PC is odd, decode a mips16 | |
| 2636 | instruction. Break out instruction handling into new | |
| 2637 | build_instruction function. | |
| 2638 | (build_instruction): New static function, broken out of | |
| 2639 | process_instructions. Check modifiers rather than flags for SHIFT | |
| 2640 | bit count and m[ft]{hi,lo} direction. | |
| 2641 | (usage): Pass program name to fprintf. | |
| 2642 | (main): Remove unused variable this_option_optind. Change | |
| 2643 | ``*loptarg++'' to ``loptarg++''. | |
| 2644 | (my_strtoul): Parenthesize && within ||. | |
| 350d33b8 | 2645 | * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd. |
| 831f59a2 ILT |
2646 | (simulate): If PC is odd, fetch a 16 bit instruction, and |
| 2647 | increment PC by 2 rather than 4. | |
| 2648 | * configure.in: Add case for mips16*-*-*. | |
| 2649 | * configure: Rebuild. | |
| 2650 | ||
| 2651 | Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com> | |
| 2652 | ||
| 2653 | * interp.c: Allow -t to enable tracing in standalone simulator. | |
| 2654 | Fix garbage output in trace file and error messages. | |
| 2655 | ||
| e3d12c65 DE |
2656 | Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com> |
| 2657 | ||
| 2658 | * Makefile.in: Delete stuff moved to ../common/Make-common.in. | |
| 2659 | (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define. | |
| 2660 | * configure.in: Simplify using macros in ../common/aclocal.m4. | |
| 2661 | * configure: Regenerated. | |
| 2662 | * tconfig.in: New file. | |
| 2663 | ||
| 2664 | Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com> | |
| 2665 | ||
| 2666 | * interp.c: Fix bugs in 64-bit port. | |
| 2667 | Use ansi function declarations for msvc compiler. | |
| 2668 | Initialize and test file pointer in trace code. | |
| 2669 | Prevent duplicate definition of LAST_EMED_REGNUM. | |
| 2670 | ||
| 2671 | Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com> | |
| 2672 | ||
| 2673 | * interp.c (xfer_big_long): Prevent unwanted sign extension. | |
| 2674 | ||
| 2675 | Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk> | |
| 2676 | ||
| 2677 | * interp.c (SignalException): Check for explicit terminating | |
| 2678 | breakpoint value. | |
| 2679 | * gencode.c: Pass instruction value through SignalException() | |
| 2680 | calls for Trap, Breakpoint and Syscall. | |
| 2681 | ||
| 2682 | Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk> | |
| 2683 | ||
| 2684 | * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is | |
| 2685 | only used on those hosts that provide it. | |
| 2686 | * configure.in: Add sqrt() to list of functions to be checked for. | |
| 2687 | * config.in: Re-generated. | |
| 2688 | * configure: Re-generated. | |
| 2689 | ||
| 2690 | Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com> | |
| 2691 | ||
| 2692 | * gencode.c (process_instructions): Call build_endian_shift when | |
| 2693 | expanding STORE RIGHT, to fix swr. | |
| 2694 | * support.h (SIGNEXTEND): If the sign bit is not set, explicitly | |
| 2695 | clear the high bits. | |
| 2696 | * interp.c (Convert): Fix fmt_single to fmt_long to not truncate. | |
| 2697 | Fix float to int conversions to produce signed values. | |
| 2698 | ||
| cc5201d7 ILT |
2699 | Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com> |
| 2700 | ||
| 458e1f58 ILT |
2701 | * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction. |
| 2702 | (process_instructions): Correct handling of nor instruction. | |
| 2703 | Correct shift count for 32 bit shift instructions. Correct sign | |
| 2704 | extension for arithmetic shifts to not shift the number of bits in | |
| 2705 | the type. Fix 64 bit multiply high word calculation. Fix 32 bit | |
| 2706 | unsigned multiply. Fix ldxc1 and friends to use coprocessor 1. | |
| 2707 | Fix madd. | |
| c05d1721 ILT |
2708 | * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC. |
| 2709 | It's OK to have a mult follow a mult. What's not OK is to have a | |
| 2710 | mult follow an mfhi. | |
| 458e1f58 | 2711 | (Convert): Comment out incorrect rounding code. |
| cc5201d7 | 2712 | |
| f24b7b69 JSC |
2713 | Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk> |
| 2714 | ||
| 2715 | * interp.c (sim_monitor): Improved monitor printf | |
| 2716 | simulation. Tidied up simulator warnings, and added "--log" option | |
| 2717 | for directing warning message output. | |
| 2718 | * gencode.c: Use sim_warning() rather than WARNING macro. | |
| 2719 | ||
| 2720 | Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com> | |
| 2721 | ||
| 2722 | * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and | |
| 2723 | getopt1.o, rather than on gencode.c. Link objects together. | |
| 2724 | Don't link against -liberty. | |
| 2725 | (gencode.o, getopt.o, getopt1.o): New targets. | |
| 2726 | * gencode.c: Include <ctype.h> and "ansidecl.h". | |
| 2727 | (AND): Undefine after including "ansidecl.h". | |
| 2728 | (ULONG_MAX): Define if not defined. | |
| 2729 | (OP_*): Don't define macros; now defined in opcode/mips.h. | |
| 2730 | (main): Call my_strtoul rather than strtoul. | |
| 2731 | (my_strtoul): New static function. | |
| 2732 | ||
| 2733 | Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com) | |
| 2734 | ||
| 2735 | * gencode.c (process_instructions): Generate word64 and uword64 | |
| 2736 | instead of `long long' and `unsigned long long' data types. | |
| 2737 | * interp.c: #include sysdep.h to get signals, and define default | |
| 2738 | for SIGBUS. | |
| 2739 | * (Convert): Work around for Visual-C++ compiler bug with type | |
| 2740 | conversion. | |
| 2741 | * support.h: Make things compile under Visual-C++ by using | |
| 2742 | __int64 instead of `long long'. Change many refs to long long | |
| 2743 | into word64/uword64 typedefs. | |
| 2744 | ||
| a271d1d9 JM |
2745 | Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp) |
| 2746 | ||
| 2747 | * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir, | |
| 2748 | INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values. | |
| 2749 | (docdir): Removed. | |
| 2750 | * configure.in (AC_PREREQ): autoconf 2.5 or higher. | |
| 2751 | (AC_PROG_INSTALL): Added. | |
| 2752 | (AC_PROG_CC): Moved to before configure.host call. | |
| 2753 | * configure: Rebuilt. | |
| 2754 | ||
| 2755 | Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk> | |
| 2756 | ||
| 2757 | * configure.in: Define @SIMCONF@ depending on mips target. | |
| 2758 | * configure: Rebuild. | |
| 2759 | * Makefile.in (run): Add @SIMCONF@ to control simulator | |
| 2760 | construction. | |
| 2761 | * gencode.c: Change LOADDRMASK to 64bit memory model only. | |
| 2762 | * interp.c: Remove some debugging, provide more detailed error | |
| 2763 | messages, update memory accesses to use LOADDRMASK. | |
| 2764 | ||
| 4fa134be ILT |
2765 | Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com> |
| 2766 | ||
| 2767 | * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS, | |
| 2768 | AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set | |
| 2769 | stamp-h. | |
| 2770 | * configure: Rebuild. | |
| 2771 | * config.in: New file, generated by autoheader. | |
| 2772 | * interp.c: Include "config.h". Include <stdlib.h>, <string.h>, | |
| 2773 | and <strings.h> if they exist. Replace #ifdef sun with #ifdef | |
| 2774 | HAVE_ANINT and HAVE_AINT, as appropriate. | |
| 2775 | * Makefile.in (run): Use @LIBS@ rather than -lm. | |
| 2776 | (interp.o): Depend upon config.h. | |
| 2777 | (Makefile): Just rebuild Makefile. | |
| 2778 | (clean): Remove stamp-h. | |
| 2779 | (mostlyclean): Make the same as clean, not as distclean. | |
| 2780 | (config.h, stamp-h): New targets. | |
| 2781 | ||
| 2782 | Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk> | |
| 2783 | ||
| 2784 | * interp.c (ColdReset): Fix boolean test. Make all simulator | |
| 2785 | globals static. | |
| 2786 | ||
| f7481d45 JSC |
2787 | Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk> |
| 2788 | ||
| 2789 | * interp.c (xfer_direct_word, xfer_direct_long, | |
| 2790 | swap_direct_word, swap_direct_long, xfer_big_word, | |
| 2791 | xfer_big_long, xfer_little_word, xfer_little_long, | |
| 2792 | swap_word,swap_long): Added. | |
| 2793 | * interp.c (ColdReset): Provide function indirection to | |
| 2794 | host<->simulated_target transfer routines. | |
| 2795 | * interp.c (sim_store_register, sim_fetch_register): Updated to | |
| 2796 | make use of indirected transfer routines. | |
| 2797 | ||
| 2798 | Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk> | |
| 2799 | ||
| 2800 | * gencode.c (process_instructions): Ensure FP ABS instruction | |
| 2801 | recognised. | |
| 2802 | * interp.c (AbsoluteValue): Add routine. Also provide simple PMON | |
| 2803 | system call support. | |
| 2804 | ||
| 8b554809 JSC |
2805 | Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk> |
| 2806 | ||
| 2807 | * interp.c (sim_do_command): Complain if callback structure not | |
| 2808 | initialised. | |
| 2809 | ||
| d0757082 JSC |
2810 | Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk> |
| 2811 | ||
| 2812 | * interp.c (Convert): Provide round-to-nearest and round-to-zero | |
| 2813 | support for Sun hosts. | |
| 2814 | * Makefile.in (gencode): Ensure the host compiler and libraries | |
| 2815 | used for cross-hosted build. | |
| 2816 | ||
| e871dd18 JSC |
2817 | Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk> |
| 2818 | ||
| 2819 | * interp.c, gencode.c: Some more (TODO) tidying. | |
| 2820 | ||
| 2821 | Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk> | |
| 2822 | ||
| 2823 | * gencode.c, interp.c: Replaced explicit long long references with | |
| 2824 | WORD64HI, WORD64LO, SET64HI and SET64LO macro calls. | |
| 2825 | * support.h (SET64LO, SET64HI): Macros added. | |
| 2826 | ||
| 5c59ec43 ILT |
2827 | Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com> |
| 2828 | ||
| 2829 | * configure: Regenerate with autoconf 2.7. | |
| 2830 | ||
| 2831 | Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com> | |
| 2832 | ||
| 2833 | * interp.c (LoadMemory): Enclose text following #endif in /* */. | |
| 2834 | * support.h: Remove superfluous "1" from #if. | |
| 2835 | * support.h (CHECKSIM): Remove stray 'a' at end of line. | |
| 2836 | ||
| 2837 | Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com> | |
| 2838 | ||
| 2839 | * interp.c (StoreFPR): Control UndefinedResult() call on | |
| 2840 | WARN_RESULT manifest. | |
| 2841 | ||
| 8bae0a0c JSC |
2842 | Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk> |
| 2843 | ||
| 2844 | * gencode.c: Tidied instruction decoding, and added FP instruction | |
| 2845 | support. | |
| 2846 | ||
| 2847 | * interp.c: Added dineroIII, and BSD profiling support. Also | |
| 2848 | run-time FP handling. | |
| 2849 | ||
| 2850 | Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk> | |
| 2851 | ||
| 2852 | * Changelog, Makefile.in, README.Cygnus, configure, configure.in, | |
| 2853 | gencode.c, interp.c, support.h: created. |