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[gdb/testsuite] Fix gdb.threads/fork-plus-threads.exp with readnow
[deliverable/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
77c0fdb7
MF		 12021-05-04 Mike Frysinger <vapier@gentoo.org>
2
3 * dv-tx3904sio.c: Include stdlib.h.
4
9b1af85c
MF		 52021-05-04 Mike Frysinger <vapier@gentoo.org>
6
7 * configure.ac (hw_extra_devices): Inline contents into
8 SIM_AC_OPTION_HARDWARE and delete.
9 * configure: Regenerate.
10
d97ba9c6
MF		 112021-05-04 Mike Frysinger <vapier@gentoo.org>
12
13 * Makefile.in (SIM_IGEN_OBJ): Change @mips_igen_engine@ to engine.o.
14 (MIPS_EXTRA_LIB, SIM_EXTRA_LIBS): Delete.
15 * configure.ac (mips_igen_engine, mips_extra_libs): Delete.
16 * configure: Regenerate.
17
4df817de
MF		 182021-05-04 Mike Frysinger <vapier@gentoo.org>
19
20 * mdmx.c (qh_acc): Change 2nd AccAddAQH to AccAddLQH.
21
aa0fca16
MF		 222021-05-04 Mike Frysinger <vapier@gentoo.org>
23
24 * configure: Regenerate.
25
adbaa7b8
MF		 262021-05-01 Mike Frysinger <vapier@gentoo.org>
27
28 * cp1.c (store_fcr): Mark static.
29
fe348617
MF		 302021-05-01 Mike Frysinger <vapier@gentoo.org>
31
32 * config.in, configure: Regenerate.
33
9d903352
MF		 342021-04-23 Mike Frysinger <vapier@gentoo.org>
35
36 * configure.ac (hw_enabled): Delete.
37 (SIM_AC_OPTION_HARDWARE): Delete first two args.
38 * configure: Regenerate.
39
19f6a43c
TT		 402021-04-22 Tom Tromey <tom@tromey.com>
41
42 * configure, config.in: Rebuild.
43
e7d8f1da
TT		 442021-04-22 Tom Tromey <tom@tromey.com>
45
46 * Makefile.in (interp.o, m16run.o, micromipsrun.o, multi-run.o):
47 Remove.
48 (SIM_EXTRA_DEPS): New variable.
49
efd82ac7
TT		 502021-04-22 Tom Tromey <tom@tromey.com>
51
52 * configure: Rebuild.
53
2662c237
MF		 542021-04-21 Mike Frysinger <vapier@gentoo.org>
55
56 * aclocal.m4: Regenerate.
57
1f195bc3
SM		 582021-04-21 Simon Marchi <simon.marchi@polymtl.ca>
59
60 * configure: Regenerate.
61
37e9f182
MF		 622021-04-18 Mike Frysinger <vapier@gentoo.org>
63
64 * configure: Regenerate.
65
d5a71b11
MF		 662021-04-12 Mike Frysinger <vapier@gentoo.org>
67
68 * interp.c (sim_open): Delete 3rd arg to sim_cpu_alloc_all.
69
2b8d134b
SM		 702021-04-08 Simon Marchi <simon.marchi@polymtl.ca>
71
72 * Makefile.in: Set ASAN_OPTIONS when running igen.
73
5c6f091a
FS		 742021-04-04 Steve Ellcey <sellcey@mips.com>
75 Faraz Shahbazker <fshahbazker@wavecomp.com>
76
77 * interp.c (sim_monitor): Add switch entries for unlink (13),
78 lseek (14), and stat (15).
79
b6b1c790
MF		 802021-04-02 Mike Frysinger <vapier@gentoo.org>
81
82 * Makefile.in (../igen/igen): Delete rule.
83 (tmp-igen, tmp-m16, tmp-micromips): Delete ../igen make.
84
c2783492
MF		 852021-04-02 Mike Frysinger <vapier@gentoo.org>
86
87 * aclocal.m4, configure: Regenerate.
88
ebe9564b
MF		 892021-02-28 Mike Frysinger <vapier@gentoo.org>
90
91 * configure: Regenerate.
92
f8069d55
MF		 932021-02-27 Mike Frysinger <vapier@gentoo.org>
94
95 * Makefile.in (SIM_EXTRA_ALL): Delete.
96 (all): New target.
97
760b3e8b
MF		 982021-02-21 Mike Frysinger <vapier@gentoo.org>
99
100 * configure.ac (AC_CONFIG_MACRO_DIRS): Replace common with m4.
101 * aclocal.m4, configure: Regenerate.
102
136da8cd
MF		 1032021-02-13 Mike Frysinger <vapier@gentoo.org>
104
105 * configure.ac: Replace sinclude with AC_CONFIG_MACRO_DIRS.
106 * aclocal.m4, configure: Regenerate.
107
4c0d76b9
MF		 1082021-02-06 Mike Frysinger <vapier@gentoo.org>
109
110 * interp.c (sim_open): Delete call to STATE_WATCHPOINTS.
111
aa09469f
MF		 1122021-02-06 Mike Frysinger <vapier@gentoo.org>
113
114 * configure: Regenerate.
115
d4e3adda
MF		 1162021-01-30 Mike Frysinger <vapier@gentoo.org>
117
118 * interp.c (sim_open): Delete STATE_WATCHPOINTS (sd)->sizeof_pc.
119
68ed2854
MF		 1202021-01-11 Mike Frysinger <vapier@gentoo.org>
121
122 * config.in, configure: Regenerate.
123 * interp.c: Delete HAVE_STRING_H, HAVE_STRINGS_H, HAVE_STDLIB_H,
124 and strings.h include.
125
50df264d
MF		 1262021-01-09 Mike Frysinger <vapier@gentoo.org>
127
128 * configure: Regenerate.
129
bf470982
MF		 1302021-01-09 Mike Frysinger <vapier@gentoo.org>
131
132 * configure.ac (SIM_AC_OPTION_WARNINGS): Pass "no".
133 * configure: Regenerate.
134
46f900c0
MF		 1352021-01-08 Mike Frysinger <vapier@gentoo.org>
136
137 * configure: Regenerate.
138
dfb856ba
MF		 1392021-01-04 Mike Frysinger <vapier@gentoo.org>
140
141 * configure: Regenerate.
142
382bc56b
PK		 1432020-12-31 Pavel I. Kryukov <kryukov@frtk.ru> (tiny change)
144
145 * sim-main.c: Include <stdlib.h>.
146
ad9675dd
PK		 1472020-12-14 Pavel I. Kryukov <kryukov@frtk.ru> (tiny change)
148
149 * cp1.c: Include <stdlib.h>.
150
f693213d
SM		 1512020-07-29 Simon Marchi <simon.marchi@efficios.com>
152
153 * configure: Re-generate.
154
5c887dd5
JB		 1552017-09-06 John Baldwin <jhb@FreeBSD.org>
156
157 * configure: Regenerate.
158
91588b3a
MF		 1592016-11-11 Mike Frysinger <vapier@gentoo.org>
160
6cb2202b 161 PR sim/20808
91588b3a
MF		 162 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Define CPU to cpu
163 and SD to sd.
164
e04659e8
MF		 1652016-11-11 Mike Frysinger <vapier@gentoo.org>
166
6cb2202b 167 PR sim/20809
e04659e8
MF		 168 * mips.igen (check_u64): Enable for `r3900'.
169
1554f758
MF		 1702016-02-05 Mike Frysinger <vapier@gentoo.org>
171
172 * configure.ac (sim_engine_run): Change sd->base.prog_bfd to
173 STATE_PROG_BFD (sd).
174 * configure: Regenerate.
175
3d304f48
AB		 1762016-01-18 Andrew Bennett <andrew.bennett@imgtec.com>
177 Maciej W. Rozycki <macro@imgtec.com>
178
179 PR sim/19441
180 * micromips.igen (delayslot_micromips): Enable for `micromips32',
181 `micromips64' and `micromipsdsp' only.
182 (process_isa_mode): Enable for `micromips32' and `micromips64' only.
183 (do_micromips_jalr, do_micromips_jal): Likewise.
184 (compute_movep_src_reg): Likewise.
185 (compute_andi16_imm): Likewise.
186 (convert_fmt_micromips): Likewise.
187 (convert_fmt_micromips_cvt_d): Likewise.
188 (convert_fmt_micromips_cvt_s): Likewise.
189 (FMT_MICROMIPS): Likewise.
190 (FMT_MICROMIPS_CVT_D): Likewise.
191 (FMT_MICROMIPS_CVT_S): Likewise.
192
b36d953b
MF		 1932016-01-12 Mike Frysinger <vapier@gentoo.org>
194
195 * interp.c: Include elf-bfd.h.
196 (sim_create_inferior): Truncate pc to 32-bits when EI_CLASS is
197 ELFCLASS32.
198
ce39bd38
MF		 1992016-01-10 Mike Frysinger <vapier@gentoo.org>
200
201 * config.in, configure: Regenerate.
202
99d8e879
MF		 2032016-01-10 Mike Frysinger <vapier@gentoo.org>
204
205 * configure: Regenerate.
206
35656e95
MF		 2072016-01-10 Mike Frysinger <vapier@gentoo.org>
208
209 * configure: Regenerate.
210
16f7876d
MF		 2112016-01-10 Mike Frysinger <vapier@gentoo.org>
212
213 * configure: Regenerate.
214
e19418e0
MF		 2152016-01-10 Mike Frysinger <vapier@gentoo.org>
216
217 * configure: Regenerate.
218
6d90347b
MF		 2192016-01-10 Mike Frysinger <vapier@gentoo.org>
220
221 * configure.ac (SIM_AC_OPTION_SMP): Delete call.
222 * configure: Regenerate.
223
347fe5bb
MF		 2242016-01-10 Mike Frysinger <vapier@gentoo.org>
225
226 * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
227 * configure: Regenerate.
228
22be3fbe
MF		 2292016-01-10 Mike Frysinger <vapier@gentoo.org>
230
231 * configure: Regenerate.
232
0dc73ef7
MF		 2332016-01-10 Mike Frysinger <vapier@gentoo.org>
234
235 * configure: Regenerate.
236
936df756
MF		 2372016-01-09 Mike Frysinger <vapier@gentoo.org>
238
239 * config.in, configure: Regenerate.
240
2e3d4f4d
MF		 2412016-01-06 Mike Frysinger <vapier@gentoo.org>
242
243 * interp.c (sim_open): Mark argv const.
244 (sim_create_inferior): Mark argv and env const.
245
9bbf6f91
MF		 2462016-01-04 Mike Frysinger <vapier@gentoo.org>
247
248 * configure: Regenerate.
249
77cf2ef5
MF		 2502016-01-03 Mike Frysinger <vapier@gentoo.org>
251
252 * interp.c (sim_open): Update sim_parse_args comment.
253
0cb8d851
MF		 2542016-01-03 Mike Frysinger <vapier@gentoo.org>
255
256 * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
257 * configure: Regenerate.
258
1ac72f06
MF		 2592016-01-02 Mike Frysinger <vapier@gentoo.org>
260
261 * configure.ac (mips_endian): Change LITTLE_ENDIAN to LITTLE.
262 (default_endian): Likewise. Change BIG_ENDIAN to BIG.
263 * configure: Regenerate.
264 * sim-main.h (BigEndianMem): Change BIG_ENDIAN to BFD_ENDIAN_BIG.
265
d47f5b30
MF		 2662016-01-02 Mike Frysinger <vapier@gentoo.org>
267
268 * dv-tx3904cpu.c (CPU, SD): Delete.
269
e1211e55
MF		 2702015-12-30 Mike Frysinger <vapier@gentoo.org>
271
272 * wrapper.c (mips_reg_store, mips_reg_fetch): Define.
273 (sim_open): Call CPU_REG_FETCH/CPU_REG_STORE.
274 (sim_store_register): Rename to ...
275 (mips_reg_store): ... this. Delete local cpu var.
276 Update sim_io_eprintf calls.
277 (sim_fetch_register): Rename to ...
278 (mips_reg_fetch): ... this. Delete local cpu var.
279 Update sim_io_eprintf calls.
280
5e744ef8
MF		 2812015-12-27 Mike Frysinger <vapier@gentoo.org>
282
283 * Makefile.in (SIM_OBJS): Delete sim-hload.o.
284
1b393626
MF		 2852015-12-26 Mike Frysinger <vapier@gentoo.org>
286
287 * config.in, configure: Regenerate.
288
26f8bf63
MF		 2892015-12-26 Mike Frysinger <vapier@gentoo.org>
290
291 * interp.c (sim_write, sim_read): Delete.
292 (store_word): Delete call to AddressTranslation and set paddr=vaddr.
293 (load_word): Likewise.
294 * micromips.igen (cache): Likewise.
295 * mips.igen (do_ll, do_lld, do_sc, do_scd, do_suxc1_32, do_swc1,
296 do_swxc1, cache, do_load, do_load_left, do_load_right, do_store,
297 do_store_left, do_store_right, do_load_double, do_store_double):
298 Likewise.
299 (do_pref): Delete call to AddressTranslation and stub out Prefetch.
300 (do_prefx): Likewise.
301 * sim-main.c (address_translation, prefetch): Delete.
302 (ifetch32, ifetch16): Delete call to AddressTranslation and set
303 paddr=vaddr.
304 * sim-main.h (Uncached, CachedNoncoherent, CachedCoherent, Cached,
305 address_translation, AddressTranslation, prefetch, Prefetch): Delete.
306 (LoadMemory, StoreMemory): Delete CCA arg.
307
ef04e371
MF		 3082015-12-24 Mike Frysinger <vapier@gentoo.org>
309
310 * configure.ac (SIM_SUBTARGET): Drop -DTARGET_TX3904=1.
311 * configure: Regenerated.
312
cb379ede
MF		 3132015-12-24 Mike Frysinger <vapier@gentoo.org>
314
315 * sim-main.h (SIM_QUIET_NAN_NEGATED): Move from tconfig.h.
316 * tconfig.h: Delete.
317
26936211
MF		 3182015-12-24 Mike Frysinger <vapier@gentoo.org>
319
320 * tconfig.h (SIM_HANDLES_LMA): Delete.
321
84e8e361
MF		 3222015-12-24 Mike Frysinger <vapier@gentoo.org>
323
324 * sim-main.h (WITH_WATCHPOINTS): Delete.
325
3cabaf66
MF		 3262015-12-24 Mike Frysinger <vapier@gentoo.org>
327
328 * interp.c [SIM_HAVE_FLATMEM] (sim_open): Delete flatmem code.
329
8abe6c66
MF		 3302015-12-24 Mike Frysinger <vapier@gentoo.org>
331
332 * tconfig.h (SIM_HAVE_SIMCACHE): Delete.
333
1d19cae7
DV		 3342015-12-15 Dominik Vogt <vogt@linux.vnet.ibm.com>
335
336 * micromips.igen (process_isa_mode): Fix left shift of negative
337 value.
338
cdf850e9
MF		 3392015-11-17 Mike Frysinger <vapier@gentoo.org>
340
341 * sim-main.h (WITH_MODULO_MEMORY): Delete.
342
797eee42
MF		 3432015-11-15 Mike Frysinger <vapier@gentoo.org>
344
345 * Makefile.in (SIM_OBJS): Delete sim-reason.o and sim-stop.o.
346
6e4f085c
MF		 3472015-11-14 Mike Frysinger <vapier@gentoo.org>
348
349 * interp.c (sim_close): Rename to ...
350 (mips_sim_close): ... this. Delete calls to sim_module_uninstall and
351 sim_io_shutdown.
352 * sim-main.h (mips_sim_close): Declare.
353 (SIM_CLOSE_HOOK): Define.
354
8e394ffc
AB		 3552015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
356 Ali Lown <ali.lown@imgtec.com>
357
358 * Makefile.in (tmp-micromips): New rule.
359 (tmp-mach-multi): Add support for micromips.
360 * configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
361 that works for both mips64 and micromips64.
362 (mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
363 micromips32.
364 Add build support for micromips.
365 * dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
366 do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
367 do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
368 do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
369 do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
370 do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
371 do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
372 do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
373 Refactored instruction code to use these functions.
374 * dsp2.igen: Refactored instruction code to use the new functions.
375 * interp.c (decode_coproc): Refactored to work with any instruction
376 encoding.
377 (isa_mode): New variable
378 (RSVD_INSTRUCTION): Changed to 0x00000039.
379 * m16.igen (BREAK16): Refactored instruction to use do_break16.
380 (JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
381 * micromips.dc: New file.
382 * micromips.igen: New file.
383 * micromips16.dc: New file.
384 * micromipsdsp.igen: New file.
385 * micromipsrun.c: New file.
386 * mips.igen (do_swc1): Changed to work with any instruction encoding.
387 (do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
388 do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo,
389 do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu,
390 do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu,
391 do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub,
392 do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo,
393 do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc,
394 do_scd, do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu,
395 do_tgeu, do_tlt do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt,
396 do_add_fmt, do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1,
397 do_cvt_d_fmt, do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl,
398 do_cvt_s_pu, do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt,
399 do_luxc1_32, do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b,
400 do_mov_fmt, do_movtf, do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt,
401 do_mtc1b, do_mul_fmt, do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps,
402 do_plu_ps, do_pul_ps, do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt,
403 do_prefx, do_sdc1, do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt,
404 do_swc1, do_swxc1, do_trunc_fmt): New functions, refactored from existing
405 instructions.
406 Refactored instruction code to use these functions.
407 (RSVD): Changed to use new reserved instruction.
408 (loadstore_ea, not_word_value, unpredictable, check_mt_hilo,
409 check_mf_hilo, check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32,
410 do_sdc1, do_suxc1_32, check_fmt_p, check_fpu, do_load_double,
411 do_store_double): Added micromips32 and micromips64 models.
412 Added include for micromips.igen and micromipsdsp.igen
413 Add micromips32 and micromips64 models.
414 (DecodeCoproc): Updated to use new macro definition.
415 * mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
416 do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
417 do_seb, do_seh do_rdhwr, do_wsbh): New functions.
418 Refactored instruction code to use these functions.
419 * sim-main.h (CP0_operation): New enum.
420 (DecodeCoproc): Updated macro.
421 (IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
422 MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16,
423 MICROMIPS_DELAYSLOT_SIZE_32, ISA_MODE_MIPS32 and
424 ISA_MODE_MICROMIPS): New defines.
425 (sim_state): Add isa_mode field.
426
8d0978fb
MF		 4272015-06-23 Mike Frysinger <vapier@gentoo.org>
428
429 * configure: Regenerate.
430
306f4178
MF		 4312015-06-12 Mike Frysinger <vapier@gentoo.org>
432
433 * configure.ac: Change configure.in to configure.ac.
434 * configure: Regenerate.
435
a3487082
MF		 4362015-06-12 Mike Frysinger <vapier@gentoo.org>
437
438 * configure: Regenerate.
439
29bc024d
MF		 4402015-06-12 Mike Frysinger <vapier@gentoo.org>
441
442 * interp.c [TRACE]: Delete.
443 (TRACE): Change to WITH_TRACE_ANY_P.
444 [!WITH_TRACE_ANY_P] (open_trace): Define.
445 (mips_option_handler, open_trace, sim_close, dotrace):
446 Change defined(TRACE) to WITH_TRACE_ANY_P.
447 (sim_open): Delete TRACE ifdef check.
448 * sim-main.c (load_memory): Delete TRACE ifdef check.
449 (store_memory): Likewise.
450 * sim-main.h [WITH_TRACE_ANY_P] (dotrace, tracefh): Protect decls.
451 [!WITH_TRACE_ANY_P] (dotrace): Define.
452
3ebe2863
MF		 4532015-04-18 Mike Frysinger <vapier@gentoo.org>
454
455 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESTART_HOOK): Delete
456 comments.
457
20bca71d
MF		 4582015-04-18 Mike Frysinger <vapier@gentoo.org>
459
460 * sim-main.h (SIM_CPU): Delete.
461
7e83aa92
MF		 4622015-04-18 Mike Frysinger <vapier@gentoo.org>
463
464 * sim-main.h (sim_cia): Delete.
465
034685f9
MF		 4662015-04-17 Mike Frysinger <vapier@gentoo.org>
467
468 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Change CIA_GET to
469 PU_PC_GET.
470 * interp.c (interrupt_event): Change CIA_GET to CPU_PC_GET.
471 (sim_create_inferior): Change CIA_SET to CPU_PC_SET.
472 * m16run.c (sim_engine_run): Change CIA_GET to CPU_PC_GET and
473 CIA_SET to CPU_PC_SET.
474 * sim-main.h (CIA_GET, CIA_SET): Delete.
475
78e9aa70
MF		 4762015-04-15 Mike Frysinger <vapier@gentoo.org>
477
478 * Makefile.in (SIM_OBJS): Delete sim-cpu.o.
479 * sim-main.h (STATE_CPU): Delete.
480
bf12d44e
MF		 4812015-04-13 Mike Frysinger <vapier@gentoo.org>
482
483 * configure: Regenerate.
484
7bebb329
MF		 4852015-04-13 Mike Frysinger <vapier@gentoo.org>
486
487 * Makefile.in (SIM_OBJS): Add sim-cpu.o.
488 * interp.c (mips_pc_get, mips_pc_set): New functions.
489 (sim_open): Declare new local var i. Call sim_cpu_alloc_all.
490 Call CPU_PC_FETCH & CPU_PC_STORE for all cpus.
491 (sim_pc_get): Delete.
492 * sim-main.h (SIM_CPU): Define.
493 (struct sim_state): Change cpu to an array of pointers.
494 (STATE_CPU): Drop &.
495
8ac57fbd
MF		 4962015-04-13 Mike Frysinger <vapier@gentoo.org>
497
498 * interp.c (mips_option_handler, open_trace, sim_close,
499 sim_write, sim_read, sim_store_register, sim_fetch_register,
500 sim_create_inferior, pr_addr, pr_uword64): Convert old style
501 prototypes.
502 (sim_open): Convert old style prototype. Change casts with
503 sim_write to unsigned char *.
504 (fetch_str): Change null to unsigned char, and change cast to
505 unsigned char *.
506 (sim_monitor): Change c & ch to unsigned char. Change cast to
507 unsigned char *.
508
e787f858
MF		 5092015-04-12 Mike Frysinger <vapier@gentoo.org>
510
511 * Makefile.in (SIM_OBJS): Move interp.o to the start of the list.
512
122bbfb5
MF		 5132015-04-06 Mike Frysinger <vapier@gentoo.org>
514
515 * Makefile.in (SIM_OBJS): Delete sim-engine.o.
516
0fe84f3f
MF		 5172015-04-01 Mike Frysinger <vapier@gentoo.org>
518
519 * tconfig.h (SIM_HAVE_PROFILE): Delete.
520
aadc9410
MF		 5212015-03-31 Mike Frysinger <vapier@gentoo.org>
522
523 * config.in, configure: Regenerate.
524
05f53ed6
MF		 5252015-03-24 Mike Frysinger <vapier@gentoo.org>
526
527 * interp.c (sim_pc_get): New function.
528
c0931f26
MF		 5292015-03-24 Mike Frysinger <vapier@gentoo.org>
530
531 * sim-main.h (SIM_HAVE_BIENDIAN): Delete.
532 * tconfig.h (SIM_HAVE_BIENDIAN): Delete.
533
30452bbe
MF		 5342015-03-24 Mike Frysinger <vapier@gentoo.org>
535
536 * configure: Regenerate.
537
64dd13df
MF		 5382015-03-23 Mike Frysinger <vapier@gentoo.org>
539
540 * configure: Regenerate.
541
49cd1634
MF		 5422015-03-23 Mike Frysinger <vapier@gentoo.org>
543
544 * configure: Regenerate.
545 * configure.ac (mips_extra_objs): Delete.
546 * Makefile.in (MIPS_EXTRA_OBJS): Delete.
547 (SIM_OBJS): Delete MIPS_EXTRA_OBJS.
548
3649cb06
MF		 5492015-03-23 Mike Frysinger <vapier@gentoo.org>
550
551 * configure: Regenerate.
552 * configure.ac: Delete sim_hw checks for dv-sockser.
553
ae7d0cac
MF		 5542015-03-16 Mike Frysinger <vapier@gentoo.org>
555
556 * config.in, configure: Regenerate.
557 * tconfig.in: Rename file ...
558 * tconfig.h: ... here.
559
8406bb59
MF		 5602015-03-15 Mike Frysinger <vapier@gentoo.org>
561
562 * tconfig.in: Delete includes.
563 [HAVE_DV_SOCKSER]: Delete.
564
465fb143
MF		 5652015-03-14 Mike Frysinger <vapier@gentoo.org>
566
567 * Makefile.in (SIM_RUN_OBJS): Delete.
568
5cddc23a
MF		 5692015-03-14 Mike Frysinger <vapier@gentoo.org>
570
571 * configure.ac (AC_CHECK_HEADERS): Delete.
572 * aclocal.m4, configure: Regenerate.
573
2974be62
AM		 5742014-08-19 Alan Modra <amodra@gmail.com>
575
576 * configure: Regenerate.
577
faa743bb
RM		 5782014-08-15 Roland McGrath <mcgrathr@google.com>
579
580 * configure: Regenerate.
581 * config.in: Regenerate.
582
1a8a700e
MF		 5832014-03-04 Mike Frysinger <vapier@gentoo.org>
584
585 * configure: Regenerate.
586
bf3d9781
AM		 5872013-09-23 Alan Modra <amodra@gmail.com>
588
589 * configure: Regenerate.
590
31e6ad7d
MF		 5912013-06-03 Mike Frysinger <vapier@gentoo.org>
592
593 * aclocal.m4, configure: Regenerate.
594
d3685d60
TT		 5952013-05-10 Freddie Chopin <freddie_chopin@op.pl>
596
597 * configure: Rebuild.
598
1517bd27
MF		 5992013-03-26 Mike Frysinger <vapier@gentoo.org>
600
601 * configure: Regenerate.
602
3be31516
JS		 6032013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
604
605 * configure.ac: Address use of dv-sockser.o.
606 * tconfig.in: Conditionalize use of dv_sockser_install.
607 * configure: Regenerated.
608 * config.in: Regenerated.
609
37cb8f8e
SE		 6102012-10-04 Chao-ying Fu <fu@mips.com>
611 Steve Ellcey <sellcey@mips.com>
612
613 * mips/mips3264r2.igen (rdhwr): New.
614
87c8644f
JS		 6152012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
616
617 * configure.ac: Always link against dv-sockser.o.
618 * configure: Regenerate.
619
5f3ef9d0
JB		 6202012-06-15 Joel Brobecker <brobecker@adacore.com>
621
622 * config.in, configure: Regenerate.
623
a6ff997c
NC		 6242012-05-18 Nick Clifton <nickc@redhat.com>
625
626 PR 14072
627 * interp.c: Include config.h before system header files.
628
2232061b
MF		 6292012-03-24 Mike Frysinger <vapier@gentoo.org>
630
631 * aclocal.m4, config.in, configure: Regenerate.
632
db2e4d67
MF		 6332011-12-03 Mike Frysinger <vapier@gentoo.org>
634
635 * aclocal.m4: New file.
636 * configure: Regenerate.
637
4399a56b
MF		 6382011-10-19 Mike Frysinger <vapier@gentoo.org>
639
640 * configure: Regenerate after common/acinclude.m4 update.
641
9c082ca8
MF		 6422011-10-17 Mike Frysinger <vapier@gentoo.org>
643
644 * configure.ac: Change include to common/acinclude.m4.
645
6ffe910a
MF		 6462011-10-17 Mike Frysinger <vapier@gentoo.org>
647
648 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
649 call. Replace common.m4 include with SIM_AC_COMMON.
650 * configure: Regenerate.
651
31b28250
HPN		 6522011-07-08 Hans-Peter Nilsson <hp@axis.com>
653
3faa01e3
HPN		 654 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
655 $(SIM_EXTRA_DEPS).
656 (tmp-mach-multi): Exit early when igen fails.
31b28250 657
2419798b
MF		 6582011-07-05 Mike Frysinger <vapier@gentoo.org>
659
660 * interp.c (sim_do_command): Delete.
661
d79fe0d6
MF		 6622011-02-14 Mike Frysinger <vapier@gentoo.org>
663
664 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
665 (tx3904sio_fifo_reset): Likewise.
666 * interp.c (sim_monitor): Likewise.
667
5558e7e6
MF		 6682010-04-14 Mike Frysinger <vapier@gentoo.org>
669
670 * interp.c (sim_write): Add const to buffer arg.
671
35aafff4
JB		 6722010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
673
674 * interp.c: Don't include sysdep.h
675
3725885a
RW		 6762010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
677
678 * configure: Regenerate.
679
d6416cdc
RW		 6802009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
681
81ecdfbb
RW		 682 * config.in: Regenerate.
683 * configure: Likewise.
684
d6416cdc
RW		 685 * configure: Regenerate.
686
b5bd9624
HPN		 6872008-07-11 Hans-Peter Nilsson <hp@axis.com>
688
689 * configure: Regenerate to track ../common/common.m4 changes.
690 * config.in: Ditto.
691
6efef468 6922008-06-06 Vladimir Prus <vladimir@codesourcery.com>
72f4393d
L		 693 Daniel Jacobowitz <dan@codesourcery.com>
694 Joseph Myers <joseph@codesourcery.com>
6efef468
JM		 695
696 * configure: Regenerate.
697
60dc88db
RS		 6982007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
699
700 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
701 that unconditionally allows fmt_ps.
702 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
703 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
704 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
705 filter from 64,f to 32,f.
706 (PREFX): Change filter from 64 to 32.
707 (LDXC1, LUXC1): Provide separate mips32r2 implementations
708 that use do_load_double instead of do_load. Make both LUXC1
709 versions unpredictable if SizeFGR () != 64.
710 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
711 instead of do_store. Remove unused variable. Make both SUXC1
712 versions unpredictable if SizeFGR () != 64.
713
599ca73e
RS		 7142007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
715
716 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
717 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
718 shifts for that case.
719
2525df03
NC		 7202007-09-04 Nick Clifton <nickc@redhat.com>
721
722 * interp.c (options enum): Add OPTION_INFO_MEMORY.
723 (display_mem_info): New static variable.
724 (mips_option_handler): Handle OPTION_INFO_MEMORY.
725 (mips_options): Add info-memory and memory-info.
726 (sim_open): After processing the command line and board
727 specification, check display_mem_info. If it is set then
728 call the real handler for the --memory-info command line
729 switch.
730
35ee6e1e
JB		 7312007-08-24 Joel Brobecker <brobecker@adacore.com>
732
733 * configure.ac: Change license of multi-run.c to GPL version 3.
734 * configure: Regenerate.
735
d5fb0879
RS		 7362007-06-28 Richard Sandiford <richard@codesourcery.com>
737
738 * configure.ac, configure: Revert last patch.
739
2a2ce21b
RS		 7402007-06-26 Richard Sandiford <richard@codesourcery.com>
741
742 * configure.ac (sim_mipsisa3264_configs): New variable.
743 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
744 every configuration support all four targets, using the triplet to
745 determine the default.
746 * configure: Regenerate.
747
efdcccc9
RS		 7482007-06-25 Richard Sandiford <richard@codesourcery.com>
749
0a7692b2 750 * Makefile.in (m16run.o): New rule.
efdcccc9 751
f532a356
TS		 7522007-05-15 Thiemo Seufer <ths@mips.com>
753
754 * mips3264r2.igen (DSHD): Fix compile warning.
755
bfe9c90b
TS		 7562007-05-14 Thiemo Seufer <ths@mips.com>
757
758 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
759 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
760 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
761 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
762 for mips32r2.
763
53f4826b
TS		 7642007-03-01 Thiemo Seufer <ths@mips.com>
765
766 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
767 and mips64.
768
8bf3ddc8
TS		 7692007-02-20 Thiemo Seufer <ths@mips.com>
770
771 * dsp.igen: Update copyright notice.
772 * dsp2.igen: Fix copyright notice.
773
8b082fb1 7742007-02-20 Thiemo Seufer <ths@mips.com>
72f4393d 775 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 776
777 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
778 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
779 Add dsp2 to sim_igen_machine.
780 * configure: Regenerate.
781 * dsp.igen (do_ph_op): Add MUL support when op = 2.
782 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
783 (mulq_rs.ph): Use do_ph_mulq.
784 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
785 * mips.igen: Add dsp2 model and include dsp2.igen.
786 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
787 for *mips32r2, *mips64r2, *dsp.
788 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
789 for *mips32r2, *mips64r2, *dsp2.
790 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
791
b1004875 7922007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 793 Nigel Stephens <nigel@mips.com>
b1004875
TS		 794
795 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
796 jumps with hazard barrier.
797
f8df4c77 7982007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 799 Nigel Stephens <nigel@mips.com>
f8df4c77
TS		 800
801 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
802 after each call to sim_io_write.
803
b1004875 8042007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 805 Nigel Stephens <nigel@mips.com>
b1004875
TS		 806
807 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
808 supported by this simulator.
07802d98
TS		 809 (decode_coproc): Recognise additional CP0 Config registers
810 correctly.
811
14fb6c5a 8122007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d
L		 813 Nigel Stephens <nigel@mips.com>
814 David Ung <davidu@mips.com>
14fb6c5a
TS		 815
816 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
817 uninterpreted formats. If fmt is one of the uninterpreted types
818 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
819 fmt_word, and fmt_uninterpreted_64 like fmt_long.
820 (store_fpr): When writing an invalid odd register, set the
821 matching even register to fmt_unknown, not the following register.
822 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
823 the the memory window at offset 0 set by --memory-size command
824 line option.
825 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
826 point register.
827 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
828 register.
829 (sim_monitor): When returning the memory size to the MIPS
830 application, use the value in STATE_MEM_SIZE, not an arbitrary
831 hardcoded value.
832 (cop_lw): Don' mess around with FPR_STATE, just pass
833 fmt_uninterpreted_32 to StoreFPR.
834 (cop_sw): Similarly.
835 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
836 (cop_sd): Similarly.
837 * mips.igen (not_word_value): Single version for mips32, mips64
838 and mips16.
839
c8847145 8402007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 841 Nigel Stephens <nigel@mips.com>
c8847145
TS		 842
843 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
844 MBytes.
845
4b5d35ee
TS		 8462007-02-17 Thiemo Seufer <ths@mips.com>
847
848 * configure.ac (mips*-sde-elf*): Move in front of generic machine
849 configuration.
850 * configure: Regenerate.
851
3669427c
TS		 8522007-02-17 Thiemo Seufer <ths@mips.com>
853
854 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
855 Add mdmx to sim_igen_machine.
856 (mipsisa64*-*-*): Likewise. Remove dsp.
857 (mipsisa32*-*-*): Remove dsp.
858 * configure: Regenerate.
859
109ad085
TS		 8602007-02-13 Thiemo Seufer <ths@mips.com>
861
862 * configure.ac: Add mips*-sde-elf* target.
863 * configure: Regenerate.
864
921d7ad3
HPN		 8652006-12-21 Hans-Peter Nilsson <hp@axis.com>
866
867 * acconfig.h: Remove.
868 * config.in, configure: Regenerate.
869
02f97da7
TS		 8702006-11-07 Thiemo Seufer <ths@mips.com>
871
872 * dsp.igen (do_w_op): Fix compiler warning.
873
2d2733fc 8742006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 875 David Ung <davidu@mips.com>
2d2733fc
TS		 876
877 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
878 sim_igen_machine.
879 * configure: Regenerate.
880 * mips.igen (model): Add smartmips.
881 (MADDU): Increment ACX if carry.
882 (do_mult): Clear ACX.
883 (ROR,RORV): Add smartmips.
72f4393d 884 (include): Include smartmips.igen.
2d2733fc
TS		 885 * sim-main.h (ACX): Set to REGISTERS[89].
886 * smartmips.igen: New file.
887
d85c3a10 8882006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 889 David Ung <davidu@mips.com>
d85c3a10
TS		 890
891 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
892 mips3264r2.igen. Add missing dependency rules.
893 * m16e.igen: Support for mips16e save/restore instructions.
894
e85e3205
RE		 8952006-06-13 Richard Earnshaw <rearnsha@arm.com>
896
897 * configure: Regenerated.
898
2f0122dc
DJ		 8992006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
900
901 * configure: Regenerated.
902
20e95c23
DJ		 9032006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
904
905 * configure: Regenerated.
906
69088b17
CF		 9072006-05-15 Chao-ying Fu <fu@mips.com>
908
909 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
910
0275de4e
NC		 9112006-04-18 Nick Clifton <nickc@redhat.com>
912
913 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
914 statement.
915
b3a3ffef
HPN		 9162006-03-29 Hans-Peter Nilsson <hp@axis.com>
917
918 * configure: Regenerate.
919
40a5538e
CF		 9202005-12-14 Chao-ying Fu <fu@mips.com>
921
922 * Makefile.in (SIM_OBJS): Add dsp.o.
923 (dsp.o): New dependency.
924 (IGEN_INCLUDE): Add dsp.igen.
925 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
926 mipsisa64*-*-*): Add dsp to sim_igen_machine.
927 * configure: Regenerate.
928 * mips.igen: Add dsp model and include dsp.igen.
929 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
930 because these instructions are extended in DSP ASE.
931 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
932 adding 6 DSP accumulator registers and 1 DSP control register.
933 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
934 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
935 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
936 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
937 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
938 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
939 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
940 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
941 DSPCR_CCOND_SMASK): New define.
942 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
943 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
944
21d14896
ILT		 9452005-07-08 Ian Lance Taylor <ian@airs.com>
946
947 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
948
b16d63da 9492005-06-16 David Ung <davidu@mips.com>
72f4393d
L		 950 Nigel Stephens <nigel@mips.com>
951
952 * mips.igen: New mips16e model and include m16e.igen.
953 (check_u64): Add mips16e tag.
954 * m16e.igen: New file for MIPS16e instructions.
955 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
956 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
957 models.
958 * configure: Regenerate.
b16d63da 959
e70cb6cd 9602005-05-26 David Ung <davidu@mips.com>
72f4393d 961
e70cb6cd
CD		 962 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
963 tags to all instructions which are applicable to the new ISAs.
964 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
965 vr.igen.
966 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
72f4393d 967 instructions.
e70cb6cd
CD		 968 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
969 to mips.igen.
970 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
971 * configure: Regenerate.
72f4393d 972
2b193c4a
MK		 9732005-03-23 Mark Kettenis <kettenis@gnu.org>
974
975 * configure: Regenerate.
976
35695fd6
AC		 9772005-01-14 Andrew Cagney <cagney@gnu.org>
978
979 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
980 explicit call to AC_CONFIG_HEADER.
981 * configure: Regenerate.
982
f0569246
AC		 9832005-01-12 Andrew Cagney <cagney@gnu.org>
984
985 * configure.ac: Update to use ../common/common.m4.
986 * configure: Re-generate.
987
38f48d72
AC		 9882005-01-11 Andrew Cagney <cagney@localhost.localdomain>
989
990 * configure: Regenerated to track ../common/aclocal.m4 changes.
991
b7026657
AC		 9922005-01-07 Andrew Cagney <cagney@gnu.org>
993
994 * configure.ac: Rename configure.in, require autoconf 2.59.
995 * configure: Re-generate.
996
379832de
HPN		 9972004-12-08 Hans-Peter Nilsson <hp@axis.com>
998
999 * configure: Regenerate for ../common/aclocal.m4 update.
1000
cd62154c 10012004-09-24 Monika Chaddha <monika@acmet.com>
72f4393d 1002
cd62154c
AC		 1003 Committed by Andrew Cagney.
1004 * m16.igen (CMP, CMPI): Fix assembler.
1005
e5da76ec
CD		 10062004-08-18 Chris Demetriou <cgd@broadcom.com>
1007
1008 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
1009 * configure: Regenerate.
1010
139181c8
CD		 10112004-06-25 Chris Demetriou <cgd@broadcom.com>
1012
1013 * configure.in (sim_m16_machine): Include mipsIII.
1014 * configure: Regenerate.
1015
1a27f959
CD		 10162004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
1017
72f4393d 1018 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
1a27f959
CD		 1019 from COP0_BADVADDR.
1020 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
1021
5dbb7b5a
CD		 10222004-04-10 Chris Demetriou <cgd@broadcom.com>
1023
1024 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
1025
14234056
CD		 10262004-04-09 Chris Demetriou <cgd@broadcom.com>
1027
1028 * mips.igen (check_fmt): Remove.
1029 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
1030 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
1031 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
1032 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
1033 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
1034 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
1035 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1036 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
1037 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
1038 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
1039
c6f9085c
CD		 10402004-04-09 Chris Demetriou <cgd@broadcom.com>
1041
1042 * sb1.igen (check_sbx): New function.
1043 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
1044
11d66e66 10452004-03-29 Chris Demetriou <cgd@broadcom.com>
0e1b7197
RS		 1046 Richard Sandiford <rsandifo@redhat.com>
1047
1048 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
1049 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
1050 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
1051 separate implementations for mipsIV and mipsV. Use new macros to
1052 determine whether the restrictions apply.
1053
b3208fb8
CD		 10542004-01-19 Chris Demetriou <cgd@broadcom.com>
1055
1056 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
1057 (check_mult_hilo): Improve comments.
1058 (check_div_hilo): Likewise. Also, fork off a new version
1059 to handle mips32/mips64 (since there are no hazards to check
1060 in MIPS32/MIPS64).
1061
9a1d84fb
CD		 10622003-06-17 Richard Sandiford <rsandifo@redhat.com>
1063
1064 * mips.igen (do_dmultx): Fix check for negative operands.
1065
ae451ac6
ILT		 10662003-05-16 Ian Lance Taylor <ian@airs.com>
1067
1068 * Makefile.in (SHELL): Make sure this is defined.
1069 (various): Use $(SHELL) whenever we invoke move-if-change.
1070
dd69d292
CD		 10712003-05-03 Chris Demetriou <cgd@broadcom.com>
1072
1073 * cp1.c: Tweak attribution slightly.
1074 * cp1.h: Likewise.
1075 * mdmx.c: Likewise.
1076 * mdmx.igen: Likewise.
1077 * mips3d.igen: Likewise.
1078 * sb1.igen: Likewise.
1079
bcd0068e
CD		 10802003-04-15 Richard Sandiford <rsandifo@redhat.com>
1081
1082 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
1083 unsigned operands.
1084
6b4a8935
AC		 10852003-02-27 Andrew Cagney <cagney@redhat.com>
1086
601da316
AC		 1087 * interp.c (sim_open): Rename _bfd to bfd.
1088 (sim_create_inferior): Ditto.
6b4a8935 1089
d29e330f
CD		 10902003-01-14 Chris Demetriou <cgd@broadcom.com>
1091
1092 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
1093
a2353a08
CD		 10942003-01-14 Chris Demetriou <cgd@broadcom.com>
1095
1096 * mips.igen (EI, DI): Remove.
1097
80551777
CD		 10982003-01-05 Richard Sandiford <rsandifo@redhat.com>
1099
1100 * Makefile.in (tmp-run-multi): Fix mips16 filter.
1101
4c54fc26
CD		 11022003-01-04 Richard Sandiford <rsandifo@redhat.com>
1103 Andrew Cagney <ac131313@redhat.com>
1104 Gavin Romig-Koch <gavin@redhat.com>
1105 Graydon Hoare <graydon@redhat.com>
1106 Aldy Hernandez <aldyh@redhat.com>
1107 Dave Brolley <brolley@redhat.com>
1108 Chris Demetriou <cgd@broadcom.com>
1109
1110 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
1111 (sim_mach_default): New variable.
1112 (mips64vr-*-*, mips64vrel-*-*): New configurations.
1113 Add a new simulator generator, MULTI.
1114 * configure: Regenerate.
1115 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
1116 (multi-run.o): New dependency.
1117 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
1118 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
1119 (tmp-multi): Combine them.
1120 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
1121 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
1122 (distclean-extra): New rule.
1123 * sim-main.h: Include bfd.h.
1124 (MIPS_MACH): New macro.
1125 * mips.igen (vr4120, vr5400, vr5500): New models.
1126 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
1127 * vr.igen: Replace with new version.
1128
e6c674b8
CD		 11292003-01-04 Chris Demetriou <cgd@broadcom.com>
1130
1131 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
1132 * configure: Regenerate.
1133
28f50ac8
CD		 11342002-12-31 Chris Demetriou <cgd@broadcom.com>
1135
1136 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
1137 * mips.igen: Remove all invocations of check_branch_bug and
1138 mark_branch_bug.
1139
5071ffe6
CD		 11402002-12-16 Chris Demetriou <cgd@broadcom.com>
1141
72f4393d 1142 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
5071ffe6 1143
06e7837e
CD		 11442002-07-30 Chris Demetriou <cgd@broadcom.com>
1145
1146 * mips.igen (do_load_double, do_store_double): New functions.
1147 (LDC1, SDC1): Rename to...
1148 (LDC1b, SDC1b): respectively.
1149 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
1150
2265c243
MS		 11512002-07-29 Michael Snyder <msnyder@redhat.com>
1152
1153 * cp1.c (fp_recip2): Modify initialization expression so that
1154 GCC will recognize it as constant.
1155
a2f8b4f3
CD		 11562002-06-18 Chris Demetriou <cgd@broadcom.com>
1157
1158 * mdmx.c (SD_): Delete.
1159 (Unpredictable): Re-define, for now, to directly invoke
1160 unpredictable_action().
1161 (mdmx_acc_op): Fix error in .ob immediate handling.
1162
b4b6c939
AC		 11632002-06-18 Andrew Cagney <cagney@redhat.com>
1164
1165 * interp.c (sim_firmware_command): Initialize `address'.
1166
c8cca39f
AC		 11672002-06-16 Andrew Cagney <ac131313@redhat.com>
1168
1169 * configure: Regenerated to track ../common/aclocal.m4 changes.
1170
e7e81181 11712002-06-14 Chris Demetriou <cgd@broadcom.com>
72f4393d 1172 Ed Satterthwaite <ehs@broadcom.com>
e7e81181
CD		 1173
1174 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
1175 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
1176 * mips.igen: Include mips3d.igen.
1177 (mips3d): New model name for MIPS-3D ASE instructions.
1178 (CVT.W.fmt): Don't use this instruction for word (source) format
72f4393d 1179 instructions.
e7e81181
CD		 1180 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
1181 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
1182 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
1183 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
1184 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
1185 (RSquareRoot1, RSquareRoot2): New macros.
1186 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
1187 (fp_rsqrt2): New functions.
1188 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
1189 * configure: Regenerate.
1190
3a2b820e 11912002-06-13 Chris Demetriou <cgd@broadcom.com>
72f4393d 1192 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 1193
1194 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
1195 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
1196 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
1197 (convert): Note that this function is not used for paired-single
1198 format conversions.
1199 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
1200 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
1201 (check_fmt_p): Enable paired-single support.
1202 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
1203 (PUU.PS): New instructions.
1204 (CVT.S.fmt): Don't use this instruction for paired-single format
1205 destinations.
1206 * sim-main.h (FP_formats): New value 'fmt_ps.'
1207 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
1208 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
1209
d18ea9c2
CD		 12102002-06-12 Chris Demetriou <cgd@broadcom.com>
1211
1212 * mips.igen: Fix formatting of function calls in
1213 many FP operations.
1214
95fd5cee
CD		 12152002-06-12 Chris Demetriou <cgd@broadcom.com>
1216
1217 * mips.igen (MOVN, MOVZ): Trace result.
1218 (TNEI): Print "tnei" as the opcode name in traces.
1219 (CEIL.W): Add disassembly string for traces.
1220 (RSQRT.fmt): Make location of disassembly string consistent
1221 with other instructions.
1222
4f0d55ae
CD		 12232002-06-12 Chris Demetriou <cgd@broadcom.com>
1224
1225 * mips.igen (X): Delete unused function.
1226
3c25f8c7
AC		 12272002-06-08 Andrew Cagney <cagney@redhat.com>
1228
1229 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
1230
f3c08b7e 12312002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1232 Ed Satterthwaite <ehs@broadcom.com>
f3c08b7e
CD		 1233
1234 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
1235 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
1236 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
1237 (fp_nmsub): New prototypes.
1238 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
1239 (NegMultiplySub): New defines.
1240 * mips.igen (RSQRT.fmt): Use RSquareRoot().
1241 (MADD.D, MADD.S): Replace with...
1242 (MADD.fmt): New instruction.
1243 (MSUB.D, MSUB.S): Replace with...
1244 (MSUB.fmt): New instruction.
1245 (NMADD.D, NMADD.S): Replace with...
1246 (NMADD.fmt): New instruction.
1247 (NMSUB.D, MSUB.S): Replace with...
1248 (NMSUB.fmt): New instruction.
1249
52714ff9 12502002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1251 Ed Satterthwaite <ehs@broadcom.com>
52714ff9
CD		 1252
1253 * cp1.c: Fix more comment spelling and formatting.
1254 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
1255 (denorm_mode): New function.
1256 (fpu_unary, fpu_binary): Round results after operation, collect
1257 status from rounding operations, and update the FCSR.
1258 (convert): Collect status from integer conversions and rounding
1259 operations, and update the FCSR. Adjust NaN values that result
1260 from conversions. Convert to use sim_io_eprintf rather than
1261 fprintf, and remove some debugging code.
1262 * cp1.h (fenr_FS): New define.
1263
577d8c4b
CD		 12642002-06-07 Chris Demetriou <cgd@broadcom.com>
1265
1266 * cp1.c (convert): Remove unusable debugging code, and move MIPS
1267 rounding mode to sim FP rounding mode flag conversion code into...
1268 (rounding_mode): New function.
1269
196496ed
CD		 12702002-06-07 Chris Demetriou <cgd@broadcom.com>
1271
1272 * cp1.c: Clean up formatting of a few comments.
1273 (value_fpr): Reformat switch statement.
1274
cfe9ea23 12752002-06-06 Chris Demetriou <cgd@broadcom.com>
72f4393d 1276 Ed Satterthwaite <ehs@broadcom.com>
cfe9ea23
CD		 1277
1278 * cp1.h: New file.
1279 * sim-main.h: Include cp1.h.
1280 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
1281 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
1282 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
1283 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
1284 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
1285 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
1286 * cp1.c: Don't include sim-fpu.h; already included by
1287 sim-main.h. Clean up formatting of some comments.
1288 (NaN, Equal, Less): Remove.
1289 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
1290 (fp_cmp): New functions.
1291 * mips.igen (do_c_cond_fmt): Remove.
1292 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
1293 Compare. Add result tracing.
1294 (CxC1): Remove, replace with...
1295 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
1296 (DMxC1): Remove, replace with...
1297 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
72f4393d
L		 1298 (MxC1): Remove, replace with...
1299 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
cfe9ea23 1300
ee7254b0
CD		 13012002-06-04 Chris Demetriou <cgd@broadcom.com>
1302
1303 * sim-main.h (FGRIDX): Remove, replace all uses with...
1304 (FGR_BASE): New macro.
1305 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
1306 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
1307 (NR_FGR, FGR): Likewise.
1308 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
1309 * mips.igen: Likewise.
1310
d3eb724f
CD		 13112002-06-04 Chris Demetriou <cgd@broadcom.com>
1312
1313 * cp1.c: Add an FSF Copyright notice to this file.
1314
ba46ddd0 13152002-06-04 Chris Demetriou <cgd@broadcom.com>
72f4393d 1316 Ed Satterthwaite <ehs@broadcom.com>
ba46ddd0
CD		 1317
1318 * cp1.c (Infinity): Remove.
1319 * sim-main.h (Infinity): Likewise.
1320
1321 * cp1.c (fp_unary, fp_binary): New functions.
1322 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
1323 (fp_sqrt): New functions, implemented in terms of the above.
1324 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1325 (Recip, SquareRoot): Remove (replaced by functions above).
1326 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
1327 (fp_recip, fp_sqrt): New prototypes.
1328 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1329 (Recip, SquareRoot): Replace prototypes with #defines which
1330 invoke the functions above.
72f4393d 1331
18d8a52d
CD		 13322002-06-03 Chris Demetriou <cgd@broadcom.com>
1333
1334 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
1335 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
1336 file, remove PARAMS from prototypes.
1337 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
1338 simulator state arguments.
1339 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
1340 pass simulator state arguments.
1341 * cp1.c (SD): Redefine as CPU_STATE(cpu).
1342 (store_fpr, convert): Remove 'sd' argument.
1343 (value_fpr): Likewise. Convert to use 'SD' instead.
1344
0f154cbd
CD		 13452002-06-03 Chris Demetriou <cgd@broadcom.com>
1346
1347 * cp1.c (Min, Max): Remove #if 0'd functions.
1348 * sim-main.h (Min, Max): Remove.
1349
e80fc152
CD		 13502002-06-03 Chris Demetriou <cgd@broadcom.com>
1351
1352 * cp1.c: fix formatting of switch case and default labels.
1353 * interp.c: Likewise.
1354 * sim-main.c: Likewise.
1355
bad673a9
CD		 13562002-06-03 Chris Demetriou <cgd@broadcom.com>
1357
1358 * cp1.c: Clean up comments which describe FP formats.
1359 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
1360
7cbea089 13612002-06-03 Chris Demetriou <cgd@broadcom.com>
72f4393d 1362 Ed Satterthwaite <ehs@broadcom.com>
7cbea089
CD		 1363
1364 * configure.in (mipsisa64sb1*-*-*): New target for supporting
1365 Broadcom SiByte SB-1 processor configurations.
1366 * configure: Regenerate.
1367 * sb1.igen: New file.
1368 * mips.igen: Include sb1.igen.
1369 (sb1): New model.
1370 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
1371 * mdmx.igen: Add "sb1" model to all appropriate functions and
1372 instructions.
1373 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
1374 (ob_func, ob_acc): Reference the above.
1375 (qh_acc): Adjust to keep the same size as ob_acc.
1376 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
1377 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
1378
909daa82
CD		 13792002-06-03 Chris Demetriou <cgd@broadcom.com>
1380
1381 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
1382
f4f1b9f1 13832002-06-02 Chris Demetriou <cgd@broadcom.com>
72f4393d 1384 Ed Satterthwaite <ehs@broadcom.com>
f4f1b9f1
CD		 1385
1386 * mips.igen (mdmx): New (pseudo-)model.
1387 * mdmx.c, mdmx.igen: New files.
1388 * Makefile.in (SIM_OBJS): Add mdmx.o.
1389 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
1390 New typedefs.
1391 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
1392 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
1393 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
1394 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
1395 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
1396 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
1397 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
1398 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
1399 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
1400 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
1401 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
1402 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
1403 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
1404 (qh_fmtsel): New macros.
1405 (_sim_cpu): New member "acc".
1406 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
1407 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
1408
5accf1ff
CD		 14092002-05-01 Chris Demetriou <cgd@broadcom.com>
1410
1411 * interp.c: Use 'deprecated' rather than 'depreciated.'
1412 * sim-main.h: Likewise.
1413
402586aa
CD		 14142002-05-01 Chris Demetriou <cgd@broadcom.com>
1415
1416 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
1417 which wouldn't compile anyway.
1418 * sim-main.h (unpredictable_action): New function prototype.
1419 (Unpredictable): Define to call igen function unpredictable().
1420 (NotWordValue): New macro to call igen function not_word_value().
1421 (UndefinedResult): Remove.
1422 * interp.c (undefined_result): Remove.
1423 (unpredictable_action): New function.
1424 * mips.igen (not_word_value, unpredictable): New functions.
1425 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
1426 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
1427 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
1428 NotWordValue() to check for unpredictable inputs, then
1429 Unpredictable() to handle them.
1430
c9b9995a
CD		 14312002-02-24 Chris Demetriou <cgd@broadcom.com>
1432
1433 * mips.igen: Fix formatting of calls to Unpredictable().
1434
e1015982
AC		 14352002-04-20 Andrew Cagney <ac131313@redhat.com>
1436
1437 * interp.c (sim_open): Revert previous change.
1438
b882a66b
AO		 14392002-04-18 Alexandre Oliva <aoliva@redhat.com>
1440
1441 * interp.c (sim_open): Disable chunk of code that wrote code in
1442 vector table entries.
1443
c429b7dd
CD		 14442002-03-19 Chris Demetriou <cgd@broadcom.com>
1445
1446 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
1447 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
1448 unused definitions.
1449
37d146fa
CD		 14502002-03-19 Chris Demetriou <cgd@broadcom.com>
1451
1452 * cp1.c: Fix many formatting issues.
1453
07892c0b
CD		 14542002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1455
1456 * cp1.c (fpu_format_name): New function to replace...
1457 (DOFMT): This. Delete, and update all callers.
1458 (fpu_rounding_mode_name): New function to replace...
1459 (RMMODE): This. Delete, and update all callers.
1460
487f79b7
CD		 14612002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1462
1463 * interp.c: Move FPU support routines from here to...
1464 * cp1.c: Here. New file.
1465 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
1466 (cp1.o): New target.
1467
1e799e28
CD		 14682002-03-12 Chris Demetriou <cgd@broadcom.com>
1469
1470 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
1471 * mips.igen (mips32, mips64): New models, add to all instructions
1472 and functions as appropriate.
1473 (loadstore_ea, check_u64): New variant for model mips64.
1474 (check_fmt_p): New variant for models mipsV and mips64, remove
1475 mipsV model marking fro other variant.
1476 (SLL) Rename to...
1477 (SLLa) this.
1478 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
1479 for mips32 and mips64.
1480 (DCLO, DCLZ): New instructions for mips64.
1481
82f728db
CD		 14822002-03-07 Chris Demetriou <cgd@broadcom.com>
1483
1484 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
1485 immediate or code as a hex value with the "%#lx" format.
1486 (ANDI): Likewise, and fix printed instruction name.
1487
b96e7ef1
CD		 14882002-03-05 Chris Demetriou <cgd@broadcom.com>
1489
1490 * sim-main.h (UndefinedResult, Unpredictable): New macros
1491 which currently do nothing.
1492
d35d4f70
CD		 14932002-03-05 Chris Demetriou <cgd@broadcom.com>
1494
1495 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
1496 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
1497 (status_CU3): New definitions.
1498
1499 * sim-main.h (ExceptionCause): Add new values for MIPS32
1500 and MIPS64: MDMX, MCheck, CacheErr. Update comments
1501 for DebugBreakPoint and NMIReset to note their status in
1502 MIPS32 and MIPS64.
1503 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
1504 (SignalExceptionCacheErr): New exception macros.
1505
3ad6f714
CD		 15062002-03-05 Chris Demetriou <cgd@broadcom.com>
1507
1508 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
1509 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
1510 is always enabled.
1511 (SignalExceptionCoProcessorUnusable): Take as argument the
1512 unusable coprocessor number.
1513
86b77b47
CD		 15142002-03-05 Chris Demetriou <cgd@broadcom.com>
1515
1516 * mips.igen: Fix formatting of all SignalException calls.
1517
97a88e93 15182002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 1519
1520 * sim-main.h (SIGNEXTEND): Remove.
1521
97a88e93 15222002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 1523
1524 * mips.igen: Remove gencode comment from top of file, fix
1525 spelling in another comment.
1526
97a88e93 15272002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 1528
1529 * mips.igen (check_fmt, check_fmt_p): New functions to check
1530 whether specific floating point formats are usable.
1531 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1532 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
1533 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
1534 Use the new functions.
1535 (do_c_cond_fmt): Remove format checks...
1536 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
1537
97a88e93 15382002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 1539
1540 * mips.igen: Fix formatting of check_fpu calls.
1541
41774c9d
CD		 15422002-03-03 Chris Demetriou <cgd@broadcom.com>
1543
1544 * mips.igen (FLOOR.L.fmt): Store correct destination register.
1545
4a0bd876
CD		 15462002-03-03 Chris Demetriou <cgd@broadcom.com>
1547
1548 * mips.igen: Remove whitespace at end of lines.
1549
09297648
CD		 15502002-03-02 Chris Demetriou <cgd@broadcom.com>
1551
1552 * mips.igen (loadstore_ea): New function to do effective
1553 address calculations.
1554 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
1555 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
1556 CACHE): Use loadstore_ea to do effective address computations.
1557
043b7057
CD		 15582002-03-02 Chris Demetriou <cgd@broadcom.com>
1559
1560 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
1561 * mips.igen (LL, CxC1, MxC1): Likewise.
1562
c1e8ada4
CD		 15632002-03-02 Chris Demetriou <cgd@broadcom.com>
1564
1565 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
1566 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
1567 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
1568 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
1569 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
1570 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
1571 Don't split opcode fields by hand, use the opcode field values
1572 provided by igen.
1573
3e1dca16
CD		 15742002-03-01 Chris Demetriou <cgd@broadcom.com>
1575
1576 * mips.igen (do_divu): Fix spacing.
1577
1578 * mips.igen (do_dsllv): Move to be right before DSLLV,
1579 to match the rest of the do_<shift> functions.
1580
fff8d27d
CD		 15812002-03-01 Chris Demetriou <cgd@broadcom.com>
1582
1583 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
1584 DSRL32, do_dsrlv): Trace inputs and results.
1585
0d3e762b
CD		 15862002-03-01 Chris Demetriou <cgd@broadcom.com>
1587
1588 * mips.igen (CACHE): Provide instruction-printing string.
1589
1590 * interp.c (signal_exception): Comment tokens after #endif.
1591
eb5fcf93
CD		 15922002-02-28 Chris Demetriou <cgd@broadcom.com>
1593
1594 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
72f4393d
L		 1595 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
1596 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
1597 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
1598 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
1599 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
1600 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
eb5fcf93
CD		 1601 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
1602
bb22bd7d
CD		 16032002-02-28 Chris Demetriou <cgd@broadcom.com>
1604
1605 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
1606 instruction-printing string.
1607 (LWU): Use '64' as the filter flag.
1608
91a177cf
CD		 16092002-02-28 Chris Demetriou <cgd@broadcom.com>
1610
1611 * mips.igen (SDXC1): Fix instruction-printing string.
1612
387f484a
CD		 16132002-02-28 Chris Demetriou <cgd@broadcom.com>
1614
1615 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
1616 filter flags "32,f".
1617
3d81f391
CD		 16182002-02-27 Chris Demetriou <cgd@broadcom.com>
1619
1620 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1621 as the filter flag.
1622
af5107af
CD		 16232002-02-27 Chris Demetriou <cgd@broadcom.com>
1624
1625 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1626 add a comma) so that it more closely match the MIPS ISA
1627 documentation opcode partitioning.
1628 (PREF): Put useful names on opcode fields, and include
1629 instruction-printing string.
1630
ca971540
CD		 16312002-02-27 Chris Demetriou <cgd@broadcom.com>
1632
1633 * mips.igen (check_u64): New function which in the future will
1634 check whether 64-bit instructions are usable and signal an
1635 exception if not. Currently a no-op.
1636 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1637 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1638 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1639 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1640
1641 * mips.igen (check_fpu): New function which in the future will
1642 check whether FPU instructions are usable and signal an exception
1643 if not. Currently a no-op.
1644 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1645 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1646 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1647 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1648 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1649 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1650 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1651 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1652
1c47a468
CD		 16532002-02-27 Chris Demetriou <cgd@broadcom.com>
1654
1655 * mips.igen (do_load_left, do_load_right): Move to be immediately
1656 following do_load.
1657 (do_store_left, do_store_right): Move to be immediately following
1658 do_store.
1659
603a98e7
CD		 16602002-02-27 Chris Demetriou <cgd@broadcom.com>
1661
1662 * mips.igen (mipsV): New model name. Also, add it to
1663 all instructions and functions where it is appropriate.
1664
c5d00cc7
CD		 16652002-02-18 Chris Demetriou <cgd@broadcom.com>
1666
1667 * mips.igen: For all functions and instructions, list model
1668 names that support that instruction one per line.
1669
074e9cb8
CD		 16702002-02-11 Chris Demetriou <cgd@broadcom.com>
1671
1672 * mips.igen: Add some additional comments about supported
1673 models, and about which instructions go where.
1674 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1675 order as is used in the rest of the file.
1676
9805e229
CD		 16772002-02-11 Chris Demetriou <cgd@broadcom.com>
1678
1679 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1680 indicating that ALU32_END or ALU64_END are there to check
1681 for overflow.
1682 (DADD): Likewise, but also remove previous comment about
1683 overflow checking.
1684
f701dad2
CD		 16852002-02-10 Chris Demetriou <cgd@broadcom.com>
1686
1687 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1688 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1689 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1690 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1691 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1692 fields (i.e., add and move commas) so that they more closely
1693 match the MIPS ISA documentation opcode partitioning.
1694
16952002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098 1696
72f4393d
L		 1697 * mips.igen (ADDI): Print immediate value.
1698 (BREAK): Print code.
1699 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1700 (SLL): Print "nop" specially, and don't run the code
1701 that does the shift for the "nop" case.
20ae0098 1702
9e52972e
FF		 17032001-11-17 Fred Fish <fnf@redhat.com>
1704
1705 * sim-main.h (float_operation): Move enum declaration outside
1706 of _sim_cpu struct declaration.
1707
c0efbca4
JB		 17082001-04-12 Jim Blandy <jimb@redhat.com>
1709
1710 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1711 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1712 set of the FCSR.
1713 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1714 PENDING_FILL, and you can get the intended effect gracefully by
1715 calling PENDING_SCHED directly.
1716
fb891446
BE		 17172001-02-23 Ben Elliston <bje@redhat.com>
1718
1719 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1720 already defined elsewhere.
1721
8030f857
BE		 17222001-02-19 Ben Elliston <bje@redhat.com>
1723
1724 * sim-main.h (sim_monitor): Return an int.
1725 * interp.c (sim_monitor): Add return values.
1726 (signal_exception): Handle error conditions from sim_monitor.
1727
56b48a7a
CD		 17282001-02-08 Ben Elliston <bje@redhat.com>
1729
1730 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1731 (store_memory): Likewise, pass cia to sim_core_write*.
1732
d3ee60d9
FCE		 17332000-10-19 Frank Ch. Eigler <fche@redhat.com>
1734
1735 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1736 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1737
071da002
AC		 1738Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1739
1740 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1741 * Makefile.in: Don't delete *.igen when cleaning directory.
1742
a28c02cd
AC		 1743Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1744
1745 * m16.igen (break): Call SignalException not sim_engine_halt.
1746
80ee11fa
AC		 1747Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1748
1749 From Jason Eckhardt:
1750 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1751
673388c0
AC		 1752Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1753
1754 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1755
4c0deff4
NC		 17562000-05-24 Michael Hayes <mhayes@cygnus.com>
1757
1758 * mips.igen (do_dmultx): Fix typo.
1759
eb2d80b4
AC		 1760Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1761
1762 * configure: Regenerated to track ../common/aclocal.m4 changes.
1763
dd37a34b
AC		 1764Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1765
1766 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1767
4c0deff4
NC		 17682000-04-12 Frank Ch. Eigler <fche@redhat.com>
1769
1770 * sim-main.h (GPR_CLEAR): Define macro.
1771
e30db738
AC		 1772Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1773
1774 * interp.c (decode_coproc): Output long using %lx and not %s.
1775
cb7450ea
FCE		 17762000-03-21 Frank Ch. Eigler <fche@redhat.com>
1777
1778 * interp.c (sim_open): Sort & extend dummy memory regions for
1779 --board=jmr3904 for eCos.
1780
a3027dd7
FCE		 17812000-03-02 Frank Ch. Eigler <fche@redhat.com>
1782
1783 * configure: Regenerated.
1784
1785Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1786
1787 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1788 calls, conditional on the simulator being in verbose mode.
1789
dfcd3bfb
JM		 1790Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1791
1792 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1793 cache don't get ReservedInstruction traps.
1794
c2d11a7d
JM		 17951999-11-29 Mark Salter <msalter@cygnus.com>
1796
1797 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1798 to clear status bits in sdisr register. This is how the hardware works.
1799
1800 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1801 being used by cygmon.
1802
4ce44c66
JM		 18031999-11-11 Andrew Haley <aph@cygnus.com>
1804
1805 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1806 instructions.
1807
cff3e48b
JM		 1808Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1809
1810 * mips.igen (MULT): Correct previous mis-applied patch.
1811
d4f3574e
SS		 1812Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1813
1814 * mips.igen (delayslot32): Handle sequence like
1815 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1816 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1817 (MULT): Actually pass the third register...
1818
18191999-09-03 Mark Salter <msalter@cygnus.com>
1820
1821 * interp.c (sim_open): Added more memory aliases for additional
1822 hardware being touched by cygmon on jmr3904 board.
1823
1824Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1825
1826 * configure: Regenerated to track ../common/aclocal.m4 changes.
1827
a0b3c4fd
JM		 1828Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1829
1830 * interp.c (sim_store_register): Handle case where client - GDB -
1831 specifies that a 4 byte register is 8 bytes in size.
1832 (sim_fetch_register): Ditto.
72f4393d 1833
adf40b2e
JM		 18341999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1835
1836 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1837 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1838 (idt_monitor_base): Base address for IDT monitor traps.
1839 (pmon_monitor_base): Ditto for PMON.
1840 (lsipmon_monitor_base): Ditto for LSI PMON.
1841 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1842 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1843 (sim_firmware_command): New function.
1844 (mips_option_handler): Call it for OPTION_FIRMWARE.
1845 (sim_open): Allocate memory for idt_monitor region. If "--board"
1846 option was given, add no monitor by default. Add BREAK hooks only if
1847 monitors are also there.
72f4393d 1848
43e526b9
JM		 1849Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1850
1851 * interp.c (sim_monitor): Flush output before reading input.
1852
1853Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1854
1855 * tconfig.in (SIM_HANDLES_LMA): Always define.
1856
1857Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1858
1859 From Mark Salter <msalter@cygnus.com>:
1860 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1861 (sim_open): Add setup for BSP board.
1862
9846de1b
JM		 1863Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1864
1865 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1866 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1867 them as unimplemented.
1868
cd0fc7c3
SS		 18691999-05-08 Felix Lee <flee@cygnus.com>
1870
1871 * configure: Regenerated to track ../common/aclocal.m4 changes.
72f4393d 1872
7a292a7a
SS		 18731999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1874
1875 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1876
1877Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1878
1879 * configure.in: Any mips64vr5*-*-* target should have
1880 -DTARGET_ENABLE_FR=1.
1881 (default_endian): Any mips64vr*el-*-* target should default to
1882 LITTLE_ENDIAN.
1883 * configure: Re-generate.
1884
18851999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1886
1887 * mips.igen (ldl): Extend from _16_, not 32.
1888
1889Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1890
1891 * interp.c (sim_store_register): Force registers written to by GDB
1892 into an un-interpreted state.
1893
c906108c
SS		 18941999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1895
1896 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1897 CPU, start periodic background I/O polls.
72f4393d 1898 (tx3904sio_poll): New function: periodic I/O poller.
c906108c
SS		 1899
19001998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1901
1902 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
72f4393d 1903
c906108c
SS		 1904Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1905
1906 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1907 case statement.
1908
19091998-12-29 Frank Ch. Eigler <fche@cygnus.com>
72f4393d
L		 1910
1911 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
c906108c
SS		 1912 (load_word): Call SIM_CORE_SIGNAL hook on error.
1913 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1914 starting. For exception dispatching, pass PC instead of NULL_CIA.
1915 (decode_coproc): Use COP0_BADVADDR to store faulting address.
72f4393d 1916 * sim-main.h (COP0_BADVADDR): Define.
c906108c
SS		 1917 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1918 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
72f4393d 1919 (_sim_cpu): Add exc_* fields to store register value snapshots.
c906108c
SS		 1920 * mips.igen (*): Replace memory-related SignalException* calls
1921 with references to SIM_CORE_SIGNAL hook.
72f4393d 1922
c906108c
SS		 1923 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1924 fix.
1925 * sim-main.c (*): Minor warning cleanups.
72f4393d 1926
c906108c
SS		 19271998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1928
1929 * m16.igen (DADDIU5): Correct type-o.
1930
1931Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1932
1933 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1934 variables.
1935
1936Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1937
1938 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1939 to include path.
1940 (interp.o): Add dependency on itable.h
1941 (oengine.c, gencode): Delete remaining references.
1942 (BUILT_SRC_FROM_GEN): Clean up.
72f4393d 1943
c906108c 19441998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
72f4393d 1945
c906108c
SS		 1946 * vr4run.c: New.
1947 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1948 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1949 tmp-run-hack) : New.
1950 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
72f4393d 1951 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
c906108c
SS		 1952 Drop the "64" qualifier to get the HACK generator working.
1953 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1954 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1955 qualifier to get the hack generator working.
1956 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1957 (DSLL): Use do_dsll.
1958 (DSLLV): Use do_dsllv.
1959 (DSRA): Use do_dsra.
1960 (DSRL): Use do_dsrl.
1961 (DSRLV): Use do_dsrlv.
1962 (BC1): Move *vr4100 to get the HACK generator working.
72f4393d 1963 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
c906108c
SS		 1964 get the HACK generator working.
1965 (MACC) Rename to get the HACK generator working.
1966 (DMACC,MACCS,DMACCS): Add the 64.
72f4393d 1967
c906108c
SS		 19681998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1969
1970 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1971 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
72f4393d 1972
c906108c
SS		 19731998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1974
1975 * mips/interp.c (DEBUG): Cleanups.
1976
19771998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1978
1979 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1980 (tx3904sio_tickle): fflush after a stdout character output.
72f4393d 1981
c906108c
SS		 19821998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1983
1984 * interp.c (sim_close): Uninstall modules.
1985
1986Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1987
1988 * sim-main.h, interp.c (sim_monitor): Change to global
1989 function.
1990
1991Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1992
1993 * configure.in (vr4100): Only include vr4100 instructions in
1994 simulator.
1995 * configure: Re-generate.
1996 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1997
1998Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1999
2000 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
2001 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
2002 true alternative.
2003
2004 * configure.in (sim_default_gen, sim_use_gen): Replace with
2005 sim_gen.
2006 (--enable-sim-igen): Delete config option. Always using IGEN.
2007 * configure: Re-generate.
72f4393d 2008
c906108c
SS		 2009 * Makefile.in (gencode): Kill, kill, kill.
2010 * gencode.c: Ditto.
72f4393d 2011
c906108c
SS		 2012Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
2013
2014 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
2015 bit mips16 igen simulator.
2016 * configure: Re-generate.
2017
2018 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
2019 as part of vr4100 ISA.
2020 * vr.igen: Mark all instructions as 64 bit only.
2021
2022Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2023
2024 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
2025 Pacify GCC.
2026
2027Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
2028
2029 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
2030 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
2031 * configure: Re-generate.
2032
2033 * m16.igen (BREAK): Define breakpoint instruction.
2034 (JALX32): Mark instruction as mips16 and not r3900.
2035 * mips.igen (C.cond.fmt): Fix typo in instruction format.
2036
2037 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
2038
2039Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
2040
2041 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
2042 insn as a debug breakpoint.
2043
2044 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
2045 pending.slot_size.
2046 (PENDING_SCHED): Clean up trace statement.
2047 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
2048 (PENDING_FILL): Delay write by only one cycle.
2049 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
2050
2051 * sim-main.c (pending_tick): Clean up trace statements. Add trace
2052 of pending writes.
2053 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
2054 32 & 64.
2055 (pending_tick): Move incrementing of index to FOR statement.
2056 (pending_tick): Only update PENDING_OUT after a write has occured.
72f4393d 2057
c906108c
SS		 2058 * configure.in: Add explicit mips-lsi-* target. Use gencode to
2059 build simulator.
2060 * configure: Re-generate.
72f4393d 2061
c906108c
SS		 2062 * interp.c (sim_engine_run OLD): Delete explicit call to
2063 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
72f4393d 2064
c906108c
SS		 2065Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
2066
2067 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
2068 interrupt level number to match changed SignalExceptionInterrupt
2069 macro.
2070
2071Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
2072
2073 * interp.c: #include "itable.h" if WITH_IGEN.
2074 (get_insn_name): New function.
2075 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
2076 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
2077
2078Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
2079
2080 * configure: Rebuilt to inhale new common/aclocal.m4.
2081
2082Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
2083
2084 * dv-tx3904sio.c: Include sim-assert.h.
2085
2086Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
2087
2088 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
2089 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
2090 Reorganize target-specific sim-hardware checks.
2091 * configure: rebuilt.
2092 * interp.c (sim_open): For tx39 target boards, set
2093 OPERATING_ENVIRONMENT, add tx3904sio devices.
2094 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
2095 ROM executables. Install dv-sockser into sim-modules list.
72f4393d 2096
c906108c
SS		 2097 * dv-tx3904irc.c: Compiler warning clean-up.
2098 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
2099 frequent hw-trace messages.
2100
2101Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
2102
2103 * vr.igen (MulAcc): Identify as a vr4100 specific function.
2104
2105Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2106
2107 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
2108
2109 * vr.igen: New file.
2110 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
2111 * mips.igen: Define vr4100 model. Include vr.igen.
2112Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
2113
2114 * mips.igen (check_mf_hilo): Correct check.
2115
2116Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2117
2118 * sim-main.h (interrupt_event): Add prototype.
2119
2120 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
2121 register_ptr, register_value.
2122 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
2123
2124 * sim-main.h (tracefh): Make extern.
2125
2126Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
2127
2128 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
72f4393d 2129 Reduce unnecessarily high timer event frequency.
c906108c 2130 * dv-tx3904cpu.c: Ditto for interrupt event.
72f4393d 2131
c906108c
SS		 2132Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
2133
2134 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
2135 to allay warnings.
2136 (interrupt_event): Made non-static.
72f4393d 2137
c906108c
SS		 2138 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
2139 interchange of configuration values for external vs. internal
2140 clock dividers.
72f4393d 2141
c906108c
SS		 2142Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
2143
72f4393d 2144 * mips.igen (BREAK): Moved code to here for
c906108c
SS		 2145 simulator-reserved break instructions.
2146 * gencode.c (build_instruction): Ditto.
2147 * interp.c (signal_exception): Code moved from here. Non-
72f4393d 2148 reserved instructions now use exception vector, rather
c906108c
SS		 2149 than halting sim.
2150 * sim-main.h: Moved magic constants to here.
2151
2152Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
2153
2154 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
2155 register upon non-zero interrupt event level, clear upon zero
2156 event value.
2157 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
2158 by passing zero event value.
2159 (*_io_{read,write}_buffer): Endianness fixes.
2160 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
2161 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
2162
2163 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
2164 serial I/O and timer module at base address 0xFFFF0000.
72f4393d 2165
c906108c
SS		 2166Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
2167
72f4393d 2168 * mips.igen (SWC1) : Correct the handling of ReverseEndian
c906108c
SS		 2169 and BigEndianCPU.
2170
2171Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
2172
2173 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
2174 parts.
2175 * configure: Update.
2176
2177Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
2178
2179 * dv-tx3904tmr.c: New file - implements tx3904 timer.
2180 * dv-tx3904{irc,cpu}.c: Mild reformatting.
2181 * configure.in: Include tx3904tmr in hw_device list.
2182 * configure: Rebuilt.
2183 * interp.c (sim_open): Instantiate three timer instances.
2184 Fix address typo of tx3904irc instance.
2185
2186Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
2187
2188 * interp.c (signal_exception): SystemCall exception now uses
2189 the exception vector.
2190
2191Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
2192
2193 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
2194 to allay warnings.
2195
2196Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2197
2198 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
2199
2200Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
2201
2202 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
2203
2204 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
2205 sim-main.h. Declare a struct hw_descriptor instead of struct
2206 hw_device_descriptor.
2207
2208Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
2209
2210 * mips.igen (do_store_left, do_load_left): Compute nr of left and
2211 right bits and then re-align left hand bytes to correct byte
2212 lanes. Fix incorrect computation in do_store_left when loading
2213 bytes from second word.
2214
2215Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2216
2217 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
2218 * interp.c (sim_open): Only create a device tree when HW is
2219 enabled.
2220
2221 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
2222 * interp.c (signal_exception): Ditto.
2223
2224Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
2225
2226 * gencode.c: Mark BEGEZALL as LIKELY.
2227
2228Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
2229
2230 * sim-main.h (ALU32_END): Sign extend 32 bit results.
2231 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
72f4393d 2232
c906108c
SS		 2233Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
2234
2235 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
2236 modules. Recognize TX39 target with "mips*tx39" pattern.
2237 * configure: Rebuilt.
2238 * sim-main.h (*): Added many macros defining bits in
2239 TX39 control registers.
2240 (SignalInterrupt): Send actual PC instead of NULL.
2241 (SignalNMIReset): New exception type.
2242 * interp.c (board): New variable for future use to identify
2243 a particular board being simulated.
2244 (mips_option_handler,mips_options): Added "--board" option.
2245 (interrupt_event): Send actual PC.
2246 (sim_open): Make memory layout conditional on board setting.
2247 (signal_exception): Initial implementation of hardware interrupt
2248 handling. Accept another break instruction variant for simulator
2249 exit.
2250 (decode_coproc): Implement RFE instruction for TX39.
2251 (mips.igen): Decode RFE instruction as such.
2252 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
2253 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
2254 bbegin to implement memory map.
2255 * dv-tx3904cpu.c: New file.
2256 * dv-tx3904irc.c: New file.
2257
2258Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
2259
2260 * mips.igen (check_mt_hilo): Create a separate r3900 version.
2261
2262Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
2263
2264 * tx.igen (madd,maddu): Replace calls to check_op_hilo
2265 with calls to check_div_hilo.
2266
2267Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
2268
2269 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
2270 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
72f4393d 2271 Add special r3900 version of do_mult_hilo.
c906108c
SS		 2272 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
2273 with calls to check_mult_hilo.
2274 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
2275 with calls to check_div_hilo.
2276
2277Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
2278
2279 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
2280 Document a replacement.
2281
2282Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
2283
2284 * interp.c (sim_monitor): Make mon_printf work.
2285
2286Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
2287
2288 * sim-main.h (INSN_NAME): New arg `cpu'.
2289
2290Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
2291
72f4393d 2292 * configure: Regenerated to track ../common/aclocal.m4 changes.
c906108c
SS		 2293
2294Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
2295
2296 * configure: Regenerated to track ../common/aclocal.m4 changes.
2297 * config.in: Ditto.
2298
2299Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
2300
2301 * acconfig.h: New file.
2302 * configure.in: Reverted change of Apr 24; use sinclude again.
2303
2304Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
2305
2306 * configure: Regenerated to track ../common/aclocal.m4 changes.
2307 * config.in: Ditto.
2308
2309Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
2310
2311 * configure.in: Don't call sinclude.
2312
2313Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
2314
2315 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
2316
2317Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2318
2319 * mips.igen (ERET): Implement.
2320
2321 * interp.c (decode_coproc): Return sign-extended EPC.
2322
2323 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
2324
2325 * interp.c (signal_exception): Do not ignore Trap.
2326 (signal_exception): On TRAP, restart at exception address.
2327 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
2328 (signal_exception): Update.
2329 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
2330 so that TRAP instructions are caught.
2331
2332Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
2333
2334 * sim-main.h (struct hilo_access, struct hilo_history): Define,
2335 contains HI/LO access history.
2336 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
2337 (HIACCESS, LOACCESS): Delete, replace with
2338 (HIHISTORY, LOHISTORY): New macros.
2339 (CHECKHILO): Delete all, moved to mips.igen
72f4393d 2340
c906108c
SS		 2341 * gencode.c (build_instruction): Do not generate checks for
2342 correct HI/LO register usage.
2343
2344 * interp.c (old_engine_run): Delete checks for correct HI/LO
2345 register usage.
2346
2347 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
2348 check_mf_cycles): New functions.
2349 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
2350 do_divu, domultx, do_mult, do_multu): Use.
2351
2352 * tx.igen ("madd", "maddu"): Use.
72f4393d 2353
c906108c
SS		 2354Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
2355
2356 * mips.igen (DSRAV): Use function do_dsrav.
2357 (SRAV): Use new function do_srav.
2358
2359 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
2360 (B): Sign extend 11 bit immediate.
2361 (EXT-B*): Shift 16 bit immediate left by 1.
2362 (ADDIU*): Don't sign extend immediate value.
2363
2364Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2365
2366 * m16run.c (sim_engine_run): Restore CIA after handling an event.
2367
2368 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
2369 functions.
2370
2371 * mips.igen (delayslot32, nullify_next_insn): New functions.
2372 (m16.igen): Always include.
2373 (do_*): Add more tracing.
2374
2375 * m16.igen (delayslot16): Add NIA argument, could be called by a
2376 32 bit MIPS16 instruction.
72f4393d 2377
c906108c
SS		 2378 * interp.c (ifetch16): Move function from here.
2379 * sim-main.c (ifetch16): To here.
72f4393d 2380
c906108c
SS		 2381 * sim-main.c (ifetch16, ifetch32): Update to match current
2382 implementations of LH, LW.
2383 (signal_exception): Don't print out incorrect hex value of illegal
2384 instruction.
2385
2386Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2387
2388 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
2389 instruction.
2390
2391 * m16.igen: Implement MIPS16 instructions.
72f4393d 2392
c906108c
SS		 2393 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
2394 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
2395 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
2396 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
2397 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
2398 bodies of corresponding code from 32 bit insn to these. Also used
2399 by MIPS16 versions of functions.
72f4393d 2400
c906108c
SS		 2401 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
2402 (IMEM16): Drop NR argument from macro.
2403
2404Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2405
2406 * Makefile.in (SIM_OBJS): Add sim-main.o.
2407
2408 * sim-main.h (address_translation, load_memory, store_memory,
2409 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
2410 as INLINE_SIM_MAIN.
2411 (pr_addr, pr_uword64): Declare.
2412 (sim-main.c): Include when H_REVEALS_MODULE_P.
72f4393d 2413
c906108c
SS		 2414 * interp.c (address_translation, load_memory, store_memory,
2415 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
2416 from here.
2417 * sim-main.c: To here. Fix compilation problems.
72f4393d 2418
c906108c
SS		 2419 * configure.in: Enable inlining.
2420 * configure: Re-config.
2421
2422Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2423
2424 * configure: Regenerated to track ../common/aclocal.m4 changes.
2425
2426Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2427
2428 * mips.igen: Include tx.igen.
2429 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
2430 * tx.igen: New file, contains MADD and MADDU.
2431
2432 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
2433 the hardwired constant `7'.
2434 (store_memory): Ditto.
2435 (LOADDRMASK): Move definition to sim-main.h.
2436
2437 mips.igen (MTC0): Enable for r3900.
2438 (ADDU): Add trace.
2439
2440 mips.igen (do_load_byte): Delete.
2441 (do_load, do_store, do_load_left, do_load_write, do_store_left,
2442 do_store_right): New functions.
2443 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
2444
2445 configure.in: Let the tx39 use igen again.
2446 configure: Update.
72f4393d 2447
c906108c
SS		 2448Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2449
2450 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
2451 not an address sized quantity. Return zero for cache sizes.
2452
2453Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
2454
2455 * mips.igen (r3900): r3900 does not support 64 bit integer
2456 operations.
2457
2458Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
2459
2460 * configure.in (mipstx39*-*-*): Use gencode simulator rather
2461 than igen one.
2462 * configure : Rebuild.
72f4393d 2463
c906108c
SS		 2464Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
2465
2466 * configure: Regenerated to track ../common/aclocal.m4 changes.
2467
2468Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2469
2470 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
2471
2472Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
2473
2474 * configure: Regenerated to track ../common/aclocal.m4 changes.
2475 * config.in: Regenerated to track ../common/aclocal.m4 changes.
2476
2477Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2478
2479 * configure: Regenerated to track ../common/aclocal.m4 changes.
2480
2481Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
2482
2483 * interp.c (Max, Min): Comment out functions. Not yet used.
2484
2485Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
2486
2487 * configure: Regenerated to track ../common/aclocal.m4 changes.
2488
2489Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
2490
2491 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
2492 configurable settings for stand-alone simulator.
72f4393d 2493
c906108c 2494 * configure.in: Added X11 search, just in case.
72f4393d 2495
c906108c
SS		 2496 * configure: Regenerated.
2497
2498Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
2499
2500 * interp.c (sim_write, sim_read, load_memory, store_memory):
2501 Replace sim_core_*_map with read_map, write_map, exec_map resp.
2502
2503Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
2504
2505 * sim-main.h (GETFCC): Return an unsigned value.
2506
2507Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2508
2509 * mips.igen (DIV): Fix check for -1 / MIN_INT.
2510 (DADD): Result destination is RD not RT.
2511
2512Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2513
2514 * sim-main.h (HIACCESS, LOACCESS): Always define.
2515
2516 * mdmx.igen (Maxi, Mini): Rename Max, Min.
2517
2518 * interp.c (sim_info): Delete.
2519
2520Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
2521
2522 * interp.c (DECLARE_OPTION_HANDLER): Use it.
2523 (mips_option_handler): New argument `cpu'.
2524 (sim_open): Update call to sim_add_option_table.
2525
2526Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
2527
2528 * mips.igen (CxC1): Add tracing.
2529
2530Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
2531
2532 * sim-main.h (Max, Min): Declare.
2533
2534 * interp.c (Max, Min): New functions.
2535
2536 * mips.igen (BC1): Add tracing.
72f4393d 2537
c906108c 2538Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
72f4393d 2539
c906108c 2540 * interp.c Added memory map for stack in vr4100
72f4393d 2541
c906108c
SS		 2542Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
2543
2544 * interp.c (load_memory): Add missing "break"'s.
2545
2546Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2547
2548 * interp.c (sim_store_register, sim_fetch_register): Pass in
2549 length parameter. Return -1.
2550
2551Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
2552
2553 * interp.c: Added hardware init hook, fixed warnings.
2554
2555Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2556
2557 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
2558
2559Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
2560
2561 * interp.c (ifetch16): New function.
2562
2563 * sim-main.h (IMEM32): Rename IMEM.
2564 (IMEM16_IMMED): Define.
2565 (IMEM16): Define.
2566 (DELAY_SLOT): Update.
72f4393d 2567
c906108c 2568 * m16run.c (sim_engine_run): New file.
72f4393d 2569
c906108c
SS		 2570 * m16.igen: All instructions except LB.
2571 (LB): Call do_load_byte.
2572 * mips.igen (do_load_byte): New function.
2573 (LB): Call do_load_byte.
2574
2575 * mips.igen: Move spec for insn bit size and high bit from here.
2576 * Makefile.in (tmp-igen, tmp-m16): To here.
2577
2578 * m16.dc: New file, decode mips16 instructions.
2579
2580 * Makefile.in (SIM_NO_ALL): Define.
2581 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
2582
2583Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
2584
2585 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
2586 point unit to 32 bit registers.
2587 * configure: Re-generate.
2588
2589Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2590
2591 * configure.in (sim_use_gen): Make IGEN the default simulator
2592 generator for generic 32 and 64 bit mips targets.
2593 * configure: Re-generate.
2594
2595Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2596
2597 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
2598 bitsize.
2599
2600 * interp.c (sim_fetch_register, sim_store_register): Read/write
2601 FGR from correct location.
2602 (sim_open): Set size of FGR's according to
2603 WITH_TARGET_FLOATING_POINT_BITSIZE.
72f4393d 2604
c906108c
SS		 2605 * sim-main.h (FGR): Store floating point registers in a separate
2606 array.
2607
2608Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
2609
2610 * configure: Regenerated to track ../common/aclocal.m4 changes.
2611
2612Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2613
2614 * interp.c (ColdReset): Call PENDING_INVALIDATE.
2615
2616 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
2617
2618 * interp.c (pending_tick): New function. Deliver pending writes.
2619
2620 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2621 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2622 it can handle mixed sized quantites and single bits.
72f4393d 2623
c906108c
SS		 2624Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2625
2626 * interp.c (oengine.h): Do not include when building with IGEN.
2627 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2628 (sim_info): Ditto for PROCESSOR_64BIT.
2629 (sim_monitor): Replace ut_reg with unsigned_word.
2630 (*): Ditto for t_reg.
2631 (LOADDRMASK): Define.
2632 (sim_open): Remove defunct check that host FP is IEEE compliant,
2633 using software to emulate floating point.
2634 (value_fpr, ...): Always compile, was conditional on HASFPU.
2635
2636Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2637
2638 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2639 size.
2640
2641 * interp.c (SD, CPU): Define.
2642 (mips_option_handler): Set flags in each CPU.
2643 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2644 (sim_close): Do not clear STATE, deleted anyway.
2645 (sim_write, sim_read): Assume CPU zero's vm should be used for
2646 data transfers.
2647 (sim_create_inferior): Set the PC for all processors.
2648 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2649 argument.
2650 (mips16_entry): Pass correct nr of args to store_word, load_word.
2651 (ColdReset): Cold reset all cpu's.
2652 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2653 (sim_monitor, load_memory, store_memory, signal_exception): Use
2654 `CPU' instead of STATE_CPU.
2655
2656
2657 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2658 SD or CPU_.
72f4393d 2659
c906108c
SS		 2660 * sim-main.h (signal_exception): Add sim_cpu arg.
2661 (SignalException*): Pass both SD and CPU to signal_exception.
2662 * interp.c (signal_exception): Update.
72f4393d 2663
c906108c
SS		 2664 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2665 Ditto
2666 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2667 address_translation): Ditto
2668 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
72f4393d 2669
c906108c
SS		 2670Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2671
2672 * configure: Regenerated to track ../common/aclocal.m4 changes.
2673
2674Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2675
2676 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2677
72f4393d 2678 * mips.igen (model): Map processor names onto BFD name.
c906108c
SS		 2679
2680 * sim-main.h (CPU_CIA): Delete.
2681 (SET_CIA, GET_CIA): Define
2682
2683Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2684
2685 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2686 regiser.
2687
2688 * configure.in (default_endian): Configure a big-endian simulator
2689 by default.
2690 * configure: Re-generate.
72f4393d 2691
c906108c
SS		 2692Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2693
2694 * configure: Regenerated to track ../common/aclocal.m4 changes.
2695
2696Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2697
2698 * interp.c (sim_monitor): Handle Densan monitor outbyte
2699 and inbyte functions.
2700
27011997-12-29 Felix Lee <flee@cygnus.com>
2702
2703 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2704
2705Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2706
2707 * Makefile.in (tmp-igen): Arrange for $zero to always be
2708 reset to zero after every instruction.
2709
2710Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2711
2712 * configure: Regenerated to track ../common/aclocal.m4 changes.
2713 * config.in: Ditto.
2714
2715Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2716
2717 * mips.igen (MSUB): Fix to work like MADD.
2718 * gencode.c (MSUB): Similarly.
2719
2720Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2721
2722 * configure: Regenerated to track ../common/aclocal.m4 changes.
2723
2724Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2725
2726 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2727
2728Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2729
2730 * sim-main.h (sim-fpu.h): Include.
2731
2732 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2733 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2734 using host independant sim_fpu module.
2735
2736Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2737
2738 * interp.c (signal_exception): Report internal errors with SIGABRT
2739 not SIGQUIT.
2740
2741 * sim-main.h (C0_CONFIG): New register.
2742 (signal.h): No longer include.
2743
2744 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2745
2746Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2747
2748 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2749
2750Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2751
2752 * mips.igen: Tag vr5000 instructions.
2753 (ANDI): Was missing mipsIV model, fix assembler syntax.
2754 (do_c_cond_fmt): New function.
2755 (C.cond.fmt): Handle mips I-III which do not support CC field
2756 separatly.
2757 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2758 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2759 in IV3.2 spec.
2760 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2761 vr5000 which saves LO in a GPR separatly.
72f4393d 2762
c906108c
SS		 2763 * configure.in (enable-sim-igen): For vr5000, select vr5000
2764 specific instructions.
2765 * configure: Re-generate.
72f4393d 2766
c906108c
SS		 2767Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2768
2769 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2770
2771 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2772 fmt_uninterpreted_64 bit cases to switch. Convert to
2773 fmt_formatted,
2774
2775 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2776
2777 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2778 as specified in IV3.2 spec.
2779 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2780
2781Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2782
2783 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2784 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2785 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2786 PENDING_FILL versions of instructions. Simplify.
2787 (X): New function.
2788 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2789 instructions.
2790 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2791 a signed value.
2792 (MTHI, MFHI): Disable code checking HI-LO.
72f4393d 2793
c906108c
SS		 2794 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2795 global.
2796 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2797
2798Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2799
2800 * gencode.c (build_mips16_operands): Replace IPC with cia.
2801
2802 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2803 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2804 IPC to `cia'.
2805 (UndefinedResult): Replace function with macro/function
2806 combination.
2807 (sim_engine_run): Don't save PC in IPC.
2808
2809 * sim-main.h (IPC): Delete.
2810
2811
2812 * interp.c (signal_exception, store_word, load_word,
2813 address_translation, load_memory, store_memory, cache_op,
2814 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2815 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2816 current instruction address - cia - argument.
2817 (sim_read, sim_write): Call address_translation directly.
2818 (sim_engine_run): Rename variable vaddr to cia.
2819 (signal_exception): Pass cia to sim_monitor
72f4393d 2820
c906108c
SS		 2821 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2822 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2823 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2824
2825 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2826 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2827 SIM_ASSERT.
72f4393d 2828
c906108c
SS		 2829 * interp.c (signal_exception): Pass restart address to
2830 sim_engine_restart.
2831
2832 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2833 idecode.o): Add dependency.
2834
2835 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2836 Delete definitions
2837 (DELAY_SLOT): Update NIA not PC with branch address.
2838 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2839
2840 * mips.igen: Use CIA not PC in branch calculations.
2841 (illegal): Call SignalException.
2842 (BEQ, ADDIU): Fix assembler.
2843
2844Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2845
2846 * m16.igen (JALX): Was missing.
2847
2848 * configure.in (enable-sim-igen): New configuration option.
2849 * configure: Re-generate.
72f4393d 2850
c906108c
SS		 2851 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2852
2853 * interp.c (load_memory, store_memory): Delete parameter RAW.
2854 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2855 bypassing {load,store}_memory.
2856
2857 * sim-main.h (ByteSwapMem): Delete definition.
2858
2859 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2860
2861 * interp.c (sim_do_command, sim_commands): Delete mips specific
2862 commands. Handled by module sim-options.
72f4393d 2863
c906108c
SS		 2864 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2865 (WITH_MODULO_MEMORY): Define.
2866
2867 * interp.c (sim_info): Delete code printing memory size.
2868
2869 * interp.c (mips_size): Nee sim_size, delete function.
2870 (power2): Delete.
2871 (monitor, monitor_base, monitor_size): Delete global variables.
2872 (sim_open, sim_close): Delete code creating monitor and other
2873 memory regions. Use sim-memopts module, via sim_do_commandf, to
2874 manage memory regions.
2875 (load_memory, store_memory): Use sim-core for memory model.
72f4393d 2876
c906108c
SS		 2877 * interp.c (address_translation): Delete all memory map code
2878 except line forcing 32 bit addresses.
2879
2880Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2881
2882 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2883 trace options.
2884
2885 * interp.c (logfh, logfile): Delete globals.
2886 (sim_open, sim_close): Delete code opening & closing log file.
2887 (mips_option_handler): Delete -l and -n options.
2888 (OPTION mips_options): Ditto.
2889
2890 * interp.c (OPTION mips_options): Rename option trace to dinero.
2891 (mips_option_handler): Update.
2892
2893Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2894
2895 * interp.c (fetch_str): New function.
2896 (sim_monitor): Rewrite using sim_read & sim_write.
2897 (sim_open): Check magic number.
2898 (sim_open): Write monitor vectors into memory using sim_write.
2899 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2900 (sim_read, sim_write): Simplify - transfer data one byte at a
2901 time.
2902 (load_memory, store_memory): Clarify meaning of parameter RAW.
2903
2904 * sim-main.h (isHOST): Defete definition.
2905 (isTARGET): Mark as depreciated.
2906 (address_translation): Delete parameter HOST.
2907
2908 * interp.c (address_translation): Delete parameter HOST.
2909
2910Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2911
72f4393d 2912 * mips.igen:
c906108c
SS		 2913
2914 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2915 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2916
2917Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2918
2919 * mips.igen: Add model filter field to records.
2920
2921Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2922
2923 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
72f4393d 2924
c906108c
SS		 2925 interp.c (sim_engine_run): Do not compile function sim_engine_run
2926 when WITH_IGEN == 1.
2927
2928 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2929 target architecture.
2930
2931 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2932 igen. Replace with configuration variables sim_igen_flags /
2933 sim_m16_flags.
2934
2935 * m16.igen: New file. Copy mips16 insns here.
2936 * mips.igen: From here.
2937
2938Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2939
2940 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2941 to top.
2942 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2943
2944Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2945
2946 * gencode.c (build_instruction): Follow sim_write's lead in using
2947 BigEndianMem instead of !ByteSwapMem.
2948
2949Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2950
2951 * configure.in (sim_gen): Dependent on target, select type of
2952 generator. Always select old style generator.
2953
2954 configure: Re-generate.
2955
2956 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2957 targets.
2958 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2959 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2960 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2961 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2962 SIM_@sim_gen@_*, set by autoconf.
72f4393d 2963
c906108c
SS		 2964Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2965
2966 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2967
2968 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2969 CURRENT_FLOATING_POINT instead.
2970
2971 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2972 (address_translation): Raise exception InstructionFetch when
2973 translation fails and isINSTRUCTION.
72f4393d 2974
c906108c
SS		 2975 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2976 sim_engine_run): Change type of of vaddr and paddr to
2977 address_word.
2978 (address_translation, prefetch, load_memory, store_memory,
2979 cache_op): Change type of vAddr and pAddr to address_word.
2980
2981 * gencode.c (build_instruction): Change type of vaddr and paddr to
2982 address_word.
2983
2984Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2985
2986 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2987 macro to obtain result of ALU op.
2988
2989Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2990
2991 * interp.c (sim_info): Call profile_print.
2992
2993Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2994
2995 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2996
2997 * sim-main.h (WITH_PROFILE): Do not define, defined in
2998 common/sim-config.h. Use sim-profile module.
2999 (simPROFILE): Delete defintion.
3000
3001 * interp.c (PROFILE): Delete definition.
3002 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
3003 (sim_close): Delete code writing profile histogram.
3004 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
3005 Delete.
3006 (sim_engine_run): Delete code profiling the PC.
3007
3008Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3009
3010 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
3011
3012 * interp.c (sim_monitor): Make register pointers of type
3013 unsigned_word*.
3014
3015 * sim-main.h: Make registers of type unsigned_word not
3016 signed_word.
3017
3018Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3019
3020 * interp.c (sync_operation): Rename from SyncOperation, make
3021 global, add SD argument.
3022 (prefetch): Rename from Prefetch, make global, add SD argument.
3023 (decode_coproc): Make global.
3024
3025 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
3026
3027 * gencode.c (build_instruction): Generate DecodeCoproc not
3028 decode_coproc calls.
3029
3030 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
3031 (SizeFGR): Move to sim-main.h
3032 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
3033 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
3034 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
3035 sim-main.h.
3036 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
3037 FP_RM_TOMINF, GETRM): Move to sim-main.h.
3038 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
3039 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
3040 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
3041 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
72f4393d 3042
c906108c
SS		 3043 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
3044 exception.
3045 (sim-alu.h): Include.
3046 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
3047 (sim_cia): Typedef to instruction_address.
72f4393d 3048
c906108c
SS		 3049Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
3050
3051 * Makefile.in (interp.o): Rename generated file engine.c to
3052 oengine.c.
72f4393d 3053
c906108c 3054 * interp.c: Update.
72f4393d 3055
c906108c
SS		 3056Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
3057
3058 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
72f4393d 3059
c906108c
SS		 3060Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3061
3062 * gencode.c (build_instruction): For "FPSQRT", output correct
3063 number of arguments to Recip.
72f4393d 3064
c906108c
SS		 3065Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
3066
3067 * Makefile.in (interp.o): Depends on sim-main.h
3068
3069 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
3070
3071 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
3072 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
3073 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
3074 STATE, DSSTATE): Define
3075 (GPR, FGRIDX, ..): Define.
3076
3077 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
3078 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
3079 (GPR, FGRIDX, ...): Delete macros.
72f4393d 3080
c906108c 3081 * interp.c: Update names to match defines from sim-main.h
72f4393d 3082
c906108c
SS		 3083Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
3084
3085 * interp.c (sim_monitor): Add SD argument.
3086 (sim_warning): Delete. Replace calls with calls to
3087 sim_io_eprintf.
3088 (sim_error): Delete. Replace calls with sim_io_error.
3089 (open_trace, writeout32, writeout16, getnum): Add SD argument.
3090 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
3091 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
3092 argument.
3093 (mips_size): Rename from sim_size. Add SD argument.
3094
3095 * interp.c (simulator): Delete global variable.
3096 (callback): Delete global variable.
3097 (mips_option_handler, sim_open, sim_write, sim_read,
3098 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
3099 sim_size,sim_monitor): Use sim_io_* not callback->*.
3100 (sim_open): ZALLOC simulator struct.
3101 (PROFILE): Do not define.
3102
3103Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3104
3105 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
3106 support.h with corresponding code.
3107
3108 * sim-main.h (word64, uword64), support.h: Move definition to
3109 sim-main.h.
3110 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
3111
3112 * support.h: Delete
3113 * Makefile.in: Update dependencies
3114 * interp.c: Do not include.
72f4393d 3115
c906108c
SS		 3116Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3117
3118 * interp.c (address_translation, load_memory, store_memory,
3119 cache_op): Rename to from AddressTranslation et.al., make global,
3120 add SD argument
72f4393d 3121
c906108c
SS		 3122 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
3123 CacheOp): Define.
72f4393d 3124
c906108c
SS		 3125 * interp.c (SignalException): Rename to signal_exception, make
3126 global.
3127
3128 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
72f4393d 3129
c906108c
SS		 3130 * sim-main.h (SignalException, SignalExceptionInterrupt,
3131 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
3132 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
3133 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
3134 Define.
72f4393d 3135
c906108c 3136 * interp.c, support.h: Use.
72f4393d 3137
c906108c
SS		 3138Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3139
3140 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
3141 to value_fpr / store_fpr. Add SD argument.
3142 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
3143 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
3144
3145 * sim-main.h (ValueFPR, StoreFPR): Define.
72f4393d 3146
c906108c
SS		 3147Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
3148
3149 * interp.c (sim_engine_run): Check consistency between configure
3150 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
3151 and HASFPU.
3152
3153 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
72f4393d 3154 (mips_fpu): Configure WITH_FLOATING_POINT.
c906108c
SS		 3155 (mips_endian): Configure WITH_TARGET_ENDIAN.
3156 * configure: Update.
3157
3158Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3159
3160 * configure: Regenerated to track ../common/aclocal.m4 changes.
3161
3162Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
3163
3164 * configure: Regenerated.
3165
3166Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
3167
3168 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
3169
3170Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3171
3172 * gencode.c (print_igen_insn_models): Assume certain architectures
3173 include all mips* instructions.
3174 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
3175 instruction.
3176
3177 * Makefile.in (tmp.igen): Add target. Generate igen input from
3178 gencode file.
3179
3180 * gencode.c (FEATURE_IGEN): Define.
3181 (main): Add --igen option. Generate output in igen format.
3182 (process_instructions): Format output according to igen option.
3183 (print_igen_insn_format): New function.
3184 (print_igen_insn_models): New function.
3185 (process_instructions): Only issue warnings and ignore
3186 instructions when no FEATURE_IGEN.
3187
3188Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3189
3190 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
3191 MIPS targets.
3192
3193Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3194
3195 * configure: Regenerated to track ../common/aclocal.m4 changes.
3196
3197Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
3198
3199 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
3200 SIM_RESERVED_BITS): Delete, moved to common.
3201 (SIM_EXTRA_CFLAGS): Update.
72f4393d 3202
c906108c
SS		 3203Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3204
3205 * configure.in: Configure non-strict memory alignment.
3206 * configure: Regenerated to track ../common/aclocal.m4 changes.
3207
3208Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
3209
3210 * configure: Regenerated to track ../common/aclocal.m4 changes.
3211
3212Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
3213
3214 * gencode.c (SDBBP,DERET): Added (3900) insns.
3215 (RFE): Turn on for 3900.
3216 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
3217 (dsstate): Made global.
3218 (SUBTARGET_R3900): Added.
3219 (CANCELDELAYSLOT): New.
3220 (SignalException): Ignore SystemCall rather than ignore and
3221 terminate. Add DebugBreakPoint handling.
3222 (decode_coproc): New insns RFE, DERET; and new registers Debug
3223 and DEPC protected by SUBTARGET_R3900.
3224 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
3225 bits explicitly.
3226 * Makefile.in,configure.in: Add mips subtarget option.
72f4393d 3227 * configure: Update.
c906108c
SS		 3228
3229Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
3230
3231 * gencode.c: Add r3900 (tx39).
72f4393d 3232
c906108c
SS		 3233
3234Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
3235
3236 * gencode.c (build_instruction): Don't need to subtract 4 for
3237 JALR, just 2.
3238
3239Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
3240
3241 * interp.c: Correct some HASFPU problems.
3242
3243Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
3244
3245 * configure: Regenerated to track ../common/aclocal.m4 changes.
3246
3247Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3248
3249 * interp.c (mips_options): Fix samples option short form, should
3250 be `x'.
3251
3252Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
3253
3254 * interp.c (sim_info): Enable info code. Was just returning.
3255
3256Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3257
3258 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
3259 MFC0.
3260
3261Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
3262
3263 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
3264 constants.
3265 (build_instruction): Ditto for LL.
3266
3267Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
3268
3269 * configure: Regenerated to track ../common/aclocal.m4 changes.
3270
3271Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3272
3273 * configure: Regenerated to track ../common/aclocal.m4 changes.
3274 * config.in: Ditto.
3275
3276Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
3277
3278 * interp.c (sim_open): Add call to sim_analyze_program, update
3279 call to sim_config.
3280
3281Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
3282
3283 * interp.c (sim_kill): Delete.
3284 (sim_create_inferior): Add ABFD argument. Set PC from same.
3285 (sim_load): Move code initializing trap handlers from here.
3286 (sim_open): To here.
3287 (sim_load): Delete, use sim-hload.c.
3288
3289 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
3290
3291Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3292
3293 * configure: Regenerated to track ../common/aclocal.m4 changes.
3294 * config.in: Ditto.
3295
3296Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3297
3298 * interp.c (sim_open): Add ABFD argument.
3299 (sim_load): Move call to sim_config from here.
3300 (sim_open): To here. Check return status.
3301
3302Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
72f4393d 3303
c906108c
SS		 3304 * gencode.c (build_instruction): Two arg MADD should
3305 not assign result to $0.
72f4393d 3306
c906108c
SS		 3307Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
3308
3309 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
3310 * sim/mips/configure.in: Regenerate.
3311
3312Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
3313
3314 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
3315 signed8, unsigned8 et.al. types.
3316
3317 * interp.c (SUB_REG_FETCH): Handle both little and big endian
3318 hosts when selecting subreg.
3319
3320Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
3321
3322 * interp.c (sim_engine_run): Reset the ZERO register to zero
3323 regardless of FEATURE_WARN_ZERO.
3324 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
3325
3326Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
3327
3328 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
3329 (SignalException): For BreakPoints ignore any mode bits and just
3330 save the PC.
3331 (SignalException): Always set the CAUSE register.
3332
3333Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
3334
3335 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
3336 exception has been taken.
3337
3338 * interp.c: Implement the ERET and mt/f sr instructions.
3339
3340Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
3341
3342 * interp.c (SignalException): Don't bother restarting an
3343 interrupt.
3344
3345Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3346
3347 * interp.c (SignalException): Really take an interrupt.
3348 (interrupt_event): Only deliver interrupts when enabled.
3349
3350Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
3351
3352 * interp.c (sim_info): Only print info when verbose.
3353 (sim_info) Use sim_io_printf for output.
72f4393d 3354
c906108c
SS		 3355Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3356
3357 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
3358 mips architectures.
3359
3360Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3361
3362 * interp.c (sim_do_command): Check for common commands if a
3363 simulator specific command fails.
3364
3365Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
3366
3367 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
3368 and simBE when DEBUG is defined.
3369
3370Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
3371
3372 * interp.c (interrupt_event): New function. Pass exception event
3373 onto exception handler.
3374
3375 * configure.in: Check for stdlib.h.
3376 * configure: Regenerate.
3377
3378 * gencode.c (build_instruction): Add UNUSED attribute to tempS
3379 variable declaration.
3380 (build_instruction): Initialize memval1.
3381 (build_instruction): Add UNUSED attribute to byte, bigend,
3382 reverse.
3383 (build_operands): Ditto.
3384
3385 * interp.c: Fix GCC warnings.
3386 (sim_get_quit_code): Delete.
3387
3388 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
3389 * Makefile.in: Ditto.
3390 * configure: Re-generate.
72f4393d 3391
c906108c
SS		 3392 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
3393
3394Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
3395
3396 * interp.c (mips_option_handler): New function parse argumes using
3397 sim-options.
3398 (myname): Replace with STATE_MY_NAME.
3399 (sim_open): Delete check for host endianness - performed by
3400 sim_config.
3401 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
3402 (sim_open): Move much of the initialization from here.
3403 (sim_load): To here. After the image has been loaded and
3404 endianness set.
3405 (sim_open): Move ColdReset from here.
3406 (sim_create_inferior): To here.
3407 (sim_open): Make FP check less dependant on host endianness.
3408
3409 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
3410 run.
3411 * interp.c (sim_set_callbacks): Delete.
3412
3413 * interp.c (membank, membank_base, membank_size): Replace with
3414 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
3415 (sim_open): Remove call to callback->init. gdb/run do this.
3416
3417 * interp.c: Update
3418
3419 * sim-main.h (SIM_HAVE_FLATMEM): Define.
3420
3421 * interp.c (big_endian_p): Delete, replaced by
3422 current_target_byte_order.
3423
3424Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3425
3426 * interp.c (host_read_long, host_read_word, host_swap_word,
3427 host_swap_long): Delete. Using common sim-endian.
3428 (sim_fetch_register, sim_store_register): Use H2T.
3429 (pipeline_ticks): Delete. Handled by sim-events.
3430 (sim_info): Update.
3431 (sim_engine_run): Update.
3432
3433Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
3434
3435 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
3436 reason from here.
3437 (SignalException): To here. Signal using sim_engine_halt.
3438 (sim_stop_reason): Delete, moved to common.
72f4393d 3439
c906108c
SS		 3440Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
3441
3442 * interp.c (sim_open): Add callback argument.
3443 (sim_set_callbacks): Delete SIM_DESC argument.
3444 (sim_size): Ditto.
3445
3446Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3447
3448 * Makefile.in (SIM_OBJS): Add common modules.
3449
3450 * interp.c (sim_set_callbacks): Also set SD callback.
3451 (set_endianness, xfer_*, swap_*): Delete.
3452 (host_read_word, host_read_long, host_swap_word, host_swap_long):
3453 Change to functions using sim-endian macros.
3454 (control_c, sim_stop): Delete, use common version.
3455 (simulate): Convert into.
3456 (sim_engine_run): This function.
3457 (sim_resume): Delete.
72f4393d 3458
c906108c
SS		 3459 * interp.c (simulation): New variable - the simulator object.
3460 (sim_kind): Delete global - merged into simulation.
3461 (sim_load): Cleanup. Move PC assignment from here.
3462 (sim_create_inferior): To here.
3463
3464 * sim-main.h: New file.
3465 * interp.c (sim-main.h): Include.
72f4393d 3466
c906108c
SS		 3467Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
3468
3469 * configure: Regenerated to track ../common/aclocal.m4 changes.
3470
3471Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
3472
3473 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
3474
3475Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
3476
72f4393d
L		 3477 * gencode.c (build_instruction): DIV instructions: check
3478 for division by zero and integer overflow before using
c906108c
SS		 3479 host's division operation.
3480
3481Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
3482
3483 * Makefile.in (SIM_OBJS): Add sim-load.o.
3484 * interp.c: #include bfd.h.
3485 (target_byte_order): Delete.
3486 (sim_kind, myname, big_endian_p): New static locals.
3487 (sim_open): Set sim_kind, myname. Move call to set_endianness to
3488 after argument parsing. Recognize -E arg, set endianness accordingly.
3489 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
3490 load file into simulator. Set PC from bfd.
3491 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
3492 (set_endianness): Use big_endian_p instead of target_byte_order.
3493
3494Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
3495
3496 * interp.c (sim_size): Delete prototype - conflicts with
3497 definition in remote-sim.h. Correct definition.
3498
3499Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3500
3501 * configure: Regenerated to track ../common/aclocal.m4 changes.
3502 * config.in: Ditto.
3503
3504Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
3505
3506 * interp.c (sim_open): New arg `kind'.
3507
3508 * configure: Regenerated to track ../common/aclocal.m4 changes.
3509
3510Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3511
3512 * configure: Regenerated to track ../common/aclocal.m4 changes.
3513
3514Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
3515
3516 * interp.c (sim_open): Set optind to 0 before calling getopt.
3517
3518Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3519
3520 * configure: Regenerated to track ../common/aclocal.m4 changes.
3521
3522Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
3523
3524 * interp.c : Replace uses of pr_addr with pr_uword64
3525 where the bit length is always 64 independent of SIM_ADDR.
3526 (pr_uword64) : added.
3527
3528Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3529
3530 * configure: Re-generate.
3531
3532Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
3533
3534 * configure: Regenerate to track ../common/aclocal.m4 changes.
3535
3536Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
3537
3538 * interp.c (sim_open): New SIM_DESC result. Argument is now
3539 in argv form.
3540 (other sim_*): New SIM_DESC argument.
3541
3542Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
3543
3544 * interp.c: Fix printing of addresses for non-64-bit targets.
3545 (pr_addr): Add function to print address based on size.
3546
3547Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
3548
3549 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
3550
3551Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
3552
3553 * gencode.c (build_mips16_operands): Correct computation of base
3554 address for extended PC relative instruction.
3555
3556Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
3557
3558 * interp.c (mips16_entry): Add support for floating point cases.
3559 (SignalException): Pass floating point cases to mips16_entry.
3560 (ValueFPR): Don't restrict fmt_single and fmt_word to even
3561 registers.
3562 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
3563 or fmt_word.
3564 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
3565 and then set the state to fmt_uninterpreted.
3566 (COP_SW): Temporarily set the state to fmt_word while calling
3567 ValueFPR.
3568
3569Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
3570
3571 * gencode.c (build_instruction): The high order may be set in the
3572 comparison flags at any ISA level, not just ISA 4.
3573
3574Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
3575
3576 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
3577 COMMON_{PRE,POST}_CONFIG_FRAG instead.
3578 * configure.in: sinclude ../common/aclocal.m4.
3579 * configure: Regenerated.
3580
3581Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
3582
3583 * configure: Rebuild after change to aclocal.m4.
3584
3585Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
3586
3587 * configure configure.in Makefile.in: Update to new configure
3588 scheme which is more compatible with WinGDB builds.
3589 * configure.in: Improve comment on how to run autoconf.
3590 * configure: Re-run autoconf to get new ../common/aclocal.m4.
3591 * Makefile.in: Use autoconf substitution to install common
3592 makefile fragment.
3593
3594Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
3595
3596 * gencode.c (build_instruction): Use BigEndianCPU instead of
3597 ByteSwapMem.
3598
3599Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
3600
3601 * interp.c (sim_monitor): Make output to stdout visible in
3602 wingdb's I/O log window.
3603
3604Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
3605
3606 * support.h: Undo previous change to SIGTRAP
3607 and SIGQUIT values.
3608
3609Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
3610
3611 * interp.c (store_word, load_word): New static functions.
3612 (mips16_entry): New static function.
3613 (SignalException): Look for mips16 entry and exit instructions.
3614 (simulate): Use the correct index when setting fpr_state after
3615 doing a pending move.
3616
3617Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
3618
3619 * interp.c: Fix byte-swapping code throughout to work on
3620 both little- and big-endian hosts.
3621
3622Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
3623
3624 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3625 with gdb/config/i386/xm-windows.h.
3626
3627Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
3628
3629 * gencode.c (build_instruction): Work around MSVC++ code gen bug
3630 that messes up arithmetic shifts.
3631
3632Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
3633
3634 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
3635 SIGTRAP and SIGQUIT for _WIN32.
3636
3637Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3638
3639 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3640 force a 64 bit multiplication.
3641 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3642 destination register is 0, since that is the default mips16 nop
3643 instruction.
3644
3645Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3646
3647 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3648 (build_endian_shift): Don't check proc64.
3649 (build_instruction): Always set memval to uword64. Cast op2 to
3650 uword64 when shifting it left in memory instructions. Always use
3651 the same code for stores--don't special case proc64.
3652
3653 * gencode.c (build_mips16_operands): Fix base PC value for PC
3654 relative operands.
3655 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3656 jal instruction.
3657 * interp.c (simJALDELAYSLOT): Define.
3658 (JALDELAYSLOT): Define.
3659 (INDELAYSLOT, INJALDELAYSLOT): Define.
3660 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3661
3662Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3663
3664 * interp.c (sim_open): add flush_cache as a PMON routine
3665 (sim_monitor): handle flush_cache by ignoring it
3666
3667Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3668
3669 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3670 BigEndianMem.
3671 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3672 (BigEndianMem): Rename to ByteSwapMem and change sense.
3673 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3674 BigEndianMem references to !ByteSwapMem.
3675 (set_endianness): New function, with prototype.
3676 (sim_open): Call set_endianness.
3677 (sim_info): Use simBE instead of BigEndianMem.
3678 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3679 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3680 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3681 ifdefs, keeping the prototype declaration.
3682 (swap_word): Rewrite correctly.
3683 (ColdReset): Delete references to CONFIG. Delete endianness related
3684 code; moved to set_endianness.
72f4393d 3685
c906108c
SS		 3686Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3687
3688 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3689 * interp.c (CHECKHILO): Define away.
3690 (simSIGINT): New macro.
3691 (membank_size): Increase from 1MB to 2MB.
3692 (control_c): New function.
3693 (sim_resume): Rename parameter signal to signal_number. Add local
3694 variable prev. Call signal before and after simulate.
3695 (sim_stop_reason): Add simSIGINT support.
3696 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3697 functions always.
3698 (sim_warning): Delete call to SignalException. Do call printf_filtered
3699 if logfh is NULL.
3700 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3701 a call to sim_warning.
3702
3703Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3704
3705 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3706 16 bit instructions.
3707
3708Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3709
3710 Add support for mips16 (16 bit MIPS implementation):
3711 * gencode.c (inst_type): Add mips16 instruction encoding types.
3712 (GETDATASIZEINSN): Define.
3713 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3714 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3715 mtlo.
3716 (MIPS16_DECODE): New table, for mips16 instructions.
3717 (bitmap_val): New static function.
3718 (struct mips16_op): Define.
3719 (mips16_op_table): New table, for mips16 operands.
3720 (build_mips16_operands): New static function.
3721 (process_instructions): If PC is odd, decode a mips16
3722 instruction. Break out instruction handling into new
3723 build_instruction function.
3724 (build_instruction): New static function, broken out of
3725 process_instructions. Check modifiers rather than flags for SHIFT
3726 bit count and m[ft]{hi,lo} direction.
3727 (usage): Pass program name to fprintf.
3728 (main): Remove unused variable this_option_optind. Change
3729 ``*loptarg++'' to ``loptarg++''.
3730 (my_strtoul): Parenthesize && within ||.
3731 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3732 (simulate): If PC is odd, fetch a 16 bit instruction, and
3733 increment PC by 2 rather than 4.
3734 * configure.in: Add case for mips16*-*-*.
3735 * configure: Rebuild.
3736
3737Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3738
3739 * interp.c: Allow -t to enable tracing in standalone simulator.
3740 Fix garbage output in trace file and error messages.
3741
3742Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3743
3744 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3745 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3746 * configure.in: Simplify using macros in ../common/aclocal.m4.
3747 * configure: Regenerated.
3748 * tconfig.in: New file.
3749
3750Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3751
3752 * interp.c: Fix bugs in 64-bit port.
3753 Use ansi function declarations for msvc compiler.
3754 Initialize and test file pointer in trace code.
3755 Prevent duplicate definition of LAST_EMED_REGNUM.
3756
3757Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3758
3759 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3760
3761Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3762
3763 * interp.c (SignalException): Check for explicit terminating
3764 breakpoint value.
3765 * gencode.c: Pass instruction value through SignalException()
3766 calls for Trap, Breakpoint and Syscall.
3767
3768Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3769
3770 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3771 only used on those hosts that provide it.
3772 * configure.in: Add sqrt() to list of functions to be checked for.
3773 * config.in: Re-generated.
3774 * configure: Re-generated.
3775
3776Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3777
3778 * gencode.c (process_instructions): Call build_endian_shift when
3779 expanding STORE RIGHT, to fix swr.
3780 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3781 clear the high bits.
3782 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3783 Fix float to int conversions to produce signed values.
3784
3785Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3786
3787 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3788 (process_instructions): Correct handling of nor instruction.
3789 Correct shift count for 32 bit shift instructions. Correct sign
3790 extension for arithmetic shifts to not shift the number of bits in
3791 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3792 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3793 Fix madd.
3794 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3795 It's OK to have a mult follow a mult. What's not OK is to have a
3796 mult follow an mfhi.
3797 (Convert): Comment out incorrect rounding code.
3798
3799Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3800
3801 * interp.c (sim_monitor): Improved monitor printf
3802 simulation. Tidied up simulator warnings, and added "--log" option
3803 for directing warning message output.
3804 * gencode.c: Use sim_warning() rather than WARNING macro.
3805
3806Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3807
3808 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3809 getopt1.o, rather than on gencode.c. Link objects together.
3810 Don't link against -liberty.
3811 (gencode.o, getopt.o, getopt1.o): New targets.
3812 * gencode.c: Include <ctype.h> and "ansidecl.h".
3813 (AND): Undefine after including "ansidecl.h".
3814 (ULONG_MAX): Define if not defined.
3815 (OP_*): Don't define macros; now defined in opcode/mips.h.
3816 (main): Call my_strtoul rather than strtoul.
3817 (my_strtoul): New static function.
3818
3819Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3820
3821 * gencode.c (process_instructions): Generate word64 and uword64
3822 instead of `long long' and `unsigned long long' data types.
3823 * interp.c: #include sysdep.h to get signals, and define default
3824 for SIGBUS.
3825 * (Convert): Work around for Visual-C++ compiler bug with type
3826 conversion.
3827 * support.h: Make things compile under Visual-C++ by using
3828 __int64 instead of `long long'. Change many refs to long long
3829 into word64/uword64 typedefs.
3830
3831Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3832
72f4393d
L		 3833 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3834 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3835 (docdir): Removed.
3836 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3837 (AC_PROG_INSTALL): Added.
c906108c 3838 (AC_PROG_CC): Moved to before configure.host call.
72f4393d
L		 3839 * configure: Rebuilt.
3840
c906108c
SS		 3841Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3842
3843 * configure.in: Define @SIMCONF@ depending on mips target.
3844 * configure: Rebuild.
3845 * Makefile.in (run): Add @SIMCONF@ to control simulator
3846 construction.
3847 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3848 * interp.c: Remove some debugging, provide more detailed error
3849 messages, update memory accesses to use LOADDRMASK.
72f4393d 3850
c906108c
SS		 3851Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3852
3853 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3854 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3855 stamp-h.
3856 * configure: Rebuild.
3857 * config.in: New file, generated by autoheader.
3858 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3859 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3860 HAVE_ANINT and HAVE_AINT, as appropriate.
3861 * Makefile.in (run): Use @LIBS@ rather than -lm.
3862 (interp.o): Depend upon config.h.
3863 (Makefile): Just rebuild Makefile.
3864 (clean): Remove stamp-h.
3865 (mostlyclean): Make the same as clean, not as distclean.
3866 (config.h, stamp-h): New targets.
3867
3868Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3869
3870 * interp.c (ColdReset): Fix boolean test. Make all simulator
3871 globals static.
3872
3873Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3874
3875 * interp.c (xfer_direct_word, xfer_direct_long,
3876 swap_direct_word, swap_direct_long, xfer_big_word,
3877 xfer_big_long, xfer_little_word, xfer_little_long,
3878 swap_word,swap_long): Added.
3879 * interp.c (ColdReset): Provide function indirection to
3880 host<->simulated_target transfer routines.
3881 * interp.c (sim_store_register, sim_fetch_register): Updated to
3882 make use of indirected transfer routines.
3883
3884Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3885
3886 * gencode.c (process_instructions): Ensure FP ABS instruction
3887 recognised.
3888 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3889 system call support.
3890
3891Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3892
3893 * interp.c (sim_do_command): Complain if callback structure not
3894 initialised.
3895
3896Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3897
3898 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3899 support for Sun hosts.
3900 * Makefile.in (gencode): Ensure the host compiler and libraries
3901 used for cross-hosted build.
3902
3903Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3904
3905 * interp.c, gencode.c: Some more (TODO) tidying.
3906
3907Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3908
3909 * gencode.c, interp.c: Replaced explicit long long references with
3910 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3911 * support.h (SET64LO, SET64HI): Macros added.
3912
3913Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3914
3915 * configure: Regenerate with autoconf 2.7.
3916
3917Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3918
3919 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3920 * support.h: Remove superfluous "1" from #if.
3921 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3922
3923Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3924
3925 * interp.c (StoreFPR): Control UndefinedResult() call on
3926 WARN_RESULT manifest.
3927
3928Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3929
3930 * gencode.c: Tidied instruction decoding, and added FP instruction
3931 support.
3932
3933 * interp.c: Added dineroIII, and BSD profiling support. Also
3934 run-time FP handling.
3935
3936Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3937
3938 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3939 gencode.c, interp.c, support.h: created.
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