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sim-main.h: track SKY register number changes from gdb
[deliverable/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
dd15abd5
GRK		 1start-sanitize-vr4320
2Tue Mar 3 11:56:29 1998 Gavin Koch <gavin@cygnus.com>
3
4 * vr4320.igen: New file.
5 * Makefile.in (vr4320.igen) : Added.
6 * configure.in (mips64vr4320-*-*): Added.
7 * configure : Rebuilt.
8 * mips.igen : Correct the bfd-names in the mips-ISA model entries.
9 Add the vr4320 model entry and mark the vr4320 insn as necessary.
10
11end-sanitize-vr4320
ca6f76d1
AC		 12Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
13
14 * sim-main.h (GETFCC): Return an unsigned value.
15
16start-sanitize-r5900
17 * r5900.igen: Use an unsigned array index variable `i'.
18 (QFSRV): Ditto for variable bytes.
19
20end-sanitize-r5900
21Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
22
23 * mips.igen (DIV): Fix check for -1 / MIN_INT.
24 (DADD): Result destination is RD not RT.
25
26start-sanitize-r5900
27 * r5900.igen (DIV1): Fix check for -1 / MIN_INT.
28 (DIVU1): Don't check for MIN_INT / -1 as performing unsigned
29 divide.
30
31end-sanitize-r5900
0e701ac3
AC		 32Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
33
34 * sim-main.h (HIACCESS, LOACCESS): Always define.
35
36 * mdmx.igen (Maxi, Mini): Rename Max, Min.
37
38 * interp.c (sim_info): Delete.
39
7c5d88c1
DE		 40Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
41
42 * interp.c (DECLARE_OPTION_HANDLER): Use it.
43 (mips_option_handler): New argument `cpu'.
44 (sim_open): Update call to sim_add_option_table.
45
f89c0689
AC		 46Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
47
48 * mips.igen (CxC1): Add tracing.
49
50start-sanitize-r5900
51Wed Feb 25 13:59:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
52
53 * r5900.igen (StoreFP): Delete.
54 (r59fp_store, r59fp_overflow, r59fp_op1, r59fp_op2, r59fp_op3):
55 New functions.
56 (rsqrt.s, sqrt.s): Implement.
57 (r59cond): New function.
58 (C.COND.S): Call r59cond in assembler line.
59 (cvt.w.s, cvt.s.w): Implement.
60
61 * mips.igen (rsqrt.fmt, sqrt.fmt, cvt.*.*): Remove from r5900
62 instruction set.
63
64 * sim-main.h: Define an enum of r5900 FCSR bit fields.
65
66end-sanitize-r5900
a48e8c8d 67start-sanitize-r5900
d3e1d594
AC		 68Tue Feb 24 14:44:18 1998 Andrew Cagney <cagney@b1.cygnus.com>
69
70 * r5900.igen: Add tracing to all p* instructions.
71
a48e8c8d
AC		 72Tue Feb 24 02:47:33 1998 Andrew Cagney <cagney@b1.cygnus.com>
73
74 * interp.c (sim_store_register, sim_fetch_register): Pull swifty
75 to get gdb talking to re-aranged sim_cpu register structure.
76
77end-sanitize-r5900
78Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
79
80 * sim-main.h (Max, Min): Declare.
81
82 * interp.c (Max, Min): New functions.
83
84 * mips.igen (BC1): Add tracing.
85
86start-sanitize-vr5400
87Fri Feb 20 16:27:17 1998 Andrew Cagney <cagney@b1.cygnus.com>
88
89 * mdmx.igen: Tag all functions as requiring either with mdmx or
90 vr5400 processor.
91
92end-sanitize-vr5400
93start-sanitize-r5900
94Fri Feb 20 15:55:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
95
96 * configure.in (SIM_AC_OPTION_FLOAT): For r5900, set FP bit size
97 to 32.
98 (SIM_AC_OPTION_BITSIZE): For r5900, set nr address bits to 32.
99
100 * mips.igen (C.cond.fmt, ..): Not part of r5900 insn set.
101
102 * r5900.igen: Rewrite.
103
104 * sim-main.h: Move r5900 registers to a separate _sim_r5900_cpu
105 struct.
106 (GPR_SB, GPR_SH, GPR_SW, GPR_SD, GPR_UB, GPR_UH, GPR_UW, GPR_UD):
107 Define in terms of GPR/GPR1 instead of REGISTERS/REGISTERS.1
108
109end-sanitize-r5900
110Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
111
112 * interp.c Added memory map for stack in vr4100
113
f319bab2
GRK		 114Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
115
116 * interp.c (load_memory): Add missing "break"'s.
117
118Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
119
120 * interp.c (sim_store_register, sim_fetch_register): Pass in
121 length parameter. Return -1.
122
123Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
124
125 * interp.c: Added hardware init hook, fixed warnings.
126
452b3808
AC		 127Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
128
129 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
130
37379a25
AC		 131Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
132
133 * interp.c (ifetch16): New function.
134
135 * sim-main.h (IMEM32): Rename IMEM.
136 (IMEM16_IMMED): Define.
137 (IMEM16): Define.
138 (DELAY_SLOT): Update.
139
140 * m16run.c (sim_engine_run): New file.
141
142 * m16.igen: All instructions except LB.
143 (LB): Call do_load_byte.
144 * mips.igen (do_load_byte): New function.
145 (LB): Call do_load_byte.
146
147 * mips.igen: Move spec for insn bit size and high bit from here.
148 * Makefile.in (tmp-igen, tmp-m16): To here.
149
150 * m16.dc: New file, decode mips16 instructions.
151
152 * Makefile.in (SIM_NO_ALL): Define.
153 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
154
155start-sanitize-tx19
156 * m16.igen: Mark all mips16 insns as being part of the tx19 insn
157 set.
158
159end-sanitize-tx19
160Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
161
162 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
163 point unit to 32 bit registers.
164 * configure: Re-generate.
165
166Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
167
168 * configure.in (sim_use_gen): Make IGEN the default simulator
169 generator for generic 32 and 64 bit mips targets.
170 * configure: Re-generate.
171
a97f304b
AC		 172Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
173
174 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
175 bitsize.
176
177 * interp.c (sim_fetch_register, sim_store_register): Read/write
178 FGR from correct location.
179 (sim_open): Set size of FGR's according to
180 WITH_TARGET_FLOATING_POINT_BITSIZE.
181
182 * sim-main.h (FGR): Store floating point registers in a separate
183 array.
184
185Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
186
187 * configure: Regenerated to track ../common/aclocal.m4 changes.
188
189start-sanitize-vr5400
190 * mdmx.igen: Mark all instructions as 64bit/fp specific.
191
192end-sanitize-vr5400
2acd126a
AC		 193Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
194
195 * interp.c (ColdReset): Call PENDING_INVALIDATE.
196
197 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
198
199 * interp.c (pending_tick): New function. Deliver pending writes.
200
201 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
202 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
203 it can handle mixed sized quantites and single bits.
204
192ae475
AC		 205Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
206
207 * interp.c (oengine.h): Do not include when building with IGEN.
208 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
209 (sim_info): Ditto for PROCESSOR_64BIT.
210 (sim_monitor): Replace ut_reg with unsigned_word.
211 (*): Ditto for t_reg.
212 (LOADDRMASK): Define.
213 (sim_open): Remove defunct check that host FP is IEEE compliant,
214 using software to emulate floating point.
215 (value_fpr, ...): Always compile, was conditional on HASFPU.
216
01737f42
AC		 217Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
218
219 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
220 size.
221
222 * interp.c (SD, CPU): Define.
223 (mips_option_handler): Set flags in each CPU.
224 (interrupt_event): Assume CPU 0 is the one being iterrupted.
225 (sim_close): Do not clear STATE, deleted anyway.
226 (sim_write, sim_read): Assume CPU zero's vm should be used for
227 data transfers.
228 (sim_create_inferior): Set the PC for all processors.
229 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
230 argument.
231 (mips16_entry): Pass correct nr of args to store_word, load_word.
232 (ColdReset): Cold reset all cpu's.
233 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
234 (sim_monitor, load_memory, store_memory, signal_exception): Use
235 `CPU' instead of STATE_CPU.
236
237
238 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
239 SD or CPU_.
240
241 * sim-main.h (signal_exception): Add sim_cpu arg.
242 (SignalException*): Pass both SD and CPU to signal_exception.
243 * interp.c (signal_exception): Update.
244
245 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
246 Ditto
247 (sync_operation, prefetch, cache_op, store_memory, load_memory,
248 address_translation): Ditto
249 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
250
251start-sanitize-vr5400
252 * mdmx.igen (get_scale): Pass CPU_ to semantic_illegal instead of
253 `sd'.
254 (ByteAlign): Use StoreFPR, pass args in correct order.
255
256end-sanitize-vr5400
257start-sanitize-r5900
258Sun Feb 1 10:59:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
259
260 * configure.in (sim_igen_filter): For r5900, configure as SMP.
261
262end-sanitize-r5900
412c4e94
AC		 263Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
264
265 * configure: Regenerated to track ../common/aclocal.m4 changes.
266
9ec6741b
AC		 267Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
268
c4db5b04
AC		 269start-sanitize-r5900
270 * configure.in (sim_igen_filter): For r5900, use igen.
271 * configure: Re-generate.
272
273end-sanitize-r5900
9ec6741b
AC		 274 * interp.c (sim_engine_run): Add `nr_cpus' argument.
275
276 * mips.igen (model): Map processor names onto BFD name.
277
278 * sim-main.h (CPU_CIA): Delete.
279 (SET_CIA, GET_CIA): Define
280
2d44e12a
AC		 281Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
282
283 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
284 regiser.
285
286 * configure.in (default_endian): Configure a big-endian simulator
287 by default.
288 * configure: Re-generate.
289
462cfbc4
DE		 290Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
291
292 * configure: Regenerated to track ../common/aclocal.m4 changes.
293
e0e0fc76
MA		 294Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
295
296 * interp.c (sim_monitor): Handle Densan monitor outbyte
297 and inbyte functions.
298
76ef4165
FL		 2991997-12-29 Felix Lee <flee@cygnus.com>
300
301 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
302
303Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
304
305 * Makefile.in (tmp-igen): Arrange for $zero to always be
306 reset to zero after every instruction.
307
9c8ec16d
AC		 308Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
309
310 * configure: Regenerated to track ../common/aclocal.m4 changes.
311 * config.in: Ditto.
312
255cbbf1 313start-sanitize-vr5400
b17d2d14
AC		 314Sat Dec 13 15:18:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
315
316 * vr5400.igen (Low32Bits, High32Bits): Sign extend extracted 32
317 bit values.
318
319end-sanitize-vr5400
320start-sanitize-vr5400
255cbbf1
JL		 321Fri Dec 12 12:26:07 1997 Jeffrey A Law (law@cygnus.com)
322
323 * configure.in (sim_igen_filter): Multi-sim vr5000 - vr5000 or
324 vr5400 with the vr5000 as the default.
325
326end-sanitize-vr5400
23850e92
JL		 327Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
328
329 * mips.igen (MSUB): Fix to work like MADD.
330 * gencode.c (MSUB): Similarly.
331
c02ed6a8
AC		 332start-sanitize-vr5400
333Tue Dec 9 12:02:12 1997 Andrew Cagney <cagney@b1.cygnus.com>
334
335 * configure.in (sim_igen_filter): Multi-sim vr5400 - vr5000 or
336 vr5400.
337
338end-sanitize-vr5400
6e51f990
DE		 339Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
340
341 * configure: Regenerated to track ../common/aclocal.m4 changes.
342
35c246c9
AC		 343Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
344
345 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
346
347start-sanitize-vr5400
0d5d0d10 348 * mdmx.igen (value_vr): Correct sim_io_eprintf format argument.
0931ce5a 349 (value_cc, store_cc): Implement.
0d5d0d10 350
35c246c9
AC		 351 * sim-main.h: Add 8*3*8 bit accumulator.
352
353 * vr5400.igen: Move mdmx instructins from here
354 * mdmx.igen: To here - new file. Add/fix missing instructions.
355 * mips.igen: Include mdmx.igen.
0931ce5a 356 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
35c246c9 357
c02ed6a8 358end-sanitize-vr5400
58fb5d0a
AC		 359Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
360
361 * sim-main.h (sim-fpu.h): Include.
362
363 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
364 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
365 using host independant sim_fpu module.
366
a09a30d2
AC		 367Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
368
232156de
AC		 369 * interp.c (signal_exception): Report internal errors with SIGABRT
370 not SIGQUIT.
a09a30d2 371
232156de
AC		 372 * sim-main.h (C0_CONFIG): New register.
373 (signal.h): No longer include.
374
375 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
a09a30d2 376
486740ce
DE		 377Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
378
379 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
380
f23e93da
AC		 381Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
382
383 * mips.igen: Tag vr5000 instructions.
384 (ANDI): Was missing mipsIV model, fix assembler syntax.
385 (do_c_cond_fmt): New function.
386 (C.cond.fmt): Handle mips I-III which do not support CC field
387 separatly.
388 (bc1): Handle mips IV which do not have a delaed FCC separatly.
389 (SDR): Mask paddr when BigEndianMem, not the converse as specified
390 in IV3.2 spec.
391 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
392 vr5000 which saves LO in a GPR separatly.
393
394 * configure.in (enable-sim-igen): For vr5000, select vr5000
395 specific instructions.
396 * configure: Re-generate.
397
398Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
399
400 * Makefile.in (SIM_OBJS): Add sim-fpu module.
401
402 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
403 fmt_uninterpreted_64 bit cases to switch. Convert to
404 fmt_formatted,
405
406 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
407
408 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
409 as specified in IV3.2 spec.
410 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
411
030843d7
AC		 412Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
413
414 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
415 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
416 (start-sanitize-r5900):
417 (LWXC1, SWXC1): Delete from r5900 instruction set.
418 (end-sanitize-r5900):
419 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
a94c5493 420 PENDING_FILL versions of instructions. Simplify.
030843d7
AC		 421 (X): New function.
422 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
423 instructions.
a94c5493
AC		 424 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
425 a signed value.
030843d7
AC		 426 (MTHI, MFHI): Disable code checking HI-LO.
427
428 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
429 global.
430 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
431
7ce8b917
AC		 432Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
433
95469ceb
AC		 434 * gencode.c (build_mips16_operands): Replace IPC with cia.
435
436 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
437 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
438 IPC to `cia'.
439 (UndefinedResult): Replace function with macro/function
440 combination.
441 (sim_engine_run): Don't save PC in IPC.
442
443 * sim-main.h (IPC): Delete.
444
445 start-sanitize-vr5400
446 * vr5400.igen (vr): Add missing cia argument to value_fpr.
447 (do_select): Rename function select.
448 end-sanitize-vr5400
449
7ce8b917
AC		 450 * interp.c (signal_exception, store_word, load_word,
451 address_translation, load_memory, store_memory, cache_op,
452 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
95469ceb
AC		 453 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
454 current instruction address - cia - argument.
7ce8b917
AC		 455 (sim_read, sim_write): Call address_translation directly.
456 (sim_engine_run): Rename variable vaddr to cia.
95469ceb
AC		 457 (signal_exception): Pass cia to sim_monitor
458
7ce8b917
AC		 459 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
460 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
461 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
462
463 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
464 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
465 SIM_ASSERT.
466
467 * interp.c (signal_exception): Pass restart address to
468 sim_engine_restart.
469
470 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
471 idecode.o): Add dependency.
472
473 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
474 Delete definitions
475 (DELAY_SLOT): Update NIA not PC with branch address.
476 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
477
478 * mips.igen: Use CIA not PC in branch calculations.
479 (illegal): Call SignalException.
480 (BEQ, ADDIU): Fix assembler.
481
63be8feb
AC		 482Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
483
44b8585a
AC		 484 * m16.igen (JALX): Was missing.
485
486 * configure.in (enable-sim-igen): New configuration option.
487 * configure: Re-generate.
488
63be8feb
AC		 489 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
490
491 * interp.c (load_memory, store_memory): Delete parameter RAW.
492 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
493 bypassing {load,store}_memory.
494
495 * sim-main.h (ByteSwapMem): Delete definition.
496
497 * Makefile.in (SIM_OBJS): Add sim-memopt module.
498
499 * interp.c (sim_do_command, sim_commands): Delete mips specific
500 commands. Handled by module sim-options.
501
502 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
503 (WITH_MODULO_MEMORY): Define.
504
505 * interp.c (sim_info): Delete code printing memory size.
506
507 * interp.c (mips_size): Nee sim_size, delete function.
508 (power2): Delete.
509 (monitor, monitor_base, monitor_size): Delete global variables.
510 (sim_open, sim_close): Delete code creating monitor and other
511 memory regions. Use sim-memopts module, via sim_do_commandf, to
512 manage memory regions.
513 (load_memory, store_memory): Use sim-core for memory model.
514
515 * interp.c (address_translation): Delete all memory map code
516 except line forcing 32 bit addresses.
517
22de994d
AC		 518Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
519
520 * sim-main.h (WITH_TRACE): Delete definition. Enables common
521 trace options.
522
523 * interp.c (logfh, logfile): Delete globals.
524 (sim_open, sim_close): Delete code opening & closing log file.
525 (mips_option_handler): Delete -l and -n options.
526 (OPTION mips_options): Ditto.
527
528 * interp.c (OPTION mips_options): Rename option trace to dinero.
529 (mips_option_handler): Update.
530
525d929e
AC		 531Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
532
533 * interp.c (fetch_str): New function.
534 (sim_monitor): Rewrite using sim_read & sim_write.
535 (sim_open): Check magic number.
536 (sim_open): Write monitor vectors into memory using sim_write.
537 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
538 (sim_read, sim_write): Simplify - transfer data one byte at a
539 time.
540 (load_memory, store_memory): Clarify meaning of parameter RAW.
541
542 * sim-main.h (isHOST): Defete definition.
543 (isTARGET): Mark as depreciated.
544 (address_translation): Delete parameter HOST.
545
546 * interp.c (address_translation): Delete parameter HOST.
547
6205f379
GRK		 548start-sanitize-tx49
549Wed Oct 29 14:21:32 1997 Gavin Koch <gavin@cygnus.com>
550
551 * gencode.c: Add tx49 configury and insns.
552 * configure.in: Add tx49 configury.
553 * configure: Update.
554
555end-sanitize-tx49
01b9cd49
AC		 556Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
557
558 * mips.igen:
559
560 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
561 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
562
89d09738
AC		 563Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
564
565 * mips.igen: Add model filter field to records.
566
16bd5d6e
AC		 567Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
568
569 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
570
571 interp.c (sim_engine_run): Do not compile function sim_engine_run
572 when WITH_IGEN == 1.
573
574 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
575 target architecture.
576
577 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
578 igen. Replace with configuration variables sim_igen_flags /
579 sim_m16_flags.
580
16bd5d6e 581 start-sanitize-r5900
8c31916d
AC		 582 * r5900.igen: New file. Copy r5900 insns here.
583 end-sanitize-r5900
16bd5d6e 584 start-sanitize-vr5400
58fb5d0a 585 * vr5400.igen: New file.
255cbbf1 586 end-sanitize-vr5400
16bd5d6e
AC		 587 * m16.igen: New file. Copy mips16 insns here.
588 * mips.igen: From here.
589
90ad43b2
AC		 590Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
591
592 start-sanitize-vr5400
593 * mips.igen: Tag all mipsIV instructions with vr5400 model.
594
595 * configure.in: Add mips64vr5400 target.
596 * configure: Re-generate.
597
598 end-sanitize-vr5400
599 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
600 to top.
601 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
602
635ae9cb
GRK		 603Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
604
605 * gencode.c (build_instruction): Follow sim_write's lead in using
606 BigEndianMem instead of !ByteSwapMem.
607
122edc03
AC		 608Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
609
610 * configure.in (sim_gen): Dependent on target, select type of
611 generator. Always select old style generator.
612
613 configure: Re-generate.
614
615 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
616 targets.
617 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
618 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
619 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
620 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
621 SIM_@sim_gen@_*, set by autoconf.
622
dad6f1f3
AC		 623Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
624
625 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
626
627 * interp.c (ColdReset): Remove #ifdef HASFPU, check
628 CURRENT_FLOATING_POINT instead.
629
630 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
631 (address_translation): Raise exception InstructionFetch when
632 translation fails and isINSTRUCTION.
633
634 * interp.c (sim_open, sim_write, sim_monitor, store_word,
635 sim_engine_run): Change type of of vaddr and paddr to
636 address_word.
637 (address_translation, prefetch, load_memory, store_memory,
638 cache_op): Change type of vAddr and pAddr to address_word.
639
640 * gencode.c (build_instruction): Change type of vaddr and paddr to
641 address_word.
642
92ad193b
AC		 643Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
644
645 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
646 macro to obtain result of ALU op.
647
aa324b9b
AC		 648Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
649
650 * interp.c (sim_info): Call profile_print.
651
e2f8ffb7
AC		 652Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
653
654 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
655
656 * sim-main.h (WITH_PROFILE): Do not define, defined in
657 common/sim-config.h. Use sim-profile module.
658 (simPROFILE): Delete defintion.
659
660 * interp.c (PROFILE): Delete definition.
661 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
662 (sim_close): Delete code writing profile histogram.
663 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
664 Delete.
665 (sim_engine_run): Delete code profiling the PC.
666
fb5a2a3e
AC		 667Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
668
669 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
670
671 * interp.c (sim_monitor): Make register pointers of type
672 unsigned_word*.
673
674 * sim-main.h: Make registers of type unsigned_word not
675 signed_word.
676
ea985d24
AC		 677Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
678
679start-sanitize-r5900
680 * sim-main.h (BYTES_IN_MMI_REGS, ..., SUB_REG_FETCH, ..., GPR_SB,
681 ...): Move to sim-main.h
682
683end-sanitize-r5900
684 * interp.c (sync_operation): Rename from SyncOperation, make
685 global, add SD argument.
686 (prefetch): Rename from Prefetch, make global, add SD argument.
687 (decode_coproc): Make global.
688
689 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
690
691 * gencode.c (build_instruction): Generate DecodeCoproc not
692 decode_coproc calls.
693
694 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
695 (SizeFGR): Move to sim-main.h
696 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
697 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
698 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
699 sim-main.h.
700 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
701 FP_RM_TOMINF, GETRM): Move to sim-main.h.
702 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
703 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
704 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
705 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
706
707 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
708 exception.
709 (sim-alu.h): Include.
710 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
711 (sim_cia): Typedef to instruction_address.
712
284e759d
AC		 713Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
714
715 * Makefile.in (interp.o): Rename generated file engine.c to
716 oengine.c.
717
718 * interp.c: Update.
719
339fb149
AC		 720Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
721
722 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
723
8b70f837
AC		 724Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
725
726 * gencode.c (build_instruction): For "FPSQRT", output correct
727 number of arguments to Recip.
728
0c2c5f61
AC		 729Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
730
731 * Makefile.in (interp.o): Depends on sim-main.h
732
733 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
734
735 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
736 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
737 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
738 STATE, DSSTATE): Define
739 (GPR, FGRIDX, ..): Define.
740
741 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
742 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
743 (GPR, FGRIDX, ...): Delete macros.
744
745 * interp.c: Update names to match defines from sim-main.h
746
18c64df6
AC		 747Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
748
749 * interp.c (sim_monitor): Add SD argument.
750 (sim_warning): Delete. Replace calls with calls to
751 sim_io_eprintf.
752 (sim_error): Delete. Replace calls with sim_io_error.
753 (open_trace, writeout32, writeout16, getnum): Add SD argument.
754 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
755 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
756 argument.
757 (mips_size): Rename from sim_size. Add SD argument.
758
759 * interp.c (simulator): Delete global variable.
760 (callback): Delete global variable.
761 (mips_option_handler, sim_open, sim_write, sim_read,
762 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
763 sim_size,sim_monitor): Use sim_io_* not callback->*.
764 (sim_open): ZALLOC simulator struct.
765 (PROFILE): Do not define.
766
767Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
768
769 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
770 support.h with corresponding code.
771
772 * sim-main.h (word64, uword64), support.h: Move definition to
773 sim-main.h.
774 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
775
776 * support.h: Delete
777 * Makefile.in: Update dependencies
778 * interp.c: Do not include.
779
780Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
781
782 * interp.c (address_translation, load_memory, store_memory,
783 cache_op): Rename to from AddressTranslation et.al., make global,
784 add SD argument
785
786 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
787 CacheOp): Define.
788
789 * interp.c (SignalException): Rename to signal_exception, make
790 global.
791
792 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
793
794 * sim-main.h (SignalException, SignalExceptionInterrupt,
795 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
796 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
797 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
798 Define.
799
800 * interp.c, support.h: Use.
801
802Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
803
804 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
805 to value_fpr / store_fpr. Add SD argument.
806 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
807 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
808
809 * sim-main.h (ValueFPR, StoreFPR): Define.
810
811Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
812
813 * interp.c (sim_engine_run): Check consistency between configure
814 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
815 and HASFPU.
816
817 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
818 (mips_fpu): Configure WITH_FLOATING_POINT.
819 (mips_endian): Configure WITH_TARGET_ENDIAN.
820 * configure: Update.
821
822Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
823
824 * configure: Regenerated to track ../common/aclocal.m4 changes.
825
adf4739e
AC		 826start-sanitize-r5900
827Mon Aug 25 19:11:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
828
829 * interp.c (MAX_REG): Allow up-to 128 registers.
830 (LO1, HI1): Define value that matches REGISTER_NAMES in gdb.
831 (REGISTER_SA): Ditto.
832 (sim_open): Initialize register_widths for r5900 specific
833 registers.
834 (sim_fetch_register, sim_store_register): Check for request of
835 r5900 specific SA register. Check for request for hi 64 bits of
836 r5900 specific registers.
837
838end-sanitize-r5900
26b20b0a
BM		 839Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
840
841 * configure: Regenerated.
842
6eedf3f4
MA		 843Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
844
845 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
846
e63bc706
AC		 847Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
848
6eedf3f4
MA		 849 * gencode.c (print_igen_insn_models): Assume certain architectures
850 include all mips* instructions.
851 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
852 instruction.
853
e63bc706
AC		 854 * Makefile.in (tmp.igen): Add target. Generate igen input from
855 gencode file.
856
857 * gencode.c (FEATURE_IGEN): Define.
858 (main): Add --igen option. Generate output in igen format.
859 (process_instructions): Format output according to igen option.
860 (print_igen_insn_format): New function.
861 (print_igen_insn_models): New function.
862 (process_instructions): Only issue warnings and ignore
863 instructions when no FEATURE_IGEN.
864
eb2e3c85
AC		 865Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
866
867 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
868 MIPS targets.
869
92f91d1f
AC		 870Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
871
872 * configure: Regenerated to track ../common/aclocal.m4 changes.
873
874Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
875
876 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
877 SIM_RESERVED_BITS): Delete, moved to common.
878 (SIM_EXTRA_CFLAGS): Update.
879
794e9ac9
AC		 880Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
881
76a6247f 882 * configure.in: Configure non-strict memory alignment.
794e9ac9
AC		 883 * configure: Regenerated to track ../common/aclocal.m4 changes.
884
b45caf05
AC		 885Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
886
887 * configure: Regenerated to track ../common/aclocal.m4 changes.
888
889Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
890
891 * gencode.c (SDBBP,DERET): Added (3900) insns.
892 (RFE): Turn on for 3900.
893 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
894 (dsstate): Made global.
895 (SUBTARGET_R3900): Added.
896 (CANCELDELAYSLOT): New.
897 (SignalException): Ignore SystemCall rather than ignore and
898 terminate. Add DebugBreakPoint handling.
899 (decode_coproc): New insns RFE, DERET; and new registers Debug
900 and DEPC protected by SUBTARGET_R3900.
901 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
902 bits explicitly.
903 * Makefile.in,configure.in: Add mips subtarget option.
904 * configure: Update.
905
7afa8d4e
GRK		 906Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
907
908 * gencode.c: Add r3900 (tx39).
909
910start-sanitize-tx19
911 * gencode.c: Fix some configuration problems by improving
912 the relationship between tx19 and tx39.
913end-sanitize-tx19
914
667065d0
GRK		 915Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
916
917 * gencode.c (build_instruction): Don't need to subtract 4 for
918 JALR, just 2.
919
9cb8397f
GRK		 920Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
921
922 * interp.c: Correct some HASFPU problems.
923
a2ab5e65
AC		 924Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
925
926 * configure: Regenerated to track ../common/aclocal.m4 changes.
927
11ac69e0
AC		 928Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
929
930 * interp.c (mips_options): Fix samples option short form, should
931 be `x'.
932
972f3a34
AC		 933Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
934
935 * interp.c (sim_info): Enable info code. Was just returning.
936
9eeaaefa
AC		 937Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
938
939 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
940 MFC0.
941
c31c13b4
AC		 942Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
943
944 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
945 constants.
946 (build_instruction): Ditto for LL.
947
b637f306
GRK		 948start-sanitize-tx19
949Sun Sep 7 16:05:46 1997 Gavin Koch <gavin@cygnus.com>
950
951 * mips/configure.in, mips/gencode: Add tx19/r1900.
952
953end-sanitize-tx19
6fea4763
DE		 954Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
955
956 * configure: Regenerated to track ../common/aclocal.m4 changes.
957
52352d38
AC		 958start-sanitize-r5900
959Mon Sep 1 18:43:30 1997 Andrew Cagney <cagney@b1.cygnus.com>
960
961 * gencode.c (build_instruction): For "pabsw" and "pabsh", check
962 for overflow due to ABS of MININT, set result to MAXINT.
963 (build_instruction): For "psrlvw", signextend bit 31.
964
965end-sanitize-r5900
88117054
AC		 966Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
967
968 * configure: Regenerated to track ../common/aclocal.m4 changes.
969 * config.in: Ditto.
970
fafce69a
AC		 971Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
972
973 * interp.c (sim_open): Add call to sim_analyze_program, update
974 call to sim_config.
975
7230ff0f
AC		 976Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
977
978 * interp.c (sim_kill): Delete.
fafce69a
AC		 979 (sim_create_inferior): Add ABFD argument. Set PC from same.
980 (sim_load): Move code initializing trap handlers from here.
981 (sim_open): To here.
982 (sim_load): Delete, use sim-hload.c.
983
984 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
7230ff0f 985
247fccde
AC		 986Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
987
988 * configure: Regenerated to track ../common/aclocal.m4 changes.
989 * config.in: Ditto.
990
991Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
992
993 * interp.c (sim_open): Add ABFD argument.
994 (sim_load): Move call to sim_config from here.
995 (sim_open): To here. Check return status.
996
997start-sanitize-r5900
998 * gencode.c (build_instruction): Do not define x8000000000000000,
999 x7FFFFFFFFFFFFFFF, or xFFFFFFFF80000000.
1000
1001end-sanitize-r5900
1002start-sanitize-r5900
1003Mon Jul 28 19:49:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1004
1005 * gencode.c (build_instruction): For "pdivw", "pdivbw" and
1006 "pdivuw" check for overflow due to signed divide by -1.
1007
1008end-sanitize-r5900
c12e2e4c
GRK		 1009Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1010
1011 * gencode.c (build_instruction): Two arg MADD should
1012 not assign result to $0.
1013
1e851d2c
AC		 1014start-sanitize-r5900
1015Thu Jul 10 11:58:48 1997 Andrew Cagney <cagney@critters.cygnus.com>
1016
1017 * gencode.c (build_instruction): For "ppac5" use unsigned
1018 arrithmetic so that the sign bit doesn't smear when right shifted.
1019 (build_instruction): For "pdiv" perform sign extension when
1020 storing results in HI and LO.
1021 (build_instructions): For "pdiv" and "pdivbw" check for
1022 divide-by-zero.
1023 (build_instruction): For "pmfhl.slw" update hi part of dest
1024 register as well as low part.
1025 (build_instruction): For "pmfhl" portably handle long long values.
1026 (build_instruction): For "pmfhl.sh" correctly negative values.
1027 Store half words 2 and three in the correct place.
1028 (build_instruction): For "psllvw", sign extend value after shift.
1029
1030end-sanitize-r5900
1031Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1032
1033 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1034 * sim/mips/configure.in: Regenerate.
1035
1036Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1037
1038 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1039 signed8, unsigned8 et.al. types.
1040
1041start-sanitize-r5900
1042 * gencode.c (build_instruction): For PMULTU* do not sign extend
1043 registers. Make generated code easier to debug.
1044
1045end-sanitize-r5900
1046 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1047 hosts when selecting subreg.
1048
1049start-sanitize-r5900
1050Tue Jul 8 18:07:20 1997 Andrew Cagney <cagney@andros.cygnus.com>
1051
1052 * gencode.c (type_for_data_len): For 32bit operations concerned
1053 with overflow, perform op using 64bits.
1054 (build_instruction): For PADD, always compute operation using type
1055 returned by type_for_data_len.
1056 (build_instruction): For PSUBU, when overflow, saturate to zero as
1057 actually underflow.
1058
1059end-sanitize-r5900
ae19b07b
JL		 1060Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1061
649625bb 1062start-sanitize-r5900
64435234
JL		 1063 * gencode.c (build_instruction): Handle "pext5" according to
1064 version 1.95 of the r5900 ISA.
1065
649625bb
JL		 1066 * gencode.c (build_instruction): Handle "ppac5" according to
1067 version 1.95 of the r5900 ISA.
649625bb 1068
1e851d2c 1069end-sanitize-r5900
05d1322f
JL		 1070 * interp.c (sim_engine_run): Reset the ZERO register to zero
1071 regardless of FEATURE_WARN_ZERO.
ae19b07b
JL		 1072 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1073
1074Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1075
1076 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1077 (SignalException): For BreakPoints ignore any mode bits and just
1078 save the PC.
1079 (SignalException): Always set the CAUSE register.
1080
56e7c849
AC		 1081Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1082
1083 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1084 exception has been taken.
1085
1086 * interp.c: Implement the ERET and mt/f sr instructions.
1087
ae19b07b 1088start-sanitize-r5900
56e7c849
AC		 1089Mon Jun 2 23:28:19 1997 Andrew Cagney <cagney@b1.cygnus.com>
1090
1091 * gencode.c (build_instruction): For paddu, extract unsigned
1092 sub-fields.
1093
1094 * gencode.c (build_instruction): Saturate padds instead of padd
1095 instructions.
1096
1097end-sanitize-r5900
1098Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1099
1100 * interp.c (SignalException): Don't bother restarting an
1101 interrupt.
1102
1103Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1104
1105 * interp.c (SignalException): Really take an interrupt.
1106 (interrupt_event): Only deliver interrupts when enabled.
1107
1108Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1109
1110 * interp.c (sim_info): Only print info when verbose.
1111 (sim_info) Use sim_io_printf for output.
1112
2f2e6c5d
AC		 1113Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1114
1115 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1116 mips architectures.
1117
1118Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1119
1120 * interp.c (sim_do_command): Check for common commands if a
1121 simulator specific command fails.
1122
d3d2a9f7
GRK		 1123Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
1124
1125 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1126 and simBE when DEBUG is defined.
1127
50a2a691
AC		 1128Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
1129
1130 * interp.c (interrupt_event): New function. Pass exception event
1131 onto exception handler.
1132
1133 * configure.in: Check for stdlib.h.
1134 * configure: Regenerate.
1135
1136 * gencode.c (build_instruction): Add UNUSED attribute to tempS
1137 variable declaration.
1138 (build_instruction): Initialize memval1.
1139 (build_instruction): Add UNUSED attribute to byte, bigend,
1140 reverse.
1141 (build_operands): Ditto.
1142
1143 * interp.c: Fix GCC warnings.
1144 (sim_get_quit_code): Delete.
1145
1146 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1147 * Makefile.in: Ditto.
1148 * configure: Re-generate.
1149
1150 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1151
1152Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1153
1154 * interp.c (mips_option_handler): New function parse argumes using
1155 sim-options.
1156 (myname): Replace with STATE_MY_NAME.
1157 (sim_open): Delete check for host endianness - performed by
1158 sim_config.
1159 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1160 (sim_open): Move much of the initialization from here.
1161 (sim_load): To here. After the image has been loaded and
1162 endianness set.
1163 (sim_open): Move ColdReset from here.
1164 (sim_create_inferior): To here.
1165 (sim_open): Make FP check less dependant on host endianness.
1166
1167 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1168 run.
1169 * interp.c (sim_set_callbacks): Delete.
1170
1171 * interp.c (membank, membank_base, membank_size): Replace with
1172 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1173 (sim_open): Remove call to callback->init. gdb/run do this.
1174
1175 * interp.c: Update
1176
1177 * sim-main.h (SIM_HAVE_FLATMEM): Define.
1178
1179 * interp.c (big_endian_p): Delete, replaced by
1180 current_target_byte_order.
1181
1182Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1183
1184 * interp.c (host_read_long, host_read_word, host_swap_word,
1185 host_swap_long): Delete. Using common sim-endian.
1186 (sim_fetch_register, sim_store_register): Use H2T.
1187 (pipeline_ticks): Delete. Handled by sim-events.
1188 (sim_info): Update.
1189 (sim_engine_run): Update.
1190
1191Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
1192
1193 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1194 reason from here.
1195 (SignalException): To here. Signal using sim_engine_halt.
1196 (sim_stop_reason): Delete, moved to common.
1197
1198Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
1199
1200 * interp.c (sim_open): Add callback argument.
1201 (sim_set_callbacks): Delete SIM_DESC argument.
1202 (sim_size): Ditto.
1203
2e61a3ad
AC		 1204Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1205
1206 * Makefile.in (SIM_OBJS): Add common modules.
1207
1208 * interp.c (sim_set_callbacks): Also set SD callback.
1209 (set_endianness, xfer_*, swap_*): Delete.
1210 (host_read_word, host_read_long, host_swap_word, host_swap_long):
1211 Change to functions using sim-endian macros.
1212 (control_c, sim_stop): Delete, use common version.
1213 (simulate): Convert into.
1214 (sim_engine_run): This function.
1215 (sim_resume): Delete.
1216
1217 * interp.c (simulation): New variable - the simulator object.
1218 (sim_kind): Delete global - merged into simulation.
1219 (sim_load): Cleanup. Move PC assignment from here.
1220 (sim_create_inferior): To here.
1221
1222 * sim-main.h: New file.
1223 * interp.c (sim-main.h): Include.
1224
1225Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
1226
1227 * configure: Regenerated to track ../common/aclocal.m4 changes.
1228
3be0e228
DE		 1229Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
1230
1231 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
1232
d654ba0a
GRK		 1233Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
1234
1235 * gencode.c (build_instruction): DIV instructions: check
1236 for division by zero and integer overflow before using
1237 host's division operation.
1238
9d52bcb7
DE		 1239Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
1240
1241 * Makefile.in (SIM_OBJS): Add sim-load.o.
1242 * interp.c: #include bfd.h.
1243 (target_byte_order): Delete.
1244 (sim_kind, myname, big_endian_p): New static locals.
1245 (sim_open): Set sim_kind, myname. Move call to set_endianness to
1246 after argument parsing. Recognize -E arg, set endianness accordingly.
1247 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
1248 load file into simulator. Set PC from bfd.
1249 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
1250 (set_endianness): Use big_endian_p instead of target_byte_order.
1251
87e43259
AC		 1252Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
1253
1254 * interp.c (sim_size): Delete prototype - conflicts with
1255 definition in remote-sim.h. Correct definition.
1256
1257Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1258
1259 * configure: Regenerated to track ../common/aclocal.m4 changes.
1260 * config.in: Ditto.
1261
fbda74b1
DE		 1262Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
1263
8a7c3105
DE		 1264 * interp.c (sim_open): New arg `kind'.
1265
fbda74b1
DE		 1266 * configure: Regenerated to track ../common/aclocal.m4 changes.
1267
a35e91c3
AC		 1268Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1269
1270 * configure: Regenerated to track ../common/aclocal.m4 changes.
1271
1272Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
1273
1274 * interp.c (sim_open): Set optind to 0 before calling getopt.
1275
1276Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1277
1278 * configure: Regenerated to track ../common/aclocal.m4 changes.
1279
6efa34d8
GRK		 1280Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
1281
1282 * interp.c : Replace uses of pr_addr with pr_uword64
1283 where the bit length is always 64 independent of SIM_ADDR.
1284 (pr_uword64) : added.
1285
a77aa7ec
AC		 1286Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1287
1288 * configure: Re-generate.
1289
601fb8ae
MM		 1290Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
1291
1292 * configure: Regenerate to track ../common/aclocal.m4 changes.
1293
53b9417e
DE		 1294Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
1295
1296 * interp.c (sim_open): New SIM_DESC result. Argument is now
1297 in argv form.
1298 (other sim_*): New SIM_DESC argument.
1299
1300start-sanitize-r5900
1301Wed Feb 26 18:32:21 1997 Gavin Koch <gavin@cygnus.com>
1302
1303 * gencode.c (POP_AND,POP_OR,POP_NOR,POP_XOR):
1304 Change values to avoid overloading DOUBLEWORD which is tested
1305 for all insns.
1306 * gencode.c: reinstate "offending code".
53b9417e 1307
56e7c849 1308end-sanitize-r5900
53b9417e
DE		 1309Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
1310
1311 * interp.c: Fix printing of addresses for non-64-bit targets.
1312 (pr_addr): Add function to print address based on size.
1313start-sanitize-r5900
1314 * gencode.c: #ifdef out offending code until a permanent fix
1315 can be added. Code is causing build errors for non-5900 mips targets.
1316end-sanitize-r5900
1317
1318start-sanitize-r5900
1319Thu Feb 20 10:40:24 1997 Gavin Koch <gavin@cetus.cygnus.com>
1320
1321 * gencode.c (process_instructions): Correct test for ISA dependent
1322 architecture bits in isa field of MIPS_DECODE.
1323
1324end-sanitize-r5900
7e05106d
MA		 1325Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
1326
1327 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
1328
2d18fbc6 1329start-sanitize-r5900
53b9417e 1330Tue Feb 18 17:03:47 1997 Gavin Koch <gavin@cygnus.com>
2d18fbc6
GRK		 1331
1332 * gencode.c (MIPS_DECODE): Correct instruction feature flags for
1333 PMADDUW.
1334
1335end-sanitize-r5900
1336Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
1337
1338 * gencode.c (build_mips16_operands): Correct computation of base
1339 address for extended PC relative instruction.
1340
276c2d7d
GRK		 1341start-sanitize-r5900
1342Fri Feb 7 11:12:44 1997 Gavin Koch <gavin@cygnus.com>
2d18fbc6
GRK		 1343
1344 * Makefile.in, configure, configure.in, gencode.c,
1345 interp.c, support.h: add r5900.
1346
276c2d7d 1347end-sanitize-r5900
da0bce9c
ILT		 1348Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
1349
1350 * interp.c (mips16_entry): Add support for floating point cases.
1351 (SignalException): Pass floating point cases to mips16_entry.
1352 (ValueFPR): Don't restrict fmt_single and fmt_word to even
1353 registers.
1354 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
1355 or fmt_word.
1356 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
1357 and then set the state to fmt_uninterpreted.
1358 (COP_SW): Temporarily set the state to fmt_word while calling
1359 ValueFPR.
1360
6389d856
ILT		 1361Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
1362
1363 * gencode.c (build_instruction): The high order may be set in the
1364 comparison flags at any ISA level, not just ISA 4.
1365
19c5af72
DE		 1366Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
1367
1368 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
1369 COMMON_{PRE,POST}_CONFIG_FRAG instead.
1370 * configure.in: sinclude ../common/aclocal.m4.
1371 * configure: Regenerated.
1372
736a306c
ILT		 1373Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
1374
1375 * configure: Rebuild after change to aclocal.m4.
1376
295dbbe4
SG		 1377Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
1378
1379 * configure configure.in Makefile.in: Update to new configure
1380 scheme which is more compatible with WinGDB builds.
1381 * configure.in: Improve comment on how to run autoconf.
1382 * configure: Re-run autoconf to get new ../common/aclocal.m4.
1383 * Makefile.in: Use autoconf substitution to install common
1384 makefile fragment.
1385
1386Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
1387
1388 * gencode.c (build_instruction): Use BigEndianCPU instead of
1389 ByteSwapMem.
1390
e1db0d47
MA		 1391Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
1392
1393 * interp.c (sim_monitor): Make output to stdout visible in
1394 wingdb's I/O log window.
1395
2902e8ab
MA		 1396Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
1397
1398 * support.h: Undo previous change to SIGTRAP
1399 and SIGQUIT values.
1400
7e6c297e
ILT		 1401Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
1402
1403 * interp.c (store_word, load_word): New static functions.
1404 (mips16_entry): New static function.
1405 (SignalException): Look for mips16 entry and exit instructions.
1406 (simulate): Use the correct index when setting fpr_state after
1407 doing a pending move.
1408
0049ba7a
MA		 1409Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
1410
1411 * interp.c: Fix byte-swapping code throughout to work on
1412 both little- and big-endian hosts.
1413
2510786b
MA		 1414Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
1415
1416 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
1417 with gdb/config/i386/xm-windows.h.
1418
39bf0ef4
MA		 1419Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
1420
1421 * gencode.c (build_instruction): Work around MSVC++ code gen bug
1422 that messes up arithmetic shifts.
1423
dbeec768
SG		 1424Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
1425
1426 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
1427 SIGTRAP and SIGQUIT for _WIN32.
1428
deffd638
ILT		 1429Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
1430
1431 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
1432 force a 64 bit multiplication.
1433 (build_instruction) [OR]: In mips16 mode, don't do anything if the
1434 destination register is 0, since that is the default mips16 nop
1435 instruction.
1436
aaff8437
ILT		 1437Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
1438
063443cf
ILT		 1439 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
1440 (build_endian_shift): Don't check proc64.
1441 (build_instruction): Always set memval to uword64. Cast op2 to
1442 uword64 when shifting it left in memory instructions. Always use
1443 the same code for stores--don't special case proc64.
1444
aaff8437
ILT		 1445 * gencode.c (build_mips16_operands): Fix base PC value for PC
1446 relative operands.
1447 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
1448 jal instruction.
1449 * interp.c (simJALDELAYSLOT): Define.
1450 (JALDELAYSLOT): Define.
1451 (INDELAYSLOT, INJALDELAYSLOT): Define.
1452 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
1453
280f90e1
AMT		 1454Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
1455
1456 * interp.c (sim_open): add flush_cache as a PMON routine
1457 (sim_monitor): handle flush_cache by ignoring it
1458
aaff8437
ILT		 1459Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
1460
1461 * gencode.c (build_instruction): Use !ByteSwapMem instead of
1462 BigEndianMem.
1463 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
1464 (BigEndianMem): Rename to ByteSwapMem and change sense.
1465 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
1466 BigEndianMem references to !ByteSwapMem.
1467 (set_endianness): New function, with prototype.
1468 (sim_open): Call set_endianness.
1469 (sim_info): Use simBE instead of BigEndianMem.
1470 (xfer_direct_word, xfer_direct_long, swap_direct_word,
1471 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
1472 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
1473 ifdefs, keeping the prototype declaration.
1474 (swap_word): Rewrite correctly.
1475 (ColdReset): Delete references to CONFIG. Delete endianness related
1476 code; moved to set_endianness.
1477
6429b296
JW		 1478Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
1479
1480 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
1481 * interp.c (CHECKHILO): Define away.
1482 (simSIGINT): New macro.
1483 (membank_size): Increase from 1MB to 2MB.
1484 (control_c): New function.
1485 (sim_resume): Rename parameter signal to signal_number. Add local
1486 variable prev. Call signal before and after simulate.
1487 (sim_stop_reason): Add simSIGINT support.
1488 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
1489 functions always.
1490 (sim_warning): Delete call to SignalException. Do call printf_filtered
1491 if logfh is NULL.
1492 (AddressTranslation): Add #ifdef DEBUG around debugging message and
1493 a call to sim_warning.
1494
1495Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
1496
1497 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
1498 16 bit instructions.
1499
831f59a2
ILT		 1500Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
1501
1502 Add support for mips16 (16 bit MIPS implementation):
1503 * gencode.c (inst_type): Add mips16 instruction encoding types.
1504 (GETDATASIZEINSN): Define.
1505 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
1506 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
1507 mtlo.
1508 (MIPS16_DECODE): New table, for mips16 instructions.
1509 (bitmap_val): New static function.
1510 (struct mips16_op): Define.
1511 (mips16_op_table): New table, for mips16 operands.
1512 (build_mips16_operands): New static function.
1513 (process_instructions): If PC is odd, decode a mips16
1514 instruction. Break out instruction handling into new
1515 build_instruction function.
1516 (build_instruction): New static function, broken out of
1517 process_instructions. Check modifiers rather than flags for SHIFT
1518 bit count and m[ft]{hi,lo} direction.
1519 (usage): Pass program name to fprintf.
1520 (main): Remove unused variable this_option_optind. Change
1521 ``*loptarg++'' to ``loptarg++''.
1522 (my_strtoul): Parenthesize && within ||.
350d33b8 1523 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
831f59a2
ILT		 1524 (simulate): If PC is odd, fetch a 16 bit instruction, and
1525 increment PC by 2 rather than 4.
1526 * configure.in: Add case for mips16*-*-*.
1527 * configure: Rebuild.
1528
1529Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
1530
1531 * interp.c: Allow -t to enable tracing in standalone simulator.
1532 Fix garbage output in trace file and error messages.
1533
e3d12c65
DE		 1534Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
1535
1536 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
1537 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
1538 * configure.in: Simplify using macros in ../common/aclocal.m4.
1539 * configure: Regenerated.
1540 * tconfig.in: New file.
1541
1542Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
1543
1544 * interp.c: Fix bugs in 64-bit port.
1545 Use ansi function declarations for msvc compiler.
1546 Initialize and test file pointer in trace code.
1547 Prevent duplicate definition of LAST_EMED_REGNUM.
1548
1549Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
1550
1551 * interp.c (xfer_big_long): Prevent unwanted sign extension.
1552
1553Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
1554
1555 * interp.c (SignalException): Check for explicit terminating
1556 breakpoint value.
1557 * gencode.c: Pass instruction value through SignalException()
1558 calls for Trap, Breakpoint and Syscall.
1559
1560Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
1561
1562 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
1563 only used on those hosts that provide it.
1564 * configure.in: Add sqrt() to list of functions to be checked for.
1565 * config.in: Re-generated.
1566 * configure: Re-generated.
1567
1568Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
1569
1570 * gencode.c (process_instructions): Call build_endian_shift when
1571 expanding STORE RIGHT, to fix swr.
1572 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
1573 clear the high bits.
1574 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
1575 Fix float to int conversions to produce signed values.
1576
cc5201d7
ILT		 1577Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
1578
458e1f58
ILT		 1579 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
1580 (process_instructions): Correct handling of nor instruction.
1581 Correct shift count for 32 bit shift instructions. Correct sign
1582 extension for arithmetic shifts to not shift the number of bits in
1583 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
1584 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
1585 Fix madd.
c05d1721
ILT		 1586 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
1587 It's OK to have a mult follow a mult. What's not OK is to have a
1588 mult follow an mfhi.
458e1f58 1589 (Convert): Comment out incorrect rounding code.
cc5201d7 1590
f24b7b69
JSC		 1591Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
1592
1593 * interp.c (sim_monitor): Improved monitor printf
1594 simulation. Tidied up simulator warnings, and added "--log" option
1595 for directing warning message output.
1596 * gencode.c: Use sim_warning() rather than WARNING macro.
1597
1598Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
1599
1600 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
1601 getopt1.o, rather than on gencode.c. Link objects together.
1602 Don't link against -liberty.
1603 (gencode.o, getopt.o, getopt1.o): New targets.
1604 * gencode.c: Include <ctype.h> and "ansidecl.h".
1605 (AND): Undefine after including "ansidecl.h".
1606 (ULONG_MAX): Define if not defined.
1607 (OP_*): Don't define macros; now defined in opcode/mips.h.
1608 (main): Call my_strtoul rather than strtoul.
1609 (my_strtoul): New static function.
1610
1611Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
1612
1613 * gencode.c (process_instructions): Generate word64 and uword64
1614 instead of `long long' and `unsigned long long' data types.
1615 * interp.c: #include sysdep.h to get signals, and define default
1616 for SIGBUS.
1617 * (Convert): Work around for Visual-C++ compiler bug with type
1618 conversion.
1619 * support.h: Make things compile under Visual-C++ by using
1620 __int64 instead of `long long'. Change many refs to long long
1621 into word64/uword64 typedefs.
1622
a271d1d9
JM		 1623Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
1624
1625 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
1626 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
1627 (docdir): Removed.
1628 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
1629 (AC_PROG_INSTALL): Added.
1630 (AC_PROG_CC): Moved to before configure.host call.
1631 * configure: Rebuilt.
1632
1633Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
1634
1635 * configure.in: Define @SIMCONF@ depending on mips target.
1636 * configure: Rebuild.
1637 * Makefile.in (run): Add @SIMCONF@ to control simulator
1638 construction.
1639 * gencode.c: Change LOADDRMASK to 64bit memory model only.
1640 * interp.c: Remove some debugging, provide more detailed error
1641 messages, update memory accesses to use LOADDRMASK.
1642
4fa134be
ILT		 1643Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
1644
1645 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
1646 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
1647 stamp-h.
1648 * configure: Rebuild.
1649 * config.in: New file, generated by autoheader.
1650 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
1651 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
1652 HAVE_ANINT and HAVE_AINT, as appropriate.
1653 * Makefile.in (run): Use @LIBS@ rather than -lm.
1654 (interp.o): Depend upon config.h.
1655 (Makefile): Just rebuild Makefile.
1656 (clean): Remove stamp-h.
1657 (mostlyclean): Make the same as clean, not as distclean.
1658 (config.h, stamp-h): New targets.
1659
1660Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
1661
1662 * interp.c (ColdReset): Fix boolean test. Make all simulator
1663 globals static.
1664
f7481d45
JSC		 1665Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
1666
1667 * interp.c (xfer_direct_word, xfer_direct_long,
1668 swap_direct_word, swap_direct_long, xfer_big_word,
1669 xfer_big_long, xfer_little_word, xfer_little_long,
1670 swap_word,swap_long): Added.
1671 * interp.c (ColdReset): Provide function indirection to
1672 host<->simulated_target transfer routines.
1673 * interp.c (sim_store_register, sim_fetch_register): Updated to
1674 make use of indirected transfer routines.
1675
1676Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
1677
1678 * gencode.c (process_instructions): Ensure FP ABS instruction
1679 recognised.
1680 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
1681 system call support.
1682
8b554809
JSC		 1683Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
1684
1685 * interp.c (sim_do_command): Complain if callback structure not
1686 initialised.
1687
d0757082
JSC		 1688Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
1689
1690 * interp.c (Convert): Provide round-to-nearest and round-to-zero
1691 support for Sun hosts.
1692 * Makefile.in (gencode): Ensure the host compiler and libraries
1693 used for cross-hosted build.
1694
e871dd18
JSC		 1695Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
1696
1697 * interp.c, gencode.c: Some more (TODO) tidying.
1698
1699Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
1700
1701 * gencode.c, interp.c: Replaced explicit long long references with
1702 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
1703 * support.h (SET64LO, SET64HI): Macros added.
1704
5c59ec43
ILT		 1705Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
1706
1707 * configure: Regenerate with autoconf 2.7.
1708
1709Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
1710
1711 * interp.c (LoadMemory): Enclose text following #endif in /* */.
1712 * support.h: Remove superfluous "1" from #if.
1713 * support.h (CHECKSIM): Remove stray 'a' at end of line.
1714
1715Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
1716
1717 * interp.c (StoreFPR): Control UndefinedResult() call on
1718 WARN_RESULT manifest.
1719
8bae0a0c
JSC		 1720Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
1721
1722 * gencode.c: Tidied instruction decoding, and added FP instruction
1723 support.
1724
1725 * interp.c: Added dineroIII, and BSD profiling support. Also
1726 run-time FP handling.
1727
1728Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
1729
1730 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
1731 gencode.c, interp.c, support.h: created.
GDB Binutils - Deliverables
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