projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
sim: drop common/cconfig.h in favor of a single config.h
[deliverable/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
936df756
MF		 12016-01-09 Mike Frysinger <vapier@gentoo.org>
2
3 * config.in, configure: Regenerate.
4
2e3d4f4d
MF		 52016-01-06 Mike Frysinger <vapier@gentoo.org>
6
7 * interp.c (sim_open): Mark argv const.
8 (sim_create_inferior): Mark argv and env const.
9
9bbf6f91
MF		 102016-01-04 Mike Frysinger <vapier@gentoo.org>
11
12 * configure: Regenerate.
13
77cf2ef5
MF		 142016-01-03 Mike Frysinger <vapier@gentoo.org>
15
16 * interp.c (sim_open): Update sim_parse_args comment.
17
0cb8d851
MF		 182016-01-03 Mike Frysinger <vapier@gentoo.org>
19
20 * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
21 * configure: Regenerate.
22
1ac72f06
MF		 232016-01-02 Mike Frysinger <vapier@gentoo.org>
24
25 * configure.ac (mips_endian): Change LITTLE_ENDIAN to LITTLE.
26 (default_endian): Likewise. Change BIG_ENDIAN to BIG.
27 * configure: Regenerate.
28 * sim-main.h (BigEndianMem): Change BIG_ENDIAN to BFD_ENDIAN_BIG.
29
d47f5b30
MF		 302016-01-02 Mike Frysinger <vapier@gentoo.org>
31
32 * dv-tx3904cpu.c (CPU, SD): Delete.
33
e1211e55
MF		 342015-12-30 Mike Frysinger <vapier@gentoo.org>
35
36 * wrapper.c (mips_reg_store, mips_reg_fetch): Define.
37 (sim_open): Call CPU_REG_FETCH/CPU_REG_STORE.
38 (sim_store_register): Rename to ...
39 (mips_reg_store): ... this. Delete local cpu var.
40 Update sim_io_eprintf calls.
41 (sim_fetch_register): Rename to ...
42 (mips_reg_fetch): ... this. Delete local cpu var.
43 Update sim_io_eprintf calls.
44
5e744ef8
MF		 452015-12-27 Mike Frysinger <vapier@gentoo.org>
46
47 * Makefile.in (SIM_OBJS): Delete sim-hload.o.
48
1b393626
MF		 492015-12-26 Mike Frysinger <vapier@gentoo.org>
50
51 * config.in, configure: Regenerate.
52
26f8bf63
MF		 532015-12-26 Mike Frysinger <vapier@gentoo.org>
54
55 * interp.c (sim_write, sim_read): Delete.
56 (store_word): Delete call to AddressTranslation and set paddr=vaddr.
57 (load_word): Likewise.
58 * micromips.igen (cache): Likewise.
59 * mips.igen (do_ll, do_lld, do_sc, do_scd, do_suxc1_32, do_swc1,
60 do_swxc1, cache, do_load, do_load_left, do_load_right, do_store,
61 do_store_left, do_store_right, do_load_double, do_store_double):
62 Likewise.
63 (do_pref): Delete call to AddressTranslation and stub out Prefetch.
64 (do_prefx): Likewise.
65 * sim-main.c (address_translation, prefetch): Delete.
66 (ifetch32, ifetch16): Delete call to AddressTranslation and set
67 paddr=vaddr.
68 * sim-main.h (Uncached, CachedNoncoherent, CachedCoherent, Cached,
69 address_translation, AddressTranslation, prefetch, Prefetch): Delete.
70 (LoadMemory, StoreMemory): Delete CCA arg.
71
ef04e371
MF		 722015-12-24 Mike Frysinger <vapier@gentoo.org>
73
74 * configure.ac (SIM_SUBTARGET): Drop -DTARGET_TX3904=1.
75 * configure: Regenerated.
76
cb379ede
MF		 772015-12-24 Mike Frysinger <vapier@gentoo.org>
78
79 * sim-main.h (SIM_QUIET_NAN_NEGATED): Move from tconfig.h.
80 * tconfig.h: Delete.
81
26936211
MF		 822015-12-24 Mike Frysinger <vapier@gentoo.org>
83
84 * tconfig.h (SIM_HANDLES_LMA): Delete.
85
84e8e361
MF		 862015-12-24 Mike Frysinger <vapier@gentoo.org>
87
88 * sim-main.h (WITH_WATCHPOINTS): Delete.
89
3cabaf66
MF		 902015-12-24 Mike Frysinger <vapier@gentoo.org>
91
92 * interp.c [SIM_HAVE_FLATMEM] (sim_open): Delete flatmem code.
93
8abe6c66
MF		 942015-12-24 Mike Frysinger <vapier@gentoo.org>
95
96 * tconfig.h (SIM_HAVE_SIMCACHE): Delete.
97
1d19cae7
DV		 982015-12-15 Dominik Vogt <vogt@linux.vnet.ibm.com>
99
100 * micromips.igen (process_isa_mode): Fix left shift of negative
101 value.
102
cdf850e9
MF		 1032015-11-17 Mike Frysinger <vapier@gentoo.org>
104
105 * sim-main.h (WITH_MODULO_MEMORY): Delete.
106
797eee42
MF		 1072015-11-15 Mike Frysinger <vapier@gentoo.org>
108
109 * Makefile.in (SIM_OBJS): Delete sim-reason.o and sim-stop.o.
110
6e4f085c
MF		 1112015-11-14 Mike Frysinger <vapier@gentoo.org>
112
113 * interp.c (sim_close): Rename to ...
114 (mips_sim_close): ... this. Delete calls to sim_module_uninstall and
115 sim_io_shutdown.
116 * sim-main.h (mips_sim_close): Declare.
117 (SIM_CLOSE_HOOK): Define.
118
8e394ffc
AB		 1192015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
120 Ali Lown <ali.lown@imgtec.com>
121
122 * Makefile.in (tmp-micromips): New rule.
123 (tmp-mach-multi): Add support for micromips.
124 * configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
125 that works for both mips64 and micromips64.
126 (mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
127 micromips32.
128 Add build support for micromips.
129 * dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
130 do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
131 do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
132 do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
133 do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
134 do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
135 do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
136 do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
137 Refactored instruction code to use these functions.
138 * dsp2.igen: Refactored instruction code to use the new functions.
139 * interp.c (decode_coproc): Refactored to work with any instruction
140 encoding.
141 (isa_mode): New variable
142 (RSVD_INSTRUCTION): Changed to 0x00000039.
143 * m16.igen (BREAK16): Refactored instruction to use do_break16.
144 (JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
145 * micromips.dc: New file.
146 * micromips.igen: New file.
147 * micromips16.dc: New file.
148 * micromipsdsp.igen: New file.
149 * micromipsrun.c: New file.
150 * mips.igen (do_swc1): Changed to work with any instruction encoding.
151 (do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
152 do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo,
153 do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu,
154 do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu,
155 do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub,
156 do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo,
157 do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc,
158 do_scd, do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu,
159 do_tgeu, do_tlt do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt,
160 do_add_fmt, do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1,
161 do_cvt_d_fmt, do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl,
162 do_cvt_s_pu, do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt,
163 do_luxc1_32, do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b,
164 do_mov_fmt, do_movtf, do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt,
165 do_mtc1b, do_mul_fmt, do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps,
166 do_plu_ps, do_pul_ps, do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt,
167 do_prefx, do_sdc1, do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt,
168 do_swc1, do_swxc1, do_trunc_fmt): New functions, refactored from existing
169 instructions.
170 Refactored instruction code to use these functions.
171 (RSVD): Changed to use new reserved instruction.
172 (loadstore_ea, not_word_value, unpredictable, check_mt_hilo,
173 check_mf_hilo, check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32,
174 do_sdc1, do_suxc1_32, check_fmt_p, check_fpu, do_load_double,
175 do_store_double): Added micromips32 and micromips64 models.
176 Added include for micromips.igen and micromipsdsp.igen
177 Add micromips32 and micromips64 models.
178 (DecodeCoproc): Updated to use new macro definition.
179 * mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
180 do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
181 do_seb, do_seh do_rdhwr, do_wsbh): New functions.
182 Refactored instruction code to use these functions.
183 * sim-main.h (CP0_operation): New enum.
184 (DecodeCoproc): Updated macro.
185 (IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
186 MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16,
187 MICROMIPS_DELAYSLOT_SIZE_32, ISA_MODE_MIPS32 and
188 ISA_MODE_MICROMIPS): New defines.
189 (sim_state): Add isa_mode field.
190
8d0978fb
MF		 1912015-06-23 Mike Frysinger <vapier@gentoo.org>
192
193 * configure: Regenerate.
194
306f4178
MF		 1952015-06-12 Mike Frysinger <vapier@gentoo.org>
196
197 * configure.ac: Change configure.in to configure.ac.
198 * configure: Regenerate.
199
a3487082
MF		 2002015-06-12 Mike Frysinger <vapier@gentoo.org>
201
202 * configure: Regenerate.
203
29bc024d
MF		 2042015-06-12 Mike Frysinger <vapier@gentoo.org>
205
206 * interp.c [TRACE]: Delete.
207 (TRACE): Change to WITH_TRACE_ANY_P.
208 [!WITH_TRACE_ANY_P] (open_trace): Define.
209 (mips_option_handler, open_trace, sim_close, dotrace):
210 Change defined(TRACE) to WITH_TRACE_ANY_P.
211 (sim_open): Delete TRACE ifdef check.
212 * sim-main.c (load_memory): Delete TRACE ifdef check.
213 (store_memory): Likewise.
214 * sim-main.h [WITH_TRACE_ANY_P] (dotrace, tracefh): Protect decls.
215 [!WITH_TRACE_ANY_P] (dotrace): Define.
216
3ebe2863
MF		 2172015-04-18 Mike Frysinger <vapier@gentoo.org>
218
219 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESTART_HOOK): Delete
220 comments.
221
20bca71d
MF		 2222015-04-18 Mike Frysinger <vapier@gentoo.org>
223
224 * sim-main.h (SIM_CPU): Delete.
225
7e83aa92
MF		 2262015-04-18 Mike Frysinger <vapier@gentoo.org>
227
228 * sim-main.h (sim_cia): Delete.
229
034685f9
MF		 2302015-04-17 Mike Frysinger <vapier@gentoo.org>
231
232 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Change CIA_GET to
233 PU_PC_GET.
234 * interp.c (interrupt_event): Change CIA_GET to CPU_PC_GET.
235 (sim_create_inferior): Change CIA_SET to CPU_PC_SET.
236 * m16run.c (sim_engine_run): Change CIA_GET to CPU_PC_GET and
237 CIA_SET to CPU_PC_SET.
238 * sim-main.h (CIA_GET, CIA_SET): Delete.
239
78e9aa70
MF		 2402015-04-15 Mike Frysinger <vapier@gentoo.org>
241
242 * Makefile.in (SIM_OBJS): Delete sim-cpu.o.
243 * sim-main.h (STATE_CPU): Delete.
244
bf12d44e
MF		 2452015-04-13 Mike Frysinger <vapier@gentoo.org>
246
247 * configure: Regenerate.
248
7bebb329
MF		 2492015-04-13 Mike Frysinger <vapier@gentoo.org>
250
251 * Makefile.in (SIM_OBJS): Add sim-cpu.o.
252 * interp.c (mips_pc_get, mips_pc_set): New functions.
253 (sim_open): Declare new local var i. Call sim_cpu_alloc_all.
254 Call CPU_PC_FETCH & CPU_PC_STORE for all cpus.
255 (sim_pc_get): Delete.
256 * sim-main.h (SIM_CPU): Define.
257 (struct sim_state): Change cpu to an array of pointers.
258 (STATE_CPU): Drop &.
259
8ac57fbd
MF		 2602015-04-13 Mike Frysinger <vapier@gentoo.org>
261
262 * interp.c (mips_option_handler, open_trace, sim_close,
263 sim_write, sim_read, sim_store_register, sim_fetch_register,
264 sim_create_inferior, pr_addr, pr_uword64): Convert old style
265 prototypes.
266 (sim_open): Convert old style prototype. Change casts with
267 sim_write to unsigned char *.
268 (fetch_str): Change null to unsigned char, and change cast to
269 unsigned char *.
270 (sim_monitor): Change c & ch to unsigned char. Change cast to
271 unsigned char *.
272
e787f858
MF		 2732015-04-12 Mike Frysinger <vapier@gentoo.org>
274
275 * Makefile.in (SIM_OBJS): Move interp.o to the start of the list.
276
122bbfb5
MF		 2772015-04-06 Mike Frysinger <vapier@gentoo.org>
278
279 * Makefile.in (SIM_OBJS): Delete sim-engine.o.
280
0fe84f3f
MF		 2812015-04-01 Mike Frysinger <vapier@gentoo.org>
282
283 * tconfig.h (SIM_HAVE_PROFILE): Delete.
284
aadc9410
MF		 2852015-03-31 Mike Frysinger <vapier@gentoo.org>
286
287 * config.in, configure: Regenerate.
288
05f53ed6
MF		 2892015-03-24 Mike Frysinger <vapier@gentoo.org>
290
291 * interp.c (sim_pc_get): New function.
292
c0931f26
MF		 2932015-03-24 Mike Frysinger <vapier@gentoo.org>
294
295 * sim-main.h (SIM_HAVE_BIENDIAN): Delete.
296 * tconfig.h (SIM_HAVE_BIENDIAN): Delete.
297
30452bbe
MF		 2982015-03-24 Mike Frysinger <vapier@gentoo.org>
299
300 * configure: Regenerate.
301
64dd13df
MF		 3022015-03-23 Mike Frysinger <vapier@gentoo.org>
303
304 * configure: Regenerate.
305
49cd1634
MF		 3062015-03-23 Mike Frysinger <vapier@gentoo.org>
307
308 * configure: Regenerate.
309 * configure.ac (mips_extra_objs): Delete.
310 * Makefile.in (MIPS_EXTRA_OBJS): Delete.
311 (SIM_OBJS): Delete MIPS_EXTRA_OBJS.
312
3649cb06
MF		 3132015-03-23 Mike Frysinger <vapier@gentoo.org>
314
315 * configure: Regenerate.
316 * configure.ac: Delete sim_hw checks for dv-sockser.
317
ae7d0cac
MF		 3182015-03-16 Mike Frysinger <vapier@gentoo.org>
319
320 * config.in, configure: Regenerate.
321 * tconfig.in: Rename file ...
322 * tconfig.h: ... here.
323
8406bb59
MF		 3242015-03-15 Mike Frysinger <vapier@gentoo.org>
325
326 * tconfig.in: Delete includes.
327 [HAVE_DV_SOCKSER]: Delete.
328
465fb143
MF		 3292015-03-14 Mike Frysinger <vapier@gentoo.org>
330
331 * Makefile.in (SIM_RUN_OBJS): Delete.
332
5cddc23a
MF		 3332015-03-14 Mike Frysinger <vapier@gentoo.org>
334
335 * configure.ac (AC_CHECK_HEADERS): Delete.
336 * aclocal.m4, configure: Regenerate.
337
2974be62
AM		 3382014-08-19 Alan Modra <amodra@gmail.com>
339
340 * configure: Regenerate.
341
faa743bb
RM		 3422014-08-15 Roland McGrath <mcgrathr@google.com>
343
344 * configure: Regenerate.
345 * config.in: Regenerate.
346
1a8a700e
MF		 3472014-03-04 Mike Frysinger <vapier@gentoo.org>
348
349 * configure: Regenerate.
350
bf3d9781
AM		 3512013-09-23 Alan Modra <amodra@gmail.com>
352
353 * configure: Regenerate.
354
31e6ad7d
MF		 3552013-06-03 Mike Frysinger <vapier@gentoo.org>
356
357 * aclocal.m4, configure: Regenerate.
358
d3685d60
TT		 3592013-05-10 Freddie Chopin <freddie_chopin@op.pl>
360
361 * configure: Rebuild.
362
1517bd27
MF		 3632013-03-26 Mike Frysinger <vapier@gentoo.org>
364
365 * configure: Regenerate.
366
3be31516
JS		 3672013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
368
369 * configure.ac: Address use of dv-sockser.o.
370 * tconfig.in: Conditionalize use of dv_sockser_install.
371 * configure: Regenerated.
372 * config.in: Regenerated.
373
37cb8f8e
SE		 3742012-10-04 Chao-ying Fu <fu@mips.com>
375 Steve Ellcey <sellcey@mips.com>
376
377 * mips/mips3264r2.igen (rdhwr): New.
378
87c8644f
JS		 3792012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
380
381 * configure.ac: Always link against dv-sockser.o.
382 * configure: Regenerate.
383
5f3ef9d0
JB		 3842012-06-15 Joel Brobecker <brobecker@adacore.com>
385
386 * config.in, configure: Regenerate.
387
a6ff997c
NC		 3882012-05-18 Nick Clifton <nickc@redhat.com>
389
390 PR 14072
391 * interp.c: Include config.h before system header files.
392
2232061b
MF		 3932012-03-24 Mike Frysinger <vapier@gentoo.org>
394
395 * aclocal.m4, config.in, configure: Regenerate.
396
db2e4d67
MF		 3972011-12-03 Mike Frysinger <vapier@gentoo.org>
398
399 * aclocal.m4: New file.
400 * configure: Regenerate.
401
4399a56b
MF		 4022011-10-19 Mike Frysinger <vapier@gentoo.org>
403
404 * configure: Regenerate after common/acinclude.m4 update.
405
9c082ca8
MF		 4062011-10-17 Mike Frysinger <vapier@gentoo.org>
407
408 * configure.ac: Change include to common/acinclude.m4.
409
6ffe910a
MF		 4102011-10-17 Mike Frysinger <vapier@gentoo.org>
411
412 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
413 call. Replace common.m4 include with SIM_AC_COMMON.
414 * configure: Regenerate.
415
31b28250
HPN		 4162011-07-08 Hans-Peter Nilsson <hp@axis.com>
417
3faa01e3
HPN		 418 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
419 $(SIM_EXTRA_DEPS).
420 (tmp-mach-multi): Exit early when igen fails.
31b28250 421
2419798b
MF		 4222011-07-05 Mike Frysinger <vapier@gentoo.org>
423
424 * interp.c (sim_do_command): Delete.
425
d79fe0d6
MF		 4262011-02-14 Mike Frysinger <vapier@gentoo.org>
427
428 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
429 (tx3904sio_fifo_reset): Likewise.
430 * interp.c (sim_monitor): Likewise.
431
5558e7e6
MF		 4322010-04-14 Mike Frysinger <vapier@gentoo.org>
433
434 * interp.c (sim_write): Add const to buffer arg.
435
35aafff4
JB		 4362010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
437
438 * interp.c: Don't include sysdep.h
439
3725885a
RW		 4402010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
441
442 * configure: Regenerate.
443
d6416cdc
RW		 4442009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
445
81ecdfbb
RW		 446 * config.in: Regenerate.
447 * configure: Likewise.
448
d6416cdc
RW		 449 * configure: Regenerate.
450
b5bd9624
HPN		 4512008-07-11 Hans-Peter Nilsson <hp@axis.com>
452
453 * configure: Regenerate to track ../common/common.m4 changes.
454 * config.in: Ditto.
455
6efef468 4562008-06-06 Vladimir Prus <vladimir@codesourcery.com>
72f4393d
L		 457 Daniel Jacobowitz <dan@codesourcery.com>
458 Joseph Myers <joseph@codesourcery.com>
6efef468
JM		 459
460 * configure: Regenerate.
461
60dc88db
RS		 4622007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
463
464 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
465 that unconditionally allows fmt_ps.
466 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
467 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
468 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
469 filter from 64,f to 32,f.
470 (PREFX): Change filter from 64 to 32.
471 (LDXC1, LUXC1): Provide separate mips32r2 implementations
472 that use do_load_double instead of do_load. Make both LUXC1
473 versions unpredictable if SizeFGR () != 64.
474 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
475 instead of do_store. Remove unused variable. Make both SUXC1
476 versions unpredictable if SizeFGR () != 64.
477
599ca73e
RS		 4782007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
479
480 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
481 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
482 shifts for that case.
483
2525df03
NC		 4842007-09-04 Nick Clifton <nickc@redhat.com>
485
486 * interp.c (options enum): Add OPTION_INFO_MEMORY.
487 (display_mem_info): New static variable.
488 (mips_option_handler): Handle OPTION_INFO_MEMORY.
489 (mips_options): Add info-memory and memory-info.
490 (sim_open): After processing the command line and board
491 specification, check display_mem_info. If it is set then
492 call the real handler for the --memory-info command line
493 switch.
494
35ee6e1e
JB		 4952007-08-24 Joel Brobecker <brobecker@adacore.com>
496
497 * configure.ac: Change license of multi-run.c to GPL version 3.
498 * configure: Regenerate.
499
d5fb0879
RS		 5002007-06-28 Richard Sandiford <richard@codesourcery.com>
501
502 * configure.ac, configure: Revert last patch.
503
2a2ce21b
RS		 5042007-06-26 Richard Sandiford <richard@codesourcery.com>
505
506 * configure.ac (sim_mipsisa3264_configs): New variable.
507 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
508 every configuration support all four targets, using the triplet to
509 determine the default.
510 * configure: Regenerate.
511
efdcccc9
RS		 5122007-06-25 Richard Sandiford <richard@codesourcery.com>
513
0a7692b2 514 * Makefile.in (m16run.o): New rule.
efdcccc9 515
f532a356
TS		 5162007-05-15 Thiemo Seufer <ths@mips.com>
517
518 * mips3264r2.igen (DSHD): Fix compile warning.
519
bfe9c90b
TS		 5202007-05-14 Thiemo Seufer <ths@mips.com>
521
522 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
523 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
524 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
525 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
526 for mips32r2.
527
53f4826b
TS		 5282007-03-01 Thiemo Seufer <ths@mips.com>
529
530 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
531 and mips64.
532
8bf3ddc8
TS		 5332007-02-20 Thiemo Seufer <ths@mips.com>
534
535 * dsp.igen: Update copyright notice.
536 * dsp2.igen: Fix copyright notice.
537
8b082fb1 5382007-02-20 Thiemo Seufer <ths@mips.com>
72f4393d 539 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 540
541 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
542 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
543 Add dsp2 to sim_igen_machine.
544 * configure: Regenerate.
545 * dsp.igen (do_ph_op): Add MUL support when op = 2.
546 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
547 (mulq_rs.ph): Use do_ph_mulq.
548 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
549 * mips.igen: Add dsp2 model and include dsp2.igen.
550 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
551 for *mips32r2, *mips64r2, *dsp.
552 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
553 for *mips32r2, *mips64r2, *dsp2.
554 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
555
b1004875 5562007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 557 Nigel Stephens <nigel@mips.com>
b1004875
TS		 558
559 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
560 jumps with hazard barrier.
561
f8df4c77 5622007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 563 Nigel Stephens <nigel@mips.com>
f8df4c77
TS		 564
565 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
566 after each call to sim_io_write.
567
b1004875 5682007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 569 Nigel Stephens <nigel@mips.com>
b1004875
TS		 570
571 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
572 supported by this simulator.
07802d98
TS		 573 (decode_coproc): Recognise additional CP0 Config registers
574 correctly.
575
14fb6c5a 5762007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d
L		 577 Nigel Stephens <nigel@mips.com>
578 David Ung <davidu@mips.com>
14fb6c5a
TS		 579
580 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
581 uninterpreted formats. If fmt is one of the uninterpreted types
582 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
583 fmt_word, and fmt_uninterpreted_64 like fmt_long.
584 (store_fpr): When writing an invalid odd register, set the
585 matching even register to fmt_unknown, not the following register.
586 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
587 the the memory window at offset 0 set by --memory-size command
588 line option.
589 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
590 point register.
591 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
592 register.
593 (sim_monitor): When returning the memory size to the MIPS
594 application, use the value in STATE_MEM_SIZE, not an arbitrary
595 hardcoded value.
596 (cop_lw): Don' mess around with FPR_STATE, just pass
597 fmt_uninterpreted_32 to StoreFPR.
598 (cop_sw): Similarly.
599 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
600 (cop_sd): Similarly.
601 * mips.igen (not_word_value): Single version for mips32, mips64
602 and mips16.
603
c8847145 6042007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 605 Nigel Stephens <nigel@mips.com>
c8847145
TS		 606
607 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
608 MBytes.
609
4b5d35ee
TS		 6102007-02-17 Thiemo Seufer <ths@mips.com>
611
612 * configure.ac (mips*-sde-elf*): Move in front of generic machine
613 configuration.
614 * configure: Regenerate.
615
3669427c
TS		 6162007-02-17 Thiemo Seufer <ths@mips.com>
617
618 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
619 Add mdmx to sim_igen_machine.
620 (mipsisa64*-*-*): Likewise. Remove dsp.
621 (mipsisa32*-*-*): Remove dsp.
622 * configure: Regenerate.
623
109ad085
TS		 6242007-02-13 Thiemo Seufer <ths@mips.com>
625
626 * configure.ac: Add mips*-sde-elf* target.
627 * configure: Regenerate.
628
921d7ad3
HPN		 6292006-12-21 Hans-Peter Nilsson <hp@axis.com>
630
631 * acconfig.h: Remove.
632 * config.in, configure: Regenerate.
633
02f97da7
TS		 6342006-11-07 Thiemo Seufer <ths@mips.com>
635
636 * dsp.igen (do_w_op): Fix compiler warning.
637
2d2733fc 6382006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 639 David Ung <davidu@mips.com>
2d2733fc
TS		 640
641 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
642 sim_igen_machine.
643 * configure: Regenerate.
644 * mips.igen (model): Add smartmips.
645 (MADDU): Increment ACX if carry.
646 (do_mult): Clear ACX.
647 (ROR,RORV): Add smartmips.
72f4393d 648 (include): Include smartmips.igen.
2d2733fc
TS		 649 * sim-main.h (ACX): Set to REGISTERS[89].
650 * smartmips.igen: New file.
651
d85c3a10 6522006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 653 David Ung <davidu@mips.com>
d85c3a10
TS		 654
655 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
656 mips3264r2.igen. Add missing dependency rules.
657 * m16e.igen: Support for mips16e save/restore instructions.
658
e85e3205
RE		 6592006-06-13 Richard Earnshaw <rearnsha@arm.com>
660
661 * configure: Regenerated.
662
2f0122dc
DJ		 6632006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
664
665 * configure: Regenerated.
666
20e95c23
DJ		 6672006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
668
669 * configure: Regenerated.
670
69088b17
CF		 6712006-05-15 Chao-ying Fu <fu@mips.com>
672
673 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
674
0275de4e
NC		 6752006-04-18 Nick Clifton <nickc@redhat.com>
676
677 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
678 statement.
679
b3a3ffef
HPN		 6802006-03-29 Hans-Peter Nilsson <hp@axis.com>
681
682 * configure: Regenerate.
683
40a5538e
CF		 6842005-12-14 Chao-ying Fu <fu@mips.com>
685
686 * Makefile.in (SIM_OBJS): Add dsp.o.
687 (dsp.o): New dependency.
688 (IGEN_INCLUDE): Add dsp.igen.
689 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
690 mipsisa64*-*-*): Add dsp to sim_igen_machine.
691 * configure: Regenerate.
692 * mips.igen: Add dsp model and include dsp.igen.
693 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
694 because these instructions are extended in DSP ASE.
695 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
696 adding 6 DSP accumulator registers and 1 DSP control register.
697 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
698 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
699 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
700 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
701 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
702 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
703 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
704 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
705 DSPCR_CCOND_SMASK): New define.
706 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
707 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
708
21d14896
ILT		 7092005-07-08 Ian Lance Taylor <ian@airs.com>
710
711 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
712
b16d63da 7132005-06-16 David Ung <davidu@mips.com>
72f4393d
L		 714 Nigel Stephens <nigel@mips.com>
715
716 * mips.igen: New mips16e model and include m16e.igen.
717 (check_u64): Add mips16e tag.
718 * m16e.igen: New file for MIPS16e instructions.
719 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
720 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
721 models.
722 * configure: Regenerate.
b16d63da 723
e70cb6cd 7242005-05-26 David Ung <davidu@mips.com>
72f4393d 725
e70cb6cd
CD		 726 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
727 tags to all instructions which are applicable to the new ISAs.
728 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
729 vr.igen.
730 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
72f4393d 731 instructions.
e70cb6cd
CD		 732 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
733 to mips.igen.
734 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
735 * configure: Regenerate.
72f4393d 736
2b193c4a
MK		 7372005-03-23 Mark Kettenis <kettenis@gnu.org>
738
739 * configure: Regenerate.
740
35695fd6
AC		 7412005-01-14 Andrew Cagney <cagney@gnu.org>
742
743 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
744 explicit call to AC_CONFIG_HEADER.
745 * configure: Regenerate.
746
f0569246
AC		 7472005-01-12 Andrew Cagney <cagney@gnu.org>
748
749 * configure.ac: Update to use ../common/common.m4.
750 * configure: Re-generate.
751
38f48d72
AC		 7522005-01-11 Andrew Cagney <cagney@localhost.localdomain>
753
754 * configure: Regenerated to track ../common/aclocal.m4 changes.
755
b7026657
AC		 7562005-01-07 Andrew Cagney <cagney@gnu.org>
757
758 * configure.ac: Rename configure.in, require autoconf 2.59.
759 * configure: Re-generate.
760
379832de
HPN		 7612004-12-08 Hans-Peter Nilsson <hp@axis.com>
762
763 * configure: Regenerate for ../common/aclocal.m4 update.
764
cd62154c 7652004-09-24 Monika Chaddha <monika@acmet.com>
72f4393d 766
cd62154c
AC		 767 Committed by Andrew Cagney.
768 * m16.igen (CMP, CMPI): Fix assembler.
769
e5da76ec
CD		 7702004-08-18 Chris Demetriou <cgd@broadcom.com>
771
772 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
773 * configure: Regenerate.
774
139181c8
CD		 7752004-06-25 Chris Demetriou <cgd@broadcom.com>
776
777 * configure.in (sim_m16_machine): Include mipsIII.
778 * configure: Regenerate.
779
1a27f959
CD		 7802004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
781
72f4393d 782 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
1a27f959
CD		 783 from COP0_BADVADDR.
784 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
785
5dbb7b5a
CD		 7862004-04-10 Chris Demetriou <cgd@broadcom.com>
787
788 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
789
14234056
CD		 7902004-04-09 Chris Demetriou <cgd@broadcom.com>
791
792 * mips.igen (check_fmt): Remove.
793 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
794 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
795 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
796 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
797 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
798 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
799 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
800 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
801 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
802 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
803
c6f9085c
CD		 8042004-04-09 Chris Demetriou <cgd@broadcom.com>
805
806 * sb1.igen (check_sbx): New function.
807 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
808
11d66e66 8092004-03-29 Chris Demetriou <cgd@broadcom.com>
0e1b7197
RS		 810 Richard Sandiford <rsandifo@redhat.com>
811
812 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
813 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
814 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
815 separate implementations for mipsIV and mipsV. Use new macros to
816 determine whether the restrictions apply.
817
b3208fb8
CD		 8182004-01-19 Chris Demetriou <cgd@broadcom.com>
819
820 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
821 (check_mult_hilo): Improve comments.
822 (check_div_hilo): Likewise. Also, fork off a new version
823 to handle mips32/mips64 (since there are no hazards to check
824 in MIPS32/MIPS64).
825
9a1d84fb
CD		 8262003-06-17 Richard Sandiford <rsandifo@redhat.com>
827
828 * mips.igen (do_dmultx): Fix check for negative operands.
829
ae451ac6
ILT		 8302003-05-16 Ian Lance Taylor <ian@airs.com>
831
832 * Makefile.in (SHELL): Make sure this is defined.
833 (various): Use $(SHELL) whenever we invoke move-if-change.
834
dd69d292
CD		 8352003-05-03 Chris Demetriou <cgd@broadcom.com>
836
837 * cp1.c: Tweak attribution slightly.
838 * cp1.h: Likewise.
839 * mdmx.c: Likewise.
840 * mdmx.igen: Likewise.
841 * mips3d.igen: Likewise.
842 * sb1.igen: Likewise.
843
bcd0068e
CD		 8442003-04-15 Richard Sandiford <rsandifo@redhat.com>
845
846 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
847 unsigned operands.
848
6b4a8935
AC		 8492003-02-27 Andrew Cagney <cagney@redhat.com>
850
601da316
AC		 851 * interp.c (sim_open): Rename _bfd to bfd.
852 (sim_create_inferior): Ditto.
6b4a8935 853
d29e330f
CD		 8542003-01-14 Chris Demetriou <cgd@broadcom.com>
855
856 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
857
a2353a08
CD		 8582003-01-14 Chris Demetriou <cgd@broadcom.com>
859
860 * mips.igen (EI, DI): Remove.
861
80551777
CD		 8622003-01-05 Richard Sandiford <rsandifo@redhat.com>
863
864 * Makefile.in (tmp-run-multi): Fix mips16 filter.
865
4c54fc26
CD		 8662003-01-04 Richard Sandiford <rsandifo@redhat.com>
867 Andrew Cagney <ac131313@redhat.com>
868 Gavin Romig-Koch <gavin@redhat.com>
869 Graydon Hoare <graydon@redhat.com>
870 Aldy Hernandez <aldyh@redhat.com>
871 Dave Brolley <brolley@redhat.com>
872 Chris Demetriou <cgd@broadcom.com>
873
874 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
875 (sim_mach_default): New variable.
876 (mips64vr-*-*, mips64vrel-*-*): New configurations.
877 Add a new simulator generator, MULTI.
878 * configure: Regenerate.
879 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
880 (multi-run.o): New dependency.
881 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
882 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
883 (tmp-multi): Combine them.
884 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
885 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
886 (distclean-extra): New rule.
887 * sim-main.h: Include bfd.h.
888 (MIPS_MACH): New macro.
889 * mips.igen (vr4120, vr5400, vr5500): New models.
890 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
891 * vr.igen: Replace with new version.
892
e6c674b8
CD		 8932003-01-04 Chris Demetriou <cgd@broadcom.com>
894
895 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
896 * configure: Regenerate.
897
28f50ac8
CD		 8982002-12-31 Chris Demetriou <cgd@broadcom.com>
899
900 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
901 * mips.igen: Remove all invocations of check_branch_bug and
902 mark_branch_bug.
903
5071ffe6
CD		 9042002-12-16 Chris Demetriou <cgd@broadcom.com>
905
72f4393d 906 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
5071ffe6 907
06e7837e
CD		 9082002-07-30 Chris Demetriou <cgd@broadcom.com>
909
910 * mips.igen (do_load_double, do_store_double): New functions.
911 (LDC1, SDC1): Rename to...
912 (LDC1b, SDC1b): respectively.
913 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
914
2265c243
MS		 9152002-07-29 Michael Snyder <msnyder@redhat.com>
916
917 * cp1.c (fp_recip2): Modify initialization expression so that
918 GCC will recognize it as constant.
919
a2f8b4f3
CD		 9202002-06-18 Chris Demetriou <cgd@broadcom.com>
921
922 * mdmx.c (SD_): Delete.
923 (Unpredictable): Re-define, for now, to directly invoke
924 unpredictable_action().
925 (mdmx_acc_op): Fix error in .ob immediate handling.
926
b4b6c939
AC		 9272002-06-18 Andrew Cagney <cagney@redhat.com>
928
929 * interp.c (sim_firmware_command): Initialize `address'.
930
c8cca39f
AC		 9312002-06-16 Andrew Cagney <ac131313@redhat.com>
932
933 * configure: Regenerated to track ../common/aclocal.m4 changes.
934
e7e81181 9352002-06-14 Chris Demetriou <cgd@broadcom.com>
72f4393d 936 Ed Satterthwaite <ehs@broadcom.com>
e7e81181
CD		 937
938 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
939 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
940 * mips.igen: Include mips3d.igen.
941 (mips3d): New model name for MIPS-3D ASE instructions.
942 (CVT.W.fmt): Don't use this instruction for word (source) format
72f4393d 943 instructions.
e7e81181
CD		 944 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
945 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
946 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
947 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
948 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
949 (RSquareRoot1, RSquareRoot2): New macros.
950 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
951 (fp_rsqrt2): New functions.
952 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
953 * configure: Regenerate.
954
3a2b820e 9552002-06-13 Chris Demetriou <cgd@broadcom.com>
72f4393d 956 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 957
958 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
959 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
960 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
961 (convert): Note that this function is not used for paired-single
962 format conversions.
963 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
964 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
965 (check_fmt_p): Enable paired-single support.
966 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
967 (PUU.PS): New instructions.
968 (CVT.S.fmt): Don't use this instruction for paired-single format
969 destinations.
970 * sim-main.h (FP_formats): New value 'fmt_ps.'
971 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
972 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
973
d18ea9c2
CD		 9742002-06-12 Chris Demetriou <cgd@broadcom.com>
975
976 * mips.igen: Fix formatting of function calls in
977 many FP operations.
978
95fd5cee
CD		 9792002-06-12 Chris Demetriou <cgd@broadcom.com>
980
981 * mips.igen (MOVN, MOVZ): Trace result.
982 (TNEI): Print "tnei" as the opcode name in traces.
983 (CEIL.W): Add disassembly string for traces.
984 (RSQRT.fmt): Make location of disassembly string consistent
985 with other instructions.
986
4f0d55ae
CD		 9872002-06-12 Chris Demetriou <cgd@broadcom.com>
988
989 * mips.igen (X): Delete unused function.
990
3c25f8c7
AC		 9912002-06-08 Andrew Cagney <cagney@redhat.com>
992
993 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
994
f3c08b7e 9952002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 996 Ed Satterthwaite <ehs@broadcom.com>
f3c08b7e
CD		 997
998 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
999 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
1000 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
1001 (fp_nmsub): New prototypes.
1002 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
1003 (NegMultiplySub): New defines.
1004 * mips.igen (RSQRT.fmt): Use RSquareRoot().
1005 (MADD.D, MADD.S): Replace with...
1006 (MADD.fmt): New instruction.
1007 (MSUB.D, MSUB.S): Replace with...
1008 (MSUB.fmt): New instruction.
1009 (NMADD.D, NMADD.S): Replace with...
1010 (NMADD.fmt): New instruction.
1011 (NMSUB.D, MSUB.S): Replace with...
1012 (NMSUB.fmt): New instruction.
1013
52714ff9 10142002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1015 Ed Satterthwaite <ehs@broadcom.com>
52714ff9
CD		 1016
1017 * cp1.c: Fix more comment spelling and formatting.
1018 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
1019 (denorm_mode): New function.
1020 (fpu_unary, fpu_binary): Round results after operation, collect
1021 status from rounding operations, and update the FCSR.
1022 (convert): Collect status from integer conversions and rounding
1023 operations, and update the FCSR. Adjust NaN values that result
1024 from conversions. Convert to use sim_io_eprintf rather than
1025 fprintf, and remove some debugging code.
1026 * cp1.h (fenr_FS): New define.
1027
577d8c4b
CD		 10282002-06-07 Chris Demetriou <cgd@broadcom.com>
1029
1030 * cp1.c (convert): Remove unusable debugging code, and move MIPS
1031 rounding mode to sim FP rounding mode flag conversion code into...
1032 (rounding_mode): New function.
1033
196496ed
CD		 10342002-06-07 Chris Demetriou <cgd@broadcom.com>
1035
1036 * cp1.c: Clean up formatting of a few comments.
1037 (value_fpr): Reformat switch statement.
1038
cfe9ea23 10392002-06-06 Chris Demetriou <cgd@broadcom.com>
72f4393d 1040 Ed Satterthwaite <ehs@broadcom.com>
cfe9ea23
CD		 1041
1042 * cp1.h: New file.
1043 * sim-main.h: Include cp1.h.
1044 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
1045 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
1046 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
1047 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
1048 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
1049 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
1050 * cp1.c: Don't include sim-fpu.h; already included by
1051 sim-main.h. Clean up formatting of some comments.
1052 (NaN, Equal, Less): Remove.
1053 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
1054 (fp_cmp): New functions.
1055 * mips.igen (do_c_cond_fmt): Remove.
1056 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
1057 Compare. Add result tracing.
1058 (CxC1): Remove, replace with...
1059 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
1060 (DMxC1): Remove, replace with...
1061 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
72f4393d
L		 1062 (MxC1): Remove, replace with...
1063 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
cfe9ea23 1064
ee7254b0
CD		 10652002-06-04 Chris Demetriou <cgd@broadcom.com>
1066
1067 * sim-main.h (FGRIDX): Remove, replace all uses with...
1068 (FGR_BASE): New macro.
1069 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
1070 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
1071 (NR_FGR, FGR): Likewise.
1072 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
1073 * mips.igen: Likewise.
1074
d3eb724f
CD		 10752002-06-04 Chris Demetriou <cgd@broadcom.com>
1076
1077 * cp1.c: Add an FSF Copyright notice to this file.
1078
ba46ddd0 10792002-06-04 Chris Demetriou <cgd@broadcom.com>
72f4393d 1080 Ed Satterthwaite <ehs@broadcom.com>
ba46ddd0
CD		 1081
1082 * cp1.c (Infinity): Remove.
1083 * sim-main.h (Infinity): Likewise.
1084
1085 * cp1.c (fp_unary, fp_binary): New functions.
1086 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
1087 (fp_sqrt): New functions, implemented in terms of the above.
1088 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1089 (Recip, SquareRoot): Remove (replaced by functions above).
1090 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
1091 (fp_recip, fp_sqrt): New prototypes.
1092 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1093 (Recip, SquareRoot): Replace prototypes with #defines which
1094 invoke the functions above.
72f4393d 1095
18d8a52d
CD		 10962002-06-03 Chris Demetriou <cgd@broadcom.com>
1097
1098 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
1099 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
1100 file, remove PARAMS from prototypes.
1101 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
1102 simulator state arguments.
1103 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
1104 pass simulator state arguments.
1105 * cp1.c (SD): Redefine as CPU_STATE(cpu).
1106 (store_fpr, convert): Remove 'sd' argument.
1107 (value_fpr): Likewise. Convert to use 'SD' instead.
1108
0f154cbd
CD		 11092002-06-03 Chris Demetriou <cgd@broadcom.com>
1110
1111 * cp1.c (Min, Max): Remove #if 0'd functions.
1112 * sim-main.h (Min, Max): Remove.
1113
e80fc152
CD		 11142002-06-03 Chris Demetriou <cgd@broadcom.com>
1115
1116 * cp1.c: fix formatting of switch case and default labels.
1117 * interp.c: Likewise.
1118 * sim-main.c: Likewise.
1119
bad673a9
CD		 11202002-06-03 Chris Demetriou <cgd@broadcom.com>
1121
1122 * cp1.c: Clean up comments which describe FP formats.
1123 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
1124
7cbea089 11252002-06-03 Chris Demetriou <cgd@broadcom.com>
72f4393d 1126 Ed Satterthwaite <ehs@broadcom.com>
7cbea089
CD		 1127
1128 * configure.in (mipsisa64sb1*-*-*): New target for supporting
1129 Broadcom SiByte SB-1 processor configurations.
1130 * configure: Regenerate.
1131 * sb1.igen: New file.
1132 * mips.igen: Include sb1.igen.
1133 (sb1): New model.
1134 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
1135 * mdmx.igen: Add "sb1" model to all appropriate functions and
1136 instructions.
1137 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
1138 (ob_func, ob_acc): Reference the above.
1139 (qh_acc): Adjust to keep the same size as ob_acc.
1140 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
1141 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
1142
909daa82
CD		 11432002-06-03 Chris Demetriou <cgd@broadcom.com>
1144
1145 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
1146
f4f1b9f1 11472002-06-02 Chris Demetriou <cgd@broadcom.com>
72f4393d 1148 Ed Satterthwaite <ehs@broadcom.com>
f4f1b9f1
CD		 1149
1150 * mips.igen (mdmx): New (pseudo-)model.
1151 * mdmx.c, mdmx.igen: New files.
1152 * Makefile.in (SIM_OBJS): Add mdmx.o.
1153 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
1154 New typedefs.
1155 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
1156 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
1157 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
1158 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
1159 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
1160 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
1161 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
1162 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
1163 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
1164 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
1165 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
1166 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
1167 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
1168 (qh_fmtsel): New macros.
1169 (_sim_cpu): New member "acc".
1170 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
1171 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
1172
5accf1ff
CD		 11732002-05-01 Chris Demetriou <cgd@broadcom.com>
1174
1175 * interp.c: Use 'deprecated' rather than 'depreciated.'
1176 * sim-main.h: Likewise.
1177
402586aa
CD		 11782002-05-01 Chris Demetriou <cgd@broadcom.com>
1179
1180 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
1181 which wouldn't compile anyway.
1182 * sim-main.h (unpredictable_action): New function prototype.
1183 (Unpredictable): Define to call igen function unpredictable().
1184 (NotWordValue): New macro to call igen function not_word_value().
1185 (UndefinedResult): Remove.
1186 * interp.c (undefined_result): Remove.
1187 (unpredictable_action): New function.
1188 * mips.igen (not_word_value, unpredictable): New functions.
1189 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
1190 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
1191 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
1192 NotWordValue() to check for unpredictable inputs, then
1193 Unpredictable() to handle them.
1194
c9b9995a
CD		 11952002-02-24 Chris Demetriou <cgd@broadcom.com>
1196
1197 * mips.igen: Fix formatting of calls to Unpredictable().
1198
e1015982
AC		 11992002-04-20 Andrew Cagney <ac131313@redhat.com>
1200
1201 * interp.c (sim_open): Revert previous change.
1202
b882a66b
AO		 12032002-04-18 Alexandre Oliva <aoliva@redhat.com>
1204
1205 * interp.c (sim_open): Disable chunk of code that wrote code in
1206 vector table entries.
1207
c429b7dd
CD		 12082002-03-19 Chris Demetriou <cgd@broadcom.com>
1209
1210 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
1211 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
1212 unused definitions.
1213
37d146fa
CD		 12142002-03-19 Chris Demetriou <cgd@broadcom.com>
1215
1216 * cp1.c: Fix many formatting issues.
1217
07892c0b
CD		 12182002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1219
1220 * cp1.c (fpu_format_name): New function to replace...
1221 (DOFMT): This. Delete, and update all callers.
1222 (fpu_rounding_mode_name): New function to replace...
1223 (RMMODE): This. Delete, and update all callers.
1224
487f79b7
CD		 12252002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1226
1227 * interp.c: Move FPU support routines from here to...
1228 * cp1.c: Here. New file.
1229 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
1230 (cp1.o): New target.
1231
1e799e28
CD		 12322002-03-12 Chris Demetriou <cgd@broadcom.com>
1233
1234 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
1235 * mips.igen (mips32, mips64): New models, add to all instructions
1236 and functions as appropriate.
1237 (loadstore_ea, check_u64): New variant for model mips64.
1238 (check_fmt_p): New variant for models mipsV and mips64, remove
1239 mipsV model marking fro other variant.
1240 (SLL) Rename to...
1241 (SLLa) this.
1242 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
1243 for mips32 and mips64.
1244 (DCLO, DCLZ): New instructions for mips64.
1245
82f728db
CD		 12462002-03-07 Chris Demetriou <cgd@broadcom.com>
1247
1248 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
1249 immediate or code as a hex value with the "%#lx" format.
1250 (ANDI): Likewise, and fix printed instruction name.
1251
b96e7ef1
CD		 12522002-03-05 Chris Demetriou <cgd@broadcom.com>
1253
1254 * sim-main.h (UndefinedResult, Unpredictable): New macros
1255 which currently do nothing.
1256
d35d4f70
CD		 12572002-03-05 Chris Demetriou <cgd@broadcom.com>
1258
1259 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
1260 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
1261 (status_CU3): New definitions.
1262
1263 * sim-main.h (ExceptionCause): Add new values for MIPS32
1264 and MIPS64: MDMX, MCheck, CacheErr. Update comments
1265 for DebugBreakPoint and NMIReset to note their status in
1266 MIPS32 and MIPS64.
1267 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
1268 (SignalExceptionCacheErr): New exception macros.
1269
3ad6f714
CD		 12702002-03-05 Chris Demetriou <cgd@broadcom.com>
1271
1272 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
1273 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
1274 is always enabled.
1275 (SignalExceptionCoProcessorUnusable): Take as argument the
1276 unusable coprocessor number.
1277
86b77b47
CD		 12782002-03-05 Chris Demetriou <cgd@broadcom.com>
1279
1280 * mips.igen: Fix formatting of all SignalException calls.
1281
97a88e93 12822002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 1283
1284 * sim-main.h (SIGNEXTEND): Remove.
1285
97a88e93 12862002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 1287
1288 * mips.igen: Remove gencode comment from top of file, fix
1289 spelling in another comment.
1290
97a88e93 12912002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 1292
1293 * mips.igen (check_fmt, check_fmt_p): New functions to check
1294 whether specific floating point formats are usable.
1295 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1296 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
1297 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
1298 Use the new functions.
1299 (do_c_cond_fmt): Remove format checks...
1300 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
1301
97a88e93 13022002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 1303
1304 * mips.igen: Fix formatting of check_fpu calls.
1305
41774c9d
CD		 13062002-03-03 Chris Demetriou <cgd@broadcom.com>
1307
1308 * mips.igen (FLOOR.L.fmt): Store correct destination register.
1309
4a0bd876
CD		 13102002-03-03 Chris Demetriou <cgd@broadcom.com>
1311
1312 * mips.igen: Remove whitespace at end of lines.
1313
09297648
CD		 13142002-03-02 Chris Demetriou <cgd@broadcom.com>
1315
1316 * mips.igen (loadstore_ea): New function to do effective
1317 address calculations.
1318 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
1319 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
1320 CACHE): Use loadstore_ea to do effective address computations.
1321
043b7057
CD		 13222002-03-02 Chris Demetriou <cgd@broadcom.com>
1323
1324 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
1325 * mips.igen (LL, CxC1, MxC1): Likewise.
1326
c1e8ada4
CD		 13272002-03-02 Chris Demetriou <cgd@broadcom.com>
1328
1329 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
1330 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
1331 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
1332 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
1333 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
1334 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
1335 Don't split opcode fields by hand, use the opcode field values
1336 provided by igen.
1337
3e1dca16
CD		 13382002-03-01 Chris Demetriou <cgd@broadcom.com>
1339
1340 * mips.igen (do_divu): Fix spacing.
1341
1342 * mips.igen (do_dsllv): Move to be right before DSLLV,
1343 to match the rest of the do_<shift> functions.
1344
fff8d27d
CD		 13452002-03-01 Chris Demetriou <cgd@broadcom.com>
1346
1347 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
1348 DSRL32, do_dsrlv): Trace inputs and results.
1349
0d3e762b
CD		 13502002-03-01 Chris Demetriou <cgd@broadcom.com>
1351
1352 * mips.igen (CACHE): Provide instruction-printing string.
1353
1354 * interp.c (signal_exception): Comment tokens after #endif.
1355
eb5fcf93
CD		 13562002-02-28 Chris Demetriou <cgd@broadcom.com>
1357
1358 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
72f4393d
L		 1359 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
1360 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
1361 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
1362 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
1363 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
1364 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
eb5fcf93
CD		 1365 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
1366
bb22bd7d
CD		 13672002-02-28 Chris Demetriou <cgd@broadcom.com>
1368
1369 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
1370 instruction-printing string.
1371 (LWU): Use '64' as the filter flag.
1372
91a177cf
CD		 13732002-02-28 Chris Demetriou <cgd@broadcom.com>
1374
1375 * mips.igen (SDXC1): Fix instruction-printing string.
1376
387f484a
CD		 13772002-02-28 Chris Demetriou <cgd@broadcom.com>
1378
1379 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
1380 filter flags "32,f".
1381
3d81f391
CD		 13822002-02-27 Chris Demetriou <cgd@broadcom.com>
1383
1384 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1385 as the filter flag.
1386
af5107af
CD		 13872002-02-27 Chris Demetriou <cgd@broadcom.com>
1388
1389 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1390 add a comma) so that it more closely match the MIPS ISA
1391 documentation opcode partitioning.
1392 (PREF): Put useful names on opcode fields, and include
1393 instruction-printing string.
1394
ca971540
CD		 13952002-02-27 Chris Demetriou <cgd@broadcom.com>
1396
1397 * mips.igen (check_u64): New function which in the future will
1398 check whether 64-bit instructions are usable and signal an
1399 exception if not. Currently a no-op.
1400 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1401 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1402 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1403 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1404
1405 * mips.igen (check_fpu): New function which in the future will
1406 check whether FPU instructions are usable and signal an exception
1407 if not. Currently a no-op.
1408 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1409 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1410 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1411 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1412 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1413 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1414 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1415 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1416
1c47a468
CD		 14172002-02-27 Chris Demetriou <cgd@broadcom.com>
1418
1419 * mips.igen (do_load_left, do_load_right): Move to be immediately
1420 following do_load.
1421 (do_store_left, do_store_right): Move to be immediately following
1422 do_store.
1423
603a98e7
CD		 14242002-02-27 Chris Demetriou <cgd@broadcom.com>
1425
1426 * mips.igen (mipsV): New model name. Also, add it to
1427 all instructions and functions where it is appropriate.
1428
c5d00cc7
CD		 14292002-02-18 Chris Demetriou <cgd@broadcom.com>
1430
1431 * mips.igen: For all functions and instructions, list model
1432 names that support that instruction one per line.
1433
074e9cb8
CD		 14342002-02-11 Chris Demetriou <cgd@broadcom.com>
1435
1436 * mips.igen: Add some additional comments about supported
1437 models, and about which instructions go where.
1438 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1439 order as is used in the rest of the file.
1440
9805e229
CD		 14412002-02-11 Chris Demetriou <cgd@broadcom.com>
1442
1443 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1444 indicating that ALU32_END or ALU64_END are there to check
1445 for overflow.
1446 (DADD): Likewise, but also remove previous comment about
1447 overflow checking.
1448
f701dad2
CD		 14492002-02-10 Chris Demetriou <cgd@broadcom.com>
1450
1451 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1452 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1453 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1454 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1455 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1456 fields (i.e., add and move commas) so that they more closely
1457 match the MIPS ISA documentation opcode partitioning.
1458
14592002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098 1460
72f4393d
L		 1461 * mips.igen (ADDI): Print immediate value.
1462 (BREAK): Print code.
1463 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1464 (SLL): Print "nop" specially, and don't run the code
1465 that does the shift for the "nop" case.
20ae0098 1466
9e52972e
FF		 14672001-11-17 Fred Fish <fnf@redhat.com>
1468
1469 * sim-main.h (float_operation): Move enum declaration outside
1470 of _sim_cpu struct declaration.
1471
c0efbca4
JB		 14722001-04-12 Jim Blandy <jimb@redhat.com>
1473
1474 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1475 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1476 set of the FCSR.
1477 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1478 PENDING_FILL, and you can get the intended effect gracefully by
1479 calling PENDING_SCHED directly.
1480
fb891446
BE		 14812001-02-23 Ben Elliston <bje@redhat.com>
1482
1483 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1484 already defined elsewhere.
1485
8030f857
BE		 14862001-02-19 Ben Elliston <bje@redhat.com>
1487
1488 * sim-main.h (sim_monitor): Return an int.
1489 * interp.c (sim_monitor): Add return values.
1490 (signal_exception): Handle error conditions from sim_monitor.
1491
56b48a7a
CD		 14922001-02-08 Ben Elliston <bje@redhat.com>
1493
1494 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1495 (store_memory): Likewise, pass cia to sim_core_write*.
1496
d3ee60d9
FCE		 14972000-10-19 Frank Ch. Eigler <fche@redhat.com>
1498
1499 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1500 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1501
071da002
AC		 1502Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1503
1504 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1505 * Makefile.in: Don't delete *.igen when cleaning directory.
1506
a28c02cd
AC		 1507Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1508
1509 * m16.igen (break): Call SignalException not sim_engine_halt.
1510
80ee11fa
AC		 1511Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1512
1513 From Jason Eckhardt:
1514 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1515
673388c0
AC		 1516Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1517
1518 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1519
4c0deff4
NC		 15202000-05-24 Michael Hayes <mhayes@cygnus.com>
1521
1522 * mips.igen (do_dmultx): Fix typo.
1523
eb2d80b4
AC		 1524Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1525
1526 * configure: Regenerated to track ../common/aclocal.m4 changes.
1527
dd37a34b
AC		 1528Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1529
1530 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1531
4c0deff4
NC		 15322000-04-12 Frank Ch. Eigler <fche@redhat.com>
1533
1534 * sim-main.h (GPR_CLEAR): Define macro.
1535
e30db738
AC		 1536Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1537
1538 * interp.c (decode_coproc): Output long using %lx and not %s.
1539
cb7450ea
FCE		 15402000-03-21 Frank Ch. Eigler <fche@redhat.com>
1541
1542 * interp.c (sim_open): Sort & extend dummy memory regions for
1543 --board=jmr3904 for eCos.
1544
a3027dd7
FCE		 15452000-03-02 Frank Ch. Eigler <fche@redhat.com>
1546
1547 * configure: Regenerated.
1548
1549Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1550
1551 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1552 calls, conditional on the simulator being in verbose mode.
1553
dfcd3bfb
JM		 1554Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1555
1556 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1557 cache don't get ReservedInstruction traps.
1558
c2d11a7d
JM		 15591999-11-29 Mark Salter <msalter@cygnus.com>
1560
1561 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1562 to clear status bits in sdisr register. This is how the hardware works.
1563
1564 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1565 being used by cygmon.
1566
4ce44c66
JM		 15671999-11-11 Andrew Haley <aph@cygnus.com>
1568
1569 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1570 instructions.
1571
cff3e48b
JM		 1572Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1573
1574 * mips.igen (MULT): Correct previous mis-applied patch.
1575
d4f3574e
SS		 1576Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1577
1578 * mips.igen (delayslot32): Handle sequence like
1579 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1580 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1581 (MULT): Actually pass the third register...
1582
15831999-09-03 Mark Salter <msalter@cygnus.com>
1584
1585 * interp.c (sim_open): Added more memory aliases for additional
1586 hardware being touched by cygmon on jmr3904 board.
1587
1588Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1589
1590 * configure: Regenerated to track ../common/aclocal.m4 changes.
1591
a0b3c4fd
JM		 1592Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1593
1594 * interp.c (sim_store_register): Handle case where client - GDB -
1595 specifies that a 4 byte register is 8 bytes in size.
1596 (sim_fetch_register): Ditto.
72f4393d 1597
adf40b2e
JM		 15981999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1599
1600 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1601 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1602 (idt_monitor_base): Base address for IDT monitor traps.
1603 (pmon_monitor_base): Ditto for PMON.
1604 (lsipmon_monitor_base): Ditto for LSI PMON.
1605 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1606 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1607 (sim_firmware_command): New function.
1608 (mips_option_handler): Call it for OPTION_FIRMWARE.
1609 (sim_open): Allocate memory for idt_monitor region. If "--board"
1610 option was given, add no monitor by default. Add BREAK hooks only if
1611 monitors are also there.
72f4393d 1612
43e526b9
JM		 1613Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1614
1615 * interp.c (sim_monitor): Flush output before reading input.
1616
1617Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1618
1619 * tconfig.in (SIM_HANDLES_LMA): Always define.
1620
1621Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1622
1623 From Mark Salter <msalter@cygnus.com>:
1624 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1625 (sim_open): Add setup for BSP board.
1626
9846de1b
JM		 1627Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1628
1629 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1630 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1631 them as unimplemented.
1632
cd0fc7c3
SS		 16331999-05-08 Felix Lee <flee@cygnus.com>
1634
1635 * configure: Regenerated to track ../common/aclocal.m4 changes.
72f4393d 1636
7a292a7a
SS		 16371999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1638
1639 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1640
1641Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1642
1643 * configure.in: Any mips64vr5*-*-* target should have
1644 -DTARGET_ENABLE_FR=1.
1645 (default_endian): Any mips64vr*el-*-* target should default to
1646 LITTLE_ENDIAN.
1647 * configure: Re-generate.
1648
16491999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1650
1651 * mips.igen (ldl): Extend from _16_, not 32.
1652
1653Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1654
1655 * interp.c (sim_store_register): Force registers written to by GDB
1656 into an un-interpreted state.
1657
c906108c
SS		 16581999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1659
1660 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1661 CPU, start periodic background I/O polls.
72f4393d 1662 (tx3904sio_poll): New function: periodic I/O poller.
c906108c
SS		 1663
16641998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1665
1666 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
72f4393d 1667
c906108c
SS		 1668Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1669
1670 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1671 case statement.
1672
16731998-12-29 Frank Ch. Eigler <fche@cygnus.com>
72f4393d
L		 1674
1675 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
c906108c
SS		 1676 (load_word): Call SIM_CORE_SIGNAL hook on error.
1677 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1678 starting. For exception dispatching, pass PC instead of NULL_CIA.
1679 (decode_coproc): Use COP0_BADVADDR to store faulting address.
72f4393d 1680 * sim-main.h (COP0_BADVADDR): Define.
c906108c
SS		 1681 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1682 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
72f4393d 1683 (_sim_cpu): Add exc_* fields to store register value snapshots.
c906108c
SS		 1684 * mips.igen (*): Replace memory-related SignalException* calls
1685 with references to SIM_CORE_SIGNAL hook.
72f4393d 1686
c906108c
SS		 1687 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1688 fix.
1689 * sim-main.c (*): Minor warning cleanups.
72f4393d 1690
c906108c
SS		 16911998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1692
1693 * m16.igen (DADDIU5): Correct type-o.
1694
1695Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1696
1697 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1698 variables.
1699
1700Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1701
1702 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1703 to include path.
1704 (interp.o): Add dependency on itable.h
1705 (oengine.c, gencode): Delete remaining references.
1706 (BUILT_SRC_FROM_GEN): Clean up.
72f4393d 1707
c906108c 17081998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
72f4393d 1709
c906108c
SS		 1710 * vr4run.c: New.
1711 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1712 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1713 tmp-run-hack) : New.
1714 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
72f4393d 1715 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
c906108c
SS		 1716 Drop the "64" qualifier to get the HACK generator working.
1717 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1718 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1719 qualifier to get the hack generator working.
1720 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1721 (DSLL): Use do_dsll.
1722 (DSLLV): Use do_dsllv.
1723 (DSRA): Use do_dsra.
1724 (DSRL): Use do_dsrl.
1725 (DSRLV): Use do_dsrlv.
1726 (BC1): Move *vr4100 to get the HACK generator working.
72f4393d 1727 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
c906108c
SS		 1728 get the HACK generator working.
1729 (MACC) Rename to get the HACK generator working.
1730 (DMACC,MACCS,DMACCS): Add the 64.
72f4393d 1731
c906108c
SS		 17321998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1733
1734 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1735 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
72f4393d 1736
c906108c
SS		 17371998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1738
1739 * mips/interp.c (DEBUG): Cleanups.
1740
17411998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1742
1743 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1744 (tx3904sio_tickle): fflush after a stdout character output.
72f4393d 1745
c906108c
SS		 17461998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1747
1748 * interp.c (sim_close): Uninstall modules.
1749
1750Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1751
1752 * sim-main.h, interp.c (sim_monitor): Change to global
1753 function.
1754
1755Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1756
1757 * configure.in (vr4100): Only include vr4100 instructions in
1758 simulator.
1759 * configure: Re-generate.
1760 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1761
1762Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1763
1764 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1765 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1766 true alternative.
1767
1768 * configure.in (sim_default_gen, sim_use_gen): Replace with
1769 sim_gen.
1770 (--enable-sim-igen): Delete config option. Always using IGEN.
1771 * configure: Re-generate.
72f4393d 1772
c906108c
SS		 1773 * Makefile.in (gencode): Kill, kill, kill.
1774 * gencode.c: Ditto.
72f4393d 1775
c906108c
SS		 1776Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1777
1778 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1779 bit mips16 igen simulator.
1780 * configure: Re-generate.
1781
1782 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1783 as part of vr4100 ISA.
1784 * vr.igen: Mark all instructions as 64 bit only.
1785
1786Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1787
1788 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1789 Pacify GCC.
1790
1791Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1792
1793 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1794 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1795 * configure: Re-generate.
1796
1797 * m16.igen (BREAK): Define breakpoint instruction.
1798 (JALX32): Mark instruction as mips16 and not r3900.
1799 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1800
1801 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1802
1803Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1804
1805 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1806 insn as a debug breakpoint.
1807
1808 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1809 pending.slot_size.
1810 (PENDING_SCHED): Clean up trace statement.
1811 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1812 (PENDING_FILL): Delay write by only one cycle.
1813 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1814
1815 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1816 of pending writes.
1817 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1818 32 & 64.
1819 (pending_tick): Move incrementing of index to FOR statement.
1820 (pending_tick): Only update PENDING_OUT after a write has occured.
72f4393d 1821
c906108c
SS		 1822 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1823 build simulator.
1824 * configure: Re-generate.
72f4393d 1825
c906108c
SS		 1826 * interp.c (sim_engine_run OLD): Delete explicit call to
1827 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
72f4393d 1828
c906108c
SS		 1829Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1830
1831 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1832 interrupt level number to match changed SignalExceptionInterrupt
1833 macro.
1834
1835Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1836
1837 * interp.c: #include "itable.h" if WITH_IGEN.
1838 (get_insn_name): New function.
1839 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1840 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1841
1842Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1843
1844 * configure: Rebuilt to inhale new common/aclocal.m4.
1845
1846Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1847
1848 * dv-tx3904sio.c: Include sim-assert.h.
1849
1850Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1851
1852 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1853 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1854 Reorganize target-specific sim-hardware checks.
1855 * configure: rebuilt.
1856 * interp.c (sim_open): For tx39 target boards, set
1857 OPERATING_ENVIRONMENT, add tx3904sio devices.
1858 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1859 ROM executables. Install dv-sockser into sim-modules list.
72f4393d 1860
c906108c
SS		 1861 * dv-tx3904irc.c: Compiler warning clean-up.
1862 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1863 frequent hw-trace messages.
1864
1865Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1866
1867 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1868
1869Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1870
1871 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1872
1873 * vr.igen: New file.
1874 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1875 * mips.igen: Define vr4100 model. Include vr.igen.
1876Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1877
1878 * mips.igen (check_mf_hilo): Correct check.
1879
1880Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1881
1882 * sim-main.h (interrupt_event): Add prototype.
1883
1884 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1885 register_ptr, register_value.
1886 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1887
1888 * sim-main.h (tracefh): Make extern.
1889
1890Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1891
1892 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
72f4393d 1893 Reduce unnecessarily high timer event frequency.
c906108c 1894 * dv-tx3904cpu.c: Ditto for interrupt event.
72f4393d 1895
c906108c
SS		 1896Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1897
1898 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1899 to allay warnings.
1900 (interrupt_event): Made non-static.
72f4393d 1901
c906108c
SS		 1902 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1903 interchange of configuration values for external vs. internal
1904 clock dividers.
72f4393d 1905
c906108c
SS		 1906Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1907
72f4393d 1908 * mips.igen (BREAK): Moved code to here for
c906108c
SS		 1909 simulator-reserved break instructions.
1910 * gencode.c (build_instruction): Ditto.
1911 * interp.c (signal_exception): Code moved from here. Non-
72f4393d 1912 reserved instructions now use exception vector, rather
c906108c
SS		 1913 than halting sim.
1914 * sim-main.h: Moved magic constants to here.
1915
1916Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1917
1918 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1919 register upon non-zero interrupt event level, clear upon zero
1920 event value.
1921 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1922 by passing zero event value.
1923 (*_io_{read,write}_buffer): Endianness fixes.
1924 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1925 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1926
1927 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1928 serial I/O and timer module at base address 0xFFFF0000.
72f4393d 1929
c906108c
SS		 1930Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1931
72f4393d 1932 * mips.igen (SWC1) : Correct the handling of ReverseEndian
c906108c
SS		 1933 and BigEndianCPU.
1934
1935Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1936
1937 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1938 parts.
1939 * configure: Update.
1940
1941Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1942
1943 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1944 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1945 * configure.in: Include tx3904tmr in hw_device list.
1946 * configure: Rebuilt.
1947 * interp.c (sim_open): Instantiate three timer instances.
1948 Fix address typo of tx3904irc instance.
1949
1950Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1951
1952 * interp.c (signal_exception): SystemCall exception now uses
1953 the exception vector.
1954
1955Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1956
1957 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1958 to allay warnings.
1959
1960Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1961
1962 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1963
1964Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1965
1966 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1967
1968 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1969 sim-main.h. Declare a struct hw_descriptor instead of struct
1970 hw_device_descriptor.
1971
1972Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1973
1974 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1975 right bits and then re-align left hand bytes to correct byte
1976 lanes. Fix incorrect computation in do_store_left when loading
1977 bytes from second word.
1978
1979Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1980
1981 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1982 * interp.c (sim_open): Only create a device tree when HW is
1983 enabled.
1984
1985 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1986 * interp.c (signal_exception): Ditto.
1987
1988Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1989
1990 * gencode.c: Mark BEGEZALL as LIKELY.
1991
1992Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1993
1994 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1995 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
72f4393d 1996
c906108c
SS		 1997Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1998
1999 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
2000 modules. Recognize TX39 target with "mips*tx39" pattern.
2001 * configure: Rebuilt.
2002 * sim-main.h (*): Added many macros defining bits in
2003 TX39 control registers.
2004 (SignalInterrupt): Send actual PC instead of NULL.
2005 (SignalNMIReset): New exception type.
2006 * interp.c (board): New variable for future use to identify
2007 a particular board being simulated.
2008 (mips_option_handler,mips_options): Added "--board" option.
2009 (interrupt_event): Send actual PC.
2010 (sim_open): Make memory layout conditional on board setting.
2011 (signal_exception): Initial implementation of hardware interrupt
2012 handling. Accept another break instruction variant for simulator
2013 exit.
2014 (decode_coproc): Implement RFE instruction for TX39.
2015 (mips.igen): Decode RFE instruction as such.
2016 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
2017 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
2018 bbegin to implement memory map.
2019 * dv-tx3904cpu.c: New file.
2020 * dv-tx3904irc.c: New file.
2021
2022Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
2023
2024 * mips.igen (check_mt_hilo): Create a separate r3900 version.
2025
2026Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
2027
2028 * tx.igen (madd,maddu): Replace calls to check_op_hilo
2029 with calls to check_div_hilo.
2030
2031Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
2032
2033 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
2034 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
72f4393d 2035 Add special r3900 version of do_mult_hilo.
c906108c
SS		 2036 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
2037 with calls to check_mult_hilo.
2038 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
2039 with calls to check_div_hilo.
2040
2041Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
2042
2043 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
2044 Document a replacement.
2045
2046Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
2047
2048 * interp.c (sim_monitor): Make mon_printf work.
2049
2050Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
2051
2052 * sim-main.h (INSN_NAME): New arg `cpu'.
2053
2054Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
2055
72f4393d 2056 * configure: Regenerated to track ../common/aclocal.m4 changes.
c906108c
SS		 2057
2058Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
2059
2060 * configure: Regenerated to track ../common/aclocal.m4 changes.
2061 * config.in: Ditto.
2062
2063Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
2064
2065 * acconfig.h: New file.
2066 * configure.in: Reverted change of Apr 24; use sinclude again.
2067
2068Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
2069
2070 * configure: Regenerated to track ../common/aclocal.m4 changes.
2071 * config.in: Ditto.
2072
2073Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
2074
2075 * configure.in: Don't call sinclude.
2076
2077Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
2078
2079 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
2080
2081Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2082
2083 * mips.igen (ERET): Implement.
2084
2085 * interp.c (decode_coproc): Return sign-extended EPC.
2086
2087 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
2088
2089 * interp.c (signal_exception): Do not ignore Trap.
2090 (signal_exception): On TRAP, restart at exception address.
2091 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
2092 (signal_exception): Update.
2093 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
2094 so that TRAP instructions are caught.
2095
2096Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
2097
2098 * sim-main.h (struct hilo_access, struct hilo_history): Define,
2099 contains HI/LO access history.
2100 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
2101 (HIACCESS, LOACCESS): Delete, replace with
2102 (HIHISTORY, LOHISTORY): New macros.
2103 (CHECKHILO): Delete all, moved to mips.igen
72f4393d 2104
c906108c
SS		 2105 * gencode.c (build_instruction): Do not generate checks for
2106 correct HI/LO register usage.
2107
2108 * interp.c (old_engine_run): Delete checks for correct HI/LO
2109 register usage.
2110
2111 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
2112 check_mf_cycles): New functions.
2113 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
2114 do_divu, domultx, do_mult, do_multu): Use.
2115
2116 * tx.igen ("madd", "maddu"): Use.
72f4393d 2117
c906108c
SS		 2118Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
2119
2120 * mips.igen (DSRAV): Use function do_dsrav.
2121 (SRAV): Use new function do_srav.
2122
2123 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
2124 (B): Sign extend 11 bit immediate.
2125 (EXT-B*): Shift 16 bit immediate left by 1.
2126 (ADDIU*): Don't sign extend immediate value.
2127
2128Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2129
2130 * m16run.c (sim_engine_run): Restore CIA after handling an event.
2131
2132 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
2133 functions.
2134
2135 * mips.igen (delayslot32, nullify_next_insn): New functions.
2136 (m16.igen): Always include.
2137 (do_*): Add more tracing.
2138
2139 * m16.igen (delayslot16): Add NIA argument, could be called by a
2140 32 bit MIPS16 instruction.
72f4393d 2141
c906108c
SS		 2142 * interp.c (ifetch16): Move function from here.
2143 * sim-main.c (ifetch16): To here.
72f4393d 2144
c906108c
SS		 2145 * sim-main.c (ifetch16, ifetch32): Update to match current
2146 implementations of LH, LW.
2147 (signal_exception): Don't print out incorrect hex value of illegal
2148 instruction.
2149
2150Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2151
2152 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
2153 instruction.
2154
2155 * m16.igen: Implement MIPS16 instructions.
72f4393d 2156
c906108c
SS		 2157 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
2158 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
2159 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
2160 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
2161 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
2162 bodies of corresponding code from 32 bit insn to these. Also used
2163 by MIPS16 versions of functions.
72f4393d 2164
c906108c
SS		 2165 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
2166 (IMEM16): Drop NR argument from macro.
2167
2168Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2169
2170 * Makefile.in (SIM_OBJS): Add sim-main.o.
2171
2172 * sim-main.h (address_translation, load_memory, store_memory,
2173 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
2174 as INLINE_SIM_MAIN.
2175 (pr_addr, pr_uword64): Declare.
2176 (sim-main.c): Include when H_REVEALS_MODULE_P.
72f4393d 2177
c906108c
SS		 2178 * interp.c (address_translation, load_memory, store_memory,
2179 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
2180 from here.
2181 * sim-main.c: To here. Fix compilation problems.
72f4393d 2182
c906108c
SS		 2183 * configure.in: Enable inlining.
2184 * configure: Re-config.
2185
2186Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2187
2188 * configure: Regenerated to track ../common/aclocal.m4 changes.
2189
2190Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2191
2192 * mips.igen: Include tx.igen.
2193 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
2194 * tx.igen: New file, contains MADD and MADDU.
2195
2196 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
2197 the hardwired constant `7'.
2198 (store_memory): Ditto.
2199 (LOADDRMASK): Move definition to sim-main.h.
2200
2201 mips.igen (MTC0): Enable for r3900.
2202 (ADDU): Add trace.
2203
2204 mips.igen (do_load_byte): Delete.
2205 (do_load, do_store, do_load_left, do_load_write, do_store_left,
2206 do_store_right): New functions.
2207 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
2208
2209 configure.in: Let the tx39 use igen again.
2210 configure: Update.
72f4393d 2211
c906108c
SS		 2212Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2213
2214 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
2215 not an address sized quantity. Return zero for cache sizes.
2216
2217Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
2218
2219 * mips.igen (r3900): r3900 does not support 64 bit integer
2220 operations.
2221
2222Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
2223
2224 * configure.in (mipstx39*-*-*): Use gencode simulator rather
2225 than igen one.
2226 * configure : Rebuild.
72f4393d 2227
c906108c
SS		 2228Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
2229
2230 * configure: Regenerated to track ../common/aclocal.m4 changes.
2231
2232Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2233
2234 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
2235
2236Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
2237
2238 * configure: Regenerated to track ../common/aclocal.m4 changes.
2239 * config.in: Regenerated to track ../common/aclocal.m4 changes.
2240
2241Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2242
2243 * configure: Regenerated to track ../common/aclocal.m4 changes.
2244
2245Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
2246
2247 * interp.c (Max, Min): Comment out functions. Not yet used.
2248
2249Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
2250
2251 * configure: Regenerated to track ../common/aclocal.m4 changes.
2252
2253Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
2254
2255 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
2256 configurable settings for stand-alone simulator.
72f4393d 2257
c906108c 2258 * configure.in: Added X11 search, just in case.
72f4393d 2259
c906108c
SS		 2260 * configure: Regenerated.
2261
2262Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
2263
2264 * interp.c (sim_write, sim_read, load_memory, store_memory):
2265 Replace sim_core_*_map with read_map, write_map, exec_map resp.
2266
2267Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
2268
2269 * sim-main.h (GETFCC): Return an unsigned value.
2270
2271Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2272
2273 * mips.igen (DIV): Fix check for -1 / MIN_INT.
2274 (DADD): Result destination is RD not RT.
2275
2276Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2277
2278 * sim-main.h (HIACCESS, LOACCESS): Always define.
2279
2280 * mdmx.igen (Maxi, Mini): Rename Max, Min.
2281
2282 * interp.c (sim_info): Delete.
2283
2284Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
2285
2286 * interp.c (DECLARE_OPTION_HANDLER): Use it.
2287 (mips_option_handler): New argument `cpu'.
2288 (sim_open): Update call to sim_add_option_table.
2289
2290Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
2291
2292 * mips.igen (CxC1): Add tracing.
2293
2294Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
2295
2296 * sim-main.h (Max, Min): Declare.
2297
2298 * interp.c (Max, Min): New functions.
2299
2300 * mips.igen (BC1): Add tracing.
72f4393d 2301
c906108c 2302Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
72f4393d 2303
c906108c 2304 * interp.c Added memory map for stack in vr4100
72f4393d 2305
c906108c
SS		 2306Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
2307
2308 * interp.c (load_memory): Add missing "break"'s.
2309
2310Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2311
2312 * interp.c (sim_store_register, sim_fetch_register): Pass in
2313 length parameter. Return -1.
2314
2315Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
2316
2317 * interp.c: Added hardware init hook, fixed warnings.
2318
2319Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2320
2321 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
2322
2323Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
2324
2325 * interp.c (ifetch16): New function.
2326
2327 * sim-main.h (IMEM32): Rename IMEM.
2328 (IMEM16_IMMED): Define.
2329 (IMEM16): Define.
2330 (DELAY_SLOT): Update.
72f4393d 2331
c906108c 2332 * m16run.c (sim_engine_run): New file.
72f4393d 2333
c906108c
SS		 2334 * m16.igen: All instructions except LB.
2335 (LB): Call do_load_byte.
2336 * mips.igen (do_load_byte): New function.
2337 (LB): Call do_load_byte.
2338
2339 * mips.igen: Move spec for insn bit size and high bit from here.
2340 * Makefile.in (tmp-igen, tmp-m16): To here.
2341
2342 * m16.dc: New file, decode mips16 instructions.
2343
2344 * Makefile.in (SIM_NO_ALL): Define.
2345 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
2346
2347Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
2348
2349 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
2350 point unit to 32 bit registers.
2351 * configure: Re-generate.
2352
2353Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2354
2355 * configure.in (sim_use_gen): Make IGEN the default simulator
2356 generator for generic 32 and 64 bit mips targets.
2357 * configure: Re-generate.
2358
2359Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2360
2361 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
2362 bitsize.
2363
2364 * interp.c (sim_fetch_register, sim_store_register): Read/write
2365 FGR from correct location.
2366 (sim_open): Set size of FGR's according to
2367 WITH_TARGET_FLOATING_POINT_BITSIZE.
72f4393d 2368
c906108c
SS		 2369 * sim-main.h (FGR): Store floating point registers in a separate
2370 array.
2371
2372Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
2373
2374 * configure: Regenerated to track ../common/aclocal.m4 changes.
2375
2376Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2377
2378 * interp.c (ColdReset): Call PENDING_INVALIDATE.
2379
2380 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
2381
2382 * interp.c (pending_tick): New function. Deliver pending writes.
2383
2384 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2385 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2386 it can handle mixed sized quantites and single bits.
72f4393d 2387
c906108c
SS		 2388Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2389
2390 * interp.c (oengine.h): Do not include when building with IGEN.
2391 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2392 (sim_info): Ditto for PROCESSOR_64BIT.
2393 (sim_monitor): Replace ut_reg with unsigned_word.
2394 (*): Ditto for t_reg.
2395 (LOADDRMASK): Define.
2396 (sim_open): Remove defunct check that host FP is IEEE compliant,
2397 using software to emulate floating point.
2398 (value_fpr, ...): Always compile, was conditional on HASFPU.
2399
2400Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2401
2402 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2403 size.
2404
2405 * interp.c (SD, CPU): Define.
2406 (mips_option_handler): Set flags in each CPU.
2407 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2408 (sim_close): Do not clear STATE, deleted anyway.
2409 (sim_write, sim_read): Assume CPU zero's vm should be used for
2410 data transfers.
2411 (sim_create_inferior): Set the PC for all processors.
2412 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2413 argument.
2414 (mips16_entry): Pass correct nr of args to store_word, load_word.
2415 (ColdReset): Cold reset all cpu's.
2416 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2417 (sim_monitor, load_memory, store_memory, signal_exception): Use
2418 `CPU' instead of STATE_CPU.
2419
2420
2421 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2422 SD or CPU_.
72f4393d 2423
c906108c
SS		 2424 * sim-main.h (signal_exception): Add sim_cpu arg.
2425 (SignalException*): Pass both SD and CPU to signal_exception.
2426 * interp.c (signal_exception): Update.
72f4393d 2427
c906108c
SS		 2428 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2429 Ditto
2430 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2431 address_translation): Ditto
2432 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
72f4393d 2433
c906108c
SS		 2434Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2435
2436 * configure: Regenerated to track ../common/aclocal.m4 changes.
2437
2438Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2439
2440 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2441
72f4393d 2442 * mips.igen (model): Map processor names onto BFD name.
c906108c
SS		 2443
2444 * sim-main.h (CPU_CIA): Delete.
2445 (SET_CIA, GET_CIA): Define
2446
2447Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2448
2449 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2450 regiser.
2451
2452 * configure.in (default_endian): Configure a big-endian simulator
2453 by default.
2454 * configure: Re-generate.
72f4393d 2455
c906108c
SS		 2456Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2457
2458 * configure: Regenerated to track ../common/aclocal.m4 changes.
2459
2460Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2461
2462 * interp.c (sim_monitor): Handle Densan monitor outbyte
2463 and inbyte functions.
2464
24651997-12-29 Felix Lee <flee@cygnus.com>
2466
2467 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2468
2469Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2470
2471 * Makefile.in (tmp-igen): Arrange for $zero to always be
2472 reset to zero after every instruction.
2473
2474Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2475
2476 * configure: Regenerated to track ../common/aclocal.m4 changes.
2477 * config.in: Ditto.
2478
2479Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2480
2481 * mips.igen (MSUB): Fix to work like MADD.
2482 * gencode.c (MSUB): Similarly.
2483
2484Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2485
2486 * configure: Regenerated to track ../common/aclocal.m4 changes.
2487
2488Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2489
2490 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2491
2492Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2493
2494 * sim-main.h (sim-fpu.h): Include.
2495
2496 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2497 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2498 using host independant sim_fpu module.
2499
2500Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2501
2502 * interp.c (signal_exception): Report internal errors with SIGABRT
2503 not SIGQUIT.
2504
2505 * sim-main.h (C0_CONFIG): New register.
2506 (signal.h): No longer include.
2507
2508 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2509
2510Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2511
2512 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2513
2514Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2515
2516 * mips.igen: Tag vr5000 instructions.
2517 (ANDI): Was missing mipsIV model, fix assembler syntax.
2518 (do_c_cond_fmt): New function.
2519 (C.cond.fmt): Handle mips I-III which do not support CC field
2520 separatly.
2521 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2522 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2523 in IV3.2 spec.
2524 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2525 vr5000 which saves LO in a GPR separatly.
72f4393d 2526
c906108c
SS		 2527 * configure.in (enable-sim-igen): For vr5000, select vr5000
2528 specific instructions.
2529 * configure: Re-generate.
72f4393d 2530
c906108c
SS		 2531Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2532
2533 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2534
2535 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2536 fmt_uninterpreted_64 bit cases to switch. Convert to
2537 fmt_formatted,
2538
2539 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2540
2541 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2542 as specified in IV3.2 spec.
2543 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2544
2545Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2546
2547 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2548 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2549 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2550 PENDING_FILL versions of instructions. Simplify.
2551 (X): New function.
2552 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2553 instructions.
2554 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2555 a signed value.
2556 (MTHI, MFHI): Disable code checking HI-LO.
72f4393d 2557
c906108c
SS		 2558 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2559 global.
2560 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2561
2562Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2563
2564 * gencode.c (build_mips16_operands): Replace IPC with cia.
2565
2566 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2567 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2568 IPC to `cia'.
2569 (UndefinedResult): Replace function with macro/function
2570 combination.
2571 (sim_engine_run): Don't save PC in IPC.
2572
2573 * sim-main.h (IPC): Delete.
2574
2575
2576 * interp.c (signal_exception, store_word, load_word,
2577 address_translation, load_memory, store_memory, cache_op,
2578 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2579 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2580 current instruction address - cia - argument.
2581 (sim_read, sim_write): Call address_translation directly.
2582 (sim_engine_run): Rename variable vaddr to cia.
2583 (signal_exception): Pass cia to sim_monitor
72f4393d 2584
c906108c
SS		 2585 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2586 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2587 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2588
2589 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2590 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2591 SIM_ASSERT.
72f4393d 2592
c906108c
SS		 2593 * interp.c (signal_exception): Pass restart address to
2594 sim_engine_restart.
2595
2596 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2597 idecode.o): Add dependency.
2598
2599 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2600 Delete definitions
2601 (DELAY_SLOT): Update NIA not PC with branch address.
2602 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2603
2604 * mips.igen: Use CIA not PC in branch calculations.
2605 (illegal): Call SignalException.
2606 (BEQ, ADDIU): Fix assembler.
2607
2608Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2609
2610 * m16.igen (JALX): Was missing.
2611
2612 * configure.in (enable-sim-igen): New configuration option.
2613 * configure: Re-generate.
72f4393d 2614
c906108c
SS		 2615 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2616
2617 * interp.c (load_memory, store_memory): Delete parameter RAW.
2618 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2619 bypassing {load,store}_memory.
2620
2621 * sim-main.h (ByteSwapMem): Delete definition.
2622
2623 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2624
2625 * interp.c (sim_do_command, sim_commands): Delete mips specific
2626 commands. Handled by module sim-options.
72f4393d 2627
c906108c
SS		 2628 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2629 (WITH_MODULO_MEMORY): Define.
2630
2631 * interp.c (sim_info): Delete code printing memory size.
2632
2633 * interp.c (mips_size): Nee sim_size, delete function.
2634 (power2): Delete.
2635 (monitor, monitor_base, monitor_size): Delete global variables.
2636 (sim_open, sim_close): Delete code creating monitor and other
2637 memory regions. Use sim-memopts module, via sim_do_commandf, to
2638 manage memory regions.
2639 (load_memory, store_memory): Use sim-core for memory model.
72f4393d 2640
c906108c
SS		 2641 * interp.c (address_translation): Delete all memory map code
2642 except line forcing 32 bit addresses.
2643
2644Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2645
2646 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2647 trace options.
2648
2649 * interp.c (logfh, logfile): Delete globals.
2650 (sim_open, sim_close): Delete code opening & closing log file.
2651 (mips_option_handler): Delete -l and -n options.
2652 (OPTION mips_options): Ditto.
2653
2654 * interp.c (OPTION mips_options): Rename option trace to dinero.
2655 (mips_option_handler): Update.
2656
2657Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2658
2659 * interp.c (fetch_str): New function.
2660 (sim_monitor): Rewrite using sim_read & sim_write.
2661 (sim_open): Check magic number.
2662 (sim_open): Write monitor vectors into memory using sim_write.
2663 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2664 (sim_read, sim_write): Simplify - transfer data one byte at a
2665 time.
2666 (load_memory, store_memory): Clarify meaning of parameter RAW.
2667
2668 * sim-main.h (isHOST): Defete definition.
2669 (isTARGET): Mark as depreciated.
2670 (address_translation): Delete parameter HOST.
2671
2672 * interp.c (address_translation): Delete parameter HOST.
2673
2674Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2675
72f4393d 2676 * mips.igen:
c906108c
SS		 2677
2678 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2679 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2680
2681Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2682
2683 * mips.igen: Add model filter field to records.
2684
2685Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2686
2687 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
72f4393d 2688
c906108c
SS		 2689 interp.c (sim_engine_run): Do not compile function sim_engine_run
2690 when WITH_IGEN == 1.
2691
2692 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2693 target architecture.
2694
2695 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2696 igen. Replace with configuration variables sim_igen_flags /
2697 sim_m16_flags.
2698
2699 * m16.igen: New file. Copy mips16 insns here.
2700 * mips.igen: From here.
2701
2702Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2703
2704 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2705 to top.
2706 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2707
2708Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2709
2710 * gencode.c (build_instruction): Follow sim_write's lead in using
2711 BigEndianMem instead of !ByteSwapMem.
2712
2713Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2714
2715 * configure.in (sim_gen): Dependent on target, select type of
2716 generator. Always select old style generator.
2717
2718 configure: Re-generate.
2719
2720 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2721 targets.
2722 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2723 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2724 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2725 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2726 SIM_@sim_gen@_*, set by autoconf.
72f4393d 2727
c906108c
SS		 2728Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2729
2730 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2731
2732 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2733 CURRENT_FLOATING_POINT instead.
2734
2735 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2736 (address_translation): Raise exception InstructionFetch when
2737 translation fails and isINSTRUCTION.
72f4393d 2738
c906108c
SS		 2739 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2740 sim_engine_run): Change type of of vaddr and paddr to
2741 address_word.
2742 (address_translation, prefetch, load_memory, store_memory,
2743 cache_op): Change type of vAddr and pAddr to address_word.
2744
2745 * gencode.c (build_instruction): Change type of vaddr and paddr to
2746 address_word.
2747
2748Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2749
2750 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2751 macro to obtain result of ALU op.
2752
2753Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2754
2755 * interp.c (sim_info): Call profile_print.
2756
2757Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2758
2759 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2760
2761 * sim-main.h (WITH_PROFILE): Do not define, defined in
2762 common/sim-config.h. Use sim-profile module.
2763 (simPROFILE): Delete defintion.
2764
2765 * interp.c (PROFILE): Delete definition.
2766 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2767 (sim_close): Delete code writing profile histogram.
2768 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2769 Delete.
2770 (sim_engine_run): Delete code profiling the PC.
2771
2772Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2773
2774 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2775
2776 * interp.c (sim_monitor): Make register pointers of type
2777 unsigned_word*.
2778
2779 * sim-main.h: Make registers of type unsigned_word not
2780 signed_word.
2781
2782Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2783
2784 * interp.c (sync_operation): Rename from SyncOperation, make
2785 global, add SD argument.
2786 (prefetch): Rename from Prefetch, make global, add SD argument.
2787 (decode_coproc): Make global.
2788
2789 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2790
2791 * gencode.c (build_instruction): Generate DecodeCoproc not
2792 decode_coproc calls.
2793
2794 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2795 (SizeFGR): Move to sim-main.h
2796 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2797 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2798 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2799 sim-main.h.
2800 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2801 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2802 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2803 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2804 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2805 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
72f4393d 2806
c906108c
SS		 2807 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2808 exception.
2809 (sim-alu.h): Include.
2810 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2811 (sim_cia): Typedef to instruction_address.
72f4393d 2812
c906108c
SS		 2813Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2814
2815 * Makefile.in (interp.o): Rename generated file engine.c to
2816 oengine.c.
72f4393d 2817
c906108c 2818 * interp.c: Update.
72f4393d 2819
c906108c
SS		 2820Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2821
2822 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
72f4393d 2823
c906108c
SS		 2824Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2825
2826 * gencode.c (build_instruction): For "FPSQRT", output correct
2827 number of arguments to Recip.
72f4393d 2828
c906108c
SS		 2829Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2830
2831 * Makefile.in (interp.o): Depends on sim-main.h
2832
2833 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2834
2835 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2836 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2837 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2838 STATE, DSSTATE): Define
2839 (GPR, FGRIDX, ..): Define.
2840
2841 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2842 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2843 (GPR, FGRIDX, ...): Delete macros.
72f4393d 2844
c906108c 2845 * interp.c: Update names to match defines from sim-main.h
72f4393d 2846
c906108c
SS		 2847Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2848
2849 * interp.c (sim_monitor): Add SD argument.
2850 (sim_warning): Delete. Replace calls with calls to
2851 sim_io_eprintf.
2852 (sim_error): Delete. Replace calls with sim_io_error.
2853 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2854 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2855 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2856 argument.
2857 (mips_size): Rename from sim_size. Add SD argument.
2858
2859 * interp.c (simulator): Delete global variable.
2860 (callback): Delete global variable.
2861 (mips_option_handler, sim_open, sim_write, sim_read,
2862 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2863 sim_size,sim_monitor): Use sim_io_* not callback->*.
2864 (sim_open): ZALLOC simulator struct.
2865 (PROFILE): Do not define.
2866
2867Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2868
2869 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2870 support.h with corresponding code.
2871
2872 * sim-main.h (word64, uword64), support.h: Move definition to
2873 sim-main.h.
2874 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2875
2876 * support.h: Delete
2877 * Makefile.in: Update dependencies
2878 * interp.c: Do not include.
72f4393d 2879
c906108c
SS		 2880Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2881
2882 * interp.c (address_translation, load_memory, store_memory,
2883 cache_op): Rename to from AddressTranslation et.al., make global,
2884 add SD argument
72f4393d 2885
c906108c
SS		 2886 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2887 CacheOp): Define.
72f4393d 2888
c906108c
SS		 2889 * interp.c (SignalException): Rename to signal_exception, make
2890 global.
2891
2892 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
72f4393d 2893
c906108c
SS		 2894 * sim-main.h (SignalException, SignalExceptionInterrupt,
2895 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2896 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2897 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2898 Define.
72f4393d 2899
c906108c 2900 * interp.c, support.h: Use.
72f4393d 2901
c906108c
SS		 2902Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2903
2904 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2905 to value_fpr / store_fpr. Add SD argument.
2906 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2907 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2908
2909 * sim-main.h (ValueFPR, StoreFPR): Define.
72f4393d 2910
c906108c
SS		 2911Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2912
2913 * interp.c (sim_engine_run): Check consistency between configure
2914 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2915 and HASFPU.
2916
2917 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
72f4393d 2918 (mips_fpu): Configure WITH_FLOATING_POINT.
c906108c
SS		 2919 (mips_endian): Configure WITH_TARGET_ENDIAN.
2920 * configure: Update.
2921
2922Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2923
2924 * configure: Regenerated to track ../common/aclocal.m4 changes.
2925
2926Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2927
2928 * configure: Regenerated.
2929
2930Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2931
2932 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2933
2934Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2935
2936 * gencode.c (print_igen_insn_models): Assume certain architectures
2937 include all mips* instructions.
2938 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2939 instruction.
2940
2941 * Makefile.in (tmp.igen): Add target. Generate igen input from
2942 gencode file.
2943
2944 * gencode.c (FEATURE_IGEN): Define.
2945 (main): Add --igen option. Generate output in igen format.
2946 (process_instructions): Format output according to igen option.
2947 (print_igen_insn_format): New function.
2948 (print_igen_insn_models): New function.
2949 (process_instructions): Only issue warnings and ignore
2950 instructions when no FEATURE_IGEN.
2951
2952Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2953
2954 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2955 MIPS targets.
2956
2957Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2958
2959 * configure: Regenerated to track ../common/aclocal.m4 changes.
2960
2961Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2962
2963 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2964 SIM_RESERVED_BITS): Delete, moved to common.
2965 (SIM_EXTRA_CFLAGS): Update.
72f4393d 2966
c906108c
SS		 2967Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2968
2969 * configure.in: Configure non-strict memory alignment.
2970 * configure: Regenerated to track ../common/aclocal.m4 changes.
2971
2972Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2973
2974 * configure: Regenerated to track ../common/aclocal.m4 changes.
2975
2976Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2977
2978 * gencode.c (SDBBP,DERET): Added (3900) insns.
2979 (RFE): Turn on for 3900.
2980 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2981 (dsstate): Made global.
2982 (SUBTARGET_R3900): Added.
2983 (CANCELDELAYSLOT): New.
2984 (SignalException): Ignore SystemCall rather than ignore and
2985 terminate. Add DebugBreakPoint handling.
2986 (decode_coproc): New insns RFE, DERET; and new registers Debug
2987 and DEPC protected by SUBTARGET_R3900.
2988 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2989 bits explicitly.
2990 * Makefile.in,configure.in: Add mips subtarget option.
72f4393d 2991 * configure: Update.
c906108c
SS		 2992
2993Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2994
2995 * gencode.c: Add r3900 (tx39).
72f4393d 2996
c906108c
SS		 2997
2998Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2999
3000 * gencode.c (build_instruction): Don't need to subtract 4 for
3001 JALR, just 2.
3002
3003Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
3004
3005 * interp.c: Correct some HASFPU problems.
3006
3007Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
3008
3009 * configure: Regenerated to track ../common/aclocal.m4 changes.
3010
3011Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3012
3013 * interp.c (mips_options): Fix samples option short form, should
3014 be `x'.
3015
3016Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
3017
3018 * interp.c (sim_info): Enable info code. Was just returning.
3019
3020Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3021
3022 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
3023 MFC0.
3024
3025Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
3026
3027 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
3028 constants.
3029 (build_instruction): Ditto for LL.
3030
3031Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
3032
3033 * configure: Regenerated to track ../common/aclocal.m4 changes.
3034
3035Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3036
3037 * configure: Regenerated to track ../common/aclocal.m4 changes.
3038 * config.in: Ditto.
3039
3040Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
3041
3042 * interp.c (sim_open): Add call to sim_analyze_program, update
3043 call to sim_config.
3044
3045Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
3046
3047 * interp.c (sim_kill): Delete.
3048 (sim_create_inferior): Add ABFD argument. Set PC from same.
3049 (sim_load): Move code initializing trap handlers from here.
3050 (sim_open): To here.
3051 (sim_load): Delete, use sim-hload.c.
3052
3053 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
3054
3055Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3056
3057 * configure: Regenerated to track ../common/aclocal.m4 changes.
3058 * config.in: Ditto.
3059
3060Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3061
3062 * interp.c (sim_open): Add ABFD argument.
3063 (sim_load): Move call to sim_config from here.
3064 (sim_open): To here. Check return status.
3065
3066Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
72f4393d 3067
c906108c
SS		 3068 * gencode.c (build_instruction): Two arg MADD should
3069 not assign result to $0.
72f4393d 3070
c906108c
SS		 3071Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
3072
3073 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
3074 * sim/mips/configure.in: Regenerate.
3075
3076Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
3077
3078 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
3079 signed8, unsigned8 et.al. types.
3080
3081 * interp.c (SUB_REG_FETCH): Handle both little and big endian
3082 hosts when selecting subreg.
3083
3084Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
3085
3086 * interp.c (sim_engine_run): Reset the ZERO register to zero
3087 regardless of FEATURE_WARN_ZERO.
3088 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
3089
3090Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
3091
3092 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
3093 (SignalException): For BreakPoints ignore any mode bits and just
3094 save the PC.
3095 (SignalException): Always set the CAUSE register.
3096
3097Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
3098
3099 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
3100 exception has been taken.
3101
3102 * interp.c: Implement the ERET and mt/f sr instructions.
3103
3104Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
3105
3106 * interp.c (SignalException): Don't bother restarting an
3107 interrupt.
3108
3109Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3110
3111 * interp.c (SignalException): Really take an interrupt.
3112 (interrupt_event): Only deliver interrupts when enabled.
3113
3114Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
3115
3116 * interp.c (sim_info): Only print info when verbose.
3117 (sim_info) Use sim_io_printf for output.
72f4393d 3118
c906108c
SS		 3119Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3120
3121 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
3122 mips architectures.
3123
3124Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3125
3126 * interp.c (sim_do_command): Check for common commands if a
3127 simulator specific command fails.
3128
3129Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
3130
3131 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
3132 and simBE when DEBUG is defined.
3133
3134Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
3135
3136 * interp.c (interrupt_event): New function. Pass exception event
3137 onto exception handler.
3138
3139 * configure.in: Check for stdlib.h.
3140 * configure: Regenerate.
3141
3142 * gencode.c (build_instruction): Add UNUSED attribute to tempS
3143 variable declaration.
3144 (build_instruction): Initialize memval1.
3145 (build_instruction): Add UNUSED attribute to byte, bigend,
3146 reverse.
3147 (build_operands): Ditto.
3148
3149 * interp.c: Fix GCC warnings.
3150 (sim_get_quit_code): Delete.
3151
3152 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
3153 * Makefile.in: Ditto.
3154 * configure: Re-generate.
72f4393d 3155
c906108c
SS		 3156 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
3157
3158Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
3159
3160 * interp.c (mips_option_handler): New function parse argumes using
3161 sim-options.
3162 (myname): Replace with STATE_MY_NAME.
3163 (sim_open): Delete check for host endianness - performed by
3164 sim_config.
3165 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
3166 (sim_open): Move much of the initialization from here.
3167 (sim_load): To here. After the image has been loaded and
3168 endianness set.
3169 (sim_open): Move ColdReset from here.
3170 (sim_create_inferior): To here.
3171 (sim_open): Make FP check less dependant on host endianness.
3172
3173 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
3174 run.
3175 * interp.c (sim_set_callbacks): Delete.
3176
3177 * interp.c (membank, membank_base, membank_size): Replace with
3178 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
3179 (sim_open): Remove call to callback->init. gdb/run do this.
3180
3181 * interp.c: Update
3182
3183 * sim-main.h (SIM_HAVE_FLATMEM): Define.
3184
3185 * interp.c (big_endian_p): Delete, replaced by
3186 current_target_byte_order.
3187
3188Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3189
3190 * interp.c (host_read_long, host_read_word, host_swap_word,
3191 host_swap_long): Delete. Using common sim-endian.
3192 (sim_fetch_register, sim_store_register): Use H2T.
3193 (pipeline_ticks): Delete. Handled by sim-events.
3194 (sim_info): Update.
3195 (sim_engine_run): Update.
3196
3197Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
3198
3199 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
3200 reason from here.
3201 (SignalException): To here. Signal using sim_engine_halt.
3202 (sim_stop_reason): Delete, moved to common.
72f4393d 3203
c906108c
SS		 3204Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
3205
3206 * interp.c (sim_open): Add callback argument.
3207 (sim_set_callbacks): Delete SIM_DESC argument.
3208 (sim_size): Ditto.
3209
3210Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3211
3212 * Makefile.in (SIM_OBJS): Add common modules.
3213
3214 * interp.c (sim_set_callbacks): Also set SD callback.
3215 (set_endianness, xfer_*, swap_*): Delete.
3216 (host_read_word, host_read_long, host_swap_word, host_swap_long):
3217 Change to functions using sim-endian macros.
3218 (control_c, sim_stop): Delete, use common version.
3219 (simulate): Convert into.
3220 (sim_engine_run): This function.
3221 (sim_resume): Delete.
72f4393d 3222
c906108c
SS		 3223 * interp.c (simulation): New variable - the simulator object.
3224 (sim_kind): Delete global - merged into simulation.
3225 (sim_load): Cleanup. Move PC assignment from here.
3226 (sim_create_inferior): To here.
3227
3228 * sim-main.h: New file.
3229 * interp.c (sim-main.h): Include.
72f4393d 3230
c906108c
SS		 3231Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
3232
3233 * configure: Regenerated to track ../common/aclocal.m4 changes.
3234
3235Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
3236
3237 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
3238
3239Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
3240
72f4393d
L		 3241 * gencode.c (build_instruction): DIV instructions: check
3242 for division by zero and integer overflow before using
c906108c
SS		 3243 host's division operation.
3244
3245Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
3246
3247 * Makefile.in (SIM_OBJS): Add sim-load.o.
3248 * interp.c: #include bfd.h.
3249 (target_byte_order): Delete.
3250 (sim_kind, myname, big_endian_p): New static locals.
3251 (sim_open): Set sim_kind, myname. Move call to set_endianness to
3252 after argument parsing. Recognize -E arg, set endianness accordingly.
3253 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
3254 load file into simulator. Set PC from bfd.
3255 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
3256 (set_endianness): Use big_endian_p instead of target_byte_order.
3257
3258Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
3259
3260 * interp.c (sim_size): Delete prototype - conflicts with
3261 definition in remote-sim.h. Correct definition.
3262
3263Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3264
3265 * configure: Regenerated to track ../common/aclocal.m4 changes.
3266 * config.in: Ditto.
3267
3268Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
3269
3270 * interp.c (sim_open): New arg `kind'.
3271
3272 * configure: Regenerated to track ../common/aclocal.m4 changes.
3273
3274Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3275
3276 * configure: Regenerated to track ../common/aclocal.m4 changes.
3277
3278Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
3279
3280 * interp.c (sim_open): Set optind to 0 before calling getopt.
3281
3282Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3283
3284 * configure: Regenerated to track ../common/aclocal.m4 changes.
3285
3286Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
3287
3288 * interp.c : Replace uses of pr_addr with pr_uword64
3289 where the bit length is always 64 independent of SIM_ADDR.
3290 (pr_uword64) : added.
3291
3292Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3293
3294 * configure: Re-generate.
3295
3296Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
3297
3298 * configure: Regenerate to track ../common/aclocal.m4 changes.
3299
3300Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
3301
3302 * interp.c (sim_open): New SIM_DESC result. Argument is now
3303 in argv form.
3304 (other sim_*): New SIM_DESC argument.
3305
3306Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
3307
3308 * interp.c: Fix printing of addresses for non-64-bit targets.
3309 (pr_addr): Add function to print address based on size.
3310
3311Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
3312
3313 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
3314
3315Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
3316
3317 * gencode.c (build_mips16_operands): Correct computation of base
3318 address for extended PC relative instruction.
3319
3320Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
3321
3322 * interp.c (mips16_entry): Add support for floating point cases.
3323 (SignalException): Pass floating point cases to mips16_entry.
3324 (ValueFPR): Don't restrict fmt_single and fmt_word to even
3325 registers.
3326 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
3327 or fmt_word.
3328 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
3329 and then set the state to fmt_uninterpreted.
3330 (COP_SW): Temporarily set the state to fmt_word while calling
3331 ValueFPR.
3332
3333Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
3334
3335 * gencode.c (build_instruction): The high order may be set in the
3336 comparison flags at any ISA level, not just ISA 4.
3337
3338Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
3339
3340 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
3341 COMMON_{PRE,POST}_CONFIG_FRAG instead.
3342 * configure.in: sinclude ../common/aclocal.m4.
3343 * configure: Regenerated.
3344
3345Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
3346
3347 * configure: Rebuild after change to aclocal.m4.
3348
3349Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
3350
3351 * configure configure.in Makefile.in: Update to new configure
3352 scheme which is more compatible with WinGDB builds.
3353 * configure.in: Improve comment on how to run autoconf.
3354 * configure: Re-run autoconf to get new ../common/aclocal.m4.
3355 * Makefile.in: Use autoconf substitution to install common
3356 makefile fragment.
3357
3358Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
3359
3360 * gencode.c (build_instruction): Use BigEndianCPU instead of
3361 ByteSwapMem.
3362
3363Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
3364
3365 * interp.c (sim_monitor): Make output to stdout visible in
3366 wingdb's I/O log window.
3367
3368Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
3369
3370 * support.h: Undo previous change to SIGTRAP
3371 and SIGQUIT values.
3372
3373Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
3374
3375 * interp.c (store_word, load_word): New static functions.
3376 (mips16_entry): New static function.
3377 (SignalException): Look for mips16 entry and exit instructions.
3378 (simulate): Use the correct index when setting fpr_state after
3379 doing a pending move.
3380
3381Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
3382
3383 * interp.c: Fix byte-swapping code throughout to work on
3384 both little- and big-endian hosts.
3385
3386Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
3387
3388 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3389 with gdb/config/i386/xm-windows.h.
3390
3391Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
3392
3393 * gencode.c (build_instruction): Work around MSVC++ code gen bug
3394 that messes up arithmetic shifts.
3395
3396Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
3397
3398 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
3399 SIGTRAP and SIGQUIT for _WIN32.
3400
3401Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3402
3403 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3404 force a 64 bit multiplication.
3405 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3406 destination register is 0, since that is the default mips16 nop
3407 instruction.
3408
3409Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3410
3411 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3412 (build_endian_shift): Don't check proc64.
3413 (build_instruction): Always set memval to uword64. Cast op2 to
3414 uword64 when shifting it left in memory instructions. Always use
3415 the same code for stores--don't special case proc64.
3416
3417 * gencode.c (build_mips16_operands): Fix base PC value for PC
3418 relative operands.
3419 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3420 jal instruction.
3421 * interp.c (simJALDELAYSLOT): Define.
3422 (JALDELAYSLOT): Define.
3423 (INDELAYSLOT, INJALDELAYSLOT): Define.
3424 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3425
3426Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3427
3428 * interp.c (sim_open): add flush_cache as a PMON routine
3429 (sim_monitor): handle flush_cache by ignoring it
3430
3431Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3432
3433 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3434 BigEndianMem.
3435 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3436 (BigEndianMem): Rename to ByteSwapMem and change sense.
3437 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3438 BigEndianMem references to !ByteSwapMem.
3439 (set_endianness): New function, with prototype.
3440 (sim_open): Call set_endianness.
3441 (sim_info): Use simBE instead of BigEndianMem.
3442 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3443 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3444 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3445 ifdefs, keeping the prototype declaration.
3446 (swap_word): Rewrite correctly.
3447 (ColdReset): Delete references to CONFIG. Delete endianness related
3448 code; moved to set_endianness.
72f4393d 3449
c906108c
SS		 3450Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3451
3452 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3453 * interp.c (CHECKHILO): Define away.
3454 (simSIGINT): New macro.
3455 (membank_size): Increase from 1MB to 2MB.
3456 (control_c): New function.
3457 (sim_resume): Rename parameter signal to signal_number. Add local
3458 variable prev. Call signal before and after simulate.
3459 (sim_stop_reason): Add simSIGINT support.
3460 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3461 functions always.
3462 (sim_warning): Delete call to SignalException. Do call printf_filtered
3463 if logfh is NULL.
3464 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3465 a call to sim_warning.
3466
3467Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3468
3469 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3470 16 bit instructions.
3471
3472Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3473
3474 Add support for mips16 (16 bit MIPS implementation):
3475 * gencode.c (inst_type): Add mips16 instruction encoding types.
3476 (GETDATASIZEINSN): Define.
3477 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3478 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3479 mtlo.
3480 (MIPS16_DECODE): New table, for mips16 instructions.
3481 (bitmap_val): New static function.
3482 (struct mips16_op): Define.
3483 (mips16_op_table): New table, for mips16 operands.
3484 (build_mips16_operands): New static function.
3485 (process_instructions): If PC is odd, decode a mips16
3486 instruction. Break out instruction handling into new
3487 build_instruction function.
3488 (build_instruction): New static function, broken out of
3489 process_instructions. Check modifiers rather than flags for SHIFT
3490 bit count and m[ft]{hi,lo} direction.
3491 (usage): Pass program name to fprintf.
3492 (main): Remove unused variable this_option_optind. Change
3493 ``*loptarg++'' to ``loptarg++''.
3494 (my_strtoul): Parenthesize && within ||.
3495 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3496 (simulate): If PC is odd, fetch a 16 bit instruction, and
3497 increment PC by 2 rather than 4.
3498 * configure.in: Add case for mips16*-*-*.
3499 * configure: Rebuild.
3500
3501Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3502
3503 * interp.c: Allow -t to enable tracing in standalone simulator.
3504 Fix garbage output in trace file and error messages.
3505
3506Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3507
3508 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3509 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3510 * configure.in: Simplify using macros in ../common/aclocal.m4.
3511 * configure: Regenerated.
3512 * tconfig.in: New file.
3513
3514Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3515
3516 * interp.c: Fix bugs in 64-bit port.
3517 Use ansi function declarations for msvc compiler.
3518 Initialize and test file pointer in trace code.
3519 Prevent duplicate definition of LAST_EMED_REGNUM.
3520
3521Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3522
3523 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3524
3525Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3526
3527 * interp.c (SignalException): Check for explicit terminating
3528 breakpoint value.
3529 * gencode.c: Pass instruction value through SignalException()
3530 calls for Trap, Breakpoint and Syscall.
3531
3532Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3533
3534 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3535 only used on those hosts that provide it.
3536 * configure.in: Add sqrt() to list of functions to be checked for.
3537 * config.in: Re-generated.
3538 * configure: Re-generated.
3539
3540Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3541
3542 * gencode.c (process_instructions): Call build_endian_shift when
3543 expanding STORE RIGHT, to fix swr.
3544 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3545 clear the high bits.
3546 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3547 Fix float to int conversions to produce signed values.
3548
3549Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3550
3551 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3552 (process_instructions): Correct handling of nor instruction.
3553 Correct shift count for 32 bit shift instructions. Correct sign
3554 extension for arithmetic shifts to not shift the number of bits in
3555 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3556 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3557 Fix madd.
3558 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3559 It's OK to have a mult follow a mult. What's not OK is to have a
3560 mult follow an mfhi.
3561 (Convert): Comment out incorrect rounding code.
3562
3563Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3564
3565 * interp.c (sim_monitor): Improved monitor printf
3566 simulation. Tidied up simulator warnings, and added "--log" option
3567 for directing warning message output.
3568 * gencode.c: Use sim_warning() rather than WARNING macro.
3569
3570Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3571
3572 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3573 getopt1.o, rather than on gencode.c. Link objects together.
3574 Don't link against -liberty.
3575 (gencode.o, getopt.o, getopt1.o): New targets.
3576 * gencode.c: Include <ctype.h> and "ansidecl.h".
3577 (AND): Undefine after including "ansidecl.h".
3578 (ULONG_MAX): Define if not defined.
3579 (OP_*): Don't define macros; now defined in opcode/mips.h.
3580 (main): Call my_strtoul rather than strtoul.
3581 (my_strtoul): New static function.
3582
3583Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3584
3585 * gencode.c (process_instructions): Generate word64 and uword64
3586 instead of `long long' and `unsigned long long' data types.
3587 * interp.c: #include sysdep.h to get signals, and define default
3588 for SIGBUS.
3589 * (Convert): Work around for Visual-C++ compiler bug with type
3590 conversion.
3591 * support.h: Make things compile under Visual-C++ by using
3592 __int64 instead of `long long'. Change many refs to long long
3593 into word64/uword64 typedefs.
3594
3595Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3596
72f4393d
L		 3597 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3598 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3599 (docdir): Removed.
3600 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3601 (AC_PROG_INSTALL): Added.
c906108c 3602 (AC_PROG_CC): Moved to before configure.host call.
72f4393d
L		 3603 * configure: Rebuilt.
3604
c906108c
SS		 3605Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3606
3607 * configure.in: Define @SIMCONF@ depending on mips target.
3608 * configure: Rebuild.
3609 * Makefile.in (run): Add @SIMCONF@ to control simulator
3610 construction.
3611 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3612 * interp.c: Remove some debugging, provide more detailed error
3613 messages, update memory accesses to use LOADDRMASK.
72f4393d 3614
c906108c
SS		 3615Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3616
3617 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3618 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3619 stamp-h.
3620 * configure: Rebuild.
3621 * config.in: New file, generated by autoheader.
3622 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3623 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3624 HAVE_ANINT and HAVE_AINT, as appropriate.
3625 * Makefile.in (run): Use @LIBS@ rather than -lm.
3626 (interp.o): Depend upon config.h.
3627 (Makefile): Just rebuild Makefile.
3628 (clean): Remove stamp-h.
3629 (mostlyclean): Make the same as clean, not as distclean.
3630 (config.h, stamp-h): New targets.
3631
3632Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3633
3634 * interp.c (ColdReset): Fix boolean test. Make all simulator
3635 globals static.
3636
3637Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3638
3639 * interp.c (xfer_direct_word, xfer_direct_long,
3640 swap_direct_word, swap_direct_long, xfer_big_word,
3641 xfer_big_long, xfer_little_word, xfer_little_long,
3642 swap_word,swap_long): Added.
3643 * interp.c (ColdReset): Provide function indirection to
3644 host<->simulated_target transfer routines.
3645 * interp.c (sim_store_register, sim_fetch_register): Updated to
3646 make use of indirected transfer routines.
3647
3648Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3649
3650 * gencode.c (process_instructions): Ensure FP ABS instruction
3651 recognised.
3652 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3653 system call support.
3654
3655Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3656
3657 * interp.c (sim_do_command): Complain if callback structure not
3658 initialised.
3659
3660Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3661
3662 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3663 support for Sun hosts.
3664 * Makefile.in (gencode): Ensure the host compiler and libraries
3665 used for cross-hosted build.
3666
3667Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3668
3669 * interp.c, gencode.c: Some more (TODO) tidying.
3670
3671Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3672
3673 * gencode.c, interp.c: Replaced explicit long long references with
3674 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3675 * support.h (SET64LO, SET64HI): Macros added.
3676
3677Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3678
3679 * configure: Regenerate with autoconf 2.7.
3680
3681Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3682
3683 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3684 * support.h: Remove superfluous "1" from #if.
3685 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3686
3687Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3688
3689 * interp.c (StoreFPR): Control UndefinedResult() call on
3690 WARN_RESULT manifest.
3691
3692Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3693
3694 * gencode.c: Tidied instruction decoding, and added FP instruction
3695 support.
3696
3697 * interp.c: Added dineroIII, and BSD profiling support. Also
3698 run-time FP handling.
3699
3700Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3701
3702 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3703 gencode.c, interp.c, support.h: created.
GDB Binutils - Deliverables
This page took 0.841593 seconds and 4 git commands to generate.