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mips: Add multi-processor support for r5900. Others might work.
[deliverable/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
01737f42
AC		 1Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2
3 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
4 size.
5
6 * interp.c (SD, CPU): Define.
7 (mips_option_handler): Set flags in each CPU.
8 (interrupt_event): Assume CPU 0 is the one being iterrupted.
9 (sim_close): Do not clear STATE, deleted anyway.
10 (sim_write, sim_read): Assume CPU zero's vm should be used for
11 data transfers.
12 (sim_create_inferior): Set the PC for all processors.
13 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
14 argument.
15 (mips16_entry): Pass correct nr of args to store_word, load_word.
16 (ColdReset): Cold reset all cpu's.
17 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
18 (sim_monitor, load_memory, store_memory, signal_exception): Use
19 `CPU' instead of STATE_CPU.
20
21
22 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
23 SD or CPU_.
24
25 * sim-main.h (signal_exception): Add sim_cpu arg.
26 (SignalException*): Pass both SD and CPU to signal_exception.
27 * interp.c (signal_exception): Update.
28
29 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
30 Ditto
31 (sync_operation, prefetch, cache_op, store_memory, load_memory,
32 address_translation): Ditto
33 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
34
35start-sanitize-vr5400
36 * mdmx.igen (get_scale): Pass CPU_ to semantic_illegal instead of
37 `sd'.
38 (ByteAlign): Use StoreFPR, pass args in correct order.
39
40end-sanitize-vr5400
41start-sanitize-r5900
42Sun Feb 1 10:59:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
43
44 * configure.in (sim_igen_filter): For r5900, configure as SMP.
45
46end-sanitize-r5900
412c4e94
AC		 47Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
48
49 * configure: Regenerated to track ../common/aclocal.m4 changes.
50
9ec6741b
AC		 51Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
52
c4db5b04
AC		 53start-sanitize-r5900
54 * configure.in (sim_igen_filter): For r5900, use igen.
55 * configure: Re-generate.
56
57end-sanitize-r5900
9ec6741b
AC		 58 * interp.c (sim_engine_run): Add `nr_cpus' argument.
59
60 * mips.igen (model): Map processor names onto BFD name.
61
62 * sim-main.h (CPU_CIA): Delete.
63 (SET_CIA, GET_CIA): Define
64
2d44e12a
AC		 65Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
66
67 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
68 regiser.
69
70 * configure.in (default_endian): Configure a big-endian simulator
71 by default.
72 * configure: Re-generate.
73
462cfbc4
DE		 74Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
75
76 * configure: Regenerated to track ../common/aclocal.m4 changes.
77
e0e0fc76
MA		 78Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
79
80 * interp.c (sim_monitor): Handle Densan monitor outbyte
81 and inbyte functions.
82
76ef4165
FL		 831997-12-29 Felix Lee <flee@cygnus.com>
84
85 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
86
87Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
88
89 * Makefile.in (tmp-igen): Arrange for $zero to always be
90 reset to zero after every instruction.
91
9c8ec16d
AC		 92Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
93
94 * configure: Regenerated to track ../common/aclocal.m4 changes.
95 * config.in: Ditto.
96
255cbbf1 97start-sanitize-vr5400
b17d2d14
AC		 98Sat Dec 13 15:18:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
99
100 * vr5400.igen (Low32Bits, High32Bits): Sign extend extracted 32
101 bit values.
102
103end-sanitize-vr5400
104start-sanitize-vr5400
255cbbf1
JL		 105Fri Dec 12 12:26:07 1997 Jeffrey A Law (law@cygnus.com)
106
107 * configure.in (sim_igen_filter): Multi-sim vr5000 - vr5000 or
108 vr5400 with the vr5000 as the default.
109
110end-sanitize-vr5400
23850e92
JL		 111Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
112
113 * mips.igen (MSUB): Fix to work like MADD.
114 * gencode.c (MSUB): Similarly.
115
c02ed6a8
AC		 116start-sanitize-vr5400
117Tue Dec 9 12:02:12 1997 Andrew Cagney <cagney@b1.cygnus.com>
118
119 * configure.in (sim_igen_filter): Multi-sim vr5400 - vr5000 or
120 vr5400.
121
122end-sanitize-vr5400
6e51f990
DE		 123Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
124
125 * configure: Regenerated to track ../common/aclocal.m4 changes.
126
35c246c9
AC		 127Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
128
129 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
130
131start-sanitize-vr5400
0d5d0d10 132 * mdmx.igen (value_vr): Correct sim_io_eprintf format argument.
0931ce5a 133 (value_cc, store_cc): Implement.
0d5d0d10 134
35c246c9
AC		 135 * sim-main.h: Add 8*3*8 bit accumulator.
136
137 * vr5400.igen: Move mdmx instructins from here
138 * mdmx.igen: To here - new file. Add/fix missing instructions.
139 * mips.igen: Include mdmx.igen.
0931ce5a 140 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
35c246c9 141
c02ed6a8 142end-sanitize-vr5400
58fb5d0a
AC		 143Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
144
145 * sim-main.h (sim-fpu.h): Include.
146
147 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
148 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
149 using host independant sim_fpu module.
150
a09a30d2
AC		 151Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
152
232156de
AC		 153 * interp.c (signal_exception): Report internal errors with SIGABRT
154 not SIGQUIT.
a09a30d2 155
232156de
AC		 156 * sim-main.h (C0_CONFIG): New register.
157 (signal.h): No longer include.
158
159 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
a09a30d2 160
486740ce
DE		 161Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
162
163 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
164
f23e93da
AC		 165Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
166
167 * mips.igen: Tag vr5000 instructions.
168 (ANDI): Was missing mipsIV model, fix assembler syntax.
169 (do_c_cond_fmt): New function.
170 (C.cond.fmt): Handle mips I-III which do not support CC field
171 separatly.
172 (bc1): Handle mips IV which do not have a delaed FCC separatly.
173 (SDR): Mask paddr when BigEndianMem, not the converse as specified
174 in IV3.2 spec.
175 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
176 vr5000 which saves LO in a GPR separatly.
177
178 * configure.in (enable-sim-igen): For vr5000, select vr5000
179 specific instructions.
180 * configure: Re-generate.
181
182Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
183
184 * Makefile.in (SIM_OBJS): Add sim-fpu module.
185
186 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
187 fmt_uninterpreted_64 bit cases to switch. Convert to
188 fmt_formatted,
189
190 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
191
192 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
193 as specified in IV3.2 spec.
194 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
195
030843d7
AC		 196Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
197
198 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
199 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
200 (start-sanitize-r5900):
201 (LWXC1, SWXC1): Delete from r5900 instruction set.
202 (end-sanitize-r5900):
203 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
a94c5493 204 PENDING_FILL versions of instructions. Simplify.
030843d7
AC		 205 (X): New function.
206 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
207 instructions.
a94c5493
AC		 208 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
209 a signed value.
030843d7
AC		 210 (MTHI, MFHI): Disable code checking HI-LO.
211
212 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
213 global.
214 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
215
7ce8b917
AC		 216Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
217
95469ceb
AC		 218 * gencode.c (build_mips16_operands): Replace IPC with cia.
219
220 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
221 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
222 IPC to `cia'.
223 (UndefinedResult): Replace function with macro/function
224 combination.
225 (sim_engine_run): Don't save PC in IPC.
226
227 * sim-main.h (IPC): Delete.
228
229 start-sanitize-vr5400
230 * vr5400.igen (vr): Add missing cia argument to value_fpr.
231 (do_select): Rename function select.
232 end-sanitize-vr5400
233
7ce8b917
AC		 234 * interp.c (signal_exception, store_word, load_word,
235 address_translation, load_memory, store_memory, cache_op,
236 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
95469ceb
AC		 237 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
238 current instruction address - cia - argument.
7ce8b917
AC		 239 (sim_read, sim_write): Call address_translation directly.
240 (sim_engine_run): Rename variable vaddr to cia.
95469ceb
AC		 241 (signal_exception): Pass cia to sim_monitor
242
7ce8b917
AC		 243 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
244 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
245 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
246
247 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
248 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
249 SIM_ASSERT.
250
251 * interp.c (signal_exception): Pass restart address to
252 sim_engine_restart.
253
254 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
255 idecode.o): Add dependency.
256
257 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
258 Delete definitions
259 (DELAY_SLOT): Update NIA not PC with branch address.
260 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
261
262 * mips.igen: Use CIA not PC in branch calculations.
263 (illegal): Call SignalException.
264 (BEQ, ADDIU): Fix assembler.
265
63be8feb
AC		 266Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
267
44b8585a
AC		 268 * m16.igen (JALX): Was missing.
269
270 * configure.in (enable-sim-igen): New configuration option.
271 * configure: Re-generate.
272
63be8feb
AC		 273 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
274
275 * interp.c (load_memory, store_memory): Delete parameter RAW.
276 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
277 bypassing {load,store}_memory.
278
279 * sim-main.h (ByteSwapMem): Delete definition.
280
281 * Makefile.in (SIM_OBJS): Add sim-memopt module.
282
283 * interp.c (sim_do_command, sim_commands): Delete mips specific
284 commands. Handled by module sim-options.
285
286 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
287 (WITH_MODULO_MEMORY): Define.
288
289 * interp.c (sim_info): Delete code printing memory size.
290
291 * interp.c (mips_size): Nee sim_size, delete function.
292 (power2): Delete.
293 (monitor, monitor_base, monitor_size): Delete global variables.
294 (sim_open, sim_close): Delete code creating monitor and other
295 memory regions. Use sim-memopts module, via sim_do_commandf, to
296 manage memory regions.
297 (load_memory, store_memory): Use sim-core for memory model.
298
299 * interp.c (address_translation): Delete all memory map code
300 except line forcing 32 bit addresses.
301
22de994d
AC		 302Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
303
304 * sim-main.h (WITH_TRACE): Delete definition. Enables common
305 trace options.
306
307 * interp.c (logfh, logfile): Delete globals.
308 (sim_open, sim_close): Delete code opening & closing log file.
309 (mips_option_handler): Delete -l and -n options.
310 (OPTION mips_options): Ditto.
311
312 * interp.c (OPTION mips_options): Rename option trace to dinero.
313 (mips_option_handler): Update.
314
525d929e
AC		 315Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
316
317 * interp.c (fetch_str): New function.
318 (sim_monitor): Rewrite using sim_read & sim_write.
319 (sim_open): Check magic number.
320 (sim_open): Write monitor vectors into memory using sim_write.
321 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
322 (sim_read, sim_write): Simplify - transfer data one byte at a
323 time.
324 (load_memory, store_memory): Clarify meaning of parameter RAW.
325
326 * sim-main.h (isHOST): Defete definition.
327 (isTARGET): Mark as depreciated.
328 (address_translation): Delete parameter HOST.
329
330 * interp.c (address_translation): Delete parameter HOST.
331
6205f379
GRK		 332start-sanitize-tx49
333Wed Oct 29 14:21:32 1997 Gavin Koch <gavin@cygnus.com>
334
335 * gencode.c: Add tx49 configury and insns.
336 * configure.in: Add tx49 configury.
337 * configure: Update.
338
339end-sanitize-tx49
01b9cd49
AC		 340Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
341
342 * mips.igen:
343
344 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
345 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
346
89d09738
AC		 347Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
348
349 * mips.igen: Add model filter field to records.
350
16bd5d6e
AC		 351Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
352
353 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
354
355 interp.c (sim_engine_run): Do not compile function sim_engine_run
356 when WITH_IGEN == 1.
357
358 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
359 target architecture.
360
361 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
362 igen. Replace with configuration variables sim_igen_flags /
363 sim_m16_flags.
364
16bd5d6e 365 start-sanitize-r5900
8c31916d
AC		 366 * r5900.igen: New file. Copy r5900 insns here.
367 end-sanitize-r5900
16bd5d6e 368 start-sanitize-vr5400
58fb5d0a 369 * vr5400.igen: New file.
255cbbf1 370 end-sanitize-vr5400
16bd5d6e
AC		 371 * m16.igen: New file. Copy mips16 insns here.
372 * mips.igen: From here.
373
90ad43b2
AC		 374Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
375
376 start-sanitize-vr5400
377 * mips.igen: Tag all mipsIV instructions with vr5400 model.
378
379 * configure.in: Add mips64vr5400 target.
380 * configure: Re-generate.
381
382 end-sanitize-vr5400
383 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
384 to top.
385 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
386
635ae9cb
GRK		 387Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
388
389 * gencode.c (build_instruction): Follow sim_write's lead in using
390 BigEndianMem instead of !ByteSwapMem.
391
122edc03
AC		 392Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
393
394 * configure.in (sim_gen): Dependent on target, select type of
395 generator. Always select old style generator.
396
397 configure: Re-generate.
398
399 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
400 targets.
401 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
402 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
403 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
404 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
405 SIM_@sim_gen@_*, set by autoconf.
406
dad6f1f3
AC		 407Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
408
409 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
410
411 * interp.c (ColdReset): Remove #ifdef HASFPU, check
412 CURRENT_FLOATING_POINT instead.
413
414 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
415 (address_translation): Raise exception InstructionFetch when
416 translation fails and isINSTRUCTION.
417
418 * interp.c (sim_open, sim_write, sim_monitor, store_word,
419 sim_engine_run): Change type of of vaddr and paddr to
420 address_word.
421 (address_translation, prefetch, load_memory, store_memory,
422 cache_op): Change type of vAddr and pAddr to address_word.
423
424 * gencode.c (build_instruction): Change type of vaddr and paddr to
425 address_word.
426
92ad193b
AC		 427Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
428
429 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
430 macro to obtain result of ALU op.
431
aa324b9b
AC		 432Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
433
434 * interp.c (sim_info): Call profile_print.
435
e2f8ffb7
AC		 436Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
437
438 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
439
440 * sim-main.h (WITH_PROFILE): Do not define, defined in
441 common/sim-config.h. Use sim-profile module.
442 (simPROFILE): Delete defintion.
443
444 * interp.c (PROFILE): Delete definition.
445 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
446 (sim_close): Delete code writing profile histogram.
447 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
448 Delete.
449 (sim_engine_run): Delete code profiling the PC.
450
fb5a2a3e
AC		 451Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
452
453 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
454
455 * interp.c (sim_monitor): Make register pointers of type
456 unsigned_word*.
457
458 * sim-main.h: Make registers of type unsigned_word not
459 signed_word.
460
ea985d24
AC		 461Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
462
463start-sanitize-r5900
464 * sim-main.h (BYTES_IN_MMI_REGS, ..., SUB_REG_FETCH, ..., GPR_SB,
465 ...): Move to sim-main.h
466
467end-sanitize-r5900
468 * interp.c (sync_operation): Rename from SyncOperation, make
469 global, add SD argument.
470 (prefetch): Rename from Prefetch, make global, add SD argument.
471 (decode_coproc): Make global.
472
473 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
474
475 * gencode.c (build_instruction): Generate DecodeCoproc not
476 decode_coproc calls.
477
478 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
479 (SizeFGR): Move to sim-main.h
480 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
481 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
482 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
483 sim-main.h.
484 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
485 FP_RM_TOMINF, GETRM): Move to sim-main.h.
486 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
487 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
488 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
489 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
490
491 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
492 exception.
493 (sim-alu.h): Include.
494 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
495 (sim_cia): Typedef to instruction_address.
496
284e759d
AC		 497Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
498
499 * Makefile.in (interp.o): Rename generated file engine.c to
500 oengine.c.
501
502 * interp.c: Update.
503
339fb149
AC		 504Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
505
506 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
507
8b70f837
AC		 508Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
509
510 * gencode.c (build_instruction): For "FPSQRT", output correct
511 number of arguments to Recip.
512
0c2c5f61
AC		 513Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
514
515 * Makefile.in (interp.o): Depends on sim-main.h
516
517 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
518
519 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
520 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
521 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
522 STATE, DSSTATE): Define
523 (GPR, FGRIDX, ..): Define.
524
525 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
526 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
527 (GPR, FGRIDX, ...): Delete macros.
528
529 * interp.c: Update names to match defines from sim-main.h
530
18c64df6
AC		 531Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
532
533 * interp.c (sim_monitor): Add SD argument.
534 (sim_warning): Delete. Replace calls with calls to
535 sim_io_eprintf.
536 (sim_error): Delete. Replace calls with sim_io_error.
537 (open_trace, writeout32, writeout16, getnum): Add SD argument.
538 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
539 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
540 argument.
541 (mips_size): Rename from sim_size. Add SD argument.
542
543 * interp.c (simulator): Delete global variable.
544 (callback): Delete global variable.
545 (mips_option_handler, sim_open, sim_write, sim_read,
546 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
547 sim_size,sim_monitor): Use sim_io_* not callback->*.
548 (sim_open): ZALLOC simulator struct.
549 (PROFILE): Do not define.
550
551Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
552
553 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
554 support.h with corresponding code.
555
556 * sim-main.h (word64, uword64), support.h: Move definition to
557 sim-main.h.
558 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
559
560 * support.h: Delete
561 * Makefile.in: Update dependencies
562 * interp.c: Do not include.
563
564Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
565
566 * interp.c (address_translation, load_memory, store_memory,
567 cache_op): Rename to from AddressTranslation et.al., make global,
568 add SD argument
569
570 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
571 CacheOp): Define.
572
573 * interp.c (SignalException): Rename to signal_exception, make
574 global.
575
576 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
577
578 * sim-main.h (SignalException, SignalExceptionInterrupt,
579 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
580 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
581 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
582 Define.
583
584 * interp.c, support.h: Use.
585
586Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
587
588 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
589 to value_fpr / store_fpr. Add SD argument.
590 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
591 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
592
593 * sim-main.h (ValueFPR, StoreFPR): Define.
594
595Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
596
597 * interp.c (sim_engine_run): Check consistency between configure
598 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
599 and HASFPU.
600
601 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
602 (mips_fpu): Configure WITH_FLOATING_POINT.
603 (mips_endian): Configure WITH_TARGET_ENDIAN.
604 * configure: Update.
605
606Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
607
608 * configure: Regenerated to track ../common/aclocal.m4 changes.
609
adf4739e
AC		 610start-sanitize-r5900
611Mon Aug 25 19:11:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
612
613 * interp.c (MAX_REG): Allow up-to 128 registers.
614 (LO1, HI1): Define value that matches REGISTER_NAMES in gdb.
615 (REGISTER_SA): Ditto.
616 (sim_open): Initialize register_widths for r5900 specific
617 registers.
618 (sim_fetch_register, sim_store_register): Check for request of
619 r5900 specific SA register. Check for request for hi 64 bits of
620 r5900 specific registers.
621
622end-sanitize-r5900
26b20b0a
BM		 623Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
624
625 * configure: Regenerated.
626
6eedf3f4
MA		 627Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
628
629 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
630
e63bc706
AC		 631Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
632
6eedf3f4
MA		 633 * gencode.c (print_igen_insn_models): Assume certain architectures
634 include all mips* instructions.
635 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
636 instruction.
637
e63bc706
AC		 638 * Makefile.in (tmp.igen): Add target. Generate igen input from
639 gencode file.
640
641 * gencode.c (FEATURE_IGEN): Define.
642 (main): Add --igen option. Generate output in igen format.
643 (process_instructions): Format output according to igen option.
644 (print_igen_insn_format): New function.
645 (print_igen_insn_models): New function.
646 (process_instructions): Only issue warnings and ignore
647 instructions when no FEATURE_IGEN.
648
eb2e3c85
AC		 649Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
650
651 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
652 MIPS targets.
653
92f91d1f
AC		 654Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
655
656 * configure: Regenerated to track ../common/aclocal.m4 changes.
657
658Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
659
660 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
661 SIM_RESERVED_BITS): Delete, moved to common.
662 (SIM_EXTRA_CFLAGS): Update.
663
794e9ac9
AC		 664Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
665
76a6247f 666 * configure.in: Configure non-strict memory alignment.
794e9ac9
AC		 667 * configure: Regenerated to track ../common/aclocal.m4 changes.
668
b45caf05
AC		 669Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
670
671 * configure: Regenerated to track ../common/aclocal.m4 changes.
672
673Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
674
675 * gencode.c (SDBBP,DERET): Added (3900) insns.
676 (RFE): Turn on for 3900.
677 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
678 (dsstate): Made global.
679 (SUBTARGET_R3900): Added.
680 (CANCELDELAYSLOT): New.
681 (SignalException): Ignore SystemCall rather than ignore and
682 terminate. Add DebugBreakPoint handling.
683 (decode_coproc): New insns RFE, DERET; and new registers Debug
684 and DEPC protected by SUBTARGET_R3900.
685 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
686 bits explicitly.
687 * Makefile.in,configure.in: Add mips subtarget option.
688 * configure: Update.
689
7afa8d4e
GRK		 690Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
691
692 * gencode.c: Add r3900 (tx39).
693
694start-sanitize-tx19
695 * gencode.c: Fix some configuration problems by improving
696 the relationship between tx19 and tx39.
697end-sanitize-tx19
698
667065d0
GRK		 699Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
700
701 * gencode.c (build_instruction): Don't need to subtract 4 for
702 JALR, just 2.
703
9cb8397f
GRK		 704Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
705
706 * interp.c: Correct some HASFPU problems.
707
a2ab5e65
AC		 708Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
709
710 * configure: Regenerated to track ../common/aclocal.m4 changes.
711
11ac69e0
AC		 712Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
713
714 * interp.c (mips_options): Fix samples option short form, should
715 be `x'.
716
972f3a34
AC		 717Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
718
719 * interp.c (sim_info): Enable info code. Was just returning.
720
9eeaaefa
AC		 721Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
722
723 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
724 MFC0.
725
c31c13b4
AC		 726Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
727
728 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
729 constants.
730 (build_instruction): Ditto for LL.
731
b637f306
GRK		 732start-sanitize-tx19
733Sun Sep 7 16:05:46 1997 Gavin Koch <gavin@cygnus.com>
734
735 * mips/configure.in, mips/gencode: Add tx19/r1900.
736
737end-sanitize-tx19
6fea4763
DE		 738Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
739
740 * configure: Regenerated to track ../common/aclocal.m4 changes.
741
52352d38
AC		 742start-sanitize-r5900
743Mon Sep 1 18:43:30 1997 Andrew Cagney <cagney@b1.cygnus.com>
744
745 * gencode.c (build_instruction): For "pabsw" and "pabsh", check
746 for overflow due to ABS of MININT, set result to MAXINT.
747 (build_instruction): For "psrlvw", signextend bit 31.
748
749end-sanitize-r5900
88117054
AC		 750Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
751
752 * configure: Regenerated to track ../common/aclocal.m4 changes.
753 * config.in: Ditto.
754
fafce69a
AC		 755Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
756
757 * interp.c (sim_open): Add call to sim_analyze_program, update
758 call to sim_config.
759
7230ff0f
AC		 760Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
761
762 * interp.c (sim_kill): Delete.
fafce69a
AC		 763 (sim_create_inferior): Add ABFD argument. Set PC from same.
764 (sim_load): Move code initializing trap handlers from here.
765 (sim_open): To here.
766 (sim_load): Delete, use sim-hload.c.
767
768 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
7230ff0f 769
247fccde
AC		 770Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
771
772 * configure: Regenerated to track ../common/aclocal.m4 changes.
773 * config.in: Ditto.
774
775Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
776
777 * interp.c (sim_open): Add ABFD argument.
778 (sim_load): Move call to sim_config from here.
779 (sim_open): To here. Check return status.
780
781start-sanitize-r5900
782 * gencode.c (build_instruction): Do not define x8000000000000000,
783 x7FFFFFFFFFFFFFFF, or xFFFFFFFF80000000.
784
785end-sanitize-r5900
786start-sanitize-r5900
787Mon Jul 28 19:49:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
788
789 * gencode.c (build_instruction): For "pdivw", "pdivbw" and
790 "pdivuw" check for overflow due to signed divide by -1.
791
792end-sanitize-r5900
c12e2e4c
GRK		 793Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
794
795 * gencode.c (build_instruction): Two arg MADD should
796 not assign result to $0.
797
1e851d2c
AC		 798start-sanitize-r5900
799Thu Jul 10 11:58:48 1997 Andrew Cagney <cagney@critters.cygnus.com>
800
801 * gencode.c (build_instruction): For "ppac5" use unsigned
802 arrithmetic so that the sign bit doesn't smear when right shifted.
803 (build_instruction): For "pdiv" perform sign extension when
804 storing results in HI and LO.
805 (build_instructions): For "pdiv" and "pdivbw" check for
806 divide-by-zero.
807 (build_instruction): For "pmfhl.slw" update hi part of dest
808 register as well as low part.
809 (build_instruction): For "pmfhl" portably handle long long values.
810 (build_instruction): For "pmfhl.sh" correctly negative values.
811 Store half words 2 and three in the correct place.
812 (build_instruction): For "psllvw", sign extend value after shift.
813
814end-sanitize-r5900
815Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
816
817 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
818 * sim/mips/configure.in: Regenerate.
819
820Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
821
822 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
823 signed8, unsigned8 et.al. types.
824
825start-sanitize-r5900
826 * gencode.c (build_instruction): For PMULTU* do not sign extend
827 registers. Make generated code easier to debug.
828
829end-sanitize-r5900
830 * interp.c (SUB_REG_FETCH): Handle both little and big endian
831 hosts when selecting subreg.
832
833start-sanitize-r5900
834Tue Jul 8 18:07:20 1997 Andrew Cagney <cagney@andros.cygnus.com>
835
836 * gencode.c (type_for_data_len): For 32bit operations concerned
837 with overflow, perform op using 64bits.
838 (build_instruction): For PADD, always compute operation using type
839 returned by type_for_data_len.
840 (build_instruction): For PSUBU, when overflow, saturate to zero as
841 actually underflow.
842
843end-sanitize-r5900
ae19b07b
JL		 844Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
845
649625bb 846start-sanitize-r5900
64435234
JL		 847 * gencode.c (build_instruction): Handle "pext5" according to
848 version 1.95 of the r5900 ISA.
849
649625bb
JL		 850 * gencode.c (build_instruction): Handle "ppac5" according to
851 version 1.95 of the r5900 ISA.
649625bb 852
1e851d2c 853end-sanitize-r5900
05d1322f
JL		 854 * interp.c (sim_engine_run): Reset the ZERO register to zero
855 regardless of FEATURE_WARN_ZERO.
ae19b07b
JL		 856 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
857
858Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
859
860 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
861 (SignalException): For BreakPoints ignore any mode bits and just
862 save the PC.
863 (SignalException): Always set the CAUSE register.
864
56e7c849
AC		 865Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
866
867 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
868 exception has been taken.
869
870 * interp.c: Implement the ERET and mt/f sr instructions.
871
ae19b07b 872start-sanitize-r5900
56e7c849
AC		 873Mon Jun 2 23:28:19 1997 Andrew Cagney <cagney@b1.cygnus.com>
874
875 * gencode.c (build_instruction): For paddu, extract unsigned
876 sub-fields.
877
878 * gencode.c (build_instruction): Saturate padds instead of padd
879 instructions.
880
881end-sanitize-r5900
882Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
883
884 * interp.c (SignalException): Don't bother restarting an
885 interrupt.
886
887Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
888
889 * interp.c (SignalException): Really take an interrupt.
890 (interrupt_event): Only deliver interrupts when enabled.
891
892Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
893
894 * interp.c (sim_info): Only print info when verbose.
895 (sim_info) Use sim_io_printf for output.
896
2f2e6c5d
AC		 897Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
898
899 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
900 mips architectures.
901
902Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
903
904 * interp.c (sim_do_command): Check for common commands if a
905 simulator specific command fails.
906
d3d2a9f7
GRK		 907Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
908
909 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
910 and simBE when DEBUG is defined.
911
50a2a691
AC		 912Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
913
914 * interp.c (interrupt_event): New function. Pass exception event
915 onto exception handler.
916
917 * configure.in: Check for stdlib.h.
918 * configure: Regenerate.
919
920 * gencode.c (build_instruction): Add UNUSED attribute to tempS
921 variable declaration.
922 (build_instruction): Initialize memval1.
923 (build_instruction): Add UNUSED attribute to byte, bigend,
924 reverse.
925 (build_operands): Ditto.
926
927 * interp.c: Fix GCC warnings.
928 (sim_get_quit_code): Delete.
929
930 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
931 * Makefile.in: Ditto.
932 * configure: Re-generate.
933
934 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
935
936Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
937
938 * interp.c (mips_option_handler): New function parse argumes using
939 sim-options.
940 (myname): Replace with STATE_MY_NAME.
941 (sim_open): Delete check for host endianness - performed by
942 sim_config.
943 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
944 (sim_open): Move much of the initialization from here.
945 (sim_load): To here. After the image has been loaded and
946 endianness set.
947 (sim_open): Move ColdReset from here.
948 (sim_create_inferior): To here.
949 (sim_open): Make FP check less dependant on host endianness.
950
951 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
952 run.
953 * interp.c (sim_set_callbacks): Delete.
954
955 * interp.c (membank, membank_base, membank_size): Replace with
956 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
957 (sim_open): Remove call to callback->init. gdb/run do this.
958
959 * interp.c: Update
960
961 * sim-main.h (SIM_HAVE_FLATMEM): Define.
962
963 * interp.c (big_endian_p): Delete, replaced by
964 current_target_byte_order.
965
966Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
967
968 * interp.c (host_read_long, host_read_word, host_swap_word,
969 host_swap_long): Delete. Using common sim-endian.
970 (sim_fetch_register, sim_store_register): Use H2T.
971 (pipeline_ticks): Delete. Handled by sim-events.
972 (sim_info): Update.
973 (sim_engine_run): Update.
974
975Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
976
977 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
978 reason from here.
979 (SignalException): To here. Signal using sim_engine_halt.
980 (sim_stop_reason): Delete, moved to common.
981
982Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
983
984 * interp.c (sim_open): Add callback argument.
985 (sim_set_callbacks): Delete SIM_DESC argument.
986 (sim_size): Ditto.
987
2e61a3ad
AC		 988Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
989
990 * Makefile.in (SIM_OBJS): Add common modules.
991
992 * interp.c (sim_set_callbacks): Also set SD callback.
993 (set_endianness, xfer_*, swap_*): Delete.
994 (host_read_word, host_read_long, host_swap_word, host_swap_long):
995 Change to functions using sim-endian macros.
996 (control_c, sim_stop): Delete, use common version.
997 (simulate): Convert into.
998 (sim_engine_run): This function.
999 (sim_resume): Delete.
1000
1001 * interp.c (simulation): New variable - the simulator object.
1002 (sim_kind): Delete global - merged into simulation.
1003 (sim_load): Cleanup. Move PC assignment from here.
1004 (sim_create_inferior): To here.
1005
1006 * sim-main.h: New file.
1007 * interp.c (sim-main.h): Include.
1008
1009Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
1010
1011 * configure: Regenerated to track ../common/aclocal.m4 changes.
1012
3be0e228
DE		 1013Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
1014
1015 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
1016
d654ba0a
GRK		 1017Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
1018
1019 * gencode.c (build_instruction): DIV instructions: check
1020 for division by zero and integer overflow before using
1021 host's division operation.
1022
9d52bcb7
DE		 1023Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
1024
1025 * Makefile.in (SIM_OBJS): Add sim-load.o.
1026 * interp.c: #include bfd.h.
1027 (target_byte_order): Delete.
1028 (sim_kind, myname, big_endian_p): New static locals.
1029 (sim_open): Set sim_kind, myname. Move call to set_endianness to
1030 after argument parsing. Recognize -E arg, set endianness accordingly.
1031 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
1032 load file into simulator. Set PC from bfd.
1033 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
1034 (set_endianness): Use big_endian_p instead of target_byte_order.
1035
87e43259
AC		 1036Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
1037
1038 * interp.c (sim_size): Delete prototype - conflicts with
1039 definition in remote-sim.h. Correct definition.
1040
1041Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1042
1043 * configure: Regenerated to track ../common/aclocal.m4 changes.
1044 * config.in: Ditto.
1045
fbda74b1
DE		 1046Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
1047
8a7c3105
DE		 1048 * interp.c (sim_open): New arg `kind'.
1049
fbda74b1
DE		 1050 * configure: Regenerated to track ../common/aclocal.m4 changes.
1051
a35e91c3
AC		 1052Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1053
1054 * configure: Regenerated to track ../common/aclocal.m4 changes.
1055
1056Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
1057
1058 * interp.c (sim_open): Set optind to 0 before calling getopt.
1059
1060Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1061
1062 * configure: Regenerated to track ../common/aclocal.m4 changes.
1063
6efa34d8
GRK		 1064Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
1065
1066 * interp.c : Replace uses of pr_addr with pr_uword64
1067 where the bit length is always 64 independent of SIM_ADDR.
1068 (pr_uword64) : added.
1069
a77aa7ec
AC		 1070Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1071
1072 * configure: Re-generate.
1073
601fb8ae
MM		 1074Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
1075
1076 * configure: Regenerate to track ../common/aclocal.m4 changes.
1077
53b9417e
DE		 1078Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
1079
1080 * interp.c (sim_open): New SIM_DESC result. Argument is now
1081 in argv form.
1082 (other sim_*): New SIM_DESC argument.
1083
1084start-sanitize-r5900
1085Wed Feb 26 18:32:21 1997 Gavin Koch <gavin@cygnus.com>
1086
1087 * gencode.c (POP_AND,POP_OR,POP_NOR,POP_XOR):
1088 Change values to avoid overloading DOUBLEWORD which is tested
1089 for all insns.
1090 * gencode.c: reinstate "offending code".
53b9417e 1091
56e7c849 1092end-sanitize-r5900
53b9417e
DE		 1093Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
1094
1095 * interp.c: Fix printing of addresses for non-64-bit targets.
1096 (pr_addr): Add function to print address based on size.
1097start-sanitize-r5900
1098 * gencode.c: #ifdef out offending code until a permanent fix
1099 can be added. Code is causing build errors for non-5900 mips targets.
1100end-sanitize-r5900
1101
1102start-sanitize-r5900
1103Thu Feb 20 10:40:24 1997 Gavin Koch <gavin@cetus.cygnus.com>
1104
1105 * gencode.c (process_instructions): Correct test for ISA dependent
1106 architecture bits in isa field of MIPS_DECODE.
1107
1108end-sanitize-r5900
7e05106d
MA		 1109Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
1110
1111 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
1112
2d18fbc6 1113start-sanitize-r5900
53b9417e 1114Tue Feb 18 17:03:47 1997 Gavin Koch <gavin@cygnus.com>
2d18fbc6
GRK		 1115
1116 * gencode.c (MIPS_DECODE): Correct instruction feature flags for
1117 PMADDUW.
1118
1119end-sanitize-r5900
1120Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
1121
1122 * gencode.c (build_mips16_operands): Correct computation of base
1123 address for extended PC relative instruction.
1124
276c2d7d
GRK		 1125start-sanitize-r5900
1126Fri Feb 7 11:12:44 1997 Gavin Koch <gavin@cygnus.com>
2d18fbc6
GRK		 1127
1128 * Makefile.in, configure, configure.in, gencode.c,
1129 interp.c, support.h: add r5900.
1130
276c2d7d 1131end-sanitize-r5900
da0bce9c
ILT		 1132Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
1133
1134 * interp.c (mips16_entry): Add support for floating point cases.
1135 (SignalException): Pass floating point cases to mips16_entry.
1136 (ValueFPR): Don't restrict fmt_single and fmt_word to even
1137 registers.
1138 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
1139 or fmt_word.
1140 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
1141 and then set the state to fmt_uninterpreted.
1142 (COP_SW): Temporarily set the state to fmt_word while calling
1143 ValueFPR.
1144
6389d856
ILT		 1145Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
1146
1147 * gencode.c (build_instruction): The high order may be set in the
1148 comparison flags at any ISA level, not just ISA 4.
1149
19c5af72
DE		 1150Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
1151
1152 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
1153 COMMON_{PRE,POST}_CONFIG_FRAG instead.
1154 * configure.in: sinclude ../common/aclocal.m4.
1155 * configure: Regenerated.
1156
736a306c
ILT		 1157Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
1158
1159 * configure: Rebuild after change to aclocal.m4.
1160
295dbbe4
SG		 1161Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
1162
1163 * configure configure.in Makefile.in: Update to new configure
1164 scheme which is more compatible with WinGDB builds.
1165 * configure.in: Improve comment on how to run autoconf.
1166 * configure: Re-run autoconf to get new ../common/aclocal.m4.
1167 * Makefile.in: Use autoconf substitution to install common
1168 makefile fragment.
1169
1170Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
1171
1172 * gencode.c (build_instruction): Use BigEndianCPU instead of
1173 ByteSwapMem.
1174
e1db0d47
MA		 1175Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
1176
1177 * interp.c (sim_monitor): Make output to stdout visible in
1178 wingdb's I/O log window.
1179
2902e8ab
MA		 1180Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
1181
1182 * support.h: Undo previous change to SIGTRAP
1183 and SIGQUIT values.
1184
7e6c297e
ILT		 1185Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
1186
1187 * interp.c (store_word, load_word): New static functions.
1188 (mips16_entry): New static function.
1189 (SignalException): Look for mips16 entry and exit instructions.
1190 (simulate): Use the correct index when setting fpr_state after
1191 doing a pending move.
1192
0049ba7a
MA		 1193Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
1194
1195 * interp.c: Fix byte-swapping code throughout to work on
1196 both little- and big-endian hosts.
1197
2510786b
MA		 1198Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
1199
1200 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
1201 with gdb/config/i386/xm-windows.h.
1202
39bf0ef4
MA		 1203Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
1204
1205 * gencode.c (build_instruction): Work around MSVC++ code gen bug
1206 that messes up arithmetic shifts.
1207
dbeec768
SG		 1208Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
1209
1210 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
1211 SIGTRAP and SIGQUIT for _WIN32.
1212
deffd638
ILT		 1213Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
1214
1215 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
1216 force a 64 bit multiplication.
1217 (build_instruction) [OR]: In mips16 mode, don't do anything if the
1218 destination register is 0, since that is the default mips16 nop
1219 instruction.
1220
aaff8437
ILT		 1221Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
1222
063443cf
ILT		 1223 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
1224 (build_endian_shift): Don't check proc64.
1225 (build_instruction): Always set memval to uword64. Cast op2 to
1226 uword64 when shifting it left in memory instructions. Always use
1227 the same code for stores--don't special case proc64.
1228
aaff8437
ILT		 1229 * gencode.c (build_mips16_operands): Fix base PC value for PC
1230 relative operands.
1231 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
1232 jal instruction.
1233 * interp.c (simJALDELAYSLOT): Define.
1234 (JALDELAYSLOT): Define.
1235 (INDELAYSLOT, INJALDELAYSLOT): Define.
1236 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
1237
280f90e1
AMT		 1238Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
1239
1240 * interp.c (sim_open): add flush_cache as a PMON routine
1241 (sim_monitor): handle flush_cache by ignoring it
1242
aaff8437
ILT		 1243Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
1244
1245 * gencode.c (build_instruction): Use !ByteSwapMem instead of
1246 BigEndianMem.
1247 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
1248 (BigEndianMem): Rename to ByteSwapMem and change sense.
1249 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
1250 BigEndianMem references to !ByteSwapMem.
1251 (set_endianness): New function, with prototype.
1252 (sim_open): Call set_endianness.
1253 (sim_info): Use simBE instead of BigEndianMem.
1254 (xfer_direct_word, xfer_direct_long, swap_direct_word,
1255 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
1256 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
1257 ifdefs, keeping the prototype declaration.
1258 (swap_word): Rewrite correctly.
1259 (ColdReset): Delete references to CONFIG. Delete endianness related
1260 code; moved to set_endianness.
1261
6429b296
JW		 1262Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
1263
1264 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
1265 * interp.c (CHECKHILO): Define away.
1266 (simSIGINT): New macro.
1267 (membank_size): Increase from 1MB to 2MB.
1268 (control_c): New function.
1269 (sim_resume): Rename parameter signal to signal_number. Add local
1270 variable prev. Call signal before and after simulate.
1271 (sim_stop_reason): Add simSIGINT support.
1272 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
1273 functions always.
1274 (sim_warning): Delete call to SignalException. Do call printf_filtered
1275 if logfh is NULL.
1276 (AddressTranslation): Add #ifdef DEBUG around debugging message and
1277 a call to sim_warning.
1278
1279Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
1280
1281 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
1282 16 bit instructions.
1283
831f59a2
ILT		 1284Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
1285
1286 Add support for mips16 (16 bit MIPS implementation):
1287 * gencode.c (inst_type): Add mips16 instruction encoding types.
1288 (GETDATASIZEINSN): Define.
1289 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
1290 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
1291 mtlo.
1292 (MIPS16_DECODE): New table, for mips16 instructions.
1293 (bitmap_val): New static function.
1294 (struct mips16_op): Define.
1295 (mips16_op_table): New table, for mips16 operands.
1296 (build_mips16_operands): New static function.
1297 (process_instructions): If PC is odd, decode a mips16
1298 instruction. Break out instruction handling into new
1299 build_instruction function.
1300 (build_instruction): New static function, broken out of
1301 process_instructions. Check modifiers rather than flags for SHIFT
1302 bit count and m[ft]{hi,lo} direction.
1303 (usage): Pass program name to fprintf.
1304 (main): Remove unused variable this_option_optind. Change
1305 ``*loptarg++'' to ``loptarg++''.
1306 (my_strtoul): Parenthesize && within ||.
350d33b8 1307 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
831f59a2
ILT		 1308 (simulate): If PC is odd, fetch a 16 bit instruction, and
1309 increment PC by 2 rather than 4.
1310 * configure.in: Add case for mips16*-*-*.
1311 * configure: Rebuild.
1312
1313Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
1314
1315 * interp.c: Allow -t to enable tracing in standalone simulator.
1316 Fix garbage output in trace file and error messages.
1317
e3d12c65
DE		 1318Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
1319
1320 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
1321 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
1322 * configure.in: Simplify using macros in ../common/aclocal.m4.
1323 * configure: Regenerated.
1324 * tconfig.in: New file.
1325
1326Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
1327
1328 * interp.c: Fix bugs in 64-bit port.
1329 Use ansi function declarations for msvc compiler.
1330 Initialize and test file pointer in trace code.
1331 Prevent duplicate definition of LAST_EMED_REGNUM.
1332
1333Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
1334
1335 * interp.c (xfer_big_long): Prevent unwanted sign extension.
1336
1337Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
1338
1339 * interp.c (SignalException): Check for explicit terminating
1340 breakpoint value.
1341 * gencode.c: Pass instruction value through SignalException()
1342 calls for Trap, Breakpoint and Syscall.
1343
1344Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
1345
1346 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
1347 only used on those hosts that provide it.
1348 * configure.in: Add sqrt() to list of functions to be checked for.
1349 * config.in: Re-generated.
1350 * configure: Re-generated.
1351
1352Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
1353
1354 * gencode.c (process_instructions): Call build_endian_shift when
1355 expanding STORE RIGHT, to fix swr.
1356 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
1357 clear the high bits.
1358 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
1359 Fix float to int conversions to produce signed values.
1360
cc5201d7
ILT		 1361Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
1362
458e1f58
ILT		 1363 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
1364 (process_instructions): Correct handling of nor instruction.
1365 Correct shift count for 32 bit shift instructions. Correct sign
1366 extension for arithmetic shifts to not shift the number of bits in
1367 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
1368 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
1369 Fix madd.
c05d1721
ILT		 1370 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
1371 It's OK to have a mult follow a mult. What's not OK is to have a
1372 mult follow an mfhi.
458e1f58 1373 (Convert): Comment out incorrect rounding code.
cc5201d7 1374
f24b7b69
JSC		 1375Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
1376
1377 * interp.c (sim_monitor): Improved monitor printf
1378 simulation. Tidied up simulator warnings, and added "--log" option
1379 for directing warning message output.
1380 * gencode.c: Use sim_warning() rather than WARNING macro.
1381
1382Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
1383
1384 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
1385 getopt1.o, rather than on gencode.c. Link objects together.
1386 Don't link against -liberty.
1387 (gencode.o, getopt.o, getopt1.o): New targets.
1388 * gencode.c: Include <ctype.h> and "ansidecl.h".
1389 (AND): Undefine after including "ansidecl.h".
1390 (ULONG_MAX): Define if not defined.
1391 (OP_*): Don't define macros; now defined in opcode/mips.h.
1392 (main): Call my_strtoul rather than strtoul.
1393 (my_strtoul): New static function.
1394
1395Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
1396
1397 * gencode.c (process_instructions): Generate word64 and uword64
1398 instead of `long long' and `unsigned long long' data types.
1399 * interp.c: #include sysdep.h to get signals, and define default
1400 for SIGBUS.
1401 * (Convert): Work around for Visual-C++ compiler bug with type
1402 conversion.
1403 * support.h: Make things compile under Visual-C++ by using
1404 __int64 instead of `long long'. Change many refs to long long
1405 into word64/uword64 typedefs.
1406
a271d1d9
JM		 1407Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
1408
1409 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
1410 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
1411 (docdir): Removed.
1412 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
1413 (AC_PROG_INSTALL): Added.
1414 (AC_PROG_CC): Moved to before configure.host call.
1415 * configure: Rebuilt.
1416
1417Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
1418
1419 * configure.in: Define @SIMCONF@ depending on mips target.
1420 * configure: Rebuild.
1421 * Makefile.in (run): Add @SIMCONF@ to control simulator
1422 construction.
1423 * gencode.c: Change LOADDRMASK to 64bit memory model only.
1424 * interp.c: Remove some debugging, provide more detailed error
1425 messages, update memory accesses to use LOADDRMASK.
1426
4fa134be
ILT		 1427Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
1428
1429 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
1430 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
1431 stamp-h.
1432 * configure: Rebuild.
1433 * config.in: New file, generated by autoheader.
1434 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
1435 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
1436 HAVE_ANINT and HAVE_AINT, as appropriate.
1437 * Makefile.in (run): Use @LIBS@ rather than -lm.
1438 (interp.o): Depend upon config.h.
1439 (Makefile): Just rebuild Makefile.
1440 (clean): Remove stamp-h.
1441 (mostlyclean): Make the same as clean, not as distclean.
1442 (config.h, stamp-h): New targets.
1443
1444Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
1445
1446 * interp.c (ColdReset): Fix boolean test. Make all simulator
1447 globals static.
1448
f7481d45
JSC		 1449Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
1450
1451 * interp.c (xfer_direct_word, xfer_direct_long,
1452 swap_direct_word, swap_direct_long, xfer_big_word,
1453 xfer_big_long, xfer_little_word, xfer_little_long,
1454 swap_word,swap_long): Added.
1455 * interp.c (ColdReset): Provide function indirection to
1456 host<->simulated_target transfer routines.
1457 * interp.c (sim_store_register, sim_fetch_register): Updated to
1458 make use of indirected transfer routines.
1459
1460Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
1461
1462 * gencode.c (process_instructions): Ensure FP ABS instruction
1463 recognised.
1464 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
1465 system call support.
1466
8b554809
JSC		 1467Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
1468
1469 * interp.c (sim_do_command): Complain if callback structure not
1470 initialised.
1471
d0757082
JSC		 1472Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
1473
1474 * interp.c (Convert): Provide round-to-nearest and round-to-zero
1475 support for Sun hosts.
1476 * Makefile.in (gencode): Ensure the host compiler and libraries
1477 used for cross-hosted build.
1478
e871dd18
JSC		 1479Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
1480
1481 * interp.c, gencode.c: Some more (TODO) tidying.
1482
1483Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
1484
1485 * gencode.c, interp.c: Replaced explicit long long references with
1486 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
1487 * support.h (SET64LO, SET64HI): Macros added.
1488
5c59ec43
ILT		 1489Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
1490
1491 * configure: Regenerate with autoconf 2.7.
1492
1493Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
1494
1495 * interp.c (LoadMemory): Enclose text following #endif in /* */.
1496 * support.h: Remove superfluous "1" from #if.
1497 * support.h (CHECKSIM): Remove stray 'a' at end of line.
1498
1499Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
1500
1501 * interp.c (StoreFPR): Control UndefinedResult() call on
1502 WARN_RESULT manifest.
1503
8bae0a0c
JSC		 1504Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
1505
1506 * gencode.c: Tidied instruction decoding, and added FP instruction
1507 support.
1508
1509 * interp.c: Added dineroIII, and BSD profiling support. Also
1510 run-time FP handling.
1511
1512Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
1513
1514 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
1515 gencode.c, interp.c, support.h: created.
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