Commit | Line | Data |
---|---|---|
20bca71d MF |
1 | 2015-04-18 Mike Frysinger <vapier@gentoo.org> |
2 | ||
3 | * sim-main.h (SIM_CPU): Delete. | |
4 | ||
7e83aa92 MF |
5 | 2015-04-18 Mike Frysinger <vapier@gentoo.org> |
6 | ||
7 | * sim-main.h (sim_cia): Delete. | |
8 | ||
034685f9 MF |
9 | 2015-04-17 Mike Frysinger <vapier@gentoo.org> |
10 | ||
11 | * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Change CIA_GET to | |
12 | PU_PC_GET. | |
13 | * interp.c (interrupt_event): Change CIA_GET to CPU_PC_GET. | |
14 | (sim_create_inferior): Change CIA_SET to CPU_PC_SET. | |
15 | * m16run.c (sim_engine_run): Change CIA_GET to CPU_PC_GET and | |
16 | CIA_SET to CPU_PC_SET. | |
17 | * sim-main.h (CIA_GET, CIA_SET): Delete. | |
18 | ||
78e9aa70 MF |
19 | 2015-04-15 Mike Frysinger <vapier@gentoo.org> |
20 | ||
21 | * Makefile.in (SIM_OBJS): Delete sim-cpu.o. | |
22 | * sim-main.h (STATE_CPU): Delete. | |
23 | ||
bf12d44e MF |
24 | 2015-04-13 Mike Frysinger <vapier@gentoo.org> |
25 | ||
26 | * configure: Regenerate. | |
27 | ||
7bebb329 MF |
28 | 2015-04-13 Mike Frysinger <vapier@gentoo.org> |
29 | ||
30 | * Makefile.in (SIM_OBJS): Add sim-cpu.o. | |
31 | * interp.c (mips_pc_get, mips_pc_set): New functions. | |
32 | (sim_open): Declare new local var i. Call sim_cpu_alloc_all. | |
33 | Call CPU_PC_FETCH & CPU_PC_STORE for all cpus. | |
34 | (sim_pc_get): Delete. | |
35 | * sim-main.h (SIM_CPU): Define. | |
36 | (struct sim_state): Change cpu to an array of pointers. | |
37 | (STATE_CPU): Drop &. | |
38 | ||
8ac57fbd MF |
39 | 2015-04-13 Mike Frysinger <vapier@gentoo.org> |
40 | ||
41 | * interp.c (mips_option_handler, open_trace, sim_close, | |
42 | sim_write, sim_read, sim_store_register, sim_fetch_register, | |
43 | sim_create_inferior, pr_addr, pr_uword64): Convert old style | |
44 | prototypes. | |
45 | (sim_open): Convert old style prototype. Change casts with | |
46 | sim_write to unsigned char *. | |
47 | (fetch_str): Change null to unsigned char, and change cast to | |
48 | unsigned char *. | |
49 | (sim_monitor): Change c & ch to unsigned char. Change cast to | |
50 | unsigned char *. | |
51 | ||
e787f858 MF |
52 | 2015-04-12 Mike Frysinger <vapier@gentoo.org> |
53 | ||
54 | * Makefile.in (SIM_OBJS): Move interp.o to the start of the list. | |
55 | ||
122bbfb5 MF |
56 | 2015-04-06 Mike Frysinger <vapier@gentoo.org> |
57 | ||
58 | * Makefile.in (SIM_OBJS): Delete sim-engine.o. | |
59 | ||
0fe84f3f MF |
60 | 2015-04-01 Mike Frysinger <vapier@gentoo.org> |
61 | ||
62 | * tconfig.h (SIM_HAVE_PROFILE): Delete. | |
63 | ||
aadc9410 MF |
64 | 2015-03-31 Mike Frysinger <vapier@gentoo.org> |
65 | ||
66 | * config.in, configure: Regenerate. | |
67 | ||
05f53ed6 MF |
68 | 2015-03-24 Mike Frysinger <vapier@gentoo.org> |
69 | ||
70 | * interp.c (sim_pc_get): New function. | |
71 | ||
c0931f26 MF |
72 | 2015-03-24 Mike Frysinger <vapier@gentoo.org> |
73 | ||
74 | * sim-main.h (SIM_HAVE_BIENDIAN): Delete. | |
75 | * tconfig.h (SIM_HAVE_BIENDIAN): Delete. | |
76 | ||
30452bbe MF |
77 | 2015-03-24 Mike Frysinger <vapier@gentoo.org> |
78 | ||
79 | * configure: Regenerate. | |
80 | ||
64dd13df MF |
81 | 2015-03-23 Mike Frysinger <vapier@gentoo.org> |
82 | ||
83 | * configure: Regenerate. | |
84 | ||
49cd1634 MF |
85 | 2015-03-23 Mike Frysinger <vapier@gentoo.org> |
86 | ||
87 | * configure: Regenerate. | |
88 | * configure.ac (mips_extra_objs): Delete. | |
89 | * Makefile.in (MIPS_EXTRA_OBJS): Delete. | |
90 | (SIM_OBJS): Delete MIPS_EXTRA_OBJS. | |
91 | ||
3649cb06 MF |
92 | 2015-03-23 Mike Frysinger <vapier@gentoo.org> |
93 | ||
94 | * configure: Regenerate. | |
95 | * configure.ac: Delete sim_hw checks for dv-sockser. | |
96 | ||
ae7d0cac MF |
97 | 2015-03-16 Mike Frysinger <vapier@gentoo.org> |
98 | ||
99 | * config.in, configure: Regenerate. | |
100 | * tconfig.in: Rename file ... | |
101 | * tconfig.h: ... here. | |
102 | ||
8406bb59 MF |
103 | 2015-03-15 Mike Frysinger <vapier@gentoo.org> |
104 | ||
105 | * tconfig.in: Delete includes. | |
106 | [HAVE_DV_SOCKSER]: Delete. | |
107 | ||
465fb143 MF |
108 | 2015-03-14 Mike Frysinger <vapier@gentoo.org> |
109 | ||
110 | * Makefile.in (SIM_RUN_OBJS): Delete. | |
111 | ||
5cddc23a MF |
112 | 2015-03-14 Mike Frysinger <vapier@gentoo.org> |
113 | ||
114 | * configure.ac (AC_CHECK_HEADERS): Delete. | |
115 | * aclocal.m4, configure: Regenerate. | |
116 | ||
2974be62 AM |
117 | 2014-08-19 Alan Modra <amodra@gmail.com> |
118 | ||
119 | * configure: Regenerate. | |
120 | ||
faa743bb RM |
121 | 2014-08-15 Roland McGrath <mcgrathr@google.com> |
122 | ||
123 | * configure: Regenerate. | |
124 | * config.in: Regenerate. | |
125 | ||
1a8a700e MF |
126 | 2014-03-04 Mike Frysinger <vapier@gentoo.org> |
127 | ||
128 | * configure: Regenerate. | |
129 | ||
bf3d9781 AM |
130 | 2013-09-23 Alan Modra <amodra@gmail.com> |
131 | ||
132 | * configure: Regenerate. | |
133 | ||
31e6ad7d MF |
134 | 2013-06-03 Mike Frysinger <vapier@gentoo.org> |
135 | ||
136 | * aclocal.m4, configure: Regenerate. | |
137 | ||
d3685d60 TT |
138 | 2013-05-10 Freddie Chopin <freddie_chopin@op.pl> |
139 | ||
140 | * configure: Rebuild. | |
141 | ||
1517bd27 MF |
142 | 2013-03-26 Mike Frysinger <vapier@gentoo.org> |
143 | ||
144 | * configure: Regenerate. | |
145 | ||
3be31516 JS |
146 | 2013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com> |
147 | ||
148 | * configure.ac: Address use of dv-sockser.o. | |
149 | * tconfig.in: Conditionalize use of dv_sockser_install. | |
150 | * configure: Regenerated. | |
151 | * config.in: Regenerated. | |
152 | ||
37cb8f8e SE |
153 | 2012-10-04 Chao-ying Fu <fu@mips.com> |
154 | Steve Ellcey <sellcey@mips.com> | |
155 | ||
156 | * mips/mips3264r2.igen (rdhwr): New. | |
157 | ||
87c8644f JS |
158 | 2012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com> |
159 | ||
160 | * configure.ac: Always link against dv-sockser.o. | |
161 | * configure: Regenerate. | |
162 | ||
5f3ef9d0 JB |
163 | 2012-06-15 Joel Brobecker <brobecker@adacore.com> |
164 | ||
165 | * config.in, configure: Regenerate. | |
166 | ||
a6ff997c NC |
167 | 2012-05-18 Nick Clifton <nickc@redhat.com> |
168 | ||
169 | PR 14072 | |
170 | * interp.c: Include config.h before system header files. | |
171 | ||
2232061b MF |
172 | 2012-03-24 Mike Frysinger <vapier@gentoo.org> |
173 | ||
174 | * aclocal.m4, config.in, configure: Regenerate. | |
175 | ||
db2e4d67 MF |
176 | 2011-12-03 Mike Frysinger <vapier@gentoo.org> |
177 | ||
178 | * aclocal.m4: New file. | |
179 | * configure: Regenerate. | |
180 | ||
4399a56b MF |
181 | 2011-10-19 Mike Frysinger <vapier@gentoo.org> |
182 | ||
183 | * configure: Regenerate after common/acinclude.m4 update. | |
184 | ||
9c082ca8 MF |
185 | 2011-10-17 Mike Frysinger <vapier@gentoo.org> |
186 | ||
187 | * configure.ac: Change include to common/acinclude.m4. | |
188 | ||
6ffe910a MF |
189 | 2011-10-17 Mike Frysinger <vapier@gentoo.org> |
190 | ||
191 | * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER | |
192 | call. Replace common.m4 include with SIM_AC_COMMON. | |
193 | * configure: Regenerate. | |
194 | ||
31b28250 HPN |
195 | 2011-07-08 Hans-Peter Nilsson <hp@axis.com> |
196 | ||
3faa01e3 HPN |
197 | * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h |
198 | $(SIM_EXTRA_DEPS). | |
199 | (tmp-mach-multi): Exit early when igen fails. | |
31b28250 | 200 | |
2419798b MF |
201 | 2011-07-05 Mike Frysinger <vapier@gentoo.org> |
202 | ||
203 | * interp.c (sim_do_command): Delete. | |
204 | ||
d79fe0d6 MF |
205 | 2011-02-14 Mike Frysinger <vapier@gentoo.org> |
206 | ||
207 | * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free. | |
208 | (tx3904sio_fifo_reset): Likewise. | |
209 | * interp.c (sim_monitor): Likewise. | |
210 | ||
5558e7e6 MF |
211 | 2010-04-14 Mike Frysinger <vapier@gentoo.org> |
212 | ||
213 | * interp.c (sim_write): Add const to buffer arg. | |
214 | ||
35aafff4 JB |
215 | 2010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change) |
216 | ||
217 | * interp.c: Don't include sysdep.h | |
218 | ||
3725885a RW |
219 | 2010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de> |
220 | ||
221 | * configure: Regenerate. | |
222 | ||
d6416cdc RW |
223 | 2009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de> |
224 | ||
81ecdfbb RW |
225 | * config.in: Regenerate. |
226 | * configure: Likewise. | |
227 | ||
d6416cdc RW |
228 | * configure: Regenerate. |
229 | ||
b5bd9624 HPN |
230 | 2008-07-11 Hans-Peter Nilsson <hp@axis.com> |
231 | ||
232 | * configure: Regenerate to track ../common/common.m4 changes. | |
233 | * config.in: Ditto. | |
234 | ||
6efef468 JM |
235 | 2008-06-06 Vladimir Prus <vladimir@codesourcery.com> |
236 | Daniel Jacobowitz <dan@codesourcery.com> | |
237 | Joseph Myers <joseph@codesourcery.com> | |
238 | ||
239 | * configure: Regenerate. | |
240 | ||
60dc88db RS |
241 | 2007-10-22 Richard Sandiford <rsandifo@nildram.co.uk> |
242 | ||
243 | * mips.igen (check_fmt_p): Provide a separate mips32r2 definition | |
244 | that unconditionally allows fmt_ps. | |
245 | (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU) | |
246 | (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt) | |
247 | (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change | |
248 | filter from 64,f to 32,f. | |
249 | (PREFX): Change filter from 64 to 32. | |
250 | (LDXC1, LUXC1): Provide separate mips32r2 implementations | |
251 | that use do_load_double instead of do_load. Make both LUXC1 | |
252 | versions unpredictable if SizeFGR () != 64. | |
253 | (SDXC1, SUXC1): Extend to mips32r2, using do_store_double | |
254 | instead of do_store. Remove unused variable. Make both SUXC1 | |
255 | versions unpredictable if SizeFGR () != 64. | |
256 | ||
599ca73e RS |
257 | 2007-10-07 Richard Sandiford <rsandifo@nildram.co.uk> |
258 | ||
259 | * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32. | |
260 | (sc, swxc1): Likewise. Also fix big-endian and reverse-endian | |
261 | shifts for that case. | |
262 | ||
2525df03 NC |
263 | 2007-09-04 Nick Clifton <nickc@redhat.com> |
264 | ||
265 | * interp.c (options enum): Add OPTION_INFO_MEMORY. | |
266 | (display_mem_info): New static variable. | |
267 | (mips_option_handler): Handle OPTION_INFO_MEMORY. | |
268 | (mips_options): Add info-memory and memory-info. | |
269 | (sim_open): After processing the command line and board | |
270 | specification, check display_mem_info. If it is set then | |
271 | call the real handler for the --memory-info command line | |
272 | switch. | |
273 | ||
35ee6e1e JB |
274 | 2007-08-24 Joel Brobecker <brobecker@adacore.com> |
275 | ||
276 | * configure.ac: Change license of multi-run.c to GPL version 3. | |
277 | * configure: Regenerate. | |
278 | ||
d5fb0879 RS |
279 | 2007-06-28 Richard Sandiford <richard@codesourcery.com> |
280 | ||
281 | * configure.ac, configure: Revert last patch. | |
282 | ||
2a2ce21b RS |
283 | 2007-06-26 Richard Sandiford <richard@codesourcery.com> |
284 | ||
285 | * configure.ac (sim_mipsisa3264_configs): New variable. | |
286 | (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make | |
287 | every configuration support all four targets, using the triplet to | |
288 | determine the default. | |
289 | * configure: Regenerate. | |
290 | ||
efdcccc9 RS |
291 | 2007-06-25 Richard Sandiford <richard@codesourcery.com> |
292 | ||
0a7692b2 | 293 | * Makefile.in (m16run.o): New rule. |
efdcccc9 | 294 | |
f532a356 TS |
295 | 2007-05-15 Thiemo Seufer <ths@mips.com> |
296 | ||
297 | * mips3264r2.igen (DSHD): Fix compile warning. | |
298 | ||
bfe9c90b TS |
299 | 2007-05-14 Thiemo Seufer <ths@mips.com> |
300 | ||
301 | * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, | |
302 | CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt, | |
303 | NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS, | |
304 | RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support | |
305 | for mips32r2. | |
306 | ||
53f4826b TS |
307 | 2007-03-01 Thiemo Seufer <ths@mips.com> |
308 | ||
309 | * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32 | |
310 | and mips64. | |
311 | ||
8bf3ddc8 TS |
312 | 2007-02-20 Thiemo Seufer <ths@mips.com> |
313 | ||
314 | * dsp.igen: Update copyright notice. | |
315 | * dsp2.igen: Fix copyright notice. | |
316 | ||
8b082fb1 TS |
317 | 2007-02-20 Thiemo Seufer <ths@mips.com> |
318 | Chao-Ying Fu <fu@mips.com> | |
319 | ||
320 | * Makefile.in (IGEN_INCLUDE): Add dsp2.igen. | |
321 | * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*): | |
322 | Add dsp2 to sim_igen_machine. | |
323 | * configure: Regenerate. | |
324 | * dsp.igen (do_ph_op): Add MUL support when op = 2. | |
325 | (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph. | |
326 | (mulq_rs.ph): Use do_ph_mulq. | |
327 | (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen. | |
328 | * mips.igen: Add dsp2 model and include dsp2.igen. | |
329 | (MFHI, MFLO, MTHI, MTLO): Extend these instructions for | |
330 | for *mips32r2, *mips64r2, *dsp. | |
331 | (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions | |
332 | for *mips32r2, *mips64r2, *dsp2. | |
333 | * dsp2.igen: New file for MIPS DSP REV 2 ASE. | |
334 | ||
b1004875 TS |
335 | 2007-02-19 Thiemo Seufer <ths@mips.com> |
336 | Nigel Stephens <nigel@mips.com> | |
337 | ||
338 | * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2 | |
339 | jumps with hazard barrier. | |
340 | ||
f8df4c77 TS |
341 | 2007-02-19 Thiemo Seufer <ths@mips.com> |
342 | Nigel Stephens <nigel@mips.com> | |
343 | ||
344 | * interp.c (sim_monitor): Flush stdout and stderr file descriptors | |
345 | after each call to sim_io_write. | |
346 | ||
b1004875 | 347 | 2007-02-19 Thiemo Seufer <ths@mips.com> |
07802d98 | 348 | Nigel Stephens <nigel@mips.com> |
b1004875 TS |
349 | |
350 | * interp.c (ColdReset): Set CP0 Config0 to reflect the address size | |
351 | supported by this simulator. | |
07802d98 TS |
352 | (decode_coproc): Recognise additional CP0 Config registers |
353 | correctly. | |
354 | ||
14fb6c5a TS |
355 | 2007-02-19 Thiemo Seufer <ths@mips.com> |
356 | Nigel Stephens <nigel@mips.com> | |
357 | David Ung <davidu@mips.com> | |
358 | ||
359 | * cp1.c (value_fpr): Don't inherit existing FPR_STATE for | |
360 | uninterpreted formats. If fmt is one of the uninterpreted types | |
361 | don't update the FPR_STATE. Handle fmt_uninterpreted_32 like | |
362 | fmt_word, and fmt_uninterpreted_64 like fmt_long. | |
363 | (store_fpr): When writing an invalid odd register, set the | |
364 | matching even register to fmt_unknown, not the following register. | |
365 | * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to | |
366 | the the memory window at offset 0 set by --memory-size command | |
367 | line option. | |
368 | (sim_store_register): Handle storing 4 bytes to an 8 byte floating | |
369 | point register. | |
370 | (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte | |
371 | register. | |
372 | (sim_monitor): When returning the memory size to the MIPS | |
373 | application, use the value in STATE_MEM_SIZE, not an arbitrary | |
374 | hardcoded value. | |
375 | (cop_lw): Don' mess around with FPR_STATE, just pass | |
376 | fmt_uninterpreted_32 to StoreFPR. | |
377 | (cop_sw): Similarly. | |
378 | (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted. | |
379 | (cop_sd): Similarly. | |
380 | * mips.igen (not_word_value): Single version for mips32, mips64 | |
381 | and mips16. | |
382 | ||
c8847145 TS |
383 | 2007-02-19 Thiemo Seufer <ths@mips.com> |
384 | Nigel Stephens <nigel@mips.com> | |
385 | ||
386 | * interp.c (MEM_SIZE): Increase default memory size from 2 to 8 | |
387 | MBytes. | |
388 | ||
4b5d35ee TS |
389 | 2007-02-17 Thiemo Seufer <ths@mips.com> |
390 | ||
391 | * configure.ac (mips*-sde-elf*): Move in front of generic machine | |
392 | configuration. | |
393 | * configure: Regenerate. | |
394 | ||
3669427c TS |
395 | 2007-02-17 Thiemo Seufer <ths@mips.com> |
396 | ||
397 | * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*): | |
398 | Add mdmx to sim_igen_machine. | |
399 | (mipsisa64*-*-*): Likewise. Remove dsp. | |
400 | (mipsisa32*-*-*): Remove dsp. | |
401 | * configure: Regenerate. | |
402 | ||
109ad085 TS |
403 | 2007-02-13 Thiemo Seufer <ths@mips.com> |
404 | ||
405 | * configure.ac: Add mips*-sde-elf* target. | |
406 | * configure: Regenerate. | |
407 | ||
921d7ad3 HPN |
408 | 2006-12-21 Hans-Peter Nilsson <hp@axis.com> |
409 | ||
410 | * acconfig.h: Remove. | |
411 | * config.in, configure: Regenerate. | |
412 | ||
02f97da7 TS |
413 | 2006-11-07 Thiemo Seufer <ths@mips.com> |
414 | ||
415 | * dsp.igen (do_w_op): Fix compiler warning. | |
416 | ||
2d2733fc TS |
417 | 2006-08-29 Thiemo Seufer <ths@mips.com> |
418 | David Ung <davidu@mips.com> | |
419 | ||
420 | * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to | |
421 | sim_igen_machine. | |
422 | * configure: Regenerate. | |
423 | * mips.igen (model): Add smartmips. | |
424 | (MADDU): Increment ACX if carry. | |
425 | (do_mult): Clear ACX. | |
426 | (ROR,RORV): Add smartmips. | |
427 | (include): Include smartmips.igen. | |
428 | * sim-main.h (ACX): Set to REGISTERS[89]. | |
429 | * smartmips.igen: New file. | |
430 | ||
d85c3a10 TS |
431 | 2006-08-29 Thiemo Seufer <ths@mips.com> |
432 | David Ung <davidu@mips.com> | |
433 | ||
434 | * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and | |
435 | mips3264r2.igen. Add missing dependency rules. | |
436 | * m16e.igen: Support for mips16e save/restore instructions. | |
437 | ||
e85e3205 RE |
438 | 2006-06-13 Richard Earnshaw <rearnsha@arm.com> |
439 | ||
440 | * configure: Regenerated. | |
441 | ||
2f0122dc DJ |
442 | 2006-06-05 Daniel Jacobowitz <dan@codesourcery.com> |
443 | ||
444 | * configure: Regenerated. | |
445 | ||
20e95c23 DJ |
446 | 2006-05-31 Daniel Jacobowitz <dan@codesourcery.com> |
447 | ||
448 | * configure: Regenerated. | |
449 | ||
69088b17 CF |
450 | 2006-05-15 Chao-ying Fu <fu@mips.com> |
451 | ||
452 | * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions. | |
453 | ||
0275de4e NC |
454 | 2006-04-18 Nick Clifton <nickc@redhat.com> |
455 | ||
456 | * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break | |
457 | statement. | |
458 | ||
b3a3ffef HPN |
459 | 2006-03-29 Hans-Peter Nilsson <hp@axis.com> |
460 | ||
461 | * configure: Regenerate. | |
462 | ||
40a5538e CF |
463 | 2005-12-14 Chao-ying Fu <fu@mips.com> |
464 | ||
465 | * Makefile.in (SIM_OBJS): Add dsp.o. | |
466 | (dsp.o): New dependency. | |
467 | (IGEN_INCLUDE): Add dsp.igen. | |
468 | * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*, | |
469 | mipsisa64*-*-*): Add dsp to sim_igen_machine. | |
470 | * configure: Regenerate. | |
471 | * mips.igen: Add dsp model and include dsp.igen. | |
472 | (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2, | |
473 | because these instructions are extended in DSP ASE. | |
474 | * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of | |
475 | adding 6 DSP accumulator registers and 1 DSP control register. | |
476 | (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX, | |
477 | AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT, | |
478 | DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK, | |
479 | DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK, | |
480 | DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK, | |
481 | DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK, | |
482 | DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6, | |
483 | DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK, | |
484 | DSPCR_CCOND_SMASK): New define. | |
485 | (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators. | |
486 | * dsp.c, dsp.igen: New files for MIPS DSP ASE. | |
487 | ||
21d14896 ILT |
488 | 2005-07-08 Ian Lance Taylor <ian@airs.com> |
489 | ||
490 | * tconfig.in (SIM_QUIET_NAN_NEGATED): Define. | |
491 | ||
b16d63da DU |
492 | 2005-06-16 David Ung <davidu@mips.com> |
493 | Nigel Stephens <nigel@mips.com> | |
494 | ||
495 | * mips.igen: New mips16e model and include m16e.igen. | |
496 | (check_u64): Add mips16e tag. | |
497 | * m16e.igen: New file for MIPS16e instructions. | |
498 | * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*, | |
499 | mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e | |
500 | models. | |
501 | * configure: Regenerate. | |
502 | ||
e70cb6cd CD |
503 | 2005-05-26 David Ung <davidu@mips.com> |
504 | ||
505 | * mips.igen (mips32r2, mips64r2): New ISA models. Add new model | |
506 | tags to all instructions which are applicable to the new ISAs. | |
507 | (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from | |
508 | vr.igen. | |
509 | * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific | |
510 | instructions. | |
511 | * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move | |
512 | to mips.igen. | |
513 | * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets. | |
514 | * configure: Regenerate. | |
515 | ||
2b193c4a MK |
516 | 2005-03-23 Mark Kettenis <kettenis@gnu.org> |
517 | ||
518 | * configure: Regenerate. | |
519 | ||
35695fd6 AC |
520 | 2005-01-14 Andrew Cagney <cagney@gnu.org> |
521 | ||
522 | * configure.ac: Sinclude aclocal.m4 before common.m4. Add | |
523 | explicit call to AC_CONFIG_HEADER. | |
524 | * configure: Regenerate. | |
525 | ||
f0569246 AC |
526 | 2005-01-12 Andrew Cagney <cagney@gnu.org> |
527 | ||
528 | * configure.ac: Update to use ../common/common.m4. | |
529 | * configure: Re-generate. | |
530 | ||
38f48d72 AC |
531 | 2005-01-11 Andrew Cagney <cagney@localhost.localdomain> |
532 | ||
533 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
534 | ||
b7026657 AC |
535 | 2005-01-07 Andrew Cagney <cagney@gnu.org> |
536 | ||
537 | * configure.ac: Rename configure.in, require autoconf 2.59. | |
538 | * configure: Re-generate. | |
539 | ||
379832de HPN |
540 | 2004-12-08 Hans-Peter Nilsson <hp@axis.com> |
541 | ||
542 | * configure: Regenerate for ../common/aclocal.m4 update. | |
543 | ||
cd62154c AC |
544 | 2004-09-24 Monika Chaddha <monika@acmet.com> |
545 | ||
546 | Committed by Andrew Cagney. | |
547 | * m16.igen (CMP, CMPI): Fix assembler. | |
548 | ||
e5da76ec CD |
549 | 2004-08-18 Chris Demetriou <cgd@broadcom.com> |
550 | ||
551 | * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine. | |
552 | * configure: Regenerate. | |
553 | ||
139181c8 CD |
554 | 2004-06-25 Chris Demetriou <cgd@broadcom.com> |
555 | ||
556 | * configure.in (sim_m16_machine): Include mipsIII. | |
557 | * configure: Regenerate. | |
558 | ||
1a27f959 CD |
559 | 2004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl> |
560 | ||
561 | * mips/interp.c (decode_coproc): Sign-extend the address retrieved | |
562 | from COP0_BADVADDR. | |
563 | * mips/sim-main.h (COP0_BADVADDR): Remove a cast. | |
564 | ||
5dbb7b5a CD |
565 | 2004-04-10 Chris Demetriou <cgd@broadcom.com> |
566 | ||
567 | * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New. | |
568 | ||
14234056 CD |
569 | 2004-04-09 Chris Demetriou <cgd@broadcom.com> |
570 | ||
571 | * mips.igen (check_fmt): Remove. | |
572 | (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W) | |
573 | (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt) | |
574 | (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt) | |
575 | (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt) | |
576 | (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt) | |
577 | (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats. | |
578 | (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt) | |
579 | (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt) | |
580 | (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt. | |
581 | (C.cnd.fmta): Remove incorrect call to check_fmt_p. | |
582 | ||
c6f9085c CD |
583 | 2004-04-09 Chris Demetriou <cgd@broadcom.com> |
584 | ||
585 | * sb1.igen (check_sbx): New function. | |
586 | (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx. | |
587 | ||
11d66e66 | 588 | 2004-03-29 Chris Demetriou <cgd@broadcom.com> |
0e1b7197 RS |
589 | Richard Sandiford <rsandifo@redhat.com> |
590 | ||
591 | * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD) | |
592 | (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New. | |
593 | * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide | |
594 | separate implementations for mipsIV and mipsV. Use new macros to | |
595 | determine whether the restrictions apply. | |
596 | ||
b3208fb8 CD |
597 | 2004-01-19 Chris Demetriou <cgd@broadcom.com> |
598 | ||
599 | * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo) | |
600 | (check_mult_hilo): Improve comments. | |
601 | (check_div_hilo): Likewise. Also, fork off a new version | |
602 | to handle mips32/mips64 (since there are no hazards to check | |
603 | in MIPS32/MIPS64). | |
604 | ||
9a1d84fb CD |
605 | 2003-06-17 Richard Sandiford <rsandifo@redhat.com> |
606 | ||
607 | * mips.igen (do_dmultx): Fix check for negative operands. | |
608 | ||
ae451ac6 ILT |
609 | 2003-05-16 Ian Lance Taylor <ian@airs.com> |
610 | ||
611 | * Makefile.in (SHELL): Make sure this is defined. | |
612 | (various): Use $(SHELL) whenever we invoke move-if-change. | |
613 | ||
dd69d292 CD |
614 | 2003-05-03 Chris Demetriou <cgd@broadcom.com> |
615 | ||
616 | * cp1.c: Tweak attribution slightly. | |
617 | * cp1.h: Likewise. | |
618 | * mdmx.c: Likewise. | |
619 | * mdmx.igen: Likewise. | |
620 | * mips3d.igen: Likewise. | |
621 | * sb1.igen: Likewise. | |
622 | ||
bcd0068e CD |
623 | 2003-04-15 Richard Sandiford <rsandifo@redhat.com> |
624 | ||
625 | * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of | |
626 | unsigned operands. | |
627 | ||
6b4a8935 AC |
628 | 2003-02-27 Andrew Cagney <cagney@redhat.com> |
629 | ||
601da316 AC |
630 | * interp.c (sim_open): Rename _bfd to bfd. |
631 | (sim_create_inferior): Ditto. | |
6b4a8935 | 632 | |
d29e330f CD |
633 | 2003-01-14 Chris Demetriou <cgd@broadcom.com> |
634 | ||
635 | * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64. | |
636 | ||
a2353a08 CD |
637 | 2003-01-14 Chris Demetriou <cgd@broadcom.com> |
638 | ||
639 | * mips.igen (EI, DI): Remove. | |
640 | ||
80551777 CD |
641 | 2003-01-05 Richard Sandiford <rsandifo@redhat.com> |
642 | ||
643 | * Makefile.in (tmp-run-multi): Fix mips16 filter. | |
644 | ||
4c54fc26 CD |
645 | 2003-01-04 Richard Sandiford <rsandifo@redhat.com> |
646 | Andrew Cagney <ac131313@redhat.com> | |
647 | Gavin Romig-Koch <gavin@redhat.com> | |
648 | Graydon Hoare <graydon@redhat.com> | |
649 | Aldy Hernandez <aldyh@redhat.com> | |
650 | Dave Brolley <brolley@redhat.com> | |
651 | Chris Demetriou <cgd@broadcom.com> | |
652 | ||
653 | * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1. | |
654 | (sim_mach_default): New variable. | |
655 | (mips64vr-*-*, mips64vrel-*-*): New configurations. | |
656 | Add a new simulator generator, MULTI. | |
657 | * configure: Regenerate. | |
658 | * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables. | |
659 | (multi-run.o): New dependency. | |
660 | (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables. | |
661 | (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules. | |
662 | (tmp-multi): Combine them. | |
663 | (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi. | |
664 | (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI. | |
665 | (distclean-extra): New rule. | |
666 | * sim-main.h: Include bfd.h. | |
667 | (MIPS_MACH): New macro. | |
668 | * mips.igen (vr4120, vr5400, vr5500): New models. | |
669 | (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500. | |
670 | * vr.igen: Replace with new version. | |
671 | ||
e6c674b8 CD |
672 | 2003-01-04 Chris Demetriou <cgd@broadcom.com> |
673 | ||
674 | * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1). | |
675 | * configure: Regenerate. | |
676 | ||
28f50ac8 CD |
677 | 2002-12-31 Chris Demetriou <cgd@broadcom.com> |
678 | ||
679 | * sim-main.h (check_branch_bug, mark_branch_bug): Remove. | |
680 | * mips.igen: Remove all invocations of check_branch_bug and | |
681 | mark_branch_bug. | |
682 | ||
5071ffe6 CD |
683 | 2002-12-16 Chris Demetriou <cgd@broadcom.com> |
684 | ||
685 | * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h". | |
686 | ||
06e7837e CD |
687 | 2002-07-30 Chris Demetriou <cgd@broadcom.com> |
688 | ||
689 | * mips.igen (do_load_double, do_store_double): New functions. | |
690 | (LDC1, SDC1): Rename to... | |
691 | (LDC1b, SDC1b): respectively. | |
692 | (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support. | |
693 | ||
2265c243 MS |
694 | 2002-07-29 Michael Snyder <msnyder@redhat.com> |
695 | ||
696 | * cp1.c (fp_recip2): Modify initialization expression so that | |
697 | GCC will recognize it as constant. | |
698 | ||
a2f8b4f3 CD |
699 | 2002-06-18 Chris Demetriou <cgd@broadcom.com> |
700 | ||
701 | * mdmx.c (SD_): Delete. | |
702 | (Unpredictable): Re-define, for now, to directly invoke | |
703 | unpredictable_action(). | |
704 | (mdmx_acc_op): Fix error in .ob immediate handling. | |
705 | ||
b4b6c939 AC |
706 | 2002-06-18 Andrew Cagney <cagney@redhat.com> |
707 | ||
708 | * interp.c (sim_firmware_command): Initialize `address'. | |
709 | ||
c8cca39f AC |
710 | 2002-06-16 Andrew Cagney <ac131313@redhat.com> |
711 | ||
712 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
713 | ||
e7e81181 CD |
714 | 2002-06-14 Chris Demetriou <cgd@broadcom.com> |
715 | Ed Satterthwaite <ehs@broadcom.com> | |
716 | ||
717 | * mips3d.igen: New file which contains MIPS-3D ASE instructions. | |
718 | * Makefile.in (IGEN_INCLUDE): Add mips3d.igen. | |
719 | * mips.igen: Include mips3d.igen. | |
720 | (mips3d): New model name for MIPS-3D ASE instructions. | |
721 | (CVT.W.fmt): Don't use this instruction for word (source) format | |
722 | instructions. | |
723 | * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32) | |
724 | (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32) | |
725 | (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions. | |
726 | (NR_FRAC_GUARD, IMPLICIT_1): New macros. | |
727 | * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2) | |
728 | (RSquareRoot1, RSquareRoot2): New macros. | |
729 | (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1) | |
730 | (fp_rsqrt2): New functions. | |
731 | * configure.in: Add MIPS-3D support to mipsisa64 simulator. | |
732 | * configure: Regenerate. | |
733 | ||
3a2b820e | 734 | 2002-06-13 Chris Demetriou <cgd@broadcom.com> |
eab54952 | 735 | Ed Satterthwaite <ehs@broadcom.com> |
3a2b820e CD |
736 | |
737 | * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros. | |
738 | (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac) | |
739 | (fp_inv_sqrt, fpu_format_name): Add paired-single support. | |
740 | (convert): Note that this function is not used for paired-single | |
741 | format conversions. | |
742 | (ps_lower, ps_upper, pack_ps, convert_ps): New functions. | |
743 | * mips.igen (FMT, MOVtf.fmt): Add paired-single support. | |
744 | (check_fmt_p): Enable paired-single support. | |
745 | (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS) | |
746 | (PUU.PS): New instructions. | |
747 | (CVT.S.fmt): Don't use this instruction for paired-single format | |
748 | destinations. | |
749 | * sim-main.h (FP_formats): New value 'fmt_ps.' | |
750 | (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes. | |
751 | (PSLower, PSUpper, PackPS, ConvertPS): New macros. | |
752 | ||
d18ea9c2 CD |
753 | 2002-06-12 Chris Demetriou <cgd@broadcom.com> |
754 | ||
755 | * mips.igen: Fix formatting of function calls in | |
756 | many FP operations. | |
757 | ||
95fd5cee CD |
758 | 2002-06-12 Chris Demetriou <cgd@broadcom.com> |
759 | ||
760 | * mips.igen (MOVN, MOVZ): Trace result. | |
761 | (TNEI): Print "tnei" as the opcode name in traces. | |
762 | (CEIL.W): Add disassembly string for traces. | |
763 | (RSQRT.fmt): Make location of disassembly string consistent | |
764 | with other instructions. | |
765 | ||
4f0d55ae CD |
766 | 2002-06-12 Chris Demetriou <cgd@broadcom.com> |
767 | ||
768 | * mips.igen (X): Delete unused function. | |
769 | ||
3c25f8c7 AC |
770 | 2002-06-08 Andrew Cagney <cagney@redhat.com> |
771 | ||
772 | * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h". | |
773 | ||
f3c08b7e CD |
774 | 2002-06-07 Chris Demetriou <cgd@broadcom.com> |
775 | Ed Satterthwaite <ehs@broadcom.com> | |
776 | ||
777 | * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt) | |
778 | (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions. | |
779 | * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd) | |
780 | (fp_nmsub): New prototypes. | |
781 | (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd) | |
782 | (NegMultiplySub): New defines. | |
783 | * mips.igen (RSQRT.fmt): Use RSquareRoot(). | |
784 | (MADD.D, MADD.S): Replace with... | |
785 | (MADD.fmt): New instruction. | |
786 | (MSUB.D, MSUB.S): Replace with... | |
787 | (MSUB.fmt): New instruction. | |
788 | (NMADD.D, NMADD.S): Replace with... | |
789 | (NMADD.fmt): New instruction. | |
790 | (NMSUB.D, MSUB.S): Replace with... | |
791 | (NMSUB.fmt): New instruction. | |
792 | ||
52714ff9 CD |
793 | 2002-06-07 Chris Demetriou <cgd@broadcom.com> |
794 | Ed Satterthwaite <ehs@broadcom.com> | |
795 | ||
796 | * cp1.c: Fix more comment spelling and formatting. | |
797 | (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value. | |
798 | (denorm_mode): New function. | |
799 | (fpu_unary, fpu_binary): Round results after operation, collect | |
800 | status from rounding operations, and update the FCSR. | |
801 | (convert): Collect status from integer conversions and rounding | |
802 | operations, and update the FCSR. Adjust NaN values that result | |
803 | from conversions. Convert to use sim_io_eprintf rather than | |
804 | fprintf, and remove some debugging code. | |
805 | * cp1.h (fenr_FS): New define. | |
806 | ||
577d8c4b CD |
807 | 2002-06-07 Chris Demetriou <cgd@broadcom.com> |
808 | ||
809 | * cp1.c (convert): Remove unusable debugging code, and move MIPS | |
810 | rounding mode to sim FP rounding mode flag conversion code into... | |
811 | (rounding_mode): New function. | |
812 | ||
196496ed CD |
813 | 2002-06-07 Chris Demetriou <cgd@broadcom.com> |
814 | ||
815 | * cp1.c: Clean up formatting of a few comments. | |
816 | (value_fpr): Reformat switch statement. | |
817 | ||
cfe9ea23 CD |
818 | 2002-06-06 Chris Demetriou <cgd@broadcom.com> |
819 | Ed Satterthwaite <ehs@broadcom.com> | |
820 | ||
821 | * cp1.h: New file. | |
822 | * sim-main.h: Include cp1.h. | |
823 | (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE) | |
824 | (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF) | |
825 | (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h. | |
826 | (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove. | |
827 | (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes. | |
828 | (ValueFCR, StoreFCR, TestFCSR, Compare): New macros. | |
829 | * cp1.c: Don't include sim-fpu.h; already included by | |
830 | sim-main.h. Clean up formatting of some comments. | |
831 | (NaN, Equal, Less): Remove. | |
832 | (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test) | |
833 | (fp_cmp): New functions. | |
834 | * mips.igen (do_c_cond_fmt): Remove. | |
835 | (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with | |
836 | Compare. Add result tracing. | |
837 | (CxC1): Remove, replace with... | |
838 | (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions. | |
839 | (DMxC1): Remove, replace with... | |
840 | (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions. | |
841 | (MxC1): Remove, replace with... | |
842 | (MFC1a, MFC1b, MTC1a, MTC1b): New instructions. | |
843 | ||
ee7254b0 CD |
844 | 2002-06-04 Chris Demetriou <cgd@broadcom.com> |
845 | ||
846 | * sim-main.h (FGRIDX): Remove, replace all uses with... | |
847 | (FGR_BASE): New macro. | |
848 | (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros. | |
849 | (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member. | |
850 | (NR_FGR, FGR): Likewise. | |
851 | * interp.c: Replace all uses of FGRIDX with FGR_BASE. | |
852 | * mips.igen: Likewise. | |
853 | ||
d3eb724f CD |
854 | 2002-06-04 Chris Demetriou <cgd@broadcom.com> |
855 | ||
856 | * cp1.c: Add an FSF Copyright notice to this file. | |
857 | ||
ba46ddd0 CD |
858 | 2002-06-04 Chris Demetriou <cgd@broadcom.com> |
859 | Ed Satterthwaite <ehs@broadcom.com> | |
860 | ||
861 | * cp1.c (Infinity): Remove. | |
862 | * sim-main.h (Infinity): Likewise. | |
863 | ||
864 | * cp1.c (fp_unary, fp_binary): New functions. | |
865 | (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip) | |
866 | (fp_sqrt): New functions, implemented in terms of the above. | |
867 | (AbsoluteValue, Negate, Add, Sub, Multiply, Divide) | |
868 | (Recip, SquareRoot): Remove (replaced by functions above). | |
869 | * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div) | |
870 | (fp_recip, fp_sqrt): New prototypes. | |
871 | (AbsoluteValue, Negate, Add, Sub, Multiply, Divide) | |
872 | (Recip, SquareRoot): Replace prototypes with #defines which | |
873 | invoke the functions above. | |
874 | ||
18d8a52d CD |
875 | 2002-06-03 Chris Demetriou <cgd@broadcom.com> |
876 | ||
877 | * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate) | |
878 | (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in | |
879 | file, remove PARAMS from prototypes. | |
880 | (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide | |
881 | simulator state arguments. | |
882 | (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to | |
883 | pass simulator state arguments. | |
884 | * cp1.c (SD): Redefine as CPU_STATE(cpu). | |
885 | (store_fpr, convert): Remove 'sd' argument. | |
886 | (value_fpr): Likewise. Convert to use 'SD' instead. | |
887 | ||
0f154cbd CD |
888 | 2002-06-03 Chris Demetriou <cgd@broadcom.com> |
889 | ||
890 | * cp1.c (Min, Max): Remove #if 0'd functions. | |
891 | * sim-main.h (Min, Max): Remove. | |
892 | ||
e80fc152 CD |
893 | 2002-06-03 Chris Demetriou <cgd@broadcom.com> |
894 | ||
895 | * cp1.c: fix formatting of switch case and default labels. | |
896 | * interp.c: Likewise. | |
897 | * sim-main.c: Likewise. | |
898 | ||
bad673a9 CD |
899 | 2002-06-03 Chris Demetriou <cgd@broadcom.com> |
900 | ||
901 | * cp1.c: Clean up comments which describe FP formats. | |
902 | (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64. | |
903 | ||
7cbea089 CD |
904 | 2002-06-03 Chris Demetriou <cgd@broadcom.com> |
905 | Ed Satterthwaite <ehs@broadcom.com> | |
906 | ||
907 | * configure.in (mipsisa64sb1*-*-*): New target for supporting | |
908 | Broadcom SiByte SB-1 processor configurations. | |
909 | * configure: Regenerate. | |
910 | * sb1.igen: New file. | |
911 | * mips.igen: Include sb1.igen. | |
912 | (sb1): New model. | |
913 | * Makefile.in (IGEN_INCLUDE): Add sb1.igen. | |
914 | * mdmx.igen: Add "sb1" model to all appropriate functions and | |
915 | instructions. | |
916 | * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions. | |
917 | (ob_func, ob_acc): Reference the above. | |
918 | (qh_acc): Adjust to keep the same size as ob_acc. | |
919 | * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff) | |
920 | (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros. | |
921 | ||
909daa82 CD |
922 | 2002-06-03 Chris Demetriou <cgd@broadcom.com> |
923 | ||
924 | * Makefile.in (IGEN_INCLUDE): Add mdmx.igen. | |
925 | ||
f4f1b9f1 CD |
926 | 2002-06-02 Chris Demetriou <cgd@broadcom.com> |
927 | Ed Satterthwaite <ehs@broadcom.com> | |
928 | ||
929 | * mips.igen (mdmx): New (pseudo-)model. | |
930 | * mdmx.c, mdmx.igen: New files. | |
931 | * Makefile.in (SIM_OBJS): Add mdmx.o. | |
932 | * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48): | |
933 | New typedefs. | |
934 | (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp) | |
935 | (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA) | |
936 | (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC) | |
937 | (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS) | |
938 | (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES) | |
939 | (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical) | |
940 | (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL) | |
941 | (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND) | |
942 | (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA) | |
943 | (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR) | |
944 | (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB) | |
945 | (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor) | |
946 | (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel) | |
947 | (qh_fmtsel): New macros. | |
948 | (_sim_cpu): New member "acc". | |
949 | (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op) | |
950 | (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions. | |
951 | ||
5accf1ff CD |
952 | 2002-05-01 Chris Demetriou <cgd@broadcom.com> |
953 | ||
954 | * interp.c: Use 'deprecated' rather than 'depreciated.' | |
955 | * sim-main.h: Likewise. | |
956 | ||
402586aa CD |
957 | 2002-05-01 Chris Demetriou <cgd@broadcom.com> |
958 | ||
959 | * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult | |
960 | which wouldn't compile anyway. | |
961 | * sim-main.h (unpredictable_action): New function prototype. | |
962 | (Unpredictable): Define to call igen function unpredictable(). | |
963 | (NotWordValue): New macro to call igen function not_word_value(). | |
964 | (UndefinedResult): Remove. | |
965 | * interp.c (undefined_result): Remove. | |
966 | (unpredictable_action): New function. | |
967 | * mips.igen (not_word_value, unpredictable): New functions. | |
968 | (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL) | |
969 | (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu) | |
970 | (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke | |
971 | NotWordValue() to check for unpredictable inputs, then | |
972 | Unpredictable() to handle them. | |
973 | ||
c9b9995a CD |
974 | 2002-02-24 Chris Demetriou <cgd@broadcom.com> |
975 | ||
976 | * mips.igen: Fix formatting of calls to Unpredictable(). | |
977 | ||
e1015982 AC |
978 | 2002-04-20 Andrew Cagney <ac131313@redhat.com> |
979 | ||
980 | * interp.c (sim_open): Revert previous change. | |
981 | ||
b882a66b AO |
982 | 2002-04-18 Alexandre Oliva <aoliva@redhat.com> |
983 | ||
984 | * interp.c (sim_open): Disable chunk of code that wrote code in | |
985 | vector table entries. | |
986 | ||
c429b7dd CD |
987 | 2002-03-19 Chris Demetriou <cgd@broadcom.com> |
988 | ||
989 | * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f) | |
990 | (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove | |
991 | unused definitions. | |
992 | ||
37d146fa CD |
993 | 2002-03-19 Chris Demetriou <cgd@broadcom.com> |
994 | ||
995 | * cp1.c: Fix many formatting issues. | |
996 | ||
07892c0b CD |
997 | 2002-03-19 Chris G. Demetriou <cgd@broadcom.com> |
998 | ||
999 | * cp1.c (fpu_format_name): New function to replace... | |
1000 | (DOFMT): This. Delete, and update all callers. | |
1001 | (fpu_rounding_mode_name): New function to replace... | |
1002 | (RMMODE): This. Delete, and update all callers. | |
1003 | ||
487f79b7 CD |
1004 | 2002-03-19 Chris G. Demetriou <cgd@broadcom.com> |
1005 | ||
1006 | * interp.c: Move FPU support routines from here to... | |
1007 | * cp1.c: Here. New file. | |
1008 | * Makefile.in (SIM_OBJS): Add cp1.o to object list. | |
1009 | (cp1.o): New target. | |
1010 | ||
1e799e28 CD |
1011 | 2002-03-12 Chris Demetriou <cgd@broadcom.com> |
1012 | ||
1013 | * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets. | |
1014 | * mips.igen (mips32, mips64): New models, add to all instructions | |
1015 | and functions as appropriate. | |
1016 | (loadstore_ea, check_u64): New variant for model mips64. | |
1017 | (check_fmt_p): New variant for models mipsV and mips64, remove | |
1018 | mipsV model marking fro other variant. | |
1019 | (SLL) Rename to... | |
1020 | (SLLa) this. | |
1021 | (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions | |
1022 | for mips32 and mips64. | |
1023 | (DCLO, DCLZ): New instructions for mips64. | |
1024 | ||
82f728db CD |
1025 | 2002-03-07 Chris Demetriou <cgd@broadcom.com> |
1026 | ||
1027 | * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print | |
1028 | immediate or code as a hex value with the "%#lx" format. | |
1029 | (ANDI): Likewise, and fix printed instruction name. | |
1030 | ||
b96e7ef1 CD |
1031 | 2002-03-05 Chris Demetriou <cgd@broadcom.com> |
1032 | ||
1033 | * sim-main.h (UndefinedResult, Unpredictable): New macros | |
1034 | which currently do nothing. | |
1035 | ||
d35d4f70 CD |
1036 | 2002-03-05 Chris Demetriou <cgd@broadcom.com> |
1037 | ||
1038 | * sim-main.h (status_UX, status_SX, status_KX, status_TS) | |
1039 | (status_PX, status_MX, status_CU0, status_CU1, status_CU2) | |
1040 | (status_CU3): New definitions. | |
1041 | ||
1042 | * sim-main.h (ExceptionCause): Add new values for MIPS32 | |
1043 | and MIPS64: MDMX, MCheck, CacheErr. Update comments | |
1044 | for DebugBreakPoint and NMIReset to note their status in | |
1045 | MIPS32 and MIPS64. | |
1046 | (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck) | |
1047 | (SignalExceptionCacheErr): New exception macros. | |
1048 | ||
3ad6f714 CD |
1049 | 2002-03-05 Chris Demetriou <cgd@broadcom.com> |
1050 | ||
1051 | * mips.igen (check_fpu): Enable check for coprocessor 1 usability. | |
1052 | * sim-main.h (COP_Usable): Define, but for now coprocessor 1 | |
1053 | is always enabled. | |
1054 | (SignalExceptionCoProcessorUnusable): Take as argument the | |
1055 | unusable coprocessor number. | |
1056 | ||
86b77b47 CD |
1057 | 2002-03-05 Chris Demetriou <cgd@broadcom.com> |
1058 | ||
1059 | * mips.igen: Fix formatting of all SignalException calls. | |
1060 | ||
97a88e93 | 1061 | 2002-03-05 Chris Demetriou <cgd@broadcom.com> |
3dea6720 CD |
1062 | |
1063 | * sim-main.h (SIGNEXTEND): Remove. | |
1064 | ||
97a88e93 | 1065 | 2002-03-04 Chris Demetriou <cgd@broadcom.com> |
b5040d49 CD |
1066 | |
1067 | * mips.igen: Remove gencode comment from top of file, fix | |
1068 | spelling in another comment. | |
1069 | ||
97a88e93 | 1070 | 2002-03-04 Chris Demetriou <cgd@broadcom.com> |
8612006b CD |
1071 | |
1072 | * mips.igen (check_fmt, check_fmt_p): New functions to check | |
1073 | whether specific floating point formats are usable. | |
1074 | (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt) | |
1075 | (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt) | |
1076 | (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W): | |
1077 | Use the new functions. | |
1078 | (do_c_cond_fmt): Remove format checks... | |
1079 | (C.cond.fmta, C.cond.fmtb): And move them into all callers. | |
1080 | ||
97a88e93 | 1081 | 2002-03-03 Chris Demetriou <cgd@broadcom.com> |
9b17d183 CD |
1082 | |
1083 | * mips.igen: Fix formatting of check_fpu calls. | |
1084 | ||
41774c9d CD |
1085 | 2002-03-03 Chris Demetriou <cgd@broadcom.com> |
1086 | ||
1087 | * mips.igen (FLOOR.L.fmt): Store correct destination register. | |
1088 | ||
4a0bd876 CD |
1089 | 2002-03-03 Chris Demetriou <cgd@broadcom.com> |
1090 | ||
1091 | * mips.igen: Remove whitespace at end of lines. | |
1092 | ||
09297648 CD |
1093 | 2002-03-02 Chris Demetriou <cgd@broadcom.com> |
1094 | ||
1095 | * mips.igen (loadstore_ea): New function to do effective | |
1096 | address calculations. | |
1097 | (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store, | |
1098 | do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1, | |
1099 | CACHE): Use loadstore_ea to do effective address computations. | |
1100 | ||
043b7057 CD |
1101 | 2002-03-02 Chris Demetriou <cgd@broadcom.com> |
1102 | ||
1103 | * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND. | |
1104 | * mips.igen (LL, CxC1, MxC1): Likewise. | |
1105 | ||
c1e8ada4 CD |
1106 | 2002-03-02 Chris Demetriou <cgd@broadcom.com> |
1107 | ||
1108 | * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt, | |
1109 | CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, | |
1110 | FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt, | |
1111 | MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D, | |
1112 | NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, | |
1113 | SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE): | |
1114 | Don't split opcode fields by hand, use the opcode field values | |
1115 | provided by igen. | |
1116 | ||
3e1dca16 CD |
1117 | 2002-03-01 Chris Demetriou <cgd@broadcom.com> |
1118 | ||
1119 | * mips.igen (do_divu): Fix spacing. | |
1120 | ||
1121 | * mips.igen (do_dsllv): Move to be right before DSLLV, | |
1122 | to match the rest of the do_<shift> functions. | |
1123 | ||
fff8d27d CD |
1124 | 2002-03-01 Chris Demetriou <cgd@broadcom.com> |
1125 | ||
1126 | * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl, | |
1127 | DSRL32, do_dsrlv): Trace inputs and results. | |
1128 | ||
0d3e762b CD |
1129 | 2002-03-01 Chris Demetriou <cgd@broadcom.com> |
1130 | ||
1131 | * mips.igen (CACHE): Provide instruction-printing string. | |
1132 | ||
1133 | * interp.c (signal_exception): Comment tokens after #endif. | |
1134 | ||
eb5fcf93 CD |
1135 | 2002-02-28 Chris Demetriou <cgd@broadcom.com> |
1136 | ||
1137 | * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32". | |
1138 | (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt, | |
1139 | NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt, | |
1140 | ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt, | |
1141 | CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta, | |
1142 | C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1, | |
1143 | SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D, | |
1144 | LWC1, SWC1): Add "f" to filter, since these are FP instructions. | |
1145 | ||
bb22bd7d CD |
1146 | 2002-02-28 Chris Demetriou <cgd@broadcom.com> |
1147 | ||
1148 | * mips.igen (DSRA32, DSRAV): Fix order of arguments in | |
1149 | instruction-printing string. | |
1150 | (LWU): Use '64' as the filter flag. | |
1151 | ||
91a177cf CD |
1152 | 2002-02-28 Chris Demetriou <cgd@broadcom.com> |
1153 | ||
1154 | * mips.igen (SDXC1): Fix instruction-printing string. | |
1155 | ||
387f484a CD |
1156 | 2002-02-28 Chris Demetriou <cgd@broadcom.com> |
1157 | ||
1158 | * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with | |
1159 | filter flags "32,f". | |
1160 | ||
3d81f391 CD |
1161 | 2002-02-27 Chris Demetriou <cgd@broadcom.com> |
1162 | ||
1163 | * mips.igen (PREFX): This is a 64-bit instruction, use '64' | |
1164 | as the filter flag. | |
1165 | ||
af5107af CD |
1166 | 2002-02-27 Chris Demetriou <cgd@broadcom.com> |
1167 | ||
1168 | * mips.igen (PREFX): Tweak instruction opcode fields (i.e., | |
1169 | add a comma) so that it more closely match the MIPS ISA | |
1170 | documentation opcode partitioning. | |
1171 | (PREF): Put useful names on opcode fields, and include | |
1172 | instruction-printing string. | |
1173 | ||
ca971540 CD |
1174 | 2002-02-27 Chris Demetriou <cgd@broadcom.com> |
1175 | ||
1176 | * mips.igen (check_u64): New function which in the future will | |
1177 | check whether 64-bit instructions are usable and signal an | |
1178 | exception if not. Currently a no-op. | |
1179 | (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL, | |
1180 | DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, | |
1181 | DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1, | |
1182 | LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64. | |
1183 | ||
1184 | * mips.igen (check_fpu): New function which in the future will | |
1185 | check whether FPU instructions are usable and signal an exception | |
1186 | if not. Currently a no-op. | |
1187 | (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb, | |
1188 | CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, | |
1189 | CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1, | |
1190 | LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf, | |
1191 | MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, | |
1192 | NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt, | |
1193 | ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1, | |
1194 | SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu. | |
1195 | ||
1c47a468 CD |
1196 | 2002-02-27 Chris Demetriou <cgd@broadcom.com> |
1197 | ||
1198 | * mips.igen (do_load_left, do_load_right): Move to be immediately | |
1199 | following do_load. | |
1200 | (do_store_left, do_store_right): Move to be immediately following | |
1201 | do_store. | |
1202 | ||
603a98e7 CD |
1203 | 2002-02-27 Chris Demetriou <cgd@broadcom.com> |
1204 | ||
1205 | * mips.igen (mipsV): New model name. Also, add it to | |
1206 | all instructions and functions where it is appropriate. | |
1207 | ||
c5d00cc7 CD |
1208 | 2002-02-18 Chris Demetriou <cgd@broadcom.com> |
1209 | ||
1210 | * mips.igen: For all functions and instructions, list model | |
1211 | names that support that instruction one per line. | |
1212 | ||
074e9cb8 CD |
1213 | 2002-02-11 Chris Demetriou <cgd@broadcom.com> |
1214 | ||
1215 | * mips.igen: Add some additional comments about supported | |
1216 | models, and about which instructions go where. | |
1217 | (BC1b, MFC0, MTC0, RFE): Sort supported models in the same | |
1218 | order as is used in the rest of the file. | |
1219 | ||
9805e229 CD |
1220 | 2002-02-11 Chris Demetriou <cgd@broadcom.com> |
1221 | ||
1222 | * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment | |
1223 | indicating that ALU32_END or ALU64_END are there to check | |
1224 | for overflow. | |
1225 | (DADD): Likewise, but also remove previous comment about | |
1226 | overflow checking. | |
1227 | ||
f701dad2 CD |
1228 | 2002-02-10 Chris Demetriou <cgd@broadcom.com> |
1229 | ||
1230 | * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32, | |
1231 | DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU, | |
1232 | JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU, | |
1233 | SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI, | |
1234 | ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode | |
1235 | fields (i.e., add and move commas) so that they more closely | |
1236 | match the MIPS ISA documentation opcode partitioning. | |
1237 | ||
1238 | 2002-02-10 Chris Demetriou <cgd@broadcom.com> | |
20ae0098 CD |
1239 | |
1240 | * mips.igen (ADDI): Print immediate value. | |
1241 | (BREAK): Print code. | |
1242 | (DADDIU, DSRAV, DSRLV): Print correct instruction name. | |
1243 | (SLL): Print "nop" specially, and don't run the code | |
1244 | that does the shift for the "nop" case. | |
1245 | ||
9e52972e FF |
1246 | 2001-11-17 Fred Fish <fnf@redhat.com> |
1247 | ||
1248 | * sim-main.h (float_operation): Move enum declaration outside | |
1249 | of _sim_cpu struct declaration. | |
1250 | ||
c0efbca4 JB |
1251 | 2001-04-12 Jim Blandy <jimb@redhat.com> |
1252 | ||
1253 | * mips.igen (CFC1, CTC1): Pass the correct register numbers to | |
1254 | PENDING_FILL. Use PENDING_SCHED directly to handle the pending | |
1255 | set of the FCSR. | |
1256 | * sim-main.h (COCIDX): Remove definition; this isn't supported by | |
1257 | PENDING_FILL, and you can get the intended effect gracefully by | |
1258 | calling PENDING_SCHED directly. | |
1259 | ||
fb891446 BE |
1260 | 2001-02-23 Ben Elliston <bje@redhat.com> |
1261 | ||
1262 | * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not | |
1263 | already defined elsewhere. | |
1264 | ||
8030f857 BE |
1265 | 2001-02-19 Ben Elliston <bje@redhat.com> |
1266 | ||
1267 | * sim-main.h (sim_monitor): Return an int. | |
1268 | * interp.c (sim_monitor): Add return values. | |
1269 | (signal_exception): Handle error conditions from sim_monitor. | |
1270 | ||
56b48a7a CD |
1271 | 2001-02-08 Ben Elliston <bje@redhat.com> |
1272 | ||
1273 | * sim-main.c (load_memory): Pass cia to sim_core_read* functions. | |
1274 | (store_memory): Likewise, pass cia to sim_core_write*. | |
1275 | ||
d3ee60d9 FCE |
1276 | 2000-10-19 Frank Ch. Eigler <fche@redhat.com> |
1277 | ||
1278 | On advice from Chris G. Demetriou <cgd@sibyte.com>: | |
1279 | * sim-main.h (GPR_CLEAR): Remove unused alternative macro. | |
1280 | ||
071da002 AC |
1281 | Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com> |
1282 | ||
1283 | From Maciej W. Rozycki <macro@ds2.pg.gda.pl>: | |
1284 | * Makefile.in: Don't delete *.igen when cleaning directory. | |
1285 | ||
a28c02cd AC |
1286 | Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com> |
1287 | ||
1288 | * m16.igen (break): Call SignalException not sim_engine_halt. | |
1289 | ||
80ee11fa AC |
1290 | Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com> |
1291 | ||
1292 | From Jason Eckhardt: | |
1293 | * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT]. | |
1294 | ||
673388c0 AC |
1295 | Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com> |
1296 | ||
1297 | * mips.igen (MxC1, DMxC1): Fix printf formatting. | |
1298 | ||
4c0deff4 NC |
1299 | 2000-05-24 Michael Hayes <mhayes@cygnus.com> |
1300 | ||
1301 | * mips.igen (do_dmultx): Fix typo. | |
1302 | ||
eb2d80b4 AC |
1303 | Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com> |
1304 | ||
1305 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
1306 | ||
dd37a34b AC |
1307 | Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com> |
1308 | ||
1309 | * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call. | |
1310 | ||
4c0deff4 NC |
1311 | 2000-04-12 Frank Ch. Eigler <fche@redhat.com> |
1312 | ||
1313 | * sim-main.h (GPR_CLEAR): Define macro. | |
1314 | ||
e30db738 AC |
1315 | Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com> |
1316 | ||
1317 | * interp.c (decode_coproc): Output long using %lx and not %s. | |
1318 | ||
cb7450ea FCE |
1319 | 2000-03-21 Frank Ch. Eigler <fche@redhat.com> |
1320 | ||
1321 | * interp.c (sim_open): Sort & extend dummy memory regions for | |
1322 | --board=jmr3904 for eCos. | |
1323 | ||
a3027dd7 FCE |
1324 | 2000-03-02 Frank Ch. Eigler <fche@redhat.com> |
1325 | ||
1326 | * configure: Regenerated. | |
1327 | ||
1328 | Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com> | |
1329 | ||
1330 | * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf | |
1331 | calls, conditional on the simulator being in verbose mode. | |
1332 | ||
dfcd3bfb JM |
1333 | Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com> |
1334 | ||
1335 | * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary | |
1336 | cache don't get ReservedInstruction traps. | |
1337 | ||
c2d11a7d JM |
1338 | 1999-11-29 Mark Salter <msalter@cygnus.com> |
1339 | ||
1340 | * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask | |
1341 | to clear status bits in sdisr register. This is how the hardware works. | |
1342 | ||
1343 | * interp.c (sim_open): Added more memory aliases for jmr3904 hardware | |
1344 | being used by cygmon. | |
1345 | ||
4ce44c66 JM |
1346 | 1999-11-11 Andrew Haley <aph@cygnus.com> |
1347 | ||
1348 | * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0 | |
1349 | instructions. | |
1350 | ||
cff3e48b JM |
1351 | Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com> |
1352 | ||
1353 | * mips.igen (MULT): Correct previous mis-applied patch. | |
1354 | ||
d4f3574e SS |
1355 | Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com> |
1356 | ||
1357 | * mips.igen (delayslot32): Handle sequence like | |
1358 | mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12 | |
1359 | correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue. | |
1360 | (MULT): Actually pass the third register... | |
1361 | ||
1362 | 1999-09-03 Mark Salter <msalter@cygnus.com> | |
1363 | ||
1364 | * interp.c (sim_open): Added more memory aliases for additional | |
1365 | hardware being touched by cygmon on jmr3904 board. | |
1366 | ||
1367 | Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com> | |
1368 | ||
1369 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
1370 | ||
a0b3c4fd JM |
1371 | Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com> |
1372 | ||
1373 | * interp.c (sim_store_register): Handle case where client - GDB - | |
1374 | specifies that a 4 byte register is 8 bytes in size. | |
1375 | (sim_fetch_register): Ditto. | |
1376 | ||
adf40b2e JM |
1377 | 1999-07-14 Frank Ch. Eigler <fche@cygnus.com> |
1378 | ||
1379 | Implement "sim firmware" option, inspired by jimb's version of 1998-01. | |
1380 | * interp.c (firmware_option_p): New global flag: "sim firmware" given. | |
1381 | (idt_monitor_base): Base address for IDT monitor traps. | |
1382 | (pmon_monitor_base): Ditto for PMON. | |
1383 | (lsipmon_monitor_base): Ditto for LSI PMON. | |
1384 | (MONITOR_BASE, MONITOR_SIZE): Removed macros. | |
1385 | (mips_option): Add "firmware" option with new OPTION_FIRMWARE key. | |
1386 | (sim_firmware_command): New function. | |
1387 | (mips_option_handler): Call it for OPTION_FIRMWARE. | |
1388 | (sim_open): Allocate memory for idt_monitor region. If "--board" | |
1389 | option was given, add no monitor by default. Add BREAK hooks only if | |
1390 | monitors are also there. | |
1391 | ||
43e526b9 JM |
1392 | Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com> |
1393 | ||
1394 | * interp.c (sim_monitor): Flush output before reading input. | |
1395 | ||
1396 | Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com> | |
1397 | ||
1398 | * tconfig.in (SIM_HANDLES_LMA): Always define. | |
1399 | ||
1400 | Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com> | |
1401 | ||
1402 | From Mark Salter <msalter@cygnus.com>: | |
1403 | * interp.c (BOARD_BSP): Define. Add to list of possible boards. | |
1404 | (sim_open): Add setup for BSP board. | |
1405 | ||
9846de1b JM |
1406 | Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com> |
1407 | ||
1408 | * mips.igen (MULT, MULTU): Add syntax for two operand version. | |
1409 | (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report | |
1410 | them as unimplemented. | |
1411 | ||
cd0fc7c3 SS |
1412 | 1999-05-08 Felix Lee <flee@cygnus.com> |
1413 | ||
1414 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
1415 | ||
7a292a7a SS |
1416 | 1999-04-21 Frank Ch. Eigler <fche@cygnus.com> |
1417 | ||
1418 | * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub. | |
1419 | ||
1420 | Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com> | |
1421 | ||
1422 | * configure.in: Any mips64vr5*-*-* target should have | |
1423 | -DTARGET_ENABLE_FR=1. | |
1424 | (default_endian): Any mips64vr*el-*-* target should default to | |
1425 | LITTLE_ENDIAN. | |
1426 | * configure: Re-generate. | |
1427 | ||
1428 | 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com> | |
1429 | ||
1430 | * mips.igen (ldl): Extend from _16_, not 32. | |
1431 | ||
1432 | Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com> | |
1433 | ||
1434 | * interp.c (sim_store_register): Force registers written to by GDB | |
1435 | into an un-interpreted state. | |
1436 | ||
c906108c SS |
1437 | 1999-02-05 Frank Ch. Eigler <fche@cygnus.com> |
1438 | ||
1439 | * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the | |
1440 | CPU, start periodic background I/O polls. | |
1441 | (tx3904sio_poll): New function: periodic I/O poller. | |
1442 | ||
1443 | 1998-12-30 Frank Ch. Eigler <fche@cygnus.com> | |
1444 | ||
1445 | * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt. | |
1446 | ||
1447 | Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE> | |
1448 | ||
1449 | * configure.in, configure (mips64vr5*-*-*): Added missing ;; in | |
1450 | case statement. | |
1451 | ||
1452 | 1998-12-29 Frank Ch. Eigler <fche@cygnus.com> | |
1453 | ||
1454 | * interp.c (sim_open): Allocate jm3904 memory in smaller chunks. | |
1455 | (load_word): Call SIM_CORE_SIGNAL hook on error. | |
1456 | (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before | |
1457 | starting. For exception dispatching, pass PC instead of NULL_CIA. | |
1458 | (decode_coproc): Use COP0_BADVADDR to store faulting address. | |
1459 | * sim-main.h (COP0_BADVADDR): Define. | |
1460 | (SIM_CORE_SIGNAL): Define hook to call mips_core_signal. | |
1461 | (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*(). | |
1462 | (_sim_cpu): Add exc_* fields to store register value snapshots. | |
1463 | * mips.igen (*): Replace memory-related SignalException* calls | |
1464 | with references to SIM_CORE_SIGNAL hook. | |
1465 | ||
1466 | * dv-tx3904irc.c (tx3904irc_port_event): printf format warning | |
1467 | fix. | |
1468 | * sim-main.c (*): Minor warning cleanups. | |
1469 | ||
1470 | 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com> | |
1471 | ||
1472 | * m16.igen (DADDIU5): Correct type-o. | |
1473 | ||
1474 | Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook> | |
1475 | ||
1476 | * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp | |
1477 | variables. | |
1478 | ||
1479 | Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook> | |
1480 | ||
1481 | * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib | |
1482 | to include path. | |
1483 | (interp.o): Add dependency on itable.h | |
1484 | (oengine.c, gencode): Delete remaining references. | |
1485 | (BUILT_SRC_FROM_GEN): Clean up. | |
1486 | ||
1487 | 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com> | |
1488 | ||
1489 | * vr4run.c: New. | |
1490 | * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a, | |
1491 | tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack, | |
1492 | tmp-run-hack) : New. | |
1493 | * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU, | |
1494 | DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX): | |
1495 | Drop the "64" qualifier to get the HACK generator working. | |
1496 | Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT. | |
1497 | * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only | |
1498 | qualifier to get the hack generator working. | |
1499 | (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New. | |
1500 | (DSLL): Use do_dsll. | |
1501 | (DSLLV): Use do_dsllv. | |
1502 | (DSRA): Use do_dsra. | |
1503 | (DSRL): Use do_dsrl. | |
1504 | (DSRLV): Use do_dsrlv. | |
1505 | (BC1): Move *vr4100 to get the HACK generator working. | |
1506 | (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to | |
1507 | get the HACK generator working. | |
1508 | (MACC) Rename to get the HACK generator working. | |
1509 | (DMACC,MACCS,DMACCS): Add the 64. | |
1510 | ||
1511 | 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com> | |
1512 | ||
1513 | * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts. | |
1514 | * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR. | |
1515 | ||
1516 | 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com> | |
1517 | ||
1518 | * mips/interp.c (DEBUG): Cleanups. | |
1519 | ||
1520 | 1998-12-10 Frank Ch. Eigler <fche@cygnus.com> | |
1521 | ||
1522 | * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes. | |
1523 | (tx3904sio_tickle): fflush after a stdout character output. | |
1524 | ||
1525 | 1998-12-03 Frank Ch. Eigler <fche@cygnus.com> | |
1526 | ||
1527 | * interp.c (sim_close): Uninstall modules. | |
1528 | ||
1529 | Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
1530 | ||
1531 | * sim-main.h, interp.c (sim_monitor): Change to global | |
1532 | function. | |
1533 | ||
1534 | Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
1535 | ||
1536 | * configure.in (vr4100): Only include vr4100 instructions in | |
1537 | simulator. | |
1538 | * configure: Re-generate. | |
1539 | * m16.igen (*): Tag all mips16 instructions as also being vr4100. | |
1540 | ||
1541 | Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
1542 | ||
1543 | * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN. | |
1544 | * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping | |
1545 | true alternative. | |
1546 | ||
1547 | * configure.in (sim_default_gen, sim_use_gen): Replace with | |
1548 | sim_gen. | |
1549 | (--enable-sim-igen): Delete config option. Always using IGEN. | |
1550 | * configure: Re-generate. | |
1551 | ||
1552 | * Makefile.in (gencode): Kill, kill, kill. | |
1553 | * gencode.c: Ditto. | |
1554 | ||
1555 | Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
1556 | ||
1557 | * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64 | |
1558 | bit mips16 igen simulator. | |
1559 | * configure: Re-generate. | |
1560 | ||
1561 | * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark | |
1562 | as part of vr4100 ISA. | |
1563 | * vr.igen: Mark all instructions as 64 bit only. | |
1564 | ||
1565 | Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
1566 | ||
1567 | * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent): | |
1568 | Pacify GCC. | |
1569 | ||
1570 | Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
1571 | ||
1572 | * configure.in: Configure mips-lsi-elf nee mips*lsi* as a | |
1573 | mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos. | |
1574 | * configure: Re-generate. | |
1575 | ||
1576 | * m16.igen (BREAK): Define breakpoint instruction. | |
1577 | (JALX32): Mark instruction as mips16 and not r3900. | |
1578 | * mips.igen (C.cond.fmt): Fix typo in instruction format. | |
1579 | ||
1580 | * sim-main.h (PENDING_FILL): Wrap C statements in do/while. | |
1581 | ||
1582 | Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
1583 | ||
1584 | * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK | |
1585 | insn as a debug breakpoint. | |
1586 | ||
1587 | * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as | |
1588 | pending.slot_size. | |
1589 | (PENDING_SCHED): Clean up trace statement. | |
1590 | (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL. | |
1591 | (PENDING_FILL): Delay write by only one cycle. | |
1592 | (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE. | |
1593 | ||
1594 | * sim-main.c (pending_tick): Clean up trace statements. Add trace | |
1595 | of pending writes. | |
1596 | (pending_tick): Fix sizes in switch statements, 4 & 8 instead of | |
1597 | 32 & 64. | |
1598 | (pending_tick): Move incrementing of index to FOR statement. | |
1599 | (pending_tick): Only update PENDING_OUT after a write has occured. | |
1600 | ||
1601 | * configure.in: Add explicit mips-lsi-* target. Use gencode to | |
1602 | build simulator. | |
1603 | * configure: Re-generate. | |
1604 | ||
1605 | * interp.c (sim_engine_run OLD): Delete explicit call to | |
1606 | PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK. | |
1607 | ||
1608 | Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com> | |
1609 | ||
1610 | * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy | |
1611 | interrupt level number to match changed SignalExceptionInterrupt | |
1612 | macro. | |
1613 | ||
1614 | Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com> | |
1615 | ||
1616 | * interp.c: #include "itable.h" if WITH_IGEN. | |
1617 | (get_insn_name): New function. | |
1618 | (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS. | |
1619 | * sim-main.h (MAX_INSNS,INSN_NAME): Delete. | |
1620 | ||
1621 | Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com> | |
1622 | ||
1623 | * configure: Rebuilt to inhale new common/aclocal.m4. | |
1624 | ||
1625 | Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com> | |
1626 | ||
1627 | * dv-tx3904sio.c: Include sim-assert.h. | |
1628 | ||
1629 | Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com> | |
1630 | ||
1631 | * dv-tx3904sio.c: New file: tx3904 serial I/O module. | |
1632 | * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target. | |
1633 | Reorganize target-specific sim-hardware checks. | |
1634 | * configure: rebuilt. | |
1635 | * interp.c (sim_open): For tx39 target boards, set | |
1636 | OPERATING_ENVIRONMENT, add tx3904sio devices. | |
1637 | * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading | |
1638 | ROM executables. Install dv-sockser into sim-modules list. | |
1639 | ||
1640 | * dv-tx3904irc.c: Compiler warning clean-up. | |
1641 | * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly | |
1642 | frequent hw-trace messages. | |
1643 | ||
1644 | Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
1645 | ||
1646 | * vr.igen (MulAcc): Identify as a vr4100 specific function. | |
1647 | ||
1648 | Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
1649 | ||
1650 | * Makefile.in (IGEN_INCLUDE): Add vr.igen. | |
1651 | ||
1652 | * vr.igen: New file. | |
1653 | (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c. | |
1654 | * mips.igen: Define vr4100 model. Include vr.igen. | |
1655 | Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com> | |
1656 | ||
1657 | * mips.igen (check_mf_hilo): Correct check. | |
1658 | ||
1659 | Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
1660 | ||
1661 | * sim-main.h (interrupt_event): Add prototype. | |
1662 | ||
1663 | * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused | |
1664 | register_ptr, register_value. | |
1665 | (deliver_tx3904tmr_tick): Fix types passed to printf fmt. | |
1666 | ||
1667 | * sim-main.h (tracefh): Make extern. | |
1668 | ||
1669 | Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com> | |
1670 | ||
1671 | * dv-tx3904tmr.c: Deschedule timer event after dispatching. | |
1672 | Reduce unnecessarily high timer event frequency. | |
1673 | * dv-tx3904cpu.c: Ditto for interrupt event. | |
1674 | ||
1675 | Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com> | |
1676 | ||
1677 | * interp.c (decode_coproc): For TX39, add stub COP0 register #7, | |
1678 | to allay warnings. | |
1679 | (interrupt_event): Made non-static. | |
1680 | ||
1681 | * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental | |
1682 | interchange of configuration values for external vs. internal | |
1683 | clock dividers. | |
1684 | ||
1685 | Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com> | |
1686 | ||
1687 | * mips.igen (BREAK): Moved code to here for | |
1688 | simulator-reserved break instructions. | |
1689 | * gencode.c (build_instruction): Ditto. | |
1690 | * interp.c (signal_exception): Code moved from here. Non- | |
1691 | reserved instructions now use exception vector, rather | |
1692 | than halting sim. | |
1693 | * sim-main.h: Moved magic constants to here. | |
1694 | ||
1695 | Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com> | |
1696 | ||
1697 | * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE | |
1698 | register upon non-zero interrupt event level, clear upon zero | |
1699 | event value. | |
1700 | * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal | |
1701 | by passing zero event value. | |
1702 | (*_io_{read,write}_buffer): Endianness fixes. | |
1703 | * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes. | |
1704 | (deliver_*_tick): Reduce sim event interval to 75% of count interval. | |
1705 | ||
1706 | * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based | |
1707 | serial I/O and timer module at base address 0xFFFF0000. | |
1708 | ||
1709 | Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com> | |
1710 | ||
1711 | * mips.igen (SWC1) : Correct the handling of ReverseEndian | |
1712 | and BigEndianCPU. | |
1713 | ||
1714 | Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com> | |
1715 | ||
1716 | * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips | |
1717 | parts. | |
1718 | * configure: Update. | |
1719 | ||
1720 | Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com> | |
1721 | ||
1722 | * dv-tx3904tmr.c: New file - implements tx3904 timer. | |
1723 | * dv-tx3904{irc,cpu}.c: Mild reformatting. | |
1724 | * configure.in: Include tx3904tmr in hw_device list. | |
1725 | * configure: Rebuilt. | |
1726 | * interp.c (sim_open): Instantiate three timer instances. | |
1727 | Fix address typo of tx3904irc instance. | |
1728 | ||
1729 | Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com> | |
1730 | ||
1731 | * interp.c (signal_exception): SystemCall exception now uses | |
1732 | the exception vector. | |
1733 | ||
1734 | Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com> | |
1735 | ||
1736 | * interp.c (decode_coproc): For TX39, add stub COP0 register #3, | |
1737 | to allay warnings. | |
1738 | ||
1739 | Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
1740 | ||
1741 | * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39. | |
1742 | ||
1743 | Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
1744 | ||
1745 | * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method. | |
1746 | ||
1747 | * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and | |
1748 | sim-main.h. Declare a struct hw_descriptor instead of struct | |
1749 | hw_device_descriptor. | |
1750 | ||
1751 | Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
1752 | ||
1753 | * mips.igen (do_store_left, do_load_left): Compute nr of left and | |
1754 | right bits and then re-align left hand bytes to correct byte | |
1755 | lanes. Fix incorrect computation in do_store_left when loading | |
1756 | bytes from second word. | |
1757 | ||
1758 | Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
1759 | ||
1760 | * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904. | |
1761 | * interp.c (sim_open): Only create a device tree when HW is | |
1762 | enabled. | |
1763 | ||
1764 | * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC. | |
1765 | * interp.c (signal_exception): Ditto. | |
1766 | ||
1767 | Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com> | |
1768 | ||
1769 | * gencode.c: Mark BEGEZALL as LIKELY. | |
1770 | ||
1771 | Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
1772 | ||
1773 | * sim-main.h (ALU32_END): Sign extend 32 bit results. | |
1774 | * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace. | |
1775 | ||
1776 | Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com> | |
1777 | ||
1778 | * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware | |
1779 | modules. Recognize TX39 target with "mips*tx39" pattern. | |
1780 | * configure: Rebuilt. | |
1781 | * sim-main.h (*): Added many macros defining bits in | |
1782 | TX39 control registers. | |
1783 | (SignalInterrupt): Send actual PC instead of NULL. | |
1784 | (SignalNMIReset): New exception type. | |
1785 | * interp.c (board): New variable for future use to identify | |
1786 | a particular board being simulated. | |
1787 | (mips_option_handler,mips_options): Added "--board" option. | |
1788 | (interrupt_event): Send actual PC. | |
1789 | (sim_open): Make memory layout conditional on board setting. | |
1790 | (signal_exception): Initial implementation of hardware interrupt | |
1791 | handling. Accept another break instruction variant for simulator | |
1792 | exit. | |
1793 | (decode_coproc): Implement RFE instruction for TX39. | |
1794 | (mips.igen): Decode RFE instruction as such. | |
1795 | * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904. | |
1796 | * interp.c: Define "jmr3904" and "jmr3904debug" board types and | |
1797 | bbegin to implement memory map. | |
1798 | * dv-tx3904cpu.c: New file. | |
1799 | * dv-tx3904irc.c: New file. | |
1800 | ||
1801 | Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com> | |
1802 | ||
1803 | * mips.igen (check_mt_hilo): Create a separate r3900 version. | |
1804 | ||
1805 | Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com> | |
1806 | ||
1807 | * tx.igen (madd,maddu): Replace calls to check_op_hilo | |
1808 | with calls to check_div_hilo. | |
1809 | ||
1810 | Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com> | |
1811 | ||
1812 | * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo): | |
1813 | Replace check_op_hilo with check_mult_hilo and check_div_hilo. | |
1814 | Add special r3900 version of do_mult_hilo. | |
1815 | (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo | |
1816 | with calls to check_mult_hilo. | |
1817 | (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo | |
1818 | with calls to check_div_hilo. | |
1819 | ||
1820 | Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
1821 | ||
1822 | * configure.in (SUBTARGET_R3900): Define for mipstx39 target. | |
1823 | Document a replacement. | |
1824 | ||
1825 | Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com> | |
1826 | ||
1827 | * interp.c (sim_monitor): Make mon_printf work. | |
1828 | ||
1829 | Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com> | |
1830 | ||
1831 | * sim-main.h (INSN_NAME): New arg `cpu'. | |
1832 | ||
1833 | Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com> | |
1834 | ||
1835 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
1836 | ||
1837 | Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche> | |
1838 | ||
1839 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
1840 | * config.in: Ditto. | |
1841 | ||
1842 | Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com> | |
1843 | ||
1844 | * acconfig.h: New file. | |
1845 | * configure.in: Reverted change of Apr 24; use sinclude again. | |
1846 | ||
1847 | Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche> | |
1848 | ||
1849 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
1850 | * config.in: Ditto. | |
1851 | ||
1852 | Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com> | |
1853 | ||
1854 | * configure.in: Don't call sinclude. | |
1855 | ||
1856 | Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com> | |
1857 | ||
1858 | * mips.igen (do_store_left): Pass 0 not NULL to store_memory. | |
1859 | ||
1860 | Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
1861 | ||
1862 | * mips.igen (ERET): Implement. | |
1863 | ||
1864 | * interp.c (decode_coproc): Return sign-extended EPC. | |
1865 | ||
1866 | * mips.igen (ANDI, LUI, MFC0): Add tracing code. | |
1867 | ||
1868 | * interp.c (signal_exception): Do not ignore Trap. | |
1869 | (signal_exception): On TRAP, restart at exception address. | |
1870 | (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define. | |
1871 | (signal_exception): Update. | |
1872 | (sim_open): Patch V_COMMON interrupt vector with an abort sequence | |
1873 | so that TRAP instructions are caught. | |
1874 | ||
1875 | Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
1876 | ||
1877 | * sim-main.h (struct hilo_access, struct hilo_history): Define, | |
1878 | contains HI/LO access history. | |
1879 | (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access. | |
1880 | (HIACCESS, LOACCESS): Delete, replace with | |
1881 | (HIHISTORY, LOHISTORY): New macros. | |
1882 | (CHECKHILO): Delete all, moved to mips.igen | |
1883 | ||
1884 | * gencode.c (build_instruction): Do not generate checks for | |
1885 | correct HI/LO register usage. | |
1886 | ||
1887 | * interp.c (old_engine_run): Delete checks for correct HI/LO | |
1888 | register usage. | |
1889 | ||
1890 | * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo, | |
1891 | check_mf_cycles): New functions. | |
1892 | (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div, | |
1893 | do_divu, domultx, do_mult, do_multu): Use. | |
1894 | ||
1895 | * tx.igen ("madd", "maddu"): Use. | |
1896 | ||
1897 | Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
1898 | ||
1899 | * mips.igen (DSRAV): Use function do_dsrav. | |
1900 | (SRAV): Use new function do_srav. | |
1901 | ||
1902 | * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX]. | |
1903 | (B): Sign extend 11 bit immediate. | |
1904 | (EXT-B*): Shift 16 bit immediate left by 1. | |
1905 | (ADDIU*): Don't sign extend immediate value. | |
1906 | ||
1907 | Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
1908 | ||
1909 | * m16run.c (sim_engine_run): Restore CIA after handling an event. | |
1910 | ||
1911 | * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use | |
1912 | functions. | |
1913 | ||
1914 | * mips.igen (delayslot32, nullify_next_insn): New functions. | |
1915 | (m16.igen): Always include. | |
1916 | (do_*): Add more tracing. | |
1917 | ||
1918 | * m16.igen (delayslot16): Add NIA argument, could be called by a | |
1919 | 32 bit MIPS16 instruction. | |
1920 | ||
1921 | * interp.c (ifetch16): Move function from here. | |
1922 | * sim-main.c (ifetch16): To here. | |
1923 | ||
1924 | * sim-main.c (ifetch16, ifetch32): Update to match current | |
1925 | implementations of LH, LW. | |
1926 | (signal_exception): Don't print out incorrect hex value of illegal | |
1927 | instruction. | |
1928 | ||
1929 | Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
1930 | ||
1931 | * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an | |
1932 | instruction. | |
1933 | ||
1934 | * m16.igen: Implement MIPS16 instructions. | |
1935 | ||
1936 | * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu, | |
1937 | do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav, | |
1938 | do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or, | |
1939 | do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra, | |
1940 | do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move | |
1941 | bodies of corresponding code from 32 bit insn to these. Also used | |
1942 | by MIPS16 versions of functions. | |
1943 | ||
1944 | * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define. | |
1945 | (IMEM16): Drop NR argument from macro. | |
1946 | ||
1947 | Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
1948 | ||
1949 | * Makefile.in (SIM_OBJS): Add sim-main.o. | |
1950 | ||
1951 | * sim-main.h (address_translation, load_memory, store_memory, | |
1952 | cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark | |
1953 | as INLINE_SIM_MAIN. | |
1954 | (pr_addr, pr_uword64): Declare. | |
1955 | (sim-main.c): Include when H_REVEALS_MODULE_P. | |
1956 | ||
1957 | * interp.c (address_translation, load_memory, store_memory, | |
1958 | cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move | |
1959 | from here. | |
1960 | * sim-main.c: To here. Fix compilation problems. | |
1961 | ||
1962 | * configure.in: Enable inlining. | |
1963 | * configure: Re-config. | |
1964 | ||
1965 | Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
1966 | ||
1967 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
1968 | ||
1969 | Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
1970 | ||
1971 | * mips.igen: Include tx.igen. | |
1972 | * Makefile.in (IGEN_INCLUDE): Add tx.igen. | |
1973 | * tx.igen: New file, contains MADD and MADDU. | |
1974 | ||
1975 | * interp.c (load_memory): When shifting bytes, use LOADDRMASK not | |
1976 | the hardwired constant `7'. | |
1977 | (store_memory): Ditto. | |
1978 | (LOADDRMASK): Move definition to sim-main.h. | |
1979 | ||
1980 | mips.igen (MTC0): Enable for r3900. | |
1981 | (ADDU): Add trace. | |
1982 | ||
1983 | mips.igen (do_load_byte): Delete. | |
1984 | (do_load, do_store, do_load_left, do_load_write, do_store_left, | |
1985 | do_store_right): New functions. | |
1986 | (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use. | |
1987 | ||
1988 | configure.in: Let the tx39 use igen again. | |
1989 | configure: Update. | |
1990 | ||
1991 | Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
1992 | ||
1993 | * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity, | |
1994 | not an address sized quantity. Return zero for cache sizes. | |
1995 | ||
1996 | Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
1997 | ||
1998 | * mips.igen (r3900): r3900 does not support 64 bit integer | |
1999 | operations. | |
2000 | ||
2001 | Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com> | |
2002 | ||
2003 | * configure.in (mipstx39*-*-*): Use gencode simulator rather | |
2004 | than igen one. | |
2005 | * configure : Rebuild. | |
2006 | ||
2007 | Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
2008 | ||
2009 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
2010 | ||
2011 | Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
2012 | ||
2013 | * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS. | |
2014 | ||
2015 | Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com> | |
2016 | ||
2017 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
2018 | * config.in: Regenerated to track ../common/aclocal.m4 changes. | |
2019 | ||
2020 | Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
2021 | ||
2022 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
2023 | ||
2024 | Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
2025 | ||
2026 | * interp.c (Max, Min): Comment out functions. Not yet used. | |
2027 | ||
2028 | Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
2029 | ||
2030 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
2031 | ||
2032 | Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com> | |
2033 | ||
2034 | * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added | |
2035 | configurable settings for stand-alone simulator. | |
2036 | ||
2037 | * configure.in: Added X11 search, just in case. | |
2038 | ||
2039 | * configure: Regenerated. | |
2040 | ||
2041 | Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
2042 | ||
2043 | * interp.c (sim_write, sim_read, load_memory, store_memory): | |
2044 | Replace sim_core_*_map with read_map, write_map, exec_map resp. | |
2045 | ||
2046 | Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
2047 | ||
2048 | * sim-main.h (GETFCC): Return an unsigned value. | |
2049 | ||
2050 | Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
2051 | ||
2052 | * mips.igen (DIV): Fix check for -1 / MIN_INT. | |
2053 | (DADD): Result destination is RD not RT. | |
2054 | ||
2055 | Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
2056 | ||
2057 | * sim-main.h (HIACCESS, LOACCESS): Always define. | |
2058 | ||
2059 | * mdmx.igen (Maxi, Mini): Rename Max, Min. | |
2060 | ||
2061 | * interp.c (sim_info): Delete. | |
2062 | ||
2063 | Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com> | |
2064 | ||
2065 | * interp.c (DECLARE_OPTION_HANDLER): Use it. | |
2066 | (mips_option_handler): New argument `cpu'. | |
2067 | (sim_open): Update call to sim_add_option_table. | |
2068 | ||
2069 | Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
2070 | ||
2071 | * mips.igen (CxC1): Add tracing. | |
2072 | ||
2073 | Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
2074 | ||
2075 | * sim-main.h (Max, Min): Declare. | |
2076 | ||
2077 | * interp.c (Max, Min): New functions. | |
2078 | ||
2079 | * mips.igen (BC1): Add tracing. | |
2080 | ||
2081 | Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com> | |
2082 | ||
2083 | * interp.c Added memory map for stack in vr4100 | |
2084 | ||
2085 | Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com> | |
2086 | ||
2087 | * interp.c (load_memory): Add missing "break"'s. | |
2088 | ||
2089 | Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
2090 | ||
2091 | * interp.c (sim_store_register, sim_fetch_register): Pass in | |
2092 | length parameter. Return -1. | |
2093 | ||
2094 | Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com> | |
2095 | ||
2096 | * interp.c: Added hardware init hook, fixed warnings. | |
2097 | ||
2098 | Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
2099 | ||
2100 | * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL. | |
2101 | ||
2102 | Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
2103 | ||
2104 | * interp.c (ifetch16): New function. | |
2105 | ||
2106 | * sim-main.h (IMEM32): Rename IMEM. | |
2107 | (IMEM16_IMMED): Define. | |
2108 | (IMEM16): Define. | |
2109 | (DELAY_SLOT): Update. | |
2110 | ||
2111 | * m16run.c (sim_engine_run): New file. | |
2112 | ||
2113 | * m16.igen: All instructions except LB. | |
2114 | (LB): Call do_load_byte. | |
2115 | * mips.igen (do_load_byte): New function. | |
2116 | (LB): Call do_load_byte. | |
2117 | ||
2118 | * mips.igen: Move spec for insn bit size and high bit from here. | |
2119 | * Makefile.in (tmp-igen, tmp-m16): To here. | |
2120 | ||
2121 | * m16.dc: New file, decode mips16 instructions. | |
2122 | ||
2123 | * Makefile.in (SIM_NO_ALL): Define. | |
2124 | (tmp-m16): Generate both 16 bit and 32 bit simulator engines. | |
2125 | ||
2126 | Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
2127 | ||
2128 | * configure.in (mips_fpu_bitsize): For tx39, restrict floating | |
2129 | point unit to 32 bit registers. | |
2130 | * configure: Re-generate. | |
2131 | ||
2132 | Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
2133 | ||
2134 | * configure.in (sim_use_gen): Make IGEN the default simulator | |
2135 | generator for generic 32 and 64 bit mips targets. | |
2136 | * configure: Re-generate. | |
2137 | ||
2138 | Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
2139 | ||
2140 | * sim-main.h (SizeFGR): Determine from floating-point and not gpr | |
2141 | bitsize. | |
2142 | ||
2143 | * interp.c (sim_fetch_register, sim_store_register): Read/write | |
2144 | FGR from correct location. | |
2145 | (sim_open): Set size of FGR's according to | |
2146 | WITH_TARGET_FLOATING_POINT_BITSIZE. | |
2147 | ||
2148 | * sim-main.h (FGR): Store floating point registers in a separate | |
2149 | array. | |
2150 | ||
2151 | Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
2152 | ||
2153 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
2154 | ||
2155 | Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
2156 | ||
2157 | * interp.c (ColdReset): Call PENDING_INVALIDATE. | |
2158 | ||
2159 | * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK. | |
2160 | ||
2161 | * interp.c (pending_tick): New function. Deliver pending writes. | |
2162 | ||
2163 | * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED, | |
2164 | PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that | |
2165 | it can handle mixed sized quantites and single bits. | |
2166 | ||
2167 | Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
2168 | ||
2169 | * interp.c (oengine.h): Do not include when building with IGEN. | |
2170 | (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE. | |
2171 | (sim_info): Ditto for PROCESSOR_64BIT. | |
2172 | (sim_monitor): Replace ut_reg with unsigned_word. | |
2173 | (*): Ditto for t_reg. | |
2174 | (LOADDRMASK): Define. | |
2175 | (sim_open): Remove defunct check that host FP is IEEE compliant, | |
2176 | using software to emulate floating point. | |
2177 | (value_fpr, ...): Always compile, was conditional on HASFPU. | |
2178 | ||
2179 | Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
2180 | ||
2181 | * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in | |
2182 | size. | |
2183 | ||
2184 | * interp.c (SD, CPU): Define. | |
2185 | (mips_option_handler): Set flags in each CPU. | |
2186 | (interrupt_event): Assume CPU 0 is the one being iterrupted. | |
2187 | (sim_close): Do not clear STATE, deleted anyway. | |
2188 | (sim_write, sim_read): Assume CPU zero's vm should be used for | |
2189 | data transfers. | |
2190 | (sim_create_inferior): Set the PC for all processors. | |
2191 | (sim_monitor, store_word, load_word, mips16_entry): Add cpu | |
2192 | argument. | |
2193 | (mips16_entry): Pass correct nr of args to store_word, load_word. | |
2194 | (ColdReset): Cold reset all cpu's. | |
2195 | (signal_exception): Pass cpu to sim_monitor & mips16_entry. | |
2196 | (sim_monitor, load_memory, store_memory, signal_exception): Use | |
2197 | `CPU' instead of STATE_CPU. | |
2198 | ||
2199 | ||
2200 | * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with | |
2201 | SD or CPU_. | |
2202 | ||
2203 | * sim-main.h (signal_exception): Add sim_cpu arg. | |
2204 | (SignalException*): Pass both SD and CPU to signal_exception. | |
2205 | * interp.c (signal_exception): Update. | |
2206 | ||
2207 | * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c: | |
2208 | Ditto | |
2209 | (sync_operation, prefetch, cache_op, store_memory, load_memory, | |
2210 | address_translation): Ditto | |
2211 | (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto. | |
2212 | ||
2213 | Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
2214 | ||
2215 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
2216 | ||
2217 | Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
2218 | ||
2219 | * interp.c (sim_engine_run): Add `nr_cpus' argument. | |
2220 | ||
2221 | * mips.igen (model): Map processor names onto BFD name. | |
2222 | ||
2223 | * sim-main.h (CPU_CIA): Delete. | |
2224 | (SET_CIA, GET_CIA): Define | |
2225 | ||
2226 | Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
2227 | ||
2228 | * sim-main.h (GPR_SET): Define, used by igen when zeroing a | |
2229 | regiser. | |
2230 | ||
2231 | * configure.in (default_endian): Configure a big-endian simulator | |
2232 | by default. | |
2233 | * configure: Re-generate. | |
2234 | ||
2235 | Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba> | |
2236 | ||
2237 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
2238 | ||
2239 | Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com> | |
2240 | ||
2241 | * interp.c (sim_monitor): Handle Densan monitor outbyte | |
2242 | and inbyte functions. | |
2243 | ||
2244 | 1997-12-29 Felix Lee <flee@cygnus.com> | |
2245 | ||
2246 | * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c). | |
2247 | ||
2248 | Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com) | |
2249 | ||
2250 | * Makefile.in (tmp-igen): Arrange for $zero to always be | |
2251 | reset to zero after every instruction. | |
2252 | ||
2253 | Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2254 | ||
2255 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
2256 | * config.in: Ditto. | |
2257 | ||
2258 | Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com) | |
2259 | ||
2260 | * mips.igen (MSUB): Fix to work like MADD. | |
2261 | * gencode.c (MSUB): Similarly. | |
2262 | ||
2263 | Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com> | |
2264 | ||
2265 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
2266 | ||
2267 | Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2268 | ||
2269 | * mips.igen (LWC1): Correct assembler - lwc1 not swc1. | |
2270 | ||
2271 | Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2272 | ||
2273 | * sim-main.h (sim-fpu.h): Include. | |
2274 | ||
2275 | * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub, | |
2276 | Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite | |
2277 | using host independant sim_fpu module. | |
2278 | ||
2279 | Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2280 | ||
2281 | * interp.c (signal_exception): Report internal errors with SIGABRT | |
2282 | not SIGQUIT. | |
2283 | ||
2284 | * sim-main.h (C0_CONFIG): New register. | |
2285 | (signal.h): No longer include. | |
2286 | ||
2287 | * interp.c (decode_coproc): Allow access C0_CONFIG to register. | |
2288 | ||
2289 | Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com> | |
2290 | ||
2291 | * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS). | |
2292 | ||
2293 | Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2294 | ||
2295 | * mips.igen: Tag vr5000 instructions. | |
2296 | (ANDI): Was missing mipsIV model, fix assembler syntax. | |
2297 | (do_c_cond_fmt): New function. | |
2298 | (C.cond.fmt): Handle mips I-III which do not support CC field | |
2299 | separatly. | |
2300 | (bc1): Handle mips IV which do not have a delaed FCC separatly. | |
2301 | (SDR): Mask paddr when BigEndianMem, not the converse as specified | |
2302 | in IV3.2 spec. | |
2303 | (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle | |
2304 | vr5000 which saves LO in a GPR separatly. | |
2305 | ||
2306 | * configure.in (enable-sim-igen): For vr5000, select vr5000 | |
2307 | specific instructions. | |
2308 | * configure: Re-generate. | |
2309 | ||
2310 | Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2311 | ||
2312 | * Makefile.in (SIM_OBJS): Add sim-fpu module. | |
2313 | ||
2314 | * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and | |
2315 | fmt_uninterpreted_64 bit cases to switch. Convert to | |
2316 | fmt_formatted, | |
2317 | ||
2318 | * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define, | |
2319 | ||
2320 | * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse | |
2321 | as specified in IV3.2 spec. | |
2322 | (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR. | |
2323 | ||
2324 | Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2325 | ||
2326 | * mips.igen: Delay slot branches add OFFSET to NIA not CIA. | |
2327 | (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement. | |
2328 | (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non | |
2329 | PENDING_FILL versions of instructions. Simplify. | |
2330 | (X): New function. | |
2331 | (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of | |
2332 | instructions. | |
2333 | (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to | |
2334 | a signed value. | |
2335 | (MTHI, MFHI): Disable code checking HI-LO. | |
2336 | ||
2337 | * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh | |
2338 | global. | |
2339 | (NULLIFY_NEXT_INSTRUCTION): Call dotrace. | |
2340 | ||
2341 | Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2342 | ||
2343 | * gencode.c (build_mips16_operands): Replace IPC with cia. | |
2344 | ||
2345 | * interp.c (sim_monitor, signal_exception, cache_op, store_fpr, | |
2346 | value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace | |
2347 | IPC to `cia'. | |
2348 | (UndefinedResult): Replace function with macro/function | |
2349 | combination. | |
2350 | (sim_engine_run): Don't save PC in IPC. | |
2351 | ||
2352 | * sim-main.h (IPC): Delete. | |
2353 | ||
2354 | ||
2355 | * interp.c (signal_exception, store_word, load_word, | |
2356 | address_translation, load_memory, store_memory, cache_op, | |
2357 | prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert, | |
2358 | cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add | |
2359 | current instruction address - cia - argument. | |
2360 | (sim_read, sim_write): Call address_translation directly. | |
2361 | (sim_engine_run): Rename variable vaddr to cia. | |
2362 | (signal_exception): Pass cia to sim_monitor | |
2363 | ||
2364 | * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp, | |
2365 | Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW, | |
2366 | COP_LD, COP_SW, COP_SD, DecodeCoproc): Update. | |
2367 | ||
2368 | * sim-main.h (SignalExceptionSimulatorFault): Delete definition. | |
2369 | * interp.c (sim_open): Replace SignalExceptionSimulatorFault with | |
2370 | SIM_ASSERT. | |
2371 | ||
2372 | * interp.c (signal_exception): Pass restart address to | |
2373 | sim_engine_restart. | |
2374 | ||
2375 | * Makefile.in (semantics.o, engine.o, support.o, itable.o, | |
2376 | idecode.o): Add dependency. | |
2377 | ||
2378 | * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK): | |
2379 | Delete definitions | |
2380 | (DELAY_SLOT): Update NIA not PC with branch address. | |
2381 | (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next. | |
2382 | ||
2383 | * mips.igen: Use CIA not PC in branch calculations. | |
2384 | (illegal): Call SignalException. | |
2385 | (BEQ, ADDIU): Fix assembler. | |
2386 | ||
2387 | Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2388 | ||
2389 | * m16.igen (JALX): Was missing. | |
2390 | ||
2391 | * configure.in (enable-sim-igen): New configuration option. | |
2392 | * configure: Re-generate. | |
2393 | ||
2394 | * sim-main.h (MAX_INSNS, INSN_NAME): Define. | |
2395 | ||
2396 | * interp.c (load_memory, store_memory): Delete parameter RAW. | |
2397 | (sim_read, sim_write): Use sim_core_{read,write}_buffer directly | |
2398 | bypassing {load,store}_memory. | |
2399 | ||
2400 | * sim-main.h (ByteSwapMem): Delete definition. | |
2401 | ||
2402 | * Makefile.in (SIM_OBJS): Add sim-memopt module. | |
2403 | ||
2404 | * interp.c (sim_do_command, sim_commands): Delete mips specific | |
2405 | commands. Handled by module sim-options. | |
2406 | ||
2407 | * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module. | |
2408 | (WITH_MODULO_MEMORY): Define. | |
2409 | ||
2410 | * interp.c (sim_info): Delete code printing memory size. | |
2411 | ||
2412 | * interp.c (mips_size): Nee sim_size, delete function. | |
2413 | (power2): Delete. | |
2414 | (monitor, monitor_base, monitor_size): Delete global variables. | |
2415 | (sim_open, sim_close): Delete code creating monitor and other | |
2416 | memory regions. Use sim-memopts module, via sim_do_commandf, to | |
2417 | manage memory regions. | |
2418 | (load_memory, store_memory): Use sim-core for memory model. | |
2419 | ||
2420 | * interp.c (address_translation): Delete all memory map code | |
2421 | except line forcing 32 bit addresses. | |
2422 | ||
2423 | Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2424 | ||
2425 | * sim-main.h (WITH_TRACE): Delete definition. Enables common | |
2426 | trace options. | |
2427 | ||
2428 | * interp.c (logfh, logfile): Delete globals. | |
2429 | (sim_open, sim_close): Delete code opening & closing log file. | |
2430 | (mips_option_handler): Delete -l and -n options. | |
2431 | (OPTION mips_options): Ditto. | |
2432 | ||
2433 | * interp.c (OPTION mips_options): Rename option trace to dinero. | |
2434 | (mips_option_handler): Update. | |
2435 | ||
2436 | Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2437 | ||
2438 | * interp.c (fetch_str): New function. | |
2439 | (sim_monitor): Rewrite using sim_read & sim_write. | |
2440 | (sim_open): Check magic number. | |
2441 | (sim_open): Write monitor vectors into memory using sim_write. | |
2442 | (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define. | |
2443 | (sim_read, sim_write): Simplify - transfer data one byte at a | |
2444 | time. | |
2445 | (load_memory, store_memory): Clarify meaning of parameter RAW. | |
2446 | ||
2447 | * sim-main.h (isHOST): Defete definition. | |
2448 | (isTARGET): Mark as depreciated. | |
2449 | (address_translation): Delete parameter HOST. | |
2450 | ||
2451 | * interp.c (address_translation): Delete parameter HOST. | |
2452 | ||
2453 | Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2454 | ||
2455 | * mips.igen: | |
2456 | ||
2457 | * Makefile.in (IGEN_INCLUDE): Files included by mips.igen. | |
2458 | (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE. | |
2459 | ||
2460 | Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2461 | ||
2462 | * mips.igen: Add model filter field to records. | |
2463 | ||
2464 | Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2465 | ||
2466 | * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0. | |
2467 | ||
2468 | interp.c (sim_engine_run): Do not compile function sim_engine_run | |
2469 | when WITH_IGEN == 1. | |
2470 | ||
2471 | * configure.in (sim_igen_flags, sim_m16_flags): Set according to | |
2472 | target architecture. | |
2473 | ||
2474 | Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to | |
2475 | igen. Replace with configuration variables sim_igen_flags / | |
2476 | sim_m16_flags. | |
2477 | ||
2478 | * m16.igen: New file. Copy mips16 insns here. | |
2479 | * mips.igen: From here. | |
2480 | ||
2481 | Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2482 | ||
2483 | * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ | |
2484 | to top. | |
2485 | (tmp-igen, tmp-m16): Pass -I srcdir to igen. | |
2486 | ||
2487 | Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com> | |
2488 | ||
2489 | * gencode.c (build_instruction): Follow sim_write's lead in using | |
2490 | BigEndianMem instead of !ByteSwapMem. | |
2491 | ||
2492 | Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2493 | ||
2494 | * configure.in (sim_gen): Dependent on target, select type of | |
2495 | generator. Always select old style generator. | |
2496 | ||
2497 | configure: Re-generate. | |
2498 | ||
2499 | Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New | |
2500 | targets. | |
2501 | (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16, | |
2502 | SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN, | |
2503 | IGEN_TRACE, IGEN_INSN, IGEN_DC): Define | |
2504 | (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member | |
2505 | SIM_@sim_gen@_*, set by autoconf. | |
2506 | ||
2507 | Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2508 | ||
2509 | * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define. | |
2510 | ||
2511 | * interp.c (ColdReset): Remove #ifdef HASFPU, check | |
2512 | CURRENT_FLOATING_POINT instead. | |
2513 | ||
2514 | * interp.c (ifetch32): New function. Fetch 32 bit instruction. | |
2515 | (address_translation): Raise exception InstructionFetch when | |
2516 | translation fails and isINSTRUCTION. | |
2517 | ||
2518 | * interp.c (sim_open, sim_write, sim_monitor, store_word, | |
2519 | sim_engine_run): Change type of of vaddr and paddr to | |
2520 | address_word. | |
2521 | (address_translation, prefetch, load_memory, store_memory, | |
2522 | cache_op): Change type of vAddr and pAddr to address_word. | |
2523 | ||
2524 | * gencode.c (build_instruction): Change type of vaddr and paddr to | |
2525 | address_word. | |
2526 | ||
2527 | Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2528 | ||
2529 | * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT | |
2530 | macro to obtain result of ALU op. | |
2531 | ||
2532 | Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2533 | ||
2534 | * interp.c (sim_info): Call profile_print. | |
2535 | ||
2536 | Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2537 | ||
2538 | * Makefile.in (SIM_OBJS): Add sim-profile.o module. | |
2539 | ||
2540 | * sim-main.h (WITH_PROFILE): Do not define, defined in | |
2541 | common/sim-config.h. Use sim-profile module. | |
2542 | (simPROFILE): Delete defintion. | |
2543 | ||
2544 | * interp.c (PROFILE): Delete definition. | |
2545 | (mips_option_handler): Delete 'p', 'y' and 'x' profile options. | |
2546 | (sim_close): Delete code writing profile histogram. | |
2547 | (mips_set_profile, mips_set_profile_size, writeout16, writeout32): | |
2548 | Delete. | |
2549 | (sim_engine_run): Delete code profiling the PC. | |
2550 | ||
2551 | Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2552 | ||
2553 | * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word. | |
2554 | ||
2555 | * interp.c (sim_monitor): Make register pointers of type | |
2556 | unsigned_word*. | |
2557 | ||
2558 | * sim-main.h: Make registers of type unsigned_word not | |
2559 | signed_word. | |
2560 | ||
2561 | Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2562 | ||
2563 | * interp.c (sync_operation): Rename from SyncOperation, make | |
2564 | global, add SD argument. | |
2565 | (prefetch): Rename from Prefetch, make global, add SD argument. | |
2566 | (decode_coproc): Make global. | |
2567 | ||
2568 | * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define. | |
2569 | ||
2570 | * gencode.c (build_instruction): Generate DecodeCoproc not | |
2571 | decode_coproc calls. | |
2572 | ||
2573 | * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h | |
2574 | (SizeFGR): Move to sim-main.h | |
2575 | (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT, | |
2576 | simSIGINT, simJALDELAYSLOT): Move to sim-main.h | |
2577 | (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to | |
2578 | sim-main.h. | |
2579 | (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF, | |
2580 | FP_RM_TOMINF, GETRM): Move to sim-main.h. | |
2581 | (Uncached, CachedNoncoherent, CachedCoherent, Cached, | |
2582 | isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h. | |
2583 | (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian, | |
2584 | BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h | |
2585 | ||
2586 | * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise | |
2587 | exception. | |
2588 | (sim-alu.h): Include. | |
2589 | (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define. | |
2590 | (sim_cia): Typedef to instruction_address. | |
2591 | ||
2592 | Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2593 | ||
2594 | * Makefile.in (interp.o): Rename generated file engine.c to | |
2595 | oengine.c. | |
2596 | ||
2597 | * interp.c: Update. | |
2598 | ||
2599 | Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2600 | ||
2601 | * gencode.c (build_instruction): Use FPR_STATE not fpr_state. | |
2602 | ||
2603 | Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2604 | ||
2605 | * gencode.c (build_instruction): For "FPSQRT", output correct | |
2606 | number of arguments to Recip. | |
2607 | ||
2608 | Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2609 | ||
2610 | * Makefile.in (interp.o): Depends on sim-main.h | |
2611 | ||
2612 | * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers. | |
2613 | ||
2614 | * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state, | |
2615 | ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields. | |
2616 | (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*, | |
2617 | STATE, DSSTATE): Define | |
2618 | (GPR, FGRIDX, ..): Define. | |
2619 | ||
2620 | * interp.c (registers, register_widths, fpr_state, ipc, dspc, | |
2621 | pending_*, hiaccess, loaccess, state, dsstate): Delete globals. | |
2622 | (GPR, FGRIDX, ...): Delete macros. | |
2623 | ||
2624 | * interp.c: Update names to match defines from sim-main.h | |
2625 | ||
2626 | Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2627 | ||
2628 | * interp.c (sim_monitor): Add SD argument. | |
2629 | (sim_warning): Delete. Replace calls with calls to | |
2630 | sim_io_eprintf. | |
2631 | (sim_error): Delete. Replace calls with sim_io_error. | |
2632 | (open_trace, writeout32, writeout16, getnum): Add SD argument. | |
2633 | (mips_set_profile): Rename from sim_set_profile. Add SD argument. | |
2634 | (mips_set_profile_size): Rename from sim_set_profile_size. Add SD | |
2635 | argument. | |
2636 | (mips_size): Rename from sim_size. Add SD argument. | |
2637 | ||
2638 | * interp.c (simulator): Delete global variable. | |
2639 | (callback): Delete global variable. | |
2640 | (mips_option_handler, sim_open, sim_write, sim_read, | |
2641 | sim_store_register, sim_fetch_register, sim_info, sim_do_command, | |
2642 | sim_size,sim_monitor): Use sim_io_* not callback->*. | |
2643 | (sim_open): ZALLOC simulator struct. | |
2644 | (PROFILE): Do not define. | |
2645 | ||
2646 | Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2647 | ||
2648 | * interp.c (sim_open), support.h: Replace CHECKSIM macro found in | |
2649 | support.h with corresponding code. | |
2650 | ||
2651 | * sim-main.h (word64, uword64), support.h: Move definition to | |
2652 | sim-main.h. | |
2653 | (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto. | |
2654 | ||
2655 | * support.h: Delete | |
2656 | * Makefile.in: Update dependencies | |
2657 | * interp.c: Do not include. | |
2658 | ||
2659 | Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2660 | ||
2661 | * interp.c (address_translation, load_memory, store_memory, | |
2662 | cache_op): Rename to from AddressTranslation et.al., make global, | |
2663 | add SD argument | |
2664 | ||
2665 | * sim-main.h (AddressTranslation, LoadMemory, StoreMemory, | |
2666 | CacheOp): Define. | |
2667 | ||
2668 | * interp.c (SignalException): Rename to signal_exception, make | |
2669 | global. | |
2670 | ||
2671 | * interp.c (Interrupt, ...): Move definitions to sim-main.h. | |
2672 | ||
2673 | * sim-main.h (SignalException, SignalExceptionInterrupt, | |
2674 | SignalExceptionInstructionFetch, SignalExceptionAddressStore, | |
2675 | SignalExceptionAddressLoad, SignalExceptionSimulatorFault, | |
2676 | SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable): | |
2677 | Define. | |
2678 | ||
2679 | * interp.c, support.h: Use. | |
2680 | ||
2681 | Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2682 | ||
2683 | * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename | |
2684 | to value_fpr / store_fpr. Add SD argument. | |
2685 | (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub, | |
2686 | Multiply, Divide, Recip, SquareRoot, Convert): Make global. | |
2687 | ||
2688 | * sim-main.h (ValueFPR, StoreFPR): Define. | |
2689 | ||
2690 | Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2691 | ||
2692 | * interp.c (sim_engine_run): Check consistency between configure | |
2693 | WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN | |
2694 | and HASFPU. | |
2695 | ||
2696 | * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE. | |
2697 | (mips_fpu): Configure WITH_FLOATING_POINT. | |
2698 | (mips_endian): Configure WITH_TARGET_ENDIAN. | |
2699 | * configure: Update. | |
2700 | ||
2701 | Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2702 | ||
2703 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
2704 | ||
2705 | Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com> | |
2706 | ||
2707 | * configure: Regenerated. | |
2708 | ||
2709 | Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com> | |
2710 | ||
2711 | * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB. | |
2712 | ||
2713 | Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2714 | ||
2715 | * gencode.c (print_igen_insn_models): Assume certain architectures | |
2716 | include all mips* instructions. | |
2717 | (print_igen_insn_format): Use data_size==-1 as marker for MIPS16 | |
2718 | instruction. | |
2719 | ||
2720 | * Makefile.in (tmp.igen): Add target. Generate igen input from | |
2721 | gencode file. | |
2722 | ||
2723 | * gencode.c (FEATURE_IGEN): Define. | |
2724 | (main): Add --igen option. Generate output in igen format. | |
2725 | (process_instructions): Format output according to igen option. | |
2726 | (print_igen_insn_format): New function. | |
2727 | (print_igen_insn_models): New function. | |
2728 | (process_instructions): Only issue warnings and ignore | |
2729 | instructions when no FEATURE_IGEN. | |
2730 | ||
2731 | Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2732 | ||
2733 | * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some | |
2734 | MIPS targets. | |
2735 | ||
2736 | Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2737 | ||
2738 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
2739 | ||
2740 | Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2741 | ||
2742 | * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN, | |
2743 | SIM_RESERVED_BITS): Delete, moved to common. | |
2744 | (SIM_EXTRA_CFLAGS): Update. | |
2745 | ||
2746 | Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2747 | ||
2748 | * configure.in: Configure non-strict memory alignment. | |
2749 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
2750 | ||
2751 | Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2752 | ||
2753 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
2754 | ||
2755 | Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com> | |
2756 | ||
2757 | * gencode.c (SDBBP,DERET): Added (3900) insns. | |
2758 | (RFE): Turn on for 3900. | |
2759 | * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added. | |
2760 | (dsstate): Made global. | |
2761 | (SUBTARGET_R3900): Added. | |
2762 | (CANCELDELAYSLOT): New. | |
2763 | (SignalException): Ignore SystemCall rather than ignore and | |
2764 | terminate. Add DebugBreakPoint handling. | |
2765 | (decode_coproc): New insns RFE, DERET; and new registers Debug | |
2766 | and DEPC protected by SUBTARGET_R3900. | |
2767 | (sim_engine_run): Use CANCELDELAYSLOT rather than clearing | |
2768 | bits explicitly. | |
2769 | * Makefile.in,configure.in: Add mips subtarget option. | |
2770 | * configure: Update. | |
2771 | ||
2772 | Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com> | |
2773 | ||
2774 | * gencode.c: Add r3900 (tx39). | |
2775 | ||
2776 | ||
2777 | Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com> | |
2778 | ||
2779 | * gencode.c (build_instruction): Don't need to subtract 4 for | |
2780 | JALR, just 2. | |
2781 | ||
2782 | Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com> | |
2783 | ||
2784 | * interp.c: Correct some HASFPU problems. | |
2785 | ||
2786 | Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2787 | ||
2788 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
2789 | ||
2790 | Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2791 | ||
2792 | * interp.c (mips_options): Fix samples option short form, should | |
2793 | be `x'. | |
2794 | ||
2795 | Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2796 | ||
2797 | * interp.c (sim_info): Enable info code. Was just returning. | |
2798 | ||
2799 | Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2800 | ||
2801 | * interp.c (decode_coproc): Clarify warning about unsuported MTC0, | |
2802 | MFC0. | |
2803 | ||
2804 | Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2805 | ||
2806 | * gencode.c (build_instruction): Use SIGNED64 for 64 bit | |
2807 | constants. | |
2808 | (build_instruction): Ditto for LL. | |
2809 | ||
2810 | Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba> | |
2811 | ||
2812 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
2813 | ||
2814 | Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2815 | ||
2816 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
2817 | * config.in: Ditto. | |
2818 | ||
2819 | Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2820 | ||
2821 | * interp.c (sim_open): Add call to sim_analyze_program, update | |
2822 | call to sim_config. | |
2823 | ||
2824 | Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2825 | ||
2826 | * interp.c (sim_kill): Delete. | |
2827 | (sim_create_inferior): Add ABFD argument. Set PC from same. | |
2828 | (sim_load): Move code initializing trap handlers from here. | |
2829 | (sim_open): To here. | |
2830 | (sim_load): Delete, use sim-hload.c. | |
2831 | ||
2832 | * Makefile.in (SIM_OBJS): Add sim-hload.o module. | |
2833 | ||
2834 | Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2835 | ||
2836 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
2837 | * config.in: Ditto. | |
2838 | ||
2839 | Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2840 | ||
2841 | * interp.c (sim_open): Add ABFD argument. | |
2842 | (sim_load): Move call to sim_config from here. | |
2843 | (sim_open): To here. Check return status. | |
2844 | ||
2845 | Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com> | |
2846 | ||
2847 | * gencode.c (build_instruction): Two arg MADD should | |
2848 | not assign result to $0. | |
2849 | ||
2850 | Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com) | |
2851 | ||
2852 | * sim/mips/configure: Change default_sim_endian to 0 (bi-endian) | |
2853 | * sim/mips/configure.in: Regenerate. | |
2854 | ||
2855 | Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com> | |
2856 | ||
2857 | * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit | |
2858 | signed8, unsigned8 et.al. types. | |
2859 | ||
2860 | * interp.c (SUB_REG_FETCH): Handle both little and big endian | |
2861 | hosts when selecting subreg. | |
2862 | ||
2863 | Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com) | |
2864 | ||
2865 | * interp.c (sim_engine_run): Reset the ZERO register to zero | |
2866 | regardless of FEATURE_WARN_ZERO. | |
2867 | * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO. | |
2868 | ||
2869 | Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2870 | ||
2871 | * interp.c (decode_coproc): Implement MTC0 N, CAUSE. | |
2872 | (SignalException): For BreakPoints ignore any mode bits and just | |
2873 | save the PC. | |
2874 | (SignalException): Always set the CAUSE register. | |
2875 | ||
2876 | Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2877 | ||
2878 | * interp.c (SignalException): Clear the simDELAYSLOT flag when an | |
2879 | exception has been taken. | |
2880 | ||
2881 | * interp.c: Implement the ERET and mt/f sr instructions. | |
2882 | ||
2883 | Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2884 | ||
2885 | * interp.c (SignalException): Don't bother restarting an | |
2886 | interrupt. | |
2887 | ||
2888 | Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2889 | ||
2890 | * interp.c (SignalException): Really take an interrupt. | |
2891 | (interrupt_event): Only deliver interrupts when enabled. | |
2892 | ||
2893 | Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2894 | ||
2895 | * interp.c (sim_info): Only print info when verbose. | |
2896 | (sim_info) Use sim_io_printf for output. | |
2897 | ||
2898 | Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2899 | ||
2900 | * interp.c (CoProcPresent): Add UNUSED attribute - not used by all | |
2901 | mips architectures. | |
2902 | ||
2903 | Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2904 | ||
2905 | * interp.c (sim_do_command): Check for common commands if a | |
2906 | simulator specific command fails. | |
2907 | ||
2908 | Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com> | |
2909 | ||
2910 | * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP | |
2911 | and simBE when DEBUG is defined. | |
2912 | ||
2913 | Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2914 | ||
2915 | * interp.c (interrupt_event): New function. Pass exception event | |
2916 | onto exception handler. | |
2917 | ||
2918 | * configure.in: Check for stdlib.h. | |
2919 | * configure: Regenerate. | |
2920 | ||
2921 | * gencode.c (build_instruction): Add UNUSED attribute to tempS | |
2922 | variable declaration. | |
2923 | (build_instruction): Initialize memval1. | |
2924 | (build_instruction): Add UNUSED attribute to byte, bigend, | |
2925 | reverse. | |
2926 | (build_operands): Ditto. | |
2927 | ||
2928 | * interp.c: Fix GCC warnings. | |
2929 | (sim_get_quit_code): Delete. | |
2930 | ||
2931 | * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS. | |
2932 | * Makefile.in: Ditto. | |
2933 | * configure: Re-generate. | |
2934 | ||
2935 | * Makefile.in (SIM_OBJS): Add sim-watch.o module. | |
2936 | ||
2937 | Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2938 | ||
2939 | * interp.c (mips_option_handler): New function parse argumes using | |
2940 | sim-options. | |
2941 | (myname): Replace with STATE_MY_NAME. | |
2942 | (sim_open): Delete check for host endianness - performed by | |
2943 | sim_config. | |
2944 | (simHOSTBE, simBE): Delete, replaced by sim-endian flags. | |
2945 | (sim_open): Move much of the initialization from here. | |
2946 | (sim_load): To here. After the image has been loaded and | |
2947 | endianness set. | |
2948 | (sim_open): Move ColdReset from here. | |
2949 | (sim_create_inferior): To here. | |
2950 | (sim_open): Make FP check less dependant on host endianness. | |
2951 | ||
2952 | * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or | |
2953 | run. | |
2954 | * interp.c (sim_set_callbacks): Delete. | |
2955 | ||
2956 | * interp.c (membank, membank_base, membank_size): Replace with | |
2957 | STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE. | |
2958 | (sim_open): Remove call to callback->init. gdb/run do this. | |
2959 | ||
2960 | * interp.c: Update | |
2961 | ||
2962 | * sim-main.h (SIM_HAVE_FLATMEM): Define. | |
2963 | ||
2964 | * interp.c (big_endian_p): Delete, replaced by | |
2965 | current_target_byte_order. | |
2966 | ||
2967 | Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2968 | ||
2969 | * interp.c (host_read_long, host_read_word, host_swap_word, | |
2970 | host_swap_long): Delete. Using common sim-endian. | |
2971 | (sim_fetch_register, sim_store_register): Use H2T. | |
2972 | (pipeline_ticks): Delete. Handled by sim-events. | |
2973 | (sim_info): Update. | |
2974 | (sim_engine_run): Update. | |
2975 | ||
2976 | Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2977 | ||
2978 | * interp.c (sim_stop_reason): Move code determining simEXCEPTION | |
2979 | reason from here. | |
2980 | (SignalException): To here. Signal using sim_engine_halt. | |
2981 | (sim_stop_reason): Delete, moved to common. | |
2982 | ||
2983 | Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com> | |
2984 | ||
2985 | * interp.c (sim_open): Add callback argument. | |
2986 | (sim_set_callbacks): Delete SIM_DESC argument. | |
2987 | (sim_size): Ditto. | |
2988 | ||
2989 | Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2990 | ||
2991 | * Makefile.in (SIM_OBJS): Add common modules. | |
2992 | ||
2993 | * interp.c (sim_set_callbacks): Also set SD callback. | |
2994 | (set_endianness, xfer_*, swap_*): Delete. | |
2995 | (host_read_word, host_read_long, host_swap_word, host_swap_long): | |
2996 | Change to functions using sim-endian macros. | |
2997 | (control_c, sim_stop): Delete, use common version. | |
2998 | (simulate): Convert into. | |
2999 | (sim_engine_run): This function. | |
3000 | (sim_resume): Delete. | |
3001 | ||
3002 | * interp.c (simulation): New variable - the simulator object. | |
3003 | (sim_kind): Delete global - merged into simulation. | |
3004 | (sim_load): Cleanup. Move PC assignment from here. | |
3005 | (sim_create_inferior): To here. | |
3006 | ||
3007 | * sim-main.h: New file. | |
3008 | * interp.c (sim-main.h): Include. | |
3009 | ||
3010 | Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com> | |
3011 | ||
3012 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
3013 | ||
3014 | Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com> | |
3015 | ||
3016 | * tconfig.in (SIM_HAVE_BIENDIAN): Define. | |
3017 | ||
3018 | Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com> | |
3019 | ||
3020 | * gencode.c (build_instruction): DIV instructions: check | |
3021 | for division by zero and integer overflow before using | |
3022 | host's division operation. | |
3023 | ||
3024 | Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com> | |
3025 | ||
3026 | * Makefile.in (SIM_OBJS): Add sim-load.o. | |
3027 | * interp.c: #include bfd.h. | |
3028 | (target_byte_order): Delete. | |
3029 | (sim_kind, myname, big_endian_p): New static locals. | |
3030 | (sim_open): Set sim_kind, myname. Move call to set_endianness to | |
3031 | after argument parsing. Recognize -E arg, set endianness accordingly. | |
3032 | (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to | |
3033 | load file into simulator. Set PC from bfd. | |
3034 | (sim_create_inferior): Return SIM_RC. Delete arg start_address. | |
3035 | (set_endianness): Use big_endian_p instead of target_byte_order. | |
3036 | ||
3037 | Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
3038 | ||
3039 | * interp.c (sim_size): Delete prototype - conflicts with | |
3040 | definition in remote-sim.h. Correct definition. | |
3041 | ||
3042 | Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com> | |
3043 | ||
3044 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
3045 | * config.in: Ditto. | |
3046 | ||
3047 | Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com> | |
3048 | ||
3049 | * interp.c (sim_open): New arg `kind'. | |
3050 | ||
3051 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
3052 | ||
3053 | Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com> | |
3054 | ||
3055 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
3056 | ||
3057 | Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com> | |
3058 | ||
3059 | * interp.c (sim_open): Set optind to 0 before calling getopt. | |
3060 | ||
3061 | Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com> | |
3062 | ||
3063 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
3064 | ||
3065 | Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com> | |
3066 | ||
3067 | * interp.c : Replace uses of pr_addr with pr_uword64 | |
3068 | where the bit length is always 64 independent of SIM_ADDR. | |
3069 | (pr_uword64) : added. | |
3070 | ||
3071 | Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com> | |
3072 | ||
3073 | * configure: Re-generate. | |
3074 | ||
3075 | Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com> | |
3076 | ||
3077 | * configure: Regenerate to track ../common/aclocal.m4 changes. | |
3078 | ||
3079 | Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com> | |
3080 | ||
3081 | * interp.c (sim_open): New SIM_DESC result. Argument is now | |
3082 | in argv form. | |
3083 | (other sim_*): New SIM_DESC argument. | |
3084 | ||
3085 | Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com> | |
3086 | ||
3087 | * interp.c: Fix printing of addresses for non-64-bit targets. | |
3088 | (pr_addr): Add function to print address based on size. | |
3089 | ||
3090 | Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com> | |
3091 | ||
3092 | * interp.c (simopen): Add support for LSI MiniRISC PMON vectors. | |
3093 | ||
3094 | Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com> | |
3095 | ||
3096 | * gencode.c (build_mips16_operands): Correct computation of base | |
3097 | address for extended PC relative instruction. | |
3098 | ||
3099 | Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com> | |
3100 | ||
3101 | * interp.c (mips16_entry): Add support for floating point cases. | |
3102 | (SignalException): Pass floating point cases to mips16_entry. | |
3103 | (ValueFPR): Don't restrict fmt_single and fmt_word to even | |
3104 | registers. | |
3105 | (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single | |
3106 | or fmt_word. | |
3107 | (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR, | |
3108 | and then set the state to fmt_uninterpreted. | |
3109 | (COP_SW): Temporarily set the state to fmt_word while calling | |
3110 | ValueFPR. | |
3111 | ||
3112 | Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com> | |
3113 | ||
3114 | * gencode.c (build_instruction): The high order may be set in the | |
3115 | comparison flags at any ISA level, not just ISA 4. | |
3116 | ||
3117 | Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com> | |
3118 | ||
3119 | * Makefile.in (@COMMON_MAKEFILE_FRAG): Use | |
3120 | COMMON_{PRE,POST}_CONFIG_FRAG instead. | |
3121 | * configure.in: sinclude ../common/aclocal.m4. | |
3122 | * configure: Regenerated. | |
3123 | ||
3124 | Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com> | |
3125 | ||
3126 | * configure: Rebuild after change to aclocal.m4. | |
3127 | ||
3128 | Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com) | |
3129 | ||
3130 | * configure configure.in Makefile.in: Update to new configure | |
3131 | scheme which is more compatible with WinGDB builds. | |
3132 | * configure.in: Improve comment on how to run autoconf. | |
3133 | * configure: Re-run autoconf to get new ../common/aclocal.m4. | |
3134 | * Makefile.in: Use autoconf substitution to install common | |
3135 | makefile fragment. | |
3136 | ||
3137 | Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com> | |
3138 | ||
3139 | * gencode.c (build_instruction): Use BigEndianCPU instead of | |
3140 | ByteSwapMem. | |
3141 | ||
3142 | Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com> | |
3143 | ||
3144 | * interp.c (sim_monitor): Make output to stdout visible in | |
3145 | wingdb's I/O log window. | |
3146 | ||
3147 | Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com> | |
3148 | ||
3149 | * support.h: Undo previous change to SIGTRAP | |
3150 | and SIGQUIT values. | |
3151 | ||
3152 | Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com> | |
3153 | ||
3154 | * interp.c (store_word, load_word): New static functions. | |
3155 | (mips16_entry): New static function. | |
3156 | (SignalException): Look for mips16 entry and exit instructions. | |
3157 | (simulate): Use the correct index when setting fpr_state after | |
3158 | doing a pending move. | |
3159 | ||
3160 | Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com> | |
3161 | ||
3162 | * interp.c: Fix byte-swapping code throughout to work on | |
3163 | both little- and big-endian hosts. | |
3164 | ||
3165 | Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com> | |
3166 | ||
3167 | * support.h: Make definitions of SIGTRAP and SIGQUIT consistent | |
3168 | with gdb/config/i386/xm-windows.h. | |
3169 | ||
3170 | Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com> | |
3171 | ||
3172 | * gencode.c (build_instruction): Work around MSVC++ code gen bug | |
3173 | that messes up arithmetic shifts. | |
3174 | ||
3175 | Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com) | |
3176 | ||
3177 | * support.h: Use _WIN32 instead of __WIN32__. Also add defs for | |
3178 | SIGTRAP and SIGQUIT for _WIN32. | |
3179 | ||
3180 | Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com> | |
3181 | ||
3182 | * gencode.c (build_instruction) [MUL]: Cast operands to word64, to | |
3183 | force a 64 bit multiplication. | |
3184 | (build_instruction) [OR]: In mips16 mode, don't do anything if the | |
3185 | destination register is 0, since that is the default mips16 nop | |
3186 | instruction. | |
3187 | ||
3188 | Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com> | |
3189 | ||
3190 | * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI. | |
3191 | (build_endian_shift): Don't check proc64. | |
3192 | (build_instruction): Always set memval to uword64. Cast op2 to | |
3193 | uword64 when shifting it left in memory instructions. Always use | |
3194 | the same code for stores--don't special case proc64. | |
3195 | ||
3196 | * gencode.c (build_mips16_operands): Fix base PC value for PC | |
3197 | relative operands. | |
3198 | (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a | |
3199 | jal instruction. | |
3200 | * interp.c (simJALDELAYSLOT): Define. | |
3201 | (JALDELAYSLOT): Define. | |
3202 | (INDELAYSLOT, INJALDELAYSLOT): Define. | |
3203 | (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared. | |
3204 | ||
3205 | Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com) | |
3206 | ||
3207 | * interp.c (sim_open): add flush_cache as a PMON routine | |
3208 | (sim_monitor): handle flush_cache by ignoring it | |
3209 | ||
3210 | Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com> | |
3211 | ||
3212 | * gencode.c (build_instruction): Use !ByteSwapMem instead of | |
3213 | BigEndianMem. | |
3214 | * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete. | |
3215 | (BigEndianMem): Rename to ByteSwapMem and change sense. | |
3216 | (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change | |
3217 | BigEndianMem references to !ByteSwapMem. | |
3218 | (set_endianness): New function, with prototype. | |
3219 | (sim_open): Call set_endianness. | |
3220 | (sim_info): Use simBE instead of BigEndianMem. | |
3221 | (xfer_direct_word, xfer_direct_long, swap_direct_word, | |
3222 | swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word, | |
3223 | xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER | |
3224 | ifdefs, keeping the prototype declaration. | |
3225 | (swap_word): Rewrite correctly. | |
3226 | (ColdReset): Delete references to CONFIG. Delete endianness related | |
3227 | code; moved to set_endianness. | |
3228 | ||
3229 | Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com> | |
3230 | ||
3231 | * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits. | |
3232 | * interp.c (CHECKHILO): Define away. | |
3233 | (simSIGINT): New macro. | |
3234 | (membank_size): Increase from 1MB to 2MB. | |
3235 | (control_c): New function. | |
3236 | (sim_resume): Rename parameter signal to signal_number. Add local | |
3237 | variable prev. Call signal before and after simulate. | |
3238 | (sim_stop_reason): Add simSIGINT support. | |
3239 | (sim_warning, sim_error, dotrace, SignalException): Define as stdarg | |
3240 | functions always. | |
3241 | (sim_warning): Delete call to SignalException. Do call printf_filtered | |
3242 | if logfh is NULL. | |
3243 | (AddressTranslation): Add #ifdef DEBUG around debugging message and | |
3244 | a call to sim_warning. | |
3245 | ||
3246 | Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com> | |
3247 | ||
3248 | * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD | |
3249 | 16 bit instructions. | |
3250 | ||
3251 | Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com> | |
3252 | ||
3253 | Add support for mips16 (16 bit MIPS implementation): | |
3254 | * gencode.c (inst_type): Add mips16 instruction encoding types. | |
3255 | (GETDATASIZEINSN): Define. | |
3256 | (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add | |
3257 | jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and | |
3258 | mtlo. | |
3259 | (MIPS16_DECODE): New table, for mips16 instructions. | |
3260 | (bitmap_val): New static function. | |
3261 | (struct mips16_op): Define. | |
3262 | (mips16_op_table): New table, for mips16 operands. | |
3263 | (build_mips16_operands): New static function. | |
3264 | (process_instructions): If PC is odd, decode a mips16 | |
3265 | instruction. Break out instruction handling into new | |
3266 | build_instruction function. | |
3267 | (build_instruction): New static function, broken out of | |
3268 | process_instructions. Check modifiers rather than flags for SHIFT | |
3269 | bit count and m[ft]{hi,lo} direction. | |
3270 | (usage): Pass program name to fprintf. | |
3271 | (main): Remove unused variable this_option_optind. Change | |
3272 | ``*loptarg++'' to ``loptarg++''. | |
3273 | (my_strtoul): Parenthesize && within ||. | |
3274 | * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd. | |
3275 | (simulate): If PC is odd, fetch a 16 bit instruction, and | |
3276 | increment PC by 2 rather than 4. | |
3277 | * configure.in: Add case for mips16*-*-*. | |
3278 | * configure: Rebuild. | |
3279 | ||
3280 | Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com> | |
3281 | ||
3282 | * interp.c: Allow -t to enable tracing in standalone simulator. | |
3283 | Fix garbage output in trace file and error messages. | |
3284 | ||
3285 | Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com> | |
3286 | ||
3287 | * Makefile.in: Delete stuff moved to ../common/Make-common.in. | |
3288 | (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define. | |
3289 | * configure.in: Simplify using macros in ../common/aclocal.m4. | |
3290 | * configure: Regenerated. | |
3291 | * tconfig.in: New file. | |
3292 | ||
3293 | Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com> | |
3294 | ||
3295 | * interp.c: Fix bugs in 64-bit port. | |
3296 | Use ansi function declarations for msvc compiler. | |
3297 | Initialize and test file pointer in trace code. | |
3298 | Prevent duplicate definition of LAST_EMED_REGNUM. | |
3299 | ||
3300 | Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com> | |
3301 | ||
3302 | * interp.c (xfer_big_long): Prevent unwanted sign extension. | |
3303 | ||
3304 | Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk> | |
3305 | ||
3306 | * interp.c (SignalException): Check for explicit terminating | |
3307 | breakpoint value. | |
3308 | * gencode.c: Pass instruction value through SignalException() | |
3309 | calls for Trap, Breakpoint and Syscall. | |
3310 | ||
3311 | Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk> | |
3312 | ||
3313 | * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is | |
3314 | only used on those hosts that provide it. | |
3315 | * configure.in: Add sqrt() to list of functions to be checked for. | |
3316 | * config.in: Re-generated. | |
3317 | * configure: Re-generated. | |
3318 | ||
3319 | Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com> | |
3320 | ||
3321 | * gencode.c (process_instructions): Call build_endian_shift when | |
3322 | expanding STORE RIGHT, to fix swr. | |
3323 | * support.h (SIGNEXTEND): If the sign bit is not set, explicitly | |
3324 | clear the high bits. | |
3325 | * interp.c (Convert): Fix fmt_single to fmt_long to not truncate. | |
3326 | Fix float to int conversions to produce signed values. | |
3327 | ||
3328 | Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com> | |
3329 | ||
3330 | * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction. | |
3331 | (process_instructions): Correct handling of nor instruction. | |
3332 | Correct shift count for 32 bit shift instructions. Correct sign | |
3333 | extension for arithmetic shifts to not shift the number of bits in | |
3334 | the type. Fix 64 bit multiply high word calculation. Fix 32 bit | |
3335 | unsigned multiply. Fix ldxc1 and friends to use coprocessor 1. | |
3336 | Fix madd. | |
3337 | * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC. | |
3338 | It's OK to have a mult follow a mult. What's not OK is to have a | |
3339 | mult follow an mfhi. | |
3340 | (Convert): Comment out incorrect rounding code. | |
3341 | ||
3342 | Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk> | |
3343 | ||
3344 | * interp.c (sim_monitor): Improved monitor printf | |
3345 | simulation. Tidied up simulator warnings, and added "--log" option | |
3346 | for directing warning message output. | |
3347 | * gencode.c: Use sim_warning() rather than WARNING macro. | |
3348 | ||
3349 | Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com> | |
3350 | ||
3351 | * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and | |
3352 | getopt1.o, rather than on gencode.c. Link objects together. | |
3353 | Don't link against -liberty. | |
3354 | (gencode.o, getopt.o, getopt1.o): New targets. | |
3355 | * gencode.c: Include <ctype.h> and "ansidecl.h". | |
3356 | (AND): Undefine after including "ansidecl.h". | |
3357 | (ULONG_MAX): Define if not defined. | |
3358 | (OP_*): Don't define macros; now defined in opcode/mips.h. | |
3359 | (main): Call my_strtoul rather than strtoul. | |
3360 | (my_strtoul): New static function. | |
3361 | ||
3362 | Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com) | |
3363 | ||
3364 | * gencode.c (process_instructions): Generate word64 and uword64 | |
3365 | instead of `long long' and `unsigned long long' data types. | |
3366 | * interp.c: #include sysdep.h to get signals, and define default | |
3367 | for SIGBUS. | |
3368 | * (Convert): Work around for Visual-C++ compiler bug with type | |
3369 | conversion. | |
3370 | * support.h: Make things compile under Visual-C++ by using | |
3371 | __int64 instead of `long long'. Change many refs to long long | |
3372 | into word64/uword64 typedefs. | |
3373 | ||
3374 | Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp) | |
3375 | ||
3376 | * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir, | |
3377 | INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values. | |
3378 | (docdir): Removed. | |
3379 | * configure.in (AC_PREREQ): autoconf 2.5 or higher. | |
3380 | (AC_PROG_INSTALL): Added. | |
3381 | (AC_PROG_CC): Moved to before configure.host call. | |
3382 | * configure: Rebuilt. | |
3383 | ||
3384 | Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk> | |
3385 | ||
3386 | * configure.in: Define @SIMCONF@ depending on mips target. | |
3387 | * configure: Rebuild. | |
3388 | * Makefile.in (run): Add @SIMCONF@ to control simulator | |
3389 | construction. | |
3390 | * gencode.c: Change LOADDRMASK to 64bit memory model only. | |
3391 | * interp.c: Remove some debugging, provide more detailed error | |
3392 | messages, update memory accesses to use LOADDRMASK. | |
3393 | ||
3394 | Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com> | |
3395 | ||
3396 | * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS, | |
3397 | AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set | |
3398 | stamp-h. | |
3399 | * configure: Rebuild. | |
3400 | * config.in: New file, generated by autoheader. | |
3401 | * interp.c: Include "config.h". Include <stdlib.h>, <string.h>, | |
3402 | and <strings.h> if they exist. Replace #ifdef sun with #ifdef | |
3403 | HAVE_ANINT and HAVE_AINT, as appropriate. | |
3404 | * Makefile.in (run): Use @LIBS@ rather than -lm. | |
3405 | (interp.o): Depend upon config.h. | |
3406 | (Makefile): Just rebuild Makefile. | |
3407 | (clean): Remove stamp-h. | |
3408 | (mostlyclean): Make the same as clean, not as distclean. | |
3409 | (config.h, stamp-h): New targets. | |
3410 | ||
3411 | Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk> | |
3412 | ||
3413 | * interp.c (ColdReset): Fix boolean test. Make all simulator | |
3414 | globals static. | |
3415 | ||
3416 | Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk> | |
3417 | ||
3418 | * interp.c (xfer_direct_word, xfer_direct_long, | |
3419 | swap_direct_word, swap_direct_long, xfer_big_word, | |
3420 | xfer_big_long, xfer_little_word, xfer_little_long, | |
3421 | swap_word,swap_long): Added. | |
3422 | * interp.c (ColdReset): Provide function indirection to | |
3423 | host<->simulated_target transfer routines. | |
3424 | * interp.c (sim_store_register, sim_fetch_register): Updated to | |
3425 | make use of indirected transfer routines. | |
3426 | ||
3427 | Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk> | |
3428 | ||
3429 | * gencode.c (process_instructions): Ensure FP ABS instruction | |
3430 | recognised. | |
3431 | * interp.c (AbsoluteValue): Add routine. Also provide simple PMON | |
3432 | system call support. | |
3433 | ||
3434 | Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk> | |
3435 | ||
3436 | * interp.c (sim_do_command): Complain if callback structure not | |
3437 | initialised. | |
3438 | ||
3439 | Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk> | |
3440 | ||
3441 | * interp.c (Convert): Provide round-to-nearest and round-to-zero | |
3442 | support for Sun hosts. | |
3443 | * Makefile.in (gencode): Ensure the host compiler and libraries | |
3444 | used for cross-hosted build. | |
3445 | ||
3446 | Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk> | |
3447 | ||
3448 | * interp.c, gencode.c: Some more (TODO) tidying. | |
3449 | ||
3450 | Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk> | |
3451 | ||
3452 | * gencode.c, interp.c: Replaced explicit long long references with | |
3453 | WORD64HI, WORD64LO, SET64HI and SET64LO macro calls. | |
3454 | * support.h (SET64LO, SET64HI): Macros added. | |
3455 | ||
3456 | Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com> | |
3457 | ||
3458 | * configure: Regenerate with autoconf 2.7. | |
3459 | ||
3460 | Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com> | |
3461 | ||
3462 | * interp.c (LoadMemory): Enclose text following #endif in /* */. | |
3463 | * support.h: Remove superfluous "1" from #if. | |
3464 | * support.h (CHECKSIM): Remove stray 'a' at end of line. | |
3465 | ||
3466 | Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com> | |
3467 | ||
3468 | * interp.c (StoreFPR): Control UndefinedResult() call on | |
3469 | WARN_RESULT manifest. | |
3470 | ||
3471 | Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk> | |
3472 | ||
3473 | * gencode.c: Tidied instruction decoding, and added FP instruction | |
3474 | support. | |
3475 | ||
3476 | * interp.c: Added dineroIII, and BSD profiling support. Also | |
3477 | run-time FP handling. | |
3478 | ||
3479 | Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk> | |
3480 | ||
3481 | * Changelog, Makefile.in, README.Cygnus, configure, configure.in, | |
3482 | gencode.c, interp.c, support.h: created. |