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2002-07-29 Michael Snyder <msnyder@redhat.com>
[deliverable/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
2265c243
MS		 12002-07-29 Michael Snyder <msnyder@redhat.com>
2
3 * cp1.c (fp_recip2): Modify initialization expression so that
4 GCC will recognize it as constant.
5
a2f8b4f3
CD		 62002-06-18 Chris Demetriou <cgd@broadcom.com>
7
8 * mdmx.c (SD_): Delete.
9 (Unpredictable): Re-define, for now, to directly invoke
10 unpredictable_action().
11 (mdmx_acc_op): Fix error in .ob immediate handling.
12
b4b6c939
AC		 132002-06-18 Andrew Cagney <cagney@redhat.com>
14
15 * interp.c (sim_firmware_command): Initialize `address'.
16
c8cca39f
AC		 172002-06-16 Andrew Cagney <ac131313@redhat.com>
18
19 * configure: Regenerated to track ../common/aclocal.m4 changes.
20
e7e81181
CD		 212002-06-14 Chris Demetriou <cgd@broadcom.com>
22 Ed Satterthwaite <ehs@broadcom.com>
23
24 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
25 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
26 * mips.igen: Include mips3d.igen.
27 (mips3d): New model name for MIPS-3D ASE instructions.
28 (CVT.W.fmt): Don't use this instruction for word (source) format
29 instructions.
30 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
31 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
32 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
33 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
34 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
35 (RSquareRoot1, RSquareRoot2): New macros.
36 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
37 (fp_rsqrt2): New functions.
38 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
39 * configure: Regenerate.
40
3a2b820e 412002-06-13 Chris Demetriou <cgd@broadcom.com>
eab54952 42 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 43
44 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
45 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
46 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
47 (convert): Note that this function is not used for paired-single
48 format conversions.
49 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
50 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
51 (check_fmt_p): Enable paired-single support.
52 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
53 (PUU.PS): New instructions.
54 (CVT.S.fmt): Don't use this instruction for paired-single format
55 destinations.
56 * sim-main.h (FP_formats): New value 'fmt_ps.'
57 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
58 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
59
d18ea9c2
CD		 602002-06-12 Chris Demetriou <cgd@broadcom.com>
61
62 * mips.igen: Fix formatting of function calls in
63 many FP operations.
64
95fd5cee
CD		 652002-06-12 Chris Demetriou <cgd@broadcom.com>
66
67 * mips.igen (MOVN, MOVZ): Trace result.
68 (TNEI): Print "tnei" as the opcode name in traces.
69 (CEIL.W): Add disassembly string for traces.
70 (RSQRT.fmt): Make location of disassembly string consistent
71 with other instructions.
72
4f0d55ae
CD		 732002-06-12 Chris Demetriou <cgd@broadcom.com>
74
75 * mips.igen (X): Delete unused function.
76
3c25f8c7
AC		 772002-06-08 Andrew Cagney <cagney@redhat.com>
78
79 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
80
f3c08b7e
CD		 812002-06-07 Chris Demetriou <cgd@broadcom.com>
82 Ed Satterthwaite <ehs@broadcom.com>
83
84 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
85 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
86 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
87 (fp_nmsub): New prototypes.
88 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
89 (NegMultiplySub): New defines.
90 * mips.igen (RSQRT.fmt): Use RSquareRoot().
91 (MADD.D, MADD.S): Replace with...
92 (MADD.fmt): New instruction.
93 (MSUB.D, MSUB.S): Replace with...
94 (MSUB.fmt): New instruction.
95 (NMADD.D, NMADD.S): Replace with...
96 (NMADD.fmt): New instruction.
97 (NMSUB.D, MSUB.S): Replace with...
98 (NMSUB.fmt): New instruction.
99
52714ff9
CD		 1002002-06-07 Chris Demetriou <cgd@broadcom.com>
101 Ed Satterthwaite <ehs@broadcom.com>
102
103 * cp1.c: Fix more comment spelling and formatting.
104 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
105 (denorm_mode): New function.
106 (fpu_unary, fpu_binary): Round results after operation, collect
107 status from rounding operations, and update the FCSR.
108 (convert): Collect status from integer conversions and rounding
109 operations, and update the FCSR. Adjust NaN values that result
110 from conversions. Convert to use sim_io_eprintf rather than
111 fprintf, and remove some debugging code.
112 * cp1.h (fenr_FS): New define.
113
577d8c4b
CD		 1142002-06-07 Chris Demetriou <cgd@broadcom.com>
115
116 * cp1.c (convert): Remove unusable debugging code, and move MIPS
117 rounding mode to sim FP rounding mode flag conversion code into...
118 (rounding_mode): New function.
119
196496ed
CD		 1202002-06-07 Chris Demetriou <cgd@broadcom.com>
121
122 * cp1.c: Clean up formatting of a few comments.
123 (value_fpr): Reformat switch statement.
124
cfe9ea23
CD		 1252002-06-06 Chris Demetriou <cgd@broadcom.com>
126 Ed Satterthwaite <ehs@broadcom.com>
127
128 * cp1.h: New file.
129 * sim-main.h: Include cp1.h.
130 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
131 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
132 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
133 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
134 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
135 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
136 * cp1.c: Don't include sim-fpu.h; already included by
137 sim-main.h. Clean up formatting of some comments.
138 (NaN, Equal, Less): Remove.
139 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
140 (fp_cmp): New functions.
141 * mips.igen (do_c_cond_fmt): Remove.
142 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
143 Compare. Add result tracing.
144 (CxC1): Remove, replace with...
145 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
146 (DMxC1): Remove, replace with...
147 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
148 (MxC1): Remove, replace with...
149 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
150
ee7254b0
CD		 1512002-06-04 Chris Demetriou <cgd@broadcom.com>
152
153 * sim-main.h (FGRIDX): Remove, replace all uses with...
154 (FGR_BASE): New macro.
155 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
156 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
157 (NR_FGR, FGR): Likewise.
158 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
159 * mips.igen: Likewise.
160
d3eb724f
CD		 1612002-06-04 Chris Demetriou <cgd@broadcom.com>
162
163 * cp1.c: Add an FSF Copyright notice to this file.
164
ba46ddd0
CD		 1652002-06-04 Chris Demetriou <cgd@broadcom.com>
166 Ed Satterthwaite <ehs@broadcom.com>
167
168 * cp1.c (Infinity): Remove.
169 * sim-main.h (Infinity): Likewise.
170
171 * cp1.c (fp_unary, fp_binary): New functions.
172 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
173 (fp_sqrt): New functions, implemented in terms of the above.
174 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
175 (Recip, SquareRoot): Remove (replaced by functions above).
176 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
177 (fp_recip, fp_sqrt): New prototypes.
178 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
179 (Recip, SquareRoot): Replace prototypes with #defines which
180 invoke the functions above.
181
18d8a52d
CD		 1822002-06-03 Chris Demetriou <cgd@broadcom.com>
183
184 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
185 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
186 file, remove PARAMS from prototypes.
187 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
188 simulator state arguments.
189 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
190 pass simulator state arguments.
191 * cp1.c (SD): Redefine as CPU_STATE(cpu).
192 (store_fpr, convert): Remove 'sd' argument.
193 (value_fpr): Likewise. Convert to use 'SD' instead.
194
0f154cbd
CD		 1952002-06-03 Chris Demetriou <cgd@broadcom.com>
196
197 * cp1.c (Min, Max): Remove #if 0'd functions.
198 * sim-main.h (Min, Max): Remove.
199
e80fc152
CD		 2002002-06-03 Chris Demetriou <cgd@broadcom.com>
201
202 * cp1.c: fix formatting of switch case and default labels.
203 * interp.c: Likewise.
204 * sim-main.c: Likewise.
205
bad673a9
CD		 2062002-06-03 Chris Demetriou <cgd@broadcom.com>
207
208 * cp1.c: Clean up comments which describe FP formats.
209 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
210
7cbea089
CD		 2112002-06-03 Chris Demetriou <cgd@broadcom.com>
212 Ed Satterthwaite <ehs@broadcom.com>
213
214 * configure.in (mipsisa64sb1*-*-*): New target for supporting
215 Broadcom SiByte SB-1 processor configurations.
216 * configure: Regenerate.
217 * sb1.igen: New file.
218 * mips.igen: Include sb1.igen.
219 (sb1): New model.
220 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
221 * mdmx.igen: Add "sb1" model to all appropriate functions and
222 instructions.
223 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
224 (ob_func, ob_acc): Reference the above.
225 (qh_acc): Adjust to keep the same size as ob_acc.
226 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
227 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
228
909daa82
CD		 2292002-06-03 Chris Demetriou <cgd@broadcom.com>
230
231 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
232
f4f1b9f1
CD		 2332002-06-02 Chris Demetriou <cgd@broadcom.com>
234 Ed Satterthwaite <ehs@broadcom.com>
235
236 * mips.igen (mdmx): New (pseudo-)model.
237 * mdmx.c, mdmx.igen: New files.
238 * Makefile.in (SIM_OBJS): Add mdmx.o.
239 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
240 New typedefs.
241 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
242 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
243 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
244 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
245 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
246 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
247 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
248 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
249 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
250 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
251 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
252 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
253 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
254 (qh_fmtsel): New macros.
255 (_sim_cpu): New member "acc".
256 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
257 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
258
5accf1ff
CD		 2592002-05-01 Chris Demetriou <cgd@broadcom.com>
260
261 * interp.c: Use 'deprecated' rather than 'depreciated.'
262 * sim-main.h: Likewise.
263
402586aa
CD		 2642002-05-01 Chris Demetriou <cgd@broadcom.com>
265
266 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
267 which wouldn't compile anyway.
268 * sim-main.h (unpredictable_action): New function prototype.
269 (Unpredictable): Define to call igen function unpredictable().
270 (NotWordValue): New macro to call igen function not_word_value().
271 (UndefinedResult): Remove.
272 * interp.c (undefined_result): Remove.
273 (unpredictable_action): New function.
274 * mips.igen (not_word_value, unpredictable): New functions.
275 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
276 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
277 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
278 NotWordValue() to check for unpredictable inputs, then
279 Unpredictable() to handle them.
280
c9b9995a
CD		 2812002-02-24 Chris Demetriou <cgd@broadcom.com>
282
283 * mips.igen: Fix formatting of calls to Unpredictable().
284
e1015982
AC		 2852002-04-20 Andrew Cagney <ac131313@redhat.com>
286
287 * interp.c (sim_open): Revert previous change.
288
b882a66b
AO		 2892002-04-18 Alexandre Oliva <aoliva@redhat.com>
290
291 * interp.c (sim_open): Disable chunk of code that wrote code in
292 vector table entries.
293
c429b7dd
CD		 2942002-03-19 Chris Demetriou <cgd@broadcom.com>
295
296 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
297 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
298 unused definitions.
299
37d146fa
CD		 3002002-03-19 Chris Demetriou <cgd@broadcom.com>
301
302 * cp1.c: Fix many formatting issues.
303
07892c0b
CD		 3042002-03-19 Chris G. Demetriou <cgd@broadcom.com>
305
306 * cp1.c (fpu_format_name): New function to replace...
307 (DOFMT): This. Delete, and update all callers.
308 (fpu_rounding_mode_name): New function to replace...
309 (RMMODE): This. Delete, and update all callers.
310
487f79b7
CD		 3112002-03-19 Chris G. Demetriou <cgd@broadcom.com>
312
313 * interp.c: Move FPU support routines from here to...
314 * cp1.c: Here. New file.
315 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
316 (cp1.o): New target.
317
1e799e28
CD		 3182002-03-12 Chris Demetriou <cgd@broadcom.com>
319
320 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
321 * mips.igen (mips32, mips64): New models, add to all instructions
322 and functions as appropriate.
323 (loadstore_ea, check_u64): New variant for model mips64.
324 (check_fmt_p): New variant for models mipsV and mips64, remove
325 mipsV model marking fro other variant.
326 (SLL) Rename to...
327 (SLLa) this.
328 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
329 for mips32 and mips64.
330 (DCLO, DCLZ): New instructions for mips64.
331
82f728db
CD		 3322002-03-07 Chris Demetriou <cgd@broadcom.com>
333
334 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
335 immediate or code as a hex value with the "%#lx" format.
336 (ANDI): Likewise, and fix printed instruction name.
337
b96e7ef1
CD		 3382002-03-05 Chris Demetriou <cgd@broadcom.com>
339
340 * sim-main.h (UndefinedResult, Unpredictable): New macros
341 which currently do nothing.
342
d35d4f70
CD		 3432002-03-05 Chris Demetriou <cgd@broadcom.com>
344
345 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
346 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
347 (status_CU3): New definitions.
348
349 * sim-main.h (ExceptionCause): Add new values for MIPS32
350 and MIPS64: MDMX, MCheck, CacheErr. Update comments
351 for DebugBreakPoint and NMIReset to note their status in
352 MIPS32 and MIPS64.
353 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
354 (SignalExceptionCacheErr): New exception macros.
355
3ad6f714
CD		 3562002-03-05 Chris Demetriou <cgd@broadcom.com>
357
358 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
359 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
360 is always enabled.
361 (SignalExceptionCoProcessorUnusable): Take as argument the
362 unusable coprocessor number.
363
86b77b47
CD		 3642002-03-05 Chris Demetriou <cgd@broadcom.com>
365
366 * mips.igen: Fix formatting of all SignalException calls.
367
97a88e93 3682002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 369
370 * sim-main.h (SIGNEXTEND): Remove.
371
97a88e93 3722002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 373
374 * mips.igen: Remove gencode comment from top of file, fix
375 spelling in another comment.
376
97a88e93 3772002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 378
379 * mips.igen (check_fmt, check_fmt_p): New functions to check
380 whether specific floating point formats are usable.
381 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
382 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
383 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
384 Use the new functions.
385 (do_c_cond_fmt): Remove format checks...
386 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
387
97a88e93 3882002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 389
390 * mips.igen: Fix formatting of check_fpu calls.
391
41774c9d
CD		 3922002-03-03 Chris Demetriou <cgd@broadcom.com>
393
394 * mips.igen (FLOOR.L.fmt): Store correct destination register.
395
4a0bd876
CD		 3962002-03-03 Chris Demetriou <cgd@broadcom.com>
397
398 * mips.igen: Remove whitespace at end of lines.
399
09297648
CD		 4002002-03-02 Chris Demetriou <cgd@broadcom.com>
401
402 * mips.igen (loadstore_ea): New function to do effective
403 address calculations.
404 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
405 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
406 CACHE): Use loadstore_ea to do effective address computations.
407
043b7057
CD		 4082002-03-02 Chris Demetriou <cgd@broadcom.com>
409
410 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
411 * mips.igen (LL, CxC1, MxC1): Likewise.
412
c1e8ada4
CD		 4132002-03-02 Chris Demetriou <cgd@broadcom.com>
414
415 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
416 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
417 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
418 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
419 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
420 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
421 Don't split opcode fields by hand, use the opcode field values
422 provided by igen.
423
3e1dca16
CD		 4242002-03-01 Chris Demetriou <cgd@broadcom.com>
425
426 * mips.igen (do_divu): Fix spacing.
427
428 * mips.igen (do_dsllv): Move to be right before DSLLV,
429 to match the rest of the do_<shift> functions.
430
fff8d27d
CD		 4312002-03-01 Chris Demetriou <cgd@broadcom.com>
432
433 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
434 DSRL32, do_dsrlv): Trace inputs and results.
435
0d3e762b
CD		 4362002-03-01 Chris Demetriou <cgd@broadcom.com>
437
438 * mips.igen (CACHE): Provide instruction-printing string.
439
440 * interp.c (signal_exception): Comment tokens after #endif.
441
eb5fcf93
CD		 4422002-02-28 Chris Demetriou <cgd@broadcom.com>
443
444 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
445 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
446 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
447 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
448 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
449 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
450 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
451 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
452
bb22bd7d
CD		 4532002-02-28 Chris Demetriou <cgd@broadcom.com>
454
455 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
456 instruction-printing string.
457 (LWU): Use '64' as the filter flag.
458
91a177cf
CD		 4592002-02-28 Chris Demetriou <cgd@broadcom.com>
460
461 * mips.igen (SDXC1): Fix instruction-printing string.
462
387f484a
CD		 4632002-02-28 Chris Demetriou <cgd@broadcom.com>
464
465 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
466 filter flags "32,f".
467
3d81f391
CD		 4682002-02-27 Chris Demetriou <cgd@broadcom.com>
469
470 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
471 as the filter flag.
472
af5107af
CD		 4732002-02-27 Chris Demetriou <cgd@broadcom.com>
474
475 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
476 add a comma) so that it more closely match the MIPS ISA
477 documentation opcode partitioning.
478 (PREF): Put useful names on opcode fields, and include
479 instruction-printing string.
480
ca971540
CD		 4812002-02-27 Chris Demetriou <cgd@broadcom.com>
482
483 * mips.igen (check_u64): New function which in the future will
484 check whether 64-bit instructions are usable and signal an
485 exception if not. Currently a no-op.
486 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
487 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
488 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
489 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
490
491 * mips.igen (check_fpu): New function which in the future will
492 check whether FPU instructions are usable and signal an exception
493 if not. Currently a no-op.
494 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
495 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
496 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
497 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
498 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
499 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
500 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
501 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
502
1c47a468
CD		 5032002-02-27 Chris Demetriou <cgd@broadcom.com>
504
505 * mips.igen (do_load_left, do_load_right): Move to be immediately
506 following do_load.
507 (do_store_left, do_store_right): Move to be immediately following
508 do_store.
509
603a98e7
CD		 5102002-02-27 Chris Demetriou <cgd@broadcom.com>
511
512 * mips.igen (mipsV): New model name. Also, add it to
513 all instructions and functions where it is appropriate.
514
c5d00cc7
CD		 5152002-02-18 Chris Demetriou <cgd@broadcom.com>
516
517 * mips.igen: For all functions and instructions, list model
518 names that support that instruction one per line.
519
074e9cb8
CD		 5202002-02-11 Chris Demetriou <cgd@broadcom.com>
521
522 * mips.igen: Add some additional comments about supported
523 models, and about which instructions go where.
524 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
525 order as is used in the rest of the file.
526
9805e229
CD		 5272002-02-11 Chris Demetriou <cgd@broadcom.com>
528
529 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
530 indicating that ALU32_END or ALU64_END are there to check
531 for overflow.
532 (DADD): Likewise, but also remove previous comment about
533 overflow checking.
534
f701dad2
CD		 5352002-02-10 Chris Demetriou <cgd@broadcom.com>
536
537 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
538 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
539 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
540 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
541 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
542 fields (i.e., add and move commas) so that they more closely
543 match the MIPS ISA documentation opcode partitioning.
544
5452002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098
CD		 546
547 * mips.igen (ADDI): Print immediate value.
548 (BREAK): Print code.
549 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
550 (SLL): Print "nop" specially, and don't run the code
551 that does the shift for the "nop" case.
552
9e52972e
FF		 5532001-11-17 Fred Fish <fnf@redhat.com>
554
555 * sim-main.h (float_operation): Move enum declaration outside
556 of _sim_cpu struct declaration.
557
c0efbca4
JB		 5582001-04-12 Jim Blandy <jimb@redhat.com>
559
560 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
561 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
562 set of the FCSR.
563 * sim-main.h (COCIDX): Remove definition; this isn't supported by
564 PENDING_FILL, and you can get the intended effect gracefully by
565 calling PENDING_SCHED directly.
566
fb891446
BE		 5672001-02-23 Ben Elliston <bje@redhat.com>
568
569 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
570 already defined elsewhere.
571
8030f857
BE		 5722001-02-19 Ben Elliston <bje@redhat.com>
573
574 * sim-main.h (sim_monitor): Return an int.
575 * interp.c (sim_monitor): Add return values.
576 (signal_exception): Handle error conditions from sim_monitor.
577
56b48a7a
CD		 5782001-02-08 Ben Elliston <bje@redhat.com>
579
580 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
581 (store_memory): Likewise, pass cia to sim_core_write*.
582
d3ee60d9
FCE		 5832000-10-19 Frank Ch. Eigler <fche@redhat.com>
584
585 On advice from Chris G. Demetriou <cgd@sibyte.com>:
586 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
587
071da002
AC		 588Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
589
590 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
591 * Makefile.in: Don't delete *.igen when cleaning directory.
592
a28c02cd
AC		 593Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
594
595 * m16.igen (break): Call SignalException not sim_engine_halt.
596
80ee11fa
AC		 597Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
598
599 From Jason Eckhardt:
600 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
601
673388c0
AC		 602Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
603
604 * mips.igen (MxC1, DMxC1): Fix printf formatting.
605
4c0deff4
NC		 6062000-05-24 Michael Hayes <mhayes@cygnus.com>
607
608 * mips.igen (do_dmultx): Fix typo.
609
eb2d80b4
AC		 610Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
611
612 * configure: Regenerated to track ../common/aclocal.m4 changes.
613
dd37a34b
AC		 614Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
615
616 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
617
4c0deff4
NC		 6182000-04-12 Frank Ch. Eigler <fche@redhat.com>
619
620 * sim-main.h (GPR_CLEAR): Define macro.
621
e30db738
AC		 622Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
623
624 * interp.c (decode_coproc): Output long using %lx and not %s.
625
cb7450ea
FCE		 6262000-03-21 Frank Ch. Eigler <fche@redhat.com>
627
628 * interp.c (sim_open): Sort & extend dummy memory regions for
629 --board=jmr3904 for eCos.
630
a3027dd7
FCE		 6312000-03-02 Frank Ch. Eigler <fche@redhat.com>
632
633 * configure: Regenerated.
634
635Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
636
637 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
638 calls, conditional on the simulator being in verbose mode.
639
dfcd3bfb
JM		 640Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
641
642 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
643 cache don't get ReservedInstruction traps.
644
c2d11a7d
JM		 6451999-11-29 Mark Salter <msalter@cygnus.com>
646
647 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
648 to clear status bits in sdisr register. This is how the hardware works.
649
650 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
651 being used by cygmon.
652
4ce44c66
JM		 6531999-11-11 Andrew Haley <aph@cygnus.com>
654
655 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
656 instructions.
657
cff3e48b
JM		 658Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
659
660 * mips.igen (MULT): Correct previous mis-applied patch.
661
d4f3574e
SS		 662Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
663
664 * mips.igen (delayslot32): Handle sequence like
665 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
666 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
667 (MULT): Actually pass the third register...
668
6691999-09-03 Mark Salter <msalter@cygnus.com>
670
671 * interp.c (sim_open): Added more memory aliases for additional
672 hardware being touched by cygmon on jmr3904 board.
673
674Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
675
676 * configure: Regenerated to track ../common/aclocal.m4 changes.
677
a0b3c4fd
JM		 678Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
679
680 * interp.c (sim_store_register): Handle case where client - GDB -
681 specifies that a 4 byte register is 8 bytes in size.
682 (sim_fetch_register): Ditto.
683
adf40b2e
JM		 6841999-07-14 Frank Ch. Eigler <fche@cygnus.com>
685
686 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
687 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
688 (idt_monitor_base): Base address for IDT monitor traps.
689 (pmon_monitor_base): Ditto for PMON.
690 (lsipmon_monitor_base): Ditto for LSI PMON.
691 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
692 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
693 (sim_firmware_command): New function.
694 (mips_option_handler): Call it for OPTION_FIRMWARE.
695 (sim_open): Allocate memory for idt_monitor region. If "--board"
696 option was given, add no monitor by default. Add BREAK hooks only if
697 monitors are also there.
698
43e526b9
JM		 699Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
700
701 * interp.c (sim_monitor): Flush output before reading input.
702
703Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
704
705 * tconfig.in (SIM_HANDLES_LMA): Always define.
706
707Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
708
709 From Mark Salter <msalter@cygnus.com>:
710 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
711 (sim_open): Add setup for BSP board.
712
9846de1b
JM		 713Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
714
715 * mips.igen (MULT, MULTU): Add syntax for two operand version.
716 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
717 them as unimplemented.
718
cd0fc7c3
SS		 7191999-05-08 Felix Lee <flee@cygnus.com>
720
721 * configure: Regenerated to track ../common/aclocal.m4 changes.
722
7a292a7a
SS		 7231999-04-21 Frank Ch. Eigler <fche@cygnus.com>
724
725 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
726
727Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
728
729 * configure.in: Any mips64vr5*-*-* target should have
730 -DTARGET_ENABLE_FR=1.
731 (default_endian): Any mips64vr*el-*-* target should default to
732 LITTLE_ENDIAN.
733 * configure: Re-generate.
734
7351999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
736
737 * mips.igen (ldl): Extend from _16_, not 32.
738
739Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
740
741 * interp.c (sim_store_register): Force registers written to by GDB
742 into an un-interpreted state.
743
c906108c
SS		 7441999-02-05 Frank Ch. Eigler <fche@cygnus.com>
745
746 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
747 CPU, start periodic background I/O polls.
748 (tx3904sio_poll): New function: periodic I/O poller.
749
7501998-12-30 Frank Ch. Eigler <fche@cygnus.com>
751
752 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
753
754Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
755
756 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
757 case statement.
758
7591998-12-29 Frank Ch. Eigler <fche@cygnus.com>
760
761 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
762 (load_word): Call SIM_CORE_SIGNAL hook on error.
763 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
764 starting. For exception dispatching, pass PC instead of NULL_CIA.
765 (decode_coproc): Use COP0_BADVADDR to store faulting address.
766 * sim-main.h (COP0_BADVADDR): Define.
767 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
768 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
769 (_sim_cpu): Add exc_* fields to store register value snapshots.
770 * mips.igen (*): Replace memory-related SignalException* calls
771 with references to SIM_CORE_SIGNAL hook.
772
773 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
774 fix.
775 * sim-main.c (*): Minor warning cleanups.
776
7771998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
778
779 * m16.igen (DADDIU5): Correct type-o.
780
781Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
782
783 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
784 variables.
785
786Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
787
788 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
789 to include path.
790 (interp.o): Add dependency on itable.h
791 (oengine.c, gencode): Delete remaining references.
792 (BUILT_SRC_FROM_GEN): Clean up.
793
7941998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
795
796 * vr4run.c: New.
797 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
798 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
799 tmp-run-hack) : New.
800 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
801 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
802 Drop the "64" qualifier to get the HACK generator working.
803 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
804 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
805 qualifier to get the hack generator working.
806 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
807 (DSLL): Use do_dsll.
808 (DSLLV): Use do_dsllv.
809 (DSRA): Use do_dsra.
810 (DSRL): Use do_dsrl.
811 (DSRLV): Use do_dsrlv.
812 (BC1): Move *vr4100 to get the HACK generator working.
813 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
814 get the HACK generator working.
815 (MACC) Rename to get the HACK generator working.
816 (DMACC,MACCS,DMACCS): Add the 64.
817
8181998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
819
820 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
821 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
822
8231998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
824
825 * mips/interp.c (DEBUG): Cleanups.
826
8271998-12-10 Frank Ch. Eigler <fche@cygnus.com>
828
829 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
830 (tx3904sio_tickle): fflush after a stdout character output.
831
8321998-12-03 Frank Ch. Eigler <fche@cygnus.com>
833
834 * interp.c (sim_close): Uninstall modules.
835
836Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
837
838 * sim-main.h, interp.c (sim_monitor): Change to global
839 function.
840
841Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
842
843 * configure.in (vr4100): Only include vr4100 instructions in
844 simulator.
845 * configure: Re-generate.
846 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
847
848Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
849
850 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
851 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
852 true alternative.
853
854 * configure.in (sim_default_gen, sim_use_gen): Replace with
855 sim_gen.
856 (--enable-sim-igen): Delete config option. Always using IGEN.
857 * configure: Re-generate.
858
859 * Makefile.in (gencode): Kill, kill, kill.
860 * gencode.c: Ditto.
861
862Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
863
864 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
865 bit mips16 igen simulator.
866 * configure: Re-generate.
867
868 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
869 as part of vr4100 ISA.
870 * vr.igen: Mark all instructions as 64 bit only.
871
872Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
873
874 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
875 Pacify GCC.
876
877Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
878
879 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
880 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
881 * configure: Re-generate.
882
883 * m16.igen (BREAK): Define breakpoint instruction.
884 (JALX32): Mark instruction as mips16 and not r3900.
885 * mips.igen (C.cond.fmt): Fix typo in instruction format.
886
887 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
888
889Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
890
891 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
892 insn as a debug breakpoint.
893
894 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
895 pending.slot_size.
896 (PENDING_SCHED): Clean up trace statement.
897 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
898 (PENDING_FILL): Delay write by only one cycle.
899 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
900
901 * sim-main.c (pending_tick): Clean up trace statements. Add trace
902 of pending writes.
903 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
904 32 & 64.
905 (pending_tick): Move incrementing of index to FOR statement.
906 (pending_tick): Only update PENDING_OUT after a write has occured.
907
908 * configure.in: Add explicit mips-lsi-* target. Use gencode to
909 build simulator.
910 * configure: Re-generate.
911
912 * interp.c (sim_engine_run OLD): Delete explicit call to
913 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
914
915Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
916
917 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
918 interrupt level number to match changed SignalExceptionInterrupt
919 macro.
920
921Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
922
923 * interp.c: #include "itable.h" if WITH_IGEN.
924 (get_insn_name): New function.
925 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
926 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
927
928Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
929
930 * configure: Rebuilt to inhale new common/aclocal.m4.
931
932Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
933
934 * dv-tx3904sio.c: Include sim-assert.h.
935
936Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
937
938 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
939 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
940 Reorganize target-specific sim-hardware checks.
941 * configure: rebuilt.
942 * interp.c (sim_open): For tx39 target boards, set
943 OPERATING_ENVIRONMENT, add tx3904sio devices.
944 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
945 ROM executables. Install dv-sockser into sim-modules list.
946
947 * dv-tx3904irc.c: Compiler warning clean-up.
948 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
949 frequent hw-trace messages.
950
951Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
952
953 * vr.igen (MulAcc): Identify as a vr4100 specific function.
954
955Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
956
957 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
958
959 * vr.igen: New file.
960 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
961 * mips.igen: Define vr4100 model. Include vr.igen.
962Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
963
964 * mips.igen (check_mf_hilo): Correct check.
965
966Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
967
968 * sim-main.h (interrupt_event): Add prototype.
969
970 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
971 register_ptr, register_value.
972 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
973
974 * sim-main.h (tracefh): Make extern.
975
976Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
977
978 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
979 Reduce unnecessarily high timer event frequency.
980 * dv-tx3904cpu.c: Ditto for interrupt event.
981
982Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
983
984 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
985 to allay warnings.
986 (interrupt_event): Made non-static.
987
988 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
989 interchange of configuration values for external vs. internal
990 clock dividers.
991
992Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
993
994 * mips.igen (BREAK): Moved code to here for
995 simulator-reserved break instructions.
996 * gencode.c (build_instruction): Ditto.
997 * interp.c (signal_exception): Code moved from here. Non-
998 reserved instructions now use exception vector, rather
999 than halting sim.
1000 * sim-main.h: Moved magic constants to here.
1001
1002Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1003
1004 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1005 register upon non-zero interrupt event level, clear upon zero
1006 event value.
1007 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1008 by passing zero event value.
1009 (*_io_{read,write}_buffer): Endianness fixes.
1010 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1011 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1012
1013 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1014 serial I/O and timer module at base address 0xFFFF0000.
1015
1016Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1017
1018 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1019 and BigEndianCPU.
1020
1021Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1022
1023 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1024 parts.
1025 * configure: Update.
1026
1027Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1028
1029 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1030 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1031 * configure.in: Include tx3904tmr in hw_device list.
1032 * configure: Rebuilt.
1033 * interp.c (sim_open): Instantiate three timer instances.
1034 Fix address typo of tx3904irc instance.
1035
1036Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1037
1038 * interp.c (signal_exception): SystemCall exception now uses
1039 the exception vector.
1040
1041Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1042
1043 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1044 to allay warnings.
1045
1046Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1047
1048 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1049
1050Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1051
1052 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1053
1054 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1055 sim-main.h. Declare a struct hw_descriptor instead of struct
1056 hw_device_descriptor.
1057
1058Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1059
1060 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1061 right bits and then re-align left hand bytes to correct byte
1062 lanes. Fix incorrect computation in do_store_left when loading
1063 bytes from second word.
1064
1065Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1066
1067 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1068 * interp.c (sim_open): Only create a device tree when HW is
1069 enabled.
1070
1071 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1072 * interp.c (signal_exception): Ditto.
1073
1074Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1075
1076 * gencode.c: Mark BEGEZALL as LIKELY.
1077
1078Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1079
1080 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1081 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1082
1083Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1084
1085 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1086 modules. Recognize TX39 target with "mips*tx39" pattern.
1087 * configure: Rebuilt.
1088 * sim-main.h (*): Added many macros defining bits in
1089 TX39 control registers.
1090 (SignalInterrupt): Send actual PC instead of NULL.
1091 (SignalNMIReset): New exception type.
1092 * interp.c (board): New variable for future use to identify
1093 a particular board being simulated.
1094 (mips_option_handler,mips_options): Added "--board" option.
1095 (interrupt_event): Send actual PC.
1096 (sim_open): Make memory layout conditional on board setting.
1097 (signal_exception): Initial implementation of hardware interrupt
1098 handling. Accept another break instruction variant for simulator
1099 exit.
1100 (decode_coproc): Implement RFE instruction for TX39.
1101 (mips.igen): Decode RFE instruction as such.
1102 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1103 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1104 bbegin to implement memory map.
1105 * dv-tx3904cpu.c: New file.
1106 * dv-tx3904irc.c: New file.
1107
1108Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1109
1110 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1111
1112Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1113
1114 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1115 with calls to check_div_hilo.
1116
1117Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1118
1119 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1120 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1121 Add special r3900 version of do_mult_hilo.
1122 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1123 with calls to check_mult_hilo.
1124 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1125 with calls to check_div_hilo.
1126
1127Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1128
1129 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1130 Document a replacement.
1131
1132Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1133
1134 * interp.c (sim_monitor): Make mon_printf work.
1135
1136Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1137
1138 * sim-main.h (INSN_NAME): New arg `cpu'.
1139
1140Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1141
1142 * configure: Regenerated to track ../common/aclocal.m4 changes.
1143
1144Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1145
1146 * configure: Regenerated to track ../common/aclocal.m4 changes.
1147 * config.in: Ditto.
1148
1149Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1150
1151 * acconfig.h: New file.
1152 * configure.in: Reverted change of Apr 24; use sinclude again.
1153
1154Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1155
1156 * configure: Regenerated to track ../common/aclocal.m4 changes.
1157 * config.in: Ditto.
1158
1159Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1160
1161 * configure.in: Don't call sinclude.
1162
1163Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1164
1165 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1166
1167Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1168
1169 * mips.igen (ERET): Implement.
1170
1171 * interp.c (decode_coproc): Return sign-extended EPC.
1172
1173 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1174
1175 * interp.c (signal_exception): Do not ignore Trap.
1176 (signal_exception): On TRAP, restart at exception address.
1177 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1178 (signal_exception): Update.
1179 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1180 so that TRAP instructions are caught.
1181
1182Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1183
1184 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1185 contains HI/LO access history.
1186 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1187 (HIACCESS, LOACCESS): Delete, replace with
1188 (HIHISTORY, LOHISTORY): New macros.
1189 (CHECKHILO): Delete all, moved to mips.igen
1190
1191 * gencode.c (build_instruction): Do not generate checks for
1192 correct HI/LO register usage.
1193
1194 * interp.c (old_engine_run): Delete checks for correct HI/LO
1195 register usage.
1196
1197 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1198 check_mf_cycles): New functions.
1199 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1200 do_divu, domultx, do_mult, do_multu): Use.
1201
1202 * tx.igen ("madd", "maddu"): Use.
1203
1204Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1205
1206 * mips.igen (DSRAV): Use function do_dsrav.
1207 (SRAV): Use new function do_srav.
1208
1209 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1210 (B): Sign extend 11 bit immediate.
1211 (EXT-B*): Shift 16 bit immediate left by 1.
1212 (ADDIU*): Don't sign extend immediate value.
1213
1214Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1215
1216 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1217
1218 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1219 functions.
1220
1221 * mips.igen (delayslot32, nullify_next_insn): New functions.
1222 (m16.igen): Always include.
1223 (do_*): Add more tracing.
1224
1225 * m16.igen (delayslot16): Add NIA argument, could be called by a
1226 32 bit MIPS16 instruction.
1227
1228 * interp.c (ifetch16): Move function from here.
1229 * sim-main.c (ifetch16): To here.
1230
1231 * sim-main.c (ifetch16, ifetch32): Update to match current
1232 implementations of LH, LW.
1233 (signal_exception): Don't print out incorrect hex value of illegal
1234 instruction.
1235
1236Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1237
1238 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1239 instruction.
1240
1241 * m16.igen: Implement MIPS16 instructions.
1242
1243 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1244 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1245 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1246 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1247 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1248 bodies of corresponding code from 32 bit insn to these. Also used
1249 by MIPS16 versions of functions.
1250
1251 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1252 (IMEM16): Drop NR argument from macro.
1253
1254Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1255
1256 * Makefile.in (SIM_OBJS): Add sim-main.o.
1257
1258 * sim-main.h (address_translation, load_memory, store_memory,
1259 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1260 as INLINE_SIM_MAIN.
1261 (pr_addr, pr_uword64): Declare.
1262 (sim-main.c): Include when H_REVEALS_MODULE_P.
1263
1264 * interp.c (address_translation, load_memory, store_memory,
1265 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1266 from here.
1267 * sim-main.c: To here. Fix compilation problems.
1268
1269 * configure.in: Enable inlining.
1270 * configure: Re-config.
1271
1272Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1273
1274 * configure: Regenerated to track ../common/aclocal.m4 changes.
1275
1276Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1277
1278 * mips.igen: Include tx.igen.
1279 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1280 * tx.igen: New file, contains MADD and MADDU.
1281
1282 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1283 the hardwired constant `7'.
1284 (store_memory): Ditto.
1285 (LOADDRMASK): Move definition to sim-main.h.
1286
1287 mips.igen (MTC0): Enable for r3900.
1288 (ADDU): Add trace.
1289
1290 mips.igen (do_load_byte): Delete.
1291 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1292 do_store_right): New functions.
1293 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1294
1295 configure.in: Let the tx39 use igen again.
1296 configure: Update.
1297
1298Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1299
1300 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1301 not an address sized quantity. Return zero for cache sizes.
1302
1303Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1304
1305 * mips.igen (r3900): r3900 does not support 64 bit integer
1306 operations.
1307
1308Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1309
1310 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1311 than igen one.
1312 * configure : Rebuild.
1313
1314Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1315
1316 * configure: Regenerated to track ../common/aclocal.m4 changes.
1317
1318Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1319
1320 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1321
1322Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1323
1324 * configure: Regenerated to track ../common/aclocal.m4 changes.
1325 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1326
1327Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1328
1329 * configure: Regenerated to track ../common/aclocal.m4 changes.
1330
1331Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1332
1333 * interp.c (Max, Min): Comment out functions. Not yet used.
1334
1335Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1336
1337 * configure: Regenerated to track ../common/aclocal.m4 changes.
1338
1339Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1340
1341 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1342 configurable settings for stand-alone simulator.
1343
1344 * configure.in: Added X11 search, just in case.
1345
1346 * configure: Regenerated.
1347
1348Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1349
1350 * interp.c (sim_write, sim_read, load_memory, store_memory):
1351 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1352
1353Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1354
1355 * sim-main.h (GETFCC): Return an unsigned value.
1356
1357Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1358
1359 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1360 (DADD): Result destination is RD not RT.
1361
1362Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1363
1364 * sim-main.h (HIACCESS, LOACCESS): Always define.
1365
1366 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1367
1368 * interp.c (sim_info): Delete.
1369
1370Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1371
1372 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1373 (mips_option_handler): New argument `cpu'.
1374 (sim_open): Update call to sim_add_option_table.
1375
1376Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1377
1378 * mips.igen (CxC1): Add tracing.
1379
1380Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1381
1382 * sim-main.h (Max, Min): Declare.
1383
1384 * interp.c (Max, Min): New functions.
1385
1386 * mips.igen (BC1): Add tracing.
1387
1388Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1389
1390 * interp.c Added memory map for stack in vr4100
1391
1392Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1393
1394 * interp.c (load_memory): Add missing "break"'s.
1395
1396Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1397
1398 * interp.c (sim_store_register, sim_fetch_register): Pass in
1399 length parameter. Return -1.
1400
1401Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1402
1403 * interp.c: Added hardware init hook, fixed warnings.
1404
1405Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1406
1407 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1408
1409Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1410
1411 * interp.c (ifetch16): New function.
1412
1413 * sim-main.h (IMEM32): Rename IMEM.
1414 (IMEM16_IMMED): Define.
1415 (IMEM16): Define.
1416 (DELAY_SLOT): Update.
1417
1418 * m16run.c (sim_engine_run): New file.
1419
1420 * m16.igen: All instructions except LB.
1421 (LB): Call do_load_byte.
1422 * mips.igen (do_load_byte): New function.
1423 (LB): Call do_load_byte.
1424
1425 * mips.igen: Move spec for insn bit size and high bit from here.
1426 * Makefile.in (tmp-igen, tmp-m16): To here.
1427
1428 * m16.dc: New file, decode mips16 instructions.
1429
1430 * Makefile.in (SIM_NO_ALL): Define.
1431 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1432
1433Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1434
1435 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1436 point unit to 32 bit registers.
1437 * configure: Re-generate.
1438
1439Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1440
1441 * configure.in (sim_use_gen): Make IGEN the default simulator
1442 generator for generic 32 and 64 bit mips targets.
1443 * configure: Re-generate.
1444
1445Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1446
1447 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1448 bitsize.
1449
1450 * interp.c (sim_fetch_register, sim_store_register): Read/write
1451 FGR from correct location.
1452 (sim_open): Set size of FGR's according to
1453 WITH_TARGET_FLOATING_POINT_BITSIZE.
1454
1455 * sim-main.h (FGR): Store floating point registers in a separate
1456 array.
1457
1458Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1459
1460 * configure: Regenerated to track ../common/aclocal.m4 changes.
1461
1462Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1463
1464 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1465
1466 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1467
1468 * interp.c (pending_tick): New function. Deliver pending writes.
1469
1470 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1471 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1472 it can handle mixed sized quantites and single bits.
1473
1474Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1475
1476 * interp.c (oengine.h): Do not include when building with IGEN.
1477 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1478 (sim_info): Ditto for PROCESSOR_64BIT.
1479 (sim_monitor): Replace ut_reg with unsigned_word.
1480 (*): Ditto for t_reg.
1481 (LOADDRMASK): Define.
1482 (sim_open): Remove defunct check that host FP is IEEE compliant,
1483 using software to emulate floating point.
1484 (value_fpr, ...): Always compile, was conditional on HASFPU.
1485
1486Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1487
1488 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1489 size.
1490
1491 * interp.c (SD, CPU): Define.
1492 (mips_option_handler): Set flags in each CPU.
1493 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1494 (sim_close): Do not clear STATE, deleted anyway.
1495 (sim_write, sim_read): Assume CPU zero's vm should be used for
1496 data transfers.
1497 (sim_create_inferior): Set the PC for all processors.
1498 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1499 argument.
1500 (mips16_entry): Pass correct nr of args to store_word, load_word.
1501 (ColdReset): Cold reset all cpu's.
1502 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1503 (sim_monitor, load_memory, store_memory, signal_exception): Use
1504 `CPU' instead of STATE_CPU.
1505
1506
1507 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1508 SD or CPU_.
1509
1510 * sim-main.h (signal_exception): Add sim_cpu arg.
1511 (SignalException*): Pass both SD and CPU to signal_exception.
1512 * interp.c (signal_exception): Update.
1513
1514 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1515 Ditto
1516 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1517 address_translation): Ditto
1518 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1519
1520Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1521
1522 * configure: Regenerated to track ../common/aclocal.m4 changes.
1523
1524Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1525
1526 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1527
1528 * mips.igen (model): Map processor names onto BFD name.
1529
1530 * sim-main.h (CPU_CIA): Delete.
1531 (SET_CIA, GET_CIA): Define
1532
1533Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1534
1535 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1536 regiser.
1537
1538 * configure.in (default_endian): Configure a big-endian simulator
1539 by default.
1540 * configure: Re-generate.
1541
1542Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1543
1544 * configure: Regenerated to track ../common/aclocal.m4 changes.
1545
1546Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1547
1548 * interp.c (sim_monitor): Handle Densan monitor outbyte
1549 and inbyte functions.
1550
15511997-12-29 Felix Lee <flee@cygnus.com>
1552
1553 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1554
1555Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1556
1557 * Makefile.in (tmp-igen): Arrange for $zero to always be
1558 reset to zero after every instruction.
1559
1560Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1561
1562 * configure: Regenerated to track ../common/aclocal.m4 changes.
1563 * config.in: Ditto.
1564
1565Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1566
1567 * mips.igen (MSUB): Fix to work like MADD.
1568 * gencode.c (MSUB): Similarly.
1569
1570Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1571
1572 * configure: Regenerated to track ../common/aclocal.m4 changes.
1573
1574Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1575
1576 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1577
1578Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1579
1580 * sim-main.h (sim-fpu.h): Include.
1581
1582 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1583 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1584 using host independant sim_fpu module.
1585
1586Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1587
1588 * interp.c (signal_exception): Report internal errors with SIGABRT
1589 not SIGQUIT.
1590
1591 * sim-main.h (C0_CONFIG): New register.
1592 (signal.h): No longer include.
1593
1594 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1595
1596Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1597
1598 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1599
1600Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1601
1602 * mips.igen: Tag vr5000 instructions.
1603 (ANDI): Was missing mipsIV model, fix assembler syntax.
1604 (do_c_cond_fmt): New function.
1605 (C.cond.fmt): Handle mips I-III which do not support CC field
1606 separatly.
1607 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1608 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1609 in IV3.2 spec.
1610 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1611 vr5000 which saves LO in a GPR separatly.
1612
1613 * configure.in (enable-sim-igen): For vr5000, select vr5000
1614 specific instructions.
1615 * configure: Re-generate.
1616
1617Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1618
1619 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1620
1621 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1622 fmt_uninterpreted_64 bit cases to switch. Convert to
1623 fmt_formatted,
1624
1625 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1626
1627 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1628 as specified in IV3.2 spec.
1629 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1630
1631Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1632
1633 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1634 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1635 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1636 PENDING_FILL versions of instructions. Simplify.
1637 (X): New function.
1638 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1639 instructions.
1640 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1641 a signed value.
1642 (MTHI, MFHI): Disable code checking HI-LO.
1643
1644 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1645 global.
1646 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1647
1648Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1649
1650 * gencode.c (build_mips16_operands): Replace IPC with cia.
1651
1652 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1653 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1654 IPC to `cia'.
1655 (UndefinedResult): Replace function with macro/function
1656 combination.
1657 (sim_engine_run): Don't save PC in IPC.
1658
1659 * sim-main.h (IPC): Delete.
1660
1661
1662 * interp.c (signal_exception, store_word, load_word,
1663 address_translation, load_memory, store_memory, cache_op,
1664 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1665 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1666 current instruction address - cia - argument.
1667 (sim_read, sim_write): Call address_translation directly.
1668 (sim_engine_run): Rename variable vaddr to cia.
1669 (signal_exception): Pass cia to sim_monitor
1670
1671 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1672 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1673 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1674
1675 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1676 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1677 SIM_ASSERT.
1678
1679 * interp.c (signal_exception): Pass restart address to
1680 sim_engine_restart.
1681
1682 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1683 idecode.o): Add dependency.
1684
1685 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1686 Delete definitions
1687 (DELAY_SLOT): Update NIA not PC with branch address.
1688 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1689
1690 * mips.igen: Use CIA not PC in branch calculations.
1691 (illegal): Call SignalException.
1692 (BEQ, ADDIU): Fix assembler.
1693
1694Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1695
1696 * m16.igen (JALX): Was missing.
1697
1698 * configure.in (enable-sim-igen): New configuration option.
1699 * configure: Re-generate.
1700
1701 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1702
1703 * interp.c (load_memory, store_memory): Delete parameter RAW.
1704 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1705 bypassing {load,store}_memory.
1706
1707 * sim-main.h (ByteSwapMem): Delete definition.
1708
1709 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1710
1711 * interp.c (sim_do_command, sim_commands): Delete mips specific
1712 commands. Handled by module sim-options.
1713
1714 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1715 (WITH_MODULO_MEMORY): Define.
1716
1717 * interp.c (sim_info): Delete code printing memory size.
1718
1719 * interp.c (mips_size): Nee sim_size, delete function.
1720 (power2): Delete.
1721 (monitor, monitor_base, monitor_size): Delete global variables.
1722 (sim_open, sim_close): Delete code creating monitor and other
1723 memory regions. Use sim-memopts module, via sim_do_commandf, to
1724 manage memory regions.
1725 (load_memory, store_memory): Use sim-core for memory model.
1726
1727 * interp.c (address_translation): Delete all memory map code
1728 except line forcing 32 bit addresses.
1729
1730Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1731
1732 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1733 trace options.
1734
1735 * interp.c (logfh, logfile): Delete globals.
1736 (sim_open, sim_close): Delete code opening & closing log file.
1737 (mips_option_handler): Delete -l and -n options.
1738 (OPTION mips_options): Ditto.
1739
1740 * interp.c (OPTION mips_options): Rename option trace to dinero.
1741 (mips_option_handler): Update.
1742
1743Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1744
1745 * interp.c (fetch_str): New function.
1746 (sim_monitor): Rewrite using sim_read & sim_write.
1747 (sim_open): Check magic number.
1748 (sim_open): Write monitor vectors into memory using sim_write.
1749 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1750 (sim_read, sim_write): Simplify - transfer data one byte at a
1751 time.
1752 (load_memory, store_memory): Clarify meaning of parameter RAW.
1753
1754 * sim-main.h (isHOST): Defete definition.
1755 (isTARGET): Mark as depreciated.
1756 (address_translation): Delete parameter HOST.
1757
1758 * interp.c (address_translation): Delete parameter HOST.
1759
1760Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1761
1762 * mips.igen:
1763
1764 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1765 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1766
1767Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1768
1769 * mips.igen: Add model filter field to records.
1770
1771Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1772
1773 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1774
1775 interp.c (sim_engine_run): Do not compile function sim_engine_run
1776 when WITH_IGEN == 1.
1777
1778 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1779 target architecture.
1780
1781 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1782 igen. Replace with configuration variables sim_igen_flags /
1783 sim_m16_flags.
1784
1785 * m16.igen: New file. Copy mips16 insns here.
1786 * mips.igen: From here.
1787
1788Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1789
1790 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1791 to top.
1792 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1793
1794Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1795
1796 * gencode.c (build_instruction): Follow sim_write's lead in using
1797 BigEndianMem instead of !ByteSwapMem.
1798
1799Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1800
1801 * configure.in (sim_gen): Dependent on target, select type of
1802 generator. Always select old style generator.
1803
1804 configure: Re-generate.
1805
1806 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1807 targets.
1808 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1809 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1810 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1811 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1812 SIM_@sim_gen@_*, set by autoconf.
1813
1814Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1815
1816 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1817
1818 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1819 CURRENT_FLOATING_POINT instead.
1820
1821 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1822 (address_translation): Raise exception InstructionFetch when
1823 translation fails and isINSTRUCTION.
1824
1825 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1826 sim_engine_run): Change type of of vaddr and paddr to
1827 address_word.
1828 (address_translation, prefetch, load_memory, store_memory,
1829 cache_op): Change type of vAddr and pAddr to address_word.
1830
1831 * gencode.c (build_instruction): Change type of vaddr and paddr to
1832 address_word.
1833
1834Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1835
1836 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1837 macro to obtain result of ALU op.
1838
1839Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1840
1841 * interp.c (sim_info): Call profile_print.
1842
1843Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1844
1845 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1846
1847 * sim-main.h (WITH_PROFILE): Do not define, defined in
1848 common/sim-config.h. Use sim-profile module.
1849 (simPROFILE): Delete defintion.
1850
1851 * interp.c (PROFILE): Delete definition.
1852 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1853 (sim_close): Delete code writing profile histogram.
1854 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1855 Delete.
1856 (sim_engine_run): Delete code profiling the PC.
1857
1858Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1859
1860 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1861
1862 * interp.c (sim_monitor): Make register pointers of type
1863 unsigned_word*.
1864
1865 * sim-main.h: Make registers of type unsigned_word not
1866 signed_word.
1867
1868Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1869
1870 * interp.c (sync_operation): Rename from SyncOperation, make
1871 global, add SD argument.
1872 (prefetch): Rename from Prefetch, make global, add SD argument.
1873 (decode_coproc): Make global.
1874
1875 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1876
1877 * gencode.c (build_instruction): Generate DecodeCoproc not
1878 decode_coproc calls.
1879
1880 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1881 (SizeFGR): Move to sim-main.h
1882 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1883 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1884 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1885 sim-main.h.
1886 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1887 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1888 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1889 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1890 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1891 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1892
1893 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1894 exception.
1895 (sim-alu.h): Include.
1896 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1897 (sim_cia): Typedef to instruction_address.
1898
1899Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1900
1901 * Makefile.in (interp.o): Rename generated file engine.c to
1902 oengine.c.
1903
1904 * interp.c: Update.
1905
1906Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1907
1908 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1909
1910Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1911
1912 * gencode.c (build_instruction): For "FPSQRT", output correct
1913 number of arguments to Recip.
1914
1915Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1916
1917 * Makefile.in (interp.o): Depends on sim-main.h
1918
1919 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1920
1921 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1922 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1923 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1924 STATE, DSSTATE): Define
1925 (GPR, FGRIDX, ..): Define.
1926
1927 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1928 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1929 (GPR, FGRIDX, ...): Delete macros.
1930
1931 * interp.c: Update names to match defines from sim-main.h
1932
1933Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1934
1935 * interp.c (sim_monitor): Add SD argument.
1936 (sim_warning): Delete. Replace calls with calls to
1937 sim_io_eprintf.
1938 (sim_error): Delete. Replace calls with sim_io_error.
1939 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1940 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1941 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1942 argument.
1943 (mips_size): Rename from sim_size. Add SD argument.
1944
1945 * interp.c (simulator): Delete global variable.
1946 (callback): Delete global variable.
1947 (mips_option_handler, sim_open, sim_write, sim_read,
1948 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1949 sim_size,sim_monitor): Use sim_io_* not callback->*.
1950 (sim_open): ZALLOC simulator struct.
1951 (PROFILE): Do not define.
1952
1953Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1954
1955 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1956 support.h with corresponding code.
1957
1958 * sim-main.h (word64, uword64), support.h: Move definition to
1959 sim-main.h.
1960 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1961
1962 * support.h: Delete
1963 * Makefile.in: Update dependencies
1964 * interp.c: Do not include.
1965
1966Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1967
1968 * interp.c (address_translation, load_memory, store_memory,
1969 cache_op): Rename to from AddressTranslation et.al., make global,
1970 add SD argument
1971
1972 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1973 CacheOp): Define.
1974
1975 * interp.c (SignalException): Rename to signal_exception, make
1976 global.
1977
1978 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1979
1980 * sim-main.h (SignalException, SignalExceptionInterrupt,
1981 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1982 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1983 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1984 Define.
1985
1986 * interp.c, support.h: Use.
1987
1988Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1989
1990 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1991 to value_fpr / store_fpr. Add SD argument.
1992 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1993 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1994
1995 * sim-main.h (ValueFPR, StoreFPR): Define.
1996
1997Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1998
1999 * interp.c (sim_engine_run): Check consistency between configure
2000 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2001 and HASFPU.
2002
2003 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2004 (mips_fpu): Configure WITH_FLOATING_POINT.
2005 (mips_endian): Configure WITH_TARGET_ENDIAN.
2006 * configure: Update.
2007
2008Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2009
2010 * configure: Regenerated to track ../common/aclocal.m4 changes.
2011
2012Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2013
2014 * configure: Regenerated.
2015
2016Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2017
2018 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2019
2020Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2021
2022 * gencode.c (print_igen_insn_models): Assume certain architectures
2023 include all mips* instructions.
2024 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2025 instruction.
2026
2027 * Makefile.in (tmp.igen): Add target. Generate igen input from
2028 gencode file.
2029
2030 * gencode.c (FEATURE_IGEN): Define.
2031 (main): Add --igen option. Generate output in igen format.
2032 (process_instructions): Format output according to igen option.
2033 (print_igen_insn_format): New function.
2034 (print_igen_insn_models): New function.
2035 (process_instructions): Only issue warnings and ignore
2036 instructions when no FEATURE_IGEN.
2037
2038Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2039
2040 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2041 MIPS targets.
2042
2043Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2044
2045 * configure: Regenerated to track ../common/aclocal.m4 changes.
2046
2047Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2048
2049 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2050 SIM_RESERVED_BITS): Delete, moved to common.
2051 (SIM_EXTRA_CFLAGS): Update.
2052
2053Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2054
2055 * configure.in: Configure non-strict memory alignment.
2056 * configure: Regenerated to track ../common/aclocal.m4 changes.
2057
2058Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2059
2060 * configure: Regenerated to track ../common/aclocal.m4 changes.
2061
2062Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2063
2064 * gencode.c (SDBBP,DERET): Added (3900) insns.
2065 (RFE): Turn on for 3900.
2066 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2067 (dsstate): Made global.
2068 (SUBTARGET_R3900): Added.
2069 (CANCELDELAYSLOT): New.
2070 (SignalException): Ignore SystemCall rather than ignore and
2071 terminate. Add DebugBreakPoint handling.
2072 (decode_coproc): New insns RFE, DERET; and new registers Debug
2073 and DEPC protected by SUBTARGET_R3900.
2074 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2075 bits explicitly.
2076 * Makefile.in,configure.in: Add mips subtarget option.
2077 * configure: Update.
2078
2079Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2080
2081 * gencode.c: Add r3900 (tx39).
2082
2083
2084Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2085
2086 * gencode.c (build_instruction): Don't need to subtract 4 for
2087 JALR, just 2.
2088
2089Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2090
2091 * interp.c: Correct some HASFPU problems.
2092
2093Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2094
2095 * configure: Regenerated to track ../common/aclocal.m4 changes.
2096
2097Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2098
2099 * interp.c (mips_options): Fix samples option short form, should
2100 be `x'.
2101
2102Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2103
2104 * interp.c (sim_info): Enable info code. Was just returning.
2105
2106Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2107
2108 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2109 MFC0.
2110
2111Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2112
2113 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2114 constants.
2115 (build_instruction): Ditto for LL.
2116
2117Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2118
2119 * configure: Regenerated to track ../common/aclocal.m4 changes.
2120
2121Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2122
2123 * configure: Regenerated to track ../common/aclocal.m4 changes.
2124 * config.in: Ditto.
2125
2126Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2127
2128 * interp.c (sim_open): Add call to sim_analyze_program, update
2129 call to sim_config.
2130
2131Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2132
2133 * interp.c (sim_kill): Delete.
2134 (sim_create_inferior): Add ABFD argument. Set PC from same.
2135 (sim_load): Move code initializing trap handlers from here.
2136 (sim_open): To here.
2137 (sim_load): Delete, use sim-hload.c.
2138
2139 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2140
2141Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2142
2143 * configure: Regenerated to track ../common/aclocal.m4 changes.
2144 * config.in: Ditto.
2145
2146Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2147
2148 * interp.c (sim_open): Add ABFD argument.
2149 (sim_load): Move call to sim_config from here.
2150 (sim_open): To here. Check return status.
2151
2152Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2153
2154 * gencode.c (build_instruction): Two arg MADD should
2155 not assign result to $0.
2156
2157Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2158
2159 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2160 * sim/mips/configure.in: Regenerate.
2161
2162Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2163
2164 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2165 signed8, unsigned8 et.al. types.
2166
2167 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2168 hosts when selecting subreg.
2169
2170Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2171
2172 * interp.c (sim_engine_run): Reset the ZERO register to zero
2173 regardless of FEATURE_WARN_ZERO.
2174 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2175
2176Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2177
2178 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2179 (SignalException): For BreakPoints ignore any mode bits and just
2180 save the PC.
2181 (SignalException): Always set the CAUSE register.
2182
2183Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2184
2185 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2186 exception has been taken.
2187
2188 * interp.c: Implement the ERET and mt/f sr instructions.
2189
2190Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2191
2192 * interp.c (SignalException): Don't bother restarting an
2193 interrupt.
2194
2195Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2196
2197 * interp.c (SignalException): Really take an interrupt.
2198 (interrupt_event): Only deliver interrupts when enabled.
2199
2200Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2201
2202 * interp.c (sim_info): Only print info when verbose.
2203 (sim_info) Use sim_io_printf for output.
2204
2205Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2206
2207 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2208 mips architectures.
2209
2210Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2211
2212 * interp.c (sim_do_command): Check for common commands if a
2213 simulator specific command fails.
2214
2215Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2216
2217 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2218 and simBE when DEBUG is defined.
2219
2220Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2221
2222 * interp.c (interrupt_event): New function. Pass exception event
2223 onto exception handler.
2224
2225 * configure.in: Check for stdlib.h.
2226 * configure: Regenerate.
2227
2228 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2229 variable declaration.
2230 (build_instruction): Initialize memval1.
2231 (build_instruction): Add UNUSED attribute to byte, bigend,
2232 reverse.
2233 (build_operands): Ditto.
2234
2235 * interp.c: Fix GCC warnings.
2236 (sim_get_quit_code): Delete.
2237
2238 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2239 * Makefile.in: Ditto.
2240 * configure: Re-generate.
2241
2242 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2243
2244Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2245
2246 * interp.c (mips_option_handler): New function parse argumes using
2247 sim-options.
2248 (myname): Replace with STATE_MY_NAME.
2249 (sim_open): Delete check for host endianness - performed by
2250 sim_config.
2251 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2252 (sim_open): Move much of the initialization from here.
2253 (sim_load): To here. After the image has been loaded and
2254 endianness set.
2255 (sim_open): Move ColdReset from here.
2256 (sim_create_inferior): To here.
2257 (sim_open): Make FP check less dependant on host endianness.
2258
2259 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2260 run.
2261 * interp.c (sim_set_callbacks): Delete.
2262
2263 * interp.c (membank, membank_base, membank_size): Replace with
2264 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2265 (sim_open): Remove call to callback->init. gdb/run do this.
2266
2267 * interp.c: Update
2268
2269 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2270
2271 * interp.c (big_endian_p): Delete, replaced by
2272 current_target_byte_order.
2273
2274Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2275
2276 * interp.c (host_read_long, host_read_word, host_swap_word,
2277 host_swap_long): Delete. Using common sim-endian.
2278 (sim_fetch_register, sim_store_register): Use H2T.
2279 (pipeline_ticks): Delete. Handled by sim-events.
2280 (sim_info): Update.
2281 (sim_engine_run): Update.
2282
2283Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2284
2285 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2286 reason from here.
2287 (SignalException): To here. Signal using sim_engine_halt.
2288 (sim_stop_reason): Delete, moved to common.
2289
2290Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2291
2292 * interp.c (sim_open): Add callback argument.
2293 (sim_set_callbacks): Delete SIM_DESC argument.
2294 (sim_size): Ditto.
2295
2296Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2297
2298 * Makefile.in (SIM_OBJS): Add common modules.
2299
2300 * interp.c (sim_set_callbacks): Also set SD callback.
2301 (set_endianness, xfer_*, swap_*): Delete.
2302 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2303 Change to functions using sim-endian macros.
2304 (control_c, sim_stop): Delete, use common version.
2305 (simulate): Convert into.
2306 (sim_engine_run): This function.
2307 (sim_resume): Delete.
2308
2309 * interp.c (simulation): New variable - the simulator object.
2310 (sim_kind): Delete global - merged into simulation.
2311 (sim_load): Cleanup. Move PC assignment from here.
2312 (sim_create_inferior): To here.
2313
2314 * sim-main.h: New file.
2315 * interp.c (sim-main.h): Include.
2316
2317Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2318
2319 * configure: Regenerated to track ../common/aclocal.m4 changes.
2320
2321Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2322
2323 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2324
2325Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2326
2327 * gencode.c (build_instruction): DIV instructions: check
2328 for division by zero and integer overflow before using
2329 host's division operation.
2330
2331Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2332
2333 * Makefile.in (SIM_OBJS): Add sim-load.o.
2334 * interp.c: #include bfd.h.
2335 (target_byte_order): Delete.
2336 (sim_kind, myname, big_endian_p): New static locals.
2337 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2338 after argument parsing. Recognize -E arg, set endianness accordingly.
2339 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2340 load file into simulator. Set PC from bfd.
2341 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2342 (set_endianness): Use big_endian_p instead of target_byte_order.
2343
2344Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2345
2346 * interp.c (sim_size): Delete prototype - conflicts with
2347 definition in remote-sim.h. Correct definition.
2348
2349Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2350
2351 * configure: Regenerated to track ../common/aclocal.m4 changes.
2352 * config.in: Ditto.
2353
2354Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2355
2356 * interp.c (sim_open): New arg `kind'.
2357
2358 * configure: Regenerated to track ../common/aclocal.m4 changes.
2359
2360Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2361
2362 * configure: Regenerated to track ../common/aclocal.m4 changes.
2363
2364Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2365
2366 * interp.c (sim_open): Set optind to 0 before calling getopt.
2367
2368Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2369
2370 * configure: Regenerated to track ../common/aclocal.m4 changes.
2371
2372Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2373
2374 * interp.c : Replace uses of pr_addr with pr_uword64
2375 where the bit length is always 64 independent of SIM_ADDR.
2376 (pr_uword64) : added.
2377
2378Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2379
2380 * configure: Re-generate.
2381
2382Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2383
2384 * configure: Regenerate to track ../common/aclocal.m4 changes.
2385
2386Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2387
2388 * interp.c (sim_open): New SIM_DESC result. Argument is now
2389 in argv form.
2390 (other sim_*): New SIM_DESC argument.
2391
2392Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2393
2394 * interp.c: Fix printing of addresses for non-64-bit targets.
2395 (pr_addr): Add function to print address based on size.
2396
2397Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2398
2399 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2400
2401Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2402
2403 * gencode.c (build_mips16_operands): Correct computation of base
2404 address for extended PC relative instruction.
2405
2406Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2407
2408 * interp.c (mips16_entry): Add support for floating point cases.
2409 (SignalException): Pass floating point cases to mips16_entry.
2410 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2411 registers.
2412 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2413 or fmt_word.
2414 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2415 and then set the state to fmt_uninterpreted.
2416 (COP_SW): Temporarily set the state to fmt_word while calling
2417 ValueFPR.
2418
2419Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2420
2421 * gencode.c (build_instruction): The high order may be set in the
2422 comparison flags at any ISA level, not just ISA 4.
2423
2424Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2425
2426 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2427 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2428 * configure.in: sinclude ../common/aclocal.m4.
2429 * configure: Regenerated.
2430
2431Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2432
2433 * configure: Rebuild after change to aclocal.m4.
2434
2435Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2436
2437 * configure configure.in Makefile.in: Update to new configure
2438 scheme which is more compatible with WinGDB builds.
2439 * configure.in: Improve comment on how to run autoconf.
2440 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2441 * Makefile.in: Use autoconf substitution to install common
2442 makefile fragment.
2443
2444Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2445
2446 * gencode.c (build_instruction): Use BigEndianCPU instead of
2447 ByteSwapMem.
2448
2449Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2450
2451 * interp.c (sim_monitor): Make output to stdout visible in
2452 wingdb's I/O log window.
2453
2454Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2455
2456 * support.h: Undo previous change to SIGTRAP
2457 and SIGQUIT values.
2458
2459Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2460
2461 * interp.c (store_word, load_word): New static functions.
2462 (mips16_entry): New static function.
2463 (SignalException): Look for mips16 entry and exit instructions.
2464 (simulate): Use the correct index when setting fpr_state after
2465 doing a pending move.
2466
2467Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2468
2469 * interp.c: Fix byte-swapping code throughout to work on
2470 both little- and big-endian hosts.
2471
2472Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2473
2474 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2475 with gdb/config/i386/xm-windows.h.
2476
2477Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2478
2479 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2480 that messes up arithmetic shifts.
2481
2482Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2483
2484 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2485 SIGTRAP and SIGQUIT for _WIN32.
2486
2487Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2488
2489 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2490 force a 64 bit multiplication.
2491 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2492 destination register is 0, since that is the default mips16 nop
2493 instruction.
2494
2495Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2496
2497 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2498 (build_endian_shift): Don't check proc64.
2499 (build_instruction): Always set memval to uword64. Cast op2 to
2500 uword64 when shifting it left in memory instructions. Always use
2501 the same code for stores--don't special case proc64.
2502
2503 * gencode.c (build_mips16_operands): Fix base PC value for PC
2504 relative operands.
2505 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2506 jal instruction.
2507 * interp.c (simJALDELAYSLOT): Define.
2508 (JALDELAYSLOT): Define.
2509 (INDELAYSLOT, INJALDELAYSLOT): Define.
2510 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2511
2512Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2513
2514 * interp.c (sim_open): add flush_cache as a PMON routine
2515 (sim_monitor): handle flush_cache by ignoring it
2516
2517Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2518
2519 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2520 BigEndianMem.
2521 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2522 (BigEndianMem): Rename to ByteSwapMem and change sense.
2523 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2524 BigEndianMem references to !ByteSwapMem.
2525 (set_endianness): New function, with prototype.
2526 (sim_open): Call set_endianness.
2527 (sim_info): Use simBE instead of BigEndianMem.
2528 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2529 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2530 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2531 ifdefs, keeping the prototype declaration.
2532 (swap_word): Rewrite correctly.
2533 (ColdReset): Delete references to CONFIG. Delete endianness related
2534 code; moved to set_endianness.
2535
2536Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2537
2538 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2539 * interp.c (CHECKHILO): Define away.
2540 (simSIGINT): New macro.
2541 (membank_size): Increase from 1MB to 2MB.
2542 (control_c): New function.
2543 (sim_resume): Rename parameter signal to signal_number. Add local
2544 variable prev. Call signal before and after simulate.
2545 (sim_stop_reason): Add simSIGINT support.
2546 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2547 functions always.
2548 (sim_warning): Delete call to SignalException. Do call printf_filtered
2549 if logfh is NULL.
2550 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2551 a call to sim_warning.
2552
2553Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2554
2555 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2556 16 bit instructions.
2557
2558Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2559
2560 Add support for mips16 (16 bit MIPS implementation):
2561 * gencode.c (inst_type): Add mips16 instruction encoding types.
2562 (GETDATASIZEINSN): Define.
2563 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2564 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2565 mtlo.
2566 (MIPS16_DECODE): New table, for mips16 instructions.
2567 (bitmap_val): New static function.
2568 (struct mips16_op): Define.
2569 (mips16_op_table): New table, for mips16 operands.
2570 (build_mips16_operands): New static function.
2571 (process_instructions): If PC is odd, decode a mips16
2572 instruction. Break out instruction handling into new
2573 build_instruction function.
2574 (build_instruction): New static function, broken out of
2575 process_instructions. Check modifiers rather than flags for SHIFT
2576 bit count and m[ft]{hi,lo} direction.
2577 (usage): Pass program name to fprintf.
2578 (main): Remove unused variable this_option_optind. Change
2579 ``*loptarg++'' to ``loptarg++''.
2580 (my_strtoul): Parenthesize && within ||.
2581 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2582 (simulate): If PC is odd, fetch a 16 bit instruction, and
2583 increment PC by 2 rather than 4.
2584 * configure.in: Add case for mips16*-*-*.
2585 * configure: Rebuild.
2586
2587Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2588
2589 * interp.c: Allow -t to enable tracing in standalone simulator.
2590 Fix garbage output in trace file and error messages.
2591
2592Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2593
2594 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2595 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2596 * configure.in: Simplify using macros in ../common/aclocal.m4.
2597 * configure: Regenerated.
2598 * tconfig.in: New file.
2599
2600Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2601
2602 * interp.c: Fix bugs in 64-bit port.
2603 Use ansi function declarations for msvc compiler.
2604 Initialize and test file pointer in trace code.
2605 Prevent duplicate definition of LAST_EMED_REGNUM.
2606
2607Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2608
2609 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2610
2611Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2612
2613 * interp.c (SignalException): Check for explicit terminating
2614 breakpoint value.
2615 * gencode.c: Pass instruction value through SignalException()
2616 calls for Trap, Breakpoint and Syscall.
2617
2618Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2619
2620 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2621 only used on those hosts that provide it.
2622 * configure.in: Add sqrt() to list of functions to be checked for.
2623 * config.in: Re-generated.
2624 * configure: Re-generated.
2625
2626Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2627
2628 * gencode.c (process_instructions): Call build_endian_shift when
2629 expanding STORE RIGHT, to fix swr.
2630 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2631 clear the high bits.
2632 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2633 Fix float to int conversions to produce signed values.
2634
2635Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2636
2637 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2638 (process_instructions): Correct handling of nor instruction.
2639 Correct shift count for 32 bit shift instructions. Correct sign
2640 extension for arithmetic shifts to not shift the number of bits in
2641 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2642 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2643 Fix madd.
2644 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2645 It's OK to have a mult follow a mult. What's not OK is to have a
2646 mult follow an mfhi.
2647 (Convert): Comment out incorrect rounding code.
2648
2649Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2650
2651 * interp.c (sim_monitor): Improved monitor printf
2652 simulation. Tidied up simulator warnings, and added "--log" option
2653 for directing warning message output.
2654 * gencode.c: Use sim_warning() rather than WARNING macro.
2655
2656Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2657
2658 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2659 getopt1.o, rather than on gencode.c. Link objects together.
2660 Don't link against -liberty.
2661 (gencode.o, getopt.o, getopt1.o): New targets.
2662 * gencode.c: Include <ctype.h> and "ansidecl.h".
2663 (AND): Undefine after including "ansidecl.h".
2664 (ULONG_MAX): Define if not defined.
2665 (OP_*): Don't define macros; now defined in opcode/mips.h.
2666 (main): Call my_strtoul rather than strtoul.
2667 (my_strtoul): New static function.
2668
2669Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2670
2671 * gencode.c (process_instructions): Generate word64 and uword64
2672 instead of `long long' and `unsigned long long' data types.
2673 * interp.c: #include sysdep.h to get signals, and define default
2674 for SIGBUS.
2675 * (Convert): Work around for Visual-C++ compiler bug with type
2676 conversion.
2677 * support.h: Make things compile under Visual-C++ by using
2678 __int64 instead of `long long'. Change many refs to long long
2679 into word64/uword64 typedefs.
2680
2681Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2682
2683 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2684 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2685 (docdir): Removed.
2686 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2687 (AC_PROG_INSTALL): Added.
2688 (AC_PROG_CC): Moved to before configure.host call.
2689 * configure: Rebuilt.
2690
2691Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2692
2693 * configure.in: Define @SIMCONF@ depending on mips target.
2694 * configure: Rebuild.
2695 * Makefile.in (run): Add @SIMCONF@ to control simulator
2696 construction.
2697 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2698 * interp.c: Remove some debugging, provide more detailed error
2699 messages, update memory accesses to use LOADDRMASK.
2700
2701Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2702
2703 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2704 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2705 stamp-h.
2706 * configure: Rebuild.
2707 * config.in: New file, generated by autoheader.
2708 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2709 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2710 HAVE_ANINT and HAVE_AINT, as appropriate.
2711 * Makefile.in (run): Use @LIBS@ rather than -lm.
2712 (interp.o): Depend upon config.h.
2713 (Makefile): Just rebuild Makefile.
2714 (clean): Remove stamp-h.
2715 (mostlyclean): Make the same as clean, not as distclean.
2716 (config.h, stamp-h): New targets.
2717
2718Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2719
2720 * interp.c (ColdReset): Fix boolean test. Make all simulator
2721 globals static.
2722
2723Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2724
2725 * interp.c (xfer_direct_word, xfer_direct_long,
2726 swap_direct_word, swap_direct_long, xfer_big_word,
2727 xfer_big_long, xfer_little_word, xfer_little_long,
2728 swap_word,swap_long): Added.
2729 * interp.c (ColdReset): Provide function indirection to
2730 host<->simulated_target transfer routines.
2731 * interp.c (sim_store_register, sim_fetch_register): Updated to
2732 make use of indirected transfer routines.
2733
2734Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2735
2736 * gencode.c (process_instructions): Ensure FP ABS instruction
2737 recognised.
2738 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2739 system call support.
2740
2741Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2742
2743 * interp.c (sim_do_command): Complain if callback structure not
2744 initialised.
2745
2746Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2747
2748 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2749 support for Sun hosts.
2750 * Makefile.in (gencode): Ensure the host compiler and libraries
2751 used for cross-hosted build.
2752
2753Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2754
2755 * interp.c, gencode.c: Some more (TODO) tidying.
2756
2757Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2758
2759 * gencode.c, interp.c: Replaced explicit long long references with
2760 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2761 * support.h (SET64LO, SET64HI): Macros added.
2762
2763Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2764
2765 * configure: Regenerate with autoconf 2.7.
2766
2767Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2768
2769 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2770 * support.h: Remove superfluous "1" from #if.
2771 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2772
2773Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2774
2775 * interp.c (StoreFPR): Control UndefinedResult() call on
2776 WARN_RESULT manifest.
2777
2778Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2779
2780 * gencode.c: Tidied instruction decoding, and added FP instruction
2781 support.
2782
2783 * interp.c: Added dineroIII, and BSD profiling support. Also
2784 run-time FP handling.
2785
2786Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2787
2788 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2789 gencode.c, interp.c, support.h: created.
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