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* som.c (som_set_reloc_info): Correct small typo.
[deliverable/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
1a27f959
CD		 12004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
2
3 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
4 from COP0_BADVADDR.
5 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
6
5dbb7b5a
CD		 72004-04-10 Chris Demetriou <cgd@broadcom.com>
8
9 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
10
14234056
CD		 112004-04-09 Chris Demetriou <cgd@broadcom.com>
12
13 * mips.igen (check_fmt): Remove.
14 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
15 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
16 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
17 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
18 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
19 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
20 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
21 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
22 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
23 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
24
c6f9085c
CD		 252004-04-09 Chris Demetriou <cgd@broadcom.com>
26
27 * sb1.igen (check_sbx): New function.
28 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
29
11d66e66 302004-03-29 Chris Demetriou <cgd@broadcom.com>
0e1b7197
RS		 31 Richard Sandiford <rsandifo@redhat.com>
32
33 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
34 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
35 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
36 separate implementations for mipsIV and mipsV. Use new macros to
37 determine whether the restrictions apply.
38
b3208fb8
CD		 392004-01-19 Chris Demetriou <cgd@broadcom.com>
40
41 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
42 (check_mult_hilo): Improve comments.
43 (check_div_hilo): Likewise. Also, fork off a new version
44 to handle mips32/mips64 (since there are no hazards to check
45 in MIPS32/MIPS64).
46
9a1d84fb
CD		 472003-06-17 Richard Sandiford <rsandifo@redhat.com>
48
49 * mips.igen (do_dmultx): Fix check for negative operands.
50
ae451ac6
ILT		 512003-05-16 Ian Lance Taylor <ian@airs.com>
52
53 * Makefile.in (SHELL): Make sure this is defined.
54 (various): Use $(SHELL) whenever we invoke move-if-change.
55
dd69d292
CD		 562003-05-03 Chris Demetriou <cgd@broadcom.com>
57
58 * cp1.c: Tweak attribution slightly.
59 * cp1.h: Likewise.
60 * mdmx.c: Likewise.
61 * mdmx.igen: Likewise.
62 * mips3d.igen: Likewise.
63 * sb1.igen: Likewise.
64
bcd0068e
CD		 652003-04-15 Richard Sandiford <rsandifo@redhat.com>
66
67 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
68 unsigned operands.
69
6b4a8935
AC		 702003-02-27 Andrew Cagney <cagney@redhat.com>
71
601da316
AC		 72 * interp.c (sim_open): Rename _bfd to bfd.
73 (sim_create_inferior): Ditto.
6b4a8935 74
d29e330f
CD		 752003-01-14 Chris Demetriou <cgd@broadcom.com>
76
77 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
78
a2353a08
CD		 792003-01-14 Chris Demetriou <cgd@broadcom.com>
80
81 * mips.igen (EI, DI): Remove.
82
80551777
CD		 832003-01-05 Richard Sandiford <rsandifo@redhat.com>
84
85 * Makefile.in (tmp-run-multi): Fix mips16 filter.
86
4c54fc26
CD		 872003-01-04 Richard Sandiford <rsandifo@redhat.com>
88 Andrew Cagney <ac131313@redhat.com>
89 Gavin Romig-Koch <gavin@redhat.com>
90 Graydon Hoare <graydon@redhat.com>
91 Aldy Hernandez <aldyh@redhat.com>
92 Dave Brolley <brolley@redhat.com>
93 Chris Demetriou <cgd@broadcom.com>
94
95 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
96 (sim_mach_default): New variable.
97 (mips64vr-*-*, mips64vrel-*-*): New configurations.
98 Add a new simulator generator, MULTI.
99 * configure: Regenerate.
100 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
101 (multi-run.o): New dependency.
102 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
103 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
104 (tmp-multi): Combine them.
105 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
106 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
107 (distclean-extra): New rule.
108 * sim-main.h: Include bfd.h.
109 (MIPS_MACH): New macro.
110 * mips.igen (vr4120, vr5400, vr5500): New models.
111 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
112 * vr.igen: Replace with new version.
113
e6c674b8
CD		 1142003-01-04 Chris Demetriou <cgd@broadcom.com>
115
116 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
117 * configure: Regenerate.
118
28f50ac8
CD		 1192002-12-31 Chris Demetriou <cgd@broadcom.com>
120
121 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
122 * mips.igen: Remove all invocations of check_branch_bug and
123 mark_branch_bug.
124
5071ffe6
CD		 1252002-12-16 Chris Demetriou <cgd@broadcom.com>
126
127 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
128
06e7837e
CD		 1292002-07-30 Chris Demetriou <cgd@broadcom.com>
130
131 * mips.igen (do_load_double, do_store_double): New functions.
132 (LDC1, SDC1): Rename to...
133 (LDC1b, SDC1b): respectively.
134 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
135
2265c243
MS		 1362002-07-29 Michael Snyder <msnyder@redhat.com>
137
138 * cp1.c (fp_recip2): Modify initialization expression so that
139 GCC will recognize it as constant.
140
a2f8b4f3
CD		 1412002-06-18 Chris Demetriou <cgd@broadcom.com>
142
143 * mdmx.c (SD_): Delete.
144 (Unpredictable): Re-define, for now, to directly invoke
145 unpredictable_action().
146 (mdmx_acc_op): Fix error in .ob immediate handling.
147
b4b6c939
AC		 1482002-06-18 Andrew Cagney <cagney@redhat.com>
149
150 * interp.c (sim_firmware_command): Initialize `address'.
151
c8cca39f
AC		 1522002-06-16 Andrew Cagney <ac131313@redhat.com>
153
154 * configure: Regenerated to track ../common/aclocal.m4 changes.
155
e7e81181
CD		 1562002-06-14 Chris Demetriou <cgd@broadcom.com>
157 Ed Satterthwaite <ehs@broadcom.com>
158
159 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
160 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
161 * mips.igen: Include mips3d.igen.
162 (mips3d): New model name for MIPS-3D ASE instructions.
163 (CVT.W.fmt): Don't use this instruction for word (source) format
164 instructions.
165 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
166 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
167 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
168 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
169 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
170 (RSquareRoot1, RSquareRoot2): New macros.
171 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
172 (fp_rsqrt2): New functions.
173 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
174 * configure: Regenerate.
175
3a2b820e 1762002-06-13 Chris Demetriou <cgd@broadcom.com>
eab54952 177 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 178
179 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
180 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
181 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
182 (convert): Note that this function is not used for paired-single
183 format conversions.
184 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
185 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
186 (check_fmt_p): Enable paired-single support.
187 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
188 (PUU.PS): New instructions.
189 (CVT.S.fmt): Don't use this instruction for paired-single format
190 destinations.
191 * sim-main.h (FP_formats): New value 'fmt_ps.'
192 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
193 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
194
d18ea9c2
CD		 1952002-06-12 Chris Demetriou <cgd@broadcom.com>
196
197 * mips.igen: Fix formatting of function calls in
198 many FP operations.
199
95fd5cee
CD		 2002002-06-12 Chris Demetriou <cgd@broadcom.com>
201
202 * mips.igen (MOVN, MOVZ): Trace result.
203 (TNEI): Print "tnei" as the opcode name in traces.
204 (CEIL.W): Add disassembly string for traces.
205 (RSQRT.fmt): Make location of disassembly string consistent
206 with other instructions.
207
4f0d55ae
CD		 2082002-06-12 Chris Demetriou <cgd@broadcom.com>
209
210 * mips.igen (X): Delete unused function.
211
3c25f8c7
AC		 2122002-06-08 Andrew Cagney <cagney@redhat.com>
213
214 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
215
f3c08b7e
CD		 2162002-06-07 Chris Demetriou <cgd@broadcom.com>
217 Ed Satterthwaite <ehs@broadcom.com>
218
219 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
220 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
221 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
222 (fp_nmsub): New prototypes.
223 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
224 (NegMultiplySub): New defines.
225 * mips.igen (RSQRT.fmt): Use RSquareRoot().
226 (MADD.D, MADD.S): Replace with...
227 (MADD.fmt): New instruction.
228 (MSUB.D, MSUB.S): Replace with...
229 (MSUB.fmt): New instruction.
230 (NMADD.D, NMADD.S): Replace with...
231 (NMADD.fmt): New instruction.
232 (NMSUB.D, MSUB.S): Replace with...
233 (NMSUB.fmt): New instruction.
234
52714ff9
CD		 2352002-06-07 Chris Demetriou <cgd@broadcom.com>
236 Ed Satterthwaite <ehs@broadcom.com>
237
238 * cp1.c: Fix more comment spelling and formatting.
239 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
240 (denorm_mode): New function.
241 (fpu_unary, fpu_binary): Round results after operation, collect
242 status from rounding operations, and update the FCSR.
243 (convert): Collect status from integer conversions and rounding
244 operations, and update the FCSR. Adjust NaN values that result
245 from conversions. Convert to use sim_io_eprintf rather than
246 fprintf, and remove some debugging code.
247 * cp1.h (fenr_FS): New define.
248
577d8c4b
CD		 2492002-06-07 Chris Demetriou <cgd@broadcom.com>
250
251 * cp1.c (convert): Remove unusable debugging code, and move MIPS
252 rounding mode to sim FP rounding mode flag conversion code into...
253 (rounding_mode): New function.
254
196496ed
CD		 2552002-06-07 Chris Demetriou <cgd@broadcom.com>
256
257 * cp1.c: Clean up formatting of a few comments.
258 (value_fpr): Reformat switch statement.
259
cfe9ea23
CD		 2602002-06-06 Chris Demetriou <cgd@broadcom.com>
261 Ed Satterthwaite <ehs@broadcom.com>
262
263 * cp1.h: New file.
264 * sim-main.h: Include cp1.h.
265 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
266 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
267 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
268 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
269 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
270 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
271 * cp1.c: Don't include sim-fpu.h; already included by
272 sim-main.h. Clean up formatting of some comments.
273 (NaN, Equal, Less): Remove.
274 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
275 (fp_cmp): New functions.
276 * mips.igen (do_c_cond_fmt): Remove.
277 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
278 Compare. Add result tracing.
279 (CxC1): Remove, replace with...
280 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
281 (DMxC1): Remove, replace with...
282 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
283 (MxC1): Remove, replace with...
284 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
285
ee7254b0
CD		 2862002-06-04 Chris Demetriou <cgd@broadcom.com>
287
288 * sim-main.h (FGRIDX): Remove, replace all uses with...
289 (FGR_BASE): New macro.
290 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
291 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
292 (NR_FGR, FGR): Likewise.
293 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
294 * mips.igen: Likewise.
295
d3eb724f
CD		 2962002-06-04 Chris Demetriou <cgd@broadcom.com>
297
298 * cp1.c: Add an FSF Copyright notice to this file.
299
ba46ddd0
CD		 3002002-06-04 Chris Demetriou <cgd@broadcom.com>
301 Ed Satterthwaite <ehs@broadcom.com>
302
303 * cp1.c (Infinity): Remove.
304 * sim-main.h (Infinity): Likewise.
305
306 * cp1.c (fp_unary, fp_binary): New functions.
307 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
308 (fp_sqrt): New functions, implemented in terms of the above.
309 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
310 (Recip, SquareRoot): Remove (replaced by functions above).
311 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
312 (fp_recip, fp_sqrt): New prototypes.
313 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
314 (Recip, SquareRoot): Replace prototypes with #defines which
315 invoke the functions above.
316
18d8a52d
CD		 3172002-06-03 Chris Demetriou <cgd@broadcom.com>
318
319 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
320 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
321 file, remove PARAMS from prototypes.
322 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
323 simulator state arguments.
324 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
325 pass simulator state arguments.
326 * cp1.c (SD): Redefine as CPU_STATE(cpu).
327 (store_fpr, convert): Remove 'sd' argument.
328 (value_fpr): Likewise. Convert to use 'SD' instead.
329
0f154cbd
CD		 3302002-06-03 Chris Demetriou <cgd@broadcom.com>
331
332 * cp1.c (Min, Max): Remove #if 0'd functions.
333 * sim-main.h (Min, Max): Remove.
334
e80fc152
CD		 3352002-06-03 Chris Demetriou <cgd@broadcom.com>
336
337 * cp1.c: fix formatting of switch case and default labels.
338 * interp.c: Likewise.
339 * sim-main.c: Likewise.
340
bad673a9
CD		 3412002-06-03 Chris Demetriou <cgd@broadcom.com>
342
343 * cp1.c: Clean up comments which describe FP formats.
344 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
345
7cbea089
CD		 3462002-06-03 Chris Demetriou <cgd@broadcom.com>
347 Ed Satterthwaite <ehs@broadcom.com>
348
349 * configure.in (mipsisa64sb1*-*-*): New target for supporting
350 Broadcom SiByte SB-1 processor configurations.
351 * configure: Regenerate.
352 * sb1.igen: New file.
353 * mips.igen: Include sb1.igen.
354 (sb1): New model.
355 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
356 * mdmx.igen: Add "sb1" model to all appropriate functions and
357 instructions.
358 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
359 (ob_func, ob_acc): Reference the above.
360 (qh_acc): Adjust to keep the same size as ob_acc.
361 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
362 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
363
909daa82
CD		 3642002-06-03 Chris Demetriou <cgd@broadcom.com>
365
366 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
367
f4f1b9f1
CD		 3682002-06-02 Chris Demetriou <cgd@broadcom.com>
369 Ed Satterthwaite <ehs@broadcom.com>
370
371 * mips.igen (mdmx): New (pseudo-)model.
372 * mdmx.c, mdmx.igen: New files.
373 * Makefile.in (SIM_OBJS): Add mdmx.o.
374 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
375 New typedefs.
376 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
377 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
378 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
379 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
380 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
381 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
382 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
383 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
384 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
385 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
386 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
387 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
388 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
389 (qh_fmtsel): New macros.
390 (_sim_cpu): New member "acc".
391 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
392 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
393
5accf1ff
CD		 3942002-05-01 Chris Demetriou <cgd@broadcom.com>
395
396 * interp.c: Use 'deprecated' rather than 'depreciated.'
397 * sim-main.h: Likewise.
398
402586aa
CD		 3992002-05-01 Chris Demetriou <cgd@broadcom.com>
400
401 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
402 which wouldn't compile anyway.
403 * sim-main.h (unpredictable_action): New function prototype.
404 (Unpredictable): Define to call igen function unpredictable().
405 (NotWordValue): New macro to call igen function not_word_value().
406 (UndefinedResult): Remove.
407 * interp.c (undefined_result): Remove.
408 (unpredictable_action): New function.
409 * mips.igen (not_word_value, unpredictable): New functions.
410 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
411 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
412 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
413 NotWordValue() to check for unpredictable inputs, then
414 Unpredictable() to handle them.
415
c9b9995a
CD		 4162002-02-24 Chris Demetriou <cgd@broadcom.com>
417
418 * mips.igen: Fix formatting of calls to Unpredictable().
419
e1015982
AC		 4202002-04-20 Andrew Cagney <ac131313@redhat.com>
421
422 * interp.c (sim_open): Revert previous change.
423
b882a66b
AO		 4242002-04-18 Alexandre Oliva <aoliva@redhat.com>
425
426 * interp.c (sim_open): Disable chunk of code that wrote code in
427 vector table entries.
428
c429b7dd
CD		 4292002-03-19 Chris Demetriou <cgd@broadcom.com>
430
431 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
432 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
433 unused definitions.
434
37d146fa
CD		 4352002-03-19 Chris Demetriou <cgd@broadcom.com>
436
437 * cp1.c: Fix many formatting issues.
438
07892c0b
CD		 4392002-03-19 Chris G. Demetriou <cgd@broadcom.com>
440
441 * cp1.c (fpu_format_name): New function to replace...
442 (DOFMT): This. Delete, and update all callers.
443 (fpu_rounding_mode_name): New function to replace...
444 (RMMODE): This. Delete, and update all callers.
445
487f79b7
CD		 4462002-03-19 Chris G. Demetriou <cgd@broadcom.com>
447
448 * interp.c: Move FPU support routines from here to...
449 * cp1.c: Here. New file.
450 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
451 (cp1.o): New target.
452
1e799e28
CD		 4532002-03-12 Chris Demetriou <cgd@broadcom.com>
454
455 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
456 * mips.igen (mips32, mips64): New models, add to all instructions
457 and functions as appropriate.
458 (loadstore_ea, check_u64): New variant for model mips64.
459 (check_fmt_p): New variant for models mipsV and mips64, remove
460 mipsV model marking fro other variant.
461 (SLL) Rename to...
462 (SLLa) this.
463 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
464 for mips32 and mips64.
465 (DCLO, DCLZ): New instructions for mips64.
466
82f728db
CD		 4672002-03-07 Chris Demetriou <cgd@broadcom.com>
468
469 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
470 immediate or code as a hex value with the "%#lx" format.
471 (ANDI): Likewise, and fix printed instruction name.
472
b96e7ef1
CD		 4732002-03-05 Chris Demetriou <cgd@broadcom.com>
474
475 * sim-main.h (UndefinedResult, Unpredictable): New macros
476 which currently do nothing.
477
d35d4f70
CD		 4782002-03-05 Chris Demetriou <cgd@broadcom.com>
479
480 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
481 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
482 (status_CU3): New definitions.
483
484 * sim-main.h (ExceptionCause): Add new values for MIPS32
485 and MIPS64: MDMX, MCheck, CacheErr. Update comments
486 for DebugBreakPoint and NMIReset to note their status in
487 MIPS32 and MIPS64.
488 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
489 (SignalExceptionCacheErr): New exception macros.
490
3ad6f714
CD		 4912002-03-05 Chris Demetriou <cgd@broadcom.com>
492
493 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
494 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
495 is always enabled.
496 (SignalExceptionCoProcessorUnusable): Take as argument the
497 unusable coprocessor number.
498
86b77b47
CD		 4992002-03-05 Chris Demetriou <cgd@broadcom.com>
500
501 * mips.igen: Fix formatting of all SignalException calls.
502
97a88e93 5032002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 504
505 * sim-main.h (SIGNEXTEND): Remove.
506
97a88e93 5072002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 508
509 * mips.igen: Remove gencode comment from top of file, fix
510 spelling in another comment.
511
97a88e93 5122002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 513
514 * mips.igen (check_fmt, check_fmt_p): New functions to check
515 whether specific floating point formats are usable.
516 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
517 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
518 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
519 Use the new functions.
520 (do_c_cond_fmt): Remove format checks...
521 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
522
97a88e93 5232002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 524
525 * mips.igen: Fix formatting of check_fpu calls.
526
41774c9d
CD		 5272002-03-03 Chris Demetriou <cgd@broadcom.com>
528
529 * mips.igen (FLOOR.L.fmt): Store correct destination register.
530
4a0bd876
CD		 5312002-03-03 Chris Demetriou <cgd@broadcom.com>
532
533 * mips.igen: Remove whitespace at end of lines.
534
09297648
CD		 5352002-03-02 Chris Demetriou <cgd@broadcom.com>
536
537 * mips.igen (loadstore_ea): New function to do effective
538 address calculations.
539 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
540 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
541 CACHE): Use loadstore_ea to do effective address computations.
542
043b7057
CD		 5432002-03-02 Chris Demetriou <cgd@broadcom.com>
544
545 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
546 * mips.igen (LL, CxC1, MxC1): Likewise.
547
c1e8ada4
CD		 5482002-03-02 Chris Demetriou <cgd@broadcom.com>
549
550 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
551 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
552 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
553 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
554 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
555 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
556 Don't split opcode fields by hand, use the opcode field values
557 provided by igen.
558
3e1dca16
CD		 5592002-03-01 Chris Demetriou <cgd@broadcom.com>
560
561 * mips.igen (do_divu): Fix spacing.
562
563 * mips.igen (do_dsllv): Move to be right before DSLLV,
564 to match the rest of the do_<shift> functions.
565
fff8d27d
CD		 5662002-03-01 Chris Demetriou <cgd@broadcom.com>
567
568 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
569 DSRL32, do_dsrlv): Trace inputs and results.
570
0d3e762b
CD		 5712002-03-01 Chris Demetriou <cgd@broadcom.com>
572
573 * mips.igen (CACHE): Provide instruction-printing string.
574
575 * interp.c (signal_exception): Comment tokens after #endif.
576
eb5fcf93
CD		 5772002-02-28 Chris Demetriou <cgd@broadcom.com>
578
579 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
580 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
581 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
582 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
583 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
584 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
585 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
586 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
587
bb22bd7d
CD		 5882002-02-28 Chris Demetriou <cgd@broadcom.com>
589
590 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
591 instruction-printing string.
592 (LWU): Use '64' as the filter flag.
593
91a177cf
CD		 5942002-02-28 Chris Demetriou <cgd@broadcom.com>
595
596 * mips.igen (SDXC1): Fix instruction-printing string.
597
387f484a
CD		 5982002-02-28 Chris Demetriou <cgd@broadcom.com>
599
600 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
601 filter flags "32,f".
602
3d81f391
CD		 6032002-02-27 Chris Demetriou <cgd@broadcom.com>
604
605 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
606 as the filter flag.
607
af5107af
CD		 6082002-02-27 Chris Demetriou <cgd@broadcom.com>
609
610 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
611 add a comma) so that it more closely match the MIPS ISA
612 documentation opcode partitioning.
613 (PREF): Put useful names on opcode fields, and include
614 instruction-printing string.
615
ca971540
CD		 6162002-02-27 Chris Demetriou <cgd@broadcom.com>
617
618 * mips.igen (check_u64): New function which in the future will
619 check whether 64-bit instructions are usable and signal an
620 exception if not. Currently a no-op.
621 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
622 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
623 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
624 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
625
626 * mips.igen (check_fpu): New function which in the future will
627 check whether FPU instructions are usable and signal an exception
628 if not. Currently a no-op.
629 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
630 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
631 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
632 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
633 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
634 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
635 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
636 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
637
1c47a468
CD		 6382002-02-27 Chris Demetriou <cgd@broadcom.com>
639
640 * mips.igen (do_load_left, do_load_right): Move to be immediately
641 following do_load.
642 (do_store_left, do_store_right): Move to be immediately following
643 do_store.
644
603a98e7
CD		 6452002-02-27 Chris Demetriou <cgd@broadcom.com>
646
647 * mips.igen (mipsV): New model name. Also, add it to
648 all instructions and functions where it is appropriate.
649
c5d00cc7
CD		 6502002-02-18 Chris Demetriou <cgd@broadcom.com>
651
652 * mips.igen: For all functions and instructions, list model
653 names that support that instruction one per line.
654
074e9cb8
CD		 6552002-02-11 Chris Demetriou <cgd@broadcom.com>
656
657 * mips.igen: Add some additional comments about supported
658 models, and about which instructions go where.
659 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
660 order as is used in the rest of the file.
661
9805e229
CD		 6622002-02-11 Chris Demetriou <cgd@broadcom.com>
663
664 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
665 indicating that ALU32_END or ALU64_END are there to check
666 for overflow.
667 (DADD): Likewise, but also remove previous comment about
668 overflow checking.
669
f701dad2
CD		 6702002-02-10 Chris Demetriou <cgd@broadcom.com>
671
672 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
673 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
674 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
675 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
676 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
677 fields (i.e., add and move commas) so that they more closely
678 match the MIPS ISA documentation opcode partitioning.
679
6802002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098
CD		 681
682 * mips.igen (ADDI): Print immediate value.
683 (BREAK): Print code.
684 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
685 (SLL): Print "nop" specially, and don't run the code
686 that does the shift for the "nop" case.
687
9e52972e
FF		 6882001-11-17 Fred Fish <fnf@redhat.com>
689
690 * sim-main.h (float_operation): Move enum declaration outside
691 of _sim_cpu struct declaration.
692
c0efbca4
JB		 6932001-04-12 Jim Blandy <jimb@redhat.com>
694
695 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
696 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
697 set of the FCSR.
698 * sim-main.h (COCIDX): Remove definition; this isn't supported by
699 PENDING_FILL, and you can get the intended effect gracefully by
700 calling PENDING_SCHED directly.
701
fb891446
BE		 7022001-02-23 Ben Elliston <bje@redhat.com>
703
704 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
705 already defined elsewhere.
706
8030f857
BE		 7072001-02-19 Ben Elliston <bje@redhat.com>
708
709 * sim-main.h (sim_monitor): Return an int.
710 * interp.c (sim_monitor): Add return values.
711 (signal_exception): Handle error conditions from sim_monitor.
712
56b48a7a
CD		 7132001-02-08 Ben Elliston <bje@redhat.com>
714
715 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
716 (store_memory): Likewise, pass cia to sim_core_write*.
717
d3ee60d9
FCE		 7182000-10-19 Frank Ch. Eigler <fche@redhat.com>
719
720 On advice from Chris G. Demetriou <cgd@sibyte.com>:
721 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
722
071da002
AC		 723Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
724
725 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
726 * Makefile.in: Don't delete *.igen when cleaning directory.
727
a28c02cd
AC		 728Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
729
730 * m16.igen (break): Call SignalException not sim_engine_halt.
731
80ee11fa
AC		 732Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
733
734 From Jason Eckhardt:
735 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
736
673388c0
AC		 737Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
738
739 * mips.igen (MxC1, DMxC1): Fix printf formatting.
740
4c0deff4
NC		 7412000-05-24 Michael Hayes <mhayes@cygnus.com>
742
743 * mips.igen (do_dmultx): Fix typo.
744
eb2d80b4
AC		 745Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
746
747 * configure: Regenerated to track ../common/aclocal.m4 changes.
748
dd37a34b
AC		 749Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
750
751 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
752
4c0deff4
NC		 7532000-04-12 Frank Ch. Eigler <fche@redhat.com>
754
755 * sim-main.h (GPR_CLEAR): Define macro.
756
e30db738
AC		 757Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
758
759 * interp.c (decode_coproc): Output long using %lx and not %s.
760
cb7450ea
FCE		 7612000-03-21 Frank Ch. Eigler <fche@redhat.com>
762
763 * interp.c (sim_open): Sort & extend dummy memory regions for
764 --board=jmr3904 for eCos.
765
a3027dd7
FCE		 7662000-03-02 Frank Ch. Eigler <fche@redhat.com>
767
768 * configure: Regenerated.
769
770Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
771
772 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
773 calls, conditional on the simulator being in verbose mode.
774
dfcd3bfb
JM		 775Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
776
777 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
778 cache don't get ReservedInstruction traps.
779
c2d11a7d
JM		 7801999-11-29 Mark Salter <msalter@cygnus.com>
781
782 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
783 to clear status bits in sdisr register. This is how the hardware works.
784
785 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
786 being used by cygmon.
787
4ce44c66
JM		 7881999-11-11 Andrew Haley <aph@cygnus.com>
789
790 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
791 instructions.
792
cff3e48b
JM		 793Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
794
795 * mips.igen (MULT): Correct previous mis-applied patch.
796
d4f3574e
SS		 797Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
798
799 * mips.igen (delayslot32): Handle sequence like
800 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
801 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
802 (MULT): Actually pass the third register...
803
8041999-09-03 Mark Salter <msalter@cygnus.com>
805
806 * interp.c (sim_open): Added more memory aliases for additional
807 hardware being touched by cygmon on jmr3904 board.
808
809Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
810
811 * configure: Regenerated to track ../common/aclocal.m4 changes.
812
a0b3c4fd
JM		 813Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
814
815 * interp.c (sim_store_register): Handle case where client - GDB -
816 specifies that a 4 byte register is 8 bytes in size.
817 (sim_fetch_register): Ditto.
818
adf40b2e
JM		 8191999-07-14 Frank Ch. Eigler <fche@cygnus.com>
820
821 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
822 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
823 (idt_monitor_base): Base address for IDT monitor traps.
824 (pmon_monitor_base): Ditto for PMON.
825 (lsipmon_monitor_base): Ditto for LSI PMON.
826 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
827 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
828 (sim_firmware_command): New function.
829 (mips_option_handler): Call it for OPTION_FIRMWARE.
830 (sim_open): Allocate memory for idt_monitor region. If "--board"
831 option was given, add no monitor by default. Add BREAK hooks only if
832 monitors are also there.
833
43e526b9
JM		 834Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
835
836 * interp.c (sim_monitor): Flush output before reading input.
837
838Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
839
840 * tconfig.in (SIM_HANDLES_LMA): Always define.
841
842Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
843
844 From Mark Salter <msalter@cygnus.com>:
845 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
846 (sim_open): Add setup for BSP board.
847
9846de1b
JM		 848Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
849
850 * mips.igen (MULT, MULTU): Add syntax for two operand version.
851 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
852 them as unimplemented.
853
cd0fc7c3
SS		 8541999-05-08 Felix Lee <flee@cygnus.com>
855
856 * configure: Regenerated to track ../common/aclocal.m4 changes.
857
7a292a7a
SS		 8581999-04-21 Frank Ch. Eigler <fche@cygnus.com>
859
860 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
861
862Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
863
864 * configure.in: Any mips64vr5*-*-* target should have
865 -DTARGET_ENABLE_FR=1.
866 (default_endian): Any mips64vr*el-*-* target should default to
867 LITTLE_ENDIAN.
868 * configure: Re-generate.
869
8701999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
871
872 * mips.igen (ldl): Extend from _16_, not 32.
873
874Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
875
876 * interp.c (sim_store_register): Force registers written to by GDB
877 into an un-interpreted state.
878
c906108c
SS		 8791999-02-05 Frank Ch. Eigler <fche@cygnus.com>
880
881 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
882 CPU, start periodic background I/O polls.
883 (tx3904sio_poll): New function: periodic I/O poller.
884
8851998-12-30 Frank Ch. Eigler <fche@cygnus.com>
886
887 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
888
889Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
890
891 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
892 case statement.
893
8941998-12-29 Frank Ch. Eigler <fche@cygnus.com>
895
896 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
897 (load_word): Call SIM_CORE_SIGNAL hook on error.
898 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
899 starting. For exception dispatching, pass PC instead of NULL_CIA.
900 (decode_coproc): Use COP0_BADVADDR to store faulting address.
901 * sim-main.h (COP0_BADVADDR): Define.
902 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
903 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
904 (_sim_cpu): Add exc_* fields to store register value snapshots.
905 * mips.igen (*): Replace memory-related SignalException* calls
906 with references to SIM_CORE_SIGNAL hook.
907
908 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
909 fix.
910 * sim-main.c (*): Minor warning cleanups.
911
9121998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
913
914 * m16.igen (DADDIU5): Correct type-o.
915
916Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
917
918 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
919 variables.
920
921Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
922
923 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
924 to include path.
925 (interp.o): Add dependency on itable.h
926 (oengine.c, gencode): Delete remaining references.
927 (BUILT_SRC_FROM_GEN): Clean up.
928
9291998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
930
931 * vr4run.c: New.
932 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
933 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
934 tmp-run-hack) : New.
935 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
936 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
937 Drop the "64" qualifier to get the HACK generator working.
938 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
939 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
940 qualifier to get the hack generator working.
941 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
942 (DSLL): Use do_dsll.
943 (DSLLV): Use do_dsllv.
944 (DSRA): Use do_dsra.
945 (DSRL): Use do_dsrl.
946 (DSRLV): Use do_dsrlv.
947 (BC1): Move *vr4100 to get the HACK generator working.
948 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
949 get the HACK generator working.
950 (MACC) Rename to get the HACK generator working.
951 (DMACC,MACCS,DMACCS): Add the 64.
952
9531998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
954
955 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
956 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
957
9581998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
959
960 * mips/interp.c (DEBUG): Cleanups.
961
9621998-12-10 Frank Ch. Eigler <fche@cygnus.com>
963
964 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
965 (tx3904sio_tickle): fflush after a stdout character output.
966
9671998-12-03 Frank Ch. Eigler <fche@cygnus.com>
968
969 * interp.c (sim_close): Uninstall modules.
970
971Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
972
973 * sim-main.h, interp.c (sim_monitor): Change to global
974 function.
975
976Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
977
978 * configure.in (vr4100): Only include vr4100 instructions in
979 simulator.
980 * configure: Re-generate.
981 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
982
983Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
984
985 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
986 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
987 true alternative.
988
989 * configure.in (sim_default_gen, sim_use_gen): Replace with
990 sim_gen.
991 (--enable-sim-igen): Delete config option. Always using IGEN.
992 * configure: Re-generate.
993
994 * Makefile.in (gencode): Kill, kill, kill.
995 * gencode.c: Ditto.
996
997Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
998
999 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1000 bit mips16 igen simulator.
1001 * configure: Re-generate.
1002
1003 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1004 as part of vr4100 ISA.
1005 * vr.igen: Mark all instructions as 64 bit only.
1006
1007Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1008
1009 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1010 Pacify GCC.
1011
1012Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1013
1014 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1015 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1016 * configure: Re-generate.
1017
1018 * m16.igen (BREAK): Define breakpoint instruction.
1019 (JALX32): Mark instruction as mips16 and not r3900.
1020 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1021
1022 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1023
1024Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1025
1026 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1027 insn as a debug breakpoint.
1028
1029 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1030 pending.slot_size.
1031 (PENDING_SCHED): Clean up trace statement.
1032 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1033 (PENDING_FILL): Delay write by only one cycle.
1034 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1035
1036 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1037 of pending writes.
1038 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1039 32 & 64.
1040 (pending_tick): Move incrementing of index to FOR statement.
1041 (pending_tick): Only update PENDING_OUT after a write has occured.
1042
1043 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1044 build simulator.
1045 * configure: Re-generate.
1046
1047 * interp.c (sim_engine_run OLD): Delete explicit call to
1048 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1049
1050Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1051
1052 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1053 interrupt level number to match changed SignalExceptionInterrupt
1054 macro.
1055
1056Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1057
1058 * interp.c: #include "itable.h" if WITH_IGEN.
1059 (get_insn_name): New function.
1060 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1061 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1062
1063Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1064
1065 * configure: Rebuilt to inhale new common/aclocal.m4.
1066
1067Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1068
1069 * dv-tx3904sio.c: Include sim-assert.h.
1070
1071Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1072
1073 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1074 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1075 Reorganize target-specific sim-hardware checks.
1076 * configure: rebuilt.
1077 * interp.c (sim_open): For tx39 target boards, set
1078 OPERATING_ENVIRONMENT, add tx3904sio devices.
1079 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1080 ROM executables. Install dv-sockser into sim-modules list.
1081
1082 * dv-tx3904irc.c: Compiler warning clean-up.
1083 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1084 frequent hw-trace messages.
1085
1086Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1087
1088 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1089
1090Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1091
1092 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1093
1094 * vr.igen: New file.
1095 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1096 * mips.igen: Define vr4100 model. Include vr.igen.
1097Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1098
1099 * mips.igen (check_mf_hilo): Correct check.
1100
1101Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1102
1103 * sim-main.h (interrupt_event): Add prototype.
1104
1105 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1106 register_ptr, register_value.
1107 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1108
1109 * sim-main.h (tracefh): Make extern.
1110
1111Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1112
1113 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1114 Reduce unnecessarily high timer event frequency.
1115 * dv-tx3904cpu.c: Ditto for interrupt event.
1116
1117Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1118
1119 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1120 to allay warnings.
1121 (interrupt_event): Made non-static.
1122
1123 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1124 interchange of configuration values for external vs. internal
1125 clock dividers.
1126
1127Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1128
1129 * mips.igen (BREAK): Moved code to here for
1130 simulator-reserved break instructions.
1131 * gencode.c (build_instruction): Ditto.
1132 * interp.c (signal_exception): Code moved from here. Non-
1133 reserved instructions now use exception vector, rather
1134 than halting sim.
1135 * sim-main.h: Moved magic constants to here.
1136
1137Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1138
1139 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1140 register upon non-zero interrupt event level, clear upon zero
1141 event value.
1142 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1143 by passing zero event value.
1144 (*_io_{read,write}_buffer): Endianness fixes.
1145 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1146 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1147
1148 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1149 serial I/O and timer module at base address 0xFFFF0000.
1150
1151Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1152
1153 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1154 and BigEndianCPU.
1155
1156Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1157
1158 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1159 parts.
1160 * configure: Update.
1161
1162Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1163
1164 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1165 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1166 * configure.in: Include tx3904tmr in hw_device list.
1167 * configure: Rebuilt.
1168 * interp.c (sim_open): Instantiate three timer instances.
1169 Fix address typo of tx3904irc instance.
1170
1171Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1172
1173 * interp.c (signal_exception): SystemCall exception now uses
1174 the exception vector.
1175
1176Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1177
1178 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1179 to allay warnings.
1180
1181Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1182
1183 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1184
1185Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1186
1187 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1188
1189 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1190 sim-main.h. Declare a struct hw_descriptor instead of struct
1191 hw_device_descriptor.
1192
1193Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1194
1195 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1196 right bits and then re-align left hand bytes to correct byte
1197 lanes. Fix incorrect computation in do_store_left when loading
1198 bytes from second word.
1199
1200Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1201
1202 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1203 * interp.c (sim_open): Only create a device tree when HW is
1204 enabled.
1205
1206 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1207 * interp.c (signal_exception): Ditto.
1208
1209Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1210
1211 * gencode.c: Mark BEGEZALL as LIKELY.
1212
1213Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1214
1215 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1216 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1217
1218Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1219
1220 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1221 modules. Recognize TX39 target with "mips*tx39" pattern.
1222 * configure: Rebuilt.
1223 * sim-main.h (*): Added many macros defining bits in
1224 TX39 control registers.
1225 (SignalInterrupt): Send actual PC instead of NULL.
1226 (SignalNMIReset): New exception type.
1227 * interp.c (board): New variable for future use to identify
1228 a particular board being simulated.
1229 (mips_option_handler,mips_options): Added "--board" option.
1230 (interrupt_event): Send actual PC.
1231 (sim_open): Make memory layout conditional on board setting.
1232 (signal_exception): Initial implementation of hardware interrupt
1233 handling. Accept another break instruction variant for simulator
1234 exit.
1235 (decode_coproc): Implement RFE instruction for TX39.
1236 (mips.igen): Decode RFE instruction as such.
1237 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1238 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1239 bbegin to implement memory map.
1240 * dv-tx3904cpu.c: New file.
1241 * dv-tx3904irc.c: New file.
1242
1243Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1244
1245 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1246
1247Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1248
1249 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1250 with calls to check_div_hilo.
1251
1252Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1253
1254 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1255 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1256 Add special r3900 version of do_mult_hilo.
1257 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1258 with calls to check_mult_hilo.
1259 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1260 with calls to check_div_hilo.
1261
1262Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1263
1264 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1265 Document a replacement.
1266
1267Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1268
1269 * interp.c (sim_monitor): Make mon_printf work.
1270
1271Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1272
1273 * sim-main.h (INSN_NAME): New arg `cpu'.
1274
1275Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1276
1277 * configure: Regenerated to track ../common/aclocal.m4 changes.
1278
1279Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1280
1281 * configure: Regenerated to track ../common/aclocal.m4 changes.
1282 * config.in: Ditto.
1283
1284Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1285
1286 * acconfig.h: New file.
1287 * configure.in: Reverted change of Apr 24; use sinclude again.
1288
1289Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1290
1291 * configure: Regenerated to track ../common/aclocal.m4 changes.
1292 * config.in: Ditto.
1293
1294Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1295
1296 * configure.in: Don't call sinclude.
1297
1298Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1299
1300 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1301
1302Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1303
1304 * mips.igen (ERET): Implement.
1305
1306 * interp.c (decode_coproc): Return sign-extended EPC.
1307
1308 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1309
1310 * interp.c (signal_exception): Do not ignore Trap.
1311 (signal_exception): On TRAP, restart at exception address.
1312 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1313 (signal_exception): Update.
1314 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1315 so that TRAP instructions are caught.
1316
1317Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1318
1319 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1320 contains HI/LO access history.
1321 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1322 (HIACCESS, LOACCESS): Delete, replace with
1323 (HIHISTORY, LOHISTORY): New macros.
1324 (CHECKHILO): Delete all, moved to mips.igen
1325
1326 * gencode.c (build_instruction): Do not generate checks for
1327 correct HI/LO register usage.
1328
1329 * interp.c (old_engine_run): Delete checks for correct HI/LO
1330 register usage.
1331
1332 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1333 check_mf_cycles): New functions.
1334 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1335 do_divu, domultx, do_mult, do_multu): Use.
1336
1337 * tx.igen ("madd", "maddu"): Use.
1338
1339Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1340
1341 * mips.igen (DSRAV): Use function do_dsrav.
1342 (SRAV): Use new function do_srav.
1343
1344 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1345 (B): Sign extend 11 bit immediate.
1346 (EXT-B*): Shift 16 bit immediate left by 1.
1347 (ADDIU*): Don't sign extend immediate value.
1348
1349Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1350
1351 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1352
1353 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1354 functions.
1355
1356 * mips.igen (delayslot32, nullify_next_insn): New functions.
1357 (m16.igen): Always include.
1358 (do_*): Add more tracing.
1359
1360 * m16.igen (delayslot16): Add NIA argument, could be called by a
1361 32 bit MIPS16 instruction.
1362
1363 * interp.c (ifetch16): Move function from here.
1364 * sim-main.c (ifetch16): To here.
1365
1366 * sim-main.c (ifetch16, ifetch32): Update to match current
1367 implementations of LH, LW.
1368 (signal_exception): Don't print out incorrect hex value of illegal
1369 instruction.
1370
1371Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1372
1373 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1374 instruction.
1375
1376 * m16.igen: Implement MIPS16 instructions.
1377
1378 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1379 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1380 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1381 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1382 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1383 bodies of corresponding code from 32 bit insn to these. Also used
1384 by MIPS16 versions of functions.
1385
1386 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1387 (IMEM16): Drop NR argument from macro.
1388
1389Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1390
1391 * Makefile.in (SIM_OBJS): Add sim-main.o.
1392
1393 * sim-main.h (address_translation, load_memory, store_memory,
1394 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1395 as INLINE_SIM_MAIN.
1396 (pr_addr, pr_uword64): Declare.
1397 (sim-main.c): Include when H_REVEALS_MODULE_P.
1398
1399 * interp.c (address_translation, load_memory, store_memory,
1400 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1401 from here.
1402 * sim-main.c: To here. Fix compilation problems.
1403
1404 * configure.in: Enable inlining.
1405 * configure: Re-config.
1406
1407Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1408
1409 * configure: Regenerated to track ../common/aclocal.m4 changes.
1410
1411Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1412
1413 * mips.igen: Include tx.igen.
1414 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1415 * tx.igen: New file, contains MADD and MADDU.
1416
1417 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1418 the hardwired constant `7'.
1419 (store_memory): Ditto.
1420 (LOADDRMASK): Move definition to sim-main.h.
1421
1422 mips.igen (MTC0): Enable for r3900.
1423 (ADDU): Add trace.
1424
1425 mips.igen (do_load_byte): Delete.
1426 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1427 do_store_right): New functions.
1428 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1429
1430 configure.in: Let the tx39 use igen again.
1431 configure: Update.
1432
1433Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1434
1435 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1436 not an address sized quantity. Return zero for cache sizes.
1437
1438Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1439
1440 * mips.igen (r3900): r3900 does not support 64 bit integer
1441 operations.
1442
1443Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1444
1445 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1446 than igen one.
1447 * configure : Rebuild.
1448
1449Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1450
1451 * configure: Regenerated to track ../common/aclocal.m4 changes.
1452
1453Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1454
1455 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1456
1457Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1458
1459 * configure: Regenerated to track ../common/aclocal.m4 changes.
1460 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1461
1462Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1463
1464 * configure: Regenerated to track ../common/aclocal.m4 changes.
1465
1466Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1467
1468 * interp.c (Max, Min): Comment out functions. Not yet used.
1469
1470Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1471
1472 * configure: Regenerated to track ../common/aclocal.m4 changes.
1473
1474Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1475
1476 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1477 configurable settings for stand-alone simulator.
1478
1479 * configure.in: Added X11 search, just in case.
1480
1481 * configure: Regenerated.
1482
1483Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1484
1485 * interp.c (sim_write, sim_read, load_memory, store_memory):
1486 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1487
1488Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1489
1490 * sim-main.h (GETFCC): Return an unsigned value.
1491
1492Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1493
1494 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1495 (DADD): Result destination is RD not RT.
1496
1497Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1498
1499 * sim-main.h (HIACCESS, LOACCESS): Always define.
1500
1501 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1502
1503 * interp.c (sim_info): Delete.
1504
1505Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1506
1507 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1508 (mips_option_handler): New argument `cpu'.
1509 (sim_open): Update call to sim_add_option_table.
1510
1511Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1512
1513 * mips.igen (CxC1): Add tracing.
1514
1515Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1516
1517 * sim-main.h (Max, Min): Declare.
1518
1519 * interp.c (Max, Min): New functions.
1520
1521 * mips.igen (BC1): Add tracing.
1522
1523Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1524
1525 * interp.c Added memory map for stack in vr4100
1526
1527Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1528
1529 * interp.c (load_memory): Add missing "break"'s.
1530
1531Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1532
1533 * interp.c (sim_store_register, sim_fetch_register): Pass in
1534 length parameter. Return -1.
1535
1536Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1537
1538 * interp.c: Added hardware init hook, fixed warnings.
1539
1540Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1541
1542 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1543
1544Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1545
1546 * interp.c (ifetch16): New function.
1547
1548 * sim-main.h (IMEM32): Rename IMEM.
1549 (IMEM16_IMMED): Define.
1550 (IMEM16): Define.
1551 (DELAY_SLOT): Update.
1552
1553 * m16run.c (sim_engine_run): New file.
1554
1555 * m16.igen: All instructions except LB.
1556 (LB): Call do_load_byte.
1557 * mips.igen (do_load_byte): New function.
1558 (LB): Call do_load_byte.
1559
1560 * mips.igen: Move spec for insn bit size and high bit from here.
1561 * Makefile.in (tmp-igen, tmp-m16): To here.
1562
1563 * m16.dc: New file, decode mips16 instructions.
1564
1565 * Makefile.in (SIM_NO_ALL): Define.
1566 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1567
1568Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1569
1570 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1571 point unit to 32 bit registers.
1572 * configure: Re-generate.
1573
1574Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1575
1576 * configure.in (sim_use_gen): Make IGEN the default simulator
1577 generator for generic 32 and 64 bit mips targets.
1578 * configure: Re-generate.
1579
1580Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1581
1582 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1583 bitsize.
1584
1585 * interp.c (sim_fetch_register, sim_store_register): Read/write
1586 FGR from correct location.
1587 (sim_open): Set size of FGR's according to
1588 WITH_TARGET_FLOATING_POINT_BITSIZE.
1589
1590 * sim-main.h (FGR): Store floating point registers in a separate
1591 array.
1592
1593Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1594
1595 * configure: Regenerated to track ../common/aclocal.m4 changes.
1596
1597Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1598
1599 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1600
1601 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1602
1603 * interp.c (pending_tick): New function. Deliver pending writes.
1604
1605 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1606 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1607 it can handle mixed sized quantites and single bits.
1608
1609Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1610
1611 * interp.c (oengine.h): Do not include when building with IGEN.
1612 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1613 (sim_info): Ditto for PROCESSOR_64BIT.
1614 (sim_monitor): Replace ut_reg with unsigned_word.
1615 (*): Ditto for t_reg.
1616 (LOADDRMASK): Define.
1617 (sim_open): Remove defunct check that host FP is IEEE compliant,
1618 using software to emulate floating point.
1619 (value_fpr, ...): Always compile, was conditional on HASFPU.
1620
1621Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1622
1623 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1624 size.
1625
1626 * interp.c (SD, CPU): Define.
1627 (mips_option_handler): Set flags in each CPU.
1628 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1629 (sim_close): Do not clear STATE, deleted anyway.
1630 (sim_write, sim_read): Assume CPU zero's vm should be used for
1631 data transfers.
1632 (sim_create_inferior): Set the PC for all processors.
1633 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1634 argument.
1635 (mips16_entry): Pass correct nr of args to store_word, load_word.
1636 (ColdReset): Cold reset all cpu's.
1637 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1638 (sim_monitor, load_memory, store_memory, signal_exception): Use
1639 `CPU' instead of STATE_CPU.
1640
1641
1642 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1643 SD or CPU_.
1644
1645 * sim-main.h (signal_exception): Add sim_cpu arg.
1646 (SignalException*): Pass both SD and CPU to signal_exception.
1647 * interp.c (signal_exception): Update.
1648
1649 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1650 Ditto
1651 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1652 address_translation): Ditto
1653 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1654
1655Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1656
1657 * configure: Regenerated to track ../common/aclocal.m4 changes.
1658
1659Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1660
1661 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1662
1663 * mips.igen (model): Map processor names onto BFD name.
1664
1665 * sim-main.h (CPU_CIA): Delete.
1666 (SET_CIA, GET_CIA): Define
1667
1668Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1669
1670 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1671 regiser.
1672
1673 * configure.in (default_endian): Configure a big-endian simulator
1674 by default.
1675 * configure: Re-generate.
1676
1677Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1678
1679 * configure: Regenerated to track ../common/aclocal.m4 changes.
1680
1681Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1682
1683 * interp.c (sim_monitor): Handle Densan monitor outbyte
1684 and inbyte functions.
1685
16861997-12-29 Felix Lee <flee@cygnus.com>
1687
1688 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1689
1690Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1691
1692 * Makefile.in (tmp-igen): Arrange for $zero to always be
1693 reset to zero after every instruction.
1694
1695Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1696
1697 * configure: Regenerated to track ../common/aclocal.m4 changes.
1698 * config.in: Ditto.
1699
1700Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1701
1702 * mips.igen (MSUB): Fix to work like MADD.
1703 * gencode.c (MSUB): Similarly.
1704
1705Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1706
1707 * configure: Regenerated to track ../common/aclocal.m4 changes.
1708
1709Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1710
1711 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1712
1713Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1714
1715 * sim-main.h (sim-fpu.h): Include.
1716
1717 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1718 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1719 using host independant sim_fpu module.
1720
1721Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1722
1723 * interp.c (signal_exception): Report internal errors with SIGABRT
1724 not SIGQUIT.
1725
1726 * sim-main.h (C0_CONFIG): New register.
1727 (signal.h): No longer include.
1728
1729 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1730
1731Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1732
1733 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1734
1735Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1736
1737 * mips.igen: Tag vr5000 instructions.
1738 (ANDI): Was missing mipsIV model, fix assembler syntax.
1739 (do_c_cond_fmt): New function.
1740 (C.cond.fmt): Handle mips I-III which do not support CC field
1741 separatly.
1742 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1743 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1744 in IV3.2 spec.
1745 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1746 vr5000 which saves LO in a GPR separatly.
1747
1748 * configure.in (enable-sim-igen): For vr5000, select vr5000
1749 specific instructions.
1750 * configure: Re-generate.
1751
1752Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1753
1754 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1755
1756 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1757 fmt_uninterpreted_64 bit cases to switch. Convert to
1758 fmt_formatted,
1759
1760 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1761
1762 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1763 as specified in IV3.2 spec.
1764 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1765
1766Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1767
1768 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1769 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1770 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1771 PENDING_FILL versions of instructions. Simplify.
1772 (X): New function.
1773 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1774 instructions.
1775 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1776 a signed value.
1777 (MTHI, MFHI): Disable code checking HI-LO.
1778
1779 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1780 global.
1781 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1782
1783Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1784
1785 * gencode.c (build_mips16_operands): Replace IPC with cia.
1786
1787 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1788 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1789 IPC to `cia'.
1790 (UndefinedResult): Replace function with macro/function
1791 combination.
1792 (sim_engine_run): Don't save PC in IPC.
1793
1794 * sim-main.h (IPC): Delete.
1795
1796
1797 * interp.c (signal_exception, store_word, load_word,
1798 address_translation, load_memory, store_memory, cache_op,
1799 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1800 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1801 current instruction address - cia - argument.
1802 (sim_read, sim_write): Call address_translation directly.
1803 (sim_engine_run): Rename variable vaddr to cia.
1804 (signal_exception): Pass cia to sim_monitor
1805
1806 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1807 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1808 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1809
1810 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1811 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1812 SIM_ASSERT.
1813
1814 * interp.c (signal_exception): Pass restart address to
1815 sim_engine_restart.
1816
1817 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1818 idecode.o): Add dependency.
1819
1820 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1821 Delete definitions
1822 (DELAY_SLOT): Update NIA not PC with branch address.
1823 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1824
1825 * mips.igen: Use CIA not PC in branch calculations.
1826 (illegal): Call SignalException.
1827 (BEQ, ADDIU): Fix assembler.
1828
1829Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1830
1831 * m16.igen (JALX): Was missing.
1832
1833 * configure.in (enable-sim-igen): New configuration option.
1834 * configure: Re-generate.
1835
1836 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1837
1838 * interp.c (load_memory, store_memory): Delete parameter RAW.
1839 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1840 bypassing {load,store}_memory.
1841
1842 * sim-main.h (ByteSwapMem): Delete definition.
1843
1844 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1845
1846 * interp.c (sim_do_command, sim_commands): Delete mips specific
1847 commands. Handled by module sim-options.
1848
1849 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1850 (WITH_MODULO_MEMORY): Define.
1851
1852 * interp.c (sim_info): Delete code printing memory size.
1853
1854 * interp.c (mips_size): Nee sim_size, delete function.
1855 (power2): Delete.
1856 (monitor, monitor_base, monitor_size): Delete global variables.
1857 (sim_open, sim_close): Delete code creating monitor and other
1858 memory regions. Use sim-memopts module, via sim_do_commandf, to
1859 manage memory regions.
1860 (load_memory, store_memory): Use sim-core for memory model.
1861
1862 * interp.c (address_translation): Delete all memory map code
1863 except line forcing 32 bit addresses.
1864
1865Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1866
1867 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1868 trace options.
1869
1870 * interp.c (logfh, logfile): Delete globals.
1871 (sim_open, sim_close): Delete code opening & closing log file.
1872 (mips_option_handler): Delete -l and -n options.
1873 (OPTION mips_options): Ditto.
1874
1875 * interp.c (OPTION mips_options): Rename option trace to dinero.
1876 (mips_option_handler): Update.
1877
1878Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1879
1880 * interp.c (fetch_str): New function.
1881 (sim_monitor): Rewrite using sim_read & sim_write.
1882 (sim_open): Check magic number.
1883 (sim_open): Write monitor vectors into memory using sim_write.
1884 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1885 (sim_read, sim_write): Simplify - transfer data one byte at a
1886 time.
1887 (load_memory, store_memory): Clarify meaning of parameter RAW.
1888
1889 * sim-main.h (isHOST): Defete definition.
1890 (isTARGET): Mark as depreciated.
1891 (address_translation): Delete parameter HOST.
1892
1893 * interp.c (address_translation): Delete parameter HOST.
1894
1895Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1896
1897 * mips.igen:
1898
1899 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1900 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1901
1902Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1903
1904 * mips.igen: Add model filter field to records.
1905
1906Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1907
1908 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1909
1910 interp.c (sim_engine_run): Do not compile function sim_engine_run
1911 when WITH_IGEN == 1.
1912
1913 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1914 target architecture.
1915
1916 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1917 igen. Replace with configuration variables sim_igen_flags /
1918 sim_m16_flags.
1919
1920 * m16.igen: New file. Copy mips16 insns here.
1921 * mips.igen: From here.
1922
1923Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1924
1925 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1926 to top.
1927 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1928
1929Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1930
1931 * gencode.c (build_instruction): Follow sim_write's lead in using
1932 BigEndianMem instead of !ByteSwapMem.
1933
1934Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1935
1936 * configure.in (sim_gen): Dependent on target, select type of
1937 generator. Always select old style generator.
1938
1939 configure: Re-generate.
1940
1941 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1942 targets.
1943 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1944 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1945 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1946 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1947 SIM_@sim_gen@_*, set by autoconf.
1948
1949Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1950
1951 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1952
1953 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1954 CURRENT_FLOATING_POINT instead.
1955
1956 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1957 (address_translation): Raise exception InstructionFetch when
1958 translation fails and isINSTRUCTION.
1959
1960 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1961 sim_engine_run): Change type of of vaddr and paddr to
1962 address_word.
1963 (address_translation, prefetch, load_memory, store_memory,
1964 cache_op): Change type of vAddr and pAddr to address_word.
1965
1966 * gencode.c (build_instruction): Change type of vaddr and paddr to
1967 address_word.
1968
1969Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1970
1971 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1972 macro to obtain result of ALU op.
1973
1974Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1975
1976 * interp.c (sim_info): Call profile_print.
1977
1978Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1979
1980 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1981
1982 * sim-main.h (WITH_PROFILE): Do not define, defined in
1983 common/sim-config.h. Use sim-profile module.
1984 (simPROFILE): Delete defintion.
1985
1986 * interp.c (PROFILE): Delete definition.
1987 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1988 (sim_close): Delete code writing profile histogram.
1989 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1990 Delete.
1991 (sim_engine_run): Delete code profiling the PC.
1992
1993Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1994
1995 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1996
1997 * interp.c (sim_monitor): Make register pointers of type
1998 unsigned_word*.
1999
2000 * sim-main.h: Make registers of type unsigned_word not
2001 signed_word.
2002
2003Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2004
2005 * interp.c (sync_operation): Rename from SyncOperation, make
2006 global, add SD argument.
2007 (prefetch): Rename from Prefetch, make global, add SD argument.
2008 (decode_coproc): Make global.
2009
2010 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2011
2012 * gencode.c (build_instruction): Generate DecodeCoproc not
2013 decode_coproc calls.
2014
2015 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2016 (SizeFGR): Move to sim-main.h
2017 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2018 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2019 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2020 sim-main.h.
2021 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2022 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2023 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2024 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2025 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2026 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2027
2028 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2029 exception.
2030 (sim-alu.h): Include.
2031 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2032 (sim_cia): Typedef to instruction_address.
2033
2034Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2035
2036 * Makefile.in (interp.o): Rename generated file engine.c to
2037 oengine.c.
2038
2039 * interp.c: Update.
2040
2041Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2042
2043 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2044
2045Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2046
2047 * gencode.c (build_instruction): For "FPSQRT", output correct
2048 number of arguments to Recip.
2049
2050Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2051
2052 * Makefile.in (interp.o): Depends on sim-main.h
2053
2054 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2055
2056 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2057 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2058 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2059 STATE, DSSTATE): Define
2060 (GPR, FGRIDX, ..): Define.
2061
2062 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2063 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2064 (GPR, FGRIDX, ...): Delete macros.
2065
2066 * interp.c: Update names to match defines from sim-main.h
2067
2068Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2069
2070 * interp.c (sim_monitor): Add SD argument.
2071 (sim_warning): Delete. Replace calls with calls to
2072 sim_io_eprintf.
2073 (sim_error): Delete. Replace calls with sim_io_error.
2074 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2075 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2076 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2077 argument.
2078 (mips_size): Rename from sim_size. Add SD argument.
2079
2080 * interp.c (simulator): Delete global variable.
2081 (callback): Delete global variable.
2082 (mips_option_handler, sim_open, sim_write, sim_read,
2083 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2084 sim_size,sim_monitor): Use sim_io_* not callback->*.
2085 (sim_open): ZALLOC simulator struct.
2086 (PROFILE): Do not define.
2087
2088Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2089
2090 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2091 support.h with corresponding code.
2092
2093 * sim-main.h (word64, uword64), support.h: Move definition to
2094 sim-main.h.
2095 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2096
2097 * support.h: Delete
2098 * Makefile.in: Update dependencies
2099 * interp.c: Do not include.
2100
2101Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2102
2103 * interp.c (address_translation, load_memory, store_memory,
2104 cache_op): Rename to from AddressTranslation et.al., make global,
2105 add SD argument
2106
2107 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2108 CacheOp): Define.
2109
2110 * interp.c (SignalException): Rename to signal_exception, make
2111 global.
2112
2113 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2114
2115 * sim-main.h (SignalException, SignalExceptionInterrupt,
2116 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2117 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2118 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2119 Define.
2120
2121 * interp.c, support.h: Use.
2122
2123Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2124
2125 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2126 to value_fpr / store_fpr. Add SD argument.
2127 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2128 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2129
2130 * sim-main.h (ValueFPR, StoreFPR): Define.
2131
2132Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2133
2134 * interp.c (sim_engine_run): Check consistency between configure
2135 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2136 and HASFPU.
2137
2138 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2139 (mips_fpu): Configure WITH_FLOATING_POINT.
2140 (mips_endian): Configure WITH_TARGET_ENDIAN.
2141 * configure: Update.
2142
2143Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2144
2145 * configure: Regenerated to track ../common/aclocal.m4 changes.
2146
2147Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2148
2149 * configure: Regenerated.
2150
2151Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2152
2153 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2154
2155Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2156
2157 * gencode.c (print_igen_insn_models): Assume certain architectures
2158 include all mips* instructions.
2159 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2160 instruction.
2161
2162 * Makefile.in (tmp.igen): Add target. Generate igen input from
2163 gencode file.
2164
2165 * gencode.c (FEATURE_IGEN): Define.
2166 (main): Add --igen option. Generate output in igen format.
2167 (process_instructions): Format output according to igen option.
2168 (print_igen_insn_format): New function.
2169 (print_igen_insn_models): New function.
2170 (process_instructions): Only issue warnings and ignore
2171 instructions when no FEATURE_IGEN.
2172
2173Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2174
2175 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2176 MIPS targets.
2177
2178Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2179
2180 * configure: Regenerated to track ../common/aclocal.m4 changes.
2181
2182Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2183
2184 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2185 SIM_RESERVED_BITS): Delete, moved to common.
2186 (SIM_EXTRA_CFLAGS): Update.
2187
2188Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2189
2190 * configure.in: Configure non-strict memory alignment.
2191 * configure: Regenerated to track ../common/aclocal.m4 changes.
2192
2193Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2194
2195 * configure: Regenerated to track ../common/aclocal.m4 changes.
2196
2197Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2198
2199 * gencode.c (SDBBP,DERET): Added (3900) insns.
2200 (RFE): Turn on for 3900.
2201 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2202 (dsstate): Made global.
2203 (SUBTARGET_R3900): Added.
2204 (CANCELDELAYSLOT): New.
2205 (SignalException): Ignore SystemCall rather than ignore and
2206 terminate. Add DebugBreakPoint handling.
2207 (decode_coproc): New insns RFE, DERET; and new registers Debug
2208 and DEPC protected by SUBTARGET_R3900.
2209 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2210 bits explicitly.
2211 * Makefile.in,configure.in: Add mips subtarget option.
2212 * configure: Update.
2213
2214Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2215
2216 * gencode.c: Add r3900 (tx39).
2217
2218
2219Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2220
2221 * gencode.c (build_instruction): Don't need to subtract 4 for
2222 JALR, just 2.
2223
2224Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2225
2226 * interp.c: Correct some HASFPU problems.
2227
2228Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2229
2230 * configure: Regenerated to track ../common/aclocal.m4 changes.
2231
2232Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2233
2234 * interp.c (mips_options): Fix samples option short form, should
2235 be `x'.
2236
2237Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2238
2239 * interp.c (sim_info): Enable info code. Was just returning.
2240
2241Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2242
2243 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2244 MFC0.
2245
2246Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2247
2248 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2249 constants.
2250 (build_instruction): Ditto for LL.
2251
2252Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2253
2254 * configure: Regenerated to track ../common/aclocal.m4 changes.
2255
2256Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2257
2258 * configure: Regenerated to track ../common/aclocal.m4 changes.
2259 * config.in: Ditto.
2260
2261Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2262
2263 * interp.c (sim_open): Add call to sim_analyze_program, update
2264 call to sim_config.
2265
2266Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2267
2268 * interp.c (sim_kill): Delete.
2269 (sim_create_inferior): Add ABFD argument. Set PC from same.
2270 (sim_load): Move code initializing trap handlers from here.
2271 (sim_open): To here.
2272 (sim_load): Delete, use sim-hload.c.
2273
2274 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2275
2276Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2277
2278 * configure: Regenerated to track ../common/aclocal.m4 changes.
2279 * config.in: Ditto.
2280
2281Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2282
2283 * interp.c (sim_open): Add ABFD argument.
2284 (sim_load): Move call to sim_config from here.
2285 (sim_open): To here. Check return status.
2286
2287Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2288
2289 * gencode.c (build_instruction): Two arg MADD should
2290 not assign result to $0.
2291
2292Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2293
2294 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2295 * sim/mips/configure.in: Regenerate.
2296
2297Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2298
2299 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2300 signed8, unsigned8 et.al. types.
2301
2302 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2303 hosts when selecting subreg.
2304
2305Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2306
2307 * interp.c (sim_engine_run): Reset the ZERO register to zero
2308 regardless of FEATURE_WARN_ZERO.
2309 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2310
2311Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2312
2313 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2314 (SignalException): For BreakPoints ignore any mode bits and just
2315 save the PC.
2316 (SignalException): Always set the CAUSE register.
2317
2318Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2319
2320 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2321 exception has been taken.
2322
2323 * interp.c: Implement the ERET and mt/f sr instructions.
2324
2325Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2326
2327 * interp.c (SignalException): Don't bother restarting an
2328 interrupt.
2329
2330Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2331
2332 * interp.c (SignalException): Really take an interrupt.
2333 (interrupt_event): Only deliver interrupts when enabled.
2334
2335Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2336
2337 * interp.c (sim_info): Only print info when verbose.
2338 (sim_info) Use sim_io_printf for output.
2339
2340Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2341
2342 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2343 mips architectures.
2344
2345Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2346
2347 * interp.c (sim_do_command): Check for common commands if a
2348 simulator specific command fails.
2349
2350Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2351
2352 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2353 and simBE when DEBUG is defined.
2354
2355Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2356
2357 * interp.c (interrupt_event): New function. Pass exception event
2358 onto exception handler.
2359
2360 * configure.in: Check for stdlib.h.
2361 * configure: Regenerate.
2362
2363 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2364 variable declaration.
2365 (build_instruction): Initialize memval1.
2366 (build_instruction): Add UNUSED attribute to byte, bigend,
2367 reverse.
2368 (build_operands): Ditto.
2369
2370 * interp.c: Fix GCC warnings.
2371 (sim_get_quit_code): Delete.
2372
2373 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2374 * Makefile.in: Ditto.
2375 * configure: Re-generate.
2376
2377 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2378
2379Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2380
2381 * interp.c (mips_option_handler): New function parse argumes using
2382 sim-options.
2383 (myname): Replace with STATE_MY_NAME.
2384 (sim_open): Delete check for host endianness - performed by
2385 sim_config.
2386 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2387 (sim_open): Move much of the initialization from here.
2388 (sim_load): To here. After the image has been loaded and
2389 endianness set.
2390 (sim_open): Move ColdReset from here.
2391 (sim_create_inferior): To here.
2392 (sim_open): Make FP check less dependant on host endianness.
2393
2394 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2395 run.
2396 * interp.c (sim_set_callbacks): Delete.
2397
2398 * interp.c (membank, membank_base, membank_size): Replace with
2399 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2400 (sim_open): Remove call to callback->init. gdb/run do this.
2401
2402 * interp.c: Update
2403
2404 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2405
2406 * interp.c (big_endian_p): Delete, replaced by
2407 current_target_byte_order.
2408
2409Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2410
2411 * interp.c (host_read_long, host_read_word, host_swap_word,
2412 host_swap_long): Delete. Using common sim-endian.
2413 (sim_fetch_register, sim_store_register): Use H2T.
2414 (pipeline_ticks): Delete. Handled by sim-events.
2415 (sim_info): Update.
2416 (sim_engine_run): Update.
2417
2418Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2419
2420 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2421 reason from here.
2422 (SignalException): To here. Signal using sim_engine_halt.
2423 (sim_stop_reason): Delete, moved to common.
2424
2425Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2426
2427 * interp.c (sim_open): Add callback argument.
2428 (sim_set_callbacks): Delete SIM_DESC argument.
2429 (sim_size): Ditto.
2430
2431Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2432
2433 * Makefile.in (SIM_OBJS): Add common modules.
2434
2435 * interp.c (sim_set_callbacks): Also set SD callback.
2436 (set_endianness, xfer_*, swap_*): Delete.
2437 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2438 Change to functions using sim-endian macros.
2439 (control_c, sim_stop): Delete, use common version.
2440 (simulate): Convert into.
2441 (sim_engine_run): This function.
2442 (sim_resume): Delete.
2443
2444 * interp.c (simulation): New variable - the simulator object.
2445 (sim_kind): Delete global - merged into simulation.
2446 (sim_load): Cleanup. Move PC assignment from here.
2447 (sim_create_inferior): To here.
2448
2449 * sim-main.h: New file.
2450 * interp.c (sim-main.h): Include.
2451
2452Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2453
2454 * configure: Regenerated to track ../common/aclocal.m4 changes.
2455
2456Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2457
2458 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2459
2460Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2461
2462 * gencode.c (build_instruction): DIV instructions: check
2463 for division by zero and integer overflow before using
2464 host's division operation.
2465
2466Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2467
2468 * Makefile.in (SIM_OBJS): Add sim-load.o.
2469 * interp.c: #include bfd.h.
2470 (target_byte_order): Delete.
2471 (sim_kind, myname, big_endian_p): New static locals.
2472 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2473 after argument parsing. Recognize -E arg, set endianness accordingly.
2474 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2475 load file into simulator. Set PC from bfd.
2476 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2477 (set_endianness): Use big_endian_p instead of target_byte_order.
2478
2479Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2480
2481 * interp.c (sim_size): Delete prototype - conflicts with
2482 definition in remote-sim.h. Correct definition.
2483
2484Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2485
2486 * configure: Regenerated to track ../common/aclocal.m4 changes.
2487 * config.in: Ditto.
2488
2489Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2490
2491 * interp.c (sim_open): New arg `kind'.
2492
2493 * configure: Regenerated to track ../common/aclocal.m4 changes.
2494
2495Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2496
2497 * configure: Regenerated to track ../common/aclocal.m4 changes.
2498
2499Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2500
2501 * interp.c (sim_open): Set optind to 0 before calling getopt.
2502
2503Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2504
2505 * configure: Regenerated to track ../common/aclocal.m4 changes.
2506
2507Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2508
2509 * interp.c : Replace uses of pr_addr with pr_uword64
2510 where the bit length is always 64 independent of SIM_ADDR.
2511 (pr_uword64) : added.
2512
2513Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2514
2515 * configure: Re-generate.
2516
2517Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2518
2519 * configure: Regenerate to track ../common/aclocal.m4 changes.
2520
2521Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2522
2523 * interp.c (sim_open): New SIM_DESC result. Argument is now
2524 in argv form.
2525 (other sim_*): New SIM_DESC argument.
2526
2527Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2528
2529 * interp.c: Fix printing of addresses for non-64-bit targets.
2530 (pr_addr): Add function to print address based on size.
2531
2532Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2533
2534 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2535
2536Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2537
2538 * gencode.c (build_mips16_operands): Correct computation of base
2539 address for extended PC relative instruction.
2540
2541Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2542
2543 * interp.c (mips16_entry): Add support for floating point cases.
2544 (SignalException): Pass floating point cases to mips16_entry.
2545 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2546 registers.
2547 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2548 or fmt_word.
2549 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2550 and then set the state to fmt_uninterpreted.
2551 (COP_SW): Temporarily set the state to fmt_word while calling
2552 ValueFPR.
2553
2554Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2555
2556 * gencode.c (build_instruction): The high order may be set in the
2557 comparison flags at any ISA level, not just ISA 4.
2558
2559Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2560
2561 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2562 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2563 * configure.in: sinclude ../common/aclocal.m4.
2564 * configure: Regenerated.
2565
2566Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2567
2568 * configure: Rebuild after change to aclocal.m4.
2569
2570Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2571
2572 * configure configure.in Makefile.in: Update to new configure
2573 scheme which is more compatible with WinGDB builds.
2574 * configure.in: Improve comment on how to run autoconf.
2575 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2576 * Makefile.in: Use autoconf substitution to install common
2577 makefile fragment.
2578
2579Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2580
2581 * gencode.c (build_instruction): Use BigEndianCPU instead of
2582 ByteSwapMem.
2583
2584Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2585
2586 * interp.c (sim_monitor): Make output to stdout visible in
2587 wingdb's I/O log window.
2588
2589Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2590
2591 * support.h: Undo previous change to SIGTRAP
2592 and SIGQUIT values.
2593
2594Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2595
2596 * interp.c (store_word, load_word): New static functions.
2597 (mips16_entry): New static function.
2598 (SignalException): Look for mips16 entry and exit instructions.
2599 (simulate): Use the correct index when setting fpr_state after
2600 doing a pending move.
2601
2602Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2603
2604 * interp.c: Fix byte-swapping code throughout to work on
2605 both little- and big-endian hosts.
2606
2607Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2608
2609 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2610 with gdb/config/i386/xm-windows.h.
2611
2612Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2613
2614 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2615 that messes up arithmetic shifts.
2616
2617Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2618
2619 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2620 SIGTRAP and SIGQUIT for _WIN32.
2621
2622Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2623
2624 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2625 force a 64 bit multiplication.
2626 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2627 destination register is 0, since that is the default mips16 nop
2628 instruction.
2629
2630Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2631
2632 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2633 (build_endian_shift): Don't check proc64.
2634 (build_instruction): Always set memval to uword64. Cast op2 to
2635 uword64 when shifting it left in memory instructions. Always use
2636 the same code for stores--don't special case proc64.
2637
2638 * gencode.c (build_mips16_operands): Fix base PC value for PC
2639 relative operands.
2640 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2641 jal instruction.
2642 * interp.c (simJALDELAYSLOT): Define.
2643 (JALDELAYSLOT): Define.
2644 (INDELAYSLOT, INJALDELAYSLOT): Define.
2645 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2646
2647Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2648
2649 * interp.c (sim_open): add flush_cache as a PMON routine
2650 (sim_monitor): handle flush_cache by ignoring it
2651
2652Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2653
2654 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2655 BigEndianMem.
2656 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2657 (BigEndianMem): Rename to ByteSwapMem and change sense.
2658 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2659 BigEndianMem references to !ByteSwapMem.
2660 (set_endianness): New function, with prototype.
2661 (sim_open): Call set_endianness.
2662 (sim_info): Use simBE instead of BigEndianMem.
2663 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2664 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2665 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2666 ifdefs, keeping the prototype declaration.
2667 (swap_word): Rewrite correctly.
2668 (ColdReset): Delete references to CONFIG. Delete endianness related
2669 code; moved to set_endianness.
2670
2671Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2672
2673 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2674 * interp.c (CHECKHILO): Define away.
2675 (simSIGINT): New macro.
2676 (membank_size): Increase from 1MB to 2MB.
2677 (control_c): New function.
2678 (sim_resume): Rename parameter signal to signal_number. Add local
2679 variable prev. Call signal before and after simulate.
2680 (sim_stop_reason): Add simSIGINT support.
2681 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2682 functions always.
2683 (sim_warning): Delete call to SignalException. Do call printf_filtered
2684 if logfh is NULL.
2685 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2686 a call to sim_warning.
2687
2688Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2689
2690 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2691 16 bit instructions.
2692
2693Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2694
2695 Add support for mips16 (16 bit MIPS implementation):
2696 * gencode.c (inst_type): Add mips16 instruction encoding types.
2697 (GETDATASIZEINSN): Define.
2698 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2699 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2700 mtlo.
2701 (MIPS16_DECODE): New table, for mips16 instructions.
2702 (bitmap_val): New static function.
2703 (struct mips16_op): Define.
2704 (mips16_op_table): New table, for mips16 operands.
2705 (build_mips16_operands): New static function.
2706 (process_instructions): If PC is odd, decode a mips16
2707 instruction. Break out instruction handling into new
2708 build_instruction function.
2709 (build_instruction): New static function, broken out of
2710 process_instructions. Check modifiers rather than flags for SHIFT
2711 bit count and m[ft]{hi,lo} direction.
2712 (usage): Pass program name to fprintf.
2713 (main): Remove unused variable this_option_optind. Change
2714 ``*loptarg++'' to ``loptarg++''.
2715 (my_strtoul): Parenthesize && within ||.
2716 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2717 (simulate): If PC is odd, fetch a 16 bit instruction, and
2718 increment PC by 2 rather than 4.
2719 * configure.in: Add case for mips16*-*-*.
2720 * configure: Rebuild.
2721
2722Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2723
2724 * interp.c: Allow -t to enable tracing in standalone simulator.
2725 Fix garbage output in trace file and error messages.
2726
2727Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2728
2729 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2730 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2731 * configure.in: Simplify using macros in ../common/aclocal.m4.
2732 * configure: Regenerated.
2733 * tconfig.in: New file.
2734
2735Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2736
2737 * interp.c: Fix bugs in 64-bit port.
2738 Use ansi function declarations for msvc compiler.
2739 Initialize and test file pointer in trace code.
2740 Prevent duplicate definition of LAST_EMED_REGNUM.
2741
2742Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2743
2744 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2745
2746Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2747
2748 * interp.c (SignalException): Check for explicit terminating
2749 breakpoint value.
2750 * gencode.c: Pass instruction value through SignalException()
2751 calls for Trap, Breakpoint and Syscall.
2752
2753Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2754
2755 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2756 only used on those hosts that provide it.
2757 * configure.in: Add sqrt() to list of functions to be checked for.
2758 * config.in: Re-generated.
2759 * configure: Re-generated.
2760
2761Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2762
2763 * gencode.c (process_instructions): Call build_endian_shift when
2764 expanding STORE RIGHT, to fix swr.
2765 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2766 clear the high bits.
2767 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2768 Fix float to int conversions to produce signed values.
2769
2770Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2771
2772 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2773 (process_instructions): Correct handling of nor instruction.
2774 Correct shift count for 32 bit shift instructions. Correct sign
2775 extension for arithmetic shifts to not shift the number of bits in
2776 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2777 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2778 Fix madd.
2779 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2780 It's OK to have a mult follow a mult. What's not OK is to have a
2781 mult follow an mfhi.
2782 (Convert): Comment out incorrect rounding code.
2783
2784Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2785
2786 * interp.c (sim_monitor): Improved monitor printf
2787 simulation. Tidied up simulator warnings, and added "--log" option
2788 for directing warning message output.
2789 * gencode.c: Use sim_warning() rather than WARNING macro.
2790
2791Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2792
2793 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2794 getopt1.o, rather than on gencode.c. Link objects together.
2795 Don't link against -liberty.
2796 (gencode.o, getopt.o, getopt1.o): New targets.
2797 * gencode.c: Include <ctype.h> and "ansidecl.h".
2798 (AND): Undefine after including "ansidecl.h".
2799 (ULONG_MAX): Define if not defined.
2800 (OP_*): Don't define macros; now defined in opcode/mips.h.
2801 (main): Call my_strtoul rather than strtoul.
2802 (my_strtoul): New static function.
2803
2804Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2805
2806 * gencode.c (process_instructions): Generate word64 and uword64
2807 instead of `long long' and `unsigned long long' data types.
2808 * interp.c: #include sysdep.h to get signals, and define default
2809 for SIGBUS.
2810 * (Convert): Work around for Visual-C++ compiler bug with type
2811 conversion.
2812 * support.h: Make things compile under Visual-C++ by using
2813 __int64 instead of `long long'. Change many refs to long long
2814 into word64/uword64 typedefs.
2815
2816Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2817
2818 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2819 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2820 (docdir): Removed.
2821 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2822 (AC_PROG_INSTALL): Added.
2823 (AC_PROG_CC): Moved to before configure.host call.
2824 * configure: Rebuilt.
2825
2826Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2827
2828 * configure.in: Define @SIMCONF@ depending on mips target.
2829 * configure: Rebuild.
2830 * Makefile.in (run): Add @SIMCONF@ to control simulator
2831 construction.
2832 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2833 * interp.c: Remove some debugging, provide more detailed error
2834 messages, update memory accesses to use LOADDRMASK.
2835
2836Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2837
2838 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2839 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2840 stamp-h.
2841 * configure: Rebuild.
2842 * config.in: New file, generated by autoheader.
2843 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2844 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2845 HAVE_ANINT and HAVE_AINT, as appropriate.
2846 * Makefile.in (run): Use @LIBS@ rather than -lm.
2847 (interp.o): Depend upon config.h.
2848 (Makefile): Just rebuild Makefile.
2849 (clean): Remove stamp-h.
2850 (mostlyclean): Make the same as clean, not as distclean.
2851 (config.h, stamp-h): New targets.
2852
2853Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2854
2855 * interp.c (ColdReset): Fix boolean test. Make all simulator
2856 globals static.
2857
2858Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2859
2860 * interp.c (xfer_direct_word, xfer_direct_long,
2861 swap_direct_word, swap_direct_long, xfer_big_word,
2862 xfer_big_long, xfer_little_word, xfer_little_long,
2863 swap_word,swap_long): Added.
2864 * interp.c (ColdReset): Provide function indirection to
2865 host<->simulated_target transfer routines.
2866 * interp.c (sim_store_register, sim_fetch_register): Updated to
2867 make use of indirected transfer routines.
2868
2869Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2870
2871 * gencode.c (process_instructions): Ensure FP ABS instruction
2872 recognised.
2873 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2874 system call support.
2875
2876Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2877
2878 * interp.c (sim_do_command): Complain if callback structure not
2879 initialised.
2880
2881Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2882
2883 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2884 support for Sun hosts.
2885 * Makefile.in (gencode): Ensure the host compiler and libraries
2886 used for cross-hosted build.
2887
2888Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2889
2890 * interp.c, gencode.c: Some more (TODO) tidying.
2891
2892Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2893
2894 * gencode.c, interp.c: Replaced explicit long long references with
2895 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2896 * support.h (SET64LO, SET64HI): Macros added.
2897
2898Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2899
2900 * configure: Regenerate with autoconf 2.7.
2901
2902Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2903
2904 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2905 * support.h: Remove superfluous "1" from #if.
2906 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2907
2908Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2909
2910 * interp.c (StoreFPR): Control UndefinedResult() call on
2911 WARN_RESULT manifest.
2912
2913Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2914
2915 * gencode.c: Tidied instruction decoding, and added FP instruction
2916 support.
2917
2918 * interp.c: Added dineroIII, and BSD profiling support. Also
2919 run-time FP handling.
2920
2921Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2922
2923 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2924 gencode.c, interp.c, support.h: created.
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