projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
sim: mips: delete mmu stubs to move to common sim_{read,write}
[deliverable/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
26f8bf63
MF		 12015-12-26 Mike Frysinger <vapier@gentoo.org>
2
3 * interp.c (sim_write, sim_read): Delete.
4 (store_word): Delete call to AddressTranslation and set paddr=vaddr.
5 (load_word): Likewise.
6 * micromips.igen (cache): Likewise.
7 * mips.igen (do_ll, do_lld, do_sc, do_scd, do_suxc1_32, do_swc1,
8 do_swxc1, cache, do_load, do_load_left, do_load_right, do_store,
9 do_store_left, do_store_right, do_load_double, do_store_double):
10 Likewise.
11 (do_pref): Delete call to AddressTranslation and stub out Prefetch.
12 (do_prefx): Likewise.
13 * sim-main.c (address_translation, prefetch): Delete.
14 (ifetch32, ifetch16): Delete call to AddressTranslation and set
15 paddr=vaddr.
16 * sim-main.h (Uncached, CachedNoncoherent, CachedCoherent, Cached,
17 address_translation, AddressTranslation, prefetch, Prefetch): Delete.
18 (LoadMemory, StoreMemory): Delete CCA arg.
19
ef04e371
MF		 202015-12-24 Mike Frysinger <vapier@gentoo.org>
21
22 * configure.ac (SIM_SUBTARGET): Drop -DTARGET_TX3904=1.
23 * configure: Regenerated.
24
cb379ede
MF		 252015-12-24 Mike Frysinger <vapier@gentoo.org>
26
27 * sim-main.h (SIM_QUIET_NAN_NEGATED): Move from tconfig.h.
28 * tconfig.h: Delete.
29
26936211
MF		 302015-12-24 Mike Frysinger <vapier@gentoo.org>
31
32 * tconfig.h (SIM_HANDLES_LMA): Delete.
33
84e8e361
MF		 342015-12-24 Mike Frysinger <vapier@gentoo.org>
35
36 * sim-main.h (WITH_WATCHPOINTS): Delete.
37
3cabaf66
MF		 382015-12-24 Mike Frysinger <vapier@gentoo.org>
39
40 * interp.c [SIM_HAVE_FLATMEM] (sim_open): Delete flatmem code.
41
8abe6c66
MF		 422015-12-24 Mike Frysinger <vapier@gentoo.org>
43
44 * tconfig.h (SIM_HAVE_SIMCACHE): Delete.
45
1d19cae7
DV		 462015-12-15 Dominik Vogt <vogt@linux.vnet.ibm.com>
47
48 * micromips.igen (process_isa_mode): Fix left shift of negative
49 value.
50
cdf850e9
MF		 512015-11-17 Mike Frysinger <vapier@gentoo.org>
52
53 * sim-main.h (WITH_MODULO_MEMORY): Delete.
54
797eee42
MF		 552015-11-15 Mike Frysinger <vapier@gentoo.org>
56
57 * Makefile.in (SIM_OBJS): Delete sim-reason.o and sim-stop.o.
58
6e4f085c
MF		 592015-11-14 Mike Frysinger <vapier@gentoo.org>
60
61 * interp.c (sim_close): Rename to ...
62 (mips_sim_close): ... this. Delete calls to sim_module_uninstall and
63 sim_io_shutdown.
64 * sim-main.h (mips_sim_close): Declare.
65 (SIM_CLOSE_HOOK): Define.
66
8e394ffc
AB		 672015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
68 Ali Lown <ali.lown@imgtec.com>
69
70 * Makefile.in (tmp-micromips): New rule.
71 (tmp-mach-multi): Add support for micromips.
72 * configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
73 that works for both mips64 and micromips64.
74 (mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
75 micromips32.
76 Add build support for micromips.
77 * dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
78 do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
79 do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
80 do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
81 do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
82 do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
83 do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
84 do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
85 Refactored instruction code to use these functions.
86 * dsp2.igen: Refactored instruction code to use the new functions.
87 * interp.c (decode_coproc): Refactored to work with any instruction
88 encoding.
89 (isa_mode): New variable
90 (RSVD_INSTRUCTION): Changed to 0x00000039.
91 * m16.igen (BREAK16): Refactored instruction to use do_break16.
92 (JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
93 * micromips.dc: New file.
94 * micromips.igen: New file.
95 * micromips16.dc: New file.
96 * micromipsdsp.igen: New file.
97 * micromipsrun.c: New file.
98 * mips.igen (do_swc1): Changed to work with any instruction encoding.
99 (do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
100 do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo,
101 do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu,
102 do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu,
103 do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub,
104 do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo,
105 do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc,
106 do_scd, do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu,
107 do_tgeu, do_tlt do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt,
108 do_add_fmt, do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1,
109 do_cvt_d_fmt, do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl,
110 do_cvt_s_pu, do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt,
111 do_luxc1_32, do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b,
112 do_mov_fmt, do_movtf, do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt,
113 do_mtc1b, do_mul_fmt, do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps,
114 do_plu_ps, do_pul_ps, do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt,
115 do_prefx, do_sdc1, do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt,
116 do_swc1, do_swxc1, do_trunc_fmt): New functions, refactored from existing
117 instructions.
118 Refactored instruction code to use these functions.
119 (RSVD): Changed to use new reserved instruction.
120 (loadstore_ea, not_word_value, unpredictable, check_mt_hilo,
121 check_mf_hilo, check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32,
122 do_sdc1, do_suxc1_32, check_fmt_p, check_fpu, do_load_double,
123 do_store_double): Added micromips32 and micromips64 models.
124 Added include for micromips.igen and micromipsdsp.igen
125 Add micromips32 and micromips64 models.
126 (DecodeCoproc): Updated to use new macro definition.
127 * mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
128 do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
129 do_seb, do_seh do_rdhwr, do_wsbh): New functions.
130 Refactored instruction code to use these functions.
131 * sim-main.h (CP0_operation): New enum.
132 (DecodeCoproc): Updated macro.
133 (IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
134 MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16,
135 MICROMIPS_DELAYSLOT_SIZE_32, ISA_MODE_MIPS32 and
136 ISA_MODE_MICROMIPS): New defines.
137 (sim_state): Add isa_mode field.
138
8d0978fb
MF		 1392015-06-23 Mike Frysinger <vapier@gentoo.org>
140
141 * configure: Regenerate.
142
306f4178
MF		 1432015-06-12 Mike Frysinger <vapier@gentoo.org>
144
145 * configure.ac: Change configure.in to configure.ac.
146 * configure: Regenerate.
147
a3487082
MF		 1482015-06-12 Mike Frysinger <vapier@gentoo.org>
149
150 * configure: Regenerate.
151
29bc024d
MF		 1522015-06-12 Mike Frysinger <vapier@gentoo.org>
153
154 * interp.c [TRACE]: Delete.
155 (TRACE): Change to WITH_TRACE_ANY_P.
156 [!WITH_TRACE_ANY_P] (open_trace): Define.
157 (mips_option_handler, open_trace, sim_close, dotrace):
158 Change defined(TRACE) to WITH_TRACE_ANY_P.
159 (sim_open): Delete TRACE ifdef check.
160 * sim-main.c (load_memory): Delete TRACE ifdef check.
161 (store_memory): Likewise.
162 * sim-main.h [WITH_TRACE_ANY_P] (dotrace, tracefh): Protect decls.
163 [!WITH_TRACE_ANY_P] (dotrace): Define.
164
3ebe2863
MF		 1652015-04-18 Mike Frysinger <vapier@gentoo.org>
166
167 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESTART_HOOK): Delete
168 comments.
169
20bca71d
MF		 1702015-04-18 Mike Frysinger <vapier@gentoo.org>
171
172 * sim-main.h (SIM_CPU): Delete.
173
7e83aa92
MF		 1742015-04-18 Mike Frysinger <vapier@gentoo.org>
175
176 * sim-main.h (sim_cia): Delete.
177
034685f9
MF		 1782015-04-17 Mike Frysinger <vapier@gentoo.org>
179
180 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Change CIA_GET to
181 PU_PC_GET.
182 * interp.c (interrupt_event): Change CIA_GET to CPU_PC_GET.
183 (sim_create_inferior): Change CIA_SET to CPU_PC_SET.
184 * m16run.c (sim_engine_run): Change CIA_GET to CPU_PC_GET and
185 CIA_SET to CPU_PC_SET.
186 * sim-main.h (CIA_GET, CIA_SET): Delete.
187
78e9aa70
MF		 1882015-04-15 Mike Frysinger <vapier@gentoo.org>
189
190 * Makefile.in (SIM_OBJS): Delete sim-cpu.o.
191 * sim-main.h (STATE_CPU): Delete.
192
bf12d44e
MF		 1932015-04-13 Mike Frysinger <vapier@gentoo.org>
194
195 * configure: Regenerate.
196
7bebb329
MF		 1972015-04-13 Mike Frysinger <vapier@gentoo.org>
198
199 * Makefile.in (SIM_OBJS): Add sim-cpu.o.
200 * interp.c (mips_pc_get, mips_pc_set): New functions.
201 (sim_open): Declare new local var i. Call sim_cpu_alloc_all.
202 Call CPU_PC_FETCH & CPU_PC_STORE for all cpus.
203 (sim_pc_get): Delete.
204 * sim-main.h (SIM_CPU): Define.
205 (struct sim_state): Change cpu to an array of pointers.
206 (STATE_CPU): Drop &.
207
8ac57fbd
MF		 2082015-04-13 Mike Frysinger <vapier@gentoo.org>
209
210 * interp.c (mips_option_handler, open_trace, sim_close,
211 sim_write, sim_read, sim_store_register, sim_fetch_register,
212 sim_create_inferior, pr_addr, pr_uword64): Convert old style
213 prototypes.
214 (sim_open): Convert old style prototype. Change casts with
215 sim_write to unsigned char *.
216 (fetch_str): Change null to unsigned char, and change cast to
217 unsigned char *.
218 (sim_monitor): Change c & ch to unsigned char. Change cast to
219 unsigned char *.
220
e787f858
MF		 2212015-04-12 Mike Frysinger <vapier@gentoo.org>
222
223 * Makefile.in (SIM_OBJS): Move interp.o to the start of the list.
224
122bbfb5
MF		 2252015-04-06 Mike Frysinger <vapier@gentoo.org>
226
227 * Makefile.in (SIM_OBJS): Delete sim-engine.o.
228
0fe84f3f
MF		 2292015-04-01 Mike Frysinger <vapier@gentoo.org>
230
231 * tconfig.h (SIM_HAVE_PROFILE): Delete.
232
aadc9410
MF		 2332015-03-31 Mike Frysinger <vapier@gentoo.org>
234
235 * config.in, configure: Regenerate.
236
05f53ed6
MF		 2372015-03-24 Mike Frysinger <vapier@gentoo.org>
238
239 * interp.c (sim_pc_get): New function.
240
c0931f26
MF		 2412015-03-24 Mike Frysinger <vapier@gentoo.org>
242
243 * sim-main.h (SIM_HAVE_BIENDIAN): Delete.
244 * tconfig.h (SIM_HAVE_BIENDIAN): Delete.
245
30452bbe
MF		 2462015-03-24 Mike Frysinger <vapier@gentoo.org>
247
248 * configure: Regenerate.
249
64dd13df
MF		 2502015-03-23 Mike Frysinger <vapier@gentoo.org>
251
252 * configure: Regenerate.
253
49cd1634
MF		 2542015-03-23 Mike Frysinger <vapier@gentoo.org>
255
256 * configure: Regenerate.
257 * configure.ac (mips_extra_objs): Delete.
258 * Makefile.in (MIPS_EXTRA_OBJS): Delete.
259 (SIM_OBJS): Delete MIPS_EXTRA_OBJS.
260
3649cb06
MF		 2612015-03-23 Mike Frysinger <vapier@gentoo.org>
262
263 * configure: Regenerate.
264 * configure.ac: Delete sim_hw checks for dv-sockser.
265
ae7d0cac
MF		 2662015-03-16 Mike Frysinger <vapier@gentoo.org>
267
268 * config.in, configure: Regenerate.
269 * tconfig.in: Rename file ...
270 * tconfig.h: ... here.
271
8406bb59
MF		 2722015-03-15 Mike Frysinger <vapier@gentoo.org>
273
274 * tconfig.in: Delete includes.
275 [HAVE_DV_SOCKSER]: Delete.
276
465fb143
MF		 2772015-03-14 Mike Frysinger <vapier@gentoo.org>
278
279 * Makefile.in (SIM_RUN_OBJS): Delete.
280
5cddc23a
MF		 2812015-03-14 Mike Frysinger <vapier@gentoo.org>
282
283 * configure.ac (AC_CHECK_HEADERS): Delete.
284 * aclocal.m4, configure: Regenerate.
285
2974be62
AM		 2862014-08-19 Alan Modra <amodra@gmail.com>
287
288 * configure: Regenerate.
289
faa743bb
RM		 2902014-08-15 Roland McGrath <mcgrathr@google.com>
291
292 * configure: Regenerate.
293 * config.in: Regenerate.
294
1a8a700e
MF		 2952014-03-04 Mike Frysinger <vapier@gentoo.org>
296
297 * configure: Regenerate.
298
bf3d9781
AM		 2992013-09-23 Alan Modra <amodra@gmail.com>
300
301 * configure: Regenerate.
302
31e6ad7d
MF		 3032013-06-03 Mike Frysinger <vapier@gentoo.org>
304
305 * aclocal.m4, configure: Regenerate.
306
d3685d60
TT		 3072013-05-10 Freddie Chopin <freddie_chopin@op.pl>
308
309 * configure: Rebuild.
310
1517bd27
MF		 3112013-03-26 Mike Frysinger <vapier@gentoo.org>
312
313 * configure: Regenerate.
314
3be31516
JS		 3152013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
316
317 * configure.ac: Address use of dv-sockser.o.
318 * tconfig.in: Conditionalize use of dv_sockser_install.
319 * configure: Regenerated.
320 * config.in: Regenerated.
321
37cb8f8e
SE		 3222012-10-04 Chao-ying Fu <fu@mips.com>
323 Steve Ellcey <sellcey@mips.com>
324
325 * mips/mips3264r2.igen (rdhwr): New.
326
87c8644f
JS		 3272012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
328
329 * configure.ac: Always link against dv-sockser.o.
330 * configure: Regenerate.
331
5f3ef9d0
JB		 3322012-06-15 Joel Brobecker <brobecker@adacore.com>
333
334 * config.in, configure: Regenerate.
335
a6ff997c
NC		 3362012-05-18 Nick Clifton <nickc@redhat.com>
337
338 PR 14072
339 * interp.c: Include config.h before system header files.
340
2232061b
MF		 3412012-03-24 Mike Frysinger <vapier@gentoo.org>
342
343 * aclocal.m4, config.in, configure: Regenerate.
344
db2e4d67
MF		 3452011-12-03 Mike Frysinger <vapier@gentoo.org>
346
347 * aclocal.m4: New file.
348 * configure: Regenerate.
349
4399a56b
MF		 3502011-10-19 Mike Frysinger <vapier@gentoo.org>
351
352 * configure: Regenerate after common/acinclude.m4 update.
353
9c082ca8
MF		 3542011-10-17 Mike Frysinger <vapier@gentoo.org>
355
356 * configure.ac: Change include to common/acinclude.m4.
357
6ffe910a
MF		 3582011-10-17 Mike Frysinger <vapier@gentoo.org>
359
360 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
361 call. Replace common.m4 include with SIM_AC_COMMON.
362 * configure: Regenerate.
363
31b28250
HPN		 3642011-07-08 Hans-Peter Nilsson <hp@axis.com>
365
3faa01e3
HPN		 366 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
367 $(SIM_EXTRA_DEPS).
368 (tmp-mach-multi): Exit early when igen fails.
31b28250 369
2419798b
MF		 3702011-07-05 Mike Frysinger <vapier@gentoo.org>
371
372 * interp.c (sim_do_command): Delete.
373
d79fe0d6
MF		 3742011-02-14 Mike Frysinger <vapier@gentoo.org>
375
376 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
377 (tx3904sio_fifo_reset): Likewise.
378 * interp.c (sim_monitor): Likewise.
379
5558e7e6
MF		 3802010-04-14 Mike Frysinger <vapier@gentoo.org>
381
382 * interp.c (sim_write): Add const to buffer arg.
383
35aafff4
JB		 3842010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
385
386 * interp.c: Don't include sysdep.h
387
3725885a
RW		 3882010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
389
390 * configure: Regenerate.
391
d6416cdc
RW		 3922009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
393
81ecdfbb
RW		 394 * config.in: Regenerate.
395 * configure: Likewise.
396
d6416cdc
RW		 397 * configure: Regenerate.
398
b5bd9624
HPN		 3992008-07-11 Hans-Peter Nilsson <hp@axis.com>
400
401 * configure: Regenerate to track ../common/common.m4 changes.
402 * config.in: Ditto.
403
6efef468 4042008-06-06 Vladimir Prus <vladimir@codesourcery.com>
72f4393d
L		 405 Daniel Jacobowitz <dan@codesourcery.com>
406 Joseph Myers <joseph@codesourcery.com>
6efef468
JM		 407
408 * configure: Regenerate.
409
60dc88db
RS		 4102007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
411
412 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
413 that unconditionally allows fmt_ps.
414 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
415 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
416 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
417 filter from 64,f to 32,f.
418 (PREFX): Change filter from 64 to 32.
419 (LDXC1, LUXC1): Provide separate mips32r2 implementations
420 that use do_load_double instead of do_load. Make both LUXC1
421 versions unpredictable if SizeFGR () != 64.
422 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
423 instead of do_store. Remove unused variable. Make both SUXC1
424 versions unpredictable if SizeFGR () != 64.
425
599ca73e
RS		 4262007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
427
428 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
429 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
430 shifts for that case.
431
2525df03
NC		 4322007-09-04 Nick Clifton <nickc@redhat.com>
433
434 * interp.c (options enum): Add OPTION_INFO_MEMORY.
435 (display_mem_info): New static variable.
436 (mips_option_handler): Handle OPTION_INFO_MEMORY.
437 (mips_options): Add info-memory and memory-info.
438 (sim_open): After processing the command line and board
439 specification, check display_mem_info. If it is set then
440 call the real handler for the --memory-info command line
441 switch.
442
35ee6e1e
JB		 4432007-08-24 Joel Brobecker <brobecker@adacore.com>
444
445 * configure.ac: Change license of multi-run.c to GPL version 3.
446 * configure: Regenerate.
447
d5fb0879
RS		 4482007-06-28 Richard Sandiford <richard@codesourcery.com>
449
450 * configure.ac, configure: Revert last patch.
451
2a2ce21b
RS		 4522007-06-26 Richard Sandiford <richard@codesourcery.com>
453
454 * configure.ac (sim_mipsisa3264_configs): New variable.
455 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
456 every configuration support all four targets, using the triplet to
457 determine the default.
458 * configure: Regenerate.
459
efdcccc9
RS		 4602007-06-25 Richard Sandiford <richard@codesourcery.com>
461
0a7692b2 462 * Makefile.in (m16run.o): New rule.
efdcccc9 463
f532a356
TS		 4642007-05-15 Thiemo Seufer <ths@mips.com>
465
466 * mips3264r2.igen (DSHD): Fix compile warning.
467
bfe9c90b
TS		 4682007-05-14 Thiemo Seufer <ths@mips.com>
469
470 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
471 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
472 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
473 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
474 for mips32r2.
475
53f4826b
TS		 4762007-03-01 Thiemo Seufer <ths@mips.com>
477
478 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
479 and mips64.
480
8bf3ddc8
TS		 4812007-02-20 Thiemo Seufer <ths@mips.com>
482
483 * dsp.igen: Update copyright notice.
484 * dsp2.igen: Fix copyright notice.
485
8b082fb1 4862007-02-20 Thiemo Seufer <ths@mips.com>
72f4393d 487 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 488
489 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
490 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
491 Add dsp2 to sim_igen_machine.
492 * configure: Regenerate.
493 * dsp.igen (do_ph_op): Add MUL support when op = 2.
494 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
495 (mulq_rs.ph): Use do_ph_mulq.
496 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
497 * mips.igen: Add dsp2 model and include dsp2.igen.
498 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
499 for *mips32r2, *mips64r2, *dsp.
500 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
501 for *mips32r2, *mips64r2, *dsp2.
502 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
503
b1004875 5042007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 505 Nigel Stephens <nigel@mips.com>
b1004875
TS		 506
507 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
508 jumps with hazard barrier.
509
f8df4c77 5102007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 511 Nigel Stephens <nigel@mips.com>
f8df4c77
TS		 512
513 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
514 after each call to sim_io_write.
515
b1004875 5162007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 517 Nigel Stephens <nigel@mips.com>
b1004875
TS		 518
519 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
520 supported by this simulator.
07802d98
TS		 521 (decode_coproc): Recognise additional CP0 Config registers
522 correctly.
523
14fb6c5a 5242007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d
L		 525 Nigel Stephens <nigel@mips.com>
526 David Ung <davidu@mips.com>
14fb6c5a
TS		 527
528 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
529 uninterpreted formats. If fmt is one of the uninterpreted types
530 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
531 fmt_word, and fmt_uninterpreted_64 like fmt_long.
532 (store_fpr): When writing an invalid odd register, set the
533 matching even register to fmt_unknown, not the following register.
534 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
535 the the memory window at offset 0 set by --memory-size command
536 line option.
537 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
538 point register.
539 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
540 register.
541 (sim_monitor): When returning the memory size to the MIPS
542 application, use the value in STATE_MEM_SIZE, not an arbitrary
543 hardcoded value.
544 (cop_lw): Don' mess around with FPR_STATE, just pass
545 fmt_uninterpreted_32 to StoreFPR.
546 (cop_sw): Similarly.
547 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
548 (cop_sd): Similarly.
549 * mips.igen (not_word_value): Single version for mips32, mips64
550 and mips16.
551
c8847145 5522007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 553 Nigel Stephens <nigel@mips.com>
c8847145
TS		 554
555 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
556 MBytes.
557
4b5d35ee
TS		 5582007-02-17 Thiemo Seufer <ths@mips.com>
559
560 * configure.ac (mips*-sde-elf*): Move in front of generic machine
561 configuration.
562 * configure: Regenerate.
563
3669427c
TS		 5642007-02-17 Thiemo Seufer <ths@mips.com>
565
566 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
567 Add mdmx to sim_igen_machine.
568 (mipsisa64*-*-*): Likewise. Remove dsp.
569 (mipsisa32*-*-*): Remove dsp.
570 * configure: Regenerate.
571
109ad085
TS		 5722007-02-13 Thiemo Seufer <ths@mips.com>
573
574 * configure.ac: Add mips*-sde-elf* target.
575 * configure: Regenerate.
576
921d7ad3
HPN		 5772006-12-21 Hans-Peter Nilsson <hp@axis.com>
578
579 * acconfig.h: Remove.
580 * config.in, configure: Regenerate.
581
02f97da7
TS		 5822006-11-07 Thiemo Seufer <ths@mips.com>
583
584 * dsp.igen (do_w_op): Fix compiler warning.
585
2d2733fc 5862006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 587 David Ung <davidu@mips.com>
2d2733fc
TS		 588
589 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
590 sim_igen_machine.
591 * configure: Regenerate.
592 * mips.igen (model): Add smartmips.
593 (MADDU): Increment ACX if carry.
594 (do_mult): Clear ACX.
595 (ROR,RORV): Add smartmips.
72f4393d 596 (include): Include smartmips.igen.
2d2733fc
TS		 597 * sim-main.h (ACX): Set to REGISTERS[89].
598 * smartmips.igen: New file.
599
d85c3a10 6002006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 601 David Ung <davidu@mips.com>
d85c3a10
TS		 602
603 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
604 mips3264r2.igen. Add missing dependency rules.
605 * m16e.igen: Support for mips16e save/restore instructions.
606
e85e3205
RE		 6072006-06-13 Richard Earnshaw <rearnsha@arm.com>
608
609 * configure: Regenerated.
610
2f0122dc
DJ		 6112006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
612
613 * configure: Regenerated.
614
20e95c23
DJ		 6152006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
616
617 * configure: Regenerated.
618
69088b17
CF		 6192006-05-15 Chao-ying Fu <fu@mips.com>
620
621 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
622
0275de4e
NC		 6232006-04-18 Nick Clifton <nickc@redhat.com>
624
625 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
626 statement.
627
b3a3ffef
HPN		 6282006-03-29 Hans-Peter Nilsson <hp@axis.com>
629
630 * configure: Regenerate.
631
40a5538e
CF		 6322005-12-14 Chao-ying Fu <fu@mips.com>
633
634 * Makefile.in (SIM_OBJS): Add dsp.o.
635 (dsp.o): New dependency.
636 (IGEN_INCLUDE): Add dsp.igen.
637 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
638 mipsisa64*-*-*): Add dsp to sim_igen_machine.
639 * configure: Regenerate.
640 * mips.igen: Add dsp model and include dsp.igen.
641 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
642 because these instructions are extended in DSP ASE.
643 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
644 adding 6 DSP accumulator registers and 1 DSP control register.
645 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
646 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
647 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
648 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
649 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
650 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
651 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
652 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
653 DSPCR_CCOND_SMASK): New define.
654 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
655 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
656
21d14896
ILT		 6572005-07-08 Ian Lance Taylor <ian@airs.com>
658
659 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
660
b16d63da 6612005-06-16 David Ung <davidu@mips.com>
72f4393d
L		 662 Nigel Stephens <nigel@mips.com>
663
664 * mips.igen: New mips16e model and include m16e.igen.
665 (check_u64): Add mips16e tag.
666 * m16e.igen: New file for MIPS16e instructions.
667 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
668 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
669 models.
670 * configure: Regenerate.
b16d63da 671
e70cb6cd 6722005-05-26 David Ung <davidu@mips.com>
72f4393d 673
e70cb6cd
CD		 674 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
675 tags to all instructions which are applicable to the new ISAs.
676 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
677 vr.igen.
678 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
72f4393d 679 instructions.
e70cb6cd
CD		 680 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
681 to mips.igen.
682 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
683 * configure: Regenerate.
72f4393d 684
2b193c4a
MK		 6852005-03-23 Mark Kettenis <kettenis@gnu.org>
686
687 * configure: Regenerate.
688
35695fd6
AC		 6892005-01-14 Andrew Cagney <cagney@gnu.org>
690
691 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
692 explicit call to AC_CONFIG_HEADER.
693 * configure: Regenerate.
694
f0569246
AC		 6952005-01-12 Andrew Cagney <cagney@gnu.org>
696
697 * configure.ac: Update to use ../common/common.m4.
698 * configure: Re-generate.
699
38f48d72
AC		 7002005-01-11 Andrew Cagney <cagney@localhost.localdomain>
701
702 * configure: Regenerated to track ../common/aclocal.m4 changes.
703
b7026657
AC		 7042005-01-07 Andrew Cagney <cagney@gnu.org>
705
706 * configure.ac: Rename configure.in, require autoconf 2.59.
707 * configure: Re-generate.
708
379832de
HPN		 7092004-12-08 Hans-Peter Nilsson <hp@axis.com>
710
711 * configure: Regenerate for ../common/aclocal.m4 update.
712
cd62154c 7132004-09-24 Monika Chaddha <monika@acmet.com>
72f4393d 714
cd62154c
AC		 715 Committed by Andrew Cagney.
716 * m16.igen (CMP, CMPI): Fix assembler.
717
e5da76ec
CD		 7182004-08-18 Chris Demetriou <cgd@broadcom.com>
719
720 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
721 * configure: Regenerate.
722
139181c8
CD		 7232004-06-25 Chris Demetriou <cgd@broadcom.com>
724
725 * configure.in (sim_m16_machine): Include mipsIII.
726 * configure: Regenerate.
727
1a27f959
CD		 7282004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
729
72f4393d 730 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
1a27f959
CD		 731 from COP0_BADVADDR.
732 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
733
5dbb7b5a
CD		 7342004-04-10 Chris Demetriou <cgd@broadcom.com>
735
736 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
737
14234056
CD		 7382004-04-09 Chris Demetriou <cgd@broadcom.com>
739
740 * mips.igen (check_fmt): Remove.
741 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
742 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
743 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
744 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
745 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
746 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
747 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
748 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
749 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
750 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
751
c6f9085c
CD		 7522004-04-09 Chris Demetriou <cgd@broadcom.com>
753
754 * sb1.igen (check_sbx): New function.
755 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
756
11d66e66 7572004-03-29 Chris Demetriou <cgd@broadcom.com>
0e1b7197
RS		 758 Richard Sandiford <rsandifo@redhat.com>
759
760 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
761 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
762 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
763 separate implementations for mipsIV and mipsV. Use new macros to
764 determine whether the restrictions apply.
765
b3208fb8
CD		 7662004-01-19 Chris Demetriou <cgd@broadcom.com>
767
768 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
769 (check_mult_hilo): Improve comments.
770 (check_div_hilo): Likewise. Also, fork off a new version
771 to handle mips32/mips64 (since there are no hazards to check
772 in MIPS32/MIPS64).
773
9a1d84fb
CD		 7742003-06-17 Richard Sandiford <rsandifo@redhat.com>
775
776 * mips.igen (do_dmultx): Fix check for negative operands.
777
ae451ac6
ILT		 7782003-05-16 Ian Lance Taylor <ian@airs.com>
779
780 * Makefile.in (SHELL): Make sure this is defined.
781 (various): Use $(SHELL) whenever we invoke move-if-change.
782
dd69d292
CD		 7832003-05-03 Chris Demetriou <cgd@broadcom.com>
784
785 * cp1.c: Tweak attribution slightly.
786 * cp1.h: Likewise.
787 * mdmx.c: Likewise.
788 * mdmx.igen: Likewise.
789 * mips3d.igen: Likewise.
790 * sb1.igen: Likewise.
791
bcd0068e
CD		 7922003-04-15 Richard Sandiford <rsandifo@redhat.com>
793
794 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
795 unsigned operands.
796
6b4a8935
AC		 7972003-02-27 Andrew Cagney <cagney@redhat.com>
798
601da316
AC		 799 * interp.c (sim_open): Rename _bfd to bfd.
800 (sim_create_inferior): Ditto.
6b4a8935 801
d29e330f
CD		 8022003-01-14 Chris Demetriou <cgd@broadcom.com>
803
804 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
805
a2353a08
CD		 8062003-01-14 Chris Demetriou <cgd@broadcom.com>
807
808 * mips.igen (EI, DI): Remove.
809
80551777
CD		 8102003-01-05 Richard Sandiford <rsandifo@redhat.com>
811
812 * Makefile.in (tmp-run-multi): Fix mips16 filter.
813
4c54fc26
CD		 8142003-01-04 Richard Sandiford <rsandifo@redhat.com>
815 Andrew Cagney <ac131313@redhat.com>
816 Gavin Romig-Koch <gavin@redhat.com>
817 Graydon Hoare <graydon@redhat.com>
818 Aldy Hernandez <aldyh@redhat.com>
819 Dave Brolley <brolley@redhat.com>
820 Chris Demetriou <cgd@broadcom.com>
821
822 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
823 (sim_mach_default): New variable.
824 (mips64vr-*-*, mips64vrel-*-*): New configurations.
825 Add a new simulator generator, MULTI.
826 * configure: Regenerate.
827 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
828 (multi-run.o): New dependency.
829 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
830 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
831 (tmp-multi): Combine them.
832 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
833 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
834 (distclean-extra): New rule.
835 * sim-main.h: Include bfd.h.
836 (MIPS_MACH): New macro.
837 * mips.igen (vr4120, vr5400, vr5500): New models.
838 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
839 * vr.igen: Replace with new version.
840
e6c674b8
CD		 8412003-01-04 Chris Demetriou <cgd@broadcom.com>
842
843 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
844 * configure: Regenerate.
845
28f50ac8
CD		 8462002-12-31 Chris Demetriou <cgd@broadcom.com>
847
848 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
849 * mips.igen: Remove all invocations of check_branch_bug and
850 mark_branch_bug.
851
5071ffe6
CD		 8522002-12-16 Chris Demetriou <cgd@broadcom.com>
853
72f4393d 854 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
5071ffe6 855
06e7837e
CD		 8562002-07-30 Chris Demetriou <cgd@broadcom.com>
857
858 * mips.igen (do_load_double, do_store_double): New functions.
859 (LDC1, SDC1): Rename to...
860 (LDC1b, SDC1b): respectively.
861 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
862
2265c243
MS		 8632002-07-29 Michael Snyder <msnyder@redhat.com>
864
865 * cp1.c (fp_recip2): Modify initialization expression so that
866 GCC will recognize it as constant.
867
a2f8b4f3
CD		 8682002-06-18 Chris Demetriou <cgd@broadcom.com>
869
870 * mdmx.c (SD_): Delete.
871 (Unpredictable): Re-define, for now, to directly invoke
872 unpredictable_action().
873 (mdmx_acc_op): Fix error in .ob immediate handling.
874
b4b6c939
AC		 8752002-06-18 Andrew Cagney <cagney@redhat.com>
876
877 * interp.c (sim_firmware_command): Initialize `address'.
878
c8cca39f
AC		 8792002-06-16 Andrew Cagney <ac131313@redhat.com>
880
881 * configure: Regenerated to track ../common/aclocal.m4 changes.
882
e7e81181 8832002-06-14 Chris Demetriou <cgd@broadcom.com>
72f4393d 884 Ed Satterthwaite <ehs@broadcom.com>
e7e81181
CD		 885
886 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
887 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
888 * mips.igen: Include mips3d.igen.
889 (mips3d): New model name for MIPS-3D ASE instructions.
890 (CVT.W.fmt): Don't use this instruction for word (source) format
72f4393d 891 instructions.
e7e81181
CD		 892 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
893 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
894 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
895 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
896 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
897 (RSquareRoot1, RSquareRoot2): New macros.
898 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
899 (fp_rsqrt2): New functions.
900 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
901 * configure: Regenerate.
902
3a2b820e 9032002-06-13 Chris Demetriou <cgd@broadcom.com>
72f4393d 904 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 905
906 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
907 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
908 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
909 (convert): Note that this function is not used for paired-single
910 format conversions.
911 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
912 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
913 (check_fmt_p): Enable paired-single support.
914 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
915 (PUU.PS): New instructions.
916 (CVT.S.fmt): Don't use this instruction for paired-single format
917 destinations.
918 * sim-main.h (FP_formats): New value 'fmt_ps.'
919 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
920 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
921
d18ea9c2
CD		 9222002-06-12 Chris Demetriou <cgd@broadcom.com>
923
924 * mips.igen: Fix formatting of function calls in
925 many FP operations.
926
95fd5cee
CD		 9272002-06-12 Chris Demetriou <cgd@broadcom.com>
928
929 * mips.igen (MOVN, MOVZ): Trace result.
930 (TNEI): Print "tnei" as the opcode name in traces.
931 (CEIL.W): Add disassembly string for traces.
932 (RSQRT.fmt): Make location of disassembly string consistent
933 with other instructions.
934
4f0d55ae
CD		 9352002-06-12 Chris Demetriou <cgd@broadcom.com>
936
937 * mips.igen (X): Delete unused function.
938
3c25f8c7
AC		 9392002-06-08 Andrew Cagney <cagney@redhat.com>
940
941 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
942
f3c08b7e 9432002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 944 Ed Satterthwaite <ehs@broadcom.com>
f3c08b7e
CD		 945
946 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
947 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
948 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
949 (fp_nmsub): New prototypes.
950 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
951 (NegMultiplySub): New defines.
952 * mips.igen (RSQRT.fmt): Use RSquareRoot().
953 (MADD.D, MADD.S): Replace with...
954 (MADD.fmt): New instruction.
955 (MSUB.D, MSUB.S): Replace with...
956 (MSUB.fmt): New instruction.
957 (NMADD.D, NMADD.S): Replace with...
958 (NMADD.fmt): New instruction.
959 (NMSUB.D, MSUB.S): Replace with...
960 (NMSUB.fmt): New instruction.
961
52714ff9 9622002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 963 Ed Satterthwaite <ehs@broadcom.com>
52714ff9
CD		 964
965 * cp1.c: Fix more comment spelling and formatting.
966 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
967 (denorm_mode): New function.
968 (fpu_unary, fpu_binary): Round results after operation, collect
969 status from rounding operations, and update the FCSR.
970 (convert): Collect status from integer conversions and rounding
971 operations, and update the FCSR. Adjust NaN values that result
972 from conversions. Convert to use sim_io_eprintf rather than
973 fprintf, and remove some debugging code.
974 * cp1.h (fenr_FS): New define.
975
577d8c4b
CD		 9762002-06-07 Chris Demetriou <cgd@broadcom.com>
977
978 * cp1.c (convert): Remove unusable debugging code, and move MIPS
979 rounding mode to sim FP rounding mode flag conversion code into...
980 (rounding_mode): New function.
981
196496ed
CD		 9822002-06-07 Chris Demetriou <cgd@broadcom.com>
983
984 * cp1.c: Clean up formatting of a few comments.
985 (value_fpr): Reformat switch statement.
986
cfe9ea23 9872002-06-06 Chris Demetriou <cgd@broadcom.com>
72f4393d 988 Ed Satterthwaite <ehs@broadcom.com>
cfe9ea23
CD		 989
990 * cp1.h: New file.
991 * sim-main.h: Include cp1.h.
992 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
993 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
994 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
995 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
996 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
997 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
998 * cp1.c: Don't include sim-fpu.h; already included by
999 sim-main.h. Clean up formatting of some comments.
1000 (NaN, Equal, Less): Remove.
1001 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
1002 (fp_cmp): New functions.
1003 * mips.igen (do_c_cond_fmt): Remove.
1004 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
1005 Compare. Add result tracing.
1006 (CxC1): Remove, replace with...
1007 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
1008 (DMxC1): Remove, replace with...
1009 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
72f4393d
L		 1010 (MxC1): Remove, replace with...
1011 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
cfe9ea23 1012
ee7254b0
CD		 10132002-06-04 Chris Demetriou <cgd@broadcom.com>
1014
1015 * sim-main.h (FGRIDX): Remove, replace all uses with...
1016 (FGR_BASE): New macro.
1017 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
1018 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
1019 (NR_FGR, FGR): Likewise.
1020 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
1021 * mips.igen: Likewise.
1022
d3eb724f
CD		 10232002-06-04 Chris Demetriou <cgd@broadcom.com>
1024
1025 * cp1.c: Add an FSF Copyright notice to this file.
1026
ba46ddd0 10272002-06-04 Chris Demetriou <cgd@broadcom.com>
72f4393d 1028 Ed Satterthwaite <ehs@broadcom.com>
ba46ddd0
CD		 1029
1030 * cp1.c (Infinity): Remove.
1031 * sim-main.h (Infinity): Likewise.
1032
1033 * cp1.c (fp_unary, fp_binary): New functions.
1034 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
1035 (fp_sqrt): New functions, implemented in terms of the above.
1036 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1037 (Recip, SquareRoot): Remove (replaced by functions above).
1038 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
1039 (fp_recip, fp_sqrt): New prototypes.
1040 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1041 (Recip, SquareRoot): Replace prototypes with #defines which
1042 invoke the functions above.
72f4393d 1043
18d8a52d
CD		 10442002-06-03 Chris Demetriou <cgd@broadcom.com>
1045
1046 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
1047 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
1048 file, remove PARAMS from prototypes.
1049 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
1050 simulator state arguments.
1051 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
1052 pass simulator state arguments.
1053 * cp1.c (SD): Redefine as CPU_STATE(cpu).
1054 (store_fpr, convert): Remove 'sd' argument.
1055 (value_fpr): Likewise. Convert to use 'SD' instead.
1056
0f154cbd
CD		 10572002-06-03 Chris Demetriou <cgd@broadcom.com>
1058
1059 * cp1.c (Min, Max): Remove #if 0'd functions.
1060 * sim-main.h (Min, Max): Remove.
1061
e80fc152
CD		 10622002-06-03 Chris Demetriou <cgd@broadcom.com>
1063
1064 * cp1.c: fix formatting of switch case and default labels.
1065 * interp.c: Likewise.
1066 * sim-main.c: Likewise.
1067
bad673a9
CD		 10682002-06-03 Chris Demetriou <cgd@broadcom.com>
1069
1070 * cp1.c: Clean up comments which describe FP formats.
1071 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
1072
7cbea089 10732002-06-03 Chris Demetriou <cgd@broadcom.com>
72f4393d 1074 Ed Satterthwaite <ehs@broadcom.com>
7cbea089
CD		 1075
1076 * configure.in (mipsisa64sb1*-*-*): New target for supporting
1077 Broadcom SiByte SB-1 processor configurations.
1078 * configure: Regenerate.
1079 * sb1.igen: New file.
1080 * mips.igen: Include sb1.igen.
1081 (sb1): New model.
1082 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
1083 * mdmx.igen: Add "sb1" model to all appropriate functions and
1084 instructions.
1085 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
1086 (ob_func, ob_acc): Reference the above.
1087 (qh_acc): Adjust to keep the same size as ob_acc.
1088 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
1089 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
1090
909daa82
CD		 10912002-06-03 Chris Demetriou <cgd@broadcom.com>
1092
1093 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
1094
f4f1b9f1 10952002-06-02 Chris Demetriou <cgd@broadcom.com>
72f4393d 1096 Ed Satterthwaite <ehs@broadcom.com>
f4f1b9f1
CD		 1097
1098 * mips.igen (mdmx): New (pseudo-)model.
1099 * mdmx.c, mdmx.igen: New files.
1100 * Makefile.in (SIM_OBJS): Add mdmx.o.
1101 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
1102 New typedefs.
1103 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
1104 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
1105 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
1106 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
1107 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
1108 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
1109 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
1110 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
1111 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
1112 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
1113 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
1114 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
1115 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
1116 (qh_fmtsel): New macros.
1117 (_sim_cpu): New member "acc".
1118 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
1119 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
1120
5accf1ff
CD		 11212002-05-01 Chris Demetriou <cgd@broadcom.com>
1122
1123 * interp.c: Use 'deprecated' rather than 'depreciated.'
1124 * sim-main.h: Likewise.
1125
402586aa
CD		 11262002-05-01 Chris Demetriou <cgd@broadcom.com>
1127
1128 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
1129 which wouldn't compile anyway.
1130 * sim-main.h (unpredictable_action): New function prototype.
1131 (Unpredictable): Define to call igen function unpredictable().
1132 (NotWordValue): New macro to call igen function not_word_value().
1133 (UndefinedResult): Remove.
1134 * interp.c (undefined_result): Remove.
1135 (unpredictable_action): New function.
1136 * mips.igen (not_word_value, unpredictable): New functions.
1137 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
1138 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
1139 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
1140 NotWordValue() to check for unpredictable inputs, then
1141 Unpredictable() to handle them.
1142
c9b9995a
CD		 11432002-02-24 Chris Demetriou <cgd@broadcom.com>
1144
1145 * mips.igen: Fix formatting of calls to Unpredictable().
1146
e1015982
AC		 11472002-04-20 Andrew Cagney <ac131313@redhat.com>
1148
1149 * interp.c (sim_open): Revert previous change.
1150
b882a66b
AO		 11512002-04-18 Alexandre Oliva <aoliva@redhat.com>
1152
1153 * interp.c (sim_open): Disable chunk of code that wrote code in
1154 vector table entries.
1155
c429b7dd
CD		 11562002-03-19 Chris Demetriou <cgd@broadcom.com>
1157
1158 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
1159 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
1160 unused definitions.
1161
37d146fa
CD		 11622002-03-19 Chris Demetriou <cgd@broadcom.com>
1163
1164 * cp1.c: Fix many formatting issues.
1165
07892c0b
CD		 11662002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1167
1168 * cp1.c (fpu_format_name): New function to replace...
1169 (DOFMT): This. Delete, and update all callers.
1170 (fpu_rounding_mode_name): New function to replace...
1171 (RMMODE): This. Delete, and update all callers.
1172
487f79b7
CD		 11732002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1174
1175 * interp.c: Move FPU support routines from here to...
1176 * cp1.c: Here. New file.
1177 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
1178 (cp1.o): New target.
1179
1e799e28
CD		 11802002-03-12 Chris Demetriou <cgd@broadcom.com>
1181
1182 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
1183 * mips.igen (mips32, mips64): New models, add to all instructions
1184 and functions as appropriate.
1185 (loadstore_ea, check_u64): New variant for model mips64.
1186 (check_fmt_p): New variant for models mipsV and mips64, remove
1187 mipsV model marking fro other variant.
1188 (SLL) Rename to...
1189 (SLLa) this.
1190 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
1191 for mips32 and mips64.
1192 (DCLO, DCLZ): New instructions for mips64.
1193
82f728db
CD		 11942002-03-07 Chris Demetriou <cgd@broadcom.com>
1195
1196 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
1197 immediate or code as a hex value with the "%#lx" format.
1198 (ANDI): Likewise, and fix printed instruction name.
1199
b96e7ef1
CD		 12002002-03-05 Chris Demetriou <cgd@broadcom.com>
1201
1202 * sim-main.h (UndefinedResult, Unpredictable): New macros
1203 which currently do nothing.
1204
d35d4f70
CD		 12052002-03-05 Chris Demetriou <cgd@broadcom.com>
1206
1207 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
1208 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
1209 (status_CU3): New definitions.
1210
1211 * sim-main.h (ExceptionCause): Add new values for MIPS32
1212 and MIPS64: MDMX, MCheck, CacheErr. Update comments
1213 for DebugBreakPoint and NMIReset to note their status in
1214 MIPS32 and MIPS64.
1215 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
1216 (SignalExceptionCacheErr): New exception macros.
1217
3ad6f714
CD		 12182002-03-05 Chris Demetriou <cgd@broadcom.com>
1219
1220 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
1221 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
1222 is always enabled.
1223 (SignalExceptionCoProcessorUnusable): Take as argument the
1224 unusable coprocessor number.
1225
86b77b47
CD		 12262002-03-05 Chris Demetriou <cgd@broadcom.com>
1227
1228 * mips.igen: Fix formatting of all SignalException calls.
1229
97a88e93 12302002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 1231
1232 * sim-main.h (SIGNEXTEND): Remove.
1233
97a88e93 12342002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 1235
1236 * mips.igen: Remove gencode comment from top of file, fix
1237 spelling in another comment.
1238
97a88e93 12392002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 1240
1241 * mips.igen (check_fmt, check_fmt_p): New functions to check
1242 whether specific floating point formats are usable.
1243 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1244 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
1245 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
1246 Use the new functions.
1247 (do_c_cond_fmt): Remove format checks...
1248 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
1249
97a88e93 12502002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 1251
1252 * mips.igen: Fix formatting of check_fpu calls.
1253
41774c9d
CD		 12542002-03-03 Chris Demetriou <cgd@broadcom.com>
1255
1256 * mips.igen (FLOOR.L.fmt): Store correct destination register.
1257
4a0bd876
CD		 12582002-03-03 Chris Demetriou <cgd@broadcom.com>
1259
1260 * mips.igen: Remove whitespace at end of lines.
1261
09297648
CD		 12622002-03-02 Chris Demetriou <cgd@broadcom.com>
1263
1264 * mips.igen (loadstore_ea): New function to do effective
1265 address calculations.
1266 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
1267 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
1268 CACHE): Use loadstore_ea to do effective address computations.
1269
043b7057
CD		 12702002-03-02 Chris Demetriou <cgd@broadcom.com>
1271
1272 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
1273 * mips.igen (LL, CxC1, MxC1): Likewise.
1274
c1e8ada4
CD		 12752002-03-02 Chris Demetriou <cgd@broadcom.com>
1276
1277 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
1278 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
1279 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
1280 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
1281 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
1282 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
1283 Don't split opcode fields by hand, use the opcode field values
1284 provided by igen.
1285
3e1dca16
CD		 12862002-03-01 Chris Demetriou <cgd@broadcom.com>
1287
1288 * mips.igen (do_divu): Fix spacing.
1289
1290 * mips.igen (do_dsllv): Move to be right before DSLLV,
1291 to match the rest of the do_<shift> functions.
1292
fff8d27d
CD		 12932002-03-01 Chris Demetriou <cgd@broadcom.com>
1294
1295 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
1296 DSRL32, do_dsrlv): Trace inputs and results.
1297
0d3e762b
CD		 12982002-03-01 Chris Demetriou <cgd@broadcom.com>
1299
1300 * mips.igen (CACHE): Provide instruction-printing string.
1301
1302 * interp.c (signal_exception): Comment tokens after #endif.
1303
eb5fcf93
CD		 13042002-02-28 Chris Demetriou <cgd@broadcom.com>
1305
1306 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
72f4393d
L		 1307 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
1308 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
1309 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
1310 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
1311 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
1312 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
eb5fcf93
CD		 1313 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
1314
bb22bd7d
CD		 13152002-02-28 Chris Demetriou <cgd@broadcom.com>
1316
1317 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
1318 instruction-printing string.
1319 (LWU): Use '64' as the filter flag.
1320
91a177cf
CD		 13212002-02-28 Chris Demetriou <cgd@broadcom.com>
1322
1323 * mips.igen (SDXC1): Fix instruction-printing string.
1324
387f484a
CD		 13252002-02-28 Chris Demetriou <cgd@broadcom.com>
1326
1327 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
1328 filter flags "32,f".
1329
3d81f391
CD		 13302002-02-27 Chris Demetriou <cgd@broadcom.com>
1331
1332 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1333 as the filter flag.
1334
af5107af
CD		 13352002-02-27 Chris Demetriou <cgd@broadcom.com>
1336
1337 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1338 add a comma) so that it more closely match the MIPS ISA
1339 documentation opcode partitioning.
1340 (PREF): Put useful names on opcode fields, and include
1341 instruction-printing string.
1342
ca971540
CD		 13432002-02-27 Chris Demetriou <cgd@broadcom.com>
1344
1345 * mips.igen (check_u64): New function which in the future will
1346 check whether 64-bit instructions are usable and signal an
1347 exception if not. Currently a no-op.
1348 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1349 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1350 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1351 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1352
1353 * mips.igen (check_fpu): New function which in the future will
1354 check whether FPU instructions are usable and signal an exception
1355 if not. Currently a no-op.
1356 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1357 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1358 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1359 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1360 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1361 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1362 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1363 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1364
1c47a468
CD		 13652002-02-27 Chris Demetriou <cgd@broadcom.com>
1366
1367 * mips.igen (do_load_left, do_load_right): Move to be immediately
1368 following do_load.
1369 (do_store_left, do_store_right): Move to be immediately following
1370 do_store.
1371
603a98e7
CD		 13722002-02-27 Chris Demetriou <cgd@broadcom.com>
1373
1374 * mips.igen (mipsV): New model name. Also, add it to
1375 all instructions and functions where it is appropriate.
1376
c5d00cc7
CD		 13772002-02-18 Chris Demetriou <cgd@broadcom.com>
1378
1379 * mips.igen: For all functions and instructions, list model
1380 names that support that instruction one per line.
1381
074e9cb8
CD		 13822002-02-11 Chris Demetriou <cgd@broadcom.com>
1383
1384 * mips.igen: Add some additional comments about supported
1385 models, and about which instructions go where.
1386 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1387 order as is used in the rest of the file.
1388
9805e229
CD		 13892002-02-11 Chris Demetriou <cgd@broadcom.com>
1390
1391 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1392 indicating that ALU32_END or ALU64_END are there to check
1393 for overflow.
1394 (DADD): Likewise, but also remove previous comment about
1395 overflow checking.
1396
f701dad2
CD		 13972002-02-10 Chris Demetriou <cgd@broadcom.com>
1398
1399 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1400 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1401 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1402 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1403 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1404 fields (i.e., add and move commas) so that they more closely
1405 match the MIPS ISA documentation opcode partitioning.
1406
14072002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098 1408
72f4393d
L		 1409 * mips.igen (ADDI): Print immediate value.
1410 (BREAK): Print code.
1411 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1412 (SLL): Print "nop" specially, and don't run the code
1413 that does the shift for the "nop" case.
20ae0098 1414
9e52972e
FF		 14152001-11-17 Fred Fish <fnf@redhat.com>
1416
1417 * sim-main.h (float_operation): Move enum declaration outside
1418 of _sim_cpu struct declaration.
1419
c0efbca4
JB		 14202001-04-12 Jim Blandy <jimb@redhat.com>
1421
1422 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1423 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1424 set of the FCSR.
1425 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1426 PENDING_FILL, and you can get the intended effect gracefully by
1427 calling PENDING_SCHED directly.
1428
fb891446
BE		 14292001-02-23 Ben Elliston <bje@redhat.com>
1430
1431 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1432 already defined elsewhere.
1433
8030f857
BE		 14342001-02-19 Ben Elliston <bje@redhat.com>
1435
1436 * sim-main.h (sim_monitor): Return an int.
1437 * interp.c (sim_monitor): Add return values.
1438 (signal_exception): Handle error conditions from sim_monitor.
1439
56b48a7a
CD		 14402001-02-08 Ben Elliston <bje@redhat.com>
1441
1442 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1443 (store_memory): Likewise, pass cia to sim_core_write*.
1444
d3ee60d9
FCE		 14452000-10-19 Frank Ch. Eigler <fche@redhat.com>
1446
1447 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1448 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1449
071da002
AC		 1450Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1451
1452 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1453 * Makefile.in: Don't delete *.igen when cleaning directory.
1454
a28c02cd
AC		 1455Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1456
1457 * m16.igen (break): Call SignalException not sim_engine_halt.
1458
80ee11fa
AC		 1459Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1460
1461 From Jason Eckhardt:
1462 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1463
673388c0
AC		 1464Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1465
1466 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1467
4c0deff4
NC		 14682000-05-24 Michael Hayes <mhayes@cygnus.com>
1469
1470 * mips.igen (do_dmultx): Fix typo.
1471
eb2d80b4
AC		 1472Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1473
1474 * configure: Regenerated to track ../common/aclocal.m4 changes.
1475
dd37a34b
AC		 1476Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1477
1478 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1479
4c0deff4
NC		 14802000-04-12 Frank Ch. Eigler <fche@redhat.com>
1481
1482 * sim-main.h (GPR_CLEAR): Define macro.
1483
e30db738
AC		 1484Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1485
1486 * interp.c (decode_coproc): Output long using %lx and not %s.
1487
cb7450ea
FCE		 14882000-03-21 Frank Ch. Eigler <fche@redhat.com>
1489
1490 * interp.c (sim_open): Sort & extend dummy memory regions for
1491 --board=jmr3904 for eCos.
1492
a3027dd7
FCE		 14932000-03-02 Frank Ch. Eigler <fche@redhat.com>
1494
1495 * configure: Regenerated.
1496
1497Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1498
1499 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1500 calls, conditional on the simulator being in verbose mode.
1501
dfcd3bfb
JM		 1502Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1503
1504 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1505 cache don't get ReservedInstruction traps.
1506
c2d11a7d
JM		 15071999-11-29 Mark Salter <msalter@cygnus.com>
1508
1509 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1510 to clear status bits in sdisr register. This is how the hardware works.
1511
1512 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1513 being used by cygmon.
1514
4ce44c66
JM		 15151999-11-11 Andrew Haley <aph@cygnus.com>
1516
1517 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1518 instructions.
1519
cff3e48b
JM		 1520Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1521
1522 * mips.igen (MULT): Correct previous mis-applied patch.
1523
d4f3574e
SS		 1524Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1525
1526 * mips.igen (delayslot32): Handle sequence like
1527 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1528 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1529 (MULT): Actually pass the third register...
1530
15311999-09-03 Mark Salter <msalter@cygnus.com>
1532
1533 * interp.c (sim_open): Added more memory aliases for additional
1534 hardware being touched by cygmon on jmr3904 board.
1535
1536Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1537
1538 * configure: Regenerated to track ../common/aclocal.m4 changes.
1539
a0b3c4fd
JM		 1540Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1541
1542 * interp.c (sim_store_register): Handle case where client - GDB -
1543 specifies that a 4 byte register is 8 bytes in size.
1544 (sim_fetch_register): Ditto.
72f4393d 1545
adf40b2e
JM		 15461999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1547
1548 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1549 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1550 (idt_monitor_base): Base address for IDT monitor traps.
1551 (pmon_monitor_base): Ditto for PMON.
1552 (lsipmon_monitor_base): Ditto for LSI PMON.
1553 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1554 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1555 (sim_firmware_command): New function.
1556 (mips_option_handler): Call it for OPTION_FIRMWARE.
1557 (sim_open): Allocate memory for idt_monitor region. If "--board"
1558 option was given, add no monitor by default. Add BREAK hooks only if
1559 monitors are also there.
72f4393d 1560
43e526b9
JM		 1561Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1562
1563 * interp.c (sim_monitor): Flush output before reading input.
1564
1565Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1566
1567 * tconfig.in (SIM_HANDLES_LMA): Always define.
1568
1569Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1570
1571 From Mark Salter <msalter@cygnus.com>:
1572 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1573 (sim_open): Add setup for BSP board.
1574
9846de1b
JM		 1575Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1576
1577 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1578 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1579 them as unimplemented.
1580
cd0fc7c3
SS		 15811999-05-08 Felix Lee <flee@cygnus.com>
1582
1583 * configure: Regenerated to track ../common/aclocal.m4 changes.
72f4393d 1584
7a292a7a
SS		 15851999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1586
1587 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1588
1589Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1590
1591 * configure.in: Any mips64vr5*-*-* target should have
1592 -DTARGET_ENABLE_FR=1.
1593 (default_endian): Any mips64vr*el-*-* target should default to
1594 LITTLE_ENDIAN.
1595 * configure: Re-generate.
1596
15971999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1598
1599 * mips.igen (ldl): Extend from _16_, not 32.
1600
1601Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1602
1603 * interp.c (sim_store_register): Force registers written to by GDB
1604 into an un-interpreted state.
1605
c906108c
SS		 16061999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1607
1608 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1609 CPU, start periodic background I/O polls.
72f4393d 1610 (tx3904sio_poll): New function: periodic I/O poller.
c906108c
SS		 1611
16121998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1613
1614 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
72f4393d 1615
c906108c
SS		 1616Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1617
1618 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1619 case statement.
1620
16211998-12-29 Frank Ch. Eigler <fche@cygnus.com>
72f4393d
L		 1622
1623 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
c906108c
SS		 1624 (load_word): Call SIM_CORE_SIGNAL hook on error.
1625 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1626 starting. For exception dispatching, pass PC instead of NULL_CIA.
1627 (decode_coproc): Use COP0_BADVADDR to store faulting address.
72f4393d 1628 * sim-main.h (COP0_BADVADDR): Define.
c906108c
SS		 1629 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1630 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
72f4393d 1631 (_sim_cpu): Add exc_* fields to store register value snapshots.
c906108c
SS		 1632 * mips.igen (*): Replace memory-related SignalException* calls
1633 with references to SIM_CORE_SIGNAL hook.
72f4393d 1634
c906108c
SS		 1635 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1636 fix.
1637 * sim-main.c (*): Minor warning cleanups.
72f4393d 1638
c906108c
SS		 16391998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1640
1641 * m16.igen (DADDIU5): Correct type-o.
1642
1643Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1644
1645 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1646 variables.
1647
1648Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1649
1650 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1651 to include path.
1652 (interp.o): Add dependency on itable.h
1653 (oengine.c, gencode): Delete remaining references.
1654 (BUILT_SRC_FROM_GEN): Clean up.
72f4393d 1655
c906108c 16561998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
72f4393d 1657
c906108c
SS		 1658 * vr4run.c: New.
1659 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1660 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1661 tmp-run-hack) : New.
1662 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
72f4393d 1663 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
c906108c
SS		 1664 Drop the "64" qualifier to get the HACK generator working.
1665 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1666 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1667 qualifier to get the hack generator working.
1668 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1669 (DSLL): Use do_dsll.
1670 (DSLLV): Use do_dsllv.
1671 (DSRA): Use do_dsra.
1672 (DSRL): Use do_dsrl.
1673 (DSRLV): Use do_dsrlv.
1674 (BC1): Move *vr4100 to get the HACK generator working.
72f4393d 1675 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
c906108c
SS		 1676 get the HACK generator working.
1677 (MACC) Rename to get the HACK generator working.
1678 (DMACC,MACCS,DMACCS): Add the 64.
72f4393d 1679
c906108c
SS		 16801998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1681
1682 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1683 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
72f4393d 1684
c906108c
SS		 16851998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1686
1687 * mips/interp.c (DEBUG): Cleanups.
1688
16891998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1690
1691 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1692 (tx3904sio_tickle): fflush after a stdout character output.
72f4393d 1693
c906108c
SS		 16941998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1695
1696 * interp.c (sim_close): Uninstall modules.
1697
1698Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1699
1700 * sim-main.h, interp.c (sim_monitor): Change to global
1701 function.
1702
1703Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1704
1705 * configure.in (vr4100): Only include vr4100 instructions in
1706 simulator.
1707 * configure: Re-generate.
1708 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1709
1710Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1711
1712 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1713 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1714 true alternative.
1715
1716 * configure.in (sim_default_gen, sim_use_gen): Replace with
1717 sim_gen.
1718 (--enable-sim-igen): Delete config option. Always using IGEN.
1719 * configure: Re-generate.
72f4393d 1720
c906108c
SS		 1721 * Makefile.in (gencode): Kill, kill, kill.
1722 * gencode.c: Ditto.
72f4393d 1723
c906108c
SS		 1724Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1725
1726 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1727 bit mips16 igen simulator.
1728 * configure: Re-generate.
1729
1730 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1731 as part of vr4100 ISA.
1732 * vr.igen: Mark all instructions as 64 bit only.
1733
1734Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1735
1736 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1737 Pacify GCC.
1738
1739Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1740
1741 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1742 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1743 * configure: Re-generate.
1744
1745 * m16.igen (BREAK): Define breakpoint instruction.
1746 (JALX32): Mark instruction as mips16 and not r3900.
1747 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1748
1749 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1750
1751Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1752
1753 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1754 insn as a debug breakpoint.
1755
1756 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1757 pending.slot_size.
1758 (PENDING_SCHED): Clean up trace statement.
1759 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1760 (PENDING_FILL): Delay write by only one cycle.
1761 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1762
1763 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1764 of pending writes.
1765 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1766 32 & 64.
1767 (pending_tick): Move incrementing of index to FOR statement.
1768 (pending_tick): Only update PENDING_OUT after a write has occured.
72f4393d 1769
c906108c
SS		 1770 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1771 build simulator.
1772 * configure: Re-generate.
72f4393d 1773
c906108c
SS		 1774 * interp.c (sim_engine_run OLD): Delete explicit call to
1775 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
72f4393d 1776
c906108c
SS		 1777Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1778
1779 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1780 interrupt level number to match changed SignalExceptionInterrupt
1781 macro.
1782
1783Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1784
1785 * interp.c: #include "itable.h" if WITH_IGEN.
1786 (get_insn_name): New function.
1787 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1788 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1789
1790Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1791
1792 * configure: Rebuilt to inhale new common/aclocal.m4.
1793
1794Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1795
1796 * dv-tx3904sio.c: Include sim-assert.h.
1797
1798Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1799
1800 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1801 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1802 Reorganize target-specific sim-hardware checks.
1803 * configure: rebuilt.
1804 * interp.c (sim_open): For tx39 target boards, set
1805 OPERATING_ENVIRONMENT, add tx3904sio devices.
1806 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1807 ROM executables. Install dv-sockser into sim-modules list.
72f4393d 1808
c906108c
SS		 1809 * dv-tx3904irc.c: Compiler warning clean-up.
1810 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1811 frequent hw-trace messages.
1812
1813Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1814
1815 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1816
1817Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1818
1819 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1820
1821 * vr.igen: New file.
1822 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1823 * mips.igen: Define vr4100 model. Include vr.igen.
1824Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1825
1826 * mips.igen (check_mf_hilo): Correct check.
1827
1828Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1829
1830 * sim-main.h (interrupt_event): Add prototype.
1831
1832 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1833 register_ptr, register_value.
1834 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1835
1836 * sim-main.h (tracefh): Make extern.
1837
1838Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1839
1840 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
72f4393d 1841 Reduce unnecessarily high timer event frequency.
c906108c 1842 * dv-tx3904cpu.c: Ditto for interrupt event.
72f4393d 1843
c906108c
SS		 1844Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1845
1846 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1847 to allay warnings.
1848 (interrupt_event): Made non-static.
72f4393d 1849
c906108c
SS		 1850 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1851 interchange of configuration values for external vs. internal
1852 clock dividers.
72f4393d 1853
c906108c
SS		 1854Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1855
72f4393d 1856 * mips.igen (BREAK): Moved code to here for
c906108c
SS		 1857 simulator-reserved break instructions.
1858 * gencode.c (build_instruction): Ditto.
1859 * interp.c (signal_exception): Code moved from here. Non-
72f4393d 1860 reserved instructions now use exception vector, rather
c906108c
SS		 1861 than halting sim.
1862 * sim-main.h: Moved magic constants to here.
1863
1864Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1865
1866 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1867 register upon non-zero interrupt event level, clear upon zero
1868 event value.
1869 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1870 by passing zero event value.
1871 (*_io_{read,write}_buffer): Endianness fixes.
1872 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1873 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1874
1875 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1876 serial I/O and timer module at base address 0xFFFF0000.
72f4393d 1877
c906108c
SS		 1878Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1879
72f4393d 1880 * mips.igen (SWC1) : Correct the handling of ReverseEndian
c906108c
SS		 1881 and BigEndianCPU.
1882
1883Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1884
1885 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1886 parts.
1887 * configure: Update.
1888
1889Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1890
1891 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1892 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1893 * configure.in: Include tx3904tmr in hw_device list.
1894 * configure: Rebuilt.
1895 * interp.c (sim_open): Instantiate three timer instances.
1896 Fix address typo of tx3904irc instance.
1897
1898Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1899
1900 * interp.c (signal_exception): SystemCall exception now uses
1901 the exception vector.
1902
1903Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1904
1905 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1906 to allay warnings.
1907
1908Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1909
1910 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1911
1912Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1913
1914 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1915
1916 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1917 sim-main.h. Declare a struct hw_descriptor instead of struct
1918 hw_device_descriptor.
1919
1920Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1921
1922 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1923 right bits and then re-align left hand bytes to correct byte
1924 lanes. Fix incorrect computation in do_store_left when loading
1925 bytes from second word.
1926
1927Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1928
1929 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1930 * interp.c (sim_open): Only create a device tree when HW is
1931 enabled.
1932
1933 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1934 * interp.c (signal_exception): Ditto.
1935
1936Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1937
1938 * gencode.c: Mark BEGEZALL as LIKELY.
1939
1940Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1941
1942 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1943 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
72f4393d 1944
c906108c
SS		 1945Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1946
1947 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1948 modules. Recognize TX39 target with "mips*tx39" pattern.
1949 * configure: Rebuilt.
1950 * sim-main.h (*): Added many macros defining bits in
1951 TX39 control registers.
1952 (SignalInterrupt): Send actual PC instead of NULL.
1953 (SignalNMIReset): New exception type.
1954 * interp.c (board): New variable for future use to identify
1955 a particular board being simulated.
1956 (mips_option_handler,mips_options): Added "--board" option.
1957 (interrupt_event): Send actual PC.
1958 (sim_open): Make memory layout conditional on board setting.
1959 (signal_exception): Initial implementation of hardware interrupt
1960 handling. Accept another break instruction variant for simulator
1961 exit.
1962 (decode_coproc): Implement RFE instruction for TX39.
1963 (mips.igen): Decode RFE instruction as such.
1964 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1965 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1966 bbegin to implement memory map.
1967 * dv-tx3904cpu.c: New file.
1968 * dv-tx3904irc.c: New file.
1969
1970Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1971
1972 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1973
1974Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1975
1976 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1977 with calls to check_div_hilo.
1978
1979Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1980
1981 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1982 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
72f4393d 1983 Add special r3900 version of do_mult_hilo.
c906108c
SS		 1984 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1985 with calls to check_mult_hilo.
1986 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1987 with calls to check_div_hilo.
1988
1989Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1990
1991 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1992 Document a replacement.
1993
1994Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1995
1996 * interp.c (sim_monitor): Make mon_printf work.
1997
1998Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1999
2000 * sim-main.h (INSN_NAME): New arg `cpu'.
2001
2002Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
2003
72f4393d 2004 * configure: Regenerated to track ../common/aclocal.m4 changes.
c906108c
SS		 2005
2006Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
2007
2008 * configure: Regenerated to track ../common/aclocal.m4 changes.
2009 * config.in: Ditto.
2010
2011Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
2012
2013 * acconfig.h: New file.
2014 * configure.in: Reverted change of Apr 24; use sinclude again.
2015
2016Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
2017
2018 * configure: Regenerated to track ../common/aclocal.m4 changes.
2019 * config.in: Ditto.
2020
2021Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
2022
2023 * configure.in: Don't call sinclude.
2024
2025Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
2026
2027 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
2028
2029Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2030
2031 * mips.igen (ERET): Implement.
2032
2033 * interp.c (decode_coproc): Return sign-extended EPC.
2034
2035 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
2036
2037 * interp.c (signal_exception): Do not ignore Trap.
2038 (signal_exception): On TRAP, restart at exception address.
2039 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
2040 (signal_exception): Update.
2041 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
2042 so that TRAP instructions are caught.
2043
2044Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
2045
2046 * sim-main.h (struct hilo_access, struct hilo_history): Define,
2047 contains HI/LO access history.
2048 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
2049 (HIACCESS, LOACCESS): Delete, replace with
2050 (HIHISTORY, LOHISTORY): New macros.
2051 (CHECKHILO): Delete all, moved to mips.igen
72f4393d 2052
c906108c
SS		 2053 * gencode.c (build_instruction): Do not generate checks for
2054 correct HI/LO register usage.
2055
2056 * interp.c (old_engine_run): Delete checks for correct HI/LO
2057 register usage.
2058
2059 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
2060 check_mf_cycles): New functions.
2061 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
2062 do_divu, domultx, do_mult, do_multu): Use.
2063
2064 * tx.igen ("madd", "maddu"): Use.
72f4393d 2065
c906108c
SS		 2066Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
2067
2068 * mips.igen (DSRAV): Use function do_dsrav.
2069 (SRAV): Use new function do_srav.
2070
2071 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
2072 (B): Sign extend 11 bit immediate.
2073 (EXT-B*): Shift 16 bit immediate left by 1.
2074 (ADDIU*): Don't sign extend immediate value.
2075
2076Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2077
2078 * m16run.c (sim_engine_run): Restore CIA after handling an event.
2079
2080 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
2081 functions.
2082
2083 * mips.igen (delayslot32, nullify_next_insn): New functions.
2084 (m16.igen): Always include.
2085 (do_*): Add more tracing.
2086
2087 * m16.igen (delayslot16): Add NIA argument, could be called by a
2088 32 bit MIPS16 instruction.
72f4393d 2089
c906108c
SS		 2090 * interp.c (ifetch16): Move function from here.
2091 * sim-main.c (ifetch16): To here.
72f4393d 2092
c906108c
SS		 2093 * sim-main.c (ifetch16, ifetch32): Update to match current
2094 implementations of LH, LW.
2095 (signal_exception): Don't print out incorrect hex value of illegal
2096 instruction.
2097
2098Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2099
2100 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
2101 instruction.
2102
2103 * m16.igen: Implement MIPS16 instructions.
72f4393d 2104
c906108c
SS		 2105 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
2106 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
2107 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
2108 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
2109 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
2110 bodies of corresponding code from 32 bit insn to these. Also used
2111 by MIPS16 versions of functions.
72f4393d 2112
c906108c
SS		 2113 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
2114 (IMEM16): Drop NR argument from macro.
2115
2116Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2117
2118 * Makefile.in (SIM_OBJS): Add sim-main.o.
2119
2120 * sim-main.h (address_translation, load_memory, store_memory,
2121 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
2122 as INLINE_SIM_MAIN.
2123 (pr_addr, pr_uword64): Declare.
2124 (sim-main.c): Include when H_REVEALS_MODULE_P.
72f4393d 2125
c906108c
SS		 2126 * interp.c (address_translation, load_memory, store_memory,
2127 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
2128 from here.
2129 * sim-main.c: To here. Fix compilation problems.
72f4393d 2130
c906108c
SS		 2131 * configure.in: Enable inlining.
2132 * configure: Re-config.
2133
2134Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2135
2136 * configure: Regenerated to track ../common/aclocal.m4 changes.
2137
2138Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2139
2140 * mips.igen: Include tx.igen.
2141 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
2142 * tx.igen: New file, contains MADD and MADDU.
2143
2144 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
2145 the hardwired constant `7'.
2146 (store_memory): Ditto.
2147 (LOADDRMASK): Move definition to sim-main.h.
2148
2149 mips.igen (MTC0): Enable for r3900.
2150 (ADDU): Add trace.
2151
2152 mips.igen (do_load_byte): Delete.
2153 (do_load, do_store, do_load_left, do_load_write, do_store_left,
2154 do_store_right): New functions.
2155 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
2156
2157 configure.in: Let the tx39 use igen again.
2158 configure: Update.
72f4393d 2159
c906108c
SS		 2160Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2161
2162 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
2163 not an address sized quantity. Return zero for cache sizes.
2164
2165Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
2166
2167 * mips.igen (r3900): r3900 does not support 64 bit integer
2168 operations.
2169
2170Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
2171
2172 * configure.in (mipstx39*-*-*): Use gencode simulator rather
2173 than igen one.
2174 * configure : Rebuild.
72f4393d 2175
c906108c
SS		 2176Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
2177
2178 * configure: Regenerated to track ../common/aclocal.m4 changes.
2179
2180Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2181
2182 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
2183
2184Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
2185
2186 * configure: Regenerated to track ../common/aclocal.m4 changes.
2187 * config.in: Regenerated to track ../common/aclocal.m4 changes.
2188
2189Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2190
2191 * configure: Regenerated to track ../common/aclocal.m4 changes.
2192
2193Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
2194
2195 * interp.c (Max, Min): Comment out functions. Not yet used.
2196
2197Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
2198
2199 * configure: Regenerated to track ../common/aclocal.m4 changes.
2200
2201Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
2202
2203 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
2204 configurable settings for stand-alone simulator.
72f4393d 2205
c906108c 2206 * configure.in: Added X11 search, just in case.
72f4393d 2207
c906108c
SS		 2208 * configure: Regenerated.
2209
2210Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
2211
2212 * interp.c (sim_write, sim_read, load_memory, store_memory):
2213 Replace sim_core_*_map with read_map, write_map, exec_map resp.
2214
2215Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
2216
2217 * sim-main.h (GETFCC): Return an unsigned value.
2218
2219Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2220
2221 * mips.igen (DIV): Fix check for -1 / MIN_INT.
2222 (DADD): Result destination is RD not RT.
2223
2224Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2225
2226 * sim-main.h (HIACCESS, LOACCESS): Always define.
2227
2228 * mdmx.igen (Maxi, Mini): Rename Max, Min.
2229
2230 * interp.c (sim_info): Delete.
2231
2232Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
2233
2234 * interp.c (DECLARE_OPTION_HANDLER): Use it.
2235 (mips_option_handler): New argument `cpu'.
2236 (sim_open): Update call to sim_add_option_table.
2237
2238Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
2239
2240 * mips.igen (CxC1): Add tracing.
2241
2242Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
2243
2244 * sim-main.h (Max, Min): Declare.
2245
2246 * interp.c (Max, Min): New functions.
2247
2248 * mips.igen (BC1): Add tracing.
72f4393d 2249
c906108c 2250Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
72f4393d 2251
c906108c 2252 * interp.c Added memory map for stack in vr4100
72f4393d 2253
c906108c
SS		 2254Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
2255
2256 * interp.c (load_memory): Add missing "break"'s.
2257
2258Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2259
2260 * interp.c (sim_store_register, sim_fetch_register): Pass in
2261 length parameter. Return -1.
2262
2263Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
2264
2265 * interp.c: Added hardware init hook, fixed warnings.
2266
2267Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2268
2269 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
2270
2271Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
2272
2273 * interp.c (ifetch16): New function.
2274
2275 * sim-main.h (IMEM32): Rename IMEM.
2276 (IMEM16_IMMED): Define.
2277 (IMEM16): Define.
2278 (DELAY_SLOT): Update.
72f4393d 2279
c906108c 2280 * m16run.c (sim_engine_run): New file.
72f4393d 2281
c906108c
SS		 2282 * m16.igen: All instructions except LB.
2283 (LB): Call do_load_byte.
2284 * mips.igen (do_load_byte): New function.
2285 (LB): Call do_load_byte.
2286
2287 * mips.igen: Move spec for insn bit size and high bit from here.
2288 * Makefile.in (tmp-igen, tmp-m16): To here.
2289
2290 * m16.dc: New file, decode mips16 instructions.
2291
2292 * Makefile.in (SIM_NO_ALL): Define.
2293 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
2294
2295Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
2296
2297 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
2298 point unit to 32 bit registers.
2299 * configure: Re-generate.
2300
2301Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2302
2303 * configure.in (sim_use_gen): Make IGEN the default simulator
2304 generator for generic 32 and 64 bit mips targets.
2305 * configure: Re-generate.
2306
2307Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2308
2309 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
2310 bitsize.
2311
2312 * interp.c (sim_fetch_register, sim_store_register): Read/write
2313 FGR from correct location.
2314 (sim_open): Set size of FGR's according to
2315 WITH_TARGET_FLOATING_POINT_BITSIZE.
72f4393d 2316
c906108c
SS		 2317 * sim-main.h (FGR): Store floating point registers in a separate
2318 array.
2319
2320Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
2321
2322 * configure: Regenerated to track ../common/aclocal.m4 changes.
2323
2324Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2325
2326 * interp.c (ColdReset): Call PENDING_INVALIDATE.
2327
2328 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
2329
2330 * interp.c (pending_tick): New function. Deliver pending writes.
2331
2332 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2333 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2334 it can handle mixed sized quantites and single bits.
72f4393d 2335
c906108c
SS		 2336Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2337
2338 * interp.c (oengine.h): Do not include when building with IGEN.
2339 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2340 (sim_info): Ditto for PROCESSOR_64BIT.
2341 (sim_monitor): Replace ut_reg with unsigned_word.
2342 (*): Ditto for t_reg.
2343 (LOADDRMASK): Define.
2344 (sim_open): Remove defunct check that host FP is IEEE compliant,
2345 using software to emulate floating point.
2346 (value_fpr, ...): Always compile, was conditional on HASFPU.
2347
2348Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2349
2350 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2351 size.
2352
2353 * interp.c (SD, CPU): Define.
2354 (mips_option_handler): Set flags in each CPU.
2355 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2356 (sim_close): Do not clear STATE, deleted anyway.
2357 (sim_write, sim_read): Assume CPU zero's vm should be used for
2358 data transfers.
2359 (sim_create_inferior): Set the PC for all processors.
2360 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2361 argument.
2362 (mips16_entry): Pass correct nr of args to store_word, load_word.
2363 (ColdReset): Cold reset all cpu's.
2364 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2365 (sim_monitor, load_memory, store_memory, signal_exception): Use
2366 `CPU' instead of STATE_CPU.
2367
2368
2369 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2370 SD or CPU_.
72f4393d 2371
c906108c
SS		 2372 * sim-main.h (signal_exception): Add sim_cpu arg.
2373 (SignalException*): Pass both SD and CPU to signal_exception.
2374 * interp.c (signal_exception): Update.
72f4393d 2375
c906108c
SS		 2376 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2377 Ditto
2378 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2379 address_translation): Ditto
2380 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
72f4393d 2381
c906108c
SS		 2382Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2383
2384 * configure: Regenerated to track ../common/aclocal.m4 changes.
2385
2386Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2387
2388 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2389
72f4393d 2390 * mips.igen (model): Map processor names onto BFD name.
c906108c
SS		 2391
2392 * sim-main.h (CPU_CIA): Delete.
2393 (SET_CIA, GET_CIA): Define
2394
2395Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2396
2397 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2398 regiser.
2399
2400 * configure.in (default_endian): Configure a big-endian simulator
2401 by default.
2402 * configure: Re-generate.
72f4393d 2403
c906108c
SS		 2404Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2405
2406 * configure: Regenerated to track ../common/aclocal.m4 changes.
2407
2408Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2409
2410 * interp.c (sim_monitor): Handle Densan monitor outbyte
2411 and inbyte functions.
2412
24131997-12-29 Felix Lee <flee@cygnus.com>
2414
2415 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2416
2417Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2418
2419 * Makefile.in (tmp-igen): Arrange for $zero to always be
2420 reset to zero after every instruction.
2421
2422Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2423
2424 * configure: Regenerated to track ../common/aclocal.m4 changes.
2425 * config.in: Ditto.
2426
2427Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2428
2429 * mips.igen (MSUB): Fix to work like MADD.
2430 * gencode.c (MSUB): Similarly.
2431
2432Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2433
2434 * configure: Regenerated to track ../common/aclocal.m4 changes.
2435
2436Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2437
2438 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2439
2440Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2441
2442 * sim-main.h (sim-fpu.h): Include.
2443
2444 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2445 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2446 using host independant sim_fpu module.
2447
2448Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2449
2450 * interp.c (signal_exception): Report internal errors with SIGABRT
2451 not SIGQUIT.
2452
2453 * sim-main.h (C0_CONFIG): New register.
2454 (signal.h): No longer include.
2455
2456 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2457
2458Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2459
2460 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2461
2462Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2463
2464 * mips.igen: Tag vr5000 instructions.
2465 (ANDI): Was missing mipsIV model, fix assembler syntax.
2466 (do_c_cond_fmt): New function.
2467 (C.cond.fmt): Handle mips I-III which do not support CC field
2468 separatly.
2469 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2470 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2471 in IV3.2 spec.
2472 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2473 vr5000 which saves LO in a GPR separatly.
72f4393d 2474
c906108c
SS		 2475 * configure.in (enable-sim-igen): For vr5000, select vr5000
2476 specific instructions.
2477 * configure: Re-generate.
72f4393d 2478
c906108c
SS		 2479Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2480
2481 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2482
2483 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2484 fmt_uninterpreted_64 bit cases to switch. Convert to
2485 fmt_formatted,
2486
2487 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2488
2489 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2490 as specified in IV3.2 spec.
2491 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2492
2493Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2494
2495 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2496 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2497 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2498 PENDING_FILL versions of instructions. Simplify.
2499 (X): New function.
2500 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2501 instructions.
2502 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2503 a signed value.
2504 (MTHI, MFHI): Disable code checking HI-LO.
72f4393d 2505
c906108c
SS		 2506 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2507 global.
2508 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2509
2510Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2511
2512 * gencode.c (build_mips16_operands): Replace IPC with cia.
2513
2514 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2515 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2516 IPC to `cia'.
2517 (UndefinedResult): Replace function with macro/function
2518 combination.
2519 (sim_engine_run): Don't save PC in IPC.
2520
2521 * sim-main.h (IPC): Delete.
2522
2523
2524 * interp.c (signal_exception, store_word, load_word,
2525 address_translation, load_memory, store_memory, cache_op,
2526 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2527 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2528 current instruction address - cia - argument.
2529 (sim_read, sim_write): Call address_translation directly.
2530 (sim_engine_run): Rename variable vaddr to cia.
2531 (signal_exception): Pass cia to sim_monitor
72f4393d 2532
c906108c
SS		 2533 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2534 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2535 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2536
2537 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2538 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2539 SIM_ASSERT.
72f4393d 2540
c906108c
SS		 2541 * interp.c (signal_exception): Pass restart address to
2542 sim_engine_restart.
2543
2544 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2545 idecode.o): Add dependency.
2546
2547 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2548 Delete definitions
2549 (DELAY_SLOT): Update NIA not PC with branch address.
2550 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2551
2552 * mips.igen: Use CIA not PC in branch calculations.
2553 (illegal): Call SignalException.
2554 (BEQ, ADDIU): Fix assembler.
2555
2556Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2557
2558 * m16.igen (JALX): Was missing.
2559
2560 * configure.in (enable-sim-igen): New configuration option.
2561 * configure: Re-generate.
72f4393d 2562
c906108c
SS		 2563 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2564
2565 * interp.c (load_memory, store_memory): Delete parameter RAW.
2566 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2567 bypassing {load,store}_memory.
2568
2569 * sim-main.h (ByteSwapMem): Delete definition.
2570
2571 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2572
2573 * interp.c (sim_do_command, sim_commands): Delete mips specific
2574 commands. Handled by module sim-options.
72f4393d 2575
c906108c
SS		 2576 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2577 (WITH_MODULO_MEMORY): Define.
2578
2579 * interp.c (sim_info): Delete code printing memory size.
2580
2581 * interp.c (mips_size): Nee sim_size, delete function.
2582 (power2): Delete.
2583 (monitor, monitor_base, monitor_size): Delete global variables.
2584 (sim_open, sim_close): Delete code creating monitor and other
2585 memory regions. Use sim-memopts module, via sim_do_commandf, to
2586 manage memory regions.
2587 (load_memory, store_memory): Use sim-core for memory model.
72f4393d 2588
c906108c
SS		 2589 * interp.c (address_translation): Delete all memory map code
2590 except line forcing 32 bit addresses.
2591
2592Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2593
2594 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2595 trace options.
2596
2597 * interp.c (logfh, logfile): Delete globals.
2598 (sim_open, sim_close): Delete code opening & closing log file.
2599 (mips_option_handler): Delete -l and -n options.
2600 (OPTION mips_options): Ditto.
2601
2602 * interp.c (OPTION mips_options): Rename option trace to dinero.
2603 (mips_option_handler): Update.
2604
2605Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2606
2607 * interp.c (fetch_str): New function.
2608 (sim_monitor): Rewrite using sim_read & sim_write.
2609 (sim_open): Check magic number.
2610 (sim_open): Write monitor vectors into memory using sim_write.
2611 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2612 (sim_read, sim_write): Simplify - transfer data one byte at a
2613 time.
2614 (load_memory, store_memory): Clarify meaning of parameter RAW.
2615
2616 * sim-main.h (isHOST): Defete definition.
2617 (isTARGET): Mark as depreciated.
2618 (address_translation): Delete parameter HOST.
2619
2620 * interp.c (address_translation): Delete parameter HOST.
2621
2622Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2623
72f4393d 2624 * mips.igen:
c906108c
SS		 2625
2626 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2627 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2628
2629Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2630
2631 * mips.igen: Add model filter field to records.
2632
2633Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2634
2635 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
72f4393d 2636
c906108c
SS		 2637 interp.c (sim_engine_run): Do not compile function sim_engine_run
2638 when WITH_IGEN == 1.
2639
2640 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2641 target architecture.
2642
2643 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2644 igen. Replace with configuration variables sim_igen_flags /
2645 sim_m16_flags.
2646
2647 * m16.igen: New file. Copy mips16 insns here.
2648 * mips.igen: From here.
2649
2650Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2651
2652 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2653 to top.
2654 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2655
2656Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2657
2658 * gencode.c (build_instruction): Follow sim_write's lead in using
2659 BigEndianMem instead of !ByteSwapMem.
2660
2661Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2662
2663 * configure.in (sim_gen): Dependent on target, select type of
2664 generator. Always select old style generator.
2665
2666 configure: Re-generate.
2667
2668 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2669 targets.
2670 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2671 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2672 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2673 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2674 SIM_@sim_gen@_*, set by autoconf.
72f4393d 2675
c906108c
SS		 2676Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2677
2678 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2679
2680 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2681 CURRENT_FLOATING_POINT instead.
2682
2683 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2684 (address_translation): Raise exception InstructionFetch when
2685 translation fails and isINSTRUCTION.
72f4393d 2686
c906108c
SS		 2687 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2688 sim_engine_run): Change type of of vaddr and paddr to
2689 address_word.
2690 (address_translation, prefetch, load_memory, store_memory,
2691 cache_op): Change type of vAddr and pAddr to address_word.
2692
2693 * gencode.c (build_instruction): Change type of vaddr and paddr to
2694 address_word.
2695
2696Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2697
2698 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2699 macro to obtain result of ALU op.
2700
2701Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2702
2703 * interp.c (sim_info): Call profile_print.
2704
2705Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2706
2707 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2708
2709 * sim-main.h (WITH_PROFILE): Do not define, defined in
2710 common/sim-config.h. Use sim-profile module.
2711 (simPROFILE): Delete defintion.
2712
2713 * interp.c (PROFILE): Delete definition.
2714 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2715 (sim_close): Delete code writing profile histogram.
2716 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2717 Delete.
2718 (sim_engine_run): Delete code profiling the PC.
2719
2720Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2721
2722 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2723
2724 * interp.c (sim_monitor): Make register pointers of type
2725 unsigned_word*.
2726
2727 * sim-main.h: Make registers of type unsigned_word not
2728 signed_word.
2729
2730Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2731
2732 * interp.c (sync_operation): Rename from SyncOperation, make
2733 global, add SD argument.
2734 (prefetch): Rename from Prefetch, make global, add SD argument.
2735 (decode_coproc): Make global.
2736
2737 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2738
2739 * gencode.c (build_instruction): Generate DecodeCoproc not
2740 decode_coproc calls.
2741
2742 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2743 (SizeFGR): Move to sim-main.h
2744 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2745 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2746 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2747 sim-main.h.
2748 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2749 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2750 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2751 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2752 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2753 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
72f4393d 2754
c906108c
SS		 2755 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2756 exception.
2757 (sim-alu.h): Include.
2758 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2759 (sim_cia): Typedef to instruction_address.
72f4393d 2760
c906108c
SS		 2761Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2762
2763 * Makefile.in (interp.o): Rename generated file engine.c to
2764 oengine.c.
72f4393d 2765
c906108c 2766 * interp.c: Update.
72f4393d 2767
c906108c
SS		 2768Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2769
2770 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
72f4393d 2771
c906108c
SS		 2772Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2773
2774 * gencode.c (build_instruction): For "FPSQRT", output correct
2775 number of arguments to Recip.
72f4393d 2776
c906108c
SS		 2777Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2778
2779 * Makefile.in (interp.o): Depends on sim-main.h
2780
2781 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2782
2783 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2784 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2785 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2786 STATE, DSSTATE): Define
2787 (GPR, FGRIDX, ..): Define.
2788
2789 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2790 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2791 (GPR, FGRIDX, ...): Delete macros.
72f4393d 2792
c906108c 2793 * interp.c: Update names to match defines from sim-main.h
72f4393d 2794
c906108c
SS		 2795Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2796
2797 * interp.c (sim_monitor): Add SD argument.
2798 (sim_warning): Delete. Replace calls with calls to
2799 sim_io_eprintf.
2800 (sim_error): Delete. Replace calls with sim_io_error.
2801 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2802 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2803 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2804 argument.
2805 (mips_size): Rename from sim_size. Add SD argument.
2806
2807 * interp.c (simulator): Delete global variable.
2808 (callback): Delete global variable.
2809 (mips_option_handler, sim_open, sim_write, sim_read,
2810 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2811 sim_size,sim_monitor): Use sim_io_* not callback->*.
2812 (sim_open): ZALLOC simulator struct.
2813 (PROFILE): Do not define.
2814
2815Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2816
2817 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2818 support.h with corresponding code.
2819
2820 * sim-main.h (word64, uword64), support.h: Move definition to
2821 sim-main.h.
2822 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2823
2824 * support.h: Delete
2825 * Makefile.in: Update dependencies
2826 * interp.c: Do not include.
72f4393d 2827
c906108c
SS		 2828Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2829
2830 * interp.c (address_translation, load_memory, store_memory,
2831 cache_op): Rename to from AddressTranslation et.al., make global,
2832 add SD argument
72f4393d 2833
c906108c
SS		 2834 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2835 CacheOp): Define.
72f4393d 2836
c906108c
SS		 2837 * interp.c (SignalException): Rename to signal_exception, make
2838 global.
2839
2840 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
72f4393d 2841
c906108c
SS		 2842 * sim-main.h (SignalException, SignalExceptionInterrupt,
2843 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2844 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2845 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2846 Define.
72f4393d 2847
c906108c 2848 * interp.c, support.h: Use.
72f4393d 2849
c906108c
SS		 2850Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2851
2852 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2853 to value_fpr / store_fpr. Add SD argument.
2854 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2855 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2856
2857 * sim-main.h (ValueFPR, StoreFPR): Define.
72f4393d 2858
c906108c
SS		 2859Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2860
2861 * interp.c (sim_engine_run): Check consistency between configure
2862 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2863 and HASFPU.
2864
2865 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
72f4393d 2866 (mips_fpu): Configure WITH_FLOATING_POINT.
c906108c
SS		 2867 (mips_endian): Configure WITH_TARGET_ENDIAN.
2868 * configure: Update.
2869
2870Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2871
2872 * configure: Regenerated to track ../common/aclocal.m4 changes.
2873
2874Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2875
2876 * configure: Regenerated.
2877
2878Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2879
2880 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2881
2882Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2883
2884 * gencode.c (print_igen_insn_models): Assume certain architectures
2885 include all mips* instructions.
2886 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2887 instruction.
2888
2889 * Makefile.in (tmp.igen): Add target. Generate igen input from
2890 gencode file.
2891
2892 * gencode.c (FEATURE_IGEN): Define.
2893 (main): Add --igen option. Generate output in igen format.
2894 (process_instructions): Format output according to igen option.
2895 (print_igen_insn_format): New function.
2896 (print_igen_insn_models): New function.
2897 (process_instructions): Only issue warnings and ignore
2898 instructions when no FEATURE_IGEN.
2899
2900Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2901
2902 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2903 MIPS targets.
2904
2905Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2906
2907 * configure: Regenerated to track ../common/aclocal.m4 changes.
2908
2909Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2910
2911 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2912 SIM_RESERVED_BITS): Delete, moved to common.
2913 (SIM_EXTRA_CFLAGS): Update.
72f4393d 2914
c906108c
SS		 2915Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2916
2917 * configure.in: Configure non-strict memory alignment.
2918 * configure: Regenerated to track ../common/aclocal.m4 changes.
2919
2920Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2921
2922 * configure: Regenerated to track ../common/aclocal.m4 changes.
2923
2924Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2925
2926 * gencode.c (SDBBP,DERET): Added (3900) insns.
2927 (RFE): Turn on for 3900.
2928 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2929 (dsstate): Made global.
2930 (SUBTARGET_R3900): Added.
2931 (CANCELDELAYSLOT): New.
2932 (SignalException): Ignore SystemCall rather than ignore and
2933 terminate. Add DebugBreakPoint handling.
2934 (decode_coproc): New insns RFE, DERET; and new registers Debug
2935 and DEPC protected by SUBTARGET_R3900.
2936 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2937 bits explicitly.
2938 * Makefile.in,configure.in: Add mips subtarget option.
72f4393d 2939 * configure: Update.
c906108c
SS		 2940
2941Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2942
2943 * gencode.c: Add r3900 (tx39).
72f4393d 2944
c906108c
SS		 2945
2946Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2947
2948 * gencode.c (build_instruction): Don't need to subtract 4 for
2949 JALR, just 2.
2950
2951Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2952
2953 * interp.c: Correct some HASFPU problems.
2954
2955Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2956
2957 * configure: Regenerated to track ../common/aclocal.m4 changes.
2958
2959Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2960
2961 * interp.c (mips_options): Fix samples option short form, should
2962 be `x'.
2963
2964Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2965
2966 * interp.c (sim_info): Enable info code. Was just returning.
2967
2968Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2969
2970 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2971 MFC0.
2972
2973Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2974
2975 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2976 constants.
2977 (build_instruction): Ditto for LL.
2978
2979Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2980
2981 * configure: Regenerated to track ../common/aclocal.m4 changes.
2982
2983Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2984
2985 * configure: Regenerated to track ../common/aclocal.m4 changes.
2986 * config.in: Ditto.
2987
2988Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2989
2990 * interp.c (sim_open): Add call to sim_analyze_program, update
2991 call to sim_config.
2992
2993Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2994
2995 * interp.c (sim_kill): Delete.
2996 (sim_create_inferior): Add ABFD argument. Set PC from same.
2997 (sim_load): Move code initializing trap handlers from here.
2998 (sim_open): To here.
2999 (sim_load): Delete, use sim-hload.c.
3000
3001 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
3002
3003Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3004
3005 * configure: Regenerated to track ../common/aclocal.m4 changes.
3006 * config.in: Ditto.
3007
3008Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3009
3010 * interp.c (sim_open): Add ABFD argument.
3011 (sim_load): Move call to sim_config from here.
3012 (sim_open): To here. Check return status.
3013
3014Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
72f4393d 3015
c906108c
SS		 3016 * gencode.c (build_instruction): Two arg MADD should
3017 not assign result to $0.
72f4393d 3018
c906108c
SS		 3019Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
3020
3021 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
3022 * sim/mips/configure.in: Regenerate.
3023
3024Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
3025
3026 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
3027 signed8, unsigned8 et.al. types.
3028
3029 * interp.c (SUB_REG_FETCH): Handle both little and big endian
3030 hosts when selecting subreg.
3031
3032Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
3033
3034 * interp.c (sim_engine_run): Reset the ZERO register to zero
3035 regardless of FEATURE_WARN_ZERO.
3036 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
3037
3038Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
3039
3040 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
3041 (SignalException): For BreakPoints ignore any mode bits and just
3042 save the PC.
3043 (SignalException): Always set the CAUSE register.
3044
3045Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
3046
3047 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
3048 exception has been taken.
3049
3050 * interp.c: Implement the ERET and mt/f sr instructions.
3051
3052Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
3053
3054 * interp.c (SignalException): Don't bother restarting an
3055 interrupt.
3056
3057Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3058
3059 * interp.c (SignalException): Really take an interrupt.
3060 (interrupt_event): Only deliver interrupts when enabled.
3061
3062Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
3063
3064 * interp.c (sim_info): Only print info when verbose.
3065 (sim_info) Use sim_io_printf for output.
72f4393d 3066
c906108c
SS		 3067Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3068
3069 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
3070 mips architectures.
3071
3072Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3073
3074 * interp.c (sim_do_command): Check for common commands if a
3075 simulator specific command fails.
3076
3077Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
3078
3079 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
3080 and simBE when DEBUG is defined.
3081
3082Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
3083
3084 * interp.c (interrupt_event): New function. Pass exception event
3085 onto exception handler.
3086
3087 * configure.in: Check for stdlib.h.
3088 * configure: Regenerate.
3089
3090 * gencode.c (build_instruction): Add UNUSED attribute to tempS
3091 variable declaration.
3092 (build_instruction): Initialize memval1.
3093 (build_instruction): Add UNUSED attribute to byte, bigend,
3094 reverse.
3095 (build_operands): Ditto.
3096
3097 * interp.c: Fix GCC warnings.
3098 (sim_get_quit_code): Delete.
3099
3100 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
3101 * Makefile.in: Ditto.
3102 * configure: Re-generate.
72f4393d 3103
c906108c
SS		 3104 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
3105
3106Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
3107
3108 * interp.c (mips_option_handler): New function parse argumes using
3109 sim-options.
3110 (myname): Replace with STATE_MY_NAME.
3111 (sim_open): Delete check for host endianness - performed by
3112 sim_config.
3113 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
3114 (sim_open): Move much of the initialization from here.
3115 (sim_load): To here. After the image has been loaded and
3116 endianness set.
3117 (sim_open): Move ColdReset from here.
3118 (sim_create_inferior): To here.
3119 (sim_open): Make FP check less dependant on host endianness.
3120
3121 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
3122 run.
3123 * interp.c (sim_set_callbacks): Delete.
3124
3125 * interp.c (membank, membank_base, membank_size): Replace with
3126 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
3127 (sim_open): Remove call to callback->init. gdb/run do this.
3128
3129 * interp.c: Update
3130
3131 * sim-main.h (SIM_HAVE_FLATMEM): Define.
3132
3133 * interp.c (big_endian_p): Delete, replaced by
3134 current_target_byte_order.
3135
3136Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3137
3138 * interp.c (host_read_long, host_read_word, host_swap_word,
3139 host_swap_long): Delete. Using common sim-endian.
3140 (sim_fetch_register, sim_store_register): Use H2T.
3141 (pipeline_ticks): Delete. Handled by sim-events.
3142 (sim_info): Update.
3143 (sim_engine_run): Update.
3144
3145Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
3146
3147 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
3148 reason from here.
3149 (SignalException): To here. Signal using sim_engine_halt.
3150 (sim_stop_reason): Delete, moved to common.
72f4393d 3151
c906108c
SS		 3152Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
3153
3154 * interp.c (sim_open): Add callback argument.
3155 (sim_set_callbacks): Delete SIM_DESC argument.
3156 (sim_size): Ditto.
3157
3158Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3159
3160 * Makefile.in (SIM_OBJS): Add common modules.
3161
3162 * interp.c (sim_set_callbacks): Also set SD callback.
3163 (set_endianness, xfer_*, swap_*): Delete.
3164 (host_read_word, host_read_long, host_swap_word, host_swap_long):
3165 Change to functions using sim-endian macros.
3166 (control_c, sim_stop): Delete, use common version.
3167 (simulate): Convert into.
3168 (sim_engine_run): This function.
3169 (sim_resume): Delete.
72f4393d 3170
c906108c
SS		 3171 * interp.c (simulation): New variable - the simulator object.
3172 (sim_kind): Delete global - merged into simulation.
3173 (sim_load): Cleanup. Move PC assignment from here.
3174 (sim_create_inferior): To here.
3175
3176 * sim-main.h: New file.
3177 * interp.c (sim-main.h): Include.
72f4393d 3178
c906108c
SS		 3179Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
3180
3181 * configure: Regenerated to track ../common/aclocal.m4 changes.
3182
3183Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
3184
3185 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
3186
3187Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
3188
72f4393d
L		 3189 * gencode.c (build_instruction): DIV instructions: check
3190 for division by zero and integer overflow before using
c906108c
SS		 3191 host's division operation.
3192
3193Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
3194
3195 * Makefile.in (SIM_OBJS): Add sim-load.o.
3196 * interp.c: #include bfd.h.
3197 (target_byte_order): Delete.
3198 (sim_kind, myname, big_endian_p): New static locals.
3199 (sim_open): Set sim_kind, myname. Move call to set_endianness to
3200 after argument parsing. Recognize -E arg, set endianness accordingly.
3201 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
3202 load file into simulator. Set PC from bfd.
3203 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
3204 (set_endianness): Use big_endian_p instead of target_byte_order.
3205
3206Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
3207
3208 * interp.c (sim_size): Delete prototype - conflicts with
3209 definition in remote-sim.h. Correct definition.
3210
3211Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3212
3213 * configure: Regenerated to track ../common/aclocal.m4 changes.
3214 * config.in: Ditto.
3215
3216Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
3217
3218 * interp.c (sim_open): New arg `kind'.
3219
3220 * configure: Regenerated to track ../common/aclocal.m4 changes.
3221
3222Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3223
3224 * configure: Regenerated to track ../common/aclocal.m4 changes.
3225
3226Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
3227
3228 * interp.c (sim_open): Set optind to 0 before calling getopt.
3229
3230Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3231
3232 * configure: Regenerated to track ../common/aclocal.m4 changes.
3233
3234Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
3235
3236 * interp.c : Replace uses of pr_addr with pr_uword64
3237 where the bit length is always 64 independent of SIM_ADDR.
3238 (pr_uword64) : added.
3239
3240Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3241
3242 * configure: Re-generate.
3243
3244Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
3245
3246 * configure: Regenerate to track ../common/aclocal.m4 changes.
3247
3248Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
3249
3250 * interp.c (sim_open): New SIM_DESC result. Argument is now
3251 in argv form.
3252 (other sim_*): New SIM_DESC argument.
3253
3254Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
3255
3256 * interp.c: Fix printing of addresses for non-64-bit targets.
3257 (pr_addr): Add function to print address based on size.
3258
3259Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
3260
3261 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
3262
3263Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
3264
3265 * gencode.c (build_mips16_operands): Correct computation of base
3266 address for extended PC relative instruction.
3267
3268Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
3269
3270 * interp.c (mips16_entry): Add support for floating point cases.
3271 (SignalException): Pass floating point cases to mips16_entry.
3272 (ValueFPR): Don't restrict fmt_single and fmt_word to even
3273 registers.
3274 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
3275 or fmt_word.
3276 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
3277 and then set the state to fmt_uninterpreted.
3278 (COP_SW): Temporarily set the state to fmt_word while calling
3279 ValueFPR.
3280
3281Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
3282
3283 * gencode.c (build_instruction): The high order may be set in the
3284 comparison flags at any ISA level, not just ISA 4.
3285
3286Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
3287
3288 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
3289 COMMON_{PRE,POST}_CONFIG_FRAG instead.
3290 * configure.in: sinclude ../common/aclocal.m4.
3291 * configure: Regenerated.
3292
3293Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
3294
3295 * configure: Rebuild after change to aclocal.m4.
3296
3297Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
3298
3299 * configure configure.in Makefile.in: Update to new configure
3300 scheme which is more compatible with WinGDB builds.
3301 * configure.in: Improve comment on how to run autoconf.
3302 * configure: Re-run autoconf to get new ../common/aclocal.m4.
3303 * Makefile.in: Use autoconf substitution to install common
3304 makefile fragment.
3305
3306Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
3307
3308 * gencode.c (build_instruction): Use BigEndianCPU instead of
3309 ByteSwapMem.
3310
3311Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
3312
3313 * interp.c (sim_monitor): Make output to stdout visible in
3314 wingdb's I/O log window.
3315
3316Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
3317
3318 * support.h: Undo previous change to SIGTRAP
3319 and SIGQUIT values.
3320
3321Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
3322
3323 * interp.c (store_word, load_word): New static functions.
3324 (mips16_entry): New static function.
3325 (SignalException): Look for mips16 entry and exit instructions.
3326 (simulate): Use the correct index when setting fpr_state after
3327 doing a pending move.
3328
3329Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
3330
3331 * interp.c: Fix byte-swapping code throughout to work on
3332 both little- and big-endian hosts.
3333
3334Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
3335
3336 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3337 with gdb/config/i386/xm-windows.h.
3338
3339Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
3340
3341 * gencode.c (build_instruction): Work around MSVC++ code gen bug
3342 that messes up arithmetic shifts.
3343
3344Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
3345
3346 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
3347 SIGTRAP and SIGQUIT for _WIN32.
3348
3349Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3350
3351 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3352 force a 64 bit multiplication.
3353 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3354 destination register is 0, since that is the default mips16 nop
3355 instruction.
3356
3357Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3358
3359 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3360 (build_endian_shift): Don't check proc64.
3361 (build_instruction): Always set memval to uword64. Cast op2 to
3362 uword64 when shifting it left in memory instructions. Always use
3363 the same code for stores--don't special case proc64.
3364
3365 * gencode.c (build_mips16_operands): Fix base PC value for PC
3366 relative operands.
3367 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3368 jal instruction.
3369 * interp.c (simJALDELAYSLOT): Define.
3370 (JALDELAYSLOT): Define.
3371 (INDELAYSLOT, INJALDELAYSLOT): Define.
3372 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3373
3374Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3375
3376 * interp.c (sim_open): add flush_cache as a PMON routine
3377 (sim_monitor): handle flush_cache by ignoring it
3378
3379Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3380
3381 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3382 BigEndianMem.
3383 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3384 (BigEndianMem): Rename to ByteSwapMem and change sense.
3385 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3386 BigEndianMem references to !ByteSwapMem.
3387 (set_endianness): New function, with prototype.
3388 (sim_open): Call set_endianness.
3389 (sim_info): Use simBE instead of BigEndianMem.
3390 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3391 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3392 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3393 ifdefs, keeping the prototype declaration.
3394 (swap_word): Rewrite correctly.
3395 (ColdReset): Delete references to CONFIG. Delete endianness related
3396 code; moved to set_endianness.
72f4393d 3397
c906108c
SS		 3398Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3399
3400 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3401 * interp.c (CHECKHILO): Define away.
3402 (simSIGINT): New macro.
3403 (membank_size): Increase from 1MB to 2MB.
3404 (control_c): New function.
3405 (sim_resume): Rename parameter signal to signal_number. Add local
3406 variable prev. Call signal before and after simulate.
3407 (sim_stop_reason): Add simSIGINT support.
3408 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3409 functions always.
3410 (sim_warning): Delete call to SignalException. Do call printf_filtered
3411 if logfh is NULL.
3412 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3413 a call to sim_warning.
3414
3415Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3416
3417 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3418 16 bit instructions.
3419
3420Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3421
3422 Add support for mips16 (16 bit MIPS implementation):
3423 * gencode.c (inst_type): Add mips16 instruction encoding types.
3424 (GETDATASIZEINSN): Define.
3425 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3426 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3427 mtlo.
3428 (MIPS16_DECODE): New table, for mips16 instructions.
3429 (bitmap_val): New static function.
3430 (struct mips16_op): Define.
3431 (mips16_op_table): New table, for mips16 operands.
3432 (build_mips16_operands): New static function.
3433 (process_instructions): If PC is odd, decode a mips16
3434 instruction. Break out instruction handling into new
3435 build_instruction function.
3436 (build_instruction): New static function, broken out of
3437 process_instructions. Check modifiers rather than flags for SHIFT
3438 bit count and m[ft]{hi,lo} direction.
3439 (usage): Pass program name to fprintf.
3440 (main): Remove unused variable this_option_optind. Change
3441 ``*loptarg++'' to ``loptarg++''.
3442 (my_strtoul): Parenthesize && within ||.
3443 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3444 (simulate): If PC is odd, fetch a 16 bit instruction, and
3445 increment PC by 2 rather than 4.
3446 * configure.in: Add case for mips16*-*-*.
3447 * configure: Rebuild.
3448
3449Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3450
3451 * interp.c: Allow -t to enable tracing in standalone simulator.
3452 Fix garbage output in trace file and error messages.
3453
3454Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3455
3456 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3457 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3458 * configure.in: Simplify using macros in ../common/aclocal.m4.
3459 * configure: Regenerated.
3460 * tconfig.in: New file.
3461
3462Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3463
3464 * interp.c: Fix bugs in 64-bit port.
3465 Use ansi function declarations for msvc compiler.
3466 Initialize and test file pointer in trace code.
3467 Prevent duplicate definition of LAST_EMED_REGNUM.
3468
3469Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3470
3471 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3472
3473Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3474
3475 * interp.c (SignalException): Check for explicit terminating
3476 breakpoint value.
3477 * gencode.c: Pass instruction value through SignalException()
3478 calls for Trap, Breakpoint and Syscall.
3479
3480Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3481
3482 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3483 only used on those hosts that provide it.
3484 * configure.in: Add sqrt() to list of functions to be checked for.
3485 * config.in: Re-generated.
3486 * configure: Re-generated.
3487
3488Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3489
3490 * gencode.c (process_instructions): Call build_endian_shift when
3491 expanding STORE RIGHT, to fix swr.
3492 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3493 clear the high bits.
3494 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3495 Fix float to int conversions to produce signed values.
3496
3497Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3498
3499 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3500 (process_instructions): Correct handling of nor instruction.
3501 Correct shift count for 32 bit shift instructions. Correct sign
3502 extension for arithmetic shifts to not shift the number of bits in
3503 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3504 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3505 Fix madd.
3506 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3507 It's OK to have a mult follow a mult. What's not OK is to have a
3508 mult follow an mfhi.
3509 (Convert): Comment out incorrect rounding code.
3510
3511Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3512
3513 * interp.c (sim_monitor): Improved monitor printf
3514 simulation. Tidied up simulator warnings, and added "--log" option
3515 for directing warning message output.
3516 * gencode.c: Use sim_warning() rather than WARNING macro.
3517
3518Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3519
3520 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3521 getopt1.o, rather than on gencode.c. Link objects together.
3522 Don't link against -liberty.
3523 (gencode.o, getopt.o, getopt1.o): New targets.
3524 * gencode.c: Include <ctype.h> and "ansidecl.h".
3525 (AND): Undefine after including "ansidecl.h".
3526 (ULONG_MAX): Define if not defined.
3527 (OP_*): Don't define macros; now defined in opcode/mips.h.
3528 (main): Call my_strtoul rather than strtoul.
3529 (my_strtoul): New static function.
3530
3531Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3532
3533 * gencode.c (process_instructions): Generate word64 and uword64
3534 instead of `long long' and `unsigned long long' data types.
3535 * interp.c: #include sysdep.h to get signals, and define default
3536 for SIGBUS.
3537 * (Convert): Work around for Visual-C++ compiler bug with type
3538 conversion.
3539 * support.h: Make things compile under Visual-C++ by using
3540 __int64 instead of `long long'. Change many refs to long long
3541 into word64/uword64 typedefs.
3542
3543Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3544
72f4393d
L		 3545 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3546 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3547 (docdir): Removed.
3548 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3549 (AC_PROG_INSTALL): Added.
c906108c 3550 (AC_PROG_CC): Moved to before configure.host call.
72f4393d
L		 3551 * configure: Rebuilt.
3552
c906108c
SS		 3553Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3554
3555 * configure.in: Define @SIMCONF@ depending on mips target.
3556 * configure: Rebuild.
3557 * Makefile.in (run): Add @SIMCONF@ to control simulator
3558 construction.
3559 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3560 * interp.c: Remove some debugging, provide more detailed error
3561 messages, update memory accesses to use LOADDRMASK.
72f4393d 3562
c906108c
SS		 3563Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3564
3565 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3566 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3567 stamp-h.
3568 * configure: Rebuild.
3569 * config.in: New file, generated by autoheader.
3570 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3571 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3572 HAVE_ANINT and HAVE_AINT, as appropriate.
3573 * Makefile.in (run): Use @LIBS@ rather than -lm.
3574 (interp.o): Depend upon config.h.
3575 (Makefile): Just rebuild Makefile.
3576 (clean): Remove stamp-h.
3577 (mostlyclean): Make the same as clean, not as distclean.
3578 (config.h, stamp-h): New targets.
3579
3580Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3581
3582 * interp.c (ColdReset): Fix boolean test. Make all simulator
3583 globals static.
3584
3585Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3586
3587 * interp.c (xfer_direct_word, xfer_direct_long,
3588 swap_direct_word, swap_direct_long, xfer_big_word,
3589 xfer_big_long, xfer_little_word, xfer_little_long,
3590 swap_word,swap_long): Added.
3591 * interp.c (ColdReset): Provide function indirection to
3592 host<->simulated_target transfer routines.
3593 * interp.c (sim_store_register, sim_fetch_register): Updated to
3594 make use of indirected transfer routines.
3595
3596Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3597
3598 * gencode.c (process_instructions): Ensure FP ABS instruction
3599 recognised.
3600 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3601 system call support.
3602
3603Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3604
3605 * interp.c (sim_do_command): Complain if callback structure not
3606 initialised.
3607
3608Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3609
3610 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3611 support for Sun hosts.
3612 * Makefile.in (gencode): Ensure the host compiler and libraries
3613 used for cross-hosted build.
3614
3615Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3616
3617 * interp.c, gencode.c: Some more (TODO) tidying.
3618
3619Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3620
3621 * gencode.c, interp.c: Replaced explicit long long references with
3622 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3623 * support.h (SET64LO, SET64HI): Macros added.
3624
3625Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3626
3627 * configure: Regenerate with autoconf 2.7.
3628
3629Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3630
3631 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3632 * support.h: Remove superfluous "1" from #if.
3633 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3634
3635Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3636
3637 * interp.c (StoreFPR): Control UndefinedResult() call on
3638 WARN_RESULT manifest.
3639
3640Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3641
3642 * gencode.c: Tidied instruction decoding, and added FP instruction
3643 support.
3644
3645 * interp.c: Added dineroIII, and BSD profiling support. Also
3646 run-time FP handling.
3647
3648Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3649
3650 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3651 gencode.c, interp.c, support.h: created.
GDB Binutils - Deliverables
This page took 0.906118 seconds and 4 git commands to generate.