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* som.c (som_bfd_ar_write_symbol_stuff): Account for trailing
[deliverable/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
ea985d24
AC		 1Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2
3start-sanitize-r5900
4 * sim-main.h (BYTES_IN_MMI_REGS, ..., SUB_REG_FETCH, ..., GPR_SB,
5 ...): Move to sim-main.h
6
7end-sanitize-r5900
8 * interp.c (sync_operation): Rename from SyncOperation, make
9 global, add SD argument.
10 (prefetch): Rename from Prefetch, make global, add SD argument.
11 (decode_coproc): Make global.
12
13 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
14
15 * gencode.c (build_instruction): Generate DecodeCoproc not
16 decode_coproc calls.
17
18 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
19 (SizeFGR): Move to sim-main.h
20 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
21 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
22 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
23 sim-main.h.
24 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
25 FP_RM_TOMINF, GETRM): Move to sim-main.h.
26 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
27 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
28 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
29 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
30
31 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
32 exception.
33 (sim-alu.h): Include.
34 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
35 (sim_cia): Typedef to instruction_address.
36
284e759d
AC		 37Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
38
39 * Makefile.in (interp.o): Rename generated file engine.c to
40 oengine.c.
41
42 * interp.c: Update.
43
339fb149
AC		 44Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
45
46 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
47
8b70f837
AC		 48Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
49
50 * gencode.c (build_instruction): For "FPSQRT", output correct
51 number of arguments to Recip.
52
0c2c5f61
AC		 53Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
54
55 * Makefile.in (interp.o): Depends on sim-main.h
56
57 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
58
59 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
60 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
61 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
62 STATE, DSSTATE): Define
63 (GPR, FGRIDX, ..): Define.
64
65 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
66 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
67 (GPR, FGRIDX, ...): Delete macros.
68
69 * interp.c: Update names to match defines from sim-main.h
70
18c64df6
AC		 71Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
72
73 * interp.c (sim_monitor): Add SD argument.
74 (sim_warning): Delete. Replace calls with calls to
75 sim_io_eprintf.
76 (sim_error): Delete. Replace calls with sim_io_error.
77 (open_trace, writeout32, writeout16, getnum): Add SD argument.
78 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
79 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
80 argument.
81 (mips_size): Rename from sim_size. Add SD argument.
82
83 * interp.c (simulator): Delete global variable.
84 (callback): Delete global variable.
85 (mips_option_handler, sim_open, sim_write, sim_read,
86 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
87 sim_size,sim_monitor): Use sim_io_* not callback->*.
88 (sim_open): ZALLOC simulator struct.
89 (PROFILE): Do not define.
90
91Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
92
93 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
94 support.h with corresponding code.
95
96 * sim-main.h (word64, uword64), support.h: Move definition to
97 sim-main.h.
98 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
99
100 * support.h: Delete
101 * Makefile.in: Update dependencies
102 * interp.c: Do not include.
103
104Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
105
106 * interp.c (address_translation, load_memory, store_memory,
107 cache_op): Rename to from AddressTranslation et.al., make global,
108 add SD argument
109
110 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
111 CacheOp): Define.
112
113 * interp.c (SignalException): Rename to signal_exception, make
114 global.
115
116 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
117
118 * sim-main.h (SignalException, SignalExceptionInterrupt,
119 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
120 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
121 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
122 Define.
123
124 * interp.c, support.h: Use.
125
126Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
127
128 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
129 to value_fpr / store_fpr. Add SD argument.
130 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
131 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
132
133 * sim-main.h (ValueFPR, StoreFPR): Define.
134
135Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
136
137 * interp.c (sim_engine_run): Check consistency between configure
138 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
139 and HASFPU.
140
141 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
142 (mips_fpu): Configure WITH_FLOATING_POINT.
143 (mips_endian): Configure WITH_TARGET_ENDIAN.
144 * configure: Update.
145
146Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
147
148 * configure: Regenerated to track ../common/aclocal.m4 changes.
149
adf4739e
AC		 150start-sanitize-r5900
151Mon Aug 25 19:11:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
152
153 * interp.c (MAX_REG): Allow up-to 128 registers.
154 (LO1, HI1): Define value that matches REGISTER_NAMES in gdb.
155 (REGISTER_SA): Ditto.
156 (sim_open): Initialize register_widths for r5900 specific
157 registers.
158 (sim_fetch_register, sim_store_register): Check for request of
159 r5900 specific SA register. Check for request for hi 64 bits of
160 r5900 specific registers.
161
162end-sanitize-r5900
26b20b0a
BM		 163Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
164
165 * configure: Regenerated.
166
6eedf3f4
MA		 167Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
168
169 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
170
e63bc706
AC		 171Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
172
6eedf3f4
MA		 173 * gencode.c (print_igen_insn_models): Assume certain architectures
174 include all mips* instructions.
175 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
176 instruction.
177
e63bc706
AC		 178 * Makefile.in (tmp.igen): Add target. Generate igen input from
179 gencode file.
180
181 * gencode.c (FEATURE_IGEN): Define.
182 (main): Add --igen option. Generate output in igen format.
183 (process_instructions): Format output according to igen option.
184 (print_igen_insn_format): New function.
185 (print_igen_insn_models): New function.
186 (process_instructions): Only issue warnings and ignore
187 instructions when no FEATURE_IGEN.
188
eb2e3c85
AC		 189Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
190
191 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
192 MIPS targets.
193
92f91d1f
AC		 194Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
195
196 * configure: Regenerated to track ../common/aclocal.m4 changes.
197
198Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
199
200 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
201 SIM_RESERVED_BITS): Delete, moved to common.
202 (SIM_EXTRA_CFLAGS): Update.
203
794e9ac9
AC		 204Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
205
76a6247f 206 * configure.in: Configure non-strict memory alignment.
794e9ac9
AC		 207 * configure: Regenerated to track ../common/aclocal.m4 changes.
208
b45caf05
AC		 209Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
210
211 * configure: Regenerated to track ../common/aclocal.m4 changes.
212
213Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
214
215 * gencode.c (SDBBP,DERET): Added (3900) insns.
216 (RFE): Turn on for 3900.
217 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
218 (dsstate): Made global.
219 (SUBTARGET_R3900): Added.
220 (CANCELDELAYSLOT): New.
221 (SignalException): Ignore SystemCall rather than ignore and
222 terminate. Add DebugBreakPoint handling.
223 (decode_coproc): New insns RFE, DERET; and new registers Debug
224 and DEPC protected by SUBTARGET_R3900.
225 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
226 bits explicitly.
227 * Makefile.in,configure.in: Add mips subtarget option.
228 * configure: Update.
229
7afa8d4e
GRK		 230Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
231
232 * gencode.c: Add r3900 (tx39).
233
234start-sanitize-tx19
235 * gencode.c: Fix some configuration problems by improving
236 the relationship between tx19 and tx39.
237end-sanitize-tx19
238
667065d0
GRK		 239Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
240
241 * gencode.c (build_instruction): Don't need to subtract 4 for
242 JALR, just 2.
243
9cb8397f
GRK		 244Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
245
246 * interp.c: Correct some HASFPU problems.
247
a2ab5e65
AC		 248Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
249
250 * configure: Regenerated to track ../common/aclocal.m4 changes.
251
11ac69e0
AC		 252Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
253
254 * interp.c (mips_options): Fix samples option short form, should
255 be `x'.
256
972f3a34
AC		 257Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
258
259 * interp.c (sim_info): Enable info code. Was just returning.
260
9eeaaefa
AC		 261Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
262
263 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
264 MFC0.
265
c31c13b4
AC		 266Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
267
268 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
269 constants.
270 (build_instruction): Ditto for LL.
271
b637f306
GRK		 272start-sanitize-tx19
273Sun Sep 7 16:05:46 1997 Gavin Koch <gavin@cygnus.com>
274
275 * mips/configure.in, mips/gencode: Add tx19/r1900.
276
277end-sanitize-tx19
6fea4763
DE		 278Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
279
280 * configure: Regenerated to track ../common/aclocal.m4 changes.
281
52352d38
AC		 282start-sanitize-r5900
283Mon Sep 1 18:43:30 1997 Andrew Cagney <cagney@b1.cygnus.com>
284
285 * gencode.c (build_instruction): For "pabsw" and "pabsh", check
286 for overflow due to ABS of MININT, set result to MAXINT.
287 (build_instruction): For "psrlvw", signextend bit 31.
288
289end-sanitize-r5900
88117054
AC		 290Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
291
292 * configure: Regenerated to track ../common/aclocal.m4 changes.
293 * config.in: Ditto.
294
fafce69a
AC		 295Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
296
297 * interp.c (sim_open): Add call to sim_analyze_program, update
298 call to sim_config.
299
7230ff0f
AC		 300Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
301
302 * interp.c (sim_kill): Delete.
fafce69a
AC		 303 (sim_create_inferior): Add ABFD argument. Set PC from same.
304 (sim_load): Move code initializing trap handlers from here.
305 (sim_open): To here.
306 (sim_load): Delete, use sim-hload.c.
307
308 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
7230ff0f 309
247fccde
AC		 310Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
311
312 * configure: Regenerated to track ../common/aclocal.m4 changes.
313 * config.in: Ditto.
314
315Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
316
317 * interp.c (sim_open): Add ABFD argument.
318 (sim_load): Move call to sim_config from here.
319 (sim_open): To here. Check return status.
320
321start-sanitize-r5900
322 * gencode.c (build_instruction): Do not define x8000000000000000,
323 x7FFFFFFFFFFFFFFF, or xFFFFFFFF80000000.
324
325end-sanitize-r5900
326start-sanitize-r5900
327Mon Jul 28 19:49:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
328
329 * gencode.c (build_instruction): For "pdivw", "pdivbw" and
330 "pdivuw" check for overflow due to signed divide by -1.
331
332end-sanitize-r5900
c12e2e4c
GRK		 333Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
334
335 * gencode.c (build_instruction): Two arg MADD should
336 not assign result to $0.
337
1e851d2c
AC		 338start-sanitize-r5900
339Thu Jul 10 11:58:48 1997 Andrew Cagney <cagney@critters.cygnus.com>
340
341 * gencode.c (build_instruction): For "ppac5" use unsigned
342 arrithmetic so that the sign bit doesn't smear when right shifted.
343 (build_instruction): For "pdiv" perform sign extension when
344 storing results in HI and LO.
345 (build_instructions): For "pdiv" and "pdivbw" check for
346 divide-by-zero.
347 (build_instruction): For "pmfhl.slw" update hi part of dest
348 register as well as low part.
349 (build_instruction): For "pmfhl" portably handle long long values.
350 (build_instruction): For "pmfhl.sh" correctly negative values.
351 Store half words 2 and three in the correct place.
352 (build_instruction): For "psllvw", sign extend value after shift.
353
354end-sanitize-r5900
355Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
356
357 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
358 * sim/mips/configure.in: Regenerate.
359
360Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
361
362 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
363 signed8, unsigned8 et.al. types.
364
365start-sanitize-r5900
366 * gencode.c (build_instruction): For PMULTU* do not sign extend
367 registers. Make generated code easier to debug.
368
369end-sanitize-r5900
370 * interp.c (SUB_REG_FETCH): Handle both little and big endian
371 hosts when selecting subreg.
372
373start-sanitize-r5900
374Tue Jul 8 18:07:20 1997 Andrew Cagney <cagney@andros.cygnus.com>
375
376 * gencode.c (type_for_data_len): For 32bit operations concerned
377 with overflow, perform op using 64bits.
378 (build_instruction): For PADD, always compute operation using type
379 returned by type_for_data_len.
380 (build_instruction): For PSUBU, when overflow, saturate to zero as
381 actually underflow.
382
383end-sanitize-r5900
ae19b07b
JL		 384Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
385
649625bb 386start-sanitize-r5900
64435234
JL		 387 * gencode.c (build_instruction): Handle "pext5" according to
388 version 1.95 of the r5900 ISA.
389
649625bb
JL		 390 * gencode.c (build_instruction): Handle "ppac5" according to
391 version 1.95 of the r5900 ISA.
649625bb 392
1e851d2c 393end-sanitize-r5900
05d1322f
JL		 394 * interp.c (sim_engine_run): Reset the ZERO register to zero
395 regardless of FEATURE_WARN_ZERO.
ae19b07b
JL		 396 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
397
398Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
399
400 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
401 (SignalException): For BreakPoints ignore any mode bits and just
402 save the PC.
403 (SignalException): Always set the CAUSE register.
404
56e7c849
AC		 405Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
406
407 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
408 exception has been taken.
409
410 * interp.c: Implement the ERET and mt/f sr instructions.
411
ae19b07b 412start-sanitize-r5900
56e7c849
AC		 413Mon Jun 2 23:28:19 1997 Andrew Cagney <cagney@b1.cygnus.com>
414
415 * gencode.c (build_instruction): For paddu, extract unsigned
416 sub-fields.
417
418 * gencode.c (build_instruction): Saturate padds instead of padd
419 instructions.
420
421end-sanitize-r5900
422Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
423
424 * interp.c (SignalException): Don't bother restarting an
425 interrupt.
426
427Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
428
429 * interp.c (SignalException): Really take an interrupt.
430 (interrupt_event): Only deliver interrupts when enabled.
431
432Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
433
434 * interp.c (sim_info): Only print info when verbose.
435 (sim_info) Use sim_io_printf for output.
436
2f2e6c5d
AC		 437Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
438
439 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
440 mips architectures.
441
442Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
443
444 * interp.c (sim_do_command): Check for common commands if a
445 simulator specific command fails.
446
d3d2a9f7
GRK		 447Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
448
449 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
450 and simBE when DEBUG is defined.
451
50a2a691
AC		 452Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
453
454 * interp.c (interrupt_event): New function. Pass exception event
455 onto exception handler.
456
457 * configure.in: Check for stdlib.h.
458 * configure: Regenerate.
459
460 * gencode.c (build_instruction): Add UNUSED attribute to tempS
461 variable declaration.
462 (build_instruction): Initialize memval1.
463 (build_instruction): Add UNUSED attribute to byte, bigend,
464 reverse.
465 (build_operands): Ditto.
466
467 * interp.c: Fix GCC warnings.
468 (sim_get_quit_code): Delete.
469
470 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
471 * Makefile.in: Ditto.
472 * configure: Re-generate.
473
474 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
475
476Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
477
478 * interp.c (mips_option_handler): New function parse argumes using
479 sim-options.
480 (myname): Replace with STATE_MY_NAME.
481 (sim_open): Delete check for host endianness - performed by
482 sim_config.
483 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
484 (sim_open): Move much of the initialization from here.
485 (sim_load): To here. After the image has been loaded and
486 endianness set.
487 (sim_open): Move ColdReset from here.
488 (sim_create_inferior): To here.
489 (sim_open): Make FP check less dependant on host endianness.
490
491 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
492 run.
493 * interp.c (sim_set_callbacks): Delete.
494
495 * interp.c (membank, membank_base, membank_size): Replace with
496 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
497 (sim_open): Remove call to callback->init. gdb/run do this.
498
499 * interp.c: Update
500
501 * sim-main.h (SIM_HAVE_FLATMEM): Define.
502
503 * interp.c (big_endian_p): Delete, replaced by
504 current_target_byte_order.
505
506Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
507
508 * interp.c (host_read_long, host_read_word, host_swap_word,
509 host_swap_long): Delete. Using common sim-endian.
510 (sim_fetch_register, sim_store_register): Use H2T.
511 (pipeline_ticks): Delete. Handled by sim-events.
512 (sim_info): Update.
513 (sim_engine_run): Update.
514
515Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
516
517 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
518 reason from here.
519 (SignalException): To here. Signal using sim_engine_halt.
520 (sim_stop_reason): Delete, moved to common.
521
522Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
523
524 * interp.c (sim_open): Add callback argument.
525 (sim_set_callbacks): Delete SIM_DESC argument.
526 (sim_size): Ditto.
527
2e61a3ad
AC		 528Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
529
530 * Makefile.in (SIM_OBJS): Add common modules.
531
532 * interp.c (sim_set_callbacks): Also set SD callback.
533 (set_endianness, xfer_*, swap_*): Delete.
534 (host_read_word, host_read_long, host_swap_word, host_swap_long):
535 Change to functions using sim-endian macros.
536 (control_c, sim_stop): Delete, use common version.
537 (simulate): Convert into.
538 (sim_engine_run): This function.
539 (sim_resume): Delete.
540
541 * interp.c (simulation): New variable - the simulator object.
542 (sim_kind): Delete global - merged into simulation.
543 (sim_load): Cleanup. Move PC assignment from here.
544 (sim_create_inferior): To here.
545
546 * sim-main.h: New file.
547 * interp.c (sim-main.h): Include.
548
549Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
550
551 * configure: Regenerated to track ../common/aclocal.m4 changes.
552
3be0e228
DE		 553Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
554
555 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
556
d654ba0a
GRK		 557Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
558
559 * gencode.c (build_instruction): DIV instructions: check
560 for division by zero and integer overflow before using
561 host's division operation.
562
9d52bcb7
DE		 563Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
564
565 * Makefile.in (SIM_OBJS): Add sim-load.o.
566 * interp.c: #include bfd.h.
567 (target_byte_order): Delete.
568 (sim_kind, myname, big_endian_p): New static locals.
569 (sim_open): Set sim_kind, myname. Move call to set_endianness to
570 after argument parsing. Recognize -E arg, set endianness accordingly.
571 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
572 load file into simulator. Set PC from bfd.
573 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
574 (set_endianness): Use big_endian_p instead of target_byte_order.
575
87e43259
AC		 576Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
577
578 * interp.c (sim_size): Delete prototype - conflicts with
579 definition in remote-sim.h. Correct definition.
580
581Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
582
583 * configure: Regenerated to track ../common/aclocal.m4 changes.
584 * config.in: Ditto.
585
fbda74b1
DE		 586Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
587
8a7c3105
DE		 588 * interp.c (sim_open): New arg `kind'.
589
fbda74b1
DE		 590 * configure: Regenerated to track ../common/aclocal.m4 changes.
591
a35e91c3
AC		 592Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
593
594 * configure: Regenerated to track ../common/aclocal.m4 changes.
595
596Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
597
598 * interp.c (sim_open): Set optind to 0 before calling getopt.
599
600Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
601
602 * configure: Regenerated to track ../common/aclocal.m4 changes.
603
6efa34d8
GRK		 604Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
605
606 * interp.c : Replace uses of pr_addr with pr_uword64
607 where the bit length is always 64 independent of SIM_ADDR.
608 (pr_uword64) : added.
609
a77aa7ec
AC		 610Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
611
612 * configure: Re-generate.
613
601fb8ae
MM		 614Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
615
616 * configure: Regenerate to track ../common/aclocal.m4 changes.
617
53b9417e
DE		 618Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
619
620 * interp.c (sim_open): New SIM_DESC result. Argument is now
621 in argv form.
622 (other sim_*): New SIM_DESC argument.
623
624start-sanitize-r5900
625Wed Feb 26 18:32:21 1997 Gavin Koch <gavin@cygnus.com>
626
627 * gencode.c (POP_AND,POP_OR,POP_NOR,POP_XOR):
628 Change values to avoid overloading DOUBLEWORD which is tested
629 for all insns.
630 * gencode.c: reinstate "offending code".
53b9417e 631
56e7c849 632end-sanitize-r5900
53b9417e
DE		 633Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
634
635 * interp.c: Fix printing of addresses for non-64-bit targets.
636 (pr_addr): Add function to print address based on size.
637start-sanitize-r5900
638 * gencode.c: #ifdef out offending code until a permanent fix
639 can be added. Code is causing build errors for non-5900 mips targets.
640end-sanitize-r5900
641
642start-sanitize-r5900
643Thu Feb 20 10:40:24 1997 Gavin Koch <gavin@cetus.cygnus.com>
644
645 * gencode.c (process_instructions): Correct test for ISA dependent
646 architecture bits in isa field of MIPS_DECODE.
647
648end-sanitize-r5900
7e05106d
MA		 649Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
650
651 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
652
2d18fbc6 653start-sanitize-r5900
53b9417e 654Tue Feb 18 17:03:47 1997 Gavin Koch <gavin@cygnus.com>
2d18fbc6
GRK		 655
656 * gencode.c (MIPS_DECODE): Correct instruction feature flags for
657 PMADDUW.
658
659end-sanitize-r5900
660Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
661
662 * gencode.c (build_mips16_operands): Correct computation of base
663 address for extended PC relative instruction.
664
276c2d7d
GRK		 665start-sanitize-r5900
666Fri Feb 7 11:12:44 1997 Gavin Koch <gavin@cygnus.com>
2d18fbc6
GRK		 667
668 * Makefile.in, configure, configure.in, gencode.c,
669 interp.c, support.h: add r5900.
670
276c2d7d 671end-sanitize-r5900
da0bce9c
ILT		 672Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
673
674 * interp.c (mips16_entry): Add support for floating point cases.
675 (SignalException): Pass floating point cases to mips16_entry.
676 (ValueFPR): Don't restrict fmt_single and fmt_word to even
677 registers.
678 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
679 or fmt_word.
680 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
681 and then set the state to fmt_uninterpreted.
682 (COP_SW): Temporarily set the state to fmt_word while calling
683 ValueFPR.
684
6389d856
ILT		 685Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
686
687 * gencode.c (build_instruction): The high order may be set in the
688 comparison flags at any ISA level, not just ISA 4.
689
19c5af72
DE		 690Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
691
692 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
693 COMMON_{PRE,POST}_CONFIG_FRAG instead.
694 * configure.in: sinclude ../common/aclocal.m4.
695 * configure: Regenerated.
696
736a306c
ILT		 697Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
698
699 * configure: Rebuild after change to aclocal.m4.
700
295dbbe4
SG		 701Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
702
703 * configure configure.in Makefile.in: Update to new configure
704 scheme which is more compatible with WinGDB builds.
705 * configure.in: Improve comment on how to run autoconf.
706 * configure: Re-run autoconf to get new ../common/aclocal.m4.
707 * Makefile.in: Use autoconf substitution to install common
708 makefile fragment.
709
710Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
711
712 * gencode.c (build_instruction): Use BigEndianCPU instead of
713 ByteSwapMem.
714
e1db0d47
MA		 715Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
716
717 * interp.c (sim_monitor): Make output to stdout visible in
718 wingdb's I/O log window.
719
2902e8ab
MA		 720Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
721
722 * support.h: Undo previous change to SIGTRAP
723 and SIGQUIT values.
724
7e6c297e
ILT		 725Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
726
727 * interp.c (store_word, load_word): New static functions.
728 (mips16_entry): New static function.
729 (SignalException): Look for mips16 entry and exit instructions.
730 (simulate): Use the correct index when setting fpr_state after
731 doing a pending move.
732
0049ba7a
MA		 733Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
734
735 * interp.c: Fix byte-swapping code throughout to work on
736 both little- and big-endian hosts.
737
2510786b
MA		 738Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
739
740 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
741 with gdb/config/i386/xm-windows.h.
742
39bf0ef4
MA		 743Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
744
745 * gencode.c (build_instruction): Work around MSVC++ code gen bug
746 that messes up arithmetic shifts.
747
dbeec768
SG		 748Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
749
750 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
751 SIGTRAP and SIGQUIT for _WIN32.
752
deffd638
ILT		 753Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
754
755 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
756 force a 64 bit multiplication.
757 (build_instruction) [OR]: In mips16 mode, don't do anything if the
758 destination register is 0, since that is the default mips16 nop
759 instruction.
760
aaff8437
ILT		 761Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
762
063443cf
ILT		 763 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
764 (build_endian_shift): Don't check proc64.
765 (build_instruction): Always set memval to uword64. Cast op2 to
766 uword64 when shifting it left in memory instructions. Always use
767 the same code for stores--don't special case proc64.
768
aaff8437
ILT		 769 * gencode.c (build_mips16_operands): Fix base PC value for PC
770 relative operands.
771 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
772 jal instruction.
773 * interp.c (simJALDELAYSLOT): Define.
774 (JALDELAYSLOT): Define.
775 (INDELAYSLOT, INJALDELAYSLOT): Define.
776 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
777
280f90e1
AMT		 778Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
779
780 * interp.c (sim_open): add flush_cache as a PMON routine
781 (sim_monitor): handle flush_cache by ignoring it
782
aaff8437
ILT		 783Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
784
785 * gencode.c (build_instruction): Use !ByteSwapMem instead of
786 BigEndianMem.
787 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
788 (BigEndianMem): Rename to ByteSwapMem and change sense.
789 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
790 BigEndianMem references to !ByteSwapMem.
791 (set_endianness): New function, with prototype.
792 (sim_open): Call set_endianness.
793 (sim_info): Use simBE instead of BigEndianMem.
794 (xfer_direct_word, xfer_direct_long, swap_direct_word,
795 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
796 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
797 ifdefs, keeping the prototype declaration.
798 (swap_word): Rewrite correctly.
799 (ColdReset): Delete references to CONFIG. Delete endianness related
800 code; moved to set_endianness.
801
6429b296
JW		 802Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
803
804 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
805 * interp.c (CHECKHILO): Define away.
806 (simSIGINT): New macro.
807 (membank_size): Increase from 1MB to 2MB.
808 (control_c): New function.
809 (sim_resume): Rename parameter signal to signal_number. Add local
810 variable prev. Call signal before and after simulate.
811 (sim_stop_reason): Add simSIGINT support.
812 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
813 functions always.
814 (sim_warning): Delete call to SignalException. Do call printf_filtered
815 if logfh is NULL.
816 (AddressTranslation): Add #ifdef DEBUG around debugging message and
817 a call to sim_warning.
818
819Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
820
821 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
822 16 bit instructions.
823
831f59a2
ILT		 824Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
825
826 Add support for mips16 (16 bit MIPS implementation):
827 * gencode.c (inst_type): Add mips16 instruction encoding types.
828 (GETDATASIZEINSN): Define.
829 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
830 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
831 mtlo.
832 (MIPS16_DECODE): New table, for mips16 instructions.
833 (bitmap_val): New static function.
834 (struct mips16_op): Define.
835 (mips16_op_table): New table, for mips16 operands.
836 (build_mips16_operands): New static function.
837 (process_instructions): If PC is odd, decode a mips16
838 instruction. Break out instruction handling into new
839 build_instruction function.
840 (build_instruction): New static function, broken out of
841 process_instructions. Check modifiers rather than flags for SHIFT
842 bit count and m[ft]{hi,lo} direction.
843 (usage): Pass program name to fprintf.
844 (main): Remove unused variable this_option_optind. Change
845 ``*loptarg++'' to ``loptarg++''.
846 (my_strtoul): Parenthesize && within ||.
350d33b8 847 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
831f59a2
ILT		 848 (simulate): If PC is odd, fetch a 16 bit instruction, and
849 increment PC by 2 rather than 4.
850 * configure.in: Add case for mips16*-*-*.
851 * configure: Rebuild.
852
853Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
854
855 * interp.c: Allow -t to enable tracing in standalone simulator.
856 Fix garbage output in trace file and error messages.
857
e3d12c65
DE		 858Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
859
860 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
861 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
862 * configure.in: Simplify using macros in ../common/aclocal.m4.
863 * configure: Regenerated.
864 * tconfig.in: New file.
865
866Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
867
868 * interp.c: Fix bugs in 64-bit port.
869 Use ansi function declarations for msvc compiler.
870 Initialize and test file pointer in trace code.
871 Prevent duplicate definition of LAST_EMED_REGNUM.
872
873Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
874
875 * interp.c (xfer_big_long): Prevent unwanted sign extension.
876
877Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
878
879 * interp.c (SignalException): Check for explicit terminating
880 breakpoint value.
881 * gencode.c: Pass instruction value through SignalException()
882 calls for Trap, Breakpoint and Syscall.
883
884Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
885
886 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
887 only used on those hosts that provide it.
888 * configure.in: Add sqrt() to list of functions to be checked for.
889 * config.in: Re-generated.
890 * configure: Re-generated.
891
892Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
893
894 * gencode.c (process_instructions): Call build_endian_shift when
895 expanding STORE RIGHT, to fix swr.
896 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
897 clear the high bits.
898 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
899 Fix float to int conversions to produce signed values.
900
cc5201d7
ILT		 901Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
902
458e1f58
ILT		 903 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
904 (process_instructions): Correct handling of nor instruction.
905 Correct shift count for 32 bit shift instructions. Correct sign
906 extension for arithmetic shifts to not shift the number of bits in
907 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
908 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
909 Fix madd.
c05d1721
ILT		 910 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
911 It's OK to have a mult follow a mult. What's not OK is to have a
912 mult follow an mfhi.
458e1f58 913 (Convert): Comment out incorrect rounding code.
cc5201d7 914
f24b7b69
JSC		 915Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
916
917 * interp.c (sim_monitor): Improved monitor printf
918 simulation. Tidied up simulator warnings, and added "--log" option
919 for directing warning message output.
920 * gencode.c: Use sim_warning() rather than WARNING macro.
921
922Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
923
924 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
925 getopt1.o, rather than on gencode.c. Link objects together.
926 Don't link against -liberty.
927 (gencode.o, getopt.o, getopt1.o): New targets.
928 * gencode.c: Include <ctype.h> and "ansidecl.h".
929 (AND): Undefine after including "ansidecl.h".
930 (ULONG_MAX): Define if not defined.
931 (OP_*): Don't define macros; now defined in opcode/mips.h.
932 (main): Call my_strtoul rather than strtoul.
933 (my_strtoul): New static function.
934
935Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
936
937 * gencode.c (process_instructions): Generate word64 and uword64
938 instead of `long long' and `unsigned long long' data types.
939 * interp.c: #include sysdep.h to get signals, and define default
940 for SIGBUS.
941 * (Convert): Work around for Visual-C++ compiler bug with type
942 conversion.
943 * support.h: Make things compile under Visual-C++ by using
944 __int64 instead of `long long'. Change many refs to long long
945 into word64/uword64 typedefs.
946
a271d1d9
JM		 947Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
948
949 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
950 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
951 (docdir): Removed.
952 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
953 (AC_PROG_INSTALL): Added.
954 (AC_PROG_CC): Moved to before configure.host call.
955 * configure: Rebuilt.
956
957Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
958
959 * configure.in: Define @SIMCONF@ depending on mips target.
960 * configure: Rebuild.
961 * Makefile.in (run): Add @SIMCONF@ to control simulator
962 construction.
963 * gencode.c: Change LOADDRMASK to 64bit memory model only.
964 * interp.c: Remove some debugging, provide more detailed error
965 messages, update memory accesses to use LOADDRMASK.
966
4fa134be
ILT		 967Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
968
969 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
970 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
971 stamp-h.
972 * configure: Rebuild.
973 * config.in: New file, generated by autoheader.
974 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
975 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
976 HAVE_ANINT and HAVE_AINT, as appropriate.
977 * Makefile.in (run): Use @LIBS@ rather than -lm.
978 (interp.o): Depend upon config.h.
979 (Makefile): Just rebuild Makefile.
980 (clean): Remove stamp-h.
981 (mostlyclean): Make the same as clean, not as distclean.
982 (config.h, stamp-h): New targets.
983
984Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
985
986 * interp.c (ColdReset): Fix boolean test. Make all simulator
987 globals static.
988
f7481d45
JSC		 989Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
990
991 * interp.c (xfer_direct_word, xfer_direct_long,
992 swap_direct_word, swap_direct_long, xfer_big_word,
993 xfer_big_long, xfer_little_word, xfer_little_long,
994 swap_word,swap_long): Added.
995 * interp.c (ColdReset): Provide function indirection to
996 host<->simulated_target transfer routines.
997 * interp.c (sim_store_register, sim_fetch_register): Updated to
998 make use of indirected transfer routines.
999
1000Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
1001
1002 * gencode.c (process_instructions): Ensure FP ABS instruction
1003 recognised.
1004 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
1005 system call support.
1006
8b554809
JSC		 1007Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
1008
1009 * interp.c (sim_do_command): Complain if callback structure not
1010 initialised.
1011
d0757082
JSC		 1012Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
1013
1014 * interp.c (Convert): Provide round-to-nearest and round-to-zero
1015 support for Sun hosts.
1016 * Makefile.in (gencode): Ensure the host compiler and libraries
1017 used for cross-hosted build.
1018
e871dd18
JSC		 1019Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
1020
1021 * interp.c, gencode.c: Some more (TODO) tidying.
1022
1023Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
1024
1025 * gencode.c, interp.c: Replaced explicit long long references with
1026 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
1027 * support.h (SET64LO, SET64HI): Macros added.
1028
5c59ec43
ILT		 1029Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
1030
1031 * configure: Regenerate with autoconf 2.7.
1032
1033Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
1034
1035 * interp.c (LoadMemory): Enclose text following #endif in /* */.
1036 * support.h: Remove superfluous "1" from #if.
1037 * support.h (CHECKSIM): Remove stray 'a' at end of line.
1038
1039Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
1040
1041 * interp.c (StoreFPR): Control UndefinedResult() call on
1042 WARN_RESULT manifest.
1043
8bae0a0c
JSC		 1044Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
1045
1046 * gencode.c: Tidied instruction decoding, and added FP instruction
1047 support.
1048
1049 * interp.c: Added dineroIII, and BSD profiling support. Also
1050 run-time FP handling.
1051
1052Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
1053
1054 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
1055 gencode.c, interp.c, support.h: created.
GDB Binutils - Deliverables
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