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[deliverable/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
35695fd6
AC		 12005-01-14 Andrew Cagney <cagney@gnu.org>
2
3 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
4 explicit call to AC_CONFIG_HEADER.
5 * configure: Regenerate.
6
f0569246
AC		 72005-01-12 Andrew Cagney <cagney@gnu.org>
8
9 * configure.ac: Update to use ../common/common.m4.
10 * configure: Re-generate.
11
38f48d72
AC		 122005-01-11 Andrew Cagney <cagney@localhost.localdomain>
13
14 * configure: Regenerated to track ../common/aclocal.m4 changes.
15
b7026657
AC		 162005-01-07 Andrew Cagney <cagney@gnu.org>
17
18 * configure.ac: Rename configure.in, require autoconf 2.59.
19 * configure: Re-generate.
20
379832de
HPN		 212004-12-08 Hans-Peter Nilsson <hp@axis.com>
22
23 * configure: Regenerate for ../common/aclocal.m4 update.
24
cd62154c
AC		 252004-09-24 Monika Chaddha <monika@acmet.com>
26
27 Committed by Andrew Cagney.
28 * m16.igen (CMP, CMPI): Fix assembler.
29
e5da76ec
CD		 302004-08-18 Chris Demetriou <cgd@broadcom.com>
31
32 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
33 * configure: Regenerate.
34
139181c8
CD		 352004-06-25 Chris Demetriou <cgd@broadcom.com>
36
37 * configure.in (sim_m16_machine): Include mipsIII.
38 * configure: Regenerate.
39
1a27f959
CD		 402004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
41
42 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
43 from COP0_BADVADDR.
44 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
45
5dbb7b5a
CD		 462004-04-10 Chris Demetriou <cgd@broadcom.com>
47
48 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
49
14234056
CD		 502004-04-09 Chris Demetriou <cgd@broadcom.com>
51
52 * mips.igen (check_fmt): Remove.
53 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
54 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
55 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
56 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
57 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
58 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
59 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
60 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
61 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
62 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
63
c6f9085c
CD		 642004-04-09 Chris Demetriou <cgd@broadcom.com>
65
66 * sb1.igen (check_sbx): New function.
67 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
68
11d66e66 692004-03-29 Chris Demetriou <cgd@broadcom.com>
0e1b7197
RS		 70 Richard Sandiford <rsandifo@redhat.com>
71
72 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
73 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
74 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
75 separate implementations for mipsIV and mipsV. Use new macros to
76 determine whether the restrictions apply.
77
b3208fb8
CD		 782004-01-19 Chris Demetriou <cgd@broadcom.com>
79
80 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
81 (check_mult_hilo): Improve comments.
82 (check_div_hilo): Likewise. Also, fork off a new version
83 to handle mips32/mips64 (since there are no hazards to check
84 in MIPS32/MIPS64).
85
9a1d84fb
CD		 862003-06-17 Richard Sandiford <rsandifo@redhat.com>
87
88 * mips.igen (do_dmultx): Fix check for negative operands.
89
ae451ac6
ILT		 902003-05-16 Ian Lance Taylor <ian@airs.com>
91
92 * Makefile.in (SHELL): Make sure this is defined.
93 (various): Use $(SHELL) whenever we invoke move-if-change.
94
dd69d292
CD		 952003-05-03 Chris Demetriou <cgd@broadcom.com>
96
97 * cp1.c: Tweak attribution slightly.
98 * cp1.h: Likewise.
99 * mdmx.c: Likewise.
100 * mdmx.igen: Likewise.
101 * mips3d.igen: Likewise.
102 * sb1.igen: Likewise.
103
bcd0068e
CD		 1042003-04-15 Richard Sandiford <rsandifo@redhat.com>
105
106 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
107 unsigned operands.
108
6b4a8935
AC		 1092003-02-27 Andrew Cagney <cagney@redhat.com>
110
601da316
AC		 111 * interp.c (sim_open): Rename _bfd to bfd.
112 (sim_create_inferior): Ditto.
6b4a8935 113
d29e330f
CD		 1142003-01-14 Chris Demetriou <cgd@broadcom.com>
115
116 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
117
a2353a08
CD		 1182003-01-14 Chris Demetriou <cgd@broadcom.com>
119
120 * mips.igen (EI, DI): Remove.
121
80551777
CD		 1222003-01-05 Richard Sandiford <rsandifo@redhat.com>
123
124 * Makefile.in (tmp-run-multi): Fix mips16 filter.
125
4c54fc26
CD		 1262003-01-04 Richard Sandiford <rsandifo@redhat.com>
127 Andrew Cagney <ac131313@redhat.com>
128 Gavin Romig-Koch <gavin@redhat.com>
129 Graydon Hoare <graydon@redhat.com>
130 Aldy Hernandez <aldyh@redhat.com>
131 Dave Brolley <brolley@redhat.com>
132 Chris Demetriou <cgd@broadcom.com>
133
134 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
135 (sim_mach_default): New variable.
136 (mips64vr-*-*, mips64vrel-*-*): New configurations.
137 Add a new simulator generator, MULTI.
138 * configure: Regenerate.
139 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
140 (multi-run.o): New dependency.
141 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
142 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
143 (tmp-multi): Combine them.
144 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
145 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
146 (distclean-extra): New rule.
147 * sim-main.h: Include bfd.h.
148 (MIPS_MACH): New macro.
149 * mips.igen (vr4120, vr5400, vr5500): New models.
150 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
151 * vr.igen: Replace with new version.
152
e6c674b8
CD		 1532003-01-04 Chris Demetriou <cgd@broadcom.com>
154
155 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
156 * configure: Regenerate.
157
28f50ac8
CD		 1582002-12-31 Chris Demetriou <cgd@broadcom.com>
159
160 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
161 * mips.igen: Remove all invocations of check_branch_bug and
162 mark_branch_bug.
163
5071ffe6
CD		 1642002-12-16 Chris Demetriou <cgd@broadcom.com>
165
166 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
167
06e7837e
CD		 1682002-07-30 Chris Demetriou <cgd@broadcom.com>
169
170 * mips.igen (do_load_double, do_store_double): New functions.
171 (LDC1, SDC1): Rename to...
172 (LDC1b, SDC1b): respectively.
173 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
174
2265c243
MS		 1752002-07-29 Michael Snyder <msnyder@redhat.com>
176
177 * cp1.c (fp_recip2): Modify initialization expression so that
178 GCC will recognize it as constant.
179
a2f8b4f3
CD		 1802002-06-18 Chris Demetriou <cgd@broadcom.com>
181
182 * mdmx.c (SD_): Delete.
183 (Unpredictable): Re-define, for now, to directly invoke
184 unpredictable_action().
185 (mdmx_acc_op): Fix error in .ob immediate handling.
186
b4b6c939
AC		 1872002-06-18 Andrew Cagney <cagney@redhat.com>
188
189 * interp.c (sim_firmware_command): Initialize `address'.
190
c8cca39f
AC		 1912002-06-16 Andrew Cagney <ac131313@redhat.com>
192
193 * configure: Regenerated to track ../common/aclocal.m4 changes.
194
e7e81181
CD		 1952002-06-14 Chris Demetriou <cgd@broadcom.com>
196 Ed Satterthwaite <ehs@broadcom.com>
197
198 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
199 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
200 * mips.igen: Include mips3d.igen.
201 (mips3d): New model name for MIPS-3D ASE instructions.
202 (CVT.W.fmt): Don't use this instruction for word (source) format
203 instructions.
204 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
205 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
206 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
207 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
208 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
209 (RSquareRoot1, RSquareRoot2): New macros.
210 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
211 (fp_rsqrt2): New functions.
212 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
213 * configure: Regenerate.
214
3a2b820e 2152002-06-13 Chris Demetriou <cgd@broadcom.com>
eab54952 216 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 217
218 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
219 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
220 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
221 (convert): Note that this function is not used for paired-single
222 format conversions.
223 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
224 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
225 (check_fmt_p): Enable paired-single support.
226 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
227 (PUU.PS): New instructions.
228 (CVT.S.fmt): Don't use this instruction for paired-single format
229 destinations.
230 * sim-main.h (FP_formats): New value 'fmt_ps.'
231 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
232 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
233
d18ea9c2
CD		 2342002-06-12 Chris Demetriou <cgd@broadcom.com>
235
236 * mips.igen: Fix formatting of function calls in
237 many FP operations.
238
95fd5cee
CD		 2392002-06-12 Chris Demetriou <cgd@broadcom.com>
240
241 * mips.igen (MOVN, MOVZ): Trace result.
242 (TNEI): Print "tnei" as the opcode name in traces.
243 (CEIL.W): Add disassembly string for traces.
244 (RSQRT.fmt): Make location of disassembly string consistent
245 with other instructions.
246
4f0d55ae
CD		 2472002-06-12 Chris Demetriou <cgd@broadcom.com>
248
249 * mips.igen (X): Delete unused function.
250
3c25f8c7
AC		 2512002-06-08 Andrew Cagney <cagney@redhat.com>
252
253 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
254
f3c08b7e
CD		 2552002-06-07 Chris Demetriou <cgd@broadcom.com>
256 Ed Satterthwaite <ehs@broadcom.com>
257
258 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
259 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
260 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
261 (fp_nmsub): New prototypes.
262 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
263 (NegMultiplySub): New defines.
264 * mips.igen (RSQRT.fmt): Use RSquareRoot().
265 (MADD.D, MADD.S): Replace with...
266 (MADD.fmt): New instruction.
267 (MSUB.D, MSUB.S): Replace with...
268 (MSUB.fmt): New instruction.
269 (NMADD.D, NMADD.S): Replace with...
270 (NMADD.fmt): New instruction.
271 (NMSUB.D, MSUB.S): Replace with...
272 (NMSUB.fmt): New instruction.
273
52714ff9
CD		 2742002-06-07 Chris Demetriou <cgd@broadcom.com>
275 Ed Satterthwaite <ehs@broadcom.com>
276
277 * cp1.c: Fix more comment spelling and formatting.
278 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
279 (denorm_mode): New function.
280 (fpu_unary, fpu_binary): Round results after operation, collect
281 status from rounding operations, and update the FCSR.
282 (convert): Collect status from integer conversions and rounding
283 operations, and update the FCSR. Adjust NaN values that result
284 from conversions. Convert to use sim_io_eprintf rather than
285 fprintf, and remove some debugging code.
286 * cp1.h (fenr_FS): New define.
287
577d8c4b
CD		 2882002-06-07 Chris Demetriou <cgd@broadcom.com>
289
290 * cp1.c (convert): Remove unusable debugging code, and move MIPS
291 rounding mode to sim FP rounding mode flag conversion code into...
292 (rounding_mode): New function.
293
196496ed
CD		 2942002-06-07 Chris Demetriou <cgd@broadcom.com>
295
296 * cp1.c: Clean up formatting of a few comments.
297 (value_fpr): Reformat switch statement.
298
cfe9ea23
CD		 2992002-06-06 Chris Demetriou <cgd@broadcom.com>
300 Ed Satterthwaite <ehs@broadcom.com>
301
302 * cp1.h: New file.
303 * sim-main.h: Include cp1.h.
304 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
305 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
306 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
307 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
308 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
309 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
310 * cp1.c: Don't include sim-fpu.h; already included by
311 sim-main.h. Clean up formatting of some comments.
312 (NaN, Equal, Less): Remove.
313 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
314 (fp_cmp): New functions.
315 * mips.igen (do_c_cond_fmt): Remove.
316 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
317 Compare. Add result tracing.
318 (CxC1): Remove, replace with...
319 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
320 (DMxC1): Remove, replace with...
321 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
322 (MxC1): Remove, replace with...
323 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
324
ee7254b0
CD		 3252002-06-04 Chris Demetriou <cgd@broadcom.com>
326
327 * sim-main.h (FGRIDX): Remove, replace all uses with...
328 (FGR_BASE): New macro.
329 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
330 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
331 (NR_FGR, FGR): Likewise.
332 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
333 * mips.igen: Likewise.
334
d3eb724f
CD		 3352002-06-04 Chris Demetriou <cgd@broadcom.com>
336
337 * cp1.c: Add an FSF Copyright notice to this file.
338
ba46ddd0
CD		 3392002-06-04 Chris Demetriou <cgd@broadcom.com>
340 Ed Satterthwaite <ehs@broadcom.com>
341
342 * cp1.c (Infinity): Remove.
343 * sim-main.h (Infinity): Likewise.
344
345 * cp1.c (fp_unary, fp_binary): New functions.
346 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
347 (fp_sqrt): New functions, implemented in terms of the above.
348 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
349 (Recip, SquareRoot): Remove (replaced by functions above).
350 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
351 (fp_recip, fp_sqrt): New prototypes.
352 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
353 (Recip, SquareRoot): Replace prototypes with #defines which
354 invoke the functions above.
355
18d8a52d
CD		 3562002-06-03 Chris Demetriou <cgd@broadcom.com>
357
358 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
359 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
360 file, remove PARAMS from prototypes.
361 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
362 simulator state arguments.
363 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
364 pass simulator state arguments.
365 * cp1.c (SD): Redefine as CPU_STATE(cpu).
366 (store_fpr, convert): Remove 'sd' argument.
367 (value_fpr): Likewise. Convert to use 'SD' instead.
368
0f154cbd
CD		 3692002-06-03 Chris Demetriou <cgd@broadcom.com>
370
371 * cp1.c (Min, Max): Remove #if 0'd functions.
372 * sim-main.h (Min, Max): Remove.
373
e80fc152
CD		 3742002-06-03 Chris Demetriou <cgd@broadcom.com>
375
376 * cp1.c: fix formatting of switch case and default labels.
377 * interp.c: Likewise.
378 * sim-main.c: Likewise.
379
bad673a9
CD		 3802002-06-03 Chris Demetriou <cgd@broadcom.com>
381
382 * cp1.c: Clean up comments which describe FP formats.
383 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
384
7cbea089
CD		 3852002-06-03 Chris Demetriou <cgd@broadcom.com>
386 Ed Satterthwaite <ehs@broadcom.com>
387
388 * configure.in (mipsisa64sb1*-*-*): New target for supporting
389 Broadcom SiByte SB-1 processor configurations.
390 * configure: Regenerate.
391 * sb1.igen: New file.
392 * mips.igen: Include sb1.igen.
393 (sb1): New model.
394 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
395 * mdmx.igen: Add "sb1" model to all appropriate functions and
396 instructions.
397 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
398 (ob_func, ob_acc): Reference the above.
399 (qh_acc): Adjust to keep the same size as ob_acc.
400 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
401 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
402
909daa82
CD		 4032002-06-03 Chris Demetriou <cgd@broadcom.com>
404
405 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
406
f4f1b9f1
CD		 4072002-06-02 Chris Demetriou <cgd@broadcom.com>
408 Ed Satterthwaite <ehs@broadcom.com>
409
410 * mips.igen (mdmx): New (pseudo-)model.
411 * mdmx.c, mdmx.igen: New files.
412 * Makefile.in (SIM_OBJS): Add mdmx.o.
413 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
414 New typedefs.
415 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
416 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
417 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
418 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
419 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
420 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
421 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
422 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
423 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
424 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
425 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
426 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
427 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
428 (qh_fmtsel): New macros.
429 (_sim_cpu): New member "acc".
430 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
431 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
432
5accf1ff
CD		 4332002-05-01 Chris Demetriou <cgd@broadcom.com>
434
435 * interp.c: Use 'deprecated' rather than 'depreciated.'
436 * sim-main.h: Likewise.
437
402586aa
CD		 4382002-05-01 Chris Demetriou <cgd@broadcom.com>
439
440 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
441 which wouldn't compile anyway.
442 * sim-main.h (unpredictable_action): New function prototype.
443 (Unpredictable): Define to call igen function unpredictable().
444 (NotWordValue): New macro to call igen function not_word_value().
445 (UndefinedResult): Remove.
446 * interp.c (undefined_result): Remove.
447 (unpredictable_action): New function.
448 * mips.igen (not_word_value, unpredictable): New functions.
449 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
450 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
451 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
452 NotWordValue() to check for unpredictable inputs, then
453 Unpredictable() to handle them.
454
c9b9995a
CD		 4552002-02-24 Chris Demetriou <cgd@broadcom.com>
456
457 * mips.igen: Fix formatting of calls to Unpredictable().
458
e1015982
AC		 4592002-04-20 Andrew Cagney <ac131313@redhat.com>
460
461 * interp.c (sim_open): Revert previous change.
462
b882a66b
AO		 4632002-04-18 Alexandre Oliva <aoliva@redhat.com>
464
465 * interp.c (sim_open): Disable chunk of code that wrote code in
466 vector table entries.
467
c429b7dd
CD		 4682002-03-19 Chris Demetriou <cgd@broadcom.com>
469
470 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
471 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
472 unused definitions.
473
37d146fa
CD		 4742002-03-19 Chris Demetriou <cgd@broadcom.com>
475
476 * cp1.c: Fix many formatting issues.
477
07892c0b
CD		 4782002-03-19 Chris G. Demetriou <cgd@broadcom.com>
479
480 * cp1.c (fpu_format_name): New function to replace...
481 (DOFMT): This. Delete, and update all callers.
482 (fpu_rounding_mode_name): New function to replace...
483 (RMMODE): This. Delete, and update all callers.
484
487f79b7
CD		 4852002-03-19 Chris G. Demetriou <cgd@broadcom.com>
486
487 * interp.c: Move FPU support routines from here to...
488 * cp1.c: Here. New file.
489 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
490 (cp1.o): New target.
491
1e799e28
CD		 4922002-03-12 Chris Demetriou <cgd@broadcom.com>
493
494 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
495 * mips.igen (mips32, mips64): New models, add to all instructions
496 and functions as appropriate.
497 (loadstore_ea, check_u64): New variant for model mips64.
498 (check_fmt_p): New variant for models mipsV and mips64, remove
499 mipsV model marking fro other variant.
500 (SLL) Rename to...
501 (SLLa) this.
502 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
503 for mips32 and mips64.
504 (DCLO, DCLZ): New instructions for mips64.
505
82f728db
CD		 5062002-03-07 Chris Demetriou <cgd@broadcom.com>
507
508 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
509 immediate or code as a hex value with the "%#lx" format.
510 (ANDI): Likewise, and fix printed instruction name.
511
b96e7ef1
CD		 5122002-03-05 Chris Demetriou <cgd@broadcom.com>
513
514 * sim-main.h (UndefinedResult, Unpredictable): New macros
515 which currently do nothing.
516
d35d4f70
CD		 5172002-03-05 Chris Demetriou <cgd@broadcom.com>
518
519 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
520 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
521 (status_CU3): New definitions.
522
523 * sim-main.h (ExceptionCause): Add new values for MIPS32
524 and MIPS64: MDMX, MCheck, CacheErr. Update comments
525 for DebugBreakPoint and NMIReset to note their status in
526 MIPS32 and MIPS64.
527 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
528 (SignalExceptionCacheErr): New exception macros.
529
3ad6f714
CD		 5302002-03-05 Chris Demetriou <cgd@broadcom.com>
531
532 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
533 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
534 is always enabled.
535 (SignalExceptionCoProcessorUnusable): Take as argument the
536 unusable coprocessor number.
537
86b77b47
CD		 5382002-03-05 Chris Demetriou <cgd@broadcom.com>
539
540 * mips.igen: Fix formatting of all SignalException calls.
541
97a88e93 5422002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 543
544 * sim-main.h (SIGNEXTEND): Remove.
545
97a88e93 5462002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 547
548 * mips.igen: Remove gencode comment from top of file, fix
549 spelling in another comment.
550
97a88e93 5512002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 552
553 * mips.igen (check_fmt, check_fmt_p): New functions to check
554 whether specific floating point formats are usable.
555 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
556 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
557 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
558 Use the new functions.
559 (do_c_cond_fmt): Remove format checks...
560 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
561
97a88e93 5622002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 563
564 * mips.igen: Fix formatting of check_fpu calls.
565
41774c9d
CD		 5662002-03-03 Chris Demetriou <cgd@broadcom.com>
567
568 * mips.igen (FLOOR.L.fmt): Store correct destination register.
569
4a0bd876
CD		 5702002-03-03 Chris Demetriou <cgd@broadcom.com>
571
572 * mips.igen: Remove whitespace at end of lines.
573
09297648
CD		 5742002-03-02 Chris Demetriou <cgd@broadcom.com>
575
576 * mips.igen (loadstore_ea): New function to do effective
577 address calculations.
578 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
579 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
580 CACHE): Use loadstore_ea to do effective address computations.
581
043b7057
CD		 5822002-03-02 Chris Demetriou <cgd@broadcom.com>
583
584 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
585 * mips.igen (LL, CxC1, MxC1): Likewise.
586
c1e8ada4
CD		 5872002-03-02 Chris Demetriou <cgd@broadcom.com>
588
589 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
590 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
591 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
592 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
593 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
594 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
595 Don't split opcode fields by hand, use the opcode field values
596 provided by igen.
597
3e1dca16
CD		 5982002-03-01 Chris Demetriou <cgd@broadcom.com>
599
600 * mips.igen (do_divu): Fix spacing.
601
602 * mips.igen (do_dsllv): Move to be right before DSLLV,
603 to match the rest of the do_<shift> functions.
604
fff8d27d
CD		 6052002-03-01 Chris Demetriou <cgd@broadcom.com>
606
607 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
608 DSRL32, do_dsrlv): Trace inputs and results.
609
0d3e762b
CD		 6102002-03-01 Chris Demetriou <cgd@broadcom.com>
611
612 * mips.igen (CACHE): Provide instruction-printing string.
613
614 * interp.c (signal_exception): Comment tokens after #endif.
615
eb5fcf93
CD		 6162002-02-28 Chris Demetriou <cgd@broadcom.com>
617
618 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
619 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
620 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
621 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
622 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
623 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
624 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
625 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
626
bb22bd7d
CD		 6272002-02-28 Chris Demetriou <cgd@broadcom.com>
628
629 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
630 instruction-printing string.
631 (LWU): Use '64' as the filter flag.
632
91a177cf
CD		 6332002-02-28 Chris Demetriou <cgd@broadcom.com>
634
635 * mips.igen (SDXC1): Fix instruction-printing string.
636
387f484a
CD		 6372002-02-28 Chris Demetriou <cgd@broadcom.com>
638
639 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
640 filter flags "32,f".
641
3d81f391
CD		 6422002-02-27 Chris Demetriou <cgd@broadcom.com>
643
644 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
645 as the filter flag.
646
af5107af
CD		 6472002-02-27 Chris Demetriou <cgd@broadcom.com>
648
649 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
650 add a comma) so that it more closely match the MIPS ISA
651 documentation opcode partitioning.
652 (PREF): Put useful names on opcode fields, and include
653 instruction-printing string.
654
ca971540
CD		 6552002-02-27 Chris Demetriou <cgd@broadcom.com>
656
657 * mips.igen (check_u64): New function which in the future will
658 check whether 64-bit instructions are usable and signal an
659 exception if not. Currently a no-op.
660 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
661 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
662 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
663 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
664
665 * mips.igen (check_fpu): New function which in the future will
666 check whether FPU instructions are usable and signal an exception
667 if not. Currently a no-op.
668 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
669 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
670 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
671 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
672 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
673 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
674 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
675 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
676
1c47a468
CD		 6772002-02-27 Chris Demetriou <cgd@broadcom.com>
678
679 * mips.igen (do_load_left, do_load_right): Move to be immediately
680 following do_load.
681 (do_store_left, do_store_right): Move to be immediately following
682 do_store.
683
603a98e7
CD		 6842002-02-27 Chris Demetriou <cgd@broadcom.com>
685
686 * mips.igen (mipsV): New model name. Also, add it to
687 all instructions and functions where it is appropriate.
688
c5d00cc7
CD		 6892002-02-18 Chris Demetriou <cgd@broadcom.com>
690
691 * mips.igen: For all functions and instructions, list model
692 names that support that instruction one per line.
693
074e9cb8
CD		 6942002-02-11 Chris Demetriou <cgd@broadcom.com>
695
696 * mips.igen: Add some additional comments about supported
697 models, and about which instructions go where.
698 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
699 order as is used in the rest of the file.
700
9805e229
CD		 7012002-02-11 Chris Demetriou <cgd@broadcom.com>
702
703 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
704 indicating that ALU32_END or ALU64_END are there to check
705 for overflow.
706 (DADD): Likewise, but also remove previous comment about
707 overflow checking.
708
f701dad2
CD		 7092002-02-10 Chris Demetriou <cgd@broadcom.com>
710
711 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
712 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
713 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
714 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
715 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
716 fields (i.e., add and move commas) so that they more closely
717 match the MIPS ISA documentation opcode partitioning.
718
7192002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098
CD		 720
721 * mips.igen (ADDI): Print immediate value.
722 (BREAK): Print code.
723 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
724 (SLL): Print "nop" specially, and don't run the code
725 that does the shift for the "nop" case.
726
9e52972e
FF		 7272001-11-17 Fred Fish <fnf@redhat.com>
728
729 * sim-main.h (float_operation): Move enum declaration outside
730 of _sim_cpu struct declaration.
731
c0efbca4
JB		 7322001-04-12 Jim Blandy <jimb@redhat.com>
733
734 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
735 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
736 set of the FCSR.
737 * sim-main.h (COCIDX): Remove definition; this isn't supported by
738 PENDING_FILL, and you can get the intended effect gracefully by
739 calling PENDING_SCHED directly.
740
fb891446
BE		 7412001-02-23 Ben Elliston <bje@redhat.com>
742
743 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
744 already defined elsewhere.
745
8030f857
BE		 7462001-02-19 Ben Elliston <bje@redhat.com>
747
748 * sim-main.h (sim_monitor): Return an int.
749 * interp.c (sim_monitor): Add return values.
750 (signal_exception): Handle error conditions from sim_monitor.
751
56b48a7a
CD		 7522001-02-08 Ben Elliston <bje@redhat.com>
753
754 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
755 (store_memory): Likewise, pass cia to sim_core_write*.
756
d3ee60d9
FCE		 7572000-10-19 Frank Ch. Eigler <fche@redhat.com>
758
759 On advice from Chris G. Demetriou <cgd@sibyte.com>:
760 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
761
071da002
AC		 762Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
763
764 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
765 * Makefile.in: Don't delete *.igen when cleaning directory.
766
a28c02cd
AC		 767Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
768
769 * m16.igen (break): Call SignalException not sim_engine_halt.
770
80ee11fa
AC		 771Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
772
773 From Jason Eckhardt:
774 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
775
673388c0
AC		 776Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
777
778 * mips.igen (MxC1, DMxC1): Fix printf formatting.
779
4c0deff4
NC		 7802000-05-24 Michael Hayes <mhayes@cygnus.com>
781
782 * mips.igen (do_dmultx): Fix typo.
783
eb2d80b4
AC		 784Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
785
786 * configure: Regenerated to track ../common/aclocal.m4 changes.
787
dd37a34b
AC		 788Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
789
790 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
791
4c0deff4
NC		 7922000-04-12 Frank Ch. Eigler <fche@redhat.com>
793
794 * sim-main.h (GPR_CLEAR): Define macro.
795
e30db738
AC		 796Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
797
798 * interp.c (decode_coproc): Output long using %lx and not %s.
799
cb7450ea
FCE		 8002000-03-21 Frank Ch. Eigler <fche@redhat.com>
801
802 * interp.c (sim_open): Sort & extend dummy memory regions for
803 --board=jmr3904 for eCos.
804
a3027dd7
FCE		 8052000-03-02 Frank Ch. Eigler <fche@redhat.com>
806
807 * configure: Regenerated.
808
809Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
810
811 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
812 calls, conditional on the simulator being in verbose mode.
813
dfcd3bfb
JM		 814Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
815
816 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
817 cache don't get ReservedInstruction traps.
818
c2d11a7d
JM		 8191999-11-29 Mark Salter <msalter@cygnus.com>
820
821 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
822 to clear status bits in sdisr register. This is how the hardware works.
823
824 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
825 being used by cygmon.
826
4ce44c66
JM		 8271999-11-11 Andrew Haley <aph@cygnus.com>
828
829 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
830 instructions.
831
cff3e48b
JM		 832Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
833
834 * mips.igen (MULT): Correct previous mis-applied patch.
835
d4f3574e
SS		 836Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
837
838 * mips.igen (delayslot32): Handle sequence like
839 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
840 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
841 (MULT): Actually pass the third register...
842
8431999-09-03 Mark Salter <msalter@cygnus.com>
844
845 * interp.c (sim_open): Added more memory aliases for additional
846 hardware being touched by cygmon on jmr3904 board.
847
848Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
849
850 * configure: Regenerated to track ../common/aclocal.m4 changes.
851
a0b3c4fd
JM		 852Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
853
854 * interp.c (sim_store_register): Handle case where client - GDB -
855 specifies that a 4 byte register is 8 bytes in size.
856 (sim_fetch_register): Ditto.
857
adf40b2e
JM		 8581999-07-14 Frank Ch. Eigler <fche@cygnus.com>
859
860 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
861 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
862 (idt_monitor_base): Base address for IDT monitor traps.
863 (pmon_monitor_base): Ditto for PMON.
864 (lsipmon_monitor_base): Ditto for LSI PMON.
865 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
866 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
867 (sim_firmware_command): New function.
868 (mips_option_handler): Call it for OPTION_FIRMWARE.
869 (sim_open): Allocate memory for idt_monitor region. If "--board"
870 option was given, add no monitor by default. Add BREAK hooks only if
871 monitors are also there.
872
43e526b9
JM		 873Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
874
875 * interp.c (sim_monitor): Flush output before reading input.
876
877Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
878
879 * tconfig.in (SIM_HANDLES_LMA): Always define.
880
881Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
882
883 From Mark Salter <msalter@cygnus.com>:
884 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
885 (sim_open): Add setup for BSP board.
886
9846de1b
JM		 887Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
888
889 * mips.igen (MULT, MULTU): Add syntax for two operand version.
890 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
891 them as unimplemented.
892
cd0fc7c3
SS		 8931999-05-08 Felix Lee <flee@cygnus.com>
894
895 * configure: Regenerated to track ../common/aclocal.m4 changes.
896
7a292a7a
SS		 8971999-04-21 Frank Ch. Eigler <fche@cygnus.com>
898
899 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
900
901Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
902
903 * configure.in: Any mips64vr5*-*-* target should have
904 -DTARGET_ENABLE_FR=1.
905 (default_endian): Any mips64vr*el-*-* target should default to
906 LITTLE_ENDIAN.
907 * configure: Re-generate.
908
9091999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
910
911 * mips.igen (ldl): Extend from _16_, not 32.
912
913Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
914
915 * interp.c (sim_store_register): Force registers written to by GDB
916 into an un-interpreted state.
917
c906108c
SS		 9181999-02-05 Frank Ch. Eigler <fche@cygnus.com>
919
920 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
921 CPU, start periodic background I/O polls.
922 (tx3904sio_poll): New function: periodic I/O poller.
923
9241998-12-30 Frank Ch. Eigler <fche@cygnus.com>
925
926 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
927
928Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
929
930 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
931 case statement.
932
9331998-12-29 Frank Ch. Eigler <fche@cygnus.com>
934
935 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
936 (load_word): Call SIM_CORE_SIGNAL hook on error.
937 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
938 starting. For exception dispatching, pass PC instead of NULL_CIA.
939 (decode_coproc): Use COP0_BADVADDR to store faulting address.
940 * sim-main.h (COP0_BADVADDR): Define.
941 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
942 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
943 (_sim_cpu): Add exc_* fields to store register value snapshots.
944 * mips.igen (*): Replace memory-related SignalException* calls
945 with references to SIM_CORE_SIGNAL hook.
946
947 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
948 fix.
949 * sim-main.c (*): Minor warning cleanups.
950
9511998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
952
953 * m16.igen (DADDIU5): Correct type-o.
954
955Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
956
957 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
958 variables.
959
960Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
961
962 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
963 to include path.
964 (interp.o): Add dependency on itable.h
965 (oengine.c, gencode): Delete remaining references.
966 (BUILT_SRC_FROM_GEN): Clean up.
967
9681998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
969
970 * vr4run.c: New.
971 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
972 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
973 tmp-run-hack) : New.
974 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
975 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
976 Drop the "64" qualifier to get the HACK generator working.
977 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
978 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
979 qualifier to get the hack generator working.
980 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
981 (DSLL): Use do_dsll.
982 (DSLLV): Use do_dsllv.
983 (DSRA): Use do_dsra.
984 (DSRL): Use do_dsrl.
985 (DSRLV): Use do_dsrlv.
986 (BC1): Move *vr4100 to get the HACK generator working.
987 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
988 get the HACK generator working.
989 (MACC) Rename to get the HACK generator working.
990 (DMACC,MACCS,DMACCS): Add the 64.
991
9921998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
993
994 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
995 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
996
9971998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
998
999 * mips/interp.c (DEBUG): Cleanups.
1000
10011998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1002
1003 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1004 (tx3904sio_tickle): fflush after a stdout character output.
1005
10061998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1007
1008 * interp.c (sim_close): Uninstall modules.
1009
1010Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1011
1012 * sim-main.h, interp.c (sim_monitor): Change to global
1013 function.
1014
1015Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1016
1017 * configure.in (vr4100): Only include vr4100 instructions in
1018 simulator.
1019 * configure: Re-generate.
1020 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1021
1022Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1023
1024 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1025 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1026 true alternative.
1027
1028 * configure.in (sim_default_gen, sim_use_gen): Replace with
1029 sim_gen.
1030 (--enable-sim-igen): Delete config option. Always using IGEN.
1031 * configure: Re-generate.
1032
1033 * Makefile.in (gencode): Kill, kill, kill.
1034 * gencode.c: Ditto.
1035
1036Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1037
1038 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1039 bit mips16 igen simulator.
1040 * configure: Re-generate.
1041
1042 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1043 as part of vr4100 ISA.
1044 * vr.igen: Mark all instructions as 64 bit only.
1045
1046Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1047
1048 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1049 Pacify GCC.
1050
1051Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1052
1053 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1054 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1055 * configure: Re-generate.
1056
1057 * m16.igen (BREAK): Define breakpoint instruction.
1058 (JALX32): Mark instruction as mips16 and not r3900.
1059 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1060
1061 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1062
1063Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1064
1065 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1066 insn as a debug breakpoint.
1067
1068 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1069 pending.slot_size.
1070 (PENDING_SCHED): Clean up trace statement.
1071 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1072 (PENDING_FILL): Delay write by only one cycle.
1073 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1074
1075 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1076 of pending writes.
1077 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1078 32 & 64.
1079 (pending_tick): Move incrementing of index to FOR statement.
1080 (pending_tick): Only update PENDING_OUT after a write has occured.
1081
1082 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1083 build simulator.
1084 * configure: Re-generate.
1085
1086 * interp.c (sim_engine_run OLD): Delete explicit call to
1087 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1088
1089Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1090
1091 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1092 interrupt level number to match changed SignalExceptionInterrupt
1093 macro.
1094
1095Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1096
1097 * interp.c: #include "itable.h" if WITH_IGEN.
1098 (get_insn_name): New function.
1099 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1100 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1101
1102Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1103
1104 * configure: Rebuilt to inhale new common/aclocal.m4.
1105
1106Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1107
1108 * dv-tx3904sio.c: Include sim-assert.h.
1109
1110Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1111
1112 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1113 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1114 Reorganize target-specific sim-hardware checks.
1115 * configure: rebuilt.
1116 * interp.c (sim_open): For tx39 target boards, set
1117 OPERATING_ENVIRONMENT, add tx3904sio devices.
1118 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1119 ROM executables. Install dv-sockser into sim-modules list.
1120
1121 * dv-tx3904irc.c: Compiler warning clean-up.
1122 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1123 frequent hw-trace messages.
1124
1125Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1126
1127 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1128
1129Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1130
1131 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1132
1133 * vr.igen: New file.
1134 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1135 * mips.igen: Define vr4100 model. Include vr.igen.
1136Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1137
1138 * mips.igen (check_mf_hilo): Correct check.
1139
1140Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1141
1142 * sim-main.h (interrupt_event): Add prototype.
1143
1144 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1145 register_ptr, register_value.
1146 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1147
1148 * sim-main.h (tracefh): Make extern.
1149
1150Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1151
1152 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1153 Reduce unnecessarily high timer event frequency.
1154 * dv-tx3904cpu.c: Ditto for interrupt event.
1155
1156Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1157
1158 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1159 to allay warnings.
1160 (interrupt_event): Made non-static.
1161
1162 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1163 interchange of configuration values for external vs. internal
1164 clock dividers.
1165
1166Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1167
1168 * mips.igen (BREAK): Moved code to here for
1169 simulator-reserved break instructions.
1170 * gencode.c (build_instruction): Ditto.
1171 * interp.c (signal_exception): Code moved from here. Non-
1172 reserved instructions now use exception vector, rather
1173 than halting sim.
1174 * sim-main.h: Moved magic constants to here.
1175
1176Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1177
1178 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1179 register upon non-zero interrupt event level, clear upon zero
1180 event value.
1181 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1182 by passing zero event value.
1183 (*_io_{read,write}_buffer): Endianness fixes.
1184 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1185 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1186
1187 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1188 serial I/O and timer module at base address 0xFFFF0000.
1189
1190Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1191
1192 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1193 and BigEndianCPU.
1194
1195Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1196
1197 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1198 parts.
1199 * configure: Update.
1200
1201Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1202
1203 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1204 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1205 * configure.in: Include tx3904tmr in hw_device list.
1206 * configure: Rebuilt.
1207 * interp.c (sim_open): Instantiate three timer instances.
1208 Fix address typo of tx3904irc instance.
1209
1210Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1211
1212 * interp.c (signal_exception): SystemCall exception now uses
1213 the exception vector.
1214
1215Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1216
1217 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1218 to allay warnings.
1219
1220Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1221
1222 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1223
1224Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1225
1226 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1227
1228 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1229 sim-main.h. Declare a struct hw_descriptor instead of struct
1230 hw_device_descriptor.
1231
1232Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1233
1234 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1235 right bits and then re-align left hand bytes to correct byte
1236 lanes. Fix incorrect computation in do_store_left when loading
1237 bytes from second word.
1238
1239Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1240
1241 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1242 * interp.c (sim_open): Only create a device tree when HW is
1243 enabled.
1244
1245 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1246 * interp.c (signal_exception): Ditto.
1247
1248Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1249
1250 * gencode.c: Mark BEGEZALL as LIKELY.
1251
1252Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1253
1254 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1255 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1256
1257Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1258
1259 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1260 modules. Recognize TX39 target with "mips*tx39" pattern.
1261 * configure: Rebuilt.
1262 * sim-main.h (*): Added many macros defining bits in
1263 TX39 control registers.
1264 (SignalInterrupt): Send actual PC instead of NULL.
1265 (SignalNMIReset): New exception type.
1266 * interp.c (board): New variable for future use to identify
1267 a particular board being simulated.
1268 (mips_option_handler,mips_options): Added "--board" option.
1269 (interrupt_event): Send actual PC.
1270 (sim_open): Make memory layout conditional on board setting.
1271 (signal_exception): Initial implementation of hardware interrupt
1272 handling. Accept another break instruction variant for simulator
1273 exit.
1274 (decode_coproc): Implement RFE instruction for TX39.
1275 (mips.igen): Decode RFE instruction as such.
1276 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1277 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1278 bbegin to implement memory map.
1279 * dv-tx3904cpu.c: New file.
1280 * dv-tx3904irc.c: New file.
1281
1282Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1283
1284 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1285
1286Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1287
1288 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1289 with calls to check_div_hilo.
1290
1291Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1292
1293 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1294 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1295 Add special r3900 version of do_mult_hilo.
1296 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1297 with calls to check_mult_hilo.
1298 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1299 with calls to check_div_hilo.
1300
1301Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1302
1303 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1304 Document a replacement.
1305
1306Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1307
1308 * interp.c (sim_monitor): Make mon_printf work.
1309
1310Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1311
1312 * sim-main.h (INSN_NAME): New arg `cpu'.
1313
1314Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1315
1316 * configure: Regenerated to track ../common/aclocal.m4 changes.
1317
1318Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1319
1320 * configure: Regenerated to track ../common/aclocal.m4 changes.
1321 * config.in: Ditto.
1322
1323Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1324
1325 * acconfig.h: New file.
1326 * configure.in: Reverted change of Apr 24; use sinclude again.
1327
1328Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1329
1330 * configure: Regenerated to track ../common/aclocal.m4 changes.
1331 * config.in: Ditto.
1332
1333Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1334
1335 * configure.in: Don't call sinclude.
1336
1337Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1338
1339 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1340
1341Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1342
1343 * mips.igen (ERET): Implement.
1344
1345 * interp.c (decode_coproc): Return sign-extended EPC.
1346
1347 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1348
1349 * interp.c (signal_exception): Do not ignore Trap.
1350 (signal_exception): On TRAP, restart at exception address.
1351 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1352 (signal_exception): Update.
1353 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1354 so that TRAP instructions are caught.
1355
1356Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1357
1358 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1359 contains HI/LO access history.
1360 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1361 (HIACCESS, LOACCESS): Delete, replace with
1362 (HIHISTORY, LOHISTORY): New macros.
1363 (CHECKHILO): Delete all, moved to mips.igen
1364
1365 * gencode.c (build_instruction): Do not generate checks for
1366 correct HI/LO register usage.
1367
1368 * interp.c (old_engine_run): Delete checks for correct HI/LO
1369 register usage.
1370
1371 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1372 check_mf_cycles): New functions.
1373 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1374 do_divu, domultx, do_mult, do_multu): Use.
1375
1376 * tx.igen ("madd", "maddu"): Use.
1377
1378Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1379
1380 * mips.igen (DSRAV): Use function do_dsrav.
1381 (SRAV): Use new function do_srav.
1382
1383 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1384 (B): Sign extend 11 bit immediate.
1385 (EXT-B*): Shift 16 bit immediate left by 1.
1386 (ADDIU*): Don't sign extend immediate value.
1387
1388Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1389
1390 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1391
1392 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1393 functions.
1394
1395 * mips.igen (delayslot32, nullify_next_insn): New functions.
1396 (m16.igen): Always include.
1397 (do_*): Add more tracing.
1398
1399 * m16.igen (delayslot16): Add NIA argument, could be called by a
1400 32 bit MIPS16 instruction.
1401
1402 * interp.c (ifetch16): Move function from here.
1403 * sim-main.c (ifetch16): To here.
1404
1405 * sim-main.c (ifetch16, ifetch32): Update to match current
1406 implementations of LH, LW.
1407 (signal_exception): Don't print out incorrect hex value of illegal
1408 instruction.
1409
1410Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1411
1412 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1413 instruction.
1414
1415 * m16.igen: Implement MIPS16 instructions.
1416
1417 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1418 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1419 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1420 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1421 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1422 bodies of corresponding code from 32 bit insn to these. Also used
1423 by MIPS16 versions of functions.
1424
1425 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1426 (IMEM16): Drop NR argument from macro.
1427
1428Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1429
1430 * Makefile.in (SIM_OBJS): Add sim-main.o.
1431
1432 * sim-main.h (address_translation, load_memory, store_memory,
1433 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1434 as INLINE_SIM_MAIN.
1435 (pr_addr, pr_uword64): Declare.
1436 (sim-main.c): Include when H_REVEALS_MODULE_P.
1437
1438 * interp.c (address_translation, load_memory, store_memory,
1439 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1440 from here.
1441 * sim-main.c: To here. Fix compilation problems.
1442
1443 * configure.in: Enable inlining.
1444 * configure: Re-config.
1445
1446Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1447
1448 * configure: Regenerated to track ../common/aclocal.m4 changes.
1449
1450Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1451
1452 * mips.igen: Include tx.igen.
1453 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1454 * tx.igen: New file, contains MADD and MADDU.
1455
1456 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1457 the hardwired constant `7'.
1458 (store_memory): Ditto.
1459 (LOADDRMASK): Move definition to sim-main.h.
1460
1461 mips.igen (MTC0): Enable for r3900.
1462 (ADDU): Add trace.
1463
1464 mips.igen (do_load_byte): Delete.
1465 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1466 do_store_right): New functions.
1467 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1468
1469 configure.in: Let the tx39 use igen again.
1470 configure: Update.
1471
1472Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1473
1474 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1475 not an address sized quantity. Return zero for cache sizes.
1476
1477Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1478
1479 * mips.igen (r3900): r3900 does not support 64 bit integer
1480 operations.
1481
1482Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1483
1484 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1485 than igen one.
1486 * configure : Rebuild.
1487
1488Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1489
1490 * configure: Regenerated to track ../common/aclocal.m4 changes.
1491
1492Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1493
1494 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1495
1496Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1497
1498 * configure: Regenerated to track ../common/aclocal.m4 changes.
1499 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1500
1501Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1502
1503 * configure: Regenerated to track ../common/aclocal.m4 changes.
1504
1505Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1506
1507 * interp.c (Max, Min): Comment out functions. Not yet used.
1508
1509Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1510
1511 * configure: Regenerated to track ../common/aclocal.m4 changes.
1512
1513Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1514
1515 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1516 configurable settings for stand-alone simulator.
1517
1518 * configure.in: Added X11 search, just in case.
1519
1520 * configure: Regenerated.
1521
1522Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1523
1524 * interp.c (sim_write, sim_read, load_memory, store_memory):
1525 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1526
1527Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1528
1529 * sim-main.h (GETFCC): Return an unsigned value.
1530
1531Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1532
1533 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1534 (DADD): Result destination is RD not RT.
1535
1536Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1537
1538 * sim-main.h (HIACCESS, LOACCESS): Always define.
1539
1540 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1541
1542 * interp.c (sim_info): Delete.
1543
1544Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1545
1546 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1547 (mips_option_handler): New argument `cpu'.
1548 (sim_open): Update call to sim_add_option_table.
1549
1550Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1551
1552 * mips.igen (CxC1): Add tracing.
1553
1554Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1555
1556 * sim-main.h (Max, Min): Declare.
1557
1558 * interp.c (Max, Min): New functions.
1559
1560 * mips.igen (BC1): Add tracing.
1561
1562Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1563
1564 * interp.c Added memory map for stack in vr4100
1565
1566Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1567
1568 * interp.c (load_memory): Add missing "break"'s.
1569
1570Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1571
1572 * interp.c (sim_store_register, sim_fetch_register): Pass in
1573 length parameter. Return -1.
1574
1575Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1576
1577 * interp.c: Added hardware init hook, fixed warnings.
1578
1579Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1580
1581 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1582
1583Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1584
1585 * interp.c (ifetch16): New function.
1586
1587 * sim-main.h (IMEM32): Rename IMEM.
1588 (IMEM16_IMMED): Define.
1589 (IMEM16): Define.
1590 (DELAY_SLOT): Update.
1591
1592 * m16run.c (sim_engine_run): New file.
1593
1594 * m16.igen: All instructions except LB.
1595 (LB): Call do_load_byte.
1596 * mips.igen (do_load_byte): New function.
1597 (LB): Call do_load_byte.
1598
1599 * mips.igen: Move spec for insn bit size and high bit from here.
1600 * Makefile.in (tmp-igen, tmp-m16): To here.
1601
1602 * m16.dc: New file, decode mips16 instructions.
1603
1604 * Makefile.in (SIM_NO_ALL): Define.
1605 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1606
1607Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1608
1609 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1610 point unit to 32 bit registers.
1611 * configure: Re-generate.
1612
1613Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1614
1615 * configure.in (sim_use_gen): Make IGEN the default simulator
1616 generator for generic 32 and 64 bit mips targets.
1617 * configure: Re-generate.
1618
1619Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1620
1621 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1622 bitsize.
1623
1624 * interp.c (sim_fetch_register, sim_store_register): Read/write
1625 FGR from correct location.
1626 (sim_open): Set size of FGR's according to
1627 WITH_TARGET_FLOATING_POINT_BITSIZE.
1628
1629 * sim-main.h (FGR): Store floating point registers in a separate
1630 array.
1631
1632Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1633
1634 * configure: Regenerated to track ../common/aclocal.m4 changes.
1635
1636Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1637
1638 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1639
1640 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1641
1642 * interp.c (pending_tick): New function. Deliver pending writes.
1643
1644 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1645 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1646 it can handle mixed sized quantites and single bits.
1647
1648Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1649
1650 * interp.c (oengine.h): Do not include when building with IGEN.
1651 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1652 (sim_info): Ditto for PROCESSOR_64BIT.
1653 (sim_monitor): Replace ut_reg with unsigned_word.
1654 (*): Ditto for t_reg.
1655 (LOADDRMASK): Define.
1656 (sim_open): Remove defunct check that host FP is IEEE compliant,
1657 using software to emulate floating point.
1658 (value_fpr, ...): Always compile, was conditional on HASFPU.
1659
1660Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1661
1662 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1663 size.
1664
1665 * interp.c (SD, CPU): Define.
1666 (mips_option_handler): Set flags in each CPU.
1667 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1668 (sim_close): Do not clear STATE, deleted anyway.
1669 (sim_write, sim_read): Assume CPU zero's vm should be used for
1670 data transfers.
1671 (sim_create_inferior): Set the PC for all processors.
1672 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1673 argument.
1674 (mips16_entry): Pass correct nr of args to store_word, load_word.
1675 (ColdReset): Cold reset all cpu's.
1676 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1677 (sim_monitor, load_memory, store_memory, signal_exception): Use
1678 `CPU' instead of STATE_CPU.
1679
1680
1681 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1682 SD or CPU_.
1683
1684 * sim-main.h (signal_exception): Add sim_cpu arg.
1685 (SignalException*): Pass both SD and CPU to signal_exception.
1686 * interp.c (signal_exception): Update.
1687
1688 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1689 Ditto
1690 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1691 address_translation): Ditto
1692 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1693
1694Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1695
1696 * configure: Regenerated to track ../common/aclocal.m4 changes.
1697
1698Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1699
1700 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1701
1702 * mips.igen (model): Map processor names onto BFD name.
1703
1704 * sim-main.h (CPU_CIA): Delete.
1705 (SET_CIA, GET_CIA): Define
1706
1707Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1708
1709 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1710 regiser.
1711
1712 * configure.in (default_endian): Configure a big-endian simulator
1713 by default.
1714 * configure: Re-generate.
1715
1716Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1717
1718 * configure: Regenerated to track ../common/aclocal.m4 changes.
1719
1720Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1721
1722 * interp.c (sim_monitor): Handle Densan monitor outbyte
1723 and inbyte functions.
1724
17251997-12-29 Felix Lee <flee@cygnus.com>
1726
1727 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1728
1729Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1730
1731 * Makefile.in (tmp-igen): Arrange for $zero to always be
1732 reset to zero after every instruction.
1733
1734Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1735
1736 * configure: Regenerated to track ../common/aclocal.m4 changes.
1737 * config.in: Ditto.
1738
1739Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1740
1741 * mips.igen (MSUB): Fix to work like MADD.
1742 * gencode.c (MSUB): Similarly.
1743
1744Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1745
1746 * configure: Regenerated to track ../common/aclocal.m4 changes.
1747
1748Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1749
1750 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1751
1752Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1753
1754 * sim-main.h (sim-fpu.h): Include.
1755
1756 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1757 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1758 using host independant sim_fpu module.
1759
1760Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1761
1762 * interp.c (signal_exception): Report internal errors with SIGABRT
1763 not SIGQUIT.
1764
1765 * sim-main.h (C0_CONFIG): New register.
1766 (signal.h): No longer include.
1767
1768 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1769
1770Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1771
1772 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1773
1774Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1775
1776 * mips.igen: Tag vr5000 instructions.
1777 (ANDI): Was missing mipsIV model, fix assembler syntax.
1778 (do_c_cond_fmt): New function.
1779 (C.cond.fmt): Handle mips I-III which do not support CC field
1780 separatly.
1781 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1782 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1783 in IV3.2 spec.
1784 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1785 vr5000 which saves LO in a GPR separatly.
1786
1787 * configure.in (enable-sim-igen): For vr5000, select vr5000
1788 specific instructions.
1789 * configure: Re-generate.
1790
1791Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1792
1793 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1794
1795 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1796 fmt_uninterpreted_64 bit cases to switch. Convert to
1797 fmt_formatted,
1798
1799 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1800
1801 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1802 as specified in IV3.2 spec.
1803 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1804
1805Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1806
1807 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1808 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1809 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1810 PENDING_FILL versions of instructions. Simplify.
1811 (X): New function.
1812 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1813 instructions.
1814 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1815 a signed value.
1816 (MTHI, MFHI): Disable code checking HI-LO.
1817
1818 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1819 global.
1820 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1821
1822Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1823
1824 * gencode.c (build_mips16_operands): Replace IPC with cia.
1825
1826 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1827 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1828 IPC to `cia'.
1829 (UndefinedResult): Replace function with macro/function
1830 combination.
1831 (sim_engine_run): Don't save PC in IPC.
1832
1833 * sim-main.h (IPC): Delete.
1834
1835
1836 * interp.c (signal_exception, store_word, load_word,
1837 address_translation, load_memory, store_memory, cache_op,
1838 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1839 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1840 current instruction address - cia - argument.
1841 (sim_read, sim_write): Call address_translation directly.
1842 (sim_engine_run): Rename variable vaddr to cia.
1843 (signal_exception): Pass cia to sim_monitor
1844
1845 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1846 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1847 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1848
1849 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1850 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1851 SIM_ASSERT.
1852
1853 * interp.c (signal_exception): Pass restart address to
1854 sim_engine_restart.
1855
1856 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1857 idecode.o): Add dependency.
1858
1859 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1860 Delete definitions
1861 (DELAY_SLOT): Update NIA not PC with branch address.
1862 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1863
1864 * mips.igen: Use CIA not PC in branch calculations.
1865 (illegal): Call SignalException.
1866 (BEQ, ADDIU): Fix assembler.
1867
1868Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1869
1870 * m16.igen (JALX): Was missing.
1871
1872 * configure.in (enable-sim-igen): New configuration option.
1873 * configure: Re-generate.
1874
1875 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1876
1877 * interp.c (load_memory, store_memory): Delete parameter RAW.
1878 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1879 bypassing {load,store}_memory.
1880
1881 * sim-main.h (ByteSwapMem): Delete definition.
1882
1883 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1884
1885 * interp.c (sim_do_command, sim_commands): Delete mips specific
1886 commands. Handled by module sim-options.
1887
1888 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1889 (WITH_MODULO_MEMORY): Define.
1890
1891 * interp.c (sim_info): Delete code printing memory size.
1892
1893 * interp.c (mips_size): Nee sim_size, delete function.
1894 (power2): Delete.
1895 (monitor, monitor_base, monitor_size): Delete global variables.
1896 (sim_open, sim_close): Delete code creating monitor and other
1897 memory regions. Use sim-memopts module, via sim_do_commandf, to
1898 manage memory regions.
1899 (load_memory, store_memory): Use sim-core for memory model.
1900
1901 * interp.c (address_translation): Delete all memory map code
1902 except line forcing 32 bit addresses.
1903
1904Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1905
1906 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1907 trace options.
1908
1909 * interp.c (logfh, logfile): Delete globals.
1910 (sim_open, sim_close): Delete code opening & closing log file.
1911 (mips_option_handler): Delete -l and -n options.
1912 (OPTION mips_options): Ditto.
1913
1914 * interp.c (OPTION mips_options): Rename option trace to dinero.
1915 (mips_option_handler): Update.
1916
1917Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1918
1919 * interp.c (fetch_str): New function.
1920 (sim_monitor): Rewrite using sim_read & sim_write.
1921 (sim_open): Check magic number.
1922 (sim_open): Write monitor vectors into memory using sim_write.
1923 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1924 (sim_read, sim_write): Simplify - transfer data one byte at a
1925 time.
1926 (load_memory, store_memory): Clarify meaning of parameter RAW.
1927
1928 * sim-main.h (isHOST): Defete definition.
1929 (isTARGET): Mark as depreciated.
1930 (address_translation): Delete parameter HOST.
1931
1932 * interp.c (address_translation): Delete parameter HOST.
1933
1934Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1935
1936 * mips.igen:
1937
1938 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1939 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1940
1941Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1942
1943 * mips.igen: Add model filter field to records.
1944
1945Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1946
1947 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1948
1949 interp.c (sim_engine_run): Do not compile function sim_engine_run
1950 when WITH_IGEN == 1.
1951
1952 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1953 target architecture.
1954
1955 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1956 igen. Replace with configuration variables sim_igen_flags /
1957 sim_m16_flags.
1958
1959 * m16.igen: New file. Copy mips16 insns here.
1960 * mips.igen: From here.
1961
1962Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1963
1964 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1965 to top.
1966 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1967
1968Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1969
1970 * gencode.c (build_instruction): Follow sim_write's lead in using
1971 BigEndianMem instead of !ByteSwapMem.
1972
1973Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1974
1975 * configure.in (sim_gen): Dependent on target, select type of
1976 generator. Always select old style generator.
1977
1978 configure: Re-generate.
1979
1980 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1981 targets.
1982 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1983 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1984 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1985 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1986 SIM_@sim_gen@_*, set by autoconf.
1987
1988Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1989
1990 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1991
1992 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1993 CURRENT_FLOATING_POINT instead.
1994
1995 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1996 (address_translation): Raise exception InstructionFetch when
1997 translation fails and isINSTRUCTION.
1998
1999 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2000 sim_engine_run): Change type of of vaddr and paddr to
2001 address_word.
2002 (address_translation, prefetch, load_memory, store_memory,
2003 cache_op): Change type of vAddr and pAddr to address_word.
2004
2005 * gencode.c (build_instruction): Change type of vaddr and paddr to
2006 address_word.
2007
2008Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2009
2010 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2011 macro to obtain result of ALU op.
2012
2013Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2014
2015 * interp.c (sim_info): Call profile_print.
2016
2017Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2018
2019 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2020
2021 * sim-main.h (WITH_PROFILE): Do not define, defined in
2022 common/sim-config.h. Use sim-profile module.
2023 (simPROFILE): Delete defintion.
2024
2025 * interp.c (PROFILE): Delete definition.
2026 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2027 (sim_close): Delete code writing profile histogram.
2028 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2029 Delete.
2030 (sim_engine_run): Delete code profiling the PC.
2031
2032Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2033
2034 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2035
2036 * interp.c (sim_monitor): Make register pointers of type
2037 unsigned_word*.
2038
2039 * sim-main.h: Make registers of type unsigned_word not
2040 signed_word.
2041
2042Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2043
2044 * interp.c (sync_operation): Rename from SyncOperation, make
2045 global, add SD argument.
2046 (prefetch): Rename from Prefetch, make global, add SD argument.
2047 (decode_coproc): Make global.
2048
2049 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2050
2051 * gencode.c (build_instruction): Generate DecodeCoproc not
2052 decode_coproc calls.
2053
2054 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2055 (SizeFGR): Move to sim-main.h
2056 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2057 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2058 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2059 sim-main.h.
2060 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2061 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2062 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2063 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2064 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2065 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2066
2067 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2068 exception.
2069 (sim-alu.h): Include.
2070 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2071 (sim_cia): Typedef to instruction_address.
2072
2073Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2074
2075 * Makefile.in (interp.o): Rename generated file engine.c to
2076 oengine.c.
2077
2078 * interp.c: Update.
2079
2080Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2081
2082 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2083
2084Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2085
2086 * gencode.c (build_instruction): For "FPSQRT", output correct
2087 number of arguments to Recip.
2088
2089Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2090
2091 * Makefile.in (interp.o): Depends on sim-main.h
2092
2093 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2094
2095 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2096 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2097 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2098 STATE, DSSTATE): Define
2099 (GPR, FGRIDX, ..): Define.
2100
2101 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2102 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2103 (GPR, FGRIDX, ...): Delete macros.
2104
2105 * interp.c: Update names to match defines from sim-main.h
2106
2107Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2108
2109 * interp.c (sim_monitor): Add SD argument.
2110 (sim_warning): Delete. Replace calls with calls to
2111 sim_io_eprintf.
2112 (sim_error): Delete. Replace calls with sim_io_error.
2113 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2114 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2115 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2116 argument.
2117 (mips_size): Rename from sim_size. Add SD argument.
2118
2119 * interp.c (simulator): Delete global variable.
2120 (callback): Delete global variable.
2121 (mips_option_handler, sim_open, sim_write, sim_read,
2122 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2123 sim_size,sim_monitor): Use sim_io_* not callback->*.
2124 (sim_open): ZALLOC simulator struct.
2125 (PROFILE): Do not define.
2126
2127Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2128
2129 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2130 support.h with corresponding code.
2131
2132 * sim-main.h (word64, uword64), support.h: Move definition to
2133 sim-main.h.
2134 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2135
2136 * support.h: Delete
2137 * Makefile.in: Update dependencies
2138 * interp.c: Do not include.
2139
2140Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2141
2142 * interp.c (address_translation, load_memory, store_memory,
2143 cache_op): Rename to from AddressTranslation et.al., make global,
2144 add SD argument
2145
2146 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2147 CacheOp): Define.
2148
2149 * interp.c (SignalException): Rename to signal_exception, make
2150 global.
2151
2152 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2153
2154 * sim-main.h (SignalException, SignalExceptionInterrupt,
2155 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2156 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2157 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2158 Define.
2159
2160 * interp.c, support.h: Use.
2161
2162Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2163
2164 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2165 to value_fpr / store_fpr. Add SD argument.
2166 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2167 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2168
2169 * sim-main.h (ValueFPR, StoreFPR): Define.
2170
2171Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2172
2173 * interp.c (sim_engine_run): Check consistency between configure
2174 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2175 and HASFPU.
2176
2177 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2178 (mips_fpu): Configure WITH_FLOATING_POINT.
2179 (mips_endian): Configure WITH_TARGET_ENDIAN.
2180 * configure: Update.
2181
2182Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2183
2184 * configure: Regenerated to track ../common/aclocal.m4 changes.
2185
2186Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2187
2188 * configure: Regenerated.
2189
2190Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2191
2192 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2193
2194Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2195
2196 * gencode.c (print_igen_insn_models): Assume certain architectures
2197 include all mips* instructions.
2198 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2199 instruction.
2200
2201 * Makefile.in (tmp.igen): Add target. Generate igen input from
2202 gencode file.
2203
2204 * gencode.c (FEATURE_IGEN): Define.
2205 (main): Add --igen option. Generate output in igen format.
2206 (process_instructions): Format output according to igen option.
2207 (print_igen_insn_format): New function.
2208 (print_igen_insn_models): New function.
2209 (process_instructions): Only issue warnings and ignore
2210 instructions when no FEATURE_IGEN.
2211
2212Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2213
2214 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2215 MIPS targets.
2216
2217Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2218
2219 * configure: Regenerated to track ../common/aclocal.m4 changes.
2220
2221Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2222
2223 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2224 SIM_RESERVED_BITS): Delete, moved to common.
2225 (SIM_EXTRA_CFLAGS): Update.
2226
2227Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2228
2229 * configure.in: Configure non-strict memory alignment.
2230 * configure: Regenerated to track ../common/aclocal.m4 changes.
2231
2232Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2233
2234 * configure: Regenerated to track ../common/aclocal.m4 changes.
2235
2236Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2237
2238 * gencode.c (SDBBP,DERET): Added (3900) insns.
2239 (RFE): Turn on for 3900.
2240 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2241 (dsstate): Made global.
2242 (SUBTARGET_R3900): Added.
2243 (CANCELDELAYSLOT): New.
2244 (SignalException): Ignore SystemCall rather than ignore and
2245 terminate. Add DebugBreakPoint handling.
2246 (decode_coproc): New insns RFE, DERET; and new registers Debug
2247 and DEPC protected by SUBTARGET_R3900.
2248 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2249 bits explicitly.
2250 * Makefile.in,configure.in: Add mips subtarget option.
2251 * configure: Update.
2252
2253Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2254
2255 * gencode.c: Add r3900 (tx39).
2256
2257
2258Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2259
2260 * gencode.c (build_instruction): Don't need to subtract 4 for
2261 JALR, just 2.
2262
2263Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2264
2265 * interp.c: Correct some HASFPU problems.
2266
2267Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2268
2269 * configure: Regenerated to track ../common/aclocal.m4 changes.
2270
2271Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2272
2273 * interp.c (mips_options): Fix samples option short form, should
2274 be `x'.
2275
2276Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2277
2278 * interp.c (sim_info): Enable info code. Was just returning.
2279
2280Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2281
2282 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2283 MFC0.
2284
2285Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2286
2287 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2288 constants.
2289 (build_instruction): Ditto for LL.
2290
2291Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2292
2293 * configure: Regenerated to track ../common/aclocal.m4 changes.
2294
2295Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2296
2297 * configure: Regenerated to track ../common/aclocal.m4 changes.
2298 * config.in: Ditto.
2299
2300Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2301
2302 * interp.c (sim_open): Add call to sim_analyze_program, update
2303 call to sim_config.
2304
2305Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2306
2307 * interp.c (sim_kill): Delete.
2308 (sim_create_inferior): Add ABFD argument. Set PC from same.
2309 (sim_load): Move code initializing trap handlers from here.
2310 (sim_open): To here.
2311 (sim_load): Delete, use sim-hload.c.
2312
2313 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2314
2315Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2316
2317 * configure: Regenerated to track ../common/aclocal.m4 changes.
2318 * config.in: Ditto.
2319
2320Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2321
2322 * interp.c (sim_open): Add ABFD argument.
2323 (sim_load): Move call to sim_config from here.
2324 (sim_open): To here. Check return status.
2325
2326Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2327
2328 * gencode.c (build_instruction): Two arg MADD should
2329 not assign result to $0.
2330
2331Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2332
2333 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2334 * sim/mips/configure.in: Regenerate.
2335
2336Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2337
2338 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2339 signed8, unsigned8 et.al. types.
2340
2341 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2342 hosts when selecting subreg.
2343
2344Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2345
2346 * interp.c (sim_engine_run): Reset the ZERO register to zero
2347 regardless of FEATURE_WARN_ZERO.
2348 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2349
2350Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2351
2352 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2353 (SignalException): For BreakPoints ignore any mode bits and just
2354 save the PC.
2355 (SignalException): Always set the CAUSE register.
2356
2357Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2358
2359 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2360 exception has been taken.
2361
2362 * interp.c: Implement the ERET and mt/f sr instructions.
2363
2364Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2365
2366 * interp.c (SignalException): Don't bother restarting an
2367 interrupt.
2368
2369Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2370
2371 * interp.c (SignalException): Really take an interrupt.
2372 (interrupt_event): Only deliver interrupts when enabled.
2373
2374Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2375
2376 * interp.c (sim_info): Only print info when verbose.
2377 (sim_info) Use sim_io_printf for output.
2378
2379Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2380
2381 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2382 mips architectures.
2383
2384Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2385
2386 * interp.c (sim_do_command): Check for common commands if a
2387 simulator specific command fails.
2388
2389Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2390
2391 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2392 and simBE when DEBUG is defined.
2393
2394Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2395
2396 * interp.c (interrupt_event): New function. Pass exception event
2397 onto exception handler.
2398
2399 * configure.in: Check for stdlib.h.
2400 * configure: Regenerate.
2401
2402 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2403 variable declaration.
2404 (build_instruction): Initialize memval1.
2405 (build_instruction): Add UNUSED attribute to byte, bigend,
2406 reverse.
2407 (build_operands): Ditto.
2408
2409 * interp.c: Fix GCC warnings.
2410 (sim_get_quit_code): Delete.
2411
2412 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2413 * Makefile.in: Ditto.
2414 * configure: Re-generate.
2415
2416 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2417
2418Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2419
2420 * interp.c (mips_option_handler): New function parse argumes using
2421 sim-options.
2422 (myname): Replace with STATE_MY_NAME.
2423 (sim_open): Delete check for host endianness - performed by
2424 sim_config.
2425 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2426 (sim_open): Move much of the initialization from here.
2427 (sim_load): To here. After the image has been loaded and
2428 endianness set.
2429 (sim_open): Move ColdReset from here.
2430 (sim_create_inferior): To here.
2431 (sim_open): Make FP check less dependant on host endianness.
2432
2433 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2434 run.
2435 * interp.c (sim_set_callbacks): Delete.
2436
2437 * interp.c (membank, membank_base, membank_size): Replace with
2438 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2439 (sim_open): Remove call to callback->init. gdb/run do this.
2440
2441 * interp.c: Update
2442
2443 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2444
2445 * interp.c (big_endian_p): Delete, replaced by
2446 current_target_byte_order.
2447
2448Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2449
2450 * interp.c (host_read_long, host_read_word, host_swap_word,
2451 host_swap_long): Delete. Using common sim-endian.
2452 (sim_fetch_register, sim_store_register): Use H2T.
2453 (pipeline_ticks): Delete. Handled by sim-events.
2454 (sim_info): Update.
2455 (sim_engine_run): Update.
2456
2457Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2458
2459 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2460 reason from here.
2461 (SignalException): To here. Signal using sim_engine_halt.
2462 (sim_stop_reason): Delete, moved to common.
2463
2464Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2465
2466 * interp.c (sim_open): Add callback argument.
2467 (sim_set_callbacks): Delete SIM_DESC argument.
2468 (sim_size): Ditto.
2469
2470Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2471
2472 * Makefile.in (SIM_OBJS): Add common modules.
2473
2474 * interp.c (sim_set_callbacks): Also set SD callback.
2475 (set_endianness, xfer_*, swap_*): Delete.
2476 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2477 Change to functions using sim-endian macros.
2478 (control_c, sim_stop): Delete, use common version.
2479 (simulate): Convert into.
2480 (sim_engine_run): This function.
2481 (sim_resume): Delete.
2482
2483 * interp.c (simulation): New variable - the simulator object.
2484 (sim_kind): Delete global - merged into simulation.
2485 (sim_load): Cleanup. Move PC assignment from here.
2486 (sim_create_inferior): To here.
2487
2488 * sim-main.h: New file.
2489 * interp.c (sim-main.h): Include.
2490
2491Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2492
2493 * configure: Regenerated to track ../common/aclocal.m4 changes.
2494
2495Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2496
2497 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2498
2499Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2500
2501 * gencode.c (build_instruction): DIV instructions: check
2502 for division by zero and integer overflow before using
2503 host's division operation.
2504
2505Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2506
2507 * Makefile.in (SIM_OBJS): Add sim-load.o.
2508 * interp.c: #include bfd.h.
2509 (target_byte_order): Delete.
2510 (sim_kind, myname, big_endian_p): New static locals.
2511 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2512 after argument parsing. Recognize -E arg, set endianness accordingly.
2513 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2514 load file into simulator. Set PC from bfd.
2515 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2516 (set_endianness): Use big_endian_p instead of target_byte_order.
2517
2518Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2519
2520 * interp.c (sim_size): Delete prototype - conflicts with
2521 definition in remote-sim.h. Correct definition.
2522
2523Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2524
2525 * configure: Regenerated to track ../common/aclocal.m4 changes.
2526 * config.in: Ditto.
2527
2528Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2529
2530 * interp.c (sim_open): New arg `kind'.
2531
2532 * configure: Regenerated to track ../common/aclocal.m4 changes.
2533
2534Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2535
2536 * configure: Regenerated to track ../common/aclocal.m4 changes.
2537
2538Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2539
2540 * interp.c (sim_open): Set optind to 0 before calling getopt.
2541
2542Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2543
2544 * configure: Regenerated to track ../common/aclocal.m4 changes.
2545
2546Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2547
2548 * interp.c : Replace uses of pr_addr with pr_uword64
2549 where the bit length is always 64 independent of SIM_ADDR.
2550 (pr_uword64) : added.
2551
2552Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2553
2554 * configure: Re-generate.
2555
2556Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2557
2558 * configure: Regenerate to track ../common/aclocal.m4 changes.
2559
2560Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2561
2562 * interp.c (sim_open): New SIM_DESC result. Argument is now
2563 in argv form.
2564 (other sim_*): New SIM_DESC argument.
2565
2566Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2567
2568 * interp.c: Fix printing of addresses for non-64-bit targets.
2569 (pr_addr): Add function to print address based on size.
2570
2571Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2572
2573 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2574
2575Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2576
2577 * gencode.c (build_mips16_operands): Correct computation of base
2578 address for extended PC relative instruction.
2579
2580Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2581
2582 * interp.c (mips16_entry): Add support for floating point cases.
2583 (SignalException): Pass floating point cases to mips16_entry.
2584 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2585 registers.
2586 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2587 or fmt_word.
2588 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2589 and then set the state to fmt_uninterpreted.
2590 (COP_SW): Temporarily set the state to fmt_word while calling
2591 ValueFPR.
2592
2593Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2594
2595 * gencode.c (build_instruction): The high order may be set in the
2596 comparison flags at any ISA level, not just ISA 4.
2597
2598Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2599
2600 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2601 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2602 * configure.in: sinclude ../common/aclocal.m4.
2603 * configure: Regenerated.
2604
2605Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2606
2607 * configure: Rebuild after change to aclocal.m4.
2608
2609Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2610
2611 * configure configure.in Makefile.in: Update to new configure
2612 scheme which is more compatible with WinGDB builds.
2613 * configure.in: Improve comment on how to run autoconf.
2614 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2615 * Makefile.in: Use autoconf substitution to install common
2616 makefile fragment.
2617
2618Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2619
2620 * gencode.c (build_instruction): Use BigEndianCPU instead of
2621 ByteSwapMem.
2622
2623Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2624
2625 * interp.c (sim_monitor): Make output to stdout visible in
2626 wingdb's I/O log window.
2627
2628Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2629
2630 * support.h: Undo previous change to SIGTRAP
2631 and SIGQUIT values.
2632
2633Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2634
2635 * interp.c (store_word, load_word): New static functions.
2636 (mips16_entry): New static function.
2637 (SignalException): Look for mips16 entry and exit instructions.
2638 (simulate): Use the correct index when setting fpr_state after
2639 doing a pending move.
2640
2641Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2642
2643 * interp.c: Fix byte-swapping code throughout to work on
2644 both little- and big-endian hosts.
2645
2646Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2647
2648 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2649 with gdb/config/i386/xm-windows.h.
2650
2651Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2652
2653 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2654 that messes up arithmetic shifts.
2655
2656Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2657
2658 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2659 SIGTRAP and SIGQUIT for _WIN32.
2660
2661Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2662
2663 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2664 force a 64 bit multiplication.
2665 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2666 destination register is 0, since that is the default mips16 nop
2667 instruction.
2668
2669Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2670
2671 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2672 (build_endian_shift): Don't check proc64.
2673 (build_instruction): Always set memval to uword64. Cast op2 to
2674 uword64 when shifting it left in memory instructions. Always use
2675 the same code for stores--don't special case proc64.
2676
2677 * gencode.c (build_mips16_operands): Fix base PC value for PC
2678 relative operands.
2679 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2680 jal instruction.
2681 * interp.c (simJALDELAYSLOT): Define.
2682 (JALDELAYSLOT): Define.
2683 (INDELAYSLOT, INJALDELAYSLOT): Define.
2684 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2685
2686Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2687
2688 * interp.c (sim_open): add flush_cache as a PMON routine
2689 (sim_monitor): handle flush_cache by ignoring it
2690
2691Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2692
2693 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2694 BigEndianMem.
2695 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2696 (BigEndianMem): Rename to ByteSwapMem and change sense.
2697 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2698 BigEndianMem references to !ByteSwapMem.
2699 (set_endianness): New function, with prototype.
2700 (sim_open): Call set_endianness.
2701 (sim_info): Use simBE instead of BigEndianMem.
2702 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2703 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2704 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2705 ifdefs, keeping the prototype declaration.
2706 (swap_word): Rewrite correctly.
2707 (ColdReset): Delete references to CONFIG. Delete endianness related
2708 code; moved to set_endianness.
2709
2710Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2711
2712 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2713 * interp.c (CHECKHILO): Define away.
2714 (simSIGINT): New macro.
2715 (membank_size): Increase from 1MB to 2MB.
2716 (control_c): New function.
2717 (sim_resume): Rename parameter signal to signal_number. Add local
2718 variable prev. Call signal before and after simulate.
2719 (sim_stop_reason): Add simSIGINT support.
2720 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2721 functions always.
2722 (sim_warning): Delete call to SignalException. Do call printf_filtered
2723 if logfh is NULL.
2724 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2725 a call to sim_warning.
2726
2727Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2728
2729 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2730 16 bit instructions.
2731
2732Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2733
2734 Add support for mips16 (16 bit MIPS implementation):
2735 * gencode.c (inst_type): Add mips16 instruction encoding types.
2736 (GETDATASIZEINSN): Define.
2737 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2738 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2739 mtlo.
2740 (MIPS16_DECODE): New table, for mips16 instructions.
2741 (bitmap_val): New static function.
2742 (struct mips16_op): Define.
2743 (mips16_op_table): New table, for mips16 operands.
2744 (build_mips16_operands): New static function.
2745 (process_instructions): If PC is odd, decode a mips16
2746 instruction. Break out instruction handling into new
2747 build_instruction function.
2748 (build_instruction): New static function, broken out of
2749 process_instructions. Check modifiers rather than flags for SHIFT
2750 bit count and m[ft]{hi,lo} direction.
2751 (usage): Pass program name to fprintf.
2752 (main): Remove unused variable this_option_optind. Change
2753 ``*loptarg++'' to ``loptarg++''.
2754 (my_strtoul): Parenthesize && within ||.
2755 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2756 (simulate): If PC is odd, fetch a 16 bit instruction, and
2757 increment PC by 2 rather than 4.
2758 * configure.in: Add case for mips16*-*-*.
2759 * configure: Rebuild.
2760
2761Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2762
2763 * interp.c: Allow -t to enable tracing in standalone simulator.
2764 Fix garbage output in trace file and error messages.
2765
2766Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2767
2768 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2769 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2770 * configure.in: Simplify using macros in ../common/aclocal.m4.
2771 * configure: Regenerated.
2772 * tconfig.in: New file.
2773
2774Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2775
2776 * interp.c: Fix bugs in 64-bit port.
2777 Use ansi function declarations for msvc compiler.
2778 Initialize and test file pointer in trace code.
2779 Prevent duplicate definition of LAST_EMED_REGNUM.
2780
2781Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2782
2783 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2784
2785Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2786
2787 * interp.c (SignalException): Check for explicit terminating
2788 breakpoint value.
2789 * gencode.c: Pass instruction value through SignalException()
2790 calls for Trap, Breakpoint and Syscall.
2791
2792Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2793
2794 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2795 only used on those hosts that provide it.
2796 * configure.in: Add sqrt() to list of functions to be checked for.
2797 * config.in: Re-generated.
2798 * configure: Re-generated.
2799
2800Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2801
2802 * gencode.c (process_instructions): Call build_endian_shift when
2803 expanding STORE RIGHT, to fix swr.
2804 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2805 clear the high bits.
2806 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2807 Fix float to int conversions to produce signed values.
2808
2809Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2810
2811 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2812 (process_instructions): Correct handling of nor instruction.
2813 Correct shift count for 32 bit shift instructions. Correct sign
2814 extension for arithmetic shifts to not shift the number of bits in
2815 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2816 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2817 Fix madd.
2818 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2819 It's OK to have a mult follow a mult. What's not OK is to have a
2820 mult follow an mfhi.
2821 (Convert): Comment out incorrect rounding code.
2822
2823Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2824
2825 * interp.c (sim_monitor): Improved monitor printf
2826 simulation. Tidied up simulator warnings, and added "--log" option
2827 for directing warning message output.
2828 * gencode.c: Use sim_warning() rather than WARNING macro.
2829
2830Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2831
2832 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2833 getopt1.o, rather than on gencode.c. Link objects together.
2834 Don't link against -liberty.
2835 (gencode.o, getopt.o, getopt1.o): New targets.
2836 * gencode.c: Include <ctype.h> and "ansidecl.h".
2837 (AND): Undefine after including "ansidecl.h".
2838 (ULONG_MAX): Define if not defined.
2839 (OP_*): Don't define macros; now defined in opcode/mips.h.
2840 (main): Call my_strtoul rather than strtoul.
2841 (my_strtoul): New static function.
2842
2843Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2844
2845 * gencode.c (process_instructions): Generate word64 and uword64
2846 instead of `long long' and `unsigned long long' data types.
2847 * interp.c: #include sysdep.h to get signals, and define default
2848 for SIGBUS.
2849 * (Convert): Work around for Visual-C++ compiler bug with type
2850 conversion.
2851 * support.h: Make things compile under Visual-C++ by using
2852 __int64 instead of `long long'. Change many refs to long long
2853 into word64/uword64 typedefs.
2854
2855Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2856
2857 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2858 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2859 (docdir): Removed.
2860 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2861 (AC_PROG_INSTALL): Added.
2862 (AC_PROG_CC): Moved to before configure.host call.
2863 * configure: Rebuilt.
2864
2865Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2866
2867 * configure.in: Define @SIMCONF@ depending on mips target.
2868 * configure: Rebuild.
2869 * Makefile.in (run): Add @SIMCONF@ to control simulator
2870 construction.
2871 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2872 * interp.c: Remove some debugging, provide more detailed error
2873 messages, update memory accesses to use LOADDRMASK.
2874
2875Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2876
2877 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2878 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2879 stamp-h.
2880 * configure: Rebuild.
2881 * config.in: New file, generated by autoheader.
2882 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2883 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2884 HAVE_ANINT and HAVE_AINT, as appropriate.
2885 * Makefile.in (run): Use @LIBS@ rather than -lm.
2886 (interp.o): Depend upon config.h.
2887 (Makefile): Just rebuild Makefile.
2888 (clean): Remove stamp-h.
2889 (mostlyclean): Make the same as clean, not as distclean.
2890 (config.h, stamp-h): New targets.
2891
2892Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2893
2894 * interp.c (ColdReset): Fix boolean test. Make all simulator
2895 globals static.
2896
2897Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2898
2899 * interp.c (xfer_direct_word, xfer_direct_long,
2900 swap_direct_word, swap_direct_long, xfer_big_word,
2901 xfer_big_long, xfer_little_word, xfer_little_long,
2902 swap_word,swap_long): Added.
2903 * interp.c (ColdReset): Provide function indirection to
2904 host<->simulated_target transfer routines.
2905 * interp.c (sim_store_register, sim_fetch_register): Updated to
2906 make use of indirected transfer routines.
2907
2908Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2909
2910 * gencode.c (process_instructions): Ensure FP ABS instruction
2911 recognised.
2912 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2913 system call support.
2914
2915Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2916
2917 * interp.c (sim_do_command): Complain if callback structure not
2918 initialised.
2919
2920Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2921
2922 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2923 support for Sun hosts.
2924 * Makefile.in (gencode): Ensure the host compiler and libraries
2925 used for cross-hosted build.
2926
2927Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2928
2929 * interp.c, gencode.c: Some more (TODO) tidying.
2930
2931Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2932
2933 * gencode.c, interp.c: Replaced explicit long long references with
2934 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2935 * support.h (SET64LO, SET64HI): Macros added.
2936
2937Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2938
2939 * configure: Regenerate with autoconf 2.7.
2940
2941Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2942
2943 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2944 * support.h: Remove superfluous "1" from #if.
2945 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2946
2947Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2948
2949 * interp.c (StoreFPR): Control UndefinedResult() call on
2950 WARN_RESULT manifest.
2951
2952Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2953
2954 * gencode.c: Tidied instruction decoding, and added FP instruction
2955 support.
2956
2957 * interp.c: Added dineroIII, and BSD profiling support. Also
2958 run-time FP handling.
2959
2960Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2961
2962 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2963 gencode.c, interp.c, support.h: created.
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