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x86: Count PLT for GOTOFF relocation against IFUNC symbol
[deliverable/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
b5689863
MF		 12021-06-19 Mike Frysinger <vapier@gentoo.org>
2
3 * aclocal.m4: Regenerate.
4 * configure: Regenerate.
5
17a5da80
MF		 62021-06-19 Mike Frysinger <vapier@gentoo.org>
7
8 * configure.ac: Delete AC_PATH_X call.
9 * configure: Regenerate.
10
07490bf8
MF		 112021-06-19 Mike Frysinger <vapier@gentoo.org>
12
13 * configure.ac: Delete AC_CHECK_LIB calls.
14 * configure: Regenerate.
15
47ce766a
MF		 162021-06-18 Mike Frysinger <vapier@gentoo.org>
17
18 * aclocal.m4, configure: Regenerate.
19
982c3a65
MF		 202021-06-18 Mike Frysinger <vapier@gentoo.org>
21
22 * Makefile.in (SIM_WERROR_CFLAGS): New variable.
23 * configure.ac: Delete call to SIM_AC_OPTION_WARNINGS.
24 * configure: Regenerate.
25
1fef66b0
MF		 262021-06-18 Mike Frysinger <vapier@gentoo.org>
27
28 * interp.c: Include sim-signal.h.
29
f9a4d543
MF		 302021-06-17 Mike Frysinger <vapier@gentoo.org>
31
32 * configure.ac: Delete SIM_AC_OPTION_ENDIAN call.
33 * aclocal.m4, configure: Regenerate.
34
b80d4475
MF		 352021-06-16 Mike Frysinger <vapier@gentoo.org>
36
37 * interp.c (dotrace): Make comment const.
38 * sim-main.h (dotrace): Likewise. Add ATTRIBUTE_PRINTF.
39
6828a302
MF		 402021-06-16 Mike Frysinger <vapier@gentoo.org>
41
42 * interp.c (sim_monitor): Change ap type to address_word*.
43 (_P, P): New macros. Rewrite dynamic printf logic to use these.
44
df32b446
MF		 452021-06-16 Mike Frysinger <vapier@gentoo.org>
46
47 * dv-tx3904sio.c (tx3904sio_fifo_push): Change next_buf to
48 unsigned_1.
49
7b2298cb
MF		 502021-06-16 Mike Frysinger <vapier@gentoo.org>
51
52 * dv-tx3904irc.c (tx3904irc_io_write_buffer): Initialize
53 register_value to 0.
54
a8a3d907
MF		 552021-06-16 Mike Frysinger <vapier@gentoo.org>
56
57 * configure: Regenerate.
58
dae666c9
MF		 592021-06-16 Mike Frysinger <vapier@gentoo.org>
60
61 * interp.c (sim_open): Change %lx to %x and PRIx macros.
62
52d37d2c
MF		 632021-06-16 Mike Frysinger <vapier@gentoo.org>
64
65 * configure: Regenerate.
66 * config.in: Removed.
67
bcaa61f7
MF		 682021-06-15 Mike Frysinger <vapier@gentoo.org>
69
70 * config.in, configure: Regenerate.
71
ba307cdd
MF		 722021-06-12 Mike Frysinger <vapier@gentoo.org>
73
74 * configure.ac: Delete call to SIM_AC_OPTION_ALIGNMENT.
75
dba333c1
MF		 762021-06-12 Mike Frysinger <vapier@gentoo.org>
77
78 * aclocal.m4, config.in, configure: Regenerate.
79
b15c5d7a
MF		 802021-06-12 Mike Frysinger <vapier@gentoo.org>
81
82 * configure.ac: Delete call to AC_CHECK_FUNCS.
83 * config.in, configure: Regenerate.
84
a55b92be
MF		 852021-06-08 Mike Frysinger <vapier@gentoo.org>
86
87 * Makefile.in: Replace $(IGEN) with $(IGEN_RUN) and ../igen/igen
88 with $(IGEN).
89
8ea881d9
MF		 902021-05-29 Mike Frysinger <vapier@gentoo.org>
91
92 * interp.c [!HAVE_DV_SOCKSER] (sockser_addr): Define to NULL.
93
b312488f
FS		 942021-05-22 Faraz Shahbazker <fshahbazker@wavecomp.com>
95
168671c1
FS		 96 * interp.c (sim_open): Add shadow mappings from 32-bit
97 address space to 64-bit sign-extended address space.
98
992021-05-22 Faraz Shahbazker <fshahbazker@wavecomp.com>
100
b312488f
FS		 101 * interp.c (sim_create_inferior): Only truncate sign extension
102 bits for 32-bit target models.
103
f4fdd845
MF		 1042021-05-17 Mike Frysinger <vapier@gentoo.org>
105
106 * sim-main.h (SIM_HAVE_COMMON_SIM_STATE): Delete.
107
8ea7241c
MF		 1082021-05-17 Mike Frysinger <vapier@gentoo.org>
109
110 * interp.c (sim_open): Switch to sim_state_alloc_extra.
111 * micromips.igen: Change SD to mips_sim_state.
112 * micromipsrun.c (sim_engine_run): Likewise.
113 * sim-main.h (SIM_HAVE_COMMON_SIM_STATE): Define.
114 (watch_options_install): Delete.
115 (struct swatch): Delete.
116 (struct sim_state): Delete.
117 (struct mips_sim_state): New struct.
118 (MIPS_SIM_STATE): Define.
119
6df01ab8
MF		 1202021-05-16 Mike Frysinger <vapier@gentoo.org>
121
122 * interp.c: Replace config.h include with defs.h.
123 * cp1.c, dsp.c, dv-tx3904cpu.c, dv-tx3904irc.c, dv-tx3904sio.c,
124 dv-tx3904tmr.c, m16run.c, mdmx.c, micromipsrun.c, sim-main.c:
125 Include defs.h.
126
79633c12
MF		 1272021-05-16 Mike Frysinger <vapier@gentoo.org>
128
129 * config.in, configure: Regenerate.
130
df68e12b
MF		 1312021-05-14 Mike Frysinger <vapier@gentoo.org>
132
133 * interp.c: Update include path.
134
77c0fdb7
MF		 1352021-05-04 Mike Frysinger <vapier@gentoo.org>
136
137 * dv-tx3904sio.c: Include stdlib.h.
138
9b1af85c
MF		 1392021-05-04 Mike Frysinger <vapier@gentoo.org>
140
141 * configure.ac (hw_extra_devices): Inline contents into
142 SIM_AC_OPTION_HARDWARE and delete.
143 * configure: Regenerate.
144
d97ba9c6
MF		 1452021-05-04 Mike Frysinger <vapier@gentoo.org>
146
147 * Makefile.in (SIM_IGEN_OBJ): Change @mips_igen_engine@ to engine.o.
148 (MIPS_EXTRA_LIB, SIM_EXTRA_LIBS): Delete.
149 * configure.ac (mips_igen_engine, mips_extra_libs): Delete.
150 * configure: Regenerate.
151
4df817de
MF		 1522021-05-04 Mike Frysinger <vapier@gentoo.org>
153
154 * mdmx.c (qh_acc): Change 2nd AccAddAQH to AccAddLQH.
155
aa0fca16
MF		 1562021-05-04 Mike Frysinger <vapier@gentoo.org>
157
158 * configure: Regenerate.
159
adbaa7b8
MF		 1602021-05-01 Mike Frysinger <vapier@gentoo.org>
161
162 * cp1.c (store_fcr): Mark static.
163
fe348617
MF		 1642021-05-01 Mike Frysinger <vapier@gentoo.org>
165
166 * config.in, configure: Regenerate.
167
9d903352
MF		 1682021-04-23 Mike Frysinger <vapier@gentoo.org>
169
170 * configure.ac (hw_enabled): Delete.
171 (SIM_AC_OPTION_HARDWARE): Delete first two args.
172 * configure: Regenerate.
173
19f6a43c
TT		 1742021-04-22 Tom Tromey <tom@tromey.com>
175
176 * configure, config.in: Rebuild.
177
e7d8f1da
TT		 1782021-04-22 Tom Tromey <tom@tromey.com>
179
180 * Makefile.in (interp.o, m16run.o, micromipsrun.o, multi-run.o):
181 Remove.
182 (SIM_EXTRA_DEPS): New variable.
183
efd82ac7
TT		 1842021-04-22 Tom Tromey <tom@tromey.com>
185
186 * configure: Rebuild.
187
2662c237
MF		 1882021-04-21 Mike Frysinger <vapier@gentoo.org>
189
190 * aclocal.m4: Regenerate.
191
1f195bc3
SM		 1922021-04-21 Simon Marchi <simon.marchi@polymtl.ca>
193
194 * configure: Regenerate.
195
37e9f182
MF		 1962021-04-18 Mike Frysinger <vapier@gentoo.org>
197
198 * configure: Regenerate.
199
d5a71b11
MF		 2002021-04-12 Mike Frysinger <vapier@gentoo.org>
201
202 * interp.c (sim_open): Delete 3rd arg to sim_cpu_alloc_all.
203
2b8d134b
SM		 2042021-04-08 Simon Marchi <simon.marchi@polymtl.ca>
205
206 * Makefile.in: Set ASAN_OPTIONS when running igen.
207
5c6f091a
FS		 2082021-04-04 Steve Ellcey <sellcey@mips.com>
209 Faraz Shahbazker <fshahbazker@wavecomp.com>
210
211 * interp.c (sim_monitor): Add switch entries for unlink (13),
212 lseek (14), and stat (15).
213
b6b1c790
MF		 2142021-04-02 Mike Frysinger <vapier@gentoo.org>
215
216 * Makefile.in (../igen/igen): Delete rule.
217 (tmp-igen, tmp-m16, tmp-micromips): Delete ../igen make.
218
c2783492
MF		 2192021-04-02 Mike Frysinger <vapier@gentoo.org>
220
221 * aclocal.m4, configure: Regenerate.
222
ebe9564b
MF		 2232021-02-28 Mike Frysinger <vapier@gentoo.org>
224
225 * configure: Regenerate.
226
f8069d55
MF		 2272021-02-27 Mike Frysinger <vapier@gentoo.org>
228
229 * Makefile.in (SIM_EXTRA_ALL): Delete.
230 (all): New target.
231
760b3e8b
MF		 2322021-02-21 Mike Frysinger <vapier@gentoo.org>
233
234 * configure.ac (AC_CONFIG_MACRO_DIRS): Replace common with m4.
235 * aclocal.m4, configure: Regenerate.
236
136da8cd
MF		 2372021-02-13 Mike Frysinger <vapier@gentoo.org>
238
239 * configure.ac: Replace sinclude with AC_CONFIG_MACRO_DIRS.
240 * aclocal.m4, configure: Regenerate.
241
4c0d76b9
MF		 2422021-02-06 Mike Frysinger <vapier@gentoo.org>
243
244 * interp.c (sim_open): Delete call to STATE_WATCHPOINTS.
245
aa09469f
MF		 2462021-02-06 Mike Frysinger <vapier@gentoo.org>
247
248 * configure: Regenerate.
249
d4e3adda
MF		 2502021-01-30 Mike Frysinger <vapier@gentoo.org>
251
252 * interp.c (sim_open): Delete STATE_WATCHPOINTS (sd)->sizeof_pc.
253
68ed2854
MF		 2542021-01-11 Mike Frysinger <vapier@gentoo.org>
255
256 * config.in, configure: Regenerate.
257 * interp.c: Delete HAVE_STRING_H, HAVE_STRINGS_H, HAVE_STDLIB_H,
258 and strings.h include.
259
50df264d
MF		 2602021-01-09 Mike Frysinger <vapier@gentoo.org>
261
262 * configure: Regenerate.
263
bf470982
MF		 2642021-01-09 Mike Frysinger <vapier@gentoo.org>
265
266 * configure.ac (SIM_AC_OPTION_WARNINGS): Pass "no".
267 * configure: Regenerate.
268
46f900c0
MF		 2692021-01-08 Mike Frysinger <vapier@gentoo.org>
270
271 * configure: Regenerate.
272
dfb856ba
MF		 2732021-01-04 Mike Frysinger <vapier@gentoo.org>
274
275 * configure: Regenerate.
276
382bc56b
PK		 2772020-12-31 Pavel I. Kryukov <kryukov@frtk.ru> (tiny change)
278
279 * sim-main.c: Include <stdlib.h>.
280
ad9675dd
PK		 2812020-12-14 Pavel I. Kryukov <kryukov@frtk.ru> (tiny change)
282
283 * cp1.c: Include <stdlib.h>.
284
f693213d
SM		 2852020-07-29 Simon Marchi <simon.marchi@efficios.com>
286
287 * configure: Re-generate.
288
5c887dd5
JB		 2892017-09-06 John Baldwin <jhb@FreeBSD.org>
290
291 * configure: Regenerate.
292
91588b3a
MF		 2932016-11-11 Mike Frysinger <vapier@gentoo.org>
294
6cb2202b 295 PR sim/20808
91588b3a
MF		 296 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Define CPU to cpu
297 and SD to sd.
298
e04659e8
MF		 2992016-11-11 Mike Frysinger <vapier@gentoo.org>
300
6cb2202b 301 PR sim/20809
e04659e8
MF		 302 * mips.igen (check_u64): Enable for `r3900'.
303
1554f758
MF		 3042016-02-05 Mike Frysinger <vapier@gentoo.org>
305
306 * configure.ac (sim_engine_run): Change sd->base.prog_bfd to
307 STATE_PROG_BFD (sd).
308 * configure: Regenerate.
309
3d304f48
AB		 3102016-01-18 Andrew Bennett <andrew.bennett@imgtec.com>
311 Maciej W. Rozycki <macro@imgtec.com>
312
313 PR sim/19441
314 * micromips.igen (delayslot_micromips): Enable for `micromips32',
315 `micromips64' and `micromipsdsp' only.
316 (process_isa_mode): Enable for `micromips32' and `micromips64' only.
317 (do_micromips_jalr, do_micromips_jal): Likewise.
318 (compute_movep_src_reg): Likewise.
319 (compute_andi16_imm): Likewise.
320 (convert_fmt_micromips): Likewise.
321 (convert_fmt_micromips_cvt_d): Likewise.
322 (convert_fmt_micromips_cvt_s): Likewise.
323 (FMT_MICROMIPS): Likewise.
324 (FMT_MICROMIPS_CVT_D): Likewise.
325 (FMT_MICROMIPS_CVT_S): Likewise.
326
b36d953b
MF		 3272016-01-12 Mike Frysinger <vapier@gentoo.org>
328
329 * interp.c: Include elf-bfd.h.
330 (sim_create_inferior): Truncate pc to 32-bits when EI_CLASS is
331 ELFCLASS32.
332
ce39bd38
MF		 3332016-01-10 Mike Frysinger <vapier@gentoo.org>
334
335 * config.in, configure: Regenerate.
336
99d8e879
MF		 3372016-01-10 Mike Frysinger <vapier@gentoo.org>
338
339 * configure: Regenerate.
340
35656e95
MF		 3412016-01-10 Mike Frysinger <vapier@gentoo.org>
342
343 * configure: Regenerate.
344
16f7876d
MF		 3452016-01-10 Mike Frysinger <vapier@gentoo.org>
346
347 * configure: Regenerate.
348
e19418e0
MF		 3492016-01-10 Mike Frysinger <vapier@gentoo.org>
350
351 * configure: Regenerate.
352
6d90347b
MF		 3532016-01-10 Mike Frysinger <vapier@gentoo.org>
354
355 * configure.ac (SIM_AC_OPTION_SMP): Delete call.
356 * configure: Regenerate.
357
347fe5bb
MF		 3582016-01-10 Mike Frysinger <vapier@gentoo.org>
359
360 * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
361 * configure: Regenerate.
362
22be3fbe
MF		 3632016-01-10 Mike Frysinger <vapier@gentoo.org>
364
365 * configure: Regenerate.
366
0dc73ef7
MF		 3672016-01-10 Mike Frysinger <vapier@gentoo.org>
368
369 * configure: Regenerate.
370
936df756
MF		 3712016-01-09 Mike Frysinger <vapier@gentoo.org>
372
373 * config.in, configure: Regenerate.
374
2e3d4f4d
MF		 3752016-01-06 Mike Frysinger <vapier@gentoo.org>
376
377 * interp.c (sim_open): Mark argv const.
378 (sim_create_inferior): Mark argv and env const.
379
9bbf6f91
MF		 3802016-01-04 Mike Frysinger <vapier@gentoo.org>
381
382 * configure: Regenerate.
383
77cf2ef5
MF		 3842016-01-03 Mike Frysinger <vapier@gentoo.org>
385
386 * interp.c (sim_open): Update sim_parse_args comment.
387
0cb8d851
MF		 3882016-01-03 Mike Frysinger <vapier@gentoo.org>
389
390 * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
391 * configure: Regenerate.
392
1ac72f06
MF		 3932016-01-02 Mike Frysinger <vapier@gentoo.org>
394
395 * configure.ac (mips_endian): Change LITTLE_ENDIAN to LITTLE.
396 (default_endian): Likewise. Change BIG_ENDIAN to BIG.
397 * configure: Regenerate.
398 * sim-main.h (BigEndianMem): Change BIG_ENDIAN to BFD_ENDIAN_BIG.
399
d47f5b30
MF		 4002016-01-02 Mike Frysinger <vapier@gentoo.org>
401
402 * dv-tx3904cpu.c (CPU, SD): Delete.
403
e1211e55
MF		 4042015-12-30 Mike Frysinger <vapier@gentoo.org>
405
406 * wrapper.c (mips_reg_store, mips_reg_fetch): Define.
407 (sim_open): Call CPU_REG_FETCH/CPU_REG_STORE.
408 (sim_store_register): Rename to ...
409 (mips_reg_store): ... this. Delete local cpu var.
410 Update sim_io_eprintf calls.
411 (sim_fetch_register): Rename to ...
412 (mips_reg_fetch): ... this. Delete local cpu var.
413 Update sim_io_eprintf calls.
414
5e744ef8
MF		 4152015-12-27 Mike Frysinger <vapier@gentoo.org>
416
417 * Makefile.in (SIM_OBJS): Delete sim-hload.o.
418
1b393626
MF		 4192015-12-26 Mike Frysinger <vapier@gentoo.org>
420
421 * config.in, configure: Regenerate.
422
26f8bf63
MF		 4232015-12-26 Mike Frysinger <vapier@gentoo.org>
424
425 * interp.c (sim_write, sim_read): Delete.
426 (store_word): Delete call to AddressTranslation and set paddr=vaddr.
427 (load_word): Likewise.
428 * micromips.igen (cache): Likewise.
429 * mips.igen (do_ll, do_lld, do_sc, do_scd, do_suxc1_32, do_swc1,
430 do_swxc1, cache, do_load, do_load_left, do_load_right, do_store,
431 do_store_left, do_store_right, do_load_double, do_store_double):
432 Likewise.
433 (do_pref): Delete call to AddressTranslation and stub out Prefetch.
434 (do_prefx): Likewise.
435 * sim-main.c (address_translation, prefetch): Delete.
436 (ifetch32, ifetch16): Delete call to AddressTranslation and set
437 paddr=vaddr.
438 * sim-main.h (Uncached, CachedNoncoherent, CachedCoherent, Cached,
439 address_translation, AddressTranslation, prefetch, Prefetch): Delete.
440 (LoadMemory, StoreMemory): Delete CCA arg.
441
ef04e371
MF		 4422015-12-24 Mike Frysinger <vapier@gentoo.org>
443
444 * configure.ac (SIM_SUBTARGET): Drop -DTARGET_TX3904=1.
445 * configure: Regenerated.
446
cb379ede
MF		 4472015-12-24 Mike Frysinger <vapier@gentoo.org>
448
449 * sim-main.h (SIM_QUIET_NAN_NEGATED): Move from tconfig.h.
450 * tconfig.h: Delete.
451
26936211
MF		 4522015-12-24 Mike Frysinger <vapier@gentoo.org>
453
454 * tconfig.h (SIM_HANDLES_LMA): Delete.
455
84e8e361
MF		 4562015-12-24 Mike Frysinger <vapier@gentoo.org>
457
458 * sim-main.h (WITH_WATCHPOINTS): Delete.
459
3cabaf66
MF		 4602015-12-24 Mike Frysinger <vapier@gentoo.org>
461
462 * interp.c [SIM_HAVE_FLATMEM] (sim_open): Delete flatmem code.
463
8abe6c66
MF		 4642015-12-24 Mike Frysinger <vapier@gentoo.org>
465
466 * tconfig.h (SIM_HAVE_SIMCACHE): Delete.
467
1d19cae7
DV		 4682015-12-15 Dominik Vogt <vogt@linux.vnet.ibm.com>
469
470 * micromips.igen (process_isa_mode): Fix left shift of negative
471 value.
472
cdf850e9
MF		 4732015-11-17 Mike Frysinger <vapier@gentoo.org>
474
475 * sim-main.h (WITH_MODULO_MEMORY): Delete.
476
797eee42
MF		 4772015-11-15 Mike Frysinger <vapier@gentoo.org>
478
479 * Makefile.in (SIM_OBJS): Delete sim-reason.o and sim-stop.o.
480
6e4f085c
MF		 4812015-11-14 Mike Frysinger <vapier@gentoo.org>
482
483 * interp.c (sim_close): Rename to ...
484 (mips_sim_close): ... this. Delete calls to sim_module_uninstall and
485 sim_io_shutdown.
486 * sim-main.h (mips_sim_close): Declare.
487 (SIM_CLOSE_HOOK): Define.
488
8e394ffc
AB		 4892015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
490 Ali Lown <ali.lown@imgtec.com>
491
492 * Makefile.in (tmp-micromips): New rule.
493 (tmp-mach-multi): Add support for micromips.
494 * configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
495 that works for both mips64 and micromips64.
496 (mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
497 micromips32.
498 Add build support for micromips.
499 * dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
500 do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
501 do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
502 do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
503 do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
504 do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
505 do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
506 do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
507 Refactored instruction code to use these functions.
508 * dsp2.igen: Refactored instruction code to use the new functions.
509 * interp.c (decode_coproc): Refactored to work with any instruction
510 encoding.
511 (isa_mode): New variable
512 (RSVD_INSTRUCTION): Changed to 0x00000039.
513 * m16.igen (BREAK16): Refactored instruction to use do_break16.
514 (JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
515 * micromips.dc: New file.
516 * micromips.igen: New file.
517 * micromips16.dc: New file.
518 * micromipsdsp.igen: New file.
519 * micromipsrun.c: New file.
520 * mips.igen (do_swc1): Changed to work with any instruction encoding.
521 (do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
522 do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo,
523 do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu,
524 do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu,
525 do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub,
526 do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo,
527 do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc,
528 do_scd, do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu,
529 do_tgeu, do_tlt do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt,
530 do_add_fmt, do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1,
531 do_cvt_d_fmt, do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl,
532 do_cvt_s_pu, do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt,
533 do_luxc1_32, do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b,
534 do_mov_fmt, do_movtf, do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt,
535 do_mtc1b, do_mul_fmt, do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps,
536 do_plu_ps, do_pul_ps, do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt,
537 do_prefx, do_sdc1, do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt,
538 do_swc1, do_swxc1, do_trunc_fmt): New functions, refactored from existing
539 instructions.
540 Refactored instruction code to use these functions.
541 (RSVD): Changed to use new reserved instruction.
542 (loadstore_ea, not_word_value, unpredictable, check_mt_hilo,
543 check_mf_hilo, check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32,
544 do_sdc1, do_suxc1_32, check_fmt_p, check_fpu, do_load_double,
545 do_store_double): Added micromips32 and micromips64 models.
546 Added include for micromips.igen and micromipsdsp.igen
547 Add micromips32 and micromips64 models.
548 (DecodeCoproc): Updated to use new macro definition.
549 * mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
550 do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
551 do_seb, do_seh do_rdhwr, do_wsbh): New functions.
552 Refactored instruction code to use these functions.
553 * sim-main.h (CP0_operation): New enum.
554 (DecodeCoproc): Updated macro.
555 (IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
556 MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16,
557 MICROMIPS_DELAYSLOT_SIZE_32, ISA_MODE_MIPS32 and
558 ISA_MODE_MICROMIPS): New defines.
559 (sim_state): Add isa_mode field.
560
8d0978fb
MF		 5612015-06-23 Mike Frysinger <vapier@gentoo.org>
562
563 * configure: Regenerate.
564
306f4178
MF		 5652015-06-12 Mike Frysinger <vapier@gentoo.org>
566
567 * configure.ac: Change configure.in to configure.ac.
568 * configure: Regenerate.
569
a3487082
MF		 5702015-06-12 Mike Frysinger <vapier@gentoo.org>
571
572 * configure: Regenerate.
573
29bc024d
MF		 5742015-06-12 Mike Frysinger <vapier@gentoo.org>
575
576 * interp.c [TRACE]: Delete.
577 (TRACE): Change to WITH_TRACE_ANY_P.
578 [!WITH_TRACE_ANY_P] (open_trace): Define.
579 (mips_option_handler, open_trace, sim_close, dotrace):
580 Change defined(TRACE) to WITH_TRACE_ANY_P.
581 (sim_open): Delete TRACE ifdef check.
582 * sim-main.c (load_memory): Delete TRACE ifdef check.
583 (store_memory): Likewise.
584 * sim-main.h [WITH_TRACE_ANY_P] (dotrace, tracefh): Protect decls.
585 [!WITH_TRACE_ANY_P] (dotrace): Define.
586
3ebe2863
MF		 5872015-04-18 Mike Frysinger <vapier@gentoo.org>
588
589 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESTART_HOOK): Delete
590 comments.
591
20bca71d
MF		 5922015-04-18 Mike Frysinger <vapier@gentoo.org>
593
594 * sim-main.h (SIM_CPU): Delete.
595
7e83aa92
MF		 5962015-04-18 Mike Frysinger <vapier@gentoo.org>
597
598 * sim-main.h (sim_cia): Delete.
599
034685f9
MF		 6002015-04-17 Mike Frysinger <vapier@gentoo.org>
601
602 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Change CIA_GET to
603 PU_PC_GET.
604 * interp.c (interrupt_event): Change CIA_GET to CPU_PC_GET.
605 (sim_create_inferior): Change CIA_SET to CPU_PC_SET.
606 * m16run.c (sim_engine_run): Change CIA_GET to CPU_PC_GET and
607 CIA_SET to CPU_PC_SET.
608 * sim-main.h (CIA_GET, CIA_SET): Delete.
609
78e9aa70
MF		 6102015-04-15 Mike Frysinger <vapier@gentoo.org>
611
612 * Makefile.in (SIM_OBJS): Delete sim-cpu.o.
613 * sim-main.h (STATE_CPU): Delete.
614
bf12d44e
MF		 6152015-04-13 Mike Frysinger <vapier@gentoo.org>
616
617 * configure: Regenerate.
618
7bebb329
MF		 6192015-04-13 Mike Frysinger <vapier@gentoo.org>
620
621 * Makefile.in (SIM_OBJS): Add sim-cpu.o.
622 * interp.c (mips_pc_get, mips_pc_set): New functions.
623 (sim_open): Declare new local var i. Call sim_cpu_alloc_all.
624 Call CPU_PC_FETCH & CPU_PC_STORE for all cpus.
625 (sim_pc_get): Delete.
626 * sim-main.h (SIM_CPU): Define.
627 (struct sim_state): Change cpu to an array of pointers.
628 (STATE_CPU): Drop &.
629
8ac57fbd
MF		 6302015-04-13 Mike Frysinger <vapier@gentoo.org>
631
632 * interp.c (mips_option_handler, open_trace, sim_close,
633 sim_write, sim_read, sim_store_register, sim_fetch_register,
634 sim_create_inferior, pr_addr, pr_uword64): Convert old style
635 prototypes.
636 (sim_open): Convert old style prototype. Change casts with
637 sim_write to unsigned char *.
638 (fetch_str): Change null to unsigned char, and change cast to
639 unsigned char *.
640 (sim_monitor): Change c & ch to unsigned char. Change cast to
641 unsigned char *.
642
e787f858
MF		 6432015-04-12 Mike Frysinger <vapier@gentoo.org>
644
645 * Makefile.in (SIM_OBJS): Move interp.o to the start of the list.
646
122bbfb5
MF		 6472015-04-06 Mike Frysinger <vapier@gentoo.org>
648
649 * Makefile.in (SIM_OBJS): Delete sim-engine.o.
650
0fe84f3f
MF		 6512015-04-01 Mike Frysinger <vapier@gentoo.org>
652
653 * tconfig.h (SIM_HAVE_PROFILE): Delete.
654
aadc9410
MF		 6552015-03-31 Mike Frysinger <vapier@gentoo.org>
656
657 * config.in, configure: Regenerate.
658
05f53ed6
MF		 6592015-03-24 Mike Frysinger <vapier@gentoo.org>
660
661 * interp.c (sim_pc_get): New function.
662
c0931f26
MF		 6632015-03-24 Mike Frysinger <vapier@gentoo.org>
664
665 * sim-main.h (SIM_HAVE_BIENDIAN): Delete.
666 * tconfig.h (SIM_HAVE_BIENDIAN): Delete.
667
30452bbe
MF		 6682015-03-24 Mike Frysinger <vapier@gentoo.org>
669
670 * configure: Regenerate.
671
64dd13df
MF		 6722015-03-23 Mike Frysinger <vapier@gentoo.org>
673
674 * configure: Regenerate.
675
49cd1634
MF		 6762015-03-23 Mike Frysinger <vapier@gentoo.org>
677
678 * configure: Regenerate.
679 * configure.ac (mips_extra_objs): Delete.
680 * Makefile.in (MIPS_EXTRA_OBJS): Delete.
681 (SIM_OBJS): Delete MIPS_EXTRA_OBJS.
682
3649cb06
MF		 6832015-03-23 Mike Frysinger <vapier@gentoo.org>
684
685 * configure: Regenerate.
686 * configure.ac: Delete sim_hw checks for dv-sockser.
687
ae7d0cac
MF		 6882015-03-16 Mike Frysinger <vapier@gentoo.org>
689
690 * config.in, configure: Regenerate.
691 * tconfig.in: Rename file ...
692 * tconfig.h: ... here.
693
8406bb59
MF		 6942015-03-15 Mike Frysinger <vapier@gentoo.org>
695
696 * tconfig.in: Delete includes.
697 [HAVE_DV_SOCKSER]: Delete.
698
465fb143
MF		 6992015-03-14 Mike Frysinger <vapier@gentoo.org>
700
701 * Makefile.in (SIM_RUN_OBJS): Delete.
702
5cddc23a
MF		 7032015-03-14 Mike Frysinger <vapier@gentoo.org>
704
705 * configure.ac (AC_CHECK_HEADERS): Delete.
706 * aclocal.m4, configure: Regenerate.
707
2974be62
AM		 7082014-08-19 Alan Modra <amodra@gmail.com>
709
710 * configure: Regenerate.
711
faa743bb
RM		 7122014-08-15 Roland McGrath <mcgrathr@google.com>
713
714 * configure: Regenerate.
715 * config.in: Regenerate.
716
1a8a700e
MF		 7172014-03-04 Mike Frysinger <vapier@gentoo.org>
718
719 * configure: Regenerate.
720
bf3d9781
AM		 7212013-09-23 Alan Modra <amodra@gmail.com>
722
723 * configure: Regenerate.
724
31e6ad7d
MF		 7252013-06-03 Mike Frysinger <vapier@gentoo.org>
726
727 * aclocal.m4, configure: Regenerate.
728
d3685d60
TT		 7292013-05-10 Freddie Chopin <freddie_chopin@op.pl>
730
731 * configure: Rebuild.
732
1517bd27
MF		 7332013-03-26 Mike Frysinger <vapier@gentoo.org>
734
735 * configure: Regenerate.
736
3be31516
JS		 7372013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
738
739 * configure.ac: Address use of dv-sockser.o.
740 * tconfig.in: Conditionalize use of dv_sockser_install.
741 * configure: Regenerated.
742 * config.in: Regenerated.
743
37cb8f8e
SE		 7442012-10-04 Chao-ying Fu <fu@mips.com>
745 Steve Ellcey <sellcey@mips.com>
746
747 * mips/mips3264r2.igen (rdhwr): New.
748
87c8644f
JS		 7492012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
750
751 * configure.ac: Always link against dv-sockser.o.
752 * configure: Regenerate.
753
5f3ef9d0
JB		 7542012-06-15 Joel Brobecker <brobecker@adacore.com>
755
756 * config.in, configure: Regenerate.
757
a6ff997c
NC		 7582012-05-18 Nick Clifton <nickc@redhat.com>
759
760 PR 14072
761 * interp.c: Include config.h before system header files.
762
2232061b
MF		 7632012-03-24 Mike Frysinger <vapier@gentoo.org>
764
765 * aclocal.m4, config.in, configure: Regenerate.
766
db2e4d67
MF		 7672011-12-03 Mike Frysinger <vapier@gentoo.org>
768
769 * aclocal.m4: New file.
770 * configure: Regenerate.
771
4399a56b
MF		 7722011-10-19 Mike Frysinger <vapier@gentoo.org>
773
774 * configure: Regenerate after common/acinclude.m4 update.
775
9c082ca8
MF		 7762011-10-17 Mike Frysinger <vapier@gentoo.org>
777
778 * configure.ac: Change include to common/acinclude.m4.
779
6ffe910a
MF		 7802011-10-17 Mike Frysinger <vapier@gentoo.org>
781
782 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
783 call. Replace common.m4 include with SIM_AC_COMMON.
784 * configure: Regenerate.
785
31b28250
HPN		 7862011-07-08 Hans-Peter Nilsson <hp@axis.com>
787
3faa01e3
HPN		 788 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
789 $(SIM_EXTRA_DEPS).
790 (tmp-mach-multi): Exit early when igen fails.
31b28250 791
2419798b
MF		 7922011-07-05 Mike Frysinger <vapier@gentoo.org>
793
794 * interp.c (sim_do_command): Delete.
795
d79fe0d6
MF		 7962011-02-14 Mike Frysinger <vapier@gentoo.org>
797
798 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
799 (tx3904sio_fifo_reset): Likewise.
800 * interp.c (sim_monitor): Likewise.
801
5558e7e6
MF		 8022010-04-14 Mike Frysinger <vapier@gentoo.org>
803
804 * interp.c (sim_write): Add const to buffer arg.
805
35aafff4
JB		 8062010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
807
808 * interp.c: Don't include sysdep.h
809
3725885a
RW		 8102010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
811
812 * configure: Regenerate.
813
d6416cdc
RW		 8142009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
815
81ecdfbb
RW		 816 * config.in: Regenerate.
817 * configure: Likewise.
818
d6416cdc
RW		 819 * configure: Regenerate.
820
b5bd9624
HPN		 8212008-07-11 Hans-Peter Nilsson <hp@axis.com>
822
823 * configure: Regenerate to track ../common/common.m4 changes.
824 * config.in: Ditto.
825
6efef468 8262008-06-06 Vladimir Prus <vladimir@codesourcery.com>
72f4393d
L		 827 Daniel Jacobowitz <dan@codesourcery.com>
828 Joseph Myers <joseph@codesourcery.com>
6efef468
JM		 829
830 * configure: Regenerate.
831
60dc88db
RS		 8322007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
833
834 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
835 that unconditionally allows fmt_ps.
836 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
837 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
838 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
839 filter from 64,f to 32,f.
840 (PREFX): Change filter from 64 to 32.
841 (LDXC1, LUXC1): Provide separate mips32r2 implementations
842 that use do_load_double instead of do_load. Make both LUXC1
843 versions unpredictable if SizeFGR () != 64.
844 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
845 instead of do_store. Remove unused variable. Make both SUXC1
846 versions unpredictable if SizeFGR () != 64.
847
599ca73e
RS		 8482007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
849
850 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
851 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
852 shifts for that case.
853
2525df03
NC		 8542007-09-04 Nick Clifton <nickc@redhat.com>
855
856 * interp.c (options enum): Add OPTION_INFO_MEMORY.
857 (display_mem_info): New static variable.
858 (mips_option_handler): Handle OPTION_INFO_MEMORY.
859 (mips_options): Add info-memory and memory-info.
860 (sim_open): After processing the command line and board
861 specification, check display_mem_info. If it is set then
862 call the real handler for the --memory-info command line
863 switch.
864
35ee6e1e
JB		 8652007-08-24 Joel Brobecker <brobecker@adacore.com>
866
867 * configure.ac: Change license of multi-run.c to GPL version 3.
868 * configure: Regenerate.
869
d5fb0879
RS		 8702007-06-28 Richard Sandiford <richard@codesourcery.com>
871
872 * configure.ac, configure: Revert last patch.
873
2a2ce21b
RS		 8742007-06-26 Richard Sandiford <richard@codesourcery.com>
875
876 * configure.ac (sim_mipsisa3264_configs): New variable.
877 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
878 every configuration support all four targets, using the triplet to
879 determine the default.
880 * configure: Regenerate.
881
efdcccc9
RS		 8822007-06-25 Richard Sandiford <richard@codesourcery.com>
883
0a7692b2 884 * Makefile.in (m16run.o): New rule.
efdcccc9 885
f532a356
TS		 8862007-05-15 Thiemo Seufer <ths@mips.com>
887
888 * mips3264r2.igen (DSHD): Fix compile warning.
889
bfe9c90b
TS		 8902007-05-14 Thiemo Seufer <ths@mips.com>
891
892 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
893 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
894 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
895 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
896 for mips32r2.
897
53f4826b
TS		 8982007-03-01 Thiemo Seufer <ths@mips.com>
899
900 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
901 and mips64.
902
8bf3ddc8
TS		 9032007-02-20 Thiemo Seufer <ths@mips.com>
904
905 * dsp.igen: Update copyright notice.
906 * dsp2.igen: Fix copyright notice.
907
8b082fb1 9082007-02-20 Thiemo Seufer <ths@mips.com>
72f4393d 909 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 910
911 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
912 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
913 Add dsp2 to sim_igen_machine.
914 * configure: Regenerate.
915 * dsp.igen (do_ph_op): Add MUL support when op = 2.
916 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
917 (mulq_rs.ph): Use do_ph_mulq.
918 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
919 * mips.igen: Add dsp2 model and include dsp2.igen.
920 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
921 for *mips32r2, *mips64r2, *dsp.
922 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
923 for *mips32r2, *mips64r2, *dsp2.
924 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
925
b1004875 9262007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 927 Nigel Stephens <nigel@mips.com>
b1004875
TS		 928
929 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
930 jumps with hazard barrier.
931
f8df4c77 9322007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 933 Nigel Stephens <nigel@mips.com>
f8df4c77
TS		 934
935 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
936 after each call to sim_io_write.
937
b1004875 9382007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 939 Nigel Stephens <nigel@mips.com>
b1004875
TS		 940
941 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
942 supported by this simulator.
07802d98
TS		 943 (decode_coproc): Recognise additional CP0 Config registers
944 correctly.
945
14fb6c5a 9462007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d
L		 947 Nigel Stephens <nigel@mips.com>
948 David Ung <davidu@mips.com>
14fb6c5a
TS		 949
950 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
951 uninterpreted formats. If fmt is one of the uninterpreted types
952 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
953 fmt_word, and fmt_uninterpreted_64 like fmt_long.
954 (store_fpr): When writing an invalid odd register, set the
955 matching even register to fmt_unknown, not the following register.
956 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
957 the the memory window at offset 0 set by --memory-size command
958 line option.
959 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
960 point register.
961 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
962 register.
963 (sim_monitor): When returning the memory size to the MIPS
964 application, use the value in STATE_MEM_SIZE, not an arbitrary
965 hardcoded value.
966 (cop_lw): Don' mess around with FPR_STATE, just pass
967 fmt_uninterpreted_32 to StoreFPR.
968 (cop_sw): Similarly.
969 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
970 (cop_sd): Similarly.
971 * mips.igen (not_word_value): Single version for mips32, mips64
972 and mips16.
973
c8847145 9742007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 975 Nigel Stephens <nigel@mips.com>
c8847145
TS		 976
977 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
978 MBytes.
979
4b5d35ee
TS		 9802007-02-17 Thiemo Seufer <ths@mips.com>
981
982 * configure.ac (mips*-sde-elf*): Move in front of generic machine
983 configuration.
984 * configure: Regenerate.
985
3669427c
TS		 9862007-02-17 Thiemo Seufer <ths@mips.com>
987
988 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
989 Add mdmx to sim_igen_machine.
990 (mipsisa64*-*-*): Likewise. Remove dsp.
991 (mipsisa32*-*-*): Remove dsp.
992 * configure: Regenerate.
993
109ad085
TS		 9942007-02-13 Thiemo Seufer <ths@mips.com>
995
996 * configure.ac: Add mips*-sde-elf* target.
997 * configure: Regenerate.
998
921d7ad3
HPN		 9992006-12-21 Hans-Peter Nilsson <hp@axis.com>
1000
1001 * acconfig.h: Remove.
1002 * config.in, configure: Regenerate.
1003
02f97da7
TS		 10042006-11-07 Thiemo Seufer <ths@mips.com>
1005
1006 * dsp.igen (do_w_op): Fix compiler warning.
1007
2d2733fc 10082006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 1009 David Ung <davidu@mips.com>
2d2733fc
TS		 1010
1011 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
1012 sim_igen_machine.
1013 * configure: Regenerate.
1014 * mips.igen (model): Add smartmips.
1015 (MADDU): Increment ACX if carry.
1016 (do_mult): Clear ACX.
1017 (ROR,RORV): Add smartmips.
72f4393d 1018 (include): Include smartmips.igen.
2d2733fc
TS		 1019 * sim-main.h (ACX): Set to REGISTERS[89].
1020 * smartmips.igen: New file.
1021
d85c3a10 10222006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 1023 David Ung <davidu@mips.com>
d85c3a10
TS		 1024
1025 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
1026 mips3264r2.igen. Add missing dependency rules.
1027 * m16e.igen: Support for mips16e save/restore instructions.
1028
e85e3205
RE		 10292006-06-13 Richard Earnshaw <rearnsha@arm.com>
1030
1031 * configure: Regenerated.
1032
2f0122dc
DJ		 10332006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
1034
1035 * configure: Regenerated.
1036
20e95c23
DJ		 10372006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
1038
1039 * configure: Regenerated.
1040
69088b17
CF		 10412006-05-15 Chao-ying Fu <fu@mips.com>
1042
1043 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
1044
0275de4e
NC		 10452006-04-18 Nick Clifton <nickc@redhat.com>
1046
1047 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
1048 statement.
1049
b3a3ffef
HPN		 10502006-03-29 Hans-Peter Nilsson <hp@axis.com>
1051
1052 * configure: Regenerate.
1053
40a5538e
CF		 10542005-12-14 Chao-ying Fu <fu@mips.com>
1055
1056 * Makefile.in (SIM_OBJS): Add dsp.o.
1057 (dsp.o): New dependency.
1058 (IGEN_INCLUDE): Add dsp.igen.
1059 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
1060 mipsisa64*-*-*): Add dsp to sim_igen_machine.
1061 * configure: Regenerate.
1062 * mips.igen: Add dsp model and include dsp.igen.
1063 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
1064 because these instructions are extended in DSP ASE.
1065 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
1066 adding 6 DSP accumulator registers and 1 DSP control register.
1067 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
1068 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
1069 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
1070 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
1071 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
1072 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
1073 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
1074 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
1075 DSPCR_CCOND_SMASK): New define.
1076 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
1077 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
1078
21d14896
ILT		 10792005-07-08 Ian Lance Taylor <ian@airs.com>
1080
1081 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
1082
b16d63da 10832005-06-16 David Ung <davidu@mips.com>
72f4393d
L		 1084 Nigel Stephens <nigel@mips.com>
1085
1086 * mips.igen: New mips16e model and include m16e.igen.
1087 (check_u64): Add mips16e tag.
1088 * m16e.igen: New file for MIPS16e instructions.
1089 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
1090 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
1091 models.
1092 * configure: Regenerate.
b16d63da 1093
e70cb6cd 10942005-05-26 David Ung <davidu@mips.com>
72f4393d 1095
e70cb6cd
CD		 1096 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
1097 tags to all instructions which are applicable to the new ISAs.
1098 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
1099 vr.igen.
1100 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
72f4393d 1101 instructions.
e70cb6cd
CD		 1102 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
1103 to mips.igen.
1104 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
1105 * configure: Regenerate.
72f4393d 1106
2b193c4a
MK		 11072005-03-23 Mark Kettenis <kettenis@gnu.org>
1108
1109 * configure: Regenerate.
1110
35695fd6
AC		 11112005-01-14 Andrew Cagney <cagney@gnu.org>
1112
1113 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
1114 explicit call to AC_CONFIG_HEADER.
1115 * configure: Regenerate.
1116
f0569246
AC		 11172005-01-12 Andrew Cagney <cagney@gnu.org>
1118
1119 * configure.ac: Update to use ../common/common.m4.
1120 * configure: Re-generate.
1121
38f48d72
AC		 11222005-01-11 Andrew Cagney <cagney@localhost.localdomain>
1123
1124 * configure: Regenerated to track ../common/aclocal.m4 changes.
1125
b7026657
AC		 11262005-01-07 Andrew Cagney <cagney@gnu.org>
1127
1128 * configure.ac: Rename configure.in, require autoconf 2.59.
1129 * configure: Re-generate.
1130
379832de
HPN		 11312004-12-08 Hans-Peter Nilsson <hp@axis.com>
1132
1133 * configure: Regenerate for ../common/aclocal.m4 update.
1134
cd62154c 11352004-09-24 Monika Chaddha <monika@acmet.com>
72f4393d 1136
cd62154c
AC		 1137 Committed by Andrew Cagney.
1138 * m16.igen (CMP, CMPI): Fix assembler.
1139
e5da76ec
CD		 11402004-08-18 Chris Demetriou <cgd@broadcom.com>
1141
1142 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
1143 * configure: Regenerate.
1144
139181c8
CD		 11452004-06-25 Chris Demetriou <cgd@broadcom.com>
1146
1147 * configure.in (sim_m16_machine): Include mipsIII.
1148 * configure: Regenerate.
1149
1a27f959
CD		 11502004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
1151
72f4393d 1152 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
1a27f959
CD		 1153 from COP0_BADVADDR.
1154 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
1155
5dbb7b5a
CD		 11562004-04-10 Chris Demetriou <cgd@broadcom.com>
1157
1158 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
1159
14234056
CD		 11602004-04-09 Chris Demetriou <cgd@broadcom.com>
1161
1162 * mips.igen (check_fmt): Remove.
1163 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
1164 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
1165 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
1166 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
1167 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
1168 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
1169 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1170 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
1171 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
1172 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
1173
c6f9085c
CD		 11742004-04-09 Chris Demetriou <cgd@broadcom.com>
1175
1176 * sb1.igen (check_sbx): New function.
1177 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
1178
11d66e66 11792004-03-29 Chris Demetriou <cgd@broadcom.com>
0e1b7197
RS		 1180 Richard Sandiford <rsandifo@redhat.com>
1181
1182 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
1183 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
1184 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
1185 separate implementations for mipsIV and mipsV. Use new macros to
1186 determine whether the restrictions apply.
1187
b3208fb8
CD		 11882004-01-19 Chris Demetriou <cgd@broadcom.com>
1189
1190 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
1191 (check_mult_hilo): Improve comments.
1192 (check_div_hilo): Likewise. Also, fork off a new version
1193 to handle mips32/mips64 (since there are no hazards to check
1194 in MIPS32/MIPS64).
1195
9a1d84fb
CD		 11962003-06-17 Richard Sandiford <rsandifo@redhat.com>
1197
1198 * mips.igen (do_dmultx): Fix check for negative operands.
1199
ae451ac6
ILT		 12002003-05-16 Ian Lance Taylor <ian@airs.com>
1201
1202 * Makefile.in (SHELL): Make sure this is defined.
1203 (various): Use $(SHELL) whenever we invoke move-if-change.
1204
dd69d292
CD		 12052003-05-03 Chris Demetriou <cgd@broadcom.com>
1206
1207 * cp1.c: Tweak attribution slightly.
1208 * cp1.h: Likewise.
1209 * mdmx.c: Likewise.
1210 * mdmx.igen: Likewise.
1211 * mips3d.igen: Likewise.
1212 * sb1.igen: Likewise.
1213
bcd0068e
CD		 12142003-04-15 Richard Sandiford <rsandifo@redhat.com>
1215
1216 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
1217 unsigned operands.
1218
6b4a8935
AC		 12192003-02-27 Andrew Cagney <cagney@redhat.com>
1220
601da316
AC		 1221 * interp.c (sim_open): Rename _bfd to bfd.
1222 (sim_create_inferior): Ditto.
6b4a8935 1223
d29e330f
CD		 12242003-01-14 Chris Demetriou <cgd@broadcom.com>
1225
1226 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
1227
a2353a08
CD		 12282003-01-14 Chris Demetriou <cgd@broadcom.com>
1229
1230 * mips.igen (EI, DI): Remove.
1231
80551777
CD		 12322003-01-05 Richard Sandiford <rsandifo@redhat.com>
1233
1234 * Makefile.in (tmp-run-multi): Fix mips16 filter.
1235
4c54fc26
CD		 12362003-01-04 Richard Sandiford <rsandifo@redhat.com>
1237 Andrew Cagney <ac131313@redhat.com>
1238 Gavin Romig-Koch <gavin@redhat.com>
1239 Graydon Hoare <graydon@redhat.com>
1240 Aldy Hernandez <aldyh@redhat.com>
1241 Dave Brolley <brolley@redhat.com>
1242 Chris Demetriou <cgd@broadcom.com>
1243
1244 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
1245 (sim_mach_default): New variable.
1246 (mips64vr-*-*, mips64vrel-*-*): New configurations.
1247 Add a new simulator generator, MULTI.
1248 * configure: Regenerate.
1249 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
1250 (multi-run.o): New dependency.
1251 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
1252 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
1253 (tmp-multi): Combine them.
1254 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
1255 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
1256 (distclean-extra): New rule.
1257 * sim-main.h: Include bfd.h.
1258 (MIPS_MACH): New macro.
1259 * mips.igen (vr4120, vr5400, vr5500): New models.
1260 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
1261 * vr.igen: Replace with new version.
1262
e6c674b8
CD		 12632003-01-04 Chris Demetriou <cgd@broadcom.com>
1264
1265 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
1266 * configure: Regenerate.
1267
28f50ac8
CD		 12682002-12-31 Chris Demetriou <cgd@broadcom.com>
1269
1270 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
1271 * mips.igen: Remove all invocations of check_branch_bug and
1272 mark_branch_bug.
1273
5071ffe6
CD		 12742002-12-16 Chris Demetriou <cgd@broadcom.com>
1275
72f4393d 1276 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
5071ffe6 1277
06e7837e
CD		 12782002-07-30 Chris Demetriou <cgd@broadcom.com>
1279
1280 * mips.igen (do_load_double, do_store_double): New functions.
1281 (LDC1, SDC1): Rename to...
1282 (LDC1b, SDC1b): respectively.
1283 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
1284
2265c243
MS		 12852002-07-29 Michael Snyder <msnyder@redhat.com>
1286
1287 * cp1.c (fp_recip2): Modify initialization expression so that
1288 GCC will recognize it as constant.
1289
a2f8b4f3
CD		 12902002-06-18 Chris Demetriou <cgd@broadcom.com>
1291
1292 * mdmx.c (SD_): Delete.
1293 (Unpredictable): Re-define, for now, to directly invoke
1294 unpredictable_action().
1295 (mdmx_acc_op): Fix error in .ob immediate handling.
1296
b4b6c939
AC		 12972002-06-18 Andrew Cagney <cagney@redhat.com>
1298
1299 * interp.c (sim_firmware_command): Initialize `address'.
1300
c8cca39f
AC		 13012002-06-16 Andrew Cagney <ac131313@redhat.com>
1302
1303 * configure: Regenerated to track ../common/aclocal.m4 changes.
1304
e7e81181 13052002-06-14 Chris Demetriou <cgd@broadcom.com>
72f4393d 1306 Ed Satterthwaite <ehs@broadcom.com>
e7e81181
CD		 1307
1308 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
1309 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
1310 * mips.igen: Include mips3d.igen.
1311 (mips3d): New model name for MIPS-3D ASE instructions.
1312 (CVT.W.fmt): Don't use this instruction for word (source) format
72f4393d 1313 instructions.
e7e81181
CD		 1314 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
1315 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
1316 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
1317 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
1318 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
1319 (RSquareRoot1, RSquareRoot2): New macros.
1320 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
1321 (fp_rsqrt2): New functions.
1322 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
1323 * configure: Regenerate.
1324
3a2b820e 13252002-06-13 Chris Demetriou <cgd@broadcom.com>
72f4393d 1326 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 1327
1328 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
1329 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
1330 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
1331 (convert): Note that this function is not used for paired-single
1332 format conversions.
1333 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
1334 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
1335 (check_fmt_p): Enable paired-single support.
1336 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
1337 (PUU.PS): New instructions.
1338 (CVT.S.fmt): Don't use this instruction for paired-single format
1339 destinations.
1340 * sim-main.h (FP_formats): New value 'fmt_ps.'
1341 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
1342 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
1343
d18ea9c2
CD		 13442002-06-12 Chris Demetriou <cgd@broadcom.com>
1345
1346 * mips.igen: Fix formatting of function calls in
1347 many FP operations.
1348
95fd5cee
CD		 13492002-06-12 Chris Demetriou <cgd@broadcom.com>
1350
1351 * mips.igen (MOVN, MOVZ): Trace result.
1352 (TNEI): Print "tnei" as the opcode name in traces.
1353 (CEIL.W): Add disassembly string for traces.
1354 (RSQRT.fmt): Make location of disassembly string consistent
1355 with other instructions.
1356
4f0d55ae
CD		 13572002-06-12 Chris Demetriou <cgd@broadcom.com>
1358
1359 * mips.igen (X): Delete unused function.
1360
3c25f8c7
AC		 13612002-06-08 Andrew Cagney <cagney@redhat.com>
1362
1363 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
1364
f3c08b7e 13652002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1366 Ed Satterthwaite <ehs@broadcom.com>
f3c08b7e
CD		 1367
1368 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
1369 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
1370 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
1371 (fp_nmsub): New prototypes.
1372 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
1373 (NegMultiplySub): New defines.
1374 * mips.igen (RSQRT.fmt): Use RSquareRoot().
1375 (MADD.D, MADD.S): Replace with...
1376 (MADD.fmt): New instruction.
1377 (MSUB.D, MSUB.S): Replace with...
1378 (MSUB.fmt): New instruction.
1379 (NMADD.D, NMADD.S): Replace with...
1380 (NMADD.fmt): New instruction.
1381 (NMSUB.D, MSUB.S): Replace with...
1382 (NMSUB.fmt): New instruction.
1383
52714ff9 13842002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1385 Ed Satterthwaite <ehs@broadcom.com>
52714ff9
CD		 1386
1387 * cp1.c: Fix more comment spelling and formatting.
1388 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
1389 (denorm_mode): New function.
1390 (fpu_unary, fpu_binary): Round results after operation, collect
1391 status from rounding operations, and update the FCSR.
1392 (convert): Collect status from integer conversions and rounding
1393 operations, and update the FCSR. Adjust NaN values that result
1394 from conversions. Convert to use sim_io_eprintf rather than
1395 fprintf, and remove some debugging code.
1396 * cp1.h (fenr_FS): New define.
1397
577d8c4b
CD		 13982002-06-07 Chris Demetriou <cgd@broadcom.com>
1399
1400 * cp1.c (convert): Remove unusable debugging code, and move MIPS
1401 rounding mode to sim FP rounding mode flag conversion code into...
1402 (rounding_mode): New function.
1403
196496ed
CD		 14042002-06-07 Chris Demetriou <cgd@broadcom.com>
1405
1406 * cp1.c: Clean up formatting of a few comments.
1407 (value_fpr): Reformat switch statement.
1408
cfe9ea23 14092002-06-06 Chris Demetriou <cgd@broadcom.com>
72f4393d 1410 Ed Satterthwaite <ehs@broadcom.com>
cfe9ea23
CD		 1411
1412 * cp1.h: New file.
1413 * sim-main.h: Include cp1.h.
1414 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
1415 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
1416 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
1417 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
1418 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
1419 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
1420 * cp1.c: Don't include sim-fpu.h; already included by
1421 sim-main.h. Clean up formatting of some comments.
1422 (NaN, Equal, Less): Remove.
1423 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
1424 (fp_cmp): New functions.
1425 * mips.igen (do_c_cond_fmt): Remove.
1426 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
1427 Compare. Add result tracing.
1428 (CxC1): Remove, replace with...
1429 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
1430 (DMxC1): Remove, replace with...
1431 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
72f4393d
L		 1432 (MxC1): Remove, replace with...
1433 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
cfe9ea23 1434
ee7254b0
CD		 14352002-06-04 Chris Demetriou <cgd@broadcom.com>
1436
1437 * sim-main.h (FGRIDX): Remove, replace all uses with...
1438 (FGR_BASE): New macro.
1439 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
1440 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
1441 (NR_FGR, FGR): Likewise.
1442 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
1443 * mips.igen: Likewise.
1444
d3eb724f
CD		 14452002-06-04 Chris Demetriou <cgd@broadcom.com>
1446
1447 * cp1.c: Add an FSF Copyright notice to this file.
1448
ba46ddd0 14492002-06-04 Chris Demetriou <cgd@broadcom.com>
72f4393d 1450 Ed Satterthwaite <ehs@broadcom.com>
ba46ddd0
CD		 1451
1452 * cp1.c (Infinity): Remove.
1453 * sim-main.h (Infinity): Likewise.
1454
1455 * cp1.c (fp_unary, fp_binary): New functions.
1456 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
1457 (fp_sqrt): New functions, implemented in terms of the above.
1458 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1459 (Recip, SquareRoot): Remove (replaced by functions above).
1460 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
1461 (fp_recip, fp_sqrt): New prototypes.
1462 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1463 (Recip, SquareRoot): Replace prototypes with #defines which
1464 invoke the functions above.
72f4393d 1465
18d8a52d
CD		 14662002-06-03 Chris Demetriou <cgd@broadcom.com>
1467
1468 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
1469 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
1470 file, remove PARAMS from prototypes.
1471 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
1472 simulator state arguments.
1473 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
1474 pass simulator state arguments.
1475 * cp1.c (SD): Redefine as CPU_STATE(cpu).
1476 (store_fpr, convert): Remove 'sd' argument.
1477 (value_fpr): Likewise. Convert to use 'SD' instead.
1478
0f154cbd
CD		 14792002-06-03 Chris Demetriou <cgd@broadcom.com>
1480
1481 * cp1.c (Min, Max): Remove #if 0'd functions.
1482 * sim-main.h (Min, Max): Remove.
1483
e80fc152
CD		 14842002-06-03 Chris Demetriou <cgd@broadcom.com>
1485
1486 * cp1.c: fix formatting of switch case and default labels.
1487 * interp.c: Likewise.
1488 * sim-main.c: Likewise.
1489
bad673a9
CD		 14902002-06-03 Chris Demetriou <cgd@broadcom.com>
1491
1492 * cp1.c: Clean up comments which describe FP formats.
1493 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
1494
7cbea089 14952002-06-03 Chris Demetriou <cgd@broadcom.com>
72f4393d 1496 Ed Satterthwaite <ehs@broadcom.com>
7cbea089
CD		 1497
1498 * configure.in (mipsisa64sb1*-*-*): New target for supporting
1499 Broadcom SiByte SB-1 processor configurations.
1500 * configure: Regenerate.
1501 * sb1.igen: New file.
1502 * mips.igen: Include sb1.igen.
1503 (sb1): New model.
1504 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
1505 * mdmx.igen: Add "sb1" model to all appropriate functions and
1506 instructions.
1507 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
1508 (ob_func, ob_acc): Reference the above.
1509 (qh_acc): Adjust to keep the same size as ob_acc.
1510 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
1511 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
1512
909daa82
CD		 15132002-06-03 Chris Demetriou <cgd@broadcom.com>
1514
1515 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
1516
f4f1b9f1 15172002-06-02 Chris Demetriou <cgd@broadcom.com>
72f4393d 1518 Ed Satterthwaite <ehs@broadcom.com>
f4f1b9f1
CD		 1519
1520 * mips.igen (mdmx): New (pseudo-)model.
1521 * mdmx.c, mdmx.igen: New files.
1522 * Makefile.in (SIM_OBJS): Add mdmx.o.
1523 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
1524 New typedefs.
1525 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
1526 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
1527 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
1528 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
1529 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
1530 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
1531 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
1532 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
1533 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
1534 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
1535 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
1536 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
1537 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
1538 (qh_fmtsel): New macros.
1539 (_sim_cpu): New member "acc".
1540 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
1541 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
1542
5accf1ff
CD		 15432002-05-01 Chris Demetriou <cgd@broadcom.com>
1544
1545 * interp.c: Use 'deprecated' rather than 'depreciated.'
1546 * sim-main.h: Likewise.
1547
402586aa
CD		 15482002-05-01 Chris Demetriou <cgd@broadcom.com>
1549
1550 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
1551 which wouldn't compile anyway.
1552 * sim-main.h (unpredictable_action): New function prototype.
1553 (Unpredictable): Define to call igen function unpredictable().
1554 (NotWordValue): New macro to call igen function not_word_value().
1555 (UndefinedResult): Remove.
1556 * interp.c (undefined_result): Remove.
1557 (unpredictable_action): New function.
1558 * mips.igen (not_word_value, unpredictable): New functions.
1559 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
1560 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
1561 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
1562 NotWordValue() to check for unpredictable inputs, then
1563 Unpredictable() to handle them.
1564
c9b9995a
CD		 15652002-02-24 Chris Demetriou <cgd@broadcom.com>
1566
1567 * mips.igen: Fix formatting of calls to Unpredictable().
1568
e1015982
AC		 15692002-04-20 Andrew Cagney <ac131313@redhat.com>
1570
1571 * interp.c (sim_open): Revert previous change.
1572
b882a66b
AO		 15732002-04-18 Alexandre Oliva <aoliva@redhat.com>
1574
1575 * interp.c (sim_open): Disable chunk of code that wrote code in
1576 vector table entries.
1577
c429b7dd
CD		 15782002-03-19 Chris Demetriou <cgd@broadcom.com>
1579
1580 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
1581 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
1582 unused definitions.
1583
37d146fa
CD		 15842002-03-19 Chris Demetriou <cgd@broadcom.com>
1585
1586 * cp1.c: Fix many formatting issues.
1587
07892c0b
CD		 15882002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1589
1590 * cp1.c (fpu_format_name): New function to replace...
1591 (DOFMT): This. Delete, and update all callers.
1592 (fpu_rounding_mode_name): New function to replace...
1593 (RMMODE): This. Delete, and update all callers.
1594
487f79b7
CD		 15952002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1596
1597 * interp.c: Move FPU support routines from here to...
1598 * cp1.c: Here. New file.
1599 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
1600 (cp1.o): New target.
1601
1e799e28
CD		 16022002-03-12 Chris Demetriou <cgd@broadcom.com>
1603
1604 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
1605 * mips.igen (mips32, mips64): New models, add to all instructions
1606 and functions as appropriate.
1607 (loadstore_ea, check_u64): New variant for model mips64.
1608 (check_fmt_p): New variant for models mipsV and mips64, remove
1609 mipsV model marking fro other variant.
1610 (SLL) Rename to...
1611 (SLLa) this.
1612 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
1613 for mips32 and mips64.
1614 (DCLO, DCLZ): New instructions for mips64.
1615
82f728db
CD		 16162002-03-07 Chris Demetriou <cgd@broadcom.com>
1617
1618 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
1619 immediate or code as a hex value with the "%#lx" format.
1620 (ANDI): Likewise, and fix printed instruction name.
1621
b96e7ef1
CD		 16222002-03-05 Chris Demetriou <cgd@broadcom.com>
1623
1624 * sim-main.h (UndefinedResult, Unpredictable): New macros
1625 which currently do nothing.
1626
d35d4f70
CD		 16272002-03-05 Chris Demetriou <cgd@broadcom.com>
1628
1629 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
1630 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
1631 (status_CU3): New definitions.
1632
1633 * sim-main.h (ExceptionCause): Add new values for MIPS32
1634 and MIPS64: MDMX, MCheck, CacheErr. Update comments
1635 for DebugBreakPoint and NMIReset to note their status in
1636 MIPS32 and MIPS64.
1637 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
1638 (SignalExceptionCacheErr): New exception macros.
1639
3ad6f714
CD		 16402002-03-05 Chris Demetriou <cgd@broadcom.com>
1641
1642 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
1643 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
1644 is always enabled.
1645 (SignalExceptionCoProcessorUnusable): Take as argument the
1646 unusable coprocessor number.
1647
86b77b47
CD		 16482002-03-05 Chris Demetriou <cgd@broadcom.com>
1649
1650 * mips.igen: Fix formatting of all SignalException calls.
1651
97a88e93 16522002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 1653
1654 * sim-main.h (SIGNEXTEND): Remove.
1655
97a88e93 16562002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 1657
1658 * mips.igen: Remove gencode comment from top of file, fix
1659 spelling in another comment.
1660
97a88e93 16612002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 1662
1663 * mips.igen (check_fmt, check_fmt_p): New functions to check
1664 whether specific floating point formats are usable.
1665 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1666 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
1667 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
1668 Use the new functions.
1669 (do_c_cond_fmt): Remove format checks...
1670 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
1671
97a88e93 16722002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 1673
1674 * mips.igen: Fix formatting of check_fpu calls.
1675
41774c9d
CD		 16762002-03-03 Chris Demetriou <cgd@broadcom.com>
1677
1678 * mips.igen (FLOOR.L.fmt): Store correct destination register.
1679
4a0bd876
CD		 16802002-03-03 Chris Demetriou <cgd@broadcom.com>
1681
1682 * mips.igen: Remove whitespace at end of lines.
1683
09297648
CD		 16842002-03-02 Chris Demetriou <cgd@broadcom.com>
1685
1686 * mips.igen (loadstore_ea): New function to do effective
1687 address calculations.
1688 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
1689 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
1690 CACHE): Use loadstore_ea to do effective address computations.
1691
043b7057
CD		 16922002-03-02 Chris Demetriou <cgd@broadcom.com>
1693
1694 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
1695 * mips.igen (LL, CxC1, MxC1): Likewise.
1696
c1e8ada4
CD		 16972002-03-02 Chris Demetriou <cgd@broadcom.com>
1698
1699 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
1700 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
1701 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
1702 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
1703 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
1704 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
1705 Don't split opcode fields by hand, use the opcode field values
1706 provided by igen.
1707
3e1dca16
CD		 17082002-03-01 Chris Demetriou <cgd@broadcom.com>
1709
1710 * mips.igen (do_divu): Fix spacing.
1711
1712 * mips.igen (do_dsllv): Move to be right before DSLLV,
1713 to match the rest of the do_<shift> functions.
1714
fff8d27d
CD		 17152002-03-01 Chris Demetriou <cgd@broadcom.com>
1716
1717 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
1718 DSRL32, do_dsrlv): Trace inputs and results.
1719
0d3e762b
CD		 17202002-03-01 Chris Demetriou <cgd@broadcom.com>
1721
1722 * mips.igen (CACHE): Provide instruction-printing string.
1723
1724 * interp.c (signal_exception): Comment tokens after #endif.
1725
eb5fcf93
CD		 17262002-02-28 Chris Demetriou <cgd@broadcom.com>
1727
1728 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
72f4393d
L		 1729 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
1730 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
1731 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
1732 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
1733 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
1734 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
eb5fcf93
CD		 1735 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
1736
bb22bd7d
CD		 17372002-02-28 Chris Demetriou <cgd@broadcom.com>
1738
1739 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
1740 instruction-printing string.
1741 (LWU): Use '64' as the filter flag.
1742
91a177cf
CD		 17432002-02-28 Chris Demetriou <cgd@broadcom.com>
1744
1745 * mips.igen (SDXC1): Fix instruction-printing string.
1746
387f484a
CD		 17472002-02-28 Chris Demetriou <cgd@broadcom.com>
1748
1749 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
1750 filter flags "32,f".
1751
3d81f391
CD		 17522002-02-27 Chris Demetriou <cgd@broadcom.com>
1753
1754 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1755 as the filter flag.
1756
af5107af
CD		 17572002-02-27 Chris Demetriou <cgd@broadcom.com>
1758
1759 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1760 add a comma) so that it more closely match the MIPS ISA
1761 documentation opcode partitioning.
1762 (PREF): Put useful names on opcode fields, and include
1763 instruction-printing string.
1764
ca971540
CD		 17652002-02-27 Chris Demetriou <cgd@broadcom.com>
1766
1767 * mips.igen (check_u64): New function which in the future will
1768 check whether 64-bit instructions are usable and signal an
1769 exception if not. Currently a no-op.
1770 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1771 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1772 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1773 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1774
1775 * mips.igen (check_fpu): New function which in the future will
1776 check whether FPU instructions are usable and signal an exception
1777 if not. Currently a no-op.
1778 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1779 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1780 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1781 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1782 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1783 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1784 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1785 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1786
1c47a468
CD		 17872002-02-27 Chris Demetriou <cgd@broadcom.com>
1788
1789 * mips.igen (do_load_left, do_load_right): Move to be immediately
1790 following do_load.
1791 (do_store_left, do_store_right): Move to be immediately following
1792 do_store.
1793
603a98e7
CD		 17942002-02-27 Chris Demetriou <cgd@broadcom.com>
1795
1796 * mips.igen (mipsV): New model name. Also, add it to
1797 all instructions and functions where it is appropriate.
1798
c5d00cc7
CD		 17992002-02-18 Chris Demetriou <cgd@broadcom.com>
1800
1801 * mips.igen: For all functions and instructions, list model
1802 names that support that instruction one per line.
1803
074e9cb8
CD		 18042002-02-11 Chris Demetriou <cgd@broadcom.com>
1805
1806 * mips.igen: Add some additional comments about supported
1807 models, and about which instructions go where.
1808 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1809 order as is used in the rest of the file.
1810
9805e229
CD		 18112002-02-11 Chris Demetriou <cgd@broadcom.com>
1812
1813 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1814 indicating that ALU32_END or ALU64_END are there to check
1815 for overflow.
1816 (DADD): Likewise, but also remove previous comment about
1817 overflow checking.
1818
f701dad2
CD		 18192002-02-10 Chris Demetriou <cgd@broadcom.com>
1820
1821 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1822 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1823 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1824 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1825 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1826 fields (i.e., add and move commas) so that they more closely
1827 match the MIPS ISA documentation opcode partitioning.
1828
18292002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098 1830
72f4393d
L		 1831 * mips.igen (ADDI): Print immediate value.
1832 (BREAK): Print code.
1833 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1834 (SLL): Print "nop" specially, and don't run the code
1835 that does the shift for the "nop" case.
20ae0098 1836
9e52972e
FF		 18372001-11-17 Fred Fish <fnf@redhat.com>
1838
1839 * sim-main.h (float_operation): Move enum declaration outside
1840 of _sim_cpu struct declaration.
1841
c0efbca4
JB		 18422001-04-12 Jim Blandy <jimb@redhat.com>
1843
1844 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1845 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1846 set of the FCSR.
1847 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1848 PENDING_FILL, and you can get the intended effect gracefully by
1849 calling PENDING_SCHED directly.
1850
fb891446
BE		 18512001-02-23 Ben Elliston <bje@redhat.com>
1852
1853 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1854 already defined elsewhere.
1855
8030f857
BE		 18562001-02-19 Ben Elliston <bje@redhat.com>
1857
1858 * sim-main.h (sim_monitor): Return an int.
1859 * interp.c (sim_monitor): Add return values.
1860 (signal_exception): Handle error conditions from sim_monitor.
1861
56b48a7a
CD		 18622001-02-08 Ben Elliston <bje@redhat.com>
1863
1864 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1865 (store_memory): Likewise, pass cia to sim_core_write*.
1866
d3ee60d9
FCE		 18672000-10-19 Frank Ch. Eigler <fche@redhat.com>
1868
1869 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1870 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1871
071da002
AC		 1872Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1873
1874 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1875 * Makefile.in: Don't delete *.igen when cleaning directory.
1876
a28c02cd
AC		 1877Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1878
1879 * m16.igen (break): Call SignalException not sim_engine_halt.
1880
80ee11fa
AC		 1881Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1882
1883 From Jason Eckhardt:
1884 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1885
673388c0
AC		 1886Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1887
1888 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1889
4c0deff4
NC		 18902000-05-24 Michael Hayes <mhayes@cygnus.com>
1891
1892 * mips.igen (do_dmultx): Fix typo.
1893
eb2d80b4
AC		 1894Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1895
1896 * configure: Regenerated to track ../common/aclocal.m4 changes.
1897
dd37a34b
AC		 1898Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1899
1900 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1901
4c0deff4
NC		 19022000-04-12 Frank Ch. Eigler <fche@redhat.com>
1903
1904 * sim-main.h (GPR_CLEAR): Define macro.
1905
e30db738
AC		 1906Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1907
1908 * interp.c (decode_coproc): Output long using %lx and not %s.
1909
cb7450ea
FCE		 19102000-03-21 Frank Ch. Eigler <fche@redhat.com>
1911
1912 * interp.c (sim_open): Sort & extend dummy memory regions for
1913 --board=jmr3904 for eCos.
1914
a3027dd7
FCE		 19152000-03-02 Frank Ch. Eigler <fche@redhat.com>
1916
1917 * configure: Regenerated.
1918
1919Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1920
1921 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1922 calls, conditional on the simulator being in verbose mode.
1923
dfcd3bfb
JM		 1924Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1925
1926 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1927 cache don't get ReservedInstruction traps.
1928
c2d11a7d
JM		 19291999-11-29 Mark Salter <msalter@cygnus.com>
1930
1931 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1932 to clear status bits in sdisr register. This is how the hardware works.
1933
1934 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1935 being used by cygmon.
1936
4ce44c66
JM		 19371999-11-11 Andrew Haley <aph@cygnus.com>
1938
1939 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1940 instructions.
1941
cff3e48b
JM		 1942Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1943
1944 * mips.igen (MULT): Correct previous mis-applied patch.
1945
d4f3574e
SS		 1946Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1947
1948 * mips.igen (delayslot32): Handle sequence like
1949 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1950 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1951 (MULT): Actually pass the third register...
1952
19531999-09-03 Mark Salter <msalter@cygnus.com>
1954
1955 * interp.c (sim_open): Added more memory aliases for additional
1956 hardware being touched by cygmon on jmr3904 board.
1957
1958Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1959
1960 * configure: Regenerated to track ../common/aclocal.m4 changes.
1961
a0b3c4fd
JM		 1962Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1963
1964 * interp.c (sim_store_register): Handle case where client - GDB -
1965 specifies that a 4 byte register is 8 bytes in size.
1966 (sim_fetch_register): Ditto.
72f4393d 1967
adf40b2e
JM		 19681999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1969
1970 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1971 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1972 (idt_monitor_base): Base address for IDT monitor traps.
1973 (pmon_monitor_base): Ditto for PMON.
1974 (lsipmon_monitor_base): Ditto for LSI PMON.
1975 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1976 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1977 (sim_firmware_command): New function.
1978 (mips_option_handler): Call it for OPTION_FIRMWARE.
1979 (sim_open): Allocate memory for idt_monitor region. If "--board"
1980 option was given, add no monitor by default. Add BREAK hooks only if
1981 monitors are also there.
72f4393d 1982
43e526b9
JM		 1983Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1984
1985 * interp.c (sim_monitor): Flush output before reading input.
1986
1987Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1988
1989 * tconfig.in (SIM_HANDLES_LMA): Always define.
1990
1991Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1992
1993 From Mark Salter <msalter@cygnus.com>:
1994 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1995 (sim_open): Add setup for BSP board.
1996
9846de1b
JM		 1997Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1998
1999 * mips.igen (MULT, MULTU): Add syntax for two operand version.
2000 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
2001 them as unimplemented.
2002
cd0fc7c3
SS		 20031999-05-08 Felix Lee <flee@cygnus.com>
2004
2005 * configure: Regenerated to track ../common/aclocal.m4 changes.
72f4393d 2006
7a292a7a
SS		 20071999-04-21 Frank Ch. Eigler <fche@cygnus.com>
2008
2009 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
2010
2011Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
2012
2013 * configure.in: Any mips64vr5*-*-* target should have
2014 -DTARGET_ENABLE_FR=1.
2015 (default_endian): Any mips64vr*el-*-* target should default to
2016 LITTLE_ENDIAN.
2017 * configure: Re-generate.
2018
20191999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
2020
2021 * mips.igen (ldl): Extend from _16_, not 32.
2022
2023Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
2024
2025 * interp.c (sim_store_register): Force registers written to by GDB
2026 into an un-interpreted state.
2027
c906108c
SS		 20281999-02-05 Frank Ch. Eigler <fche@cygnus.com>
2029
2030 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
2031 CPU, start periodic background I/O polls.
72f4393d 2032 (tx3904sio_poll): New function: periodic I/O poller.
c906108c
SS		 2033
20341998-12-30 Frank Ch. Eigler <fche@cygnus.com>
2035
2036 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
72f4393d 2037
c906108c
SS		 2038Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
2039
2040 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
2041 case statement.
2042
20431998-12-29 Frank Ch. Eigler <fche@cygnus.com>
72f4393d
L		 2044
2045 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
c906108c
SS		 2046 (load_word): Call SIM_CORE_SIGNAL hook on error.
2047 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
2048 starting. For exception dispatching, pass PC instead of NULL_CIA.
2049 (decode_coproc): Use COP0_BADVADDR to store faulting address.
72f4393d 2050 * sim-main.h (COP0_BADVADDR): Define.
c906108c
SS		 2051 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
2052 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
72f4393d 2053 (_sim_cpu): Add exc_* fields to store register value snapshots.
c906108c
SS		 2054 * mips.igen (*): Replace memory-related SignalException* calls
2055 with references to SIM_CORE_SIGNAL hook.
72f4393d 2056
c906108c
SS		 2057 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
2058 fix.
2059 * sim-main.c (*): Minor warning cleanups.
72f4393d 2060
c906108c
SS		 20611998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
2062
2063 * m16.igen (DADDIU5): Correct type-o.
2064
2065Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
2066
2067 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
2068 variables.
2069
2070Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
2071
2072 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
2073 to include path.
2074 (interp.o): Add dependency on itable.h
2075 (oengine.c, gencode): Delete remaining references.
2076 (BUILT_SRC_FROM_GEN): Clean up.
72f4393d 2077
c906108c 20781998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
72f4393d 2079
c906108c
SS		 2080 * vr4run.c: New.
2081 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
2082 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
2083 tmp-run-hack) : New.
2084 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
72f4393d 2085 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
c906108c
SS		 2086 Drop the "64" qualifier to get the HACK generator working.
2087 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
2088 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
2089 qualifier to get the hack generator working.
2090 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
2091 (DSLL): Use do_dsll.
2092 (DSLLV): Use do_dsllv.
2093 (DSRA): Use do_dsra.
2094 (DSRL): Use do_dsrl.
2095 (DSRLV): Use do_dsrlv.
2096 (BC1): Move *vr4100 to get the HACK generator working.
72f4393d 2097 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
c906108c
SS		 2098 get the HACK generator working.
2099 (MACC) Rename to get the HACK generator working.
2100 (DMACC,MACCS,DMACCS): Add the 64.
72f4393d 2101
c906108c
SS		 21021998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
2103
2104 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
2105 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
72f4393d 2106
c906108c
SS		 21071998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
2108
2109 * mips/interp.c (DEBUG): Cleanups.
2110
21111998-12-10 Frank Ch. Eigler <fche@cygnus.com>
2112
2113 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
2114 (tx3904sio_tickle): fflush after a stdout character output.
72f4393d 2115
c906108c
SS		 21161998-12-03 Frank Ch. Eigler <fche@cygnus.com>
2117
2118 * interp.c (sim_close): Uninstall modules.
2119
2120Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
2121
2122 * sim-main.h, interp.c (sim_monitor): Change to global
2123 function.
2124
2125Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2126
2127 * configure.in (vr4100): Only include vr4100 instructions in
2128 simulator.
2129 * configure: Re-generate.
2130 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
2131
2132Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
2133
2134 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
2135 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
2136 true alternative.
2137
2138 * configure.in (sim_default_gen, sim_use_gen): Replace with
2139 sim_gen.
2140 (--enable-sim-igen): Delete config option. Always using IGEN.
2141 * configure: Re-generate.
72f4393d 2142
c906108c
SS		 2143 * Makefile.in (gencode): Kill, kill, kill.
2144 * gencode.c: Ditto.
72f4393d 2145
c906108c
SS		 2146Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
2147
2148 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
2149 bit mips16 igen simulator.
2150 * configure: Re-generate.
2151
2152 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
2153 as part of vr4100 ISA.
2154 * vr.igen: Mark all instructions as 64 bit only.
2155
2156Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2157
2158 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
2159 Pacify GCC.
2160
2161Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
2162
2163 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
2164 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
2165 * configure: Re-generate.
2166
2167 * m16.igen (BREAK): Define breakpoint instruction.
2168 (JALX32): Mark instruction as mips16 and not r3900.
2169 * mips.igen (C.cond.fmt): Fix typo in instruction format.
2170
2171 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
2172
2173Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
2174
2175 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
2176 insn as a debug breakpoint.
2177
2178 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
2179 pending.slot_size.
2180 (PENDING_SCHED): Clean up trace statement.
2181 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
2182 (PENDING_FILL): Delay write by only one cycle.
2183 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
2184
2185 * sim-main.c (pending_tick): Clean up trace statements. Add trace
2186 of pending writes.
2187 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
2188 32 & 64.
2189 (pending_tick): Move incrementing of index to FOR statement.
2190 (pending_tick): Only update PENDING_OUT after a write has occured.
72f4393d 2191
c906108c
SS		 2192 * configure.in: Add explicit mips-lsi-* target. Use gencode to
2193 build simulator.
2194 * configure: Re-generate.
72f4393d 2195
c906108c
SS		 2196 * interp.c (sim_engine_run OLD): Delete explicit call to
2197 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
72f4393d 2198
c906108c
SS		 2199Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
2200
2201 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
2202 interrupt level number to match changed SignalExceptionInterrupt
2203 macro.
2204
2205Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
2206
2207 * interp.c: #include "itable.h" if WITH_IGEN.
2208 (get_insn_name): New function.
2209 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
2210 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
2211
2212Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
2213
2214 * configure: Rebuilt to inhale new common/aclocal.m4.
2215
2216Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
2217
2218 * dv-tx3904sio.c: Include sim-assert.h.
2219
2220Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
2221
2222 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
2223 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
2224 Reorganize target-specific sim-hardware checks.
2225 * configure: rebuilt.
2226 * interp.c (sim_open): For tx39 target boards, set
2227 OPERATING_ENVIRONMENT, add tx3904sio devices.
2228 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
2229 ROM executables. Install dv-sockser into sim-modules list.
72f4393d 2230
c906108c
SS		 2231 * dv-tx3904irc.c: Compiler warning clean-up.
2232 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
2233 frequent hw-trace messages.
2234
2235Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
2236
2237 * vr.igen (MulAcc): Identify as a vr4100 specific function.
2238
2239Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2240
2241 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
2242
2243 * vr.igen: New file.
2244 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
2245 * mips.igen: Define vr4100 model. Include vr.igen.
2246Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
2247
2248 * mips.igen (check_mf_hilo): Correct check.
2249
2250Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2251
2252 * sim-main.h (interrupt_event): Add prototype.
2253
2254 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
2255 register_ptr, register_value.
2256 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
2257
2258 * sim-main.h (tracefh): Make extern.
2259
2260Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
2261
2262 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
72f4393d 2263 Reduce unnecessarily high timer event frequency.
c906108c 2264 * dv-tx3904cpu.c: Ditto for interrupt event.
72f4393d 2265
c906108c
SS		 2266Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
2267
2268 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
2269 to allay warnings.
2270 (interrupt_event): Made non-static.
72f4393d 2271
c906108c
SS		 2272 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
2273 interchange of configuration values for external vs. internal
2274 clock dividers.
72f4393d 2275
c906108c
SS		 2276Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
2277
72f4393d 2278 * mips.igen (BREAK): Moved code to here for
c906108c
SS		 2279 simulator-reserved break instructions.
2280 * gencode.c (build_instruction): Ditto.
2281 * interp.c (signal_exception): Code moved from here. Non-
72f4393d 2282 reserved instructions now use exception vector, rather
c906108c
SS		 2283 than halting sim.
2284 * sim-main.h: Moved magic constants to here.
2285
2286Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
2287
2288 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
2289 register upon non-zero interrupt event level, clear upon zero
2290 event value.
2291 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
2292 by passing zero event value.
2293 (*_io_{read,write}_buffer): Endianness fixes.
2294 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
2295 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
2296
2297 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
2298 serial I/O and timer module at base address 0xFFFF0000.
72f4393d 2299
c906108c
SS		 2300Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
2301
72f4393d 2302 * mips.igen (SWC1) : Correct the handling of ReverseEndian
c906108c
SS		 2303 and BigEndianCPU.
2304
2305Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
2306
2307 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
2308 parts.
2309 * configure: Update.
2310
2311Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
2312
2313 * dv-tx3904tmr.c: New file - implements tx3904 timer.
2314 * dv-tx3904{irc,cpu}.c: Mild reformatting.
2315 * configure.in: Include tx3904tmr in hw_device list.
2316 * configure: Rebuilt.
2317 * interp.c (sim_open): Instantiate three timer instances.
2318 Fix address typo of tx3904irc instance.
2319
2320Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
2321
2322 * interp.c (signal_exception): SystemCall exception now uses
2323 the exception vector.
2324
2325Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
2326
2327 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
2328 to allay warnings.
2329
2330Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2331
2332 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
2333
2334Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
2335
2336 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
2337
2338 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
2339 sim-main.h. Declare a struct hw_descriptor instead of struct
2340 hw_device_descriptor.
2341
2342Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
2343
2344 * mips.igen (do_store_left, do_load_left): Compute nr of left and
2345 right bits and then re-align left hand bytes to correct byte
2346 lanes. Fix incorrect computation in do_store_left when loading
2347 bytes from second word.
2348
2349Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2350
2351 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
2352 * interp.c (sim_open): Only create a device tree when HW is
2353 enabled.
2354
2355 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
2356 * interp.c (signal_exception): Ditto.
2357
2358Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
2359
2360 * gencode.c: Mark BEGEZALL as LIKELY.
2361
2362Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
2363
2364 * sim-main.h (ALU32_END): Sign extend 32 bit results.
2365 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
72f4393d 2366
c906108c
SS		 2367Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
2368
2369 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
2370 modules. Recognize TX39 target with "mips*tx39" pattern.
2371 * configure: Rebuilt.
2372 * sim-main.h (*): Added many macros defining bits in
2373 TX39 control registers.
2374 (SignalInterrupt): Send actual PC instead of NULL.
2375 (SignalNMIReset): New exception type.
2376 * interp.c (board): New variable for future use to identify
2377 a particular board being simulated.
2378 (mips_option_handler,mips_options): Added "--board" option.
2379 (interrupt_event): Send actual PC.
2380 (sim_open): Make memory layout conditional on board setting.
2381 (signal_exception): Initial implementation of hardware interrupt
2382 handling. Accept another break instruction variant for simulator
2383 exit.
2384 (decode_coproc): Implement RFE instruction for TX39.
2385 (mips.igen): Decode RFE instruction as such.
2386 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
2387 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
2388 bbegin to implement memory map.
2389 * dv-tx3904cpu.c: New file.
2390 * dv-tx3904irc.c: New file.
2391
2392Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
2393
2394 * mips.igen (check_mt_hilo): Create a separate r3900 version.
2395
2396Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
2397
2398 * tx.igen (madd,maddu): Replace calls to check_op_hilo
2399 with calls to check_div_hilo.
2400
2401Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
2402
2403 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
2404 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
72f4393d 2405 Add special r3900 version of do_mult_hilo.
c906108c
SS		 2406 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
2407 with calls to check_mult_hilo.
2408 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
2409 with calls to check_div_hilo.
2410
2411Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
2412
2413 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
2414 Document a replacement.
2415
2416Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
2417
2418 * interp.c (sim_monitor): Make mon_printf work.
2419
2420Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
2421
2422 * sim-main.h (INSN_NAME): New arg `cpu'.
2423
2424Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
2425
72f4393d 2426 * configure: Regenerated to track ../common/aclocal.m4 changes.
c906108c
SS		 2427
2428Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
2429
2430 * configure: Regenerated to track ../common/aclocal.m4 changes.
2431 * config.in: Ditto.
2432
2433Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
2434
2435 * acconfig.h: New file.
2436 * configure.in: Reverted change of Apr 24; use sinclude again.
2437
2438Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
2439
2440 * configure: Regenerated to track ../common/aclocal.m4 changes.
2441 * config.in: Ditto.
2442
2443Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
2444
2445 * configure.in: Don't call sinclude.
2446
2447Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
2448
2449 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
2450
2451Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2452
2453 * mips.igen (ERET): Implement.
2454
2455 * interp.c (decode_coproc): Return sign-extended EPC.
2456
2457 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
2458
2459 * interp.c (signal_exception): Do not ignore Trap.
2460 (signal_exception): On TRAP, restart at exception address.
2461 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
2462 (signal_exception): Update.
2463 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
2464 so that TRAP instructions are caught.
2465
2466Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
2467
2468 * sim-main.h (struct hilo_access, struct hilo_history): Define,
2469 contains HI/LO access history.
2470 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
2471 (HIACCESS, LOACCESS): Delete, replace with
2472 (HIHISTORY, LOHISTORY): New macros.
2473 (CHECKHILO): Delete all, moved to mips.igen
72f4393d 2474
c906108c
SS		 2475 * gencode.c (build_instruction): Do not generate checks for
2476 correct HI/LO register usage.
2477
2478 * interp.c (old_engine_run): Delete checks for correct HI/LO
2479 register usage.
2480
2481 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
2482 check_mf_cycles): New functions.
2483 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
2484 do_divu, domultx, do_mult, do_multu): Use.
2485
2486 * tx.igen ("madd", "maddu"): Use.
72f4393d 2487
c906108c
SS		 2488Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
2489
2490 * mips.igen (DSRAV): Use function do_dsrav.
2491 (SRAV): Use new function do_srav.
2492
2493 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
2494 (B): Sign extend 11 bit immediate.
2495 (EXT-B*): Shift 16 bit immediate left by 1.
2496 (ADDIU*): Don't sign extend immediate value.
2497
2498Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2499
2500 * m16run.c (sim_engine_run): Restore CIA after handling an event.
2501
2502 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
2503 functions.
2504
2505 * mips.igen (delayslot32, nullify_next_insn): New functions.
2506 (m16.igen): Always include.
2507 (do_*): Add more tracing.
2508
2509 * m16.igen (delayslot16): Add NIA argument, could be called by a
2510 32 bit MIPS16 instruction.
72f4393d 2511
c906108c
SS		 2512 * interp.c (ifetch16): Move function from here.
2513 * sim-main.c (ifetch16): To here.
72f4393d 2514
c906108c
SS		 2515 * sim-main.c (ifetch16, ifetch32): Update to match current
2516 implementations of LH, LW.
2517 (signal_exception): Don't print out incorrect hex value of illegal
2518 instruction.
2519
2520Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2521
2522 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
2523 instruction.
2524
2525 * m16.igen: Implement MIPS16 instructions.
72f4393d 2526
c906108c
SS		 2527 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
2528 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
2529 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
2530 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
2531 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
2532 bodies of corresponding code from 32 bit insn to these. Also used
2533 by MIPS16 versions of functions.
72f4393d 2534
c906108c
SS		 2535 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
2536 (IMEM16): Drop NR argument from macro.
2537
2538Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2539
2540 * Makefile.in (SIM_OBJS): Add sim-main.o.
2541
2542 * sim-main.h (address_translation, load_memory, store_memory,
2543 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
2544 as INLINE_SIM_MAIN.
2545 (pr_addr, pr_uword64): Declare.
2546 (sim-main.c): Include when H_REVEALS_MODULE_P.
72f4393d 2547
c906108c
SS		 2548 * interp.c (address_translation, load_memory, store_memory,
2549 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
2550 from here.
2551 * sim-main.c: To here. Fix compilation problems.
72f4393d 2552
c906108c
SS		 2553 * configure.in: Enable inlining.
2554 * configure: Re-config.
2555
2556Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2557
2558 * configure: Regenerated to track ../common/aclocal.m4 changes.
2559
2560Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2561
2562 * mips.igen: Include tx.igen.
2563 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
2564 * tx.igen: New file, contains MADD and MADDU.
2565
2566 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
2567 the hardwired constant `7'.
2568 (store_memory): Ditto.
2569 (LOADDRMASK): Move definition to sim-main.h.
2570
2571 mips.igen (MTC0): Enable for r3900.
2572 (ADDU): Add trace.
2573
2574 mips.igen (do_load_byte): Delete.
2575 (do_load, do_store, do_load_left, do_load_write, do_store_left,
2576 do_store_right): New functions.
2577 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
2578
2579 configure.in: Let the tx39 use igen again.
2580 configure: Update.
72f4393d 2581
c906108c
SS		 2582Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2583
2584 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
2585 not an address sized quantity. Return zero for cache sizes.
2586
2587Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
2588
2589 * mips.igen (r3900): r3900 does not support 64 bit integer
2590 operations.
2591
2592Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
2593
2594 * configure.in (mipstx39*-*-*): Use gencode simulator rather
2595 than igen one.
2596 * configure : Rebuild.
72f4393d 2597
c906108c
SS		 2598Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
2599
2600 * configure: Regenerated to track ../common/aclocal.m4 changes.
2601
2602Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2603
2604 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
2605
2606Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
2607
2608 * configure: Regenerated to track ../common/aclocal.m4 changes.
2609 * config.in: Regenerated to track ../common/aclocal.m4 changes.
2610
2611Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2612
2613 * configure: Regenerated to track ../common/aclocal.m4 changes.
2614
2615Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
2616
2617 * interp.c (Max, Min): Comment out functions. Not yet used.
2618
2619Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
2620
2621 * configure: Regenerated to track ../common/aclocal.m4 changes.
2622
2623Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
2624
2625 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
2626 configurable settings for stand-alone simulator.
72f4393d 2627
c906108c 2628 * configure.in: Added X11 search, just in case.
72f4393d 2629
c906108c
SS		 2630 * configure: Regenerated.
2631
2632Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
2633
2634 * interp.c (sim_write, sim_read, load_memory, store_memory):
2635 Replace sim_core_*_map with read_map, write_map, exec_map resp.
2636
2637Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
2638
2639 * sim-main.h (GETFCC): Return an unsigned value.
2640
2641Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2642
2643 * mips.igen (DIV): Fix check for -1 / MIN_INT.
2644 (DADD): Result destination is RD not RT.
2645
2646Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2647
2648 * sim-main.h (HIACCESS, LOACCESS): Always define.
2649
2650 * mdmx.igen (Maxi, Mini): Rename Max, Min.
2651
2652 * interp.c (sim_info): Delete.
2653
2654Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
2655
2656 * interp.c (DECLARE_OPTION_HANDLER): Use it.
2657 (mips_option_handler): New argument `cpu'.
2658 (sim_open): Update call to sim_add_option_table.
2659
2660Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
2661
2662 * mips.igen (CxC1): Add tracing.
2663
2664Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
2665
2666 * sim-main.h (Max, Min): Declare.
2667
2668 * interp.c (Max, Min): New functions.
2669
2670 * mips.igen (BC1): Add tracing.
72f4393d 2671
c906108c 2672Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
72f4393d 2673
c906108c 2674 * interp.c Added memory map for stack in vr4100
72f4393d 2675
c906108c
SS		 2676Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
2677
2678 * interp.c (load_memory): Add missing "break"'s.
2679
2680Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2681
2682 * interp.c (sim_store_register, sim_fetch_register): Pass in
2683 length parameter. Return -1.
2684
2685Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
2686
2687 * interp.c: Added hardware init hook, fixed warnings.
2688
2689Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2690
2691 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
2692
2693Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
2694
2695 * interp.c (ifetch16): New function.
2696
2697 * sim-main.h (IMEM32): Rename IMEM.
2698 (IMEM16_IMMED): Define.
2699 (IMEM16): Define.
2700 (DELAY_SLOT): Update.
72f4393d 2701
c906108c 2702 * m16run.c (sim_engine_run): New file.
72f4393d 2703
c906108c
SS		 2704 * m16.igen: All instructions except LB.
2705 (LB): Call do_load_byte.
2706 * mips.igen (do_load_byte): New function.
2707 (LB): Call do_load_byte.
2708
2709 * mips.igen: Move spec for insn bit size and high bit from here.
2710 * Makefile.in (tmp-igen, tmp-m16): To here.
2711
2712 * m16.dc: New file, decode mips16 instructions.
2713
2714 * Makefile.in (SIM_NO_ALL): Define.
2715 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
2716
2717Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
2718
2719 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
2720 point unit to 32 bit registers.
2721 * configure: Re-generate.
2722
2723Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2724
2725 * configure.in (sim_use_gen): Make IGEN the default simulator
2726 generator for generic 32 and 64 bit mips targets.
2727 * configure: Re-generate.
2728
2729Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2730
2731 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
2732 bitsize.
2733
2734 * interp.c (sim_fetch_register, sim_store_register): Read/write
2735 FGR from correct location.
2736 (sim_open): Set size of FGR's according to
2737 WITH_TARGET_FLOATING_POINT_BITSIZE.
72f4393d 2738
c906108c
SS		 2739 * sim-main.h (FGR): Store floating point registers in a separate
2740 array.
2741
2742Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
2743
2744 * configure: Regenerated to track ../common/aclocal.m4 changes.
2745
2746Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2747
2748 * interp.c (ColdReset): Call PENDING_INVALIDATE.
2749
2750 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
2751
2752 * interp.c (pending_tick): New function. Deliver pending writes.
2753
2754 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2755 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2756 it can handle mixed sized quantites and single bits.
72f4393d 2757
c906108c
SS		 2758Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2759
2760 * interp.c (oengine.h): Do not include when building with IGEN.
2761 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2762 (sim_info): Ditto for PROCESSOR_64BIT.
2763 (sim_monitor): Replace ut_reg with unsigned_word.
2764 (*): Ditto for t_reg.
2765 (LOADDRMASK): Define.
2766 (sim_open): Remove defunct check that host FP is IEEE compliant,
2767 using software to emulate floating point.
2768 (value_fpr, ...): Always compile, was conditional on HASFPU.
2769
2770Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2771
2772 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2773 size.
2774
2775 * interp.c (SD, CPU): Define.
2776 (mips_option_handler): Set flags in each CPU.
2777 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2778 (sim_close): Do not clear STATE, deleted anyway.
2779 (sim_write, sim_read): Assume CPU zero's vm should be used for
2780 data transfers.
2781 (sim_create_inferior): Set the PC for all processors.
2782 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2783 argument.
2784 (mips16_entry): Pass correct nr of args to store_word, load_word.
2785 (ColdReset): Cold reset all cpu's.
2786 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2787 (sim_monitor, load_memory, store_memory, signal_exception): Use
2788 `CPU' instead of STATE_CPU.
2789
2790
2791 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2792 SD or CPU_.
72f4393d 2793
c906108c
SS		 2794 * sim-main.h (signal_exception): Add sim_cpu arg.
2795 (SignalException*): Pass both SD and CPU to signal_exception.
2796 * interp.c (signal_exception): Update.
72f4393d 2797
c906108c
SS		 2798 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2799 Ditto
2800 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2801 address_translation): Ditto
2802 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
72f4393d 2803
c906108c
SS		 2804Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2805
2806 * configure: Regenerated to track ../common/aclocal.m4 changes.
2807
2808Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2809
2810 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2811
72f4393d 2812 * mips.igen (model): Map processor names onto BFD name.
c906108c
SS		 2813
2814 * sim-main.h (CPU_CIA): Delete.
2815 (SET_CIA, GET_CIA): Define
2816
2817Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2818
2819 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2820 regiser.
2821
2822 * configure.in (default_endian): Configure a big-endian simulator
2823 by default.
2824 * configure: Re-generate.
72f4393d 2825
c906108c
SS		 2826Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2827
2828 * configure: Regenerated to track ../common/aclocal.m4 changes.
2829
2830Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2831
2832 * interp.c (sim_monitor): Handle Densan monitor outbyte
2833 and inbyte functions.
2834
28351997-12-29 Felix Lee <flee@cygnus.com>
2836
2837 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2838
2839Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2840
2841 * Makefile.in (tmp-igen): Arrange for $zero to always be
2842 reset to zero after every instruction.
2843
2844Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2845
2846 * configure: Regenerated to track ../common/aclocal.m4 changes.
2847 * config.in: Ditto.
2848
2849Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2850
2851 * mips.igen (MSUB): Fix to work like MADD.
2852 * gencode.c (MSUB): Similarly.
2853
2854Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2855
2856 * configure: Regenerated to track ../common/aclocal.m4 changes.
2857
2858Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2859
2860 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2861
2862Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2863
2864 * sim-main.h (sim-fpu.h): Include.
2865
2866 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2867 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2868 using host independant sim_fpu module.
2869
2870Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2871
2872 * interp.c (signal_exception): Report internal errors with SIGABRT
2873 not SIGQUIT.
2874
2875 * sim-main.h (C0_CONFIG): New register.
2876 (signal.h): No longer include.
2877
2878 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2879
2880Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2881
2882 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2883
2884Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2885
2886 * mips.igen: Tag vr5000 instructions.
2887 (ANDI): Was missing mipsIV model, fix assembler syntax.
2888 (do_c_cond_fmt): New function.
2889 (C.cond.fmt): Handle mips I-III which do not support CC field
2890 separatly.
2891 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2892 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2893 in IV3.2 spec.
2894 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2895 vr5000 which saves LO in a GPR separatly.
72f4393d 2896
c906108c
SS		 2897 * configure.in (enable-sim-igen): For vr5000, select vr5000
2898 specific instructions.
2899 * configure: Re-generate.
72f4393d 2900
c906108c
SS		 2901Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2902
2903 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2904
2905 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2906 fmt_uninterpreted_64 bit cases to switch. Convert to
2907 fmt_formatted,
2908
2909 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2910
2911 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2912 as specified in IV3.2 spec.
2913 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2914
2915Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2916
2917 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2918 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2919 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2920 PENDING_FILL versions of instructions. Simplify.
2921 (X): New function.
2922 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2923 instructions.
2924 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2925 a signed value.
2926 (MTHI, MFHI): Disable code checking HI-LO.
72f4393d 2927
c906108c
SS		 2928 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2929 global.
2930 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2931
2932Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2933
2934 * gencode.c (build_mips16_operands): Replace IPC with cia.
2935
2936 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2937 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2938 IPC to `cia'.
2939 (UndefinedResult): Replace function with macro/function
2940 combination.
2941 (sim_engine_run): Don't save PC in IPC.
2942
2943 * sim-main.h (IPC): Delete.
2944
2945
2946 * interp.c (signal_exception, store_word, load_word,
2947 address_translation, load_memory, store_memory, cache_op,
2948 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2949 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2950 current instruction address - cia - argument.
2951 (sim_read, sim_write): Call address_translation directly.
2952 (sim_engine_run): Rename variable vaddr to cia.
2953 (signal_exception): Pass cia to sim_monitor
72f4393d 2954
c906108c
SS		 2955 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2956 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2957 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2958
2959 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2960 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2961 SIM_ASSERT.
72f4393d 2962
c906108c
SS		 2963 * interp.c (signal_exception): Pass restart address to
2964 sim_engine_restart.
2965
2966 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2967 idecode.o): Add dependency.
2968
2969 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2970 Delete definitions
2971 (DELAY_SLOT): Update NIA not PC with branch address.
2972 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2973
2974 * mips.igen: Use CIA not PC in branch calculations.
2975 (illegal): Call SignalException.
2976 (BEQ, ADDIU): Fix assembler.
2977
2978Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2979
2980 * m16.igen (JALX): Was missing.
2981
2982 * configure.in (enable-sim-igen): New configuration option.
2983 * configure: Re-generate.
72f4393d 2984
c906108c
SS		 2985 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2986
2987 * interp.c (load_memory, store_memory): Delete parameter RAW.
2988 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2989 bypassing {load,store}_memory.
2990
2991 * sim-main.h (ByteSwapMem): Delete definition.
2992
2993 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2994
2995 * interp.c (sim_do_command, sim_commands): Delete mips specific
2996 commands. Handled by module sim-options.
72f4393d 2997
c906108c
SS		 2998 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2999 (WITH_MODULO_MEMORY): Define.
3000
3001 * interp.c (sim_info): Delete code printing memory size.
3002
3003 * interp.c (mips_size): Nee sim_size, delete function.
3004 (power2): Delete.
3005 (monitor, monitor_base, monitor_size): Delete global variables.
3006 (sim_open, sim_close): Delete code creating monitor and other
3007 memory regions. Use sim-memopts module, via sim_do_commandf, to
3008 manage memory regions.
3009 (load_memory, store_memory): Use sim-core for memory model.
72f4393d 3010
c906108c
SS		 3011 * interp.c (address_translation): Delete all memory map code
3012 except line forcing 32 bit addresses.
3013
3014Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
3015
3016 * sim-main.h (WITH_TRACE): Delete definition. Enables common
3017 trace options.
3018
3019 * interp.c (logfh, logfile): Delete globals.
3020 (sim_open, sim_close): Delete code opening & closing log file.
3021 (mips_option_handler): Delete -l and -n options.
3022 (OPTION mips_options): Ditto.
3023
3024 * interp.c (OPTION mips_options): Rename option trace to dinero.
3025 (mips_option_handler): Update.
3026
3027Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
3028
3029 * interp.c (fetch_str): New function.
3030 (sim_monitor): Rewrite using sim_read & sim_write.
3031 (sim_open): Check magic number.
3032 (sim_open): Write monitor vectors into memory using sim_write.
3033 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
3034 (sim_read, sim_write): Simplify - transfer data one byte at a
3035 time.
3036 (load_memory, store_memory): Clarify meaning of parameter RAW.
3037
3038 * sim-main.h (isHOST): Defete definition.
3039 (isTARGET): Mark as depreciated.
3040 (address_translation): Delete parameter HOST.
3041
3042 * interp.c (address_translation): Delete parameter HOST.
3043
3044Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
3045
72f4393d 3046 * mips.igen:
c906108c
SS		 3047
3048 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
3049 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
3050
3051Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
3052
3053 * mips.igen: Add model filter field to records.
3054
3055Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
3056
3057 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
72f4393d 3058
c906108c
SS		 3059 interp.c (sim_engine_run): Do not compile function sim_engine_run
3060 when WITH_IGEN == 1.
3061
3062 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
3063 target architecture.
3064
3065 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
3066 igen. Replace with configuration variables sim_igen_flags /
3067 sim_m16_flags.
3068
3069 * m16.igen: New file. Copy mips16 insns here.
3070 * mips.igen: From here.
3071
3072Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
3073
3074 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
3075 to top.
3076 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
3077
3078Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
3079
3080 * gencode.c (build_instruction): Follow sim_write's lead in using
3081 BigEndianMem instead of !ByteSwapMem.
3082
3083Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
3084
3085 * configure.in (sim_gen): Dependent on target, select type of
3086 generator. Always select old style generator.
3087
3088 configure: Re-generate.
3089
3090 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
3091 targets.
3092 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
3093 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
3094 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
3095 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
3096 SIM_@sim_gen@_*, set by autoconf.
72f4393d 3097
c906108c
SS		 3098Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
3099
3100 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
3101
3102 * interp.c (ColdReset): Remove #ifdef HASFPU, check
3103 CURRENT_FLOATING_POINT instead.
3104
3105 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
3106 (address_translation): Raise exception InstructionFetch when
3107 translation fails and isINSTRUCTION.
72f4393d 3108
c906108c
SS		 3109 * interp.c (sim_open, sim_write, sim_monitor, store_word,
3110 sim_engine_run): Change type of of vaddr and paddr to
3111 address_word.
3112 (address_translation, prefetch, load_memory, store_memory,
3113 cache_op): Change type of vAddr and pAddr to address_word.
3114
3115 * gencode.c (build_instruction): Change type of vaddr and paddr to
3116 address_word.
3117
3118Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
3119
3120 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
3121 macro to obtain result of ALU op.
3122
3123Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
3124
3125 * interp.c (sim_info): Call profile_print.
3126
3127Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3128
3129 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
3130
3131 * sim-main.h (WITH_PROFILE): Do not define, defined in
3132 common/sim-config.h. Use sim-profile module.
3133 (simPROFILE): Delete defintion.
3134
3135 * interp.c (PROFILE): Delete definition.
3136 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
3137 (sim_close): Delete code writing profile histogram.
3138 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
3139 Delete.
3140 (sim_engine_run): Delete code profiling the PC.
3141
3142Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3143
3144 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
3145
3146 * interp.c (sim_monitor): Make register pointers of type
3147 unsigned_word*.
3148
3149 * sim-main.h: Make registers of type unsigned_word not
3150 signed_word.
3151
3152Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3153
3154 * interp.c (sync_operation): Rename from SyncOperation, make
3155 global, add SD argument.
3156 (prefetch): Rename from Prefetch, make global, add SD argument.
3157 (decode_coproc): Make global.
3158
3159 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
3160
3161 * gencode.c (build_instruction): Generate DecodeCoproc not
3162 decode_coproc calls.
3163
3164 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
3165 (SizeFGR): Move to sim-main.h
3166 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
3167 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
3168 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
3169 sim-main.h.
3170 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
3171 FP_RM_TOMINF, GETRM): Move to sim-main.h.
3172 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
3173 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
3174 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
3175 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
72f4393d 3176
c906108c
SS		 3177 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
3178 exception.
3179 (sim-alu.h): Include.
3180 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
3181 (sim_cia): Typedef to instruction_address.
72f4393d 3182
c906108c
SS		 3183Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
3184
3185 * Makefile.in (interp.o): Rename generated file engine.c to
3186 oengine.c.
72f4393d 3187
c906108c 3188 * interp.c: Update.
72f4393d 3189
c906108c
SS		 3190Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
3191
3192 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
72f4393d 3193
c906108c
SS		 3194Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3195
3196 * gencode.c (build_instruction): For "FPSQRT", output correct
3197 number of arguments to Recip.
72f4393d 3198
c906108c
SS		 3199Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
3200
3201 * Makefile.in (interp.o): Depends on sim-main.h
3202
3203 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
3204
3205 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
3206 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
3207 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
3208 STATE, DSSTATE): Define
3209 (GPR, FGRIDX, ..): Define.
3210
3211 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
3212 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
3213 (GPR, FGRIDX, ...): Delete macros.
72f4393d 3214
c906108c 3215 * interp.c: Update names to match defines from sim-main.h
72f4393d 3216
c906108c
SS		 3217Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
3218
3219 * interp.c (sim_monitor): Add SD argument.
3220 (sim_warning): Delete. Replace calls with calls to
3221 sim_io_eprintf.
3222 (sim_error): Delete. Replace calls with sim_io_error.
3223 (open_trace, writeout32, writeout16, getnum): Add SD argument.
3224 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
3225 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
3226 argument.
3227 (mips_size): Rename from sim_size. Add SD argument.
3228
3229 * interp.c (simulator): Delete global variable.
3230 (callback): Delete global variable.
3231 (mips_option_handler, sim_open, sim_write, sim_read,
3232 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
3233 sim_size,sim_monitor): Use sim_io_* not callback->*.
3234 (sim_open): ZALLOC simulator struct.
3235 (PROFILE): Do not define.
3236
3237Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3238
3239 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
3240 support.h with corresponding code.
3241
3242 * sim-main.h (word64, uword64), support.h: Move definition to
3243 sim-main.h.
3244 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
3245
3246 * support.h: Delete
3247 * Makefile.in: Update dependencies
3248 * interp.c: Do not include.
72f4393d 3249
c906108c
SS		 3250Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3251
3252 * interp.c (address_translation, load_memory, store_memory,
3253 cache_op): Rename to from AddressTranslation et.al., make global,
3254 add SD argument
72f4393d 3255
c906108c
SS		 3256 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
3257 CacheOp): Define.
72f4393d 3258
c906108c
SS		 3259 * interp.c (SignalException): Rename to signal_exception, make
3260 global.
3261
3262 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
72f4393d 3263
c906108c
SS		 3264 * sim-main.h (SignalException, SignalExceptionInterrupt,
3265 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
3266 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
3267 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
3268 Define.
72f4393d 3269
c906108c 3270 * interp.c, support.h: Use.
72f4393d 3271
c906108c
SS		 3272Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3273
3274 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
3275 to value_fpr / store_fpr. Add SD argument.
3276 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
3277 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
3278
3279 * sim-main.h (ValueFPR, StoreFPR): Define.
72f4393d 3280
c906108c
SS		 3281Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
3282
3283 * interp.c (sim_engine_run): Check consistency between configure
3284 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
3285 and HASFPU.
3286
3287 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
72f4393d 3288 (mips_fpu): Configure WITH_FLOATING_POINT.
c906108c
SS		 3289 (mips_endian): Configure WITH_TARGET_ENDIAN.
3290 * configure: Update.
3291
3292Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3293
3294 * configure: Regenerated to track ../common/aclocal.m4 changes.
3295
3296Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
3297
3298 * configure: Regenerated.
3299
3300Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
3301
3302 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
3303
3304Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3305
3306 * gencode.c (print_igen_insn_models): Assume certain architectures
3307 include all mips* instructions.
3308 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
3309 instruction.
3310
3311 * Makefile.in (tmp.igen): Add target. Generate igen input from
3312 gencode file.
3313
3314 * gencode.c (FEATURE_IGEN): Define.
3315 (main): Add --igen option. Generate output in igen format.
3316 (process_instructions): Format output according to igen option.
3317 (print_igen_insn_format): New function.
3318 (print_igen_insn_models): New function.
3319 (process_instructions): Only issue warnings and ignore
3320 instructions when no FEATURE_IGEN.
3321
3322Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3323
3324 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
3325 MIPS targets.
3326
3327Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3328
3329 * configure: Regenerated to track ../common/aclocal.m4 changes.
3330
3331Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
3332
3333 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
3334 SIM_RESERVED_BITS): Delete, moved to common.
3335 (SIM_EXTRA_CFLAGS): Update.
72f4393d 3336
c906108c
SS		 3337Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3338
3339 * configure.in: Configure non-strict memory alignment.
3340 * configure: Regenerated to track ../common/aclocal.m4 changes.
3341
3342Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
3343
3344 * configure: Regenerated to track ../common/aclocal.m4 changes.
3345
3346Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
3347
3348 * gencode.c (SDBBP,DERET): Added (3900) insns.
3349 (RFE): Turn on for 3900.
3350 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
3351 (dsstate): Made global.
3352 (SUBTARGET_R3900): Added.
3353 (CANCELDELAYSLOT): New.
3354 (SignalException): Ignore SystemCall rather than ignore and
3355 terminate. Add DebugBreakPoint handling.
3356 (decode_coproc): New insns RFE, DERET; and new registers Debug
3357 and DEPC protected by SUBTARGET_R3900.
3358 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
3359 bits explicitly.
3360 * Makefile.in,configure.in: Add mips subtarget option.
72f4393d 3361 * configure: Update.
c906108c
SS		 3362
3363Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
3364
3365 * gencode.c: Add r3900 (tx39).
72f4393d 3366
c906108c
SS		 3367
3368Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
3369
3370 * gencode.c (build_instruction): Don't need to subtract 4 for
3371 JALR, just 2.
3372
3373Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
3374
3375 * interp.c: Correct some HASFPU problems.
3376
3377Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
3378
3379 * configure: Regenerated to track ../common/aclocal.m4 changes.
3380
3381Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3382
3383 * interp.c (mips_options): Fix samples option short form, should
3384 be `x'.
3385
3386Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
3387
3388 * interp.c (sim_info): Enable info code. Was just returning.
3389
3390Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3391
3392 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
3393 MFC0.
3394
3395Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
3396
3397 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
3398 constants.
3399 (build_instruction): Ditto for LL.
3400
3401Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
3402
3403 * configure: Regenerated to track ../common/aclocal.m4 changes.
3404
3405Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3406
3407 * configure: Regenerated to track ../common/aclocal.m4 changes.
3408 * config.in: Ditto.
3409
3410Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
3411
3412 * interp.c (sim_open): Add call to sim_analyze_program, update
3413 call to sim_config.
3414
3415Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
3416
3417 * interp.c (sim_kill): Delete.
3418 (sim_create_inferior): Add ABFD argument. Set PC from same.
3419 (sim_load): Move code initializing trap handlers from here.
3420 (sim_open): To here.
3421 (sim_load): Delete, use sim-hload.c.
3422
3423 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
3424
3425Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3426
3427 * configure: Regenerated to track ../common/aclocal.m4 changes.
3428 * config.in: Ditto.
3429
3430Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3431
3432 * interp.c (sim_open): Add ABFD argument.
3433 (sim_load): Move call to sim_config from here.
3434 (sim_open): To here. Check return status.
3435
3436Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
72f4393d 3437
c906108c
SS		 3438 * gencode.c (build_instruction): Two arg MADD should
3439 not assign result to $0.
72f4393d 3440
c906108c
SS		 3441Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
3442
3443 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
3444 * sim/mips/configure.in: Regenerate.
3445
3446Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
3447
3448 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
3449 signed8, unsigned8 et.al. types.
3450
3451 * interp.c (SUB_REG_FETCH): Handle both little and big endian
3452 hosts when selecting subreg.
3453
3454Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
3455
3456 * interp.c (sim_engine_run): Reset the ZERO register to zero
3457 regardless of FEATURE_WARN_ZERO.
3458 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
3459
3460Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
3461
3462 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
3463 (SignalException): For BreakPoints ignore any mode bits and just
3464 save the PC.
3465 (SignalException): Always set the CAUSE register.
3466
3467Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
3468
3469 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
3470 exception has been taken.
3471
3472 * interp.c: Implement the ERET and mt/f sr instructions.
3473
3474Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
3475
3476 * interp.c (SignalException): Don't bother restarting an
3477 interrupt.
3478
3479Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3480
3481 * interp.c (SignalException): Really take an interrupt.
3482 (interrupt_event): Only deliver interrupts when enabled.
3483
3484Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
3485
3486 * interp.c (sim_info): Only print info when verbose.
3487 (sim_info) Use sim_io_printf for output.
72f4393d 3488
c906108c
SS		 3489Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3490
3491 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
3492 mips architectures.
3493
3494Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3495
3496 * interp.c (sim_do_command): Check for common commands if a
3497 simulator specific command fails.
3498
3499Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
3500
3501 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
3502 and simBE when DEBUG is defined.
3503
3504Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
3505
3506 * interp.c (interrupt_event): New function. Pass exception event
3507 onto exception handler.
3508
3509 * configure.in: Check for stdlib.h.
3510 * configure: Regenerate.
3511
3512 * gencode.c (build_instruction): Add UNUSED attribute to tempS
3513 variable declaration.
3514 (build_instruction): Initialize memval1.
3515 (build_instruction): Add UNUSED attribute to byte, bigend,
3516 reverse.
3517 (build_operands): Ditto.
3518
3519 * interp.c: Fix GCC warnings.
3520 (sim_get_quit_code): Delete.
3521
3522 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
3523 * Makefile.in: Ditto.
3524 * configure: Re-generate.
72f4393d 3525
c906108c
SS		 3526 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
3527
3528Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
3529
3530 * interp.c (mips_option_handler): New function parse argumes using
3531 sim-options.
3532 (myname): Replace with STATE_MY_NAME.
3533 (sim_open): Delete check for host endianness - performed by
3534 sim_config.
3535 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
3536 (sim_open): Move much of the initialization from here.
3537 (sim_load): To here. After the image has been loaded and
3538 endianness set.
3539 (sim_open): Move ColdReset from here.
3540 (sim_create_inferior): To here.
3541 (sim_open): Make FP check less dependant on host endianness.
3542
3543 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
3544 run.
3545 * interp.c (sim_set_callbacks): Delete.
3546
3547 * interp.c (membank, membank_base, membank_size): Replace with
3548 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
3549 (sim_open): Remove call to callback->init. gdb/run do this.
3550
3551 * interp.c: Update
3552
3553 * sim-main.h (SIM_HAVE_FLATMEM): Define.
3554
3555 * interp.c (big_endian_p): Delete, replaced by
3556 current_target_byte_order.
3557
3558Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3559
3560 * interp.c (host_read_long, host_read_word, host_swap_word,
3561 host_swap_long): Delete. Using common sim-endian.
3562 (sim_fetch_register, sim_store_register): Use H2T.
3563 (pipeline_ticks): Delete. Handled by sim-events.
3564 (sim_info): Update.
3565 (sim_engine_run): Update.
3566
3567Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
3568
3569 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
3570 reason from here.
3571 (SignalException): To here. Signal using sim_engine_halt.
3572 (sim_stop_reason): Delete, moved to common.
72f4393d 3573
c906108c
SS		 3574Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
3575
3576 * interp.c (sim_open): Add callback argument.
3577 (sim_set_callbacks): Delete SIM_DESC argument.
3578 (sim_size): Ditto.
3579
3580Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3581
3582 * Makefile.in (SIM_OBJS): Add common modules.
3583
3584 * interp.c (sim_set_callbacks): Also set SD callback.
3585 (set_endianness, xfer_*, swap_*): Delete.
3586 (host_read_word, host_read_long, host_swap_word, host_swap_long):
3587 Change to functions using sim-endian macros.
3588 (control_c, sim_stop): Delete, use common version.
3589 (simulate): Convert into.
3590 (sim_engine_run): This function.
3591 (sim_resume): Delete.
72f4393d 3592
c906108c
SS		 3593 * interp.c (simulation): New variable - the simulator object.
3594 (sim_kind): Delete global - merged into simulation.
3595 (sim_load): Cleanup. Move PC assignment from here.
3596 (sim_create_inferior): To here.
3597
3598 * sim-main.h: New file.
3599 * interp.c (sim-main.h): Include.
72f4393d 3600
c906108c
SS		 3601Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
3602
3603 * configure: Regenerated to track ../common/aclocal.m4 changes.
3604
3605Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
3606
3607 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
3608
3609Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
3610
72f4393d
L		 3611 * gencode.c (build_instruction): DIV instructions: check
3612 for division by zero and integer overflow before using
c906108c
SS		 3613 host's division operation.
3614
3615Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
3616
3617 * Makefile.in (SIM_OBJS): Add sim-load.o.
3618 * interp.c: #include bfd.h.
3619 (target_byte_order): Delete.
3620 (sim_kind, myname, big_endian_p): New static locals.
3621 (sim_open): Set sim_kind, myname. Move call to set_endianness to
3622 after argument parsing. Recognize -E arg, set endianness accordingly.
3623 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
3624 load file into simulator. Set PC from bfd.
3625 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
3626 (set_endianness): Use big_endian_p instead of target_byte_order.
3627
3628Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
3629
3630 * interp.c (sim_size): Delete prototype - conflicts with
3631 definition in remote-sim.h. Correct definition.
3632
3633Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3634
3635 * configure: Regenerated to track ../common/aclocal.m4 changes.
3636 * config.in: Ditto.
3637
3638Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
3639
3640 * interp.c (sim_open): New arg `kind'.
3641
3642 * configure: Regenerated to track ../common/aclocal.m4 changes.
3643
3644Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3645
3646 * configure: Regenerated to track ../common/aclocal.m4 changes.
3647
3648Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
3649
3650 * interp.c (sim_open): Set optind to 0 before calling getopt.
3651
3652Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3653
3654 * configure: Regenerated to track ../common/aclocal.m4 changes.
3655
3656Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
3657
3658 * interp.c : Replace uses of pr_addr with pr_uword64
3659 where the bit length is always 64 independent of SIM_ADDR.
3660 (pr_uword64) : added.
3661
3662Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3663
3664 * configure: Re-generate.
3665
3666Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
3667
3668 * configure: Regenerate to track ../common/aclocal.m4 changes.
3669
3670Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
3671
3672 * interp.c (sim_open): New SIM_DESC result. Argument is now
3673 in argv form.
3674 (other sim_*): New SIM_DESC argument.
3675
3676Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
3677
3678 * interp.c: Fix printing of addresses for non-64-bit targets.
3679 (pr_addr): Add function to print address based on size.
3680
3681Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
3682
3683 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
3684
3685Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
3686
3687 * gencode.c (build_mips16_operands): Correct computation of base
3688 address for extended PC relative instruction.
3689
3690Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
3691
3692 * interp.c (mips16_entry): Add support for floating point cases.
3693 (SignalException): Pass floating point cases to mips16_entry.
3694 (ValueFPR): Don't restrict fmt_single and fmt_word to even
3695 registers.
3696 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
3697 or fmt_word.
3698 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
3699 and then set the state to fmt_uninterpreted.
3700 (COP_SW): Temporarily set the state to fmt_word while calling
3701 ValueFPR.
3702
3703Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
3704
3705 * gencode.c (build_instruction): The high order may be set in the
3706 comparison flags at any ISA level, not just ISA 4.
3707
3708Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
3709
3710 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
3711 COMMON_{PRE,POST}_CONFIG_FRAG instead.
3712 * configure.in: sinclude ../common/aclocal.m4.
3713 * configure: Regenerated.
3714
3715Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
3716
3717 * configure: Rebuild after change to aclocal.m4.
3718
3719Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
3720
3721 * configure configure.in Makefile.in: Update to new configure
3722 scheme which is more compatible with WinGDB builds.
3723 * configure.in: Improve comment on how to run autoconf.
3724 * configure: Re-run autoconf to get new ../common/aclocal.m4.
3725 * Makefile.in: Use autoconf substitution to install common
3726 makefile fragment.
3727
3728Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
3729
3730 * gencode.c (build_instruction): Use BigEndianCPU instead of
3731 ByteSwapMem.
3732
3733Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
3734
3735 * interp.c (sim_monitor): Make output to stdout visible in
3736 wingdb's I/O log window.
3737
3738Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
3739
3740 * support.h: Undo previous change to SIGTRAP
3741 and SIGQUIT values.
3742
3743Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
3744
3745 * interp.c (store_word, load_word): New static functions.
3746 (mips16_entry): New static function.
3747 (SignalException): Look for mips16 entry and exit instructions.
3748 (simulate): Use the correct index when setting fpr_state after
3749 doing a pending move.
3750
3751Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
3752
3753 * interp.c: Fix byte-swapping code throughout to work on
3754 both little- and big-endian hosts.
3755
3756Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
3757
3758 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3759 with gdb/config/i386/xm-windows.h.
3760
3761Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
3762
3763 * gencode.c (build_instruction): Work around MSVC++ code gen bug
3764 that messes up arithmetic shifts.
3765
3766Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
3767
3768 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
3769 SIGTRAP and SIGQUIT for _WIN32.
3770
3771Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3772
3773 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3774 force a 64 bit multiplication.
3775 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3776 destination register is 0, since that is the default mips16 nop
3777 instruction.
3778
3779Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3780
3781 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3782 (build_endian_shift): Don't check proc64.
3783 (build_instruction): Always set memval to uword64. Cast op2 to
3784 uword64 when shifting it left in memory instructions. Always use
3785 the same code for stores--don't special case proc64.
3786
3787 * gencode.c (build_mips16_operands): Fix base PC value for PC
3788 relative operands.
3789 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3790 jal instruction.
3791 * interp.c (simJALDELAYSLOT): Define.
3792 (JALDELAYSLOT): Define.
3793 (INDELAYSLOT, INJALDELAYSLOT): Define.
3794 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3795
3796Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3797
3798 * interp.c (sim_open): add flush_cache as a PMON routine
3799 (sim_monitor): handle flush_cache by ignoring it
3800
3801Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3802
3803 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3804 BigEndianMem.
3805 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3806 (BigEndianMem): Rename to ByteSwapMem and change sense.
3807 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3808 BigEndianMem references to !ByteSwapMem.
3809 (set_endianness): New function, with prototype.
3810 (sim_open): Call set_endianness.
3811 (sim_info): Use simBE instead of BigEndianMem.
3812 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3813 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3814 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3815 ifdefs, keeping the prototype declaration.
3816 (swap_word): Rewrite correctly.
3817 (ColdReset): Delete references to CONFIG. Delete endianness related
3818 code; moved to set_endianness.
72f4393d 3819
c906108c
SS		 3820Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3821
3822 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3823 * interp.c (CHECKHILO): Define away.
3824 (simSIGINT): New macro.
3825 (membank_size): Increase from 1MB to 2MB.
3826 (control_c): New function.
3827 (sim_resume): Rename parameter signal to signal_number. Add local
3828 variable prev. Call signal before and after simulate.
3829 (sim_stop_reason): Add simSIGINT support.
3830 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3831 functions always.
3832 (sim_warning): Delete call to SignalException. Do call printf_filtered
3833 if logfh is NULL.
3834 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3835 a call to sim_warning.
3836
3837Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3838
3839 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3840 16 bit instructions.
3841
3842Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3843
3844 Add support for mips16 (16 bit MIPS implementation):
3845 * gencode.c (inst_type): Add mips16 instruction encoding types.
3846 (GETDATASIZEINSN): Define.
3847 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3848 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3849 mtlo.
3850 (MIPS16_DECODE): New table, for mips16 instructions.
3851 (bitmap_val): New static function.
3852 (struct mips16_op): Define.
3853 (mips16_op_table): New table, for mips16 operands.
3854 (build_mips16_operands): New static function.
3855 (process_instructions): If PC is odd, decode a mips16
3856 instruction. Break out instruction handling into new
3857 build_instruction function.
3858 (build_instruction): New static function, broken out of
3859 process_instructions. Check modifiers rather than flags for SHIFT
3860 bit count and m[ft]{hi,lo} direction.
3861 (usage): Pass program name to fprintf.
3862 (main): Remove unused variable this_option_optind. Change
3863 ``*loptarg++'' to ``loptarg++''.
3864 (my_strtoul): Parenthesize && within ||.
3865 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3866 (simulate): If PC is odd, fetch a 16 bit instruction, and
3867 increment PC by 2 rather than 4.
3868 * configure.in: Add case for mips16*-*-*.
3869 * configure: Rebuild.
3870
3871Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3872
3873 * interp.c: Allow -t to enable tracing in standalone simulator.
3874 Fix garbage output in trace file and error messages.
3875
3876Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3877
3878 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3879 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3880 * configure.in: Simplify using macros in ../common/aclocal.m4.
3881 * configure: Regenerated.
3882 * tconfig.in: New file.
3883
3884Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3885
3886 * interp.c: Fix bugs in 64-bit port.
3887 Use ansi function declarations for msvc compiler.
3888 Initialize and test file pointer in trace code.
3889 Prevent duplicate definition of LAST_EMED_REGNUM.
3890
3891Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3892
3893 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3894
3895Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3896
3897 * interp.c (SignalException): Check for explicit terminating
3898 breakpoint value.
3899 * gencode.c: Pass instruction value through SignalException()
3900 calls for Trap, Breakpoint and Syscall.
3901
3902Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3903
3904 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3905 only used on those hosts that provide it.
3906 * configure.in: Add sqrt() to list of functions to be checked for.
3907 * config.in: Re-generated.
3908 * configure: Re-generated.
3909
3910Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3911
3912 * gencode.c (process_instructions): Call build_endian_shift when
3913 expanding STORE RIGHT, to fix swr.
3914 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3915 clear the high bits.
3916 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3917 Fix float to int conversions to produce signed values.
3918
3919Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3920
3921 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3922 (process_instructions): Correct handling of nor instruction.
3923 Correct shift count for 32 bit shift instructions. Correct sign
3924 extension for arithmetic shifts to not shift the number of bits in
3925 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3926 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3927 Fix madd.
3928 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3929 It's OK to have a mult follow a mult. What's not OK is to have a
3930 mult follow an mfhi.
3931 (Convert): Comment out incorrect rounding code.
3932
3933Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3934
3935 * interp.c (sim_monitor): Improved monitor printf
3936 simulation. Tidied up simulator warnings, and added "--log" option
3937 for directing warning message output.
3938 * gencode.c: Use sim_warning() rather than WARNING macro.
3939
3940Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3941
3942 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3943 getopt1.o, rather than on gencode.c. Link objects together.
3944 Don't link against -liberty.
3945 (gencode.o, getopt.o, getopt1.o): New targets.
3946 * gencode.c: Include <ctype.h> and "ansidecl.h".
3947 (AND): Undefine after including "ansidecl.h".
3948 (ULONG_MAX): Define if not defined.
3949 (OP_*): Don't define macros; now defined in opcode/mips.h.
3950 (main): Call my_strtoul rather than strtoul.
3951 (my_strtoul): New static function.
3952
3953Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3954
3955 * gencode.c (process_instructions): Generate word64 and uword64
3956 instead of `long long' and `unsigned long long' data types.
3957 * interp.c: #include sysdep.h to get signals, and define default
3958 for SIGBUS.
3959 * (Convert): Work around for Visual-C++ compiler bug with type
3960 conversion.
3961 * support.h: Make things compile under Visual-C++ by using
3962 __int64 instead of `long long'. Change many refs to long long
3963 into word64/uword64 typedefs.
3964
3965Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3966
72f4393d
L		 3967 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3968 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3969 (docdir): Removed.
3970 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3971 (AC_PROG_INSTALL): Added.
c906108c 3972 (AC_PROG_CC): Moved to before configure.host call.
72f4393d
L		 3973 * configure: Rebuilt.
3974
c906108c
SS		 3975Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3976
3977 * configure.in: Define @SIMCONF@ depending on mips target.
3978 * configure: Rebuild.
3979 * Makefile.in (run): Add @SIMCONF@ to control simulator
3980 construction.
3981 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3982 * interp.c: Remove some debugging, provide more detailed error
3983 messages, update memory accesses to use LOADDRMASK.
72f4393d 3984
c906108c
SS		 3985Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3986
3987 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3988 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3989 stamp-h.
3990 * configure: Rebuild.
3991 * config.in: New file, generated by autoheader.
3992 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3993 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3994 HAVE_ANINT and HAVE_AINT, as appropriate.
3995 * Makefile.in (run): Use @LIBS@ rather than -lm.
3996 (interp.o): Depend upon config.h.
3997 (Makefile): Just rebuild Makefile.
3998 (clean): Remove stamp-h.
3999 (mostlyclean): Make the same as clean, not as distclean.
4000 (config.h, stamp-h): New targets.
4001
4002Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
4003
4004 * interp.c (ColdReset): Fix boolean test. Make all simulator
4005 globals static.
4006
4007Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
4008
4009 * interp.c (xfer_direct_word, xfer_direct_long,
4010 swap_direct_word, swap_direct_long, xfer_big_word,
4011 xfer_big_long, xfer_little_word, xfer_little_long,
4012 swap_word,swap_long): Added.
4013 * interp.c (ColdReset): Provide function indirection to
4014 host<->simulated_target transfer routines.
4015 * interp.c (sim_store_register, sim_fetch_register): Updated to
4016 make use of indirected transfer routines.
4017
4018Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
4019
4020 * gencode.c (process_instructions): Ensure FP ABS instruction
4021 recognised.
4022 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
4023 system call support.
4024
4025Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
4026
4027 * interp.c (sim_do_command): Complain if callback structure not
4028 initialised.
4029
4030Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
4031
4032 * interp.c (Convert): Provide round-to-nearest and round-to-zero
4033 support for Sun hosts.
4034 * Makefile.in (gencode): Ensure the host compiler and libraries
4035 used for cross-hosted build.
4036
4037Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
4038
4039 * interp.c, gencode.c: Some more (TODO) tidying.
4040
4041Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
4042
4043 * gencode.c, interp.c: Replaced explicit long long references with
4044 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
4045 * support.h (SET64LO, SET64HI): Macros added.
4046
4047Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
4048
4049 * configure: Regenerate with autoconf 2.7.
4050
4051Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
4052
4053 * interp.c (LoadMemory): Enclose text following #endif in /* */.
4054 * support.h: Remove superfluous "1" from #if.
4055 * support.h (CHECKSIM): Remove stray 'a' at end of line.
4056
4057Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
4058
4059 * interp.c (StoreFPR): Control UndefinedResult() call on
4060 WARN_RESULT manifest.
4061
4062Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
4063
4064 * gencode.c: Tidied instruction decoding, and added FP instruction
4065 support.
4066
4067 * interp.c: Added dineroIII, and BSD profiling support. Also
4068 run-time FP handling.
4069
4070Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
4071
4072 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
4073 gencode.c, interp.c, support.h: created.
GDB Binutils - Deliverables
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