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* elf64-alpha.c (elf64_alpha_relax_with_lituse): Don't test for
[deliverable/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
5accf1ff
CD		 12002-05-01 Chris Demetriou <cgd@broadcom.com>
2
3 * interp.c: Use 'deprecated' rather than 'depreciated.'
4 * sim-main.h: Likewise.
5
402586aa
CD		 62002-05-01 Chris Demetriou <cgd@broadcom.com>
7
8 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
9 which wouldn't compile anyway.
10 * sim-main.h (unpredictable_action): New function prototype.
11 (Unpredictable): Define to call igen function unpredictable().
12 (NotWordValue): New macro to call igen function not_word_value().
13 (UndefinedResult): Remove.
14 * interp.c (undefined_result): Remove.
15 (unpredictable_action): New function.
16 * mips.igen (not_word_value, unpredictable): New functions.
17 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
18 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
19 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
20 NotWordValue() to check for unpredictable inputs, then
21 Unpredictable() to handle them.
22
c9b9995a
CD		 232002-02-24 Chris Demetriou <cgd@broadcom.com>
24
25 * mips.igen: Fix formatting of calls to Unpredictable().
26
e1015982
AC		 272002-04-20 Andrew Cagney <ac131313@redhat.com>
28
29 * interp.c (sim_open): Revert previous change.
30
b882a66b
AO		 312002-04-18 Alexandre Oliva <aoliva@redhat.com>
32
33 * interp.c (sim_open): Disable chunk of code that wrote code in
34 vector table entries.
35
c429b7dd
CD		 362002-03-19 Chris Demetriou <cgd@broadcom.com>
37
38 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
39 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
40 unused definitions.
41
37d146fa
CD		 422002-03-19 Chris Demetriou <cgd@broadcom.com>
43
44 * cp1.c: Fix many formatting issues.
45
07892c0b
CD		 462002-03-19 Chris G. Demetriou <cgd@broadcom.com>
47
48 * cp1.c (fpu_format_name): New function to replace...
49 (DOFMT): This. Delete, and update all callers.
50 (fpu_rounding_mode_name): New function to replace...
51 (RMMODE): This. Delete, and update all callers.
52
487f79b7
CD		 532002-03-19 Chris G. Demetriou <cgd@broadcom.com>
54
55 * interp.c: Move FPU support routines from here to...
56 * cp1.c: Here. New file.
57 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
58 (cp1.o): New target.
59
1e799e28
CD		 602002-03-12 Chris Demetriou <cgd@broadcom.com>
61
62 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
63 * mips.igen (mips32, mips64): New models, add to all instructions
64 and functions as appropriate.
65 (loadstore_ea, check_u64): New variant for model mips64.
66 (check_fmt_p): New variant for models mipsV and mips64, remove
67 mipsV model marking fro other variant.
68 (SLL) Rename to...
69 (SLLa) this.
70 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
71 for mips32 and mips64.
72 (DCLO, DCLZ): New instructions for mips64.
73
82f728db
CD		 742002-03-07 Chris Demetriou <cgd@broadcom.com>
75
76 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
77 immediate or code as a hex value with the "%#lx" format.
78 (ANDI): Likewise, and fix printed instruction name.
79
b96e7ef1
CD		 802002-03-05 Chris Demetriou <cgd@broadcom.com>
81
82 * sim-main.h (UndefinedResult, Unpredictable): New macros
83 which currently do nothing.
84
d35d4f70
CD		 852002-03-05 Chris Demetriou <cgd@broadcom.com>
86
87 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
88 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
89 (status_CU3): New definitions.
90
91 * sim-main.h (ExceptionCause): Add new values for MIPS32
92 and MIPS64: MDMX, MCheck, CacheErr. Update comments
93 for DebugBreakPoint and NMIReset to note their status in
94 MIPS32 and MIPS64.
95 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
96 (SignalExceptionCacheErr): New exception macros.
97
3ad6f714
CD		 982002-03-05 Chris Demetriou <cgd@broadcom.com>
99
100 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
101 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
102 is always enabled.
103 (SignalExceptionCoProcessorUnusable): Take as argument the
104 unusable coprocessor number.
105
86b77b47
CD		 1062002-03-05 Chris Demetriou <cgd@broadcom.com>
107
108 * mips.igen: Fix formatting of all SignalException calls.
109
97a88e93 1102002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 111
112 * sim-main.h (SIGNEXTEND): Remove.
113
97a88e93 1142002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 115
116 * mips.igen: Remove gencode comment from top of file, fix
117 spelling in another comment.
118
97a88e93 1192002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 120
121 * mips.igen (check_fmt, check_fmt_p): New functions to check
122 whether specific floating point formats are usable.
123 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
124 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
125 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
126 Use the new functions.
127 (do_c_cond_fmt): Remove format checks...
128 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
129
97a88e93 1302002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 131
132 * mips.igen: Fix formatting of check_fpu calls.
133
41774c9d
CD		 1342002-03-03 Chris Demetriou <cgd@broadcom.com>
135
136 * mips.igen (FLOOR.L.fmt): Store correct destination register.
137
4a0bd876
CD		 1382002-03-03 Chris Demetriou <cgd@broadcom.com>
139
140 * mips.igen: Remove whitespace at end of lines.
141
09297648
CD		 1422002-03-02 Chris Demetriou <cgd@broadcom.com>
143
144 * mips.igen (loadstore_ea): New function to do effective
145 address calculations.
146 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
147 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
148 CACHE): Use loadstore_ea to do effective address computations.
149
043b7057
CD		 1502002-03-02 Chris Demetriou <cgd@broadcom.com>
151
152 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
153 * mips.igen (LL, CxC1, MxC1): Likewise.
154
c1e8ada4
CD		 1552002-03-02 Chris Demetriou <cgd@broadcom.com>
156
157 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
158 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
159 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
160 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
161 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
162 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
163 Don't split opcode fields by hand, use the opcode field values
164 provided by igen.
165
3e1dca16
CD		 1662002-03-01 Chris Demetriou <cgd@broadcom.com>
167
168 * mips.igen (do_divu): Fix spacing.
169
170 * mips.igen (do_dsllv): Move to be right before DSLLV,
171 to match the rest of the do_<shift> functions.
172
fff8d27d
CD		 1732002-03-01 Chris Demetriou <cgd@broadcom.com>
174
175 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
176 DSRL32, do_dsrlv): Trace inputs and results.
177
0d3e762b
CD		 1782002-03-01 Chris Demetriou <cgd@broadcom.com>
179
180 * mips.igen (CACHE): Provide instruction-printing string.
181
182 * interp.c (signal_exception): Comment tokens after #endif.
183
eb5fcf93
CD		 1842002-02-28 Chris Demetriou <cgd@broadcom.com>
185
186 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
187 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
188 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
189 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
190 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
191 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
192 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
193 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
194
bb22bd7d
CD		 1952002-02-28 Chris Demetriou <cgd@broadcom.com>
196
197 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
198 instruction-printing string.
199 (LWU): Use '64' as the filter flag.
200
91a177cf
CD		 2012002-02-28 Chris Demetriou <cgd@broadcom.com>
202
203 * mips.igen (SDXC1): Fix instruction-printing string.
204
387f484a
CD		 2052002-02-28 Chris Demetriou <cgd@broadcom.com>
206
207 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
208 filter flags "32,f".
209
3d81f391
CD		 2102002-02-27 Chris Demetriou <cgd@broadcom.com>
211
212 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
213 as the filter flag.
214
af5107af
CD		 2152002-02-27 Chris Demetriou <cgd@broadcom.com>
216
217 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
218 add a comma) so that it more closely match the MIPS ISA
219 documentation opcode partitioning.
220 (PREF): Put useful names on opcode fields, and include
221 instruction-printing string.
222
ca971540
CD		 2232002-02-27 Chris Demetriou <cgd@broadcom.com>
224
225 * mips.igen (check_u64): New function which in the future will
226 check whether 64-bit instructions are usable and signal an
227 exception if not. Currently a no-op.
228 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
229 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
230 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
231 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
232
233 * mips.igen (check_fpu): New function which in the future will
234 check whether FPU instructions are usable and signal an exception
235 if not. Currently a no-op.
236 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
237 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
238 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
239 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
240 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
241 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
242 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
243 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
244
1c47a468
CD		 2452002-02-27 Chris Demetriou <cgd@broadcom.com>
246
247 * mips.igen (do_load_left, do_load_right): Move to be immediately
248 following do_load.
249 (do_store_left, do_store_right): Move to be immediately following
250 do_store.
251
603a98e7
CD		 2522002-02-27 Chris Demetriou <cgd@broadcom.com>
253
254 * mips.igen (mipsV): New model name. Also, add it to
255 all instructions and functions where it is appropriate.
256
c5d00cc7
CD		 2572002-02-18 Chris Demetriou <cgd@broadcom.com>
258
259 * mips.igen: For all functions and instructions, list model
260 names that support that instruction one per line.
261
074e9cb8
CD		 2622002-02-11 Chris Demetriou <cgd@broadcom.com>
263
264 * mips.igen: Add some additional comments about supported
265 models, and about which instructions go where.
266 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
267 order as is used in the rest of the file.
268
9805e229
CD		 2692002-02-11 Chris Demetriou <cgd@broadcom.com>
270
271 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
272 indicating that ALU32_END or ALU64_END are there to check
273 for overflow.
274 (DADD): Likewise, but also remove previous comment about
275 overflow checking.
276
f701dad2
CD		 2772002-02-10 Chris Demetriou <cgd@broadcom.com>
278
279 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
280 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
281 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
282 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
283 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
284 fields (i.e., add and move commas) so that they more closely
285 match the MIPS ISA documentation opcode partitioning.
286
2872002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098
CD		 288
289 * mips.igen (ADDI): Print immediate value.
290 (BREAK): Print code.
291 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
292 (SLL): Print "nop" specially, and don't run the code
293 that does the shift for the "nop" case.
294
9e52972e
FF		 2952001-11-17 Fred Fish <fnf@redhat.com>
296
297 * sim-main.h (float_operation): Move enum declaration outside
298 of _sim_cpu struct declaration.
299
c0efbca4
JB		 3002001-04-12 Jim Blandy <jimb@redhat.com>
301
302 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
303 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
304 set of the FCSR.
305 * sim-main.h (COCIDX): Remove definition; this isn't supported by
306 PENDING_FILL, and you can get the intended effect gracefully by
307 calling PENDING_SCHED directly.
308
fb891446
BE		 3092001-02-23 Ben Elliston <bje@redhat.com>
310
311 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
312 already defined elsewhere.
313
8030f857
BE		 3142001-02-19 Ben Elliston <bje@redhat.com>
315
316 * sim-main.h (sim_monitor): Return an int.
317 * interp.c (sim_monitor): Add return values.
318 (signal_exception): Handle error conditions from sim_monitor.
319
56b48a7a
CD		 3202001-02-08 Ben Elliston <bje@redhat.com>
321
322 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
323 (store_memory): Likewise, pass cia to sim_core_write*.
324
d3ee60d9
FCE		 3252000-10-19 Frank Ch. Eigler <fche@redhat.com>
326
327 On advice from Chris G. Demetriou <cgd@sibyte.com>:
328 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
329
071da002
AC		 330Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
331
332 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
333 * Makefile.in: Don't delete *.igen when cleaning directory.
334
a28c02cd
AC		 335Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
336
337 * m16.igen (break): Call SignalException not sim_engine_halt.
338
80ee11fa
AC		 339Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
340
341 From Jason Eckhardt:
342 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
343
673388c0
AC		 344Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
345
346 * mips.igen (MxC1, DMxC1): Fix printf formatting.
347
4c0deff4
NC		 3482000-05-24 Michael Hayes <mhayes@cygnus.com>
349
350 * mips.igen (do_dmultx): Fix typo.
351
eb2d80b4
AC		 352Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
353
354 * configure: Regenerated to track ../common/aclocal.m4 changes.
355
dd37a34b
AC		 356Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
357
358 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
359
4c0deff4
NC		 3602000-04-12 Frank Ch. Eigler <fche@redhat.com>
361
362 * sim-main.h (GPR_CLEAR): Define macro.
363
e30db738
AC		 364Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
365
366 * interp.c (decode_coproc): Output long using %lx and not %s.
367
cb7450ea
FCE		 3682000-03-21 Frank Ch. Eigler <fche@redhat.com>
369
370 * interp.c (sim_open): Sort & extend dummy memory regions for
371 --board=jmr3904 for eCos.
372
a3027dd7
FCE		 3732000-03-02 Frank Ch. Eigler <fche@redhat.com>
374
375 * configure: Regenerated.
376
377Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
378
379 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
380 calls, conditional on the simulator being in verbose mode.
381
dfcd3bfb
JM		 382Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
383
384 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
385 cache don't get ReservedInstruction traps.
386
c2d11a7d
JM		 3871999-11-29 Mark Salter <msalter@cygnus.com>
388
389 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
390 to clear status bits in sdisr register. This is how the hardware works.
391
392 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
393 being used by cygmon.
394
4ce44c66
JM		 3951999-11-11 Andrew Haley <aph@cygnus.com>
396
397 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
398 instructions.
399
cff3e48b
JM		 400Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
401
402 * mips.igen (MULT): Correct previous mis-applied patch.
403
d4f3574e
SS		 404Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
405
406 * mips.igen (delayslot32): Handle sequence like
407 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
408 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
409 (MULT): Actually pass the third register...
410
4111999-09-03 Mark Salter <msalter@cygnus.com>
412
413 * interp.c (sim_open): Added more memory aliases for additional
414 hardware being touched by cygmon on jmr3904 board.
415
416Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
417
418 * configure: Regenerated to track ../common/aclocal.m4 changes.
419
a0b3c4fd
JM		 420Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
421
422 * interp.c (sim_store_register): Handle case where client - GDB -
423 specifies that a 4 byte register is 8 bytes in size.
424 (sim_fetch_register): Ditto.
425
adf40b2e
JM		 4261999-07-14 Frank Ch. Eigler <fche@cygnus.com>
427
428 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
429 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
430 (idt_monitor_base): Base address for IDT monitor traps.
431 (pmon_monitor_base): Ditto for PMON.
432 (lsipmon_monitor_base): Ditto for LSI PMON.
433 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
434 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
435 (sim_firmware_command): New function.
436 (mips_option_handler): Call it for OPTION_FIRMWARE.
437 (sim_open): Allocate memory for idt_monitor region. If "--board"
438 option was given, add no monitor by default. Add BREAK hooks only if
439 monitors are also there.
440
43e526b9
JM		 441Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
442
443 * interp.c (sim_monitor): Flush output before reading input.
444
445Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
446
447 * tconfig.in (SIM_HANDLES_LMA): Always define.
448
449Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
450
451 From Mark Salter <msalter@cygnus.com>:
452 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
453 (sim_open): Add setup for BSP board.
454
9846de1b
JM		 455Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
456
457 * mips.igen (MULT, MULTU): Add syntax for two operand version.
458 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
459 them as unimplemented.
460
cd0fc7c3
SS		 4611999-05-08 Felix Lee <flee@cygnus.com>
462
463 * configure: Regenerated to track ../common/aclocal.m4 changes.
464
7a292a7a
SS		 4651999-04-21 Frank Ch. Eigler <fche@cygnus.com>
466
467 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
468
469Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
470
471 * configure.in: Any mips64vr5*-*-* target should have
472 -DTARGET_ENABLE_FR=1.
473 (default_endian): Any mips64vr*el-*-* target should default to
474 LITTLE_ENDIAN.
475 * configure: Re-generate.
476
4771999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
478
479 * mips.igen (ldl): Extend from _16_, not 32.
480
481Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
482
483 * interp.c (sim_store_register): Force registers written to by GDB
484 into an un-interpreted state.
485
c906108c
SS		 4861999-02-05 Frank Ch. Eigler <fche@cygnus.com>
487
488 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
489 CPU, start periodic background I/O polls.
490 (tx3904sio_poll): New function: periodic I/O poller.
491
4921998-12-30 Frank Ch. Eigler <fche@cygnus.com>
493
494 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
495
496Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
497
498 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
499 case statement.
500
5011998-12-29 Frank Ch. Eigler <fche@cygnus.com>
502
503 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
504 (load_word): Call SIM_CORE_SIGNAL hook on error.
505 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
506 starting. For exception dispatching, pass PC instead of NULL_CIA.
507 (decode_coproc): Use COP0_BADVADDR to store faulting address.
508 * sim-main.h (COP0_BADVADDR): Define.
509 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
510 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
511 (_sim_cpu): Add exc_* fields to store register value snapshots.
512 * mips.igen (*): Replace memory-related SignalException* calls
513 with references to SIM_CORE_SIGNAL hook.
514
515 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
516 fix.
517 * sim-main.c (*): Minor warning cleanups.
518
5191998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
520
521 * m16.igen (DADDIU5): Correct type-o.
522
523Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
524
525 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
526 variables.
527
528Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
529
530 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
531 to include path.
532 (interp.o): Add dependency on itable.h
533 (oengine.c, gencode): Delete remaining references.
534 (BUILT_SRC_FROM_GEN): Clean up.
535
5361998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
537
538 * vr4run.c: New.
539 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
540 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
541 tmp-run-hack) : New.
542 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
543 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
544 Drop the "64" qualifier to get the HACK generator working.
545 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
546 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
547 qualifier to get the hack generator working.
548 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
549 (DSLL): Use do_dsll.
550 (DSLLV): Use do_dsllv.
551 (DSRA): Use do_dsra.
552 (DSRL): Use do_dsrl.
553 (DSRLV): Use do_dsrlv.
554 (BC1): Move *vr4100 to get the HACK generator working.
555 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
556 get the HACK generator working.
557 (MACC) Rename to get the HACK generator working.
558 (DMACC,MACCS,DMACCS): Add the 64.
559
5601998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
561
562 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
563 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
564
5651998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
566
567 * mips/interp.c (DEBUG): Cleanups.
568
5691998-12-10 Frank Ch. Eigler <fche@cygnus.com>
570
571 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
572 (tx3904sio_tickle): fflush after a stdout character output.
573
5741998-12-03 Frank Ch. Eigler <fche@cygnus.com>
575
576 * interp.c (sim_close): Uninstall modules.
577
578Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
579
580 * sim-main.h, interp.c (sim_monitor): Change to global
581 function.
582
583Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
584
585 * configure.in (vr4100): Only include vr4100 instructions in
586 simulator.
587 * configure: Re-generate.
588 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
589
590Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
591
592 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
593 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
594 true alternative.
595
596 * configure.in (sim_default_gen, sim_use_gen): Replace with
597 sim_gen.
598 (--enable-sim-igen): Delete config option. Always using IGEN.
599 * configure: Re-generate.
600
601 * Makefile.in (gencode): Kill, kill, kill.
602 * gencode.c: Ditto.
603
604Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
605
606 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
607 bit mips16 igen simulator.
608 * configure: Re-generate.
609
610 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
611 as part of vr4100 ISA.
612 * vr.igen: Mark all instructions as 64 bit only.
613
614Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
615
616 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
617 Pacify GCC.
618
619Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
620
621 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
622 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
623 * configure: Re-generate.
624
625 * m16.igen (BREAK): Define breakpoint instruction.
626 (JALX32): Mark instruction as mips16 and not r3900.
627 * mips.igen (C.cond.fmt): Fix typo in instruction format.
628
629 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
630
631Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
632
633 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
634 insn as a debug breakpoint.
635
636 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
637 pending.slot_size.
638 (PENDING_SCHED): Clean up trace statement.
639 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
640 (PENDING_FILL): Delay write by only one cycle.
641 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
642
643 * sim-main.c (pending_tick): Clean up trace statements. Add trace
644 of pending writes.
645 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
646 32 & 64.
647 (pending_tick): Move incrementing of index to FOR statement.
648 (pending_tick): Only update PENDING_OUT after a write has occured.
649
650 * configure.in: Add explicit mips-lsi-* target. Use gencode to
651 build simulator.
652 * configure: Re-generate.
653
654 * interp.c (sim_engine_run OLD): Delete explicit call to
655 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
656
657Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
658
659 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
660 interrupt level number to match changed SignalExceptionInterrupt
661 macro.
662
663Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
664
665 * interp.c: #include "itable.h" if WITH_IGEN.
666 (get_insn_name): New function.
667 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
668 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
669
670Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
671
672 * configure: Rebuilt to inhale new common/aclocal.m4.
673
674Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
675
676 * dv-tx3904sio.c: Include sim-assert.h.
677
678Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
679
680 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
681 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
682 Reorganize target-specific sim-hardware checks.
683 * configure: rebuilt.
684 * interp.c (sim_open): For tx39 target boards, set
685 OPERATING_ENVIRONMENT, add tx3904sio devices.
686 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
687 ROM executables. Install dv-sockser into sim-modules list.
688
689 * dv-tx3904irc.c: Compiler warning clean-up.
690 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
691 frequent hw-trace messages.
692
693Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
694
695 * vr.igen (MulAcc): Identify as a vr4100 specific function.
696
697Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
698
699 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
700
701 * vr.igen: New file.
702 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
703 * mips.igen: Define vr4100 model. Include vr.igen.
704Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
705
706 * mips.igen (check_mf_hilo): Correct check.
707
708Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
709
710 * sim-main.h (interrupt_event): Add prototype.
711
712 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
713 register_ptr, register_value.
714 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
715
716 * sim-main.h (tracefh): Make extern.
717
718Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
719
720 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
721 Reduce unnecessarily high timer event frequency.
722 * dv-tx3904cpu.c: Ditto for interrupt event.
723
724Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
725
726 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
727 to allay warnings.
728 (interrupt_event): Made non-static.
729
730 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
731 interchange of configuration values for external vs. internal
732 clock dividers.
733
734Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
735
736 * mips.igen (BREAK): Moved code to here for
737 simulator-reserved break instructions.
738 * gencode.c (build_instruction): Ditto.
739 * interp.c (signal_exception): Code moved from here. Non-
740 reserved instructions now use exception vector, rather
741 than halting sim.
742 * sim-main.h: Moved magic constants to here.
743
744Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
745
746 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
747 register upon non-zero interrupt event level, clear upon zero
748 event value.
749 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
750 by passing zero event value.
751 (*_io_{read,write}_buffer): Endianness fixes.
752 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
753 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
754
755 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
756 serial I/O and timer module at base address 0xFFFF0000.
757
758Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
759
760 * mips.igen (SWC1) : Correct the handling of ReverseEndian
761 and BigEndianCPU.
762
763Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
764
765 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
766 parts.
767 * configure: Update.
768
769Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
770
771 * dv-tx3904tmr.c: New file - implements tx3904 timer.
772 * dv-tx3904{irc,cpu}.c: Mild reformatting.
773 * configure.in: Include tx3904tmr in hw_device list.
774 * configure: Rebuilt.
775 * interp.c (sim_open): Instantiate three timer instances.
776 Fix address typo of tx3904irc instance.
777
778Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
779
780 * interp.c (signal_exception): SystemCall exception now uses
781 the exception vector.
782
783Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
784
785 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
786 to allay warnings.
787
788Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
789
790 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
791
792Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
793
794 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
795
796 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
797 sim-main.h. Declare a struct hw_descriptor instead of struct
798 hw_device_descriptor.
799
800Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
801
802 * mips.igen (do_store_left, do_load_left): Compute nr of left and
803 right bits and then re-align left hand bytes to correct byte
804 lanes. Fix incorrect computation in do_store_left when loading
805 bytes from second word.
806
807Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
808
809 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
810 * interp.c (sim_open): Only create a device tree when HW is
811 enabled.
812
813 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
814 * interp.c (signal_exception): Ditto.
815
816Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
817
818 * gencode.c: Mark BEGEZALL as LIKELY.
819
820Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
821
822 * sim-main.h (ALU32_END): Sign extend 32 bit results.
823 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
824
825Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
826
827 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
828 modules. Recognize TX39 target with "mips*tx39" pattern.
829 * configure: Rebuilt.
830 * sim-main.h (*): Added many macros defining bits in
831 TX39 control registers.
832 (SignalInterrupt): Send actual PC instead of NULL.
833 (SignalNMIReset): New exception type.
834 * interp.c (board): New variable for future use to identify
835 a particular board being simulated.
836 (mips_option_handler,mips_options): Added "--board" option.
837 (interrupt_event): Send actual PC.
838 (sim_open): Make memory layout conditional on board setting.
839 (signal_exception): Initial implementation of hardware interrupt
840 handling. Accept another break instruction variant for simulator
841 exit.
842 (decode_coproc): Implement RFE instruction for TX39.
843 (mips.igen): Decode RFE instruction as such.
844 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
845 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
846 bbegin to implement memory map.
847 * dv-tx3904cpu.c: New file.
848 * dv-tx3904irc.c: New file.
849
850Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
851
852 * mips.igen (check_mt_hilo): Create a separate r3900 version.
853
854Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
855
856 * tx.igen (madd,maddu): Replace calls to check_op_hilo
857 with calls to check_div_hilo.
858
859Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
860
861 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
862 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
863 Add special r3900 version of do_mult_hilo.
864 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
865 with calls to check_mult_hilo.
866 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
867 with calls to check_div_hilo.
868
869Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
870
871 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
872 Document a replacement.
873
874Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
875
876 * interp.c (sim_monitor): Make mon_printf work.
877
878Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
879
880 * sim-main.h (INSN_NAME): New arg `cpu'.
881
882Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
883
884 * configure: Regenerated to track ../common/aclocal.m4 changes.
885
886Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
887
888 * configure: Regenerated to track ../common/aclocal.m4 changes.
889 * config.in: Ditto.
890
891Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
892
893 * acconfig.h: New file.
894 * configure.in: Reverted change of Apr 24; use sinclude again.
895
896Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
897
898 * configure: Regenerated to track ../common/aclocal.m4 changes.
899 * config.in: Ditto.
900
901Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
902
903 * configure.in: Don't call sinclude.
904
905Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
906
907 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
908
909Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
910
911 * mips.igen (ERET): Implement.
912
913 * interp.c (decode_coproc): Return sign-extended EPC.
914
915 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
916
917 * interp.c (signal_exception): Do not ignore Trap.
918 (signal_exception): On TRAP, restart at exception address.
919 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
920 (signal_exception): Update.
921 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
922 so that TRAP instructions are caught.
923
924Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
925
926 * sim-main.h (struct hilo_access, struct hilo_history): Define,
927 contains HI/LO access history.
928 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
929 (HIACCESS, LOACCESS): Delete, replace with
930 (HIHISTORY, LOHISTORY): New macros.
931 (CHECKHILO): Delete all, moved to mips.igen
932
933 * gencode.c (build_instruction): Do not generate checks for
934 correct HI/LO register usage.
935
936 * interp.c (old_engine_run): Delete checks for correct HI/LO
937 register usage.
938
939 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
940 check_mf_cycles): New functions.
941 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
942 do_divu, domultx, do_mult, do_multu): Use.
943
944 * tx.igen ("madd", "maddu"): Use.
945
946Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
947
948 * mips.igen (DSRAV): Use function do_dsrav.
949 (SRAV): Use new function do_srav.
950
951 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
952 (B): Sign extend 11 bit immediate.
953 (EXT-B*): Shift 16 bit immediate left by 1.
954 (ADDIU*): Don't sign extend immediate value.
955
956Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
957
958 * m16run.c (sim_engine_run): Restore CIA after handling an event.
959
960 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
961 functions.
962
963 * mips.igen (delayslot32, nullify_next_insn): New functions.
964 (m16.igen): Always include.
965 (do_*): Add more tracing.
966
967 * m16.igen (delayslot16): Add NIA argument, could be called by a
968 32 bit MIPS16 instruction.
969
970 * interp.c (ifetch16): Move function from here.
971 * sim-main.c (ifetch16): To here.
972
973 * sim-main.c (ifetch16, ifetch32): Update to match current
974 implementations of LH, LW.
975 (signal_exception): Don't print out incorrect hex value of illegal
976 instruction.
977
978Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
979
980 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
981 instruction.
982
983 * m16.igen: Implement MIPS16 instructions.
984
985 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
986 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
987 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
988 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
989 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
990 bodies of corresponding code from 32 bit insn to these. Also used
991 by MIPS16 versions of functions.
992
993 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
994 (IMEM16): Drop NR argument from macro.
995
996Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
997
998 * Makefile.in (SIM_OBJS): Add sim-main.o.
999
1000 * sim-main.h (address_translation, load_memory, store_memory,
1001 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1002 as INLINE_SIM_MAIN.
1003 (pr_addr, pr_uword64): Declare.
1004 (sim-main.c): Include when H_REVEALS_MODULE_P.
1005
1006 * interp.c (address_translation, load_memory, store_memory,
1007 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1008 from here.
1009 * sim-main.c: To here. Fix compilation problems.
1010
1011 * configure.in: Enable inlining.
1012 * configure: Re-config.
1013
1014Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1015
1016 * configure: Regenerated to track ../common/aclocal.m4 changes.
1017
1018Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1019
1020 * mips.igen: Include tx.igen.
1021 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1022 * tx.igen: New file, contains MADD and MADDU.
1023
1024 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1025 the hardwired constant `7'.
1026 (store_memory): Ditto.
1027 (LOADDRMASK): Move definition to sim-main.h.
1028
1029 mips.igen (MTC0): Enable for r3900.
1030 (ADDU): Add trace.
1031
1032 mips.igen (do_load_byte): Delete.
1033 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1034 do_store_right): New functions.
1035 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1036
1037 configure.in: Let the tx39 use igen again.
1038 configure: Update.
1039
1040Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1041
1042 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1043 not an address sized quantity. Return zero for cache sizes.
1044
1045Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1046
1047 * mips.igen (r3900): r3900 does not support 64 bit integer
1048 operations.
1049
1050Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1051
1052 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1053 than igen one.
1054 * configure : Rebuild.
1055
1056Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1057
1058 * configure: Regenerated to track ../common/aclocal.m4 changes.
1059
1060Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1061
1062 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1063
1064Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1065
1066 * configure: Regenerated to track ../common/aclocal.m4 changes.
1067 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1068
1069Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1070
1071 * configure: Regenerated to track ../common/aclocal.m4 changes.
1072
1073Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1074
1075 * interp.c (Max, Min): Comment out functions. Not yet used.
1076
1077Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1078
1079 * configure: Regenerated to track ../common/aclocal.m4 changes.
1080
1081Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1082
1083 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1084 configurable settings for stand-alone simulator.
1085
1086 * configure.in: Added X11 search, just in case.
1087
1088 * configure: Regenerated.
1089
1090Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1091
1092 * interp.c (sim_write, sim_read, load_memory, store_memory):
1093 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1094
1095Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1096
1097 * sim-main.h (GETFCC): Return an unsigned value.
1098
1099Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1100
1101 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1102 (DADD): Result destination is RD not RT.
1103
1104Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1105
1106 * sim-main.h (HIACCESS, LOACCESS): Always define.
1107
1108 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1109
1110 * interp.c (sim_info): Delete.
1111
1112Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1113
1114 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1115 (mips_option_handler): New argument `cpu'.
1116 (sim_open): Update call to sim_add_option_table.
1117
1118Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1119
1120 * mips.igen (CxC1): Add tracing.
1121
1122Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1123
1124 * sim-main.h (Max, Min): Declare.
1125
1126 * interp.c (Max, Min): New functions.
1127
1128 * mips.igen (BC1): Add tracing.
1129
1130Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1131
1132 * interp.c Added memory map for stack in vr4100
1133
1134Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1135
1136 * interp.c (load_memory): Add missing "break"'s.
1137
1138Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1139
1140 * interp.c (sim_store_register, sim_fetch_register): Pass in
1141 length parameter. Return -1.
1142
1143Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1144
1145 * interp.c: Added hardware init hook, fixed warnings.
1146
1147Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1148
1149 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1150
1151Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1152
1153 * interp.c (ifetch16): New function.
1154
1155 * sim-main.h (IMEM32): Rename IMEM.
1156 (IMEM16_IMMED): Define.
1157 (IMEM16): Define.
1158 (DELAY_SLOT): Update.
1159
1160 * m16run.c (sim_engine_run): New file.
1161
1162 * m16.igen: All instructions except LB.
1163 (LB): Call do_load_byte.
1164 * mips.igen (do_load_byte): New function.
1165 (LB): Call do_load_byte.
1166
1167 * mips.igen: Move spec for insn bit size and high bit from here.
1168 * Makefile.in (tmp-igen, tmp-m16): To here.
1169
1170 * m16.dc: New file, decode mips16 instructions.
1171
1172 * Makefile.in (SIM_NO_ALL): Define.
1173 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1174
1175Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1176
1177 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1178 point unit to 32 bit registers.
1179 * configure: Re-generate.
1180
1181Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1182
1183 * configure.in (sim_use_gen): Make IGEN the default simulator
1184 generator for generic 32 and 64 bit mips targets.
1185 * configure: Re-generate.
1186
1187Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1188
1189 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1190 bitsize.
1191
1192 * interp.c (sim_fetch_register, sim_store_register): Read/write
1193 FGR from correct location.
1194 (sim_open): Set size of FGR's according to
1195 WITH_TARGET_FLOATING_POINT_BITSIZE.
1196
1197 * sim-main.h (FGR): Store floating point registers in a separate
1198 array.
1199
1200Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1201
1202 * configure: Regenerated to track ../common/aclocal.m4 changes.
1203
1204Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1205
1206 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1207
1208 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1209
1210 * interp.c (pending_tick): New function. Deliver pending writes.
1211
1212 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1213 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1214 it can handle mixed sized quantites and single bits.
1215
1216Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1217
1218 * interp.c (oengine.h): Do not include when building with IGEN.
1219 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1220 (sim_info): Ditto for PROCESSOR_64BIT.
1221 (sim_monitor): Replace ut_reg with unsigned_word.
1222 (*): Ditto for t_reg.
1223 (LOADDRMASK): Define.
1224 (sim_open): Remove defunct check that host FP is IEEE compliant,
1225 using software to emulate floating point.
1226 (value_fpr, ...): Always compile, was conditional on HASFPU.
1227
1228Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1229
1230 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1231 size.
1232
1233 * interp.c (SD, CPU): Define.
1234 (mips_option_handler): Set flags in each CPU.
1235 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1236 (sim_close): Do not clear STATE, deleted anyway.
1237 (sim_write, sim_read): Assume CPU zero's vm should be used for
1238 data transfers.
1239 (sim_create_inferior): Set the PC for all processors.
1240 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1241 argument.
1242 (mips16_entry): Pass correct nr of args to store_word, load_word.
1243 (ColdReset): Cold reset all cpu's.
1244 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1245 (sim_monitor, load_memory, store_memory, signal_exception): Use
1246 `CPU' instead of STATE_CPU.
1247
1248
1249 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1250 SD or CPU_.
1251
1252 * sim-main.h (signal_exception): Add sim_cpu arg.
1253 (SignalException*): Pass both SD and CPU to signal_exception.
1254 * interp.c (signal_exception): Update.
1255
1256 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1257 Ditto
1258 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1259 address_translation): Ditto
1260 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1261
1262Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1263
1264 * configure: Regenerated to track ../common/aclocal.m4 changes.
1265
1266Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1267
1268 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1269
1270 * mips.igen (model): Map processor names onto BFD name.
1271
1272 * sim-main.h (CPU_CIA): Delete.
1273 (SET_CIA, GET_CIA): Define
1274
1275Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1276
1277 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1278 regiser.
1279
1280 * configure.in (default_endian): Configure a big-endian simulator
1281 by default.
1282 * configure: Re-generate.
1283
1284Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1285
1286 * configure: Regenerated to track ../common/aclocal.m4 changes.
1287
1288Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1289
1290 * interp.c (sim_monitor): Handle Densan monitor outbyte
1291 and inbyte functions.
1292
12931997-12-29 Felix Lee <flee@cygnus.com>
1294
1295 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1296
1297Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1298
1299 * Makefile.in (tmp-igen): Arrange for $zero to always be
1300 reset to zero after every instruction.
1301
1302Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1303
1304 * configure: Regenerated to track ../common/aclocal.m4 changes.
1305 * config.in: Ditto.
1306
1307Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1308
1309 * mips.igen (MSUB): Fix to work like MADD.
1310 * gencode.c (MSUB): Similarly.
1311
1312Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1313
1314 * configure: Regenerated to track ../common/aclocal.m4 changes.
1315
1316Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1317
1318 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1319
1320Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1321
1322 * sim-main.h (sim-fpu.h): Include.
1323
1324 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1325 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1326 using host independant sim_fpu module.
1327
1328Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1329
1330 * interp.c (signal_exception): Report internal errors with SIGABRT
1331 not SIGQUIT.
1332
1333 * sim-main.h (C0_CONFIG): New register.
1334 (signal.h): No longer include.
1335
1336 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1337
1338Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1339
1340 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1341
1342Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1343
1344 * mips.igen: Tag vr5000 instructions.
1345 (ANDI): Was missing mipsIV model, fix assembler syntax.
1346 (do_c_cond_fmt): New function.
1347 (C.cond.fmt): Handle mips I-III which do not support CC field
1348 separatly.
1349 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1350 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1351 in IV3.2 spec.
1352 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1353 vr5000 which saves LO in a GPR separatly.
1354
1355 * configure.in (enable-sim-igen): For vr5000, select vr5000
1356 specific instructions.
1357 * configure: Re-generate.
1358
1359Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1360
1361 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1362
1363 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1364 fmt_uninterpreted_64 bit cases to switch. Convert to
1365 fmt_formatted,
1366
1367 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1368
1369 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1370 as specified in IV3.2 spec.
1371 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1372
1373Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1374
1375 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1376 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1377 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1378 PENDING_FILL versions of instructions. Simplify.
1379 (X): New function.
1380 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1381 instructions.
1382 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1383 a signed value.
1384 (MTHI, MFHI): Disable code checking HI-LO.
1385
1386 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1387 global.
1388 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1389
1390Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1391
1392 * gencode.c (build_mips16_operands): Replace IPC with cia.
1393
1394 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1395 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1396 IPC to `cia'.
1397 (UndefinedResult): Replace function with macro/function
1398 combination.
1399 (sim_engine_run): Don't save PC in IPC.
1400
1401 * sim-main.h (IPC): Delete.
1402
1403
1404 * interp.c (signal_exception, store_word, load_word,
1405 address_translation, load_memory, store_memory, cache_op,
1406 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1407 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1408 current instruction address - cia - argument.
1409 (sim_read, sim_write): Call address_translation directly.
1410 (sim_engine_run): Rename variable vaddr to cia.
1411 (signal_exception): Pass cia to sim_monitor
1412
1413 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1414 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1415 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1416
1417 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1418 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1419 SIM_ASSERT.
1420
1421 * interp.c (signal_exception): Pass restart address to
1422 sim_engine_restart.
1423
1424 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1425 idecode.o): Add dependency.
1426
1427 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1428 Delete definitions
1429 (DELAY_SLOT): Update NIA not PC with branch address.
1430 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1431
1432 * mips.igen: Use CIA not PC in branch calculations.
1433 (illegal): Call SignalException.
1434 (BEQ, ADDIU): Fix assembler.
1435
1436Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1437
1438 * m16.igen (JALX): Was missing.
1439
1440 * configure.in (enable-sim-igen): New configuration option.
1441 * configure: Re-generate.
1442
1443 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1444
1445 * interp.c (load_memory, store_memory): Delete parameter RAW.
1446 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1447 bypassing {load,store}_memory.
1448
1449 * sim-main.h (ByteSwapMem): Delete definition.
1450
1451 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1452
1453 * interp.c (sim_do_command, sim_commands): Delete mips specific
1454 commands. Handled by module sim-options.
1455
1456 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1457 (WITH_MODULO_MEMORY): Define.
1458
1459 * interp.c (sim_info): Delete code printing memory size.
1460
1461 * interp.c (mips_size): Nee sim_size, delete function.
1462 (power2): Delete.
1463 (monitor, monitor_base, monitor_size): Delete global variables.
1464 (sim_open, sim_close): Delete code creating monitor and other
1465 memory regions. Use sim-memopts module, via sim_do_commandf, to
1466 manage memory regions.
1467 (load_memory, store_memory): Use sim-core for memory model.
1468
1469 * interp.c (address_translation): Delete all memory map code
1470 except line forcing 32 bit addresses.
1471
1472Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1473
1474 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1475 trace options.
1476
1477 * interp.c (logfh, logfile): Delete globals.
1478 (sim_open, sim_close): Delete code opening & closing log file.
1479 (mips_option_handler): Delete -l and -n options.
1480 (OPTION mips_options): Ditto.
1481
1482 * interp.c (OPTION mips_options): Rename option trace to dinero.
1483 (mips_option_handler): Update.
1484
1485Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1486
1487 * interp.c (fetch_str): New function.
1488 (sim_monitor): Rewrite using sim_read & sim_write.
1489 (sim_open): Check magic number.
1490 (sim_open): Write monitor vectors into memory using sim_write.
1491 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1492 (sim_read, sim_write): Simplify - transfer data one byte at a
1493 time.
1494 (load_memory, store_memory): Clarify meaning of parameter RAW.
1495
1496 * sim-main.h (isHOST): Defete definition.
1497 (isTARGET): Mark as depreciated.
1498 (address_translation): Delete parameter HOST.
1499
1500 * interp.c (address_translation): Delete parameter HOST.
1501
1502Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1503
1504 * mips.igen:
1505
1506 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1507 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1508
1509Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1510
1511 * mips.igen: Add model filter field to records.
1512
1513Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1514
1515 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1516
1517 interp.c (sim_engine_run): Do not compile function sim_engine_run
1518 when WITH_IGEN == 1.
1519
1520 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1521 target architecture.
1522
1523 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1524 igen. Replace with configuration variables sim_igen_flags /
1525 sim_m16_flags.
1526
1527 * m16.igen: New file. Copy mips16 insns here.
1528 * mips.igen: From here.
1529
1530Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1531
1532 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1533 to top.
1534 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1535
1536Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1537
1538 * gencode.c (build_instruction): Follow sim_write's lead in using
1539 BigEndianMem instead of !ByteSwapMem.
1540
1541Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1542
1543 * configure.in (sim_gen): Dependent on target, select type of
1544 generator. Always select old style generator.
1545
1546 configure: Re-generate.
1547
1548 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1549 targets.
1550 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1551 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1552 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1553 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1554 SIM_@sim_gen@_*, set by autoconf.
1555
1556Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1557
1558 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1559
1560 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1561 CURRENT_FLOATING_POINT instead.
1562
1563 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1564 (address_translation): Raise exception InstructionFetch when
1565 translation fails and isINSTRUCTION.
1566
1567 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1568 sim_engine_run): Change type of of vaddr and paddr to
1569 address_word.
1570 (address_translation, prefetch, load_memory, store_memory,
1571 cache_op): Change type of vAddr and pAddr to address_word.
1572
1573 * gencode.c (build_instruction): Change type of vaddr and paddr to
1574 address_word.
1575
1576Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1577
1578 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1579 macro to obtain result of ALU op.
1580
1581Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1582
1583 * interp.c (sim_info): Call profile_print.
1584
1585Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1586
1587 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1588
1589 * sim-main.h (WITH_PROFILE): Do not define, defined in
1590 common/sim-config.h. Use sim-profile module.
1591 (simPROFILE): Delete defintion.
1592
1593 * interp.c (PROFILE): Delete definition.
1594 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1595 (sim_close): Delete code writing profile histogram.
1596 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1597 Delete.
1598 (sim_engine_run): Delete code profiling the PC.
1599
1600Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1601
1602 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1603
1604 * interp.c (sim_monitor): Make register pointers of type
1605 unsigned_word*.
1606
1607 * sim-main.h: Make registers of type unsigned_word not
1608 signed_word.
1609
1610Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1611
1612 * interp.c (sync_operation): Rename from SyncOperation, make
1613 global, add SD argument.
1614 (prefetch): Rename from Prefetch, make global, add SD argument.
1615 (decode_coproc): Make global.
1616
1617 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1618
1619 * gencode.c (build_instruction): Generate DecodeCoproc not
1620 decode_coproc calls.
1621
1622 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1623 (SizeFGR): Move to sim-main.h
1624 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1625 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1626 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1627 sim-main.h.
1628 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1629 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1630 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1631 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1632 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1633 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1634
1635 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1636 exception.
1637 (sim-alu.h): Include.
1638 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1639 (sim_cia): Typedef to instruction_address.
1640
1641Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1642
1643 * Makefile.in (interp.o): Rename generated file engine.c to
1644 oengine.c.
1645
1646 * interp.c: Update.
1647
1648Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1649
1650 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1651
1652Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1653
1654 * gencode.c (build_instruction): For "FPSQRT", output correct
1655 number of arguments to Recip.
1656
1657Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1658
1659 * Makefile.in (interp.o): Depends on sim-main.h
1660
1661 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1662
1663 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1664 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1665 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1666 STATE, DSSTATE): Define
1667 (GPR, FGRIDX, ..): Define.
1668
1669 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1670 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1671 (GPR, FGRIDX, ...): Delete macros.
1672
1673 * interp.c: Update names to match defines from sim-main.h
1674
1675Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1676
1677 * interp.c (sim_monitor): Add SD argument.
1678 (sim_warning): Delete. Replace calls with calls to
1679 sim_io_eprintf.
1680 (sim_error): Delete. Replace calls with sim_io_error.
1681 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1682 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1683 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1684 argument.
1685 (mips_size): Rename from sim_size. Add SD argument.
1686
1687 * interp.c (simulator): Delete global variable.
1688 (callback): Delete global variable.
1689 (mips_option_handler, sim_open, sim_write, sim_read,
1690 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1691 sim_size,sim_monitor): Use sim_io_* not callback->*.
1692 (sim_open): ZALLOC simulator struct.
1693 (PROFILE): Do not define.
1694
1695Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1696
1697 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1698 support.h with corresponding code.
1699
1700 * sim-main.h (word64, uword64), support.h: Move definition to
1701 sim-main.h.
1702 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1703
1704 * support.h: Delete
1705 * Makefile.in: Update dependencies
1706 * interp.c: Do not include.
1707
1708Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1709
1710 * interp.c (address_translation, load_memory, store_memory,
1711 cache_op): Rename to from AddressTranslation et.al., make global,
1712 add SD argument
1713
1714 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1715 CacheOp): Define.
1716
1717 * interp.c (SignalException): Rename to signal_exception, make
1718 global.
1719
1720 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1721
1722 * sim-main.h (SignalException, SignalExceptionInterrupt,
1723 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1724 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1725 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1726 Define.
1727
1728 * interp.c, support.h: Use.
1729
1730Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1731
1732 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1733 to value_fpr / store_fpr. Add SD argument.
1734 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1735 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1736
1737 * sim-main.h (ValueFPR, StoreFPR): Define.
1738
1739Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1740
1741 * interp.c (sim_engine_run): Check consistency between configure
1742 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1743 and HASFPU.
1744
1745 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1746 (mips_fpu): Configure WITH_FLOATING_POINT.
1747 (mips_endian): Configure WITH_TARGET_ENDIAN.
1748 * configure: Update.
1749
1750Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1751
1752 * configure: Regenerated to track ../common/aclocal.m4 changes.
1753
1754Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1755
1756 * configure: Regenerated.
1757
1758Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1759
1760 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1761
1762Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1763
1764 * gencode.c (print_igen_insn_models): Assume certain architectures
1765 include all mips* instructions.
1766 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1767 instruction.
1768
1769 * Makefile.in (tmp.igen): Add target. Generate igen input from
1770 gencode file.
1771
1772 * gencode.c (FEATURE_IGEN): Define.
1773 (main): Add --igen option. Generate output in igen format.
1774 (process_instructions): Format output according to igen option.
1775 (print_igen_insn_format): New function.
1776 (print_igen_insn_models): New function.
1777 (process_instructions): Only issue warnings and ignore
1778 instructions when no FEATURE_IGEN.
1779
1780Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1781
1782 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1783 MIPS targets.
1784
1785Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1786
1787 * configure: Regenerated to track ../common/aclocal.m4 changes.
1788
1789Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1790
1791 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1792 SIM_RESERVED_BITS): Delete, moved to common.
1793 (SIM_EXTRA_CFLAGS): Update.
1794
1795Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1796
1797 * configure.in: Configure non-strict memory alignment.
1798 * configure: Regenerated to track ../common/aclocal.m4 changes.
1799
1800Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1801
1802 * configure: Regenerated to track ../common/aclocal.m4 changes.
1803
1804Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1805
1806 * gencode.c (SDBBP,DERET): Added (3900) insns.
1807 (RFE): Turn on for 3900.
1808 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1809 (dsstate): Made global.
1810 (SUBTARGET_R3900): Added.
1811 (CANCELDELAYSLOT): New.
1812 (SignalException): Ignore SystemCall rather than ignore and
1813 terminate. Add DebugBreakPoint handling.
1814 (decode_coproc): New insns RFE, DERET; and new registers Debug
1815 and DEPC protected by SUBTARGET_R3900.
1816 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1817 bits explicitly.
1818 * Makefile.in,configure.in: Add mips subtarget option.
1819 * configure: Update.
1820
1821Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1822
1823 * gencode.c: Add r3900 (tx39).
1824
1825
1826Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1827
1828 * gencode.c (build_instruction): Don't need to subtract 4 for
1829 JALR, just 2.
1830
1831Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1832
1833 * interp.c: Correct some HASFPU problems.
1834
1835Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1836
1837 * configure: Regenerated to track ../common/aclocal.m4 changes.
1838
1839Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1840
1841 * interp.c (mips_options): Fix samples option short form, should
1842 be `x'.
1843
1844Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1845
1846 * interp.c (sim_info): Enable info code. Was just returning.
1847
1848Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1849
1850 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1851 MFC0.
1852
1853Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1854
1855 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1856 constants.
1857 (build_instruction): Ditto for LL.
1858
1859Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1860
1861 * configure: Regenerated to track ../common/aclocal.m4 changes.
1862
1863Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1864
1865 * configure: Regenerated to track ../common/aclocal.m4 changes.
1866 * config.in: Ditto.
1867
1868Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1869
1870 * interp.c (sim_open): Add call to sim_analyze_program, update
1871 call to sim_config.
1872
1873Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1874
1875 * interp.c (sim_kill): Delete.
1876 (sim_create_inferior): Add ABFD argument. Set PC from same.
1877 (sim_load): Move code initializing trap handlers from here.
1878 (sim_open): To here.
1879 (sim_load): Delete, use sim-hload.c.
1880
1881 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1882
1883Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1884
1885 * configure: Regenerated to track ../common/aclocal.m4 changes.
1886 * config.in: Ditto.
1887
1888Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1889
1890 * interp.c (sim_open): Add ABFD argument.
1891 (sim_load): Move call to sim_config from here.
1892 (sim_open): To here. Check return status.
1893
1894Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1895
1896 * gencode.c (build_instruction): Two arg MADD should
1897 not assign result to $0.
1898
1899Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1900
1901 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1902 * sim/mips/configure.in: Regenerate.
1903
1904Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1905
1906 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1907 signed8, unsigned8 et.al. types.
1908
1909 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1910 hosts when selecting subreg.
1911
1912Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1913
1914 * interp.c (sim_engine_run): Reset the ZERO register to zero
1915 regardless of FEATURE_WARN_ZERO.
1916 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1917
1918Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1919
1920 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1921 (SignalException): For BreakPoints ignore any mode bits and just
1922 save the PC.
1923 (SignalException): Always set the CAUSE register.
1924
1925Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1926
1927 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1928 exception has been taken.
1929
1930 * interp.c: Implement the ERET and mt/f sr instructions.
1931
1932Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1933
1934 * interp.c (SignalException): Don't bother restarting an
1935 interrupt.
1936
1937Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1938
1939 * interp.c (SignalException): Really take an interrupt.
1940 (interrupt_event): Only deliver interrupts when enabled.
1941
1942Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1943
1944 * interp.c (sim_info): Only print info when verbose.
1945 (sim_info) Use sim_io_printf for output.
1946
1947Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1948
1949 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1950 mips architectures.
1951
1952Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1953
1954 * interp.c (sim_do_command): Check for common commands if a
1955 simulator specific command fails.
1956
1957Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
1958
1959 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1960 and simBE when DEBUG is defined.
1961
1962Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
1963
1964 * interp.c (interrupt_event): New function. Pass exception event
1965 onto exception handler.
1966
1967 * configure.in: Check for stdlib.h.
1968 * configure: Regenerate.
1969
1970 * gencode.c (build_instruction): Add UNUSED attribute to tempS
1971 variable declaration.
1972 (build_instruction): Initialize memval1.
1973 (build_instruction): Add UNUSED attribute to byte, bigend,
1974 reverse.
1975 (build_operands): Ditto.
1976
1977 * interp.c: Fix GCC warnings.
1978 (sim_get_quit_code): Delete.
1979
1980 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1981 * Makefile.in: Ditto.
1982 * configure: Re-generate.
1983
1984 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1985
1986Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1987
1988 * interp.c (mips_option_handler): New function parse argumes using
1989 sim-options.
1990 (myname): Replace with STATE_MY_NAME.
1991 (sim_open): Delete check for host endianness - performed by
1992 sim_config.
1993 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1994 (sim_open): Move much of the initialization from here.
1995 (sim_load): To here. After the image has been loaded and
1996 endianness set.
1997 (sim_open): Move ColdReset from here.
1998 (sim_create_inferior): To here.
1999 (sim_open): Make FP check less dependant on host endianness.
2000
2001 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2002 run.
2003 * interp.c (sim_set_callbacks): Delete.
2004
2005 * interp.c (membank, membank_base, membank_size): Replace with
2006 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2007 (sim_open): Remove call to callback->init. gdb/run do this.
2008
2009 * interp.c: Update
2010
2011 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2012
2013 * interp.c (big_endian_p): Delete, replaced by
2014 current_target_byte_order.
2015
2016Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2017
2018 * interp.c (host_read_long, host_read_word, host_swap_word,
2019 host_swap_long): Delete. Using common sim-endian.
2020 (sim_fetch_register, sim_store_register): Use H2T.
2021 (pipeline_ticks): Delete. Handled by sim-events.
2022 (sim_info): Update.
2023 (sim_engine_run): Update.
2024
2025Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2026
2027 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2028 reason from here.
2029 (SignalException): To here. Signal using sim_engine_halt.
2030 (sim_stop_reason): Delete, moved to common.
2031
2032Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2033
2034 * interp.c (sim_open): Add callback argument.
2035 (sim_set_callbacks): Delete SIM_DESC argument.
2036 (sim_size): Ditto.
2037
2038Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2039
2040 * Makefile.in (SIM_OBJS): Add common modules.
2041
2042 * interp.c (sim_set_callbacks): Also set SD callback.
2043 (set_endianness, xfer_*, swap_*): Delete.
2044 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2045 Change to functions using sim-endian macros.
2046 (control_c, sim_stop): Delete, use common version.
2047 (simulate): Convert into.
2048 (sim_engine_run): This function.
2049 (sim_resume): Delete.
2050
2051 * interp.c (simulation): New variable - the simulator object.
2052 (sim_kind): Delete global - merged into simulation.
2053 (sim_load): Cleanup. Move PC assignment from here.
2054 (sim_create_inferior): To here.
2055
2056 * sim-main.h: New file.
2057 * interp.c (sim-main.h): Include.
2058
2059Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2060
2061 * configure: Regenerated to track ../common/aclocal.m4 changes.
2062
2063Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2064
2065 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2066
2067Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2068
2069 * gencode.c (build_instruction): DIV instructions: check
2070 for division by zero and integer overflow before using
2071 host's division operation.
2072
2073Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2074
2075 * Makefile.in (SIM_OBJS): Add sim-load.o.
2076 * interp.c: #include bfd.h.
2077 (target_byte_order): Delete.
2078 (sim_kind, myname, big_endian_p): New static locals.
2079 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2080 after argument parsing. Recognize -E arg, set endianness accordingly.
2081 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2082 load file into simulator. Set PC from bfd.
2083 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2084 (set_endianness): Use big_endian_p instead of target_byte_order.
2085
2086Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2087
2088 * interp.c (sim_size): Delete prototype - conflicts with
2089 definition in remote-sim.h. Correct definition.
2090
2091Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2092
2093 * configure: Regenerated to track ../common/aclocal.m4 changes.
2094 * config.in: Ditto.
2095
2096Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2097
2098 * interp.c (sim_open): New arg `kind'.
2099
2100 * configure: Regenerated to track ../common/aclocal.m4 changes.
2101
2102Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2103
2104 * configure: Regenerated to track ../common/aclocal.m4 changes.
2105
2106Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2107
2108 * interp.c (sim_open): Set optind to 0 before calling getopt.
2109
2110Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2111
2112 * configure: Regenerated to track ../common/aclocal.m4 changes.
2113
2114Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2115
2116 * interp.c : Replace uses of pr_addr with pr_uword64
2117 where the bit length is always 64 independent of SIM_ADDR.
2118 (pr_uword64) : added.
2119
2120Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2121
2122 * configure: Re-generate.
2123
2124Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2125
2126 * configure: Regenerate to track ../common/aclocal.m4 changes.
2127
2128Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2129
2130 * interp.c (sim_open): New SIM_DESC result. Argument is now
2131 in argv form.
2132 (other sim_*): New SIM_DESC argument.
2133
2134Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2135
2136 * interp.c: Fix printing of addresses for non-64-bit targets.
2137 (pr_addr): Add function to print address based on size.
2138
2139Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2140
2141 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2142
2143Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2144
2145 * gencode.c (build_mips16_operands): Correct computation of base
2146 address for extended PC relative instruction.
2147
2148Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2149
2150 * interp.c (mips16_entry): Add support for floating point cases.
2151 (SignalException): Pass floating point cases to mips16_entry.
2152 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2153 registers.
2154 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2155 or fmt_word.
2156 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2157 and then set the state to fmt_uninterpreted.
2158 (COP_SW): Temporarily set the state to fmt_word while calling
2159 ValueFPR.
2160
2161Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2162
2163 * gencode.c (build_instruction): The high order may be set in the
2164 comparison flags at any ISA level, not just ISA 4.
2165
2166Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2167
2168 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2169 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2170 * configure.in: sinclude ../common/aclocal.m4.
2171 * configure: Regenerated.
2172
2173Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2174
2175 * configure: Rebuild after change to aclocal.m4.
2176
2177Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2178
2179 * configure configure.in Makefile.in: Update to new configure
2180 scheme which is more compatible with WinGDB builds.
2181 * configure.in: Improve comment on how to run autoconf.
2182 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2183 * Makefile.in: Use autoconf substitution to install common
2184 makefile fragment.
2185
2186Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2187
2188 * gencode.c (build_instruction): Use BigEndianCPU instead of
2189 ByteSwapMem.
2190
2191Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2192
2193 * interp.c (sim_monitor): Make output to stdout visible in
2194 wingdb's I/O log window.
2195
2196Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2197
2198 * support.h: Undo previous change to SIGTRAP
2199 and SIGQUIT values.
2200
2201Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2202
2203 * interp.c (store_word, load_word): New static functions.
2204 (mips16_entry): New static function.
2205 (SignalException): Look for mips16 entry and exit instructions.
2206 (simulate): Use the correct index when setting fpr_state after
2207 doing a pending move.
2208
2209Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2210
2211 * interp.c: Fix byte-swapping code throughout to work on
2212 both little- and big-endian hosts.
2213
2214Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2215
2216 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2217 with gdb/config/i386/xm-windows.h.
2218
2219Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2220
2221 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2222 that messes up arithmetic shifts.
2223
2224Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2225
2226 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2227 SIGTRAP and SIGQUIT for _WIN32.
2228
2229Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2230
2231 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2232 force a 64 bit multiplication.
2233 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2234 destination register is 0, since that is the default mips16 nop
2235 instruction.
2236
2237Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2238
2239 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2240 (build_endian_shift): Don't check proc64.
2241 (build_instruction): Always set memval to uword64. Cast op2 to
2242 uword64 when shifting it left in memory instructions. Always use
2243 the same code for stores--don't special case proc64.
2244
2245 * gencode.c (build_mips16_operands): Fix base PC value for PC
2246 relative operands.
2247 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2248 jal instruction.
2249 * interp.c (simJALDELAYSLOT): Define.
2250 (JALDELAYSLOT): Define.
2251 (INDELAYSLOT, INJALDELAYSLOT): Define.
2252 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2253
2254Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2255
2256 * interp.c (sim_open): add flush_cache as a PMON routine
2257 (sim_monitor): handle flush_cache by ignoring it
2258
2259Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2260
2261 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2262 BigEndianMem.
2263 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2264 (BigEndianMem): Rename to ByteSwapMem and change sense.
2265 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2266 BigEndianMem references to !ByteSwapMem.
2267 (set_endianness): New function, with prototype.
2268 (sim_open): Call set_endianness.
2269 (sim_info): Use simBE instead of BigEndianMem.
2270 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2271 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2272 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2273 ifdefs, keeping the prototype declaration.
2274 (swap_word): Rewrite correctly.
2275 (ColdReset): Delete references to CONFIG. Delete endianness related
2276 code; moved to set_endianness.
2277
2278Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2279
2280 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2281 * interp.c (CHECKHILO): Define away.
2282 (simSIGINT): New macro.
2283 (membank_size): Increase from 1MB to 2MB.
2284 (control_c): New function.
2285 (sim_resume): Rename parameter signal to signal_number. Add local
2286 variable prev. Call signal before and after simulate.
2287 (sim_stop_reason): Add simSIGINT support.
2288 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2289 functions always.
2290 (sim_warning): Delete call to SignalException. Do call printf_filtered
2291 if logfh is NULL.
2292 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2293 a call to sim_warning.
2294
2295Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2296
2297 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2298 16 bit instructions.
2299
2300Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2301
2302 Add support for mips16 (16 bit MIPS implementation):
2303 * gencode.c (inst_type): Add mips16 instruction encoding types.
2304 (GETDATASIZEINSN): Define.
2305 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2306 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2307 mtlo.
2308 (MIPS16_DECODE): New table, for mips16 instructions.
2309 (bitmap_val): New static function.
2310 (struct mips16_op): Define.
2311 (mips16_op_table): New table, for mips16 operands.
2312 (build_mips16_operands): New static function.
2313 (process_instructions): If PC is odd, decode a mips16
2314 instruction. Break out instruction handling into new
2315 build_instruction function.
2316 (build_instruction): New static function, broken out of
2317 process_instructions. Check modifiers rather than flags for SHIFT
2318 bit count and m[ft]{hi,lo} direction.
2319 (usage): Pass program name to fprintf.
2320 (main): Remove unused variable this_option_optind. Change
2321 ``*loptarg++'' to ``loptarg++''.
2322 (my_strtoul): Parenthesize && within ||.
2323 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2324 (simulate): If PC is odd, fetch a 16 bit instruction, and
2325 increment PC by 2 rather than 4.
2326 * configure.in: Add case for mips16*-*-*.
2327 * configure: Rebuild.
2328
2329Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2330
2331 * interp.c: Allow -t to enable tracing in standalone simulator.
2332 Fix garbage output in trace file and error messages.
2333
2334Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2335
2336 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2337 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2338 * configure.in: Simplify using macros in ../common/aclocal.m4.
2339 * configure: Regenerated.
2340 * tconfig.in: New file.
2341
2342Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2343
2344 * interp.c: Fix bugs in 64-bit port.
2345 Use ansi function declarations for msvc compiler.
2346 Initialize and test file pointer in trace code.
2347 Prevent duplicate definition of LAST_EMED_REGNUM.
2348
2349Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2350
2351 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2352
2353Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2354
2355 * interp.c (SignalException): Check for explicit terminating
2356 breakpoint value.
2357 * gencode.c: Pass instruction value through SignalException()
2358 calls for Trap, Breakpoint and Syscall.
2359
2360Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2361
2362 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2363 only used on those hosts that provide it.
2364 * configure.in: Add sqrt() to list of functions to be checked for.
2365 * config.in: Re-generated.
2366 * configure: Re-generated.
2367
2368Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2369
2370 * gencode.c (process_instructions): Call build_endian_shift when
2371 expanding STORE RIGHT, to fix swr.
2372 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2373 clear the high bits.
2374 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2375 Fix float to int conversions to produce signed values.
2376
2377Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2378
2379 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2380 (process_instructions): Correct handling of nor instruction.
2381 Correct shift count for 32 bit shift instructions. Correct sign
2382 extension for arithmetic shifts to not shift the number of bits in
2383 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2384 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2385 Fix madd.
2386 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2387 It's OK to have a mult follow a mult. What's not OK is to have a
2388 mult follow an mfhi.
2389 (Convert): Comment out incorrect rounding code.
2390
2391Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2392
2393 * interp.c (sim_monitor): Improved monitor printf
2394 simulation. Tidied up simulator warnings, and added "--log" option
2395 for directing warning message output.
2396 * gencode.c: Use sim_warning() rather than WARNING macro.
2397
2398Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2399
2400 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2401 getopt1.o, rather than on gencode.c. Link objects together.
2402 Don't link against -liberty.
2403 (gencode.o, getopt.o, getopt1.o): New targets.
2404 * gencode.c: Include <ctype.h> and "ansidecl.h".
2405 (AND): Undefine after including "ansidecl.h".
2406 (ULONG_MAX): Define if not defined.
2407 (OP_*): Don't define macros; now defined in opcode/mips.h.
2408 (main): Call my_strtoul rather than strtoul.
2409 (my_strtoul): New static function.
2410
2411Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2412
2413 * gencode.c (process_instructions): Generate word64 and uword64
2414 instead of `long long' and `unsigned long long' data types.
2415 * interp.c: #include sysdep.h to get signals, and define default
2416 for SIGBUS.
2417 * (Convert): Work around for Visual-C++ compiler bug with type
2418 conversion.
2419 * support.h: Make things compile under Visual-C++ by using
2420 __int64 instead of `long long'. Change many refs to long long
2421 into word64/uword64 typedefs.
2422
2423Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2424
2425 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2426 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2427 (docdir): Removed.
2428 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2429 (AC_PROG_INSTALL): Added.
2430 (AC_PROG_CC): Moved to before configure.host call.
2431 * configure: Rebuilt.
2432
2433Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2434
2435 * configure.in: Define @SIMCONF@ depending on mips target.
2436 * configure: Rebuild.
2437 * Makefile.in (run): Add @SIMCONF@ to control simulator
2438 construction.
2439 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2440 * interp.c: Remove some debugging, provide more detailed error
2441 messages, update memory accesses to use LOADDRMASK.
2442
2443Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2444
2445 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2446 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2447 stamp-h.
2448 * configure: Rebuild.
2449 * config.in: New file, generated by autoheader.
2450 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2451 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2452 HAVE_ANINT and HAVE_AINT, as appropriate.
2453 * Makefile.in (run): Use @LIBS@ rather than -lm.
2454 (interp.o): Depend upon config.h.
2455 (Makefile): Just rebuild Makefile.
2456 (clean): Remove stamp-h.
2457 (mostlyclean): Make the same as clean, not as distclean.
2458 (config.h, stamp-h): New targets.
2459
2460Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2461
2462 * interp.c (ColdReset): Fix boolean test. Make all simulator
2463 globals static.
2464
2465Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2466
2467 * interp.c (xfer_direct_word, xfer_direct_long,
2468 swap_direct_word, swap_direct_long, xfer_big_word,
2469 xfer_big_long, xfer_little_word, xfer_little_long,
2470 swap_word,swap_long): Added.
2471 * interp.c (ColdReset): Provide function indirection to
2472 host<->simulated_target transfer routines.
2473 * interp.c (sim_store_register, sim_fetch_register): Updated to
2474 make use of indirected transfer routines.
2475
2476Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2477
2478 * gencode.c (process_instructions): Ensure FP ABS instruction
2479 recognised.
2480 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2481 system call support.
2482
2483Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2484
2485 * interp.c (sim_do_command): Complain if callback structure not
2486 initialised.
2487
2488Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2489
2490 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2491 support for Sun hosts.
2492 * Makefile.in (gencode): Ensure the host compiler and libraries
2493 used for cross-hosted build.
2494
2495Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2496
2497 * interp.c, gencode.c: Some more (TODO) tidying.
2498
2499Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2500
2501 * gencode.c, interp.c: Replaced explicit long long references with
2502 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2503 * support.h (SET64LO, SET64HI): Macros added.
2504
2505Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2506
2507 * configure: Regenerate with autoconf 2.7.
2508
2509Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2510
2511 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2512 * support.h: Remove superfluous "1" from #if.
2513 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2514
2515Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2516
2517 * interp.c (StoreFPR): Control UndefinedResult() call on
2518 WARN_RESULT manifest.
2519
2520Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2521
2522 * gencode.c: Tidied instruction decoding, and added FP instruction
2523 support.
2524
2525 * interp.c: Added dineroIII, and BSD profiling support. Also
2526 run-time FP handling.
2527
2528Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2529
2530 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2531 gencode.c, interp.c, support.h: created.
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