Commit | Line | Data |
---|---|---|
74025eee AC |
1 | Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com> |
2 | ||
3 | * mips.igen (DSRAV): Use function do_dsrav. | |
4 | (SRAV): Use new function do_srav. | |
5 | ||
6 | * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX]. | |
7 | (B): Sign extend 11 bit immediate. | |
8 | (EXT-B*): Shift 16 bit immediate left by 1. | |
9 | (ADDIU*): Don't sign extend immediate value. | |
10 | ||
f3bdd368 AC |
11 | Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com> |
12 | ||
13 | * m16run.c (sim_engine_run): Restore CIA after handling an event. | |
14 | ||
15 | start-sanitize-tx19 | |
16 | * mips.igen (mtc0): Valid tx19 instruction. | |
17 | ||
18 | end-sanitize-tx19 | |
19 | * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use | |
20 | functions. | |
21 | ||
22 | * mips.igen (delayslot32, nullify_next_insn): New functions. | |
23 | (m16.igen): Always include. | |
24 | (do_*): Add more tracing. | |
25 | ||
26 | * m16.igen (delayslot16): Add NIA argument, could be called by a | |
27 | 32 bit MIPS16 instruction. | |
28 | ||
29 | * interp.c (ifetch16): Move function from here. | |
30 | * sim-main.c (ifetch16): To here. | |
31 | ||
32 | * sim-main.c (ifetch16, ifetch32): Update to match current | |
33 | implementations of LH, LW. | |
34 | (signal_exception): Don't print out incorrect hex value of illegal | |
35 | instruction. | |
36 | ||
c0a4c3ba AC |
37 | Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com> |
38 | ||
39 | * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an | |
40 | instruction. | |
41 | ||
42 | * m16.igen: Implement MIPS16 instructions. | |
43 | ||
44 | * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu, | |
45 | do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav, | |
46 | do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or, | |
47 | do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra, | |
48 | do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move | |
49 | bodies of corresponding code from 32 bit insn to these. Also used | |
50 | by MIPS16 versions of functions. | |
51 | ||
52 | * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define. | |
53 | (IMEM16): Drop NR argument from macro. | |
54 | ||
96a4eb30 | 55 | start-sanitize-sky |
c0a4c3ba | 56 | Mon Apr 13 16:28:52 1998 Frank Ch. Eigler <fche@cygnus.com> |
96a4eb30 FCE |
57 | |
58 | * interp.c (decode_coproc): Add proper 1000000 bit-string at top | |
59 | of VU lower instruction. | |
60 | ||
61 | end-sanitize-sky | |
b0b39eb2 FCE |
62 | start-sanitize-sky |
63 | Thu Apr 9 16:38:23 1998 Frank Ch. Eigler <fche@cygnus.com> | |
64 | ||
65 | * r5900.igen (LQC,SQC): Adapted code to DOUBLEWORD accesses | |
66 | instead of QUADWORD. | |
67 | ||
68 | * sim-main.h: Removed attempt at allowing 128-bit access. | |
69 | ||
70 | end-sanitize-sky | |
11c47f31 | 71 | start-sanitize-sky |
c0a4c3ba | 72 | Wed Apr 8 18:12:13 1998 Frank Ch. Eigler <fche@cygnus.com> |
11c47f31 FCE |
73 | |
74 | * Makefile.in (SIM_SKY_OBJS): Added sky-vudis.o. | |
75 | ||
76 | * interp.c (decode_coproc): Refer to VU CIA as a "special" | |
77 | register, not as a "misc" register. Aha. Add activity | |
78 | assertions after VCALLMS* instructions. | |
79 | ||
80 | end-sanitize-sky | |
174ff224 | 81 | start-sanitize-sky |
c0a4c3ba | 82 | Tue Apr 7 18:32:49 1998 Frank Ch. Eigler <fche@cygnus.com> |
174ff224 FCE |
83 | |
84 | * interp.c (decode_coproc): Do not apply superfluous E (end) flag | |
85 | to upper code of generated VU instruction. | |
86 | ||
87 | end-sanitize-sky | |
2ebb2a68 FCE |
88 | start-sanitize-sky |
89 | Mon Apr 6 19:55:56 1998 Frank Ch. Eigler <fche@cygnus.com> | |
90 | ||
91 | * interp.c (cop_[ls]q): Replaced stub with proper COP2 code. | |
92 | ||
93 | * sim-main.h (LOADADDRMASK): Redefine to allow 128-bit accesses | |
94 | for TARGET_SKY. | |
95 | ||
96 | * r5900.igen (SQC2): Thinko. | |
97 | ||
98 | end-sanitize-sky | |
ebcfd86a FCE |
99 | start-sanitize-sky |
100 | Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> | |
101 | ||
102 | * interp.c (*): Adapt code to merged VU device & state structs. | |
103 | (decode_coproc): Execute COP2 each macroinstruction without | |
104 | pipelining, by stepping VU to completion state. Adapted to | |
105 | read_vu_*_reg style of register access. | |
106 | ||
107 | * mips.igen ([SL]QC2): Removed these COP2 instructions. | |
108 | ||
109 | * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. | |
110 | ||
111 | * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. | |
112 | ||
113 | end-sanitize-sky | |
64ed8b6a AC |
114 | Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com> |
115 | ||
116 | * Makefile.in (SIM_OBJS): Add sim-main.o. | |
117 | ||
118 | * sim-main.h (address_translation, load_memory, store_memory, | |
119 | cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark | |
120 | as INLINE_SIM_MAIN. | |
121 | (pr_addr, pr_uword64): Declare. | |
122 | (sim-main.c): Include when H_REVEALS_MODULE_P. | |
123 | ||
124 | * interp.c (address_translation, load_memory, store_memory, | |
125 | cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move | |
126 | from here. | |
127 | * sim-main.c: To here. Fix compilation problems. | |
128 | ||
129 | * configure.in: Enable inlining. | |
130 | * configure: Re-config. | |
131 | ||
278bda40 AC |
132 | Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com> |
133 | ||
134 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
135 | ||
136 | Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
137 | ||
138 | * mips.igen: Include tx.igen. | |
139 | * Makefile.in (IGEN_INCLUDE): Add tx.igen. | |
140 | * tx.igen: New file, contains MADD and MADDU. | |
141 | ||
142 | * interp.c (load_memory): When shifting bytes, use LOADDRMASK not | |
143 | the hardwired constant `7'. | |
144 | (store_memory): Ditto. | |
145 | (LOADDRMASK): Move definition to sim-main.h. | |
146 | ||
147 | mips.igen (MTC0): Enable for r3900. | |
148 | (ADDU): Add trace. | |
149 | ||
150 | mips.igen (do_load_byte): Delete. | |
151 | (do_load, do_store, do_load_left, do_load_write, do_store_left, | |
152 | do_store_right): New functions. | |
153 | (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use. | |
154 | ||
155 | configure.in: Let the tx39 use igen again. | |
156 | configure: Update. | |
157 | ||
725fc5d9 AC |
158 | Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com> |
159 | ||
160 | * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity, | |
161 | not an address sized quantity. Return zero for cache sizes. | |
162 | ||
163 | Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
164 | ||
165 | * mips.igen (r3900): r3900 does not support 64 bit integer | |
166 | operations. | |
167 | ||
6b0c51c9 FCE |
168 | start-sanitize-sky |
169 | Wed Apr 1 08:20:31 1998 Frank Ch. Eigler <fche@cygnus.com> | |
170 | ||
171 | * mips.igen (SQC2/LQC2): Make bodies sky-target-only also. | |
6b0c51c9 | 172 | |
725fc5d9 | 173 | end-sanitize-sky |
6ed00b06 FCE |
174 | start-sanitize-sky |
175 | Mon Mar 30 18:41:43 1998 Frank Ch. Eigler <fche@cygnus.com> | |
176 | ||
177 | * interp.c (decode_coproc): Continuing COP2 work. | |
6b0c51c9 | 178 | (cop_[ls]q): Make sky-target-only. |
6ed00b06 | 179 | |
6b0c51c9 | 180 | * sim-main.h (COP_[LS]Q): Make sky-target-only. |
6ed00b06 | 181 | end-sanitize-sky |
34f51d87 GRK |
182 | Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com> |
183 | ||
184 | * configure.in (mipstx39*-*-*): Use gencode simulator rather | |
185 | than igen one. | |
186 | * configure : Rebuild. | |
187 | ||
7dd4a466 FCE |
188 | start-sanitize-sky |
189 | Sun Mar 29 17:50:11 Frank Ch. Eigler <fche@cygnus.com> | |
190 | ||
191 | * interp.c (decode_coproc): Added a missing TARGET_SKY check | |
192 | around COP2 implementation skeleton. | |
193 | ||
194 | end-sanitize-sky | |
7dba069e | 195 | start-sanitize-sky |
15232df4 FCE |
196 | Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com> |
197 | ||
15232df4 FCE |
198 | * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o. |
199 | ||
200 | * interp.c (sim_{load,store}_register): Use new vu[01]_device | |
201 | static to access VU registers. | |
202 | (decode_coproc): Added skeleton of sky COP2 (VU) instruction | |
203 | decoding. Work in progress. | |
204 | ||
205 | * mips.igen (LDCzz, SDCzz): Removed *5900 case for this | |
206 | overlapping/redundant bit pattern. | |
207 | (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in | |
208 | progress. | |
209 | ||
210 | * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for | |
211 | status register. | |
212 | ||
15232df4 FCE |
213 | * interp.c (cop_lq, cop_sq): New functions for future 128-bit |
214 | access to coprocessor registers. | |
215 | ||
216 | * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above. | |
6ed00b06 | 217 | end-sanitize-sky |
d8f53049 AC |
218 | Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com> |
219 | ||
220 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
221 | ||
82ea14fd AC |
222 | Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com> |
223 | ||
224 | * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS. | |
225 | ||
226 | Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com> | |
227 | ||
228 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
229 | * config.in: Regenerated to track ../common/aclocal.m4 changes. | |
230 | ||
d89fa2d8 AC |
231 | Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com> |
232 | ||
233 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
234 | ||
612a649e AC |
235 | Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com> |
236 | ||
237 | * interp.c (Max, Min): Comment out functions. Not yet used. | |
238 | ||
239 | start-sanitize-vr4320 | |
240 | Wed Mar 25 10:04:13 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
241 | ||
242 | * vr4320.igen (DCLZ): Pacify GCC, 64 bit arg, int format. | |
243 | ||
244 | end-sanitize-vr4320 | |
245 | Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
246 | ||
247 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
248 | ||
9b23b76d FCE |
249 | Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com> |
250 | ||
251 | * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added | |
252 | configurable settings for stand-alone simulator. | |
253 | ||
254 | start-sanitize-sky | |
255 | * configure.in: Added --with-sim-gpu2 option to specify path of | |
256 | sky GPU2 library. Triggers -DSKY_GPU2 for sky-gpuif.c, and | |
257 | links/compiles stand-alone simulator with this library. | |
258 | ||
259 | * interp.c (MEM_SIZE): Increased default sky memory size to 16MB. | |
260 | end-sanitize-sky | |
9b23b76d FCE |
261 | * configure.in: Added X11 search, just in case. |
262 | ||
263 | * configure: Regenerated. | |
264 | ||
265 | Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
266 | ||
267 | * interp.c (sim_write, sim_read, load_memory, store_memory): | |
268 | Replace sim_core_*_map with read_map, write_map, exec_map resp. | |
269 | ||
5fa71251 GRK |
270 | start-sanitize-vr4320 |
271 | Tue Mar 10 10:32:22 1998 Gavin Koch <gavin@cygnus.com> | |
272 | ||
273 | * vr4320.igen (clz,dclz) : Added. | |
274 | (dmac): Replaced 99, with LO. | |
275 | ||
276 | end-sanitize-vr4320 | |
6ba4c153 AC |
277 | start-sanitize-vr5400 |
278 | Fri Mar 6 08:30:58 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
279 | ||
280 | * mdmx.igen (SHFL.REPA.fmt, SHFL.REPB.fmt): Fix bit fields. | |
281 | ||
282 | end-sanitize-vr5400 | |
dd15abd5 GRK |
283 | start-sanitize-vr4320 |
284 | Tue Mar 3 11:56:29 1998 Gavin Koch <gavin@cygnus.com> | |
285 | ||
286 | * vr4320.igen: New file. | |
287 | * Makefile.in (vr4320.igen) : Added. | |
288 | * configure.in (mips64vr4320-*-*): Added. | |
289 | * configure : Rebuilt. | |
290 | * mips.igen : Correct the bfd-names in the mips-ISA model entries. | |
291 | Add the vr4320 model entry and mark the vr4320 insn as necessary. | |
292 | ||
293 | end-sanitize-vr4320 | |
ca6f76d1 AC |
294 | Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com> |
295 | ||
296 | * sim-main.h (GETFCC): Return an unsigned value. | |
297 | ||
298 | start-sanitize-r5900 | |
299 | * r5900.igen: Use an unsigned array index variable `i'. | |
300 | (QFSRV): Ditto for variable bytes. | |
301 | ||
302 | end-sanitize-r5900 | |
303 | Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
304 | ||
305 | * mips.igen (DIV): Fix check for -1 / MIN_INT. | |
306 | (DADD): Result destination is RD not RT. | |
307 | ||
308 | start-sanitize-r5900 | |
309 | * r5900.igen (DIV1): Fix check for -1 / MIN_INT. | |
310 | (DIVU1): Don't check for MIN_INT / -1 as performing unsigned | |
311 | divide. | |
312 | ||
313 | end-sanitize-r5900 | |
0e701ac3 AC |
314 | Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com> |
315 | ||
316 | * sim-main.h (HIACCESS, LOACCESS): Always define. | |
317 | ||
318 | * mdmx.igen (Maxi, Mini): Rename Max, Min. | |
319 | ||
320 | * interp.c (sim_info): Delete. | |
321 | ||
7c5d88c1 DE |
322 | Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com> |
323 | ||
324 | * interp.c (DECLARE_OPTION_HANDLER): Use it. | |
325 | (mips_option_handler): New argument `cpu'. | |
326 | (sim_open): Update call to sim_add_option_table. | |
327 | ||
f89c0689 AC |
328 | Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com> |
329 | ||
330 | * mips.igen (CxC1): Add tracing. | |
331 | ||
332 | start-sanitize-r5900 | |
333 | Wed Feb 25 13:59:03 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
334 | ||
335 | * r5900.igen (StoreFP): Delete. | |
336 | (r59fp_store, r59fp_overflow, r59fp_op1, r59fp_op2, r59fp_op3): | |
337 | New functions. | |
338 | (rsqrt.s, sqrt.s): Implement. | |
339 | (r59cond): New function. | |
340 | (C.COND.S): Call r59cond in assembler line. | |
341 | (cvt.w.s, cvt.s.w): Implement. | |
342 | ||
343 | * mips.igen (rsqrt.fmt, sqrt.fmt, cvt.*.*): Remove from r5900 | |
344 | instruction set. | |
345 | ||
346 | * sim-main.h: Define an enum of r5900 FCSR bit fields. | |
347 | ||
348 | end-sanitize-r5900 | |
a48e8c8d | 349 | start-sanitize-r5900 |
d3e1d594 AC |
350 | Tue Feb 24 14:44:18 1998 Andrew Cagney <cagney@b1.cygnus.com> |
351 | ||
352 | * r5900.igen: Add tracing to all p* instructions. | |
353 | ||
a48e8c8d AC |
354 | Tue Feb 24 02:47:33 1998 Andrew Cagney <cagney@b1.cygnus.com> |
355 | ||
356 | * interp.c (sim_store_register, sim_fetch_register): Pull swifty | |
357 | to get gdb talking to re-aranged sim_cpu register structure. | |
358 | ||
359 | end-sanitize-r5900 | |
360 | Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
361 | ||
362 | * sim-main.h (Max, Min): Declare. | |
363 | ||
364 | * interp.c (Max, Min): New functions. | |
365 | ||
366 | * mips.igen (BC1): Add tracing. | |
367 | ||
368 | start-sanitize-vr5400 | |
369 | Fri Feb 20 16:27:17 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
370 | ||
371 | * mdmx.igen: Tag all functions as requiring either with mdmx or | |
372 | vr5400 processor. | |
373 | ||
374 | end-sanitize-vr5400 | |
375 | start-sanitize-r5900 | |
376 | Fri Feb 20 15:55:51 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
377 | ||
378 | * configure.in (SIM_AC_OPTION_FLOAT): For r5900, set FP bit size | |
379 | to 32. | |
380 | (SIM_AC_OPTION_BITSIZE): For r5900, set nr address bits to 32. | |
381 | ||
382 | * mips.igen (C.cond.fmt, ..): Not part of r5900 insn set. | |
383 | ||
384 | * r5900.igen: Rewrite. | |
385 | ||
386 | * sim-main.h: Move r5900 registers to a separate _sim_r5900_cpu | |
387 | struct. | |
388 | (GPR_SB, GPR_SH, GPR_SW, GPR_SD, GPR_UB, GPR_UH, GPR_UW, GPR_UD): | |
389 | Define in terms of GPR/GPR1 instead of REGISTERS/REGISTERS.1 | |
390 | ||
391 | end-sanitize-r5900 | |
392 | Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com> | |
393 | ||
394 | * interp.c Added memory map for stack in vr4100 | |
395 | ||
f319bab2 GRK |
396 | Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com> |
397 | ||
398 | * interp.c (load_memory): Add missing "break"'s. | |
399 | ||
400 | Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
401 | ||
402 | * interp.c (sim_store_register, sim_fetch_register): Pass in | |
403 | length parameter. Return -1. | |
404 | ||
405 | Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com> | |
406 | ||
407 | * interp.c: Added hardware init hook, fixed warnings. | |
408 | ||
452b3808 AC |
409 | Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com> |
410 | ||
411 | * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL. | |
412 | ||
37379a25 AC |
413 | Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com> |
414 | ||
415 | * interp.c (ifetch16): New function. | |
416 | ||
417 | * sim-main.h (IMEM32): Rename IMEM. | |
418 | (IMEM16_IMMED): Define. | |
419 | (IMEM16): Define. | |
420 | (DELAY_SLOT): Update. | |
421 | ||
422 | * m16run.c (sim_engine_run): New file. | |
423 | ||
424 | * m16.igen: All instructions except LB. | |
425 | (LB): Call do_load_byte. | |
426 | * mips.igen (do_load_byte): New function. | |
427 | (LB): Call do_load_byte. | |
428 | ||
429 | * mips.igen: Move spec for insn bit size and high bit from here. | |
430 | * Makefile.in (tmp-igen, tmp-m16): To here. | |
431 | ||
432 | * m16.dc: New file, decode mips16 instructions. | |
433 | ||
434 | * Makefile.in (SIM_NO_ALL): Define. | |
435 | (tmp-m16): Generate both 16 bit and 32 bit simulator engines. | |
436 | ||
437 | start-sanitize-tx19 | |
438 | * m16.igen: Mark all mips16 insns as being part of the tx19 insn | |
439 | set. | |
440 | ||
441 | end-sanitize-tx19 | |
442 | Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
443 | ||
444 | * configure.in (mips_fpu_bitsize): For tx39, restrict floating | |
445 | point unit to 32 bit registers. | |
446 | * configure: Re-generate. | |
447 | ||
448 | Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
449 | ||
450 | * configure.in (sim_use_gen): Make IGEN the default simulator | |
451 | generator for generic 32 and 64 bit mips targets. | |
452 | * configure: Re-generate. | |
453 | ||
a97f304b AC |
454 | Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com> |
455 | ||
456 | * sim-main.h (SizeFGR): Determine from floating-point and not gpr | |
457 | bitsize. | |
458 | ||
459 | * interp.c (sim_fetch_register, sim_store_register): Read/write | |
460 | FGR from correct location. | |
461 | (sim_open): Set size of FGR's according to | |
462 | WITH_TARGET_FLOATING_POINT_BITSIZE. | |
463 | ||
464 | * sim-main.h (FGR): Store floating point registers in a separate | |
465 | array. | |
466 | ||
467 | Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
468 | ||
469 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
470 | ||
471 | start-sanitize-vr5400 | |
472 | * mdmx.igen: Mark all instructions as 64bit/fp specific. | |
473 | ||
474 | end-sanitize-vr5400 | |
2acd126a AC |
475 | Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com> |
476 | ||
477 | * interp.c (ColdReset): Call PENDING_INVALIDATE. | |
478 | ||
479 | * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK. | |
480 | ||
481 | * interp.c (pending_tick): New function. Deliver pending writes. | |
482 | ||
483 | * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED, | |
484 | PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that | |
485 | it can handle mixed sized quantites and single bits. | |
486 | ||
192ae475 AC |
487 | Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com> |
488 | ||
489 | * interp.c (oengine.h): Do not include when building with IGEN. | |
490 | (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE. | |
491 | (sim_info): Ditto for PROCESSOR_64BIT. | |
492 | (sim_monitor): Replace ut_reg with unsigned_word. | |
493 | (*): Ditto for t_reg. | |
494 | (LOADDRMASK): Define. | |
495 | (sim_open): Remove defunct check that host FP is IEEE compliant, | |
496 | using software to emulate floating point. | |
497 | (value_fpr, ...): Always compile, was conditional on HASFPU. | |
498 | ||
01737f42 AC |
499 | Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com> |
500 | ||
501 | * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in | |
502 | size. | |
503 | ||
504 | * interp.c (SD, CPU): Define. | |
505 | (mips_option_handler): Set flags in each CPU. | |
506 | (interrupt_event): Assume CPU 0 is the one being iterrupted. | |
507 | (sim_close): Do not clear STATE, deleted anyway. | |
508 | (sim_write, sim_read): Assume CPU zero's vm should be used for | |
509 | data transfers. | |
510 | (sim_create_inferior): Set the PC for all processors. | |
511 | (sim_monitor, store_word, load_word, mips16_entry): Add cpu | |
512 | argument. | |
513 | (mips16_entry): Pass correct nr of args to store_word, load_word. | |
514 | (ColdReset): Cold reset all cpu's. | |
515 | (signal_exception): Pass cpu to sim_monitor & mips16_entry. | |
516 | (sim_monitor, load_memory, store_memory, signal_exception): Use | |
517 | `CPU' instead of STATE_CPU. | |
518 | ||
519 | ||
520 | * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with | |
521 | SD or CPU_. | |
522 | ||
523 | * sim-main.h (signal_exception): Add sim_cpu arg. | |
524 | (SignalException*): Pass both SD and CPU to signal_exception. | |
525 | * interp.c (signal_exception): Update. | |
526 | ||
527 | * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c: | |
528 | Ditto | |
529 | (sync_operation, prefetch, cache_op, store_memory, load_memory, | |
530 | address_translation): Ditto | |
531 | (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto. | |
532 | ||
533 | start-sanitize-vr5400 | |
534 | * mdmx.igen (get_scale): Pass CPU_ to semantic_illegal instead of | |
535 | `sd'. | |
536 | (ByteAlign): Use StoreFPR, pass args in correct order. | |
537 | ||
538 | end-sanitize-vr5400 | |
539 | start-sanitize-r5900 | |
540 | Sun Feb 1 10:59:55 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
541 | ||
542 | * configure.in (sim_igen_filter): For r5900, configure as SMP. | |
543 | ||
544 | end-sanitize-r5900 | |
412c4e94 AC |
545 | Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com> |
546 | ||
547 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
548 | ||
9ec6741b AC |
549 | Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com> |
550 | ||
c4db5b04 AC |
551 | start-sanitize-r5900 |
552 | * configure.in (sim_igen_filter): For r5900, use igen. | |
553 | * configure: Re-generate. | |
554 | ||
555 | end-sanitize-r5900 | |
9ec6741b AC |
556 | * interp.c (sim_engine_run): Add `nr_cpus' argument. |
557 | ||
558 | * mips.igen (model): Map processor names onto BFD name. | |
559 | ||
560 | * sim-main.h (CPU_CIA): Delete. | |
561 | (SET_CIA, GET_CIA): Define | |
562 | ||
2d44e12a AC |
563 | Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com> |
564 | ||
565 | * sim-main.h (GPR_SET): Define, used by igen when zeroing a | |
566 | regiser. | |
567 | ||
568 | * configure.in (default_endian): Configure a big-endian simulator | |
569 | by default. | |
570 | * configure: Re-generate. | |
571 | ||
462cfbc4 DE |
572 | Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba> |
573 | ||
574 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
575 | ||
e0e0fc76 MA |
576 | Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com> |
577 | ||
578 | * interp.c (sim_monitor): Handle Densan monitor outbyte | |
579 | and inbyte functions. | |
580 | ||
76ef4165 FL |
581 | 1997-12-29 Felix Lee <flee@cygnus.com> |
582 | ||
583 | * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c). | |
584 | ||
585 | Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com) | |
586 | ||
587 | * Makefile.in (tmp-igen): Arrange for $zero to always be | |
588 | reset to zero after every instruction. | |
589 | ||
9c8ec16d AC |
590 | Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com> |
591 | ||
592 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
593 | * config.in: Ditto. | |
594 | ||
255cbbf1 | 595 | start-sanitize-vr5400 |
b17d2d14 AC |
596 | Sat Dec 13 15:18:51 1997 Andrew Cagney <cagney@b1.cygnus.com> |
597 | ||
598 | * vr5400.igen (Low32Bits, High32Bits): Sign extend extracted 32 | |
599 | bit values. | |
600 | ||
601 | end-sanitize-vr5400 | |
602 | start-sanitize-vr5400 | |
255cbbf1 JL |
603 | Fri Dec 12 12:26:07 1997 Jeffrey A Law (law@cygnus.com) |
604 | ||
605 | * configure.in (sim_igen_filter): Multi-sim vr5000 - vr5000 or | |
606 | vr5400 with the vr5000 as the default. | |
607 | ||
608 | end-sanitize-vr5400 | |
23850e92 JL |
609 | Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com) |
610 | ||
611 | * mips.igen (MSUB): Fix to work like MADD. | |
612 | * gencode.c (MSUB): Similarly. | |
613 | ||
c02ed6a8 AC |
614 | start-sanitize-vr5400 |
615 | Tue Dec 9 12:02:12 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
616 | ||
617 | * configure.in (sim_igen_filter): Multi-sim vr5400 - vr5000 or | |
618 | vr5400. | |
619 | ||
620 | end-sanitize-vr5400 | |
6e51f990 DE |
621 | Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com> |
622 | ||
623 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
624 | ||
35c246c9 AC |
625 | Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com> |
626 | ||
627 | * mips.igen (LWC1): Correct assembler - lwc1 not swc1. | |
628 | ||
629 | start-sanitize-vr5400 | |
0d5d0d10 | 630 | * mdmx.igen (value_vr): Correct sim_io_eprintf format argument. |
0931ce5a | 631 | (value_cc, store_cc): Implement. |
0d5d0d10 | 632 | |
35c246c9 AC |
633 | * sim-main.h: Add 8*3*8 bit accumulator. |
634 | ||
635 | * vr5400.igen: Move mdmx instructins from here | |
636 | * mdmx.igen: To here - new file. Add/fix missing instructions. | |
637 | * mips.igen: Include mdmx.igen. | |
0931ce5a | 638 | * Makefile.in (IGEN_INCLUDE): Add mdmx.igen. |
35c246c9 | 639 | |
c02ed6a8 | 640 | end-sanitize-vr5400 |
58fb5d0a AC |
641 | Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com> |
642 | ||
643 | * sim-main.h (sim-fpu.h): Include. | |
644 | ||
645 | * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub, | |
646 | Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite | |
647 | using host independant sim_fpu module. | |
648 | ||
a09a30d2 AC |
649 | Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com> |
650 | ||
232156de AC |
651 | * interp.c (signal_exception): Report internal errors with SIGABRT |
652 | not SIGQUIT. | |
a09a30d2 | 653 | |
232156de AC |
654 | * sim-main.h (C0_CONFIG): New register. |
655 | (signal.h): No longer include. | |
656 | ||
657 | * interp.c (decode_coproc): Allow access C0_CONFIG to register. | |
a09a30d2 | 658 | |
486740ce DE |
659 | Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com> |
660 | ||
661 | * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS). | |
662 | ||
f23e93da AC |
663 | Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com> |
664 | ||
665 | * mips.igen: Tag vr5000 instructions. | |
666 | (ANDI): Was missing mipsIV model, fix assembler syntax. | |
667 | (do_c_cond_fmt): New function. | |
668 | (C.cond.fmt): Handle mips I-III which do not support CC field | |
669 | separatly. | |
670 | (bc1): Handle mips IV which do not have a delaed FCC separatly. | |
671 | (SDR): Mask paddr when BigEndianMem, not the converse as specified | |
672 | in IV3.2 spec. | |
673 | (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle | |
674 | vr5000 which saves LO in a GPR separatly. | |
675 | ||
676 | * configure.in (enable-sim-igen): For vr5000, select vr5000 | |
677 | specific instructions. | |
678 | * configure: Re-generate. | |
679 | ||
680 | Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
681 | ||
682 | * Makefile.in (SIM_OBJS): Add sim-fpu module. | |
683 | ||
684 | * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and | |
685 | fmt_uninterpreted_64 bit cases to switch. Convert to | |
686 | fmt_formatted, | |
687 | ||
688 | * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define, | |
689 | ||
690 | * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse | |
691 | as specified in IV3.2 spec. | |
692 | (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR. | |
693 | ||
030843d7 AC |
694 | Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com> |
695 | ||
696 | * mips.igen: Delay slot branches add OFFSET to NIA not CIA. | |
697 | (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement. | |
698 | (start-sanitize-r5900): | |
699 | (LWXC1, SWXC1): Delete from r5900 instruction set. | |
700 | (end-sanitize-r5900): | |
701 | (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non | |
a94c5493 | 702 | PENDING_FILL versions of instructions. Simplify. |
030843d7 AC |
703 | (X): New function. |
704 | (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of | |
705 | instructions. | |
a94c5493 AC |
706 | (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to |
707 | a signed value. | |
030843d7 AC |
708 | (MTHI, MFHI): Disable code checking HI-LO. |
709 | ||
710 | * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh | |
711 | global. | |
712 | (NULLIFY_NEXT_INSTRUCTION): Call dotrace. | |
713 | ||
7ce8b917 AC |
714 | Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com> |
715 | ||
95469ceb AC |
716 | * gencode.c (build_mips16_operands): Replace IPC with cia. |
717 | ||
718 | * interp.c (sim_monitor, signal_exception, cache_op, store_fpr, | |
719 | value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace | |
720 | IPC to `cia'. | |
721 | (UndefinedResult): Replace function with macro/function | |
722 | combination. | |
723 | (sim_engine_run): Don't save PC in IPC. | |
724 | ||
725 | * sim-main.h (IPC): Delete. | |
726 | ||
727 | start-sanitize-vr5400 | |
728 | * vr5400.igen (vr): Add missing cia argument to value_fpr. | |
729 | (do_select): Rename function select. | |
730 | end-sanitize-vr5400 | |
731 | ||
7ce8b917 AC |
732 | * interp.c (signal_exception, store_word, load_word, |
733 | address_translation, load_memory, store_memory, cache_op, | |
734 | prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert, | |
95469ceb AC |
735 | cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add |
736 | current instruction address - cia - argument. | |
7ce8b917 AC |
737 | (sim_read, sim_write): Call address_translation directly. |
738 | (sim_engine_run): Rename variable vaddr to cia. | |
95469ceb AC |
739 | (signal_exception): Pass cia to sim_monitor |
740 | ||
7ce8b917 AC |
741 | * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp, |
742 | Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW, | |
743 | COP_LD, COP_SW, COP_SD, DecodeCoproc): Update. | |
744 | ||
745 | * sim-main.h (SignalExceptionSimulatorFault): Delete definition. | |
746 | * interp.c (sim_open): Replace SignalExceptionSimulatorFault with | |
747 | SIM_ASSERT. | |
748 | ||
749 | * interp.c (signal_exception): Pass restart address to | |
750 | sim_engine_restart. | |
751 | ||
752 | * Makefile.in (semantics.o, engine.o, support.o, itable.o, | |
753 | idecode.o): Add dependency. | |
754 | ||
755 | * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK): | |
756 | Delete definitions | |
757 | (DELAY_SLOT): Update NIA not PC with branch address. | |
758 | (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next. | |
759 | ||
760 | * mips.igen: Use CIA not PC in branch calculations. | |
761 | (illegal): Call SignalException. | |
762 | (BEQ, ADDIU): Fix assembler. | |
763 | ||
63be8feb AC |
764 | Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com> |
765 | ||
44b8585a AC |
766 | * m16.igen (JALX): Was missing. |
767 | ||
768 | * configure.in (enable-sim-igen): New configuration option. | |
769 | * configure: Re-generate. | |
770 | ||
63be8feb AC |
771 | * sim-main.h (MAX_INSNS, INSN_NAME): Define. |
772 | ||
773 | * interp.c (load_memory, store_memory): Delete parameter RAW. | |
774 | (sim_read, sim_write): Use sim_core_{read,write}_buffer directly | |
775 | bypassing {load,store}_memory. | |
776 | ||
777 | * sim-main.h (ByteSwapMem): Delete definition. | |
778 | ||
779 | * Makefile.in (SIM_OBJS): Add sim-memopt module. | |
780 | ||
781 | * interp.c (sim_do_command, sim_commands): Delete mips specific | |
782 | commands. Handled by module sim-options. | |
783 | ||
784 | * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module. | |
785 | (WITH_MODULO_MEMORY): Define. | |
786 | ||
787 | * interp.c (sim_info): Delete code printing memory size. | |
788 | ||
789 | * interp.c (mips_size): Nee sim_size, delete function. | |
790 | (power2): Delete. | |
791 | (monitor, monitor_base, monitor_size): Delete global variables. | |
792 | (sim_open, sim_close): Delete code creating monitor and other | |
793 | memory regions. Use sim-memopts module, via sim_do_commandf, to | |
794 | manage memory regions. | |
795 | (load_memory, store_memory): Use sim-core for memory model. | |
796 | ||
797 | * interp.c (address_translation): Delete all memory map code | |
798 | except line forcing 32 bit addresses. | |
799 | ||
22de994d AC |
800 | Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com> |
801 | ||
802 | * sim-main.h (WITH_TRACE): Delete definition. Enables common | |
803 | trace options. | |
804 | ||
805 | * interp.c (logfh, logfile): Delete globals. | |
806 | (sim_open, sim_close): Delete code opening & closing log file. | |
807 | (mips_option_handler): Delete -l and -n options. | |
808 | (OPTION mips_options): Ditto. | |
809 | ||
810 | * interp.c (OPTION mips_options): Rename option trace to dinero. | |
811 | (mips_option_handler): Update. | |
812 | ||
525d929e AC |
813 | Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com> |
814 | ||
815 | * interp.c (fetch_str): New function. | |
816 | (sim_monitor): Rewrite using sim_read & sim_write. | |
817 | (sim_open): Check magic number. | |
818 | (sim_open): Write monitor vectors into memory using sim_write. | |
819 | (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define. | |
820 | (sim_read, sim_write): Simplify - transfer data one byte at a | |
821 | time. | |
822 | (load_memory, store_memory): Clarify meaning of parameter RAW. | |
823 | ||
824 | * sim-main.h (isHOST): Defete definition. | |
825 | (isTARGET): Mark as depreciated. | |
826 | (address_translation): Delete parameter HOST. | |
827 | ||
828 | * interp.c (address_translation): Delete parameter HOST. | |
829 | ||
6205f379 GRK |
830 | start-sanitize-tx49 |
831 | Wed Oct 29 14:21:32 1997 Gavin Koch <gavin@cygnus.com> | |
832 | ||
833 | * gencode.c: Add tx49 configury and insns. | |
834 | * configure.in: Add tx49 configury. | |
835 | * configure: Update. | |
836 | ||
837 | end-sanitize-tx49 | |
01b9cd49 AC |
838 | Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com> |
839 | ||
840 | * mips.igen: | |
841 | ||
842 | * Makefile.in (IGEN_INCLUDE): Files included by mips.igen. | |
843 | (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE. | |
844 | ||
89d09738 AC |
845 | Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com> |
846 | ||
847 | * mips.igen: Add model filter field to records. | |
848 | ||
16bd5d6e AC |
849 | Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com> |
850 | ||
851 | * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0. | |
852 | ||
853 | interp.c (sim_engine_run): Do not compile function sim_engine_run | |
854 | when WITH_IGEN == 1. | |
855 | ||
856 | * configure.in (sim_igen_flags, sim_m16_flags): Set according to | |
857 | target architecture. | |
858 | ||
859 | Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to | |
860 | igen. Replace with configuration variables sim_igen_flags / | |
861 | sim_m16_flags. | |
862 | ||
16bd5d6e | 863 | start-sanitize-r5900 |
8c31916d AC |
864 | * r5900.igen: New file. Copy r5900 insns here. |
865 | end-sanitize-r5900 | |
16bd5d6e | 866 | start-sanitize-vr5400 |
58fb5d0a | 867 | * vr5400.igen: New file. |
255cbbf1 | 868 | end-sanitize-vr5400 |
16bd5d6e AC |
869 | * m16.igen: New file. Copy mips16 insns here. |
870 | * mips.igen: From here. | |
871 | ||
90ad43b2 AC |
872 | Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com> |
873 | ||
874 | start-sanitize-vr5400 | |
875 | * mips.igen: Tag all mipsIV instructions with vr5400 model. | |
876 | ||
877 | * configure.in: Add mips64vr5400 target. | |
878 | * configure: Re-generate. | |
879 | ||
880 | end-sanitize-vr5400 | |
881 | * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ | |
882 | to top. | |
883 | (tmp-igen, tmp-m16): Pass -I srcdir to igen. | |
884 | ||
635ae9cb GRK |
885 | Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com> |
886 | ||
887 | * gencode.c (build_instruction): Follow sim_write's lead in using | |
888 | BigEndianMem instead of !ByteSwapMem. | |
889 | ||
122edc03 AC |
890 | Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com> |
891 | ||
892 | * configure.in (sim_gen): Dependent on target, select type of | |
893 | generator. Always select old style generator. | |
894 | ||
895 | configure: Re-generate. | |
896 | ||
897 | Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New | |
898 | targets. | |
899 | (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16, | |
900 | SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN, | |
901 | IGEN_TRACE, IGEN_INSN, IGEN_DC): Define | |
902 | (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member | |
903 | SIM_@sim_gen@_*, set by autoconf. | |
904 | ||
dad6f1f3 AC |
905 | Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com> |
906 | ||
907 | * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define. | |
908 | ||
909 | * interp.c (ColdReset): Remove #ifdef HASFPU, check | |
910 | CURRENT_FLOATING_POINT instead. | |
911 | ||
912 | * interp.c (ifetch32): New function. Fetch 32 bit instruction. | |
913 | (address_translation): Raise exception InstructionFetch when | |
914 | translation fails and isINSTRUCTION. | |
915 | ||
916 | * interp.c (sim_open, sim_write, sim_monitor, store_word, | |
917 | sim_engine_run): Change type of of vaddr and paddr to | |
918 | address_word. | |
919 | (address_translation, prefetch, load_memory, store_memory, | |
920 | cache_op): Change type of vAddr and pAddr to address_word. | |
921 | ||
922 | * gencode.c (build_instruction): Change type of vaddr and paddr to | |
923 | address_word. | |
924 | ||
92ad193b AC |
925 | Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com> |
926 | ||
927 | * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT | |
928 | macro to obtain result of ALU op. | |
929 | ||
aa324b9b AC |
930 | Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com> |
931 | ||
932 | * interp.c (sim_info): Call profile_print. | |
933 | ||
e2f8ffb7 AC |
934 | Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com> |
935 | ||
936 | * Makefile.in (SIM_OBJS): Add sim-profile.o module. | |
937 | ||
938 | * sim-main.h (WITH_PROFILE): Do not define, defined in | |
939 | common/sim-config.h. Use sim-profile module. | |
940 | (simPROFILE): Delete defintion. | |
941 | ||
942 | * interp.c (PROFILE): Delete definition. | |
943 | (mips_option_handler): Delete 'p', 'y' and 'x' profile options. | |
944 | (sim_close): Delete code writing profile histogram. | |
945 | (mips_set_profile, mips_set_profile_size, writeout16, writeout32): | |
946 | Delete. | |
947 | (sim_engine_run): Delete code profiling the PC. | |
948 | ||
fb5a2a3e AC |
949 | Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com> |
950 | ||
951 | * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word. | |
952 | ||
953 | * interp.c (sim_monitor): Make register pointers of type | |
954 | unsigned_word*. | |
955 | ||
956 | * sim-main.h: Make registers of type unsigned_word not | |
957 | signed_word. | |
958 | ||
ea985d24 AC |
959 | Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com> |
960 | ||
961 | start-sanitize-r5900 | |
962 | * sim-main.h (BYTES_IN_MMI_REGS, ..., SUB_REG_FETCH, ..., GPR_SB, | |
963 | ...): Move to sim-main.h | |
964 | ||
965 | end-sanitize-r5900 | |
966 | * interp.c (sync_operation): Rename from SyncOperation, make | |
967 | global, add SD argument. | |
968 | (prefetch): Rename from Prefetch, make global, add SD argument. | |
969 | (decode_coproc): Make global. | |
970 | ||
971 | * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define. | |
972 | ||
973 | * gencode.c (build_instruction): Generate DecodeCoproc not | |
974 | decode_coproc calls. | |
975 | ||
976 | * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h | |
977 | (SizeFGR): Move to sim-main.h | |
978 | (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT, | |
979 | simSIGINT, simJALDELAYSLOT): Move to sim-main.h | |
980 | (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to | |
981 | sim-main.h. | |
982 | (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF, | |
983 | FP_RM_TOMINF, GETRM): Move to sim-main.h. | |
984 | (Uncached, CachedNoncoherent, CachedCoherent, Cached, | |
985 | isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h. | |
986 | (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian, | |
987 | BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h | |
988 | ||
989 | * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise | |
990 | exception. | |
991 | (sim-alu.h): Include. | |
992 | (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define. | |
993 | (sim_cia): Typedef to instruction_address. | |
994 | ||
284e759d AC |
995 | Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com> |
996 | ||
997 | * Makefile.in (interp.o): Rename generated file engine.c to | |
998 | oengine.c. | |
999 | ||
1000 | * interp.c: Update. | |
1001 | ||
339fb149 AC |
1002 | Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1003 | ||
1004 | * gencode.c (build_instruction): Use FPR_STATE not fpr_state. | |
1005 | ||
8b70f837 AC |
1006 | Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1007 | ||
1008 | * gencode.c (build_instruction): For "FPSQRT", output correct | |
1009 | number of arguments to Recip. | |
1010 | ||
0c2c5f61 AC |
1011 | Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1012 | ||
1013 | * Makefile.in (interp.o): Depends on sim-main.h | |
1014 | ||
1015 | * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers. | |
1016 | ||
1017 | * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state, | |
1018 | ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields. | |
1019 | (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*, | |
1020 | STATE, DSSTATE): Define | |
1021 | (GPR, FGRIDX, ..): Define. | |
1022 | ||
1023 | * interp.c (registers, register_widths, fpr_state, ipc, dspc, | |
1024 | pending_*, hiaccess, loaccess, state, dsstate): Delete globals. | |
1025 | (GPR, FGRIDX, ...): Delete macros. | |
1026 | ||
1027 | * interp.c: Update names to match defines from sim-main.h | |
1028 | ||
18c64df6 AC |
1029 | Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1030 | ||
1031 | * interp.c (sim_monitor): Add SD argument. | |
1032 | (sim_warning): Delete. Replace calls with calls to | |
1033 | sim_io_eprintf. | |
1034 | (sim_error): Delete. Replace calls with sim_io_error. | |
1035 | (open_trace, writeout32, writeout16, getnum): Add SD argument. | |
1036 | (mips_set_profile): Rename from sim_set_profile. Add SD argument. | |
1037 | (mips_set_profile_size): Rename from sim_set_profile_size. Add SD | |
1038 | argument. | |
1039 | (mips_size): Rename from sim_size. Add SD argument. | |
1040 | ||
1041 | * interp.c (simulator): Delete global variable. | |
1042 | (callback): Delete global variable. | |
1043 | (mips_option_handler, sim_open, sim_write, sim_read, | |
1044 | sim_store_register, sim_fetch_register, sim_info, sim_do_command, | |
1045 | sim_size,sim_monitor): Use sim_io_* not callback->*. | |
1046 | (sim_open): ZALLOC simulator struct. | |
1047 | (PROFILE): Do not define. | |
1048 | ||
1049 | Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
1050 | ||
1051 | * interp.c (sim_open), support.h: Replace CHECKSIM macro found in | |
1052 | support.h with corresponding code. | |
1053 | ||
1054 | * sim-main.h (word64, uword64), support.h: Move definition to | |
1055 | sim-main.h. | |
1056 | (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto. | |
1057 | ||
1058 | * support.h: Delete | |
1059 | * Makefile.in: Update dependencies | |
1060 | * interp.c: Do not include. | |
1061 | ||
1062 | Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
1063 | ||
1064 | * interp.c (address_translation, load_memory, store_memory, | |
1065 | cache_op): Rename to from AddressTranslation et.al., make global, | |
1066 | add SD argument | |
1067 | ||
1068 | * sim-main.h (AddressTranslation, LoadMemory, StoreMemory, | |
1069 | CacheOp): Define. | |
1070 | ||
1071 | * interp.c (SignalException): Rename to signal_exception, make | |
1072 | global. | |
1073 | ||
1074 | * interp.c (Interrupt, ...): Move definitions to sim-main.h. | |
1075 | ||
1076 | * sim-main.h (SignalException, SignalExceptionInterrupt, | |
1077 | SignalExceptionInstructionFetch, SignalExceptionAddressStore, | |
1078 | SignalExceptionAddressLoad, SignalExceptionSimulatorFault, | |
1079 | SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable): | |
1080 | Define. | |
1081 | ||
1082 | * interp.c, support.h: Use. | |
1083 | ||
1084 | Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
1085 | ||
1086 | * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename | |
1087 | to value_fpr / store_fpr. Add SD argument. | |
1088 | (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub, | |
1089 | Multiply, Divide, Recip, SquareRoot, Convert): Make global. | |
1090 | ||
1091 | * sim-main.h (ValueFPR, StoreFPR): Define. | |
1092 | ||
1093 | Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
1094 | ||
1095 | * interp.c (sim_engine_run): Check consistency between configure | |
1096 | WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN | |
1097 | and HASFPU. | |
1098 | ||
1099 | * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE. | |
1100 | (mips_fpu): Configure WITH_FLOATING_POINT. | |
1101 | (mips_endian): Configure WITH_TARGET_ENDIAN. | |
1102 | * configure: Update. | |
1103 | ||
1104 | Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
1105 | ||
1106 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
1107 | ||
adf4739e AC |
1108 | start-sanitize-r5900 |
1109 | Mon Aug 25 19:11:15 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
1110 | ||
1111 | * interp.c (MAX_REG): Allow up-to 128 registers. | |
1112 | (LO1, HI1): Define value that matches REGISTER_NAMES in gdb. | |
1113 | (REGISTER_SA): Ditto. | |
1114 | (sim_open): Initialize register_widths for r5900 specific | |
1115 | registers. | |
1116 | (sim_fetch_register, sim_store_register): Check for request of | |
1117 | r5900 specific SA register. Check for request for hi 64 bits of | |
1118 | r5900 specific registers. | |
1119 | ||
1120 | end-sanitize-r5900 | |
26b20b0a BM |
1121 | Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com> |
1122 | ||
1123 | * configure: Regenerated. | |
1124 | ||
6eedf3f4 MA |
1125 | Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com> |
1126 | ||
1127 | * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB. | |
1128 | ||
e63bc706 AC |
1129 | Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1130 | ||
6eedf3f4 MA |
1131 | * gencode.c (print_igen_insn_models): Assume certain architectures |
1132 | include all mips* instructions. | |
1133 | (print_igen_insn_format): Use data_size==-1 as marker for MIPS16 | |
1134 | instruction. | |
1135 | ||
e63bc706 AC |
1136 | * Makefile.in (tmp.igen): Add target. Generate igen input from |
1137 | gencode file. | |
1138 | ||
1139 | * gencode.c (FEATURE_IGEN): Define. | |
1140 | (main): Add --igen option. Generate output in igen format. | |
1141 | (process_instructions): Format output according to igen option. | |
1142 | (print_igen_insn_format): New function. | |
1143 | (print_igen_insn_models): New function. | |
1144 | (process_instructions): Only issue warnings and ignore | |
1145 | instructions when no FEATURE_IGEN. | |
1146 | ||
eb2e3c85 AC |
1147 | Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1148 | ||
1149 | * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some | |
1150 | MIPS targets. | |
1151 | ||
92f91d1f AC |
1152 | Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1153 | ||
1154 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
1155 | ||
1156 | Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
1157 | ||
1158 | * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN, | |
1159 | SIM_RESERVED_BITS): Delete, moved to common. | |
1160 | (SIM_EXTRA_CFLAGS): Update. | |
1161 | ||
794e9ac9 AC |
1162 | Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1163 | ||
76a6247f | 1164 | * configure.in: Configure non-strict memory alignment. |
794e9ac9 AC |
1165 | * configure: Regenerated to track ../common/aclocal.m4 changes. |
1166 | ||
b45caf05 AC |
1167 | Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1168 | ||
1169 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
1170 | ||
1171 | Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com> | |
1172 | ||
1173 | * gencode.c (SDBBP,DERET): Added (3900) insns. | |
1174 | (RFE): Turn on for 3900. | |
1175 | * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added. | |
1176 | (dsstate): Made global. | |
1177 | (SUBTARGET_R3900): Added. | |
1178 | (CANCELDELAYSLOT): New. | |
1179 | (SignalException): Ignore SystemCall rather than ignore and | |
1180 | terminate. Add DebugBreakPoint handling. | |
1181 | (decode_coproc): New insns RFE, DERET; and new registers Debug | |
1182 | and DEPC protected by SUBTARGET_R3900. | |
1183 | (sim_engine_run): Use CANCELDELAYSLOT rather than clearing | |
1184 | bits explicitly. | |
1185 | * Makefile.in,configure.in: Add mips subtarget option. | |
1186 | * configure: Update. | |
1187 | ||
7afa8d4e GRK |
1188 | Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com> |
1189 | ||
1190 | * gencode.c: Add r3900 (tx39). | |
1191 | ||
1192 | start-sanitize-tx19 | |
1193 | * gencode.c: Fix some configuration problems by improving | |
1194 | the relationship between tx19 and tx39. | |
1195 | end-sanitize-tx19 | |
1196 | ||
667065d0 GRK |
1197 | Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com> |
1198 | ||
1199 | * gencode.c (build_instruction): Don't need to subtract 4 for | |
1200 | JALR, just 2. | |
1201 | ||
9cb8397f GRK |
1202 | Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com> |
1203 | ||
1204 | * interp.c: Correct some HASFPU problems. | |
1205 | ||
a2ab5e65 AC |
1206 | Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1207 | ||
1208 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
1209 | ||
11ac69e0 AC |
1210 | Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1211 | ||
1212 | * interp.c (mips_options): Fix samples option short form, should | |
1213 | be `x'. | |
1214 | ||
972f3a34 AC |
1215 | Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1216 | ||
1217 | * interp.c (sim_info): Enable info code. Was just returning. | |
1218 | ||
9eeaaefa AC |
1219 | Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1220 | ||
1221 | * interp.c (decode_coproc): Clarify warning about unsuported MTC0, | |
1222 | MFC0. | |
1223 | ||
c31c13b4 AC |
1224 | Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1225 | ||
1226 | * gencode.c (build_instruction): Use SIGNED64 for 64 bit | |
1227 | constants. | |
1228 | (build_instruction): Ditto for LL. | |
1229 | ||
b637f306 GRK |
1230 | start-sanitize-tx19 |
1231 | Sun Sep 7 16:05:46 1997 Gavin Koch <gavin@cygnus.com> | |
1232 | ||
1233 | * mips/configure.in, mips/gencode: Add tx19/r1900. | |
1234 | ||
1235 | end-sanitize-tx19 | |
6fea4763 DE |
1236 | Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba> |
1237 | ||
1238 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
1239 | ||
52352d38 AC |
1240 | start-sanitize-r5900 |
1241 | Mon Sep 1 18:43:30 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
1242 | ||
1243 | * gencode.c (build_instruction): For "pabsw" and "pabsh", check | |
1244 | for overflow due to ABS of MININT, set result to MAXINT. | |
1245 | (build_instruction): For "psrlvw", signextend bit 31. | |
1246 | ||
1247 | end-sanitize-r5900 | |
88117054 AC |
1248 | Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1249 | ||
1250 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
1251 | * config.in: Ditto. | |
1252 | ||
fafce69a AC |
1253 | Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1254 | ||
1255 | * interp.c (sim_open): Add call to sim_analyze_program, update | |
1256 | call to sim_config. | |
1257 | ||
7230ff0f AC |
1258 | Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1259 | ||
1260 | * interp.c (sim_kill): Delete. | |
fafce69a AC |
1261 | (sim_create_inferior): Add ABFD argument. Set PC from same. |
1262 | (sim_load): Move code initializing trap handlers from here. | |
1263 | (sim_open): To here. | |
1264 | (sim_load): Delete, use sim-hload.c. | |
1265 | ||
1266 | * Makefile.in (SIM_OBJS): Add sim-hload.o module. | |
7230ff0f | 1267 | |
247fccde AC |
1268 | Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1269 | ||
1270 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
1271 | * config.in: Ditto. | |
1272 | ||
1273 | Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
1274 | ||
1275 | * interp.c (sim_open): Add ABFD argument. | |
1276 | (sim_load): Move call to sim_config from here. | |
1277 | (sim_open): To here. Check return status. | |
1278 | ||
1279 | start-sanitize-r5900 | |
1280 | * gencode.c (build_instruction): Do not define x8000000000000000, | |
1281 | x7FFFFFFFFFFFFFFF, or xFFFFFFFF80000000. | |
1282 | ||
1283 | end-sanitize-r5900 | |
1284 | start-sanitize-r5900 | |
1285 | Mon Jul 28 19:49:29 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
1286 | ||
1287 | * gencode.c (build_instruction): For "pdivw", "pdivbw" and | |
1288 | "pdivuw" check for overflow due to signed divide by -1. | |
1289 | ||
1290 | end-sanitize-r5900 | |
c12e2e4c GRK |
1291 | Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com> |
1292 | ||
1293 | * gencode.c (build_instruction): Two arg MADD should | |
1294 | not assign result to $0. | |
1295 | ||
1e851d2c AC |
1296 | start-sanitize-r5900 |
1297 | Thu Jul 10 11:58:48 1997 Andrew Cagney <cagney@critters.cygnus.com> | |
1298 | ||
1299 | * gencode.c (build_instruction): For "ppac5" use unsigned | |
1300 | arrithmetic so that the sign bit doesn't smear when right shifted. | |
1301 | (build_instruction): For "pdiv" perform sign extension when | |
1302 | storing results in HI and LO. | |
1303 | (build_instructions): For "pdiv" and "pdivbw" check for | |
1304 | divide-by-zero. | |
1305 | (build_instruction): For "pmfhl.slw" update hi part of dest | |
1306 | register as well as low part. | |
1307 | (build_instruction): For "pmfhl" portably handle long long values. | |
1308 | (build_instruction): For "pmfhl.sh" correctly negative values. | |
1309 | Store half words 2 and three in the correct place. | |
1310 | (build_instruction): For "psllvw", sign extend value after shift. | |
1311 | ||
1312 | end-sanitize-r5900 | |
1313 | Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com) | |
1314 | ||
1315 | * sim/mips/configure: Change default_sim_endian to 0 (bi-endian) | |
1316 | * sim/mips/configure.in: Regenerate. | |
1317 | ||
1318 | Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com> | |
1319 | ||
1320 | * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit | |
1321 | signed8, unsigned8 et.al. types. | |
1322 | ||
1323 | start-sanitize-r5900 | |
1324 | * gencode.c (build_instruction): For PMULTU* do not sign extend | |
1325 | registers. Make generated code easier to debug. | |
1326 | ||
1327 | end-sanitize-r5900 | |
1328 | * interp.c (SUB_REG_FETCH): Handle both little and big endian | |
1329 | hosts when selecting subreg. | |
1330 | ||
1331 | start-sanitize-r5900 | |
1332 | Tue Jul 8 18:07:20 1997 Andrew Cagney <cagney@andros.cygnus.com> | |
1333 | ||
1334 | * gencode.c (type_for_data_len): For 32bit operations concerned | |
1335 | with overflow, perform op using 64bits. | |
1336 | (build_instruction): For PADD, always compute operation using type | |
1337 | returned by type_for_data_len. | |
1338 | (build_instruction): For PSUBU, when overflow, saturate to zero as | |
1339 | actually underflow. | |
1340 | ||
1341 | end-sanitize-r5900 | |
ae19b07b JL |
1342 | Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com) |
1343 | ||
649625bb | 1344 | start-sanitize-r5900 |
64435234 JL |
1345 | * gencode.c (build_instruction): Handle "pext5" according to |
1346 | version 1.95 of the r5900 ISA. | |
1347 | ||
649625bb JL |
1348 | * gencode.c (build_instruction): Handle "ppac5" according to |
1349 | version 1.95 of the r5900 ISA. | |
649625bb | 1350 | |
1e851d2c | 1351 | end-sanitize-r5900 |
05d1322f JL |
1352 | * interp.c (sim_engine_run): Reset the ZERO register to zero |
1353 | regardless of FEATURE_WARN_ZERO. | |
ae19b07b JL |
1354 | * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO. |
1355 | ||
1356 | Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
1357 | ||
1358 | * interp.c (decode_coproc): Implement MTC0 N, CAUSE. | |
1359 | (SignalException): For BreakPoints ignore any mode bits and just | |
1360 | save the PC. | |
1361 | (SignalException): Always set the CAUSE register. | |
1362 | ||
56e7c849 AC |
1363 | Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1364 | ||
1365 | * interp.c (SignalException): Clear the simDELAYSLOT flag when an | |
1366 | exception has been taken. | |
1367 | ||
1368 | * interp.c: Implement the ERET and mt/f sr instructions. | |
1369 | ||
ae19b07b | 1370 | start-sanitize-r5900 |
56e7c849 AC |
1371 | Mon Jun 2 23:28:19 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1372 | ||
1373 | * gencode.c (build_instruction): For paddu, extract unsigned | |
1374 | sub-fields. | |
1375 | ||
1376 | * gencode.c (build_instruction): Saturate padds instead of padd | |
1377 | instructions. | |
1378 | ||
1379 | end-sanitize-r5900 | |
1380 | Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
1381 | ||
1382 | * interp.c (SignalException): Don't bother restarting an | |
1383 | interrupt. | |
1384 | ||
1385 | Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
1386 | ||
1387 | * interp.c (SignalException): Really take an interrupt. | |
1388 | (interrupt_event): Only deliver interrupts when enabled. | |
1389 | ||
1390 | Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
1391 | ||
1392 | * interp.c (sim_info): Only print info when verbose. | |
1393 | (sim_info) Use sim_io_printf for output. | |
1394 | ||
2f2e6c5d AC |
1395 | Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1396 | ||
1397 | * interp.c (CoProcPresent): Add UNUSED attribute - not used by all | |
1398 | mips architectures. | |
1399 | ||
1400 | Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
1401 | ||
1402 | * interp.c (sim_do_command): Check for common commands if a | |
1403 | simulator specific command fails. | |
1404 | ||
d3d2a9f7 GRK |
1405 | Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com> |
1406 | ||
1407 | * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP | |
1408 | and simBE when DEBUG is defined. | |
1409 | ||
50a2a691 AC |
1410 | Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1411 | ||
1412 | * interp.c (interrupt_event): New function. Pass exception event | |
1413 | onto exception handler. | |
1414 | ||
1415 | * configure.in: Check for stdlib.h. | |
1416 | * configure: Regenerate. | |
1417 | ||
1418 | * gencode.c (build_instruction): Add UNUSED attribute to tempS | |
1419 | variable declaration. | |
1420 | (build_instruction): Initialize memval1. | |
1421 | (build_instruction): Add UNUSED attribute to byte, bigend, | |
1422 | reverse. | |
1423 | (build_operands): Ditto. | |
1424 | ||
1425 | * interp.c: Fix GCC warnings. | |
1426 | (sim_get_quit_code): Delete. | |
1427 | ||
1428 | * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS. | |
1429 | * Makefile.in: Ditto. | |
1430 | * configure: Re-generate. | |
1431 | ||
1432 | * Makefile.in (SIM_OBJS): Add sim-watch.o module. | |
1433 | ||
1434 | Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
1435 | ||
1436 | * interp.c (mips_option_handler): New function parse argumes using | |
1437 | sim-options. | |
1438 | (myname): Replace with STATE_MY_NAME. | |
1439 | (sim_open): Delete check for host endianness - performed by | |
1440 | sim_config. | |
1441 | (simHOSTBE, simBE): Delete, replaced by sim-endian flags. | |
1442 | (sim_open): Move much of the initialization from here. | |
1443 | (sim_load): To here. After the image has been loaded and | |
1444 | endianness set. | |
1445 | (sim_open): Move ColdReset from here. | |
1446 | (sim_create_inferior): To here. | |
1447 | (sim_open): Make FP check less dependant on host endianness. | |
1448 | ||
1449 | * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or | |
1450 | run. | |
1451 | * interp.c (sim_set_callbacks): Delete. | |
1452 | ||
1453 | * interp.c (membank, membank_base, membank_size): Replace with | |
1454 | STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE. | |
1455 | (sim_open): Remove call to callback->init. gdb/run do this. | |
1456 | ||
1457 | * interp.c: Update | |
1458 | ||
1459 | * sim-main.h (SIM_HAVE_FLATMEM): Define. | |
1460 | ||
1461 | * interp.c (big_endian_p): Delete, replaced by | |
1462 | current_target_byte_order. | |
1463 | ||
1464 | Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
1465 | ||
1466 | * interp.c (host_read_long, host_read_word, host_swap_word, | |
1467 | host_swap_long): Delete. Using common sim-endian. | |
1468 | (sim_fetch_register, sim_store_register): Use H2T. | |
1469 | (pipeline_ticks): Delete. Handled by sim-events. | |
1470 | (sim_info): Update. | |
1471 | (sim_engine_run): Update. | |
1472 | ||
1473 | Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
1474 | ||
1475 | * interp.c (sim_stop_reason): Move code determining simEXCEPTION | |
1476 | reason from here. | |
1477 | (SignalException): To here. Signal using sim_engine_halt. | |
1478 | (sim_stop_reason): Delete, moved to common. | |
1479 | ||
1480 | Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com> | |
1481 | ||
1482 | * interp.c (sim_open): Add callback argument. | |
1483 | (sim_set_callbacks): Delete SIM_DESC argument. | |
1484 | (sim_size): Ditto. | |
1485 | ||
2e61a3ad AC |
1486 | Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1487 | ||
1488 | * Makefile.in (SIM_OBJS): Add common modules. | |
1489 | ||
1490 | * interp.c (sim_set_callbacks): Also set SD callback. | |
1491 | (set_endianness, xfer_*, swap_*): Delete. | |
1492 | (host_read_word, host_read_long, host_swap_word, host_swap_long): | |
1493 | Change to functions using sim-endian macros. | |
1494 | (control_c, sim_stop): Delete, use common version. | |
1495 | (simulate): Convert into. | |
1496 | (sim_engine_run): This function. | |
1497 | (sim_resume): Delete. | |
1498 | ||
1499 | * interp.c (simulation): New variable - the simulator object. | |
1500 | (sim_kind): Delete global - merged into simulation. | |
1501 | (sim_load): Cleanup. Move PC assignment from here. | |
1502 | (sim_create_inferior): To here. | |
1503 | ||
1504 | * sim-main.h: New file. | |
1505 | * interp.c (sim-main.h): Include. | |
1506 | ||
1507 | Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com> | |
1508 | ||
1509 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
1510 | ||
3be0e228 DE |
1511 | Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com> |
1512 | ||
1513 | * tconfig.in (SIM_HAVE_BIENDIAN): Define. | |
1514 | ||
d654ba0a GRK |
1515 | Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com> |
1516 | ||
1517 | * gencode.c (build_instruction): DIV instructions: check | |
1518 | for division by zero and integer overflow before using | |
1519 | host's division operation. | |
1520 | ||
9d52bcb7 DE |
1521 | Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com> |
1522 | ||
1523 | * Makefile.in (SIM_OBJS): Add sim-load.o. | |
1524 | * interp.c: #include bfd.h. | |
1525 | (target_byte_order): Delete. | |
1526 | (sim_kind, myname, big_endian_p): New static locals. | |
1527 | (sim_open): Set sim_kind, myname. Move call to set_endianness to | |
1528 | after argument parsing. Recognize -E arg, set endianness accordingly. | |
1529 | (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to | |
1530 | load file into simulator. Set PC from bfd. | |
1531 | (sim_create_inferior): Return SIM_RC. Delete arg start_address. | |
1532 | (set_endianness): Use big_endian_p instead of target_byte_order. | |
1533 | ||
87e43259 AC |
1534 | Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1535 | ||
1536 | * interp.c (sim_size): Delete prototype - conflicts with | |
1537 | definition in remote-sim.h. Correct definition. | |
1538 | ||
1539 | Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com> | |
1540 | ||
1541 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
1542 | * config.in: Ditto. | |
1543 | ||
fbda74b1 DE |
1544 | Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com> |
1545 | ||
8a7c3105 DE |
1546 | * interp.c (sim_open): New arg `kind'. |
1547 | ||
fbda74b1 DE |
1548 | * configure: Regenerated to track ../common/aclocal.m4 changes. |
1549 | ||
a35e91c3 AC |
1550 | Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com> |
1551 | ||
1552 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
1553 | ||
1554 | Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com> | |
1555 | ||
1556 | * interp.c (sim_open): Set optind to 0 before calling getopt. | |
1557 | ||
1558 | Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com> | |
1559 | ||
1560 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
1561 | ||
6efa34d8 GRK |
1562 | Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com> |
1563 | ||
1564 | * interp.c : Replace uses of pr_addr with pr_uword64 | |
1565 | where the bit length is always 64 independent of SIM_ADDR. | |
1566 | (pr_uword64) : added. | |
1567 | ||
a77aa7ec AC |
1568 | Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com> |
1569 | ||
1570 | * configure: Re-generate. | |
1571 | ||
601fb8ae MM |
1572 | Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com> |
1573 | ||
1574 | * configure: Regenerate to track ../common/aclocal.m4 changes. | |
1575 | ||
53b9417e DE |
1576 | Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com> |
1577 | ||
1578 | * interp.c (sim_open): New SIM_DESC result. Argument is now | |
1579 | in argv form. | |
1580 | (other sim_*): New SIM_DESC argument. | |
1581 | ||
1582 | start-sanitize-r5900 | |
1583 | Wed Feb 26 18:32:21 1997 Gavin Koch <gavin@cygnus.com> | |
1584 | ||
1585 | * gencode.c (POP_AND,POP_OR,POP_NOR,POP_XOR): | |
1586 | Change values to avoid overloading DOUBLEWORD which is tested | |
1587 | for all insns. | |
1588 | * gencode.c: reinstate "offending code". | |
53b9417e | 1589 | |
56e7c849 | 1590 | end-sanitize-r5900 |
53b9417e DE |
1591 | Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com> |
1592 | ||
1593 | * interp.c: Fix printing of addresses for non-64-bit targets. | |
1594 | (pr_addr): Add function to print address based on size. | |
1595 | start-sanitize-r5900 | |
1596 | * gencode.c: #ifdef out offending code until a permanent fix | |
1597 | can be added. Code is causing build errors for non-5900 mips targets. | |
1598 | end-sanitize-r5900 | |
1599 | ||
1600 | start-sanitize-r5900 | |
1601 | Thu Feb 20 10:40:24 1997 Gavin Koch <gavin@cetus.cygnus.com> | |
1602 | ||
1603 | * gencode.c (process_instructions): Correct test for ISA dependent | |
1604 | architecture bits in isa field of MIPS_DECODE. | |
1605 | ||
1606 | end-sanitize-r5900 | |
7e05106d MA |
1607 | Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com> |
1608 | ||
1609 | * interp.c (simopen): Add support for LSI MiniRISC PMON vectors. | |
1610 | ||
2d18fbc6 | 1611 | start-sanitize-r5900 |
53b9417e | 1612 | Tue Feb 18 17:03:47 1997 Gavin Koch <gavin@cygnus.com> |
2d18fbc6 GRK |
1613 | |
1614 | * gencode.c (MIPS_DECODE): Correct instruction feature flags for | |
1615 | PMADDUW. | |
1616 | ||
1617 | end-sanitize-r5900 | |
1618 | Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com> | |
1619 | ||
1620 | * gencode.c (build_mips16_operands): Correct computation of base | |
1621 | address for extended PC relative instruction. | |
1622 | ||
276c2d7d GRK |
1623 | start-sanitize-r5900 |
1624 | Fri Feb 7 11:12:44 1997 Gavin Koch <gavin@cygnus.com> | |
2d18fbc6 GRK |
1625 | |
1626 | * Makefile.in, configure, configure.in, gencode.c, | |
1627 | interp.c, support.h: add r5900. | |
1628 | ||
276c2d7d | 1629 | end-sanitize-r5900 |
da0bce9c ILT |
1630 | Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com> |
1631 | ||
1632 | * interp.c (mips16_entry): Add support for floating point cases. | |
1633 | (SignalException): Pass floating point cases to mips16_entry. | |
1634 | (ValueFPR): Don't restrict fmt_single and fmt_word to even | |
1635 | registers. | |
1636 | (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single | |
1637 | or fmt_word. | |
1638 | (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR, | |
1639 | and then set the state to fmt_uninterpreted. | |
1640 | (COP_SW): Temporarily set the state to fmt_word while calling | |
1641 | ValueFPR. | |
1642 | ||
6389d856 ILT |
1643 | Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com> |
1644 | ||
1645 | * gencode.c (build_instruction): The high order may be set in the | |
1646 | comparison flags at any ISA level, not just ISA 4. | |
1647 | ||
19c5af72 DE |
1648 | Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com> |
1649 | ||
1650 | * Makefile.in (@COMMON_MAKEFILE_FRAG): Use | |
1651 | COMMON_{PRE,POST}_CONFIG_FRAG instead. | |
1652 | * configure.in: sinclude ../common/aclocal.m4. | |
1653 | * configure: Regenerated. | |
1654 | ||
736a306c ILT |
1655 | Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com> |
1656 | ||
1657 | * configure: Rebuild after change to aclocal.m4. | |
1658 | ||
295dbbe4 SG |
1659 | Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com) |
1660 | ||
1661 | * configure configure.in Makefile.in: Update to new configure | |
1662 | scheme which is more compatible with WinGDB builds. | |
1663 | * configure.in: Improve comment on how to run autoconf. | |
1664 | * configure: Re-run autoconf to get new ../common/aclocal.m4. | |
1665 | * Makefile.in: Use autoconf substitution to install common | |
1666 | makefile fragment. | |
1667 | ||
1668 | Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com> | |
1669 | ||
1670 | * gencode.c (build_instruction): Use BigEndianCPU instead of | |
1671 | ByteSwapMem. | |
1672 | ||
e1db0d47 MA |
1673 | Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com> |
1674 | ||
1675 | * interp.c (sim_monitor): Make output to stdout visible in | |
1676 | wingdb's I/O log window. | |
1677 | ||
2902e8ab MA |
1678 | Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com> |
1679 | ||
1680 | * support.h: Undo previous change to SIGTRAP | |
1681 | and SIGQUIT values. | |
1682 | ||
7e6c297e ILT |
1683 | Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com> |
1684 | ||
1685 | * interp.c (store_word, load_word): New static functions. | |
1686 | (mips16_entry): New static function. | |
1687 | (SignalException): Look for mips16 entry and exit instructions. | |
1688 | (simulate): Use the correct index when setting fpr_state after | |
1689 | doing a pending move. | |
1690 | ||
0049ba7a MA |
1691 | Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com> |
1692 | ||
1693 | * interp.c: Fix byte-swapping code throughout to work on | |
1694 | both little- and big-endian hosts. | |
1695 | ||
2510786b MA |
1696 | Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com> |
1697 | ||
1698 | * support.h: Make definitions of SIGTRAP and SIGQUIT consistent | |
1699 | with gdb/config/i386/xm-windows.h. | |
1700 | ||
39bf0ef4 MA |
1701 | Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com> |
1702 | ||
1703 | * gencode.c (build_instruction): Work around MSVC++ code gen bug | |
1704 | that messes up arithmetic shifts. | |
1705 | ||
dbeec768 SG |
1706 | Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com) |
1707 | ||
1708 | * support.h: Use _WIN32 instead of __WIN32__. Also add defs for | |
1709 | SIGTRAP and SIGQUIT for _WIN32. | |
1710 | ||
deffd638 ILT |
1711 | Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com> |
1712 | ||
1713 | * gencode.c (build_instruction) [MUL]: Cast operands to word64, to | |
1714 | force a 64 bit multiplication. | |
1715 | (build_instruction) [OR]: In mips16 mode, don't do anything if the | |
1716 | destination register is 0, since that is the default mips16 nop | |
1717 | instruction. | |
1718 | ||
aaff8437 ILT |
1719 | Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com> |
1720 | ||
063443cf ILT |
1721 | * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI. |
1722 | (build_endian_shift): Don't check proc64. | |
1723 | (build_instruction): Always set memval to uword64. Cast op2 to | |
1724 | uword64 when shifting it left in memory instructions. Always use | |
1725 | the same code for stores--don't special case proc64. | |
1726 | ||
aaff8437 ILT |
1727 | * gencode.c (build_mips16_operands): Fix base PC value for PC |
1728 | relative operands. | |
1729 | (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a | |
1730 | jal instruction. | |
1731 | * interp.c (simJALDELAYSLOT): Define. | |
1732 | (JALDELAYSLOT): Define. | |
1733 | (INDELAYSLOT, INJALDELAYSLOT): Define. | |
1734 | (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared. | |
1735 | ||
280f90e1 AMT |
1736 | Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com) |
1737 | ||
1738 | * interp.c (sim_open): add flush_cache as a PMON routine | |
1739 | (sim_monitor): handle flush_cache by ignoring it | |
1740 | ||
aaff8437 ILT |
1741 | Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com> |
1742 | ||
1743 | * gencode.c (build_instruction): Use !ByteSwapMem instead of | |
1744 | BigEndianMem. | |
1745 | * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete. | |
1746 | (BigEndianMem): Rename to ByteSwapMem and change sense. | |
1747 | (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change | |
1748 | BigEndianMem references to !ByteSwapMem. | |
1749 | (set_endianness): New function, with prototype. | |
1750 | (sim_open): Call set_endianness. | |
1751 | (sim_info): Use simBE instead of BigEndianMem. | |
1752 | (xfer_direct_word, xfer_direct_long, swap_direct_word, | |
1753 | swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word, | |
1754 | xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER | |
1755 | ifdefs, keeping the prototype declaration. | |
1756 | (swap_word): Rewrite correctly. | |
1757 | (ColdReset): Delete references to CONFIG. Delete endianness related | |
1758 | code; moved to set_endianness. | |
1759 | ||
6429b296 JW |
1760 | Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com> |
1761 | ||
1762 | * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits. | |
1763 | * interp.c (CHECKHILO): Define away. | |
1764 | (simSIGINT): New macro. | |
1765 | (membank_size): Increase from 1MB to 2MB. | |
1766 | (control_c): New function. | |
1767 | (sim_resume): Rename parameter signal to signal_number. Add local | |
1768 | variable prev. Call signal before and after simulate. | |
1769 | (sim_stop_reason): Add simSIGINT support. | |
1770 | (sim_warning, sim_error, dotrace, SignalException): Define as stdarg | |
1771 | functions always. | |
1772 | (sim_warning): Delete call to SignalException. Do call printf_filtered | |
1773 | if logfh is NULL. | |
1774 | (AddressTranslation): Add #ifdef DEBUG around debugging message and | |
1775 | a call to sim_warning. | |
1776 | ||
1777 | Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com> | |
1778 | ||
1779 | * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD | |
1780 | 16 bit instructions. | |
1781 | ||
831f59a2 ILT |
1782 | Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com> |
1783 | ||
1784 | Add support for mips16 (16 bit MIPS implementation): | |
1785 | * gencode.c (inst_type): Add mips16 instruction encoding types. | |
1786 | (GETDATASIZEINSN): Define. | |
1787 | (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add | |
1788 | jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and | |
1789 | mtlo. | |
1790 | (MIPS16_DECODE): New table, for mips16 instructions. | |
1791 | (bitmap_val): New static function. | |
1792 | (struct mips16_op): Define. | |
1793 | (mips16_op_table): New table, for mips16 operands. | |
1794 | (build_mips16_operands): New static function. | |
1795 | (process_instructions): If PC is odd, decode a mips16 | |
1796 | instruction. Break out instruction handling into new | |
1797 | build_instruction function. | |
1798 | (build_instruction): New static function, broken out of | |
1799 | process_instructions. Check modifiers rather than flags for SHIFT | |
1800 | bit count and m[ft]{hi,lo} direction. | |
1801 | (usage): Pass program name to fprintf. | |
1802 | (main): Remove unused variable this_option_optind. Change | |
1803 | ``*loptarg++'' to ``loptarg++''. | |
1804 | (my_strtoul): Parenthesize && within ||. | |
350d33b8 | 1805 | * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd. |
831f59a2 ILT |
1806 | (simulate): If PC is odd, fetch a 16 bit instruction, and |
1807 | increment PC by 2 rather than 4. | |
1808 | * configure.in: Add case for mips16*-*-*. | |
1809 | * configure: Rebuild. | |
1810 | ||
1811 | Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com> | |
1812 | ||
1813 | * interp.c: Allow -t to enable tracing in standalone simulator. | |
1814 | Fix garbage output in trace file and error messages. | |
1815 | ||
e3d12c65 DE |
1816 | Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com> |
1817 | ||
1818 | * Makefile.in: Delete stuff moved to ../common/Make-common.in. | |
1819 | (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define. | |
1820 | * configure.in: Simplify using macros in ../common/aclocal.m4. | |
1821 | * configure: Regenerated. | |
1822 | * tconfig.in: New file. | |
1823 | ||
1824 | Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com> | |
1825 | ||
1826 | * interp.c: Fix bugs in 64-bit port. | |
1827 | Use ansi function declarations for msvc compiler. | |
1828 | Initialize and test file pointer in trace code. | |
1829 | Prevent duplicate definition of LAST_EMED_REGNUM. | |
1830 | ||
1831 | Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com> | |
1832 | ||
1833 | * interp.c (xfer_big_long): Prevent unwanted sign extension. | |
1834 | ||
1835 | Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk> | |
1836 | ||
1837 | * interp.c (SignalException): Check for explicit terminating | |
1838 | breakpoint value. | |
1839 | * gencode.c: Pass instruction value through SignalException() | |
1840 | calls for Trap, Breakpoint and Syscall. | |
1841 | ||
1842 | Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk> | |
1843 | ||
1844 | * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is | |
1845 | only used on those hosts that provide it. | |
1846 | * configure.in: Add sqrt() to list of functions to be checked for. | |
1847 | * config.in: Re-generated. | |
1848 | * configure: Re-generated. | |
1849 | ||
1850 | Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com> | |
1851 | ||
1852 | * gencode.c (process_instructions): Call build_endian_shift when | |
1853 | expanding STORE RIGHT, to fix swr. | |
1854 | * support.h (SIGNEXTEND): If the sign bit is not set, explicitly | |
1855 | clear the high bits. | |
1856 | * interp.c (Convert): Fix fmt_single to fmt_long to not truncate. | |
1857 | Fix float to int conversions to produce signed values. | |
1858 | ||
cc5201d7 ILT |
1859 | Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com> |
1860 | ||
458e1f58 ILT |
1861 | * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction. |
1862 | (process_instructions): Correct handling of nor instruction. | |
1863 | Correct shift count for 32 bit shift instructions. Correct sign | |
1864 | extension for arithmetic shifts to not shift the number of bits in | |
1865 | the type. Fix 64 bit multiply high word calculation. Fix 32 bit | |
1866 | unsigned multiply. Fix ldxc1 and friends to use coprocessor 1. | |
1867 | Fix madd. | |
c05d1721 ILT |
1868 | * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC. |
1869 | It's OK to have a mult follow a mult. What's not OK is to have a | |
1870 | mult follow an mfhi. | |
458e1f58 | 1871 | (Convert): Comment out incorrect rounding code. |
cc5201d7 | 1872 | |
f24b7b69 JSC |
1873 | Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk> |
1874 | ||
1875 | * interp.c (sim_monitor): Improved monitor printf | |
1876 | simulation. Tidied up simulator warnings, and added "--log" option | |
1877 | for directing warning message output. | |
1878 | * gencode.c: Use sim_warning() rather than WARNING macro. | |
1879 | ||
1880 | Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com> | |
1881 | ||
1882 | * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and | |
1883 | getopt1.o, rather than on gencode.c. Link objects together. | |
1884 | Don't link against -liberty. | |
1885 | (gencode.o, getopt.o, getopt1.o): New targets. | |
1886 | * gencode.c: Include <ctype.h> and "ansidecl.h". | |
1887 | (AND): Undefine after including "ansidecl.h". | |
1888 | (ULONG_MAX): Define if not defined. | |
1889 | (OP_*): Don't define macros; now defined in opcode/mips.h. | |
1890 | (main): Call my_strtoul rather than strtoul. | |
1891 | (my_strtoul): New static function. | |
1892 | ||
1893 | Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com) | |
1894 | ||
1895 | * gencode.c (process_instructions): Generate word64 and uword64 | |
1896 | instead of `long long' and `unsigned long long' data types. | |
1897 | * interp.c: #include sysdep.h to get signals, and define default | |
1898 | for SIGBUS. | |
1899 | * (Convert): Work around for Visual-C++ compiler bug with type | |
1900 | conversion. | |
1901 | * support.h: Make things compile under Visual-C++ by using | |
1902 | __int64 instead of `long long'. Change many refs to long long | |
1903 | into word64/uword64 typedefs. | |
1904 | ||
a271d1d9 JM |
1905 | Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp) |
1906 | ||
1907 | * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir, | |
1908 | INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values. | |
1909 | (docdir): Removed. | |
1910 | * configure.in (AC_PREREQ): autoconf 2.5 or higher. | |
1911 | (AC_PROG_INSTALL): Added. | |
1912 | (AC_PROG_CC): Moved to before configure.host call. | |
1913 | * configure: Rebuilt. | |
1914 | ||
1915 | Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk> | |
1916 | ||
1917 | * configure.in: Define @SIMCONF@ depending on mips target. | |
1918 | * configure: Rebuild. | |
1919 | * Makefile.in (run): Add @SIMCONF@ to control simulator | |
1920 | construction. | |
1921 | * gencode.c: Change LOADDRMASK to 64bit memory model only. | |
1922 | * interp.c: Remove some debugging, provide more detailed error | |
1923 | messages, update memory accesses to use LOADDRMASK. | |
1924 | ||
4fa134be ILT |
1925 | Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com> |
1926 | ||
1927 | * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS, | |
1928 | AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set | |
1929 | stamp-h. | |
1930 | * configure: Rebuild. | |
1931 | * config.in: New file, generated by autoheader. | |
1932 | * interp.c: Include "config.h". Include <stdlib.h>, <string.h>, | |
1933 | and <strings.h> if they exist. Replace #ifdef sun with #ifdef | |
1934 | HAVE_ANINT and HAVE_AINT, as appropriate. | |
1935 | * Makefile.in (run): Use @LIBS@ rather than -lm. | |
1936 | (interp.o): Depend upon config.h. | |
1937 | (Makefile): Just rebuild Makefile. | |
1938 | (clean): Remove stamp-h. | |
1939 | (mostlyclean): Make the same as clean, not as distclean. | |
1940 | (config.h, stamp-h): New targets. | |
1941 | ||
1942 | Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk> | |
1943 | ||
1944 | * interp.c (ColdReset): Fix boolean test. Make all simulator | |
1945 | globals static. | |
1946 | ||
f7481d45 JSC |
1947 | Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk> |
1948 | ||
1949 | * interp.c (xfer_direct_word, xfer_direct_long, | |
1950 | swap_direct_word, swap_direct_long, xfer_big_word, | |
1951 | xfer_big_long, xfer_little_word, xfer_little_long, | |
1952 | swap_word,swap_long): Added. | |
1953 | * interp.c (ColdReset): Provide function indirection to | |
1954 | host<->simulated_target transfer routines. | |
1955 | * interp.c (sim_store_register, sim_fetch_register): Updated to | |
1956 | make use of indirected transfer routines. | |
1957 | ||
1958 | Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk> | |
1959 | ||
1960 | * gencode.c (process_instructions): Ensure FP ABS instruction | |
1961 | recognised. | |
1962 | * interp.c (AbsoluteValue): Add routine. Also provide simple PMON | |
1963 | system call support. | |
1964 | ||
8b554809 JSC |
1965 | Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk> |
1966 | ||
1967 | * interp.c (sim_do_command): Complain if callback structure not | |
1968 | initialised. | |
1969 | ||
d0757082 JSC |
1970 | Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk> |
1971 | ||
1972 | * interp.c (Convert): Provide round-to-nearest and round-to-zero | |
1973 | support for Sun hosts. | |
1974 | * Makefile.in (gencode): Ensure the host compiler and libraries | |
1975 | used for cross-hosted build. | |
1976 | ||
e871dd18 JSC |
1977 | Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk> |
1978 | ||
1979 | * interp.c, gencode.c: Some more (TODO) tidying. | |
1980 | ||
1981 | Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk> | |
1982 | ||
1983 | * gencode.c, interp.c: Replaced explicit long long references with | |
1984 | WORD64HI, WORD64LO, SET64HI and SET64LO macro calls. | |
1985 | * support.h (SET64LO, SET64HI): Macros added. | |
1986 | ||
5c59ec43 ILT |
1987 | Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com> |
1988 | ||
1989 | * configure: Regenerate with autoconf 2.7. | |
1990 | ||
1991 | Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com> | |
1992 | ||
1993 | * interp.c (LoadMemory): Enclose text following #endif in /* */. | |
1994 | * support.h: Remove superfluous "1" from #if. | |
1995 | * support.h (CHECKSIM): Remove stray 'a' at end of line. | |
1996 | ||
1997 | Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com> | |
1998 | ||
1999 | * interp.c (StoreFPR): Control UndefinedResult() call on | |
2000 | WARN_RESULT manifest. | |
2001 | ||
8bae0a0c JSC |
2002 | Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk> |
2003 | ||
2004 | * gencode.c: Tidied instruction decoding, and added FP instruction | |
2005 | support. | |
2006 | ||
2007 | * interp.c: Added dineroIII, and BSD profiling support. Also | |
2008 | run-time FP handling. | |
2009 | ||
2010 | Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk> | |
2011 | ||
2012 | * Changelog, Makefile.in, README.Cygnus, configure, configure.in, | |
2013 | gencode.c, interp.c, support.h: created. |