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[deliverable/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
6b4a8935
AC		 12003-02-27 Andrew Cagney <cagney@redhat.com>
2
3 * interp.c (sim_open):
4 (sim_create_inferior):
5
d29e330f
CD		 62003-01-14 Chris Demetriou <cgd@broadcom.com>
7
8 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
9
a2353a08
CD		 102003-01-14 Chris Demetriou <cgd@broadcom.com>
11
12 * mips.igen (EI, DI): Remove.
13
80551777
CD		 142003-01-05 Richard Sandiford <rsandifo@redhat.com>
15
16 * Makefile.in (tmp-run-multi): Fix mips16 filter.
17
4c54fc26
CD		 182003-01-04 Richard Sandiford <rsandifo@redhat.com>
19 Andrew Cagney <ac131313@redhat.com>
20 Gavin Romig-Koch <gavin@redhat.com>
21 Graydon Hoare <graydon@redhat.com>
22 Aldy Hernandez <aldyh@redhat.com>
23 Dave Brolley <brolley@redhat.com>
24 Chris Demetriou <cgd@broadcom.com>
25
26 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
27 (sim_mach_default): New variable.
28 (mips64vr-*-*, mips64vrel-*-*): New configurations.
29 Add a new simulator generator, MULTI.
30 * configure: Regenerate.
31 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
32 (multi-run.o): New dependency.
33 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
34 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
35 (tmp-multi): Combine them.
36 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
37 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
38 (distclean-extra): New rule.
39 * sim-main.h: Include bfd.h.
40 (MIPS_MACH): New macro.
41 * mips.igen (vr4120, vr5400, vr5500): New models.
42 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
43 * vr.igen: Replace with new version.
44
e6c674b8
CD		 452003-01-04 Chris Demetriou <cgd@broadcom.com>
46
47 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
48 * configure: Regenerate.
49
28f50ac8
CD		 502002-12-31 Chris Demetriou <cgd@broadcom.com>
51
52 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
53 * mips.igen: Remove all invocations of check_branch_bug and
54 mark_branch_bug.
55
5071ffe6
CD		 562002-12-16 Chris Demetriou <cgd@broadcom.com>
57
58 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
59
06e7837e
CD		 602002-07-30 Chris Demetriou <cgd@broadcom.com>
61
62 * mips.igen (do_load_double, do_store_double): New functions.
63 (LDC1, SDC1): Rename to...
64 (LDC1b, SDC1b): respectively.
65 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
66
2265c243
MS		 672002-07-29 Michael Snyder <msnyder@redhat.com>
68
69 * cp1.c (fp_recip2): Modify initialization expression so that
70 GCC will recognize it as constant.
71
a2f8b4f3
CD		 722002-06-18 Chris Demetriou <cgd@broadcom.com>
73
74 * mdmx.c (SD_): Delete.
75 (Unpredictable): Re-define, for now, to directly invoke
76 unpredictable_action().
77 (mdmx_acc_op): Fix error in .ob immediate handling.
78
b4b6c939
AC		 792002-06-18 Andrew Cagney <cagney@redhat.com>
80
81 * interp.c (sim_firmware_command): Initialize `address'.
82
c8cca39f
AC		 832002-06-16 Andrew Cagney <ac131313@redhat.com>
84
85 * configure: Regenerated to track ../common/aclocal.m4 changes.
86
e7e81181
CD		 872002-06-14 Chris Demetriou <cgd@broadcom.com>
88 Ed Satterthwaite <ehs@broadcom.com>
89
90 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
91 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
92 * mips.igen: Include mips3d.igen.
93 (mips3d): New model name for MIPS-3D ASE instructions.
94 (CVT.W.fmt): Don't use this instruction for word (source) format
95 instructions.
96 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
97 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
98 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
99 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
100 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
101 (RSquareRoot1, RSquareRoot2): New macros.
102 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
103 (fp_rsqrt2): New functions.
104 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
105 * configure: Regenerate.
106
3a2b820e 1072002-06-13 Chris Demetriou <cgd@broadcom.com>
eab54952 108 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 109
110 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
111 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
112 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
113 (convert): Note that this function is not used for paired-single
114 format conversions.
115 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
116 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
117 (check_fmt_p): Enable paired-single support.
118 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
119 (PUU.PS): New instructions.
120 (CVT.S.fmt): Don't use this instruction for paired-single format
121 destinations.
122 * sim-main.h (FP_formats): New value 'fmt_ps.'
123 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
124 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
125
d18ea9c2
CD		 1262002-06-12 Chris Demetriou <cgd@broadcom.com>
127
128 * mips.igen: Fix formatting of function calls in
129 many FP operations.
130
95fd5cee
CD		 1312002-06-12 Chris Demetriou <cgd@broadcom.com>
132
133 * mips.igen (MOVN, MOVZ): Trace result.
134 (TNEI): Print "tnei" as the opcode name in traces.
135 (CEIL.W): Add disassembly string for traces.
136 (RSQRT.fmt): Make location of disassembly string consistent
137 with other instructions.
138
4f0d55ae
CD		 1392002-06-12 Chris Demetriou <cgd@broadcom.com>
140
141 * mips.igen (X): Delete unused function.
142
3c25f8c7
AC		 1432002-06-08 Andrew Cagney <cagney@redhat.com>
144
145 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
146
f3c08b7e
CD		 1472002-06-07 Chris Demetriou <cgd@broadcom.com>
148 Ed Satterthwaite <ehs@broadcom.com>
149
150 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
151 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
152 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
153 (fp_nmsub): New prototypes.
154 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
155 (NegMultiplySub): New defines.
156 * mips.igen (RSQRT.fmt): Use RSquareRoot().
157 (MADD.D, MADD.S): Replace with...
158 (MADD.fmt): New instruction.
159 (MSUB.D, MSUB.S): Replace with...
160 (MSUB.fmt): New instruction.
161 (NMADD.D, NMADD.S): Replace with...
162 (NMADD.fmt): New instruction.
163 (NMSUB.D, MSUB.S): Replace with...
164 (NMSUB.fmt): New instruction.
165
52714ff9
CD		 1662002-06-07 Chris Demetriou <cgd@broadcom.com>
167 Ed Satterthwaite <ehs@broadcom.com>
168
169 * cp1.c: Fix more comment spelling and formatting.
170 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
171 (denorm_mode): New function.
172 (fpu_unary, fpu_binary): Round results after operation, collect
173 status from rounding operations, and update the FCSR.
174 (convert): Collect status from integer conversions and rounding
175 operations, and update the FCSR. Adjust NaN values that result
176 from conversions. Convert to use sim_io_eprintf rather than
177 fprintf, and remove some debugging code.
178 * cp1.h (fenr_FS): New define.
179
577d8c4b
CD		 1802002-06-07 Chris Demetriou <cgd@broadcom.com>
181
182 * cp1.c (convert): Remove unusable debugging code, and move MIPS
183 rounding mode to sim FP rounding mode flag conversion code into...
184 (rounding_mode): New function.
185
196496ed
CD		 1862002-06-07 Chris Demetriou <cgd@broadcom.com>
187
188 * cp1.c: Clean up formatting of a few comments.
189 (value_fpr): Reformat switch statement.
190
cfe9ea23
CD		 1912002-06-06 Chris Demetriou <cgd@broadcom.com>
192 Ed Satterthwaite <ehs@broadcom.com>
193
194 * cp1.h: New file.
195 * sim-main.h: Include cp1.h.
196 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
197 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
198 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
199 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
200 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
201 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
202 * cp1.c: Don't include sim-fpu.h; already included by
203 sim-main.h. Clean up formatting of some comments.
204 (NaN, Equal, Less): Remove.
205 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
206 (fp_cmp): New functions.
207 * mips.igen (do_c_cond_fmt): Remove.
208 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
209 Compare. Add result tracing.
210 (CxC1): Remove, replace with...
211 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
212 (DMxC1): Remove, replace with...
213 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
214 (MxC1): Remove, replace with...
215 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
216
ee7254b0
CD		 2172002-06-04 Chris Demetriou <cgd@broadcom.com>
218
219 * sim-main.h (FGRIDX): Remove, replace all uses with...
220 (FGR_BASE): New macro.
221 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
222 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
223 (NR_FGR, FGR): Likewise.
224 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
225 * mips.igen: Likewise.
226
d3eb724f
CD		 2272002-06-04 Chris Demetriou <cgd@broadcom.com>
228
229 * cp1.c: Add an FSF Copyright notice to this file.
230
ba46ddd0
CD		 2312002-06-04 Chris Demetriou <cgd@broadcom.com>
232 Ed Satterthwaite <ehs@broadcom.com>
233
234 * cp1.c (Infinity): Remove.
235 * sim-main.h (Infinity): Likewise.
236
237 * cp1.c (fp_unary, fp_binary): New functions.
238 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
239 (fp_sqrt): New functions, implemented in terms of the above.
240 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
241 (Recip, SquareRoot): Remove (replaced by functions above).
242 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
243 (fp_recip, fp_sqrt): New prototypes.
244 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
245 (Recip, SquareRoot): Replace prototypes with #defines which
246 invoke the functions above.
247
18d8a52d
CD		 2482002-06-03 Chris Demetriou <cgd@broadcom.com>
249
250 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
251 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
252 file, remove PARAMS from prototypes.
253 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
254 simulator state arguments.
255 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
256 pass simulator state arguments.
257 * cp1.c (SD): Redefine as CPU_STATE(cpu).
258 (store_fpr, convert): Remove 'sd' argument.
259 (value_fpr): Likewise. Convert to use 'SD' instead.
260
0f154cbd
CD		 2612002-06-03 Chris Demetriou <cgd@broadcom.com>
262
263 * cp1.c (Min, Max): Remove #if 0'd functions.
264 * sim-main.h (Min, Max): Remove.
265
e80fc152
CD		 2662002-06-03 Chris Demetriou <cgd@broadcom.com>
267
268 * cp1.c: fix formatting of switch case and default labels.
269 * interp.c: Likewise.
270 * sim-main.c: Likewise.
271
bad673a9
CD		 2722002-06-03 Chris Demetriou <cgd@broadcom.com>
273
274 * cp1.c: Clean up comments which describe FP formats.
275 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
276
7cbea089
CD		 2772002-06-03 Chris Demetriou <cgd@broadcom.com>
278 Ed Satterthwaite <ehs@broadcom.com>
279
280 * configure.in (mipsisa64sb1*-*-*): New target for supporting
281 Broadcom SiByte SB-1 processor configurations.
282 * configure: Regenerate.
283 * sb1.igen: New file.
284 * mips.igen: Include sb1.igen.
285 (sb1): New model.
286 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
287 * mdmx.igen: Add "sb1" model to all appropriate functions and
288 instructions.
289 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
290 (ob_func, ob_acc): Reference the above.
291 (qh_acc): Adjust to keep the same size as ob_acc.
292 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
293 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
294
909daa82
CD		 2952002-06-03 Chris Demetriou <cgd@broadcom.com>
296
297 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
298
f4f1b9f1
CD		 2992002-06-02 Chris Demetriou <cgd@broadcom.com>
300 Ed Satterthwaite <ehs@broadcom.com>
301
302 * mips.igen (mdmx): New (pseudo-)model.
303 * mdmx.c, mdmx.igen: New files.
304 * Makefile.in (SIM_OBJS): Add mdmx.o.
305 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
306 New typedefs.
307 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
308 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
309 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
310 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
311 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
312 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
313 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
314 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
315 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
316 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
317 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
318 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
319 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
320 (qh_fmtsel): New macros.
321 (_sim_cpu): New member "acc".
322 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
323 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
324
5accf1ff
CD		 3252002-05-01 Chris Demetriou <cgd@broadcom.com>
326
327 * interp.c: Use 'deprecated' rather than 'depreciated.'
328 * sim-main.h: Likewise.
329
402586aa
CD		 3302002-05-01 Chris Demetriou <cgd@broadcom.com>
331
332 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
333 which wouldn't compile anyway.
334 * sim-main.h (unpredictable_action): New function prototype.
335 (Unpredictable): Define to call igen function unpredictable().
336 (NotWordValue): New macro to call igen function not_word_value().
337 (UndefinedResult): Remove.
338 * interp.c (undefined_result): Remove.
339 (unpredictable_action): New function.
340 * mips.igen (not_word_value, unpredictable): New functions.
341 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
342 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
343 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
344 NotWordValue() to check for unpredictable inputs, then
345 Unpredictable() to handle them.
346
c9b9995a
CD		 3472002-02-24 Chris Demetriou <cgd@broadcom.com>
348
349 * mips.igen: Fix formatting of calls to Unpredictable().
350
e1015982
AC		 3512002-04-20 Andrew Cagney <ac131313@redhat.com>
352
353 * interp.c (sim_open): Revert previous change.
354
b882a66b
AO		 3552002-04-18 Alexandre Oliva <aoliva@redhat.com>
356
357 * interp.c (sim_open): Disable chunk of code that wrote code in
358 vector table entries.
359
c429b7dd
CD		 3602002-03-19 Chris Demetriou <cgd@broadcom.com>
361
362 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
363 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
364 unused definitions.
365
37d146fa
CD		 3662002-03-19 Chris Demetriou <cgd@broadcom.com>
367
368 * cp1.c: Fix many formatting issues.
369
07892c0b
CD		 3702002-03-19 Chris G. Demetriou <cgd@broadcom.com>
371
372 * cp1.c (fpu_format_name): New function to replace...
373 (DOFMT): This. Delete, and update all callers.
374 (fpu_rounding_mode_name): New function to replace...
375 (RMMODE): This. Delete, and update all callers.
376
487f79b7
CD		 3772002-03-19 Chris G. Demetriou <cgd@broadcom.com>
378
379 * interp.c: Move FPU support routines from here to...
380 * cp1.c: Here. New file.
381 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
382 (cp1.o): New target.
383
1e799e28
CD		 3842002-03-12 Chris Demetriou <cgd@broadcom.com>
385
386 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
387 * mips.igen (mips32, mips64): New models, add to all instructions
388 and functions as appropriate.
389 (loadstore_ea, check_u64): New variant for model mips64.
390 (check_fmt_p): New variant for models mipsV and mips64, remove
391 mipsV model marking fro other variant.
392 (SLL) Rename to...
393 (SLLa) this.
394 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
395 for mips32 and mips64.
396 (DCLO, DCLZ): New instructions for mips64.
397
82f728db
CD		 3982002-03-07 Chris Demetriou <cgd@broadcom.com>
399
400 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
401 immediate or code as a hex value with the "%#lx" format.
402 (ANDI): Likewise, and fix printed instruction name.
403
b96e7ef1
CD		 4042002-03-05 Chris Demetriou <cgd@broadcom.com>
405
406 * sim-main.h (UndefinedResult, Unpredictable): New macros
407 which currently do nothing.
408
d35d4f70
CD		 4092002-03-05 Chris Demetriou <cgd@broadcom.com>
410
411 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
412 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
413 (status_CU3): New definitions.
414
415 * sim-main.h (ExceptionCause): Add new values for MIPS32
416 and MIPS64: MDMX, MCheck, CacheErr. Update comments
417 for DebugBreakPoint and NMIReset to note their status in
418 MIPS32 and MIPS64.
419 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
420 (SignalExceptionCacheErr): New exception macros.
421
3ad6f714
CD		 4222002-03-05 Chris Demetriou <cgd@broadcom.com>
423
424 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
425 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
426 is always enabled.
427 (SignalExceptionCoProcessorUnusable): Take as argument the
428 unusable coprocessor number.
429
86b77b47
CD		 4302002-03-05 Chris Demetriou <cgd@broadcom.com>
431
432 * mips.igen: Fix formatting of all SignalException calls.
433
97a88e93 4342002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 435
436 * sim-main.h (SIGNEXTEND): Remove.
437
97a88e93 4382002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 439
440 * mips.igen: Remove gencode comment from top of file, fix
441 spelling in another comment.
442
97a88e93 4432002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 444
445 * mips.igen (check_fmt, check_fmt_p): New functions to check
446 whether specific floating point formats are usable.
447 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
448 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
449 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
450 Use the new functions.
451 (do_c_cond_fmt): Remove format checks...
452 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
453
97a88e93 4542002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 455
456 * mips.igen: Fix formatting of check_fpu calls.
457
41774c9d
CD		 4582002-03-03 Chris Demetriou <cgd@broadcom.com>
459
460 * mips.igen (FLOOR.L.fmt): Store correct destination register.
461
4a0bd876
CD		 4622002-03-03 Chris Demetriou <cgd@broadcom.com>
463
464 * mips.igen: Remove whitespace at end of lines.
465
09297648
CD		 4662002-03-02 Chris Demetriou <cgd@broadcom.com>
467
468 * mips.igen (loadstore_ea): New function to do effective
469 address calculations.
470 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
471 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
472 CACHE): Use loadstore_ea to do effective address computations.
473
043b7057
CD		 4742002-03-02 Chris Demetriou <cgd@broadcom.com>
475
476 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
477 * mips.igen (LL, CxC1, MxC1): Likewise.
478
c1e8ada4
CD		 4792002-03-02 Chris Demetriou <cgd@broadcom.com>
480
481 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
482 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
483 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
484 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
485 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
486 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
487 Don't split opcode fields by hand, use the opcode field values
488 provided by igen.
489
3e1dca16
CD		 4902002-03-01 Chris Demetriou <cgd@broadcom.com>
491
492 * mips.igen (do_divu): Fix spacing.
493
494 * mips.igen (do_dsllv): Move to be right before DSLLV,
495 to match the rest of the do_<shift> functions.
496
fff8d27d
CD		 4972002-03-01 Chris Demetriou <cgd@broadcom.com>
498
499 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
500 DSRL32, do_dsrlv): Trace inputs and results.
501
0d3e762b
CD		 5022002-03-01 Chris Demetriou <cgd@broadcom.com>
503
504 * mips.igen (CACHE): Provide instruction-printing string.
505
506 * interp.c (signal_exception): Comment tokens after #endif.
507
eb5fcf93
CD		 5082002-02-28 Chris Demetriou <cgd@broadcom.com>
509
510 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
511 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
512 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
513 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
514 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
515 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
516 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
517 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
518
bb22bd7d
CD		 5192002-02-28 Chris Demetriou <cgd@broadcom.com>
520
521 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
522 instruction-printing string.
523 (LWU): Use '64' as the filter flag.
524
91a177cf
CD		 5252002-02-28 Chris Demetriou <cgd@broadcom.com>
526
527 * mips.igen (SDXC1): Fix instruction-printing string.
528
387f484a
CD		 5292002-02-28 Chris Demetriou <cgd@broadcom.com>
530
531 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
532 filter flags "32,f".
533
3d81f391
CD		 5342002-02-27 Chris Demetriou <cgd@broadcom.com>
535
536 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
537 as the filter flag.
538
af5107af
CD		 5392002-02-27 Chris Demetriou <cgd@broadcom.com>
540
541 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
542 add a comma) so that it more closely match the MIPS ISA
543 documentation opcode partitioning.
544 (PREF): Put useful names on opcode fields, and include
545 instruction-printing string.
546
ca971540
CD		 5472002-02-27 Chris Demetriou <cgd@broadcom.com>
548
549 * mips.igen (check_u64): New function which in the future will
550 check whether 64-bit instructions are usable and signal an
551 exception if not. Currently a no-op.
552 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
553 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
554 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
555 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
556
557 * mips.igen (check_fpu): New function which in the future will
558 check whether FPU instructions are usable and signal an exception
559 if not. Currently a no-op.
560 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
561 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
562 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
563 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
564 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
565 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
566 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
567 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
568
1c47a468
CD		 5692002-02-27 Chris Demetriou <cgd@broadcom.com>
570
571 * mips.igen (do_load_left, do_load_right): Move to be immediately
572 following do_load.
573 (do_store_left, do_store_right): Move to be immediately following
574 do_store.
575
603a98e7
CD		 5762002-02-27 Chris Demetriou <cgd@broadcom.com>
577
578 * mips.igen (mipsV): New model name. Also, add it to
579 all instructions and functions where it is appropriate.
580
c5d00cc7
CD		 5812002-02-18 Chris Demetriou <cgd@broadcom.com>
582
583 * mips.igen: For all functions and instructions, list model
584 names that support that instruction one per line.
585
074e9cb8
CD		 5862002-02-11 Chris Demetriou <cgd@broadcom.com>
587
588 * mips.igen: Add some additional comments about supported
589 models, and about which instructions go where.
590 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
591 order as is used in the rest of the file.
592
9805e229
CD		 5932002-02-11 Chris Demetriou <cgd@broadcom.com>
594
595 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
596 indicating that ALU32_END or ALU64_END are there to check
597 for overflow.
598 (DADD): Likewise, but also remove previous comment about
599 overflow checking.
600
f701dad2
CD		 6012002-02-10 Chris Demetriou <cgd@broadcom.com>
602
603 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
604 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
605 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
606 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
607 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
608 fields (i.e., add and move commas) so that they more closely
609 match the MIPS ISA documentation opcode partitioning.
610
6112002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098
CD		 612
613 * mips.igen (ADDI): Print immediate value.
614 (BREAK): Print code.
615 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
616 (SLL): Print "nop" specially, and don't run the code
617 that does the shift for the "nop" case.
618
9e52972e
FF		 6192001-11-17 Fred Fish <fnf@redhat.com>
620
621 * sim-main.h (float_operation): Move enum declaration outside
622 of _sim_cpu struct declaration.
623
c0efbca4
JB		 6242001-04-12 Jim Blandy <jimb@redhat.com>
625
626 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
627 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
628 set of the FCSR.
629 * sim-main.h (COCIDX): Remove definition; this isn't supported by
630 PENDING_FILL, and you can get the intended effect gracefully by
631 calling PENDING_SCHED directly.
632
fb891446
BE		 6332001-02-23 Ben Elliston <bje@redhat.com>
634
635 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
636 already defined elsewhere.
637
8030f857
BE		 6382001-02-19 Ben Elliston <bje@redhat.com>
639
640 * sim-main.h (sim_monitor): Return an int.
641 * interp.c (sim_monitor): Add return values.
642 (signal_exception): Handle error conditions from sim_monitor.
643
56b48a7a
CD		 6442001-02-08 Ben Elliston <bje@redhat.com>
645
646 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
647 (store_memory): Likewise, pass cia to sim_core_write*.
648
d3ee60d9
FCE		 6492000-10-19 Frank Ch. Eigler <fche@redhat.com>
650
651 On advice from Chris G. Demetriou <cgd@sibyte.com>:
652 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
653
071da002
AC		 654Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
655
656 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
657 * Makefile.in: Don't delete *.igen when cleaning directory.
658
a28c02cd
AC		 659Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
660
661 * m16.igen (break): Call SignalException not sim_engine_halt.
662
80ee11fa
AC		 663Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
664
665 From Jason Eckhardt:
666 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
667
673388c0
AC		 668Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
669
670 * mips.igen (MxC1, DMxC1): Fix printf formatting.
671
4c0deff4
NC		 6722000-05-24 Michael Hayes <mhayes@cygnus.com>
673
674 * mips.igen (do_dmultx): Fix typo.
675
eb2d80b4
AC		 676Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
677
678 * configure: Regenerated to track ../common/aclocal.m4 changes.
679
dd37a34b
AC		 680Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
681
682 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
683
4c0deff4
NC		 6842000-04-12 Frank Ch. Eigler <fche@redhat.com>
685
686 * sim-main.h (GPR_CLEAR): Define macro.
687
e30db738
AC		 688Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
689
690 * interp.c (decode_coproc): Output long using %lx and not %s.
691
cb7450ea
FCE		 6922000-03-21 Frank Ch. Eigler <fche@redhat.com>
693
694 * interp.c (sim_open): Sort & extend dummy memory regions for
695 --board=jmr3904 for eCos.
696
a3027dd7
FCE		 6972000-03-02 Frank Ch. Eigler <fche@redhat.com>
698
699 * configure: Regenerated.
700
701Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
702
703 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
704 calls, conditional on the simulator being in verbose mode.
705
dfcd3bfb
JM		 706Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
707
708 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
709 cache don't get ReservedInstruction traps.
710
c2d11a7d
JM		 7111999-11-29 Mark Salter <msalter@cygnus.com>
712
713 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
714 to clear status bits in sdisr register. This is how the hardware works.
715
716 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
717 being used by cygmon.
718
4ce44c66
JM		 7191999-11-11 Andrew Haley <aph@cygnus.com>
720
721 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
722 instructions.
723
cff3e48b
JM		 724Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
725
726 * mips.igen (MULT): Correct previous mis-applied patch.
727
d4f3574e
SS		 728Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
729
730 * mips.igen (delayslot32): Handle sequence like
731 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
732 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
733 (MULT): Actually pass the third register...
734
7351999-09-03 Mark Salter <msalter@cygnus.com>
736
737 * interp.c (sim_open): Added more memory aliases for additional
738 hardware being touched by cygmon on jmr3904 board.
739
740Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
741
742 * configure: Regenerated to track ../common/aclocal.m4 changes.
743
a0b3c4fd
JM		 744Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
745
746 * interp.c (sim_store_register): Handle case where client - GDB -
747 specifies that a 4 byte register is 8 bytes in size.
748 (sim_fetch_register): Ditto.
749
adf40b2e
JM		 7501999-07-14 Frank Ch. Eigler <fche@cygnus.com>
751
752 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
753 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
754 (idt_monitor_base): Base address for IDT monitor traps.
755 (pmon_monitor_base): Ditto for PMON.
756 (lsipmon_monitor_base): Ditto for LSI PMON.
757 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
758 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
759 (sim_firmware_command): New function.
760 (mips_option_handler): Call it for OPTION_FIRMWARE.
761 (sim_open): Allocate memory for idt_monitor region. If "--board"
762 option was given, add no monitor by default. Add BREAK hooks only if
763 monitors are also there.
764
43e526b9
JM		 765Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
766
767 * interp.c (sim_monitor): Flush output before reading input.
768
769Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
770
771 * tconfig.in (SIM_HANDLES_LMA): Always define.
772
773Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
774
775 From Mark Salter <msalter@cygnus.com>:
776 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
777 (sim_open): Add setup for BSP board.
778
9846de1b
JM		 779Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
780
781 * mips.igen (MULT, MULTU): Add syntax for two operand version.
782 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
783 them as unimplemented.
784
cd0fc7c3
SS		 7851999-05-08 Felix Lee <flee@cygnus.com>
786
787 * configure: Regenerated to track ../common/aclocal.m4 changes.
788
7a292a7a
SS		 7891999-04-21 Frank Ch. Eigler <fche@cygnus.com>
790
791 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
792
793Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
794
795 * configure.in: Any mips64vr5*-*-* target should have
796 -DTARGET_ENABLE_FR=1.
797 (default_endian): Any mips64vr*el-*-* target should default to
798 LITTLE_ENDIAN.
799 * configure: Re-generate.
800
8011999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
802
803 * mips.igen (ldl): Extend from _16_, not 32.
804
805Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
806
807 * interp.c (sim_store_register): Force registers written to by GDB
808 into an un-interpreted state.
809
c906108c
SS		 8101999-02-05 Frank Ch. Eigler <fche@cygnus.com>
811
812 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
813 CPU, start periodic background I/O polls.
814 (tx3904sio_poll): New function: periodic I/O poller.
815
8161998-12-30 Frank Ch. Eigler <fche@cygnus.com>
817
818 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
819
820Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
821
822 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
823 case statement.
824
8251998-12-29 Frank Ch. Eigler <fche@cygnus.com>
826
827 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
828 (load_word): Call SIM_CORE_SIGNAL hook on error.
829 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
830 starting. For exception dispatching, pass PC instead of NULL_CIA.
831 (decode_coproc): Use COP0_BADVADDR to store faulting address.
832 * sim-main.h (COP0_BADVADDR): Define.
833 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
834 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
835 (_sim_cpu): Add exc_* fields to store register value snapshots.
836 * mips.igen (*): Replace memory-related SignalException* calls
837 with references to SIM_CORE_SIGNAL hook.
838
839 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
840 fix.
841 * sim-main.c (*): Minor warning cleanups.
842
8431998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
844
845 * m16.igen (DADDIU5): Correct type-o.
846
847Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
848
849 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
850 variables.
851
852Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
853
854 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
855 to include path.
856 (interp.o): Add dependency on itable.h
857 (oengine.c, gencode): Delete remaining references.
858 (BUILT_SRC_FROM_GEN): Clean up.
859
8601998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
861
862 * vr4run.c: New.
863 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
864 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
865 tmp-run-hack) : New.
866 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
867 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
868 Drop the "64" qualifier to get the HACK generator working.
869 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
870 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
871 qualifier to get the hack generator working.
872 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
873 (DSLL): Use do_dsll.
874 (DSLLV): Use do_dsllv.
875 (DSRA): Use do_dsra.
876 (DSRL): Use do_dsrl.
877 (DSRLV): Use do_dsrlv.
878 (BC1): Move *vr4100 to get the HACK generator working.
879 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
880 get the HACK generator working.
881 (MACC) Rename to get the HACK generator working.
882 (DMACC,MACCS,DMACCS): Add the 64.
883
8841998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
885
886 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
887 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
888
8891998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
890
891 * mips/interp.c (DEBUG): Cleanups.
892
8931998-12-10 Frank Ch. Eigler <fche@cygnus.com>
894
895 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
896 (tx3904sio_tickle): fflush after a stdout character output.
897
8981998-12-03 Frank Ch. Eigler <fche@cygnus.com>
899
900 * interp.c (sim_close): Uninstall modules.
901
902Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
903
904 * sim-main.h, interp.c (sim_monitor): Change to global
905 function.
906
907Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
908
909 * configure.in (vr4100): Only include vr4100 instructions in
910 simulator.
911 * configure: Re-generate.
912 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
913
914Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
915
916 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
917 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
918 true alternative.
919
920 * configure.in (sim_default_gen, sim_use_gen): Replace with
921 sim_gen.
922 (--enable-sim-igen): Delete config option. Always using IGEN.
923 * configure: Re-generate.
924
925 * Makefile.in (gencode): Kill, kill, kill.
926 * gencode.c: Ditto.
927
928Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
929
930 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
931 bit mips16 igen simulator.
932 * configure: Re-generate.
933
934 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
935 as part of vr4100 ISA.
936 * vr.igen: Mark all instructions as 64 bit only.
937
938Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
939
940 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
941 Pacify GCC.
942
943Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
944
945 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
946 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
947 * configure: Re-generate.
948
949 * m16.igen (BREAK): Define breakpoint instruction.
950 (JALX32): Mark instruction as mips16 and not r3900.
951 * mips.igen (C.cond.fmt): Fix typo in instruction format.
952
953 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
954
955Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
956
957 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
958 insn as a debug breakpoint.
959
960 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
961 pending.slot_size.
962 (PENDING_SCHED): Clean up trace statement.
963 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
964 (PENDING_FILL): Delay write by only one cycle.
965 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
966
967 * sim-main.c (pending_tick): Clean up trace statements. Add trace
968 of pending writes.
969 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
970 32 & 64.
971 (pending_tick): Move incrementing of index to FOR statement.
972 (pending_tick): Only update PENDING_OUT after a write has occured.
973
974 * configure.in: Add explicit mips-lsi-* target. Use gencode to
975 build simulator.
976 * configure: Re-generate.
977
978 * interp.c (sim_engine_run OLD): Delete explicit call to
979 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
980
981Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
982
983 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
984 interrupt level number to match changed SignalExceptionInterrupt
985 macro.
986
987Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
988
989 * interp.c: #include "itable.h" if WITH_IGEN.
990 (get_insn_name): New function.
991 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
992 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
993
994Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
995
996 * configure: Rebuilt to inhale new common/aclocal.m4.
997
998Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
999
1000 * dv-tx3904sio.c: Include sim-assert.h.
1001
1002Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1003
1004 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1005 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1006 Reorganize target-specific sim-hardware checks.
1007 * configure: rebuilt.
1008 * interp.c (sim_open): For tx39 target boards, set
1009 OPERATING_ENVIRONMENT, add tx3904sio devices.
1010 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1011 ROM executables. Install dv-sockser into sim-modules list.
1012
1013 * dv-tx3904irc.c: Compiler warning clean-up.
1014 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1015 frequent hw-trace messages.
1016
1017Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1018
1019 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1020
1021Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1022
1023 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1024
1025 * vr.igen: New file.
1026 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1027 * mips.igen: Define vr4100 model. Include vr.igen.
1028Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1029
1030 * mips.igen (check_mf_hilo): Correct check.
1031
1032Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1033
1034 * sim-main.h (interrupt_event): Add prototype.
1035
1036 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1037 register_ptr, register_value.
1038 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1039
1040 * sim-main.h (tracefh): Make extern.
1041
1042Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1043
1044 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1045 Reduce unnecessarily high timer event frequency.
1046 * dv-tx3904cpu.c: Ditto for interrupt event.
1047
1048Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1049
1050 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1051 to allay warnings.
1052 (interrupt_event): Made non-static.
1053
1054 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1055 interchange of configuration values for external vs. internal
1056 clock dividers.
1057
1058Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1059
1060 * mips.igen (BREAK): Moved code to here for
1061 simulator-reserved break instructions.
1062 * gencode.c (build_instruction): Ditto.
1063 * interp.c (signal_exception): Code moved from here. Non-
1064 reserved instructions now use exception vector, rather
1065 than halting sim.
1066 * sim-main.h: Moved magic constants to here.
1067
1068Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1069
1070 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1071 register upon non-zero interrupt event level, clear upon zero
1072 event value.
1073 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1074 by passing zero event value.
1075 (*_io_{read,write}_buffer): Endianness fixes.
1076 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1077 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1078
1079 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1080 serial I/O and timer module at base address 0xFFFF0000.
1081
1082Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1083
1084 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1085 and BigEndianCPU.
1086
1087Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1088
1089 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1090 parts.
1091 * configure: Update.
1092
1093Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1094
1095 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1096 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1097 * configure.in: Include tx3904tmr in hw_device list.
1098 * configure: Rebuilt.
1099 * interp.c (sim_open): Instantiate three timer instances.
1100 Fix address typo of tx3904irc instance.
1101
1102Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1103
1104 * interp.c (signal_exception): SystemCall exception now uses
1105 the exception vector.
1106
1107Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1108
1109 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1110 to allay warnings.
1111
1112Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1113
1114 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1115
1116Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1117
1118 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1119
1120 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1121 sim-main.h. Declare a struct hw_descriptor instead of struct
1122 hw_device_descriptor.
1123
1124Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1125
1126 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1127 right bits and then re-align left hand bytes to correct byte
1128 lanes. Fix incorrect computation in do_store_left when loading
1129 bytes from second word.
1130
1131Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1132
1133 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1134 * interp.c (sim_open): Only create a device tree when HW is
1135 enabled.
1136
1137 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1138 * interp.c (signal_exception): Ditto.
1139
1140Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1141
1142 * gencode.c: Mark BEGEZALL as LIKELY.
1143
1144Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1145
1146 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1147 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1148
1149Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1150
1151 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1152 modules. Recognize TX39 target with "mips*tx39" pattern.
1153 * configure: Rebuilt.
1154 * sim-main.h (*): Added many macros defining bits in
1155 TX39 control registers.
1156 (SignalInterrupt): Send actual PC instead of NULL.
1157 (SignalNMIReset): New exception type.
1158 * interp.c (board): New variable for future use to identify
1159 a particular board being simulated.
1160 (mips_option_handler,mips_options): Added "--board" option.
1161 (interrupt_event): Send actual PC.
1162 (sim_open): Make memory layout conditional on board setting.
1163 (signal_exception): Initial implementation of hardware interrupt
1164 handling. Accept another break instruction variant for simulator
1165 exit.
1166 (decode_coproc): Implement RFE instruction for TX39.
1167 (mips.igen): Decode RFE instruction as such.
1168 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1169 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1170 bbegin to implement memory map.
1171 * dv-tx3904cpu.c: New file.
1172 * dv-tx3904irc.c: New file.
1173
1174Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1175
1176 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1177
1178Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1179
1180 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1181 with calls to check_div_hilo.
1182
1183Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1184
1185 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1186 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1187 Add special r3900 version of do_mult_hilo.
1188 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1189 with calls to check_mult_hilo.
1190 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1191 with calls to check_div_hilo.
1192
1193Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1194
1195 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1196 Document a replacement.
1197
1198Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1199
1200 * interp.c (sim_monitor): Make mon_printf work.
1201
1202Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1203
1204 * sim-main.h (INSN_NAME): New arg `cpu'.
1205
1206Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1207
1208 * configure: Regenerated to track ../common/aclocal.m4 changes.
1209
1210Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1211
1212 * configure: Regenerated to track ../common/aclocal.m4 changes.
1213 * config.in: Ditto.
1214
1215Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1216
1217 * acconfig.h: New file.
1218 * configure.in: Reverted change of Apr 24; use sinclude again.
1219
1220Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1221
1222 * configure: Regenerated to track ../common/aclocal.m4 changes.
1223 * config.in: Ditto.
1224
1225Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1226
1227 * configure.in: Don't call sinclude.
1228
1229Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1230
1231 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1232
1233Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1234
1235 * mips.igen (ERET): Implement.
1236
1237 * interp.c (decode_coproc): Return sign-extended EPC.
1238
1239 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1240
1241 * interp.c (signal_exception): Do not ignore Trap.
1242 (signal_exception): On TRAP, restart at exception address.
1243 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1244 (signal_exception): Update.
1245 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1246 so that TRAP instructions are caught.
1247
1248Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1249
1250 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1251 contains HI/LO access history.
1252 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1253 (HIACCESS, LOACCESS): Delete, replace with
1254 (HIHISTORY, LOHISTORY): New macros.
1255 (CHECKHILO): Delete all, moved to mips.igen
1256
1257 * gencode.c (build_instruction): Do not generate checks for
1258 correct HI/LO register usage.
1259
1260 * interp.c (old_engine_run): Delete checks for correct HI/LO
1261 register usage.
1262
1263 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1264 check_mf_cycles): New functions.
1265 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1266 do_divu, domultx, do_mult, do_multu): Use.
1267
1268 * tx.igen ("madd", "maddu"): Use.
1269
1270Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1271
1272 * mips.igen (DSRAV): Use function do_dsrav.
1273 (SRAV): Use new function do_srav.
1274
1275 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1276 (B): Sign extend 11 bit immediate.
1277 (EXT-B*): Shift 16 bit immediate left by 1.
1278 (ADDIU*): Don't sign extend immediate value.
1279
1280Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1281
1282 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1283
1284 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1285 functions.
1286
1287 * mips.igen (delayslot32, nullify_next_insn): New functions.
1288 (m16.igen): Always include.
1289 (do_*): Add more tracing.
1290
1291 * m16.igen (delayslot16): Add NIA argument, could be called by a
1292 32 bit MIPS16 instruction.
1293
1294 * interp.c (ifetch16): Move function from here.
1295 * sim-main.c (ifetch16): To here.
1296
1297 * sim-main.c (ifetch16, ifetch32): Update to match current
1298 implementations of LH, LW.
1299 (signal_exception): Don't print out incorrect hex value of illegal
1300 instruction.
1301
1302Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1303
1304 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1305 instruction.
1306
1307 * m16.igen: Implement MIPS16 instructions.
1308
1309 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1310 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1311 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1312 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1313 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1314 bodies of corresponding code from 32 bit insn to these. Also used
1315 by MIPS16 versions of functions.
1316
1317 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1318 (IMEM16): Drop NR argument from macro.
1319
1320Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1321
1322 * Makefile.in (SIM_OBJS): Add sim-main.o.
1323
1324 * sim-main.h (address_translation, load_memory, store_memory,
1325 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1326 as INLINE_SIM_MAIN.
1327 (pr_addr, pr_uword64): Declare.
1328 (sim-main.c): Include when H_REVEALS_MODULE_P.
1329
1330 * interp.c (address_translation, load_memory, store_memory,
1331 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1332 from here.
1333 * sim-main.c: To here. Fix compilation problems.
1334
1335 * configure.in: Enable inlining.
1336 * configure: Re-config.
1337
1338Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1339
1340 * configure: Regenerated to track ../common/aclocal.m4 changes.
1341
1342Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1343
1344 * mips.igen: Include tx.igen.
1345 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1346 * tx.igen: New file, contains MADD and MADDU.
1347
1348 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1349 the hardwired constant `7'.
1350 (store_memory): Ditto.
1351 (LOADDRMASK): Move definition to sim-main.h.
1352
1353 mips.igen (MTC0): Enable for r3900.
1354 (ADDU): Add trace.
1355
1356 mips.igen (do_load_byte): Delete.
1357 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1358 do_store_right): New functions.
1359 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1360
1361 configure.in: Let the tx39 use igen again.
1362 configure: Update.
1363
1364Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1365
1366 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1367 not an address sized quantity. Return zero for cache sizes.
1368
1369Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1370
1371 * mips.igen (r3900): r3900 does not support 64 bit integer
1372 operations.
1373
1374Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1375
1376 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1377 than igen one.
1378 * configure : Rebuild.
1379
1380Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1381
1382 * configure: Regenerated to track ../common/aclocal.m4 changes.
1383
1384Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1385
1386 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1387
1388Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1389
1390 * configure: Regenerated to track ../common/aclocal.m4 changes.
1391 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1392
1393Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1394
1395 * configure: Regenerated to track ../common/aclocal.m4 changes.
1396
1397Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1398
1399 * interp.c (Max, Min): Comment out functions. Not yet used.
1400
1401Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1402
1403 * configure: Regenerated to track ../common/aclocal.m4 changes.
1404
1405Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1406
1407 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1408 configurable settings for stand-alone simulator.
1409
1410 * configure.in: Added X11 search, just in case.
1411
1412 * configure: Regenerated.
1413
1414Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1415
1416 * interp.c (sim_write, sim_read, load_memory, store_memory):
1417 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1418
1419Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1420
1421 * sim-main.h (GETFCC): Return an unsigned value.
1422
1423Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1424
1425 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1426 (DADD): Result destination is RD not RT.
1427
1428Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1429
1430 * sim-main.h (HIACCESS, LOACCESS): Always define.
1431
1432 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1433
1434 * interp.c (sim_info): Delete.
1435
1436Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1437
1438 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1439 (mips_option_handler): New argument `cpu'.
1440 (sim_open): Update call to sim_add_option_table.
1441
1442Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1443
1444 * mips.igen (CxC1): Add tracing.
1445
1446Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1447
1448 * sim-main.h (Max, Min): Declare.
1449
1450 * interp.c (Max, Min): New functions.
1451
1452 * mips.igen (BC1): Add tracing.
1453
1454Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1455
1456 * interp.c Added memory map for stack in vr4100
1457
1458Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1459
1460 * interp.c (load_memory): Add missing "break"'s.
1461
1462Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1463
1464 * interp.c (sim_store_register, sim_fetch_register): Pass in
1465 length parameter. Return -1.
1466
1467Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1468
1469 * interp.c: Added hardware init hook, fixed warnings.
1470
1471Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1472
1473 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1474
1475Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1476
1477 * interp.c (ifetch16): New function.
1478
1479 * sim-main.h (IMEM32): Rename IMEM.
1480 (IMEM16_IMMED): Define.
1481 (IMEM16): Define.
1482 (DELAY_SLOT): Update.
1483
1484 * m16run.c (sim_engine_run): New file.
1485
1486 * m16.igen: All instructions except LB.
1487 (LB): Call do_load_byte.
1488 * mips.igen (do_load_byte): New function.
1489 (LB): Call do_load_byte.
1490
1491 * mips.igen: Move spec for insn bit size and high bit from here.
1492 * Makefile.in (tmp-igen, tmp-m16): To here.
1493
1494 * m16.dc: New file, decode mips16 instructions.
1495
1496 * Makefile.in (SIM_NO_ALL): Define.
1497 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1498
1499Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1500
1501 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1502 point unit to 32 bit registers.
1503 * configure: Re-generate.
1504
1505Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1506
1507 * configure.in (sim_use_gen): Make IGEN the default simulator
1508 generator for generic 32 and 64 bit mips targets.
1509 * configure: Re-generate.
1510
1511Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1512
1513 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1514 bitsize.
1515
1516 * interp.c (sim_fetch_register, sim_store_register): Read/write
1517 FGR from correct location.
1518 (sim_open): Set size of FGR's according to
1519 WITH_TARGET_FLOATING_POINT_BITSIZE.
1520
1521 * sim-main.h (FGR): Store floating point registers in a separate
1522 array.
1523
1524Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1525
1526 * configure: Regenerated to track ../common/aclocal.m4 changes.
1527
1528Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1529
1530 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1531
1532 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1533
1534 * interp.c (pending_tick): New function. Deliver pending writes.
1535
1536 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1537 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1538 it can handle mixed sized quantites and single bits.
1539
1540Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1541
1542 * interp.c (oengine.h): Do not include when building with IGEN.
1543 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1544 (sim_info): Ditto for PROCESSOR_64BIT.
1545 (sim_monitor): Replace ut_reg with unsigned_word.
1546 (*): Ditto for t_reg.
1547 (LOADDRMASK): Define.
1548 (sim_open): Remove defunct check that host FP is IEEE compliant,
1549 using software to emulate floating point.
1550 (value_fpr, ...): Always compile, was conditional on HASFPU.
1551
1552Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1553
1554 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1555 size.
1556
1557 * interp.c (SD, CPU): Define.
1558 (mips_option_handler): Set flags in each CPU.
1559 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1560 (sim_close): Do not clear STATE, deleted anyway.
1561 (sim_write, sim_read): Assume CPU zero's vm should be used for
1562 data transfers.
1563 (sim_create_inferior): Set the PC for all processors.
1564 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1565 argument.
1566 (mips16_entry): Pass correct nr of args to store_word, load_word.
1567 (ColdReset): Cold reset all cpu's.
1568 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1569 (sim_monitor, load_memory, store_memory, signal_exception): Use
1570 `CPU' instead of STATE_CPU.
1571
1572
1573 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1574 SD or CPU_.
1575
1576 * sim-main.h (signal_exception): Add sim_cpu arg.
1577 (SignalException*): Pass both SD and CPU to signal_exception.
1578 * interp.c (signal_exception): Update.
1579
1580 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1581 Ditto
1582 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1583 address_translation): Ditto
1584 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1585
1586Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1587
1588 * configure: Regenerated to track ../common/aclocal.m4 changes.
1589
1590Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1591
1592 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1593
1594 * mips.igen (model): Map processor names onto BFD name.
1595
1596 * sim-main.h (CPU_CIA): Delete.
1597 (SET_CIA, GET_CIA): Define
1598
1599Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1600
1601 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1602 regiser.
1603
1604 * configure.in (default_endian): Configure a big-endian simulator
1605 by default.
1606 * configure: Re-generate.
1607
1608Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1609
1610 * configure: Regenerated to track ../common/aclocal.m4 changes.
1611
1612Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1613
1614 * interp.c (sim_monitor): Handle Densan monitor outbyte
1615 and inbyte functions.
1616
16171997-12-29 Felix Lee <flee@cygnus.com>
1618
1619 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1620
1621Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1622
1623 * Makefile.in (tmp-igen): Arrange for $zero to always be
1624 reset to zero after every instruction.
1625
1626Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1627
1628 * configure: Regenerated to track ../common/aclocal.m4 changes.
1629 * config.in: Ditto.
1630
1631Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1632
1633 * mips.igen (MSUB): Fix to work like MADD.
1634 * gencode.c (MSUB): Similarly.
1635
1636Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1637
1638 * configure: Regenerated to track ../common/aclocal.m4 changes.
1639
1640Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1641
1642 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1643
1644Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1645
1646 * sim-main.h (sim-fpu.h): Include.
1647
1648 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1649 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1650 using host independant sim_fpu module.
1651
1652Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1653
1654 * interp.c (signal_exception): Report internal errors with SIGABRT
1655 not SIGQUIT.
1656
1657 * sim-main.h (C0_CONFIG): New register.
1658 (signal.h): No longer include.
1659
1660 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1661
1662Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1663
1664 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1665
1666Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1667
1668 * mips.igen: Tag vr5000 instructions.
1669 (ANDI): Was missing mipsIV model, fix assembler syntax.
1670 (do_c_cond_fmt): New function.
1671 (C.cond.fmt): Handle mips I-III which do not support CC field
1672 separatly.
1673 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1674 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1675 in IV3.2 spec.
1676 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1677 vr5000 which saves LO in a GPR separatly.
1678
1679 * configure.in (enable-sim-igen): For vr5000, select vr5000
1680 specific instructions.
1681 * configure: Re-generate.
1682
1683Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1684
1685 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1686
1687 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1688 fmt_uninterpreted_64 bit cases to switch. Convert to
1689 fmt_formatted,
1690
1691 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1692
1693 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1694 as specified in IV3.2 spec.
1695 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1696
1697Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1698
1699 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1700 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1701 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1702 PENDING_FILL versions of instructions. Simplify.
1703 (X): New function.
1704 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1705 instructions.
1706 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1707 a signed value.
1708 (MTHI, MFHI): Disable code checking HI-LO.
1709
1710 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1711 global.
1712 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1713
1714Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1715
1716 * gencode.c (build_mips16_operands): Replace IPC with cia.
1717
1718 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1719 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1720 IPC to `cia'.
1721 (UndefinedResult): Replace function with macro/function
1722 combination.
1723 (sim_engine_run): Don't save PC in IPC.
1724
1725 * sim-main.h (IPC): Delete.
1726
1727
1728 * interp.c (signal_exception, store_word, load_word,
1729 address_translation, load_memory, store_memory, cache_op,
1730 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1731 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1732 current instruction address - cia - argument.
1733 (sim_read, sim_write): Call address_translation directly.
1734 (sim_engine_run): Rename variable vaddr to cia.
1735 (signal_exception): Pass cia to sim_monitor
1736
1737 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1738 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1739 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1740
1741 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1742 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1743 SIM_ASSERT.
1744
1745 * interp.c (signal_exception): Pass restart address to
1746 sim_engine_restart.
1747
1748 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1749 idecode.o): Add dependency.
1750
1751 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1752 Delete definitions
1753 (DELAY_SLOT): Update NIA not PC with branch address.
1754 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1755
1756 * mips.igen: Use CIA not PC in branch calculations.
1757 (illegal): Call SignalException.
1758 (BEQ, ADDIU): Fix assembler.
1759
1760Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1761
1762 * m16.igen (JALX): Was missing.
1763
1764 * configure.in (enable-sim-igen): New configuration option.
1765 * configure: Re-generate.
1766
1767 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1768
1769 * interp.c (load_memory, store_memory): Delete parameter RAW.
1770 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1771 bypassing {load,store}_memory.
1772
1773 * sim-main.h (ByteSwapMem): Delete definition.
1774
1775 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1776
1777 * interp.c (sim_do_command, sim_commands): Delete mips specific
1778 commands. Handled by module sim-options.
1779
1780 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1781 (WITH_MODULO_MEMORY): Define.
1782
1783 * interp.c (sim_info): Delete code printing memory size.
1784
1785 * interp.c (mips_size): Nee sim_size, delete function.
1786 (power2): Delete.
1787 (monitor, monitor_base, monitor_size): Delete global variables.
1788 (sim_open, sim_close): Delete code creating monitor and other
1789 memory regions. Use sim-memopts module, via sim_do_commandf, to
1790 manage memory regions.
1791 (load_memory, store_memory): Use sim-core for memory model.
1792
1793 * interp.c (address_translation): Delete all memory map code
1794 except line forcing 32 bit addresses.
1795
1796Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1797
1798 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1799 trace options.
1800
1801 * interp.c (logfh, logfile): Delete globals.
1802 (sim_open, sim_close): Delete code opening & closing log file.
1803 (mips_option_handler): Delete -l and -n options.
1804 (OPTION mips_options): Ditto.
1805
1806 * interp.c (OPTION mips_options): Rename option trace to dinero.
1807 (mips_option_handler): Update.
1808
1809Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1810
1811 * interp.c (fetch_str): New function.
1812 (sim_monitor): Rewrite using sim_read & sim_write.
1813 (sim_open): Check magic number.
1814 (sim_open): Write monitor vectors into memory using sim_write.
1815 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1816 (sim_read, sim_write): Simplify - transfer data one byte at a
1817 time.
1818 (load_memory, store_memory): Clarify meaning of parameter RAW.
1819
1820 * sim-main.h (isHOST): Defete definition.
1821 (isTARGET): Mark as depreciated.
1822 (address_translation): Delete parameter HOST.
1823
1824 * interp.c (address_translation): Delete parameter HOST.
1825
1826Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1827
1828 * mips.igen:
1829
1830 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1831 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1832
1833Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1834
1835 * mips.igen: Add model filter field to records.
1836
1837Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1838
1839 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1840
1841 interp.c (sim_engine_run): Do not compile function sim_engine_run
1842 when WITH_IGEN == 1.
1843
1844 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1845 target architecture.
1846
1847 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1848 igen. Replace with configuration variables sim_igen_flags /
1849 sim_m16_flags.
1850
1851 * m16.igen: New file. Copy mips16 insns here.
1852 * mips.igen: From here.
1853
1854Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1855
1856 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1857 to top.
1858 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1859
1860Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1861
1862 * gencode.c (build_instruction): Follow sim_write's lead in using
1863 BigEndianMem instead of !ByteSwapMem.
1864
1865Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1866
1867 * configure.in (sim_gen): Dependent on target, select type of
1868 generator. Always select old style generator.
1869
1870 configure: Re-generate.
1871
1872 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1873 targets.
1874 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1875 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1876 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1877 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1878 SIM_@sim_gen@_*, set by autoconf.
1879
1880Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1881
1882 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1883
1884 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1885 CURRENT_FLOATING_POINT instead.
1886
1887 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1888 (address_translation): Raise exception InstructionFetch when
1889 translation fails and isINSTRUCTION.
1890
1891 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1892 sim_engine_run): Change type of of vaddr and paddr to
1893 address_word.
1894 (address_translation, prefetch, load_memory, store_memory,
1895 cache_op): Change type of vAddr and pAddr to address_word.
1896
1897 * gencode.c (build_instruction): Change type of vaddr and paddr to
1898 address_word.
1899
1900Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1901
1902 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1903 macro to obtain result of ALU op.
1904
1905Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1906
1907 * interp.c (sim_info): Call profile_print.
1908
1909Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1910
1911 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1912
1913 * sim-main.h (WITH_PROFILE): Do not define, defined in
1914 common/sim-config.h. Use sim-profile module.
1915 (simPROFILE): Delete defintion.
1916
1917 * interp.c (PROFILE): Delete definition.
1918 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1919 (sim_close): Delete code writing profile histogram.
1920 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1921 Delete.
1922 (sim_engine_run): Delete code profiling the PC.
1923
1924Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1925
1926 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1927
1928 * interp.c (sim_monitor): Make register pointers of type
1929 unsigned_word*.
1930
1931 * sim-main.h: Make registers of type unsigned_word not
1932 signed_word.
1933
1934Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1935
1936 * interp.c (sync_operation): Rename from SyncOperation, make
1937 global, add SD argument.
1938 (prefetch): Rename from Prefetch, make global, add SD argument.
1939 (decode_coproc): Make global.
1940
1941 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1942
1943 * gencode.c (build_instruction): Generate DecodeCoproc not
1944 decode_coproc calls.
1945
1946 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1947 (SizeFGR): Move to sim-main.h
1948 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1949 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1950 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1951 sim-main.h.
1952 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1953 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1954 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1955 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1956 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1957 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1958
1959 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1960 exception.
1961 (sim-alu.h): Include.
1962 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1963 (sim_cia): Typedef to instruction_address.
1964
1965Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1966
1967 * Makefile.in (interp.o): Rename generated file engine.c to
1968 oengine.c.
1969
1970 * interp.c: Update.
1971
1972Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1973
1974 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1975
1976Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1977
1978 * gencode.c (build_instruction): For "FPSQRT", output correct
1979 number of arguments to Recip.
1980
1981Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1982
1983 * Makefile.in (interp.o): Depends on sim-main.h
1984
1985 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1986
1987 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1988 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1989 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1990 STATE, DSSTATE): Define
1991 (GPR, FGRIDX, ..): Define.
1992
1993 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1994 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1995 (GPR, FGRIDX, ...): Delete macros.
1996
1997 * interp.c: Update names to match defines from sim-main.h
1998
1999Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2000
2001 * interp.c (sim_monitor): Add SD argument.
2002 (sim_warning): Delete. Replace calls with calls to
2003 sim_io_eprintf.
2004 (sim_error): Delete. Replace calls with sim_io_error.
2005 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2006 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2007 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2008 argument.
2009 (mips_size): Rename from sim_size. Add SD argument.
2010
2011 * interp.c (simulator): Delete global variable.
2012 (callback): Delete global variable.
2013 (mips_option_handler, sim_open, sim_write, sim_read,
2014 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2015 sim_size,sim_monitor): Use sim_io_* not callback->*.
2016 (sim_open): ZALLOC simulator struct.
2017 (PROFILE): Do not define.
2018
2019Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2020
2021 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2022 support.h with corresponding code.
2023
2024 * sim-main.h (word64, uword64), support.h: Move definition to
2025 sim-main.h.
2026 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2027
2028 * support.h: Delete
2029 * Makefile.in: Update dependencies
2030 * interp.c: Do not include.
2031
2032Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2033
2034 * interp.c (address_translation, load_memory, store_memory,
2035 cache_op): Rename to from AddressTranslation et.al., make global,
2036 add SD argument
2037
2038 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2039 CacheOp): Define.
2040
2041 * interp.c (SignalException): Rename to signal_exception, make
2042 global.
2043
2044 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2045
2046 * sim-main.h (SignalException, SignalExceptionInterrupt,
2047 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2048 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2049 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2050 Define.
2051
2052 * interp.c, support.h: Use.
2053
2054Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2055
2056 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2057 to value_fpr / store_fpr. Add SD argument.
2058 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2059 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2060
2061 * sim-main.h (ValueFPR, StoreFPR): Define.
2062
2063Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2064
2065 * interp.c (sim_engine_run): Check consistency between configure
2066 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2067 and HASFPU.
2068
2069 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2070 (mips_fpu): Configure WITH_FLOATING_POINT.
2071 (mips_endian): Configure WITH_TARGET_ENDIAN.
2072 * configure: Update.
2073
2074Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2075
2076 * configure: Regenerated to track ../common/aclocal.m4 changes.
2077
2078Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2079
2080 * configure: Regenerated.
2081
2082Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2083
2084 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2085
2086Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2087
2088 * gencode.c (print_igen_insn_models): Assume certain architectures
2089 include all mips* instructions.
2090 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2091 instruction.
2092
2093 * Makefile.in (tmp.igen): Add target. Generate igen input from
2094 gencode file.
2095
2096 * gencode.c (FEATURE_IGEN): Define.
2097 (main): Add --igen option. Generate output in igen format.
2098 (process_instructions): Format output according to igen option.
2099 (print_igen_insn_format): New function.
2100 (print_igen_insn_models): New function.
2101 (process_instructions): Only issue warnings and ignore
2102 instructions when no FEATURE_IGEN.
2103
2104Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2105
2106 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2107 MIPS targets.
2108
2109Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2110
2111 * configure: Regenerated to track ../common/aclocal.m4 changes.
2112
2113Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2114
2115 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2116 SIM_RESERVED_BITS): Delete, moved to common.
2117 (SIM_EXTRA_CFLAGS): Update.
2118
2119Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2120
2121 * configure.in: Configure non-strict memory alignment.
2122 * configure: Regenerated to track ../common/aclocal.m4 changes.
2123
2124Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2125
2126 * configure: Regenerated to track ../common/aclocal.m4 changes.
2127
2128Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2129
2130 * gencode.c (SDBBP,DERET): Added (3900) insns.
2131 (RFE): Turn on for 3900.
2132 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2133 (dsstate): Made global.
2134 (SUBTARGET_R3900): Added.
2135 (CANCELDELAYSLOT): New.
2136 (SignalException): Ignore SystemCall rather than ignore and
2137 terminate. Add DebugBreakPoint handling.
2138 (decode_coproc): New insns RFE, DERET; and new registers Debug
2139 and DEPC protected by SUBTARGET_R3900.
2140 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2141 bits explicitly.
2142 * Makefile.in,configure.in: Add mips subtarget option.
2143 * configure: Update.
2144
2145Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2146
2147 * gencode.c: Add r3900 (tx39).
2148
2149
2150Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2151
2152 * gencode.c (build_instruction): Don't need to subtract 4 for
2153 JALR, just 2.
2154
2155Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2156
2157 * interp.c: Correct some HASFPU problems.
2158
2159Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2160
2161 * configure: Regenerated to track ../common/aclocal.m4 changes.
2162
2163Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2164
2165 * interp.c (mips_options): Fix samples option short form, should
2166 be `x'.
2167
2168Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2169
2170 * interp.c (sim_info): Enable info code. Was just returning.
2171
2172Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2173
2174 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2175 MFC0.
2176
2177Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2178
2179 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2180 constants.
2181 (build_instruction): Ditto for LL.
2182
2183Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2184
2185 * configure: Regenerated to track ../common/aclocal.m4 changes.
2186
2187Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2188
2189 * configure: Regenerated to track ../common/aclocal.m4 changes.
2190 * config.in: Ditto.
2191
2192Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2193
2194 * interp.c (sim_open): Add call to sim_analyze_program, update
2195 call to sim_config.
2196
2197Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2198
2199 * interp.c (sim_kill): Delete.
2200 (sim_create_inferior): Add ABFD argument. Set PC from same.
2201 (sim_load): Move code initializing trap handlers from here.
2202 (sim_open): To here.
2203 (sim_load): Delete, use sim-hload.c.
2204
2205 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2206
2207Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2208
2209 * configure: Regenerated to track ../common/aclocal.m4 changes.
2210 * config.in: Ditto.
2211
2212Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2213
2214 * interp.c (sim_open): Add ABFD argument.
2215 (sim_load): Move call to sim_config from here.
2216 (sim_open): To here. Check return status.
2217
2218Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2219
2220 * gencode.c (build_instruction): Two arg MADD should
2221 not assign result to $0.
2222
2223Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2224
2225 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2226 * sim/mips/configure.in: Regenerate.
2227
2228Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2229
2230 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2231 signed8, unsigned8 et.al. types.
2232
2233 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2234 hosts when selecting subreg.
2235
2236Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2237
2238 * interp.c (sim_engine_run): Reset the ZERO register to zero
2239 regardless of FEATURE_WARN_ZERO.
2240 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2241
2242Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2243
2244 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2245 (SignalException): For BreakPoints ignore any mode bits and just
2246 save the PC.
2247 (SignalException): Always set the CAUSE register.
2248
2249Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2250
2251 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2252 exception has been taken.
2253
2254 * interp.c: Implement the ERET and mt/f sr instructions.
2255
2256Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2257
2258 * interp.c (SignalException): Don't bother restarting an
2259 interrupt.
2260
2261Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2262
2263 * interp.c (SignalException): Really take an interrupt.
2264 (interrupt_event): Only deliver interrupts when enabled.
2265
2266Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2267
2268 * interp.c (sim_info): Only print info when verbose.
2269 (sim_info) Use sim_io_printf for output.
2270
2271Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2272
2273 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2274 mips architectures.
2275
2276Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2277
2278 * interp.c (sim_do_command): Check for common commands if a
2279 simulator specific command fails.
2280
2281Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2282
2283 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2284 and simBE when DEBUG is defined.
2285
2286Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2287
2288 * interp.c (interrupt_event): New function. Pass exception event
2289 onto exception handler.
2290
2291 * configure.in: Check for stdlib.h.
2292 * configure: Regenerate.
2293
2294 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2295 variable declaration.
2296 (build_instruction): Initialize memval1.
2297 (build_instruction): Add UNUSED attribute to byte, bigend,
2298 reverse.
2299 (build_operands): Ditto.
2300
2301 * interp.c: Fix GCC warnings.
2302 (sim_get_quit_code): Delete.
2303
2304 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2305 * Makefile.in: Ditto.
2306 * configure: Re-generate.
2307
2308 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2309
2310Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2311
2312 * interp.c (mips_option_handler): New function parse argumes using
2313 sim-options.
2314 (myname): Replace with STATE_MY_NAME.
2315 (sim_open): Delete check for host endianness - performed by
2316 sim_config.
2317 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2318 (sim_open): Move much of the initialization from here.
2319 (sim_load): To here. After the image has been loaded and
2320 endianness set.
2321 (sim_open): Move ColdReset from here.
2322 (sim_create_inferior): To here.
2323 (sim_open): Make FP check less dependant on host endianness.
2324
2325 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2326 run.
2327 * interp.c (sim_set_callbacks): Delete.
2328
2329 * interp.c (membank, membank_base, membank_size): Replace with
2330 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2331 (sim_open): Remove call to callback->init. gdb/run do this.
2332
2333 * interp.c: Update
2334
2335 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2336
2337 * interp.c (big_endian_p): Delete, replaced by
2338 current_target_byte_order.
2339
2340Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2341
2342 * interp.c (host_read_long, host_read_word, host_swap_word,
2343 host_swap_long): Delete. Using common sim-endian.
2344 (sim_fetch_register, sim_store_register): Use H2T.
2345 (pipeline_ticks): Delete. Handled by sim-events.
2346 (sim_info): Update.
2347 (sim_engine_run): Update.
2348
2349Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2350
2351 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2352 reason from here.
2353 (SignalException): To here. Signal using sim_engine_halt.
2354 (sim_stop_reason): Delete, moved to common.
2355
2356Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2357
2358 * interp.c (sim_open): Add callback argument.
2359 (sim_set_callbacks): Delete SIM_DESC argument.
2360 (sim_size): Ditto.
2361
2362Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2363
2364 * Makefile.in (SIM_OBJS): Add common modules.
2365
2366 * interp.c (sim_set_callbacks): Also set SD callback.
2367 (set_endianness, xfer_*, swap_*): Delete.
2368 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2369 Change to functions using sim-endian macros.
2370 (control_c, sim_stop): Delete, use common version.
2371 (simulate): Convert into.
2372 (sim_engine_run): This function.
2373 (sim_resume): Delete.
2374
2375 * interp.c (simulation): New variable - the simulator object.
2376 (sim_kind): Delete global - merged into simulation.
2377 (sim_load): Cleanup. Move PC assignment from here.
2378 (sim_create_inferior): To here.
2379
2380 * sim-main.h: New file.
2381 * interp.c (sim-main.h): Include.
2382
2383Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2384
2385 * configure: Regenerated to track ../common/aclocal.m4 changes.
2386
2387Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2388
2389 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2390
2391Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2392
2393 * gencode.c (build_instruction): DIV instructions: check
2394 for division by zero and integer overflow before using
2395 host's division operation.
2396
2397Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2398
2399 * Makefile.in (SIM_OBJS): Add sim-load.o.
2400 * interp.c: #include bfd.h.
2401 (target_byte_order): Delete.
2402 (sim_kind, myname, big_endian_p): New static locals.
2403 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2404 after argument parsing. Recognize -E arg, set endianness accordingly.
2405 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2406 load file into simulator. Set PC from bfd.
2407 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2408 (set_endianness): Use big_endian_p instead of target_byte_order.
2409
2410Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2411
2412 * interp.c (sim_size): Delete prototype - conflicts with
2413 definition in remote-sim.h. Correct definition.
2414
2415Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2416
2417 * configure: Regenerated to track ../common/aclocal.m4 changes.
2418 * config.in: Ditto.
2419
2420Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2421
2422 * interp.c (sim_open): New arg `kind'.
2423
2424 * configure: Regenerated to track ../common/aclocal.m4 changes.
2425
2426Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2427
2428 * configure: Regenerated to track ../common/aclocal.m4 changes.
2429
2430Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2431
2432 * interp.c (sim_open): Set optind to 0 before calling getopt.
2433
2434Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2435
2436 * configure: Regenerated to track ../common/aclocal.m4 changes.
2437
2438Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2439
2440 * interp.c : Replace uses of pr_addr with pr_uword64
2441 where the bit length is always 64 independent of SIM_ADDR.
2442 (pr_uword64) : added.
2443
2444Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2445
2446 * configure: Re-generate.
2447
2448Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2449
2450 * configure: Regenerate to track ../common/aclocal.m4 changes.
2451
2452Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2453
2454 * interp.c (sim_open): New SIM_DESC result. Argument is now
2455 in argv form.
2456 (other sim_*): New SIM_DESC argument.
2457
2458Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2459
2460 * interp.c: Fix printing of addresses for non-64-bit targets.
2461 (pr_addr): Add function to print address based on size.
2462
2463Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2464
2465 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2466
2467Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2468
2469 * gencode.c (build_mips16_operands): Correct computation of base
2470 address for extended PC relative instruction.
2471
2472Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2473
2474 * interp.c (mips16_entry): Add support for floating point cases.
2475 (SignalException): Pass floating point cases to mips16_entry.
2476 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2477 registers.
2478 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2479 or fmt_word.
2480 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2481 and then set the state to fmt_uninterpreted.
2482 (COP_SW): Temporarily set the state to fmt_word while calling
2483 ValueFPR.
2484
2485Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2486
2487 * gencode.c (build_instruction): The high order may be set in the
2488 comparison flags at any ISA level, not just ISA 4.
2489
2490Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2491
2492 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2493 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2494 * configure.in: sinclude ../common/aclocal.m4.
2495 * configure: Regenerated.
2496
2497Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2498
2499 * configure: Rebuild after change to aclocal.m4.
2500
2501Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2502
2503 * configure configure.in Makefile.in: Update to new configure
2504 scheme which is more compatible with WinGDB builds.
2505 * configure.in: Improve comment on how to run autoconf.
2506 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2507 * Makefile.in: Use autoconf substitution to install common
2508 makefile fragment.
2509
2510Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2511
2512 * gencode.c (build_instruction): Use BigEndianCPU instead of
2513 ByteSwapMem.
2514
2515Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2516
2517 * interp.c (sim_monitor): Make output to stdout visible in
2518 wingdb's I/O log window.
2519
2520Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2521
2522 * support.h: Undo previous change to SIGTRAP
2523 and SIGQUIT values.
2524
2525Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2526
2527 * interp.c (store_word, load_word): New static functions.
2528 (mips16_entry): New static function.
2529 (SignalException): Look for mips16 entry and exit instructions.
2530 (simulate): Use the correct index when setting fpr_state after
2531 doing a pending move.
2532
2533Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2534
2535 * interp.c: Fix byte-swapping code throughout to work on
2536 both little- and big-endian hosts.
2537
2538Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2539
2540 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2541 with gdb/config/i386/xm-windows.h.
2542
2543Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2544
2545 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2546 that messes up arithmetic shifts.
2547
2548Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2549
2550 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2551 SIGTRAP and SIGQUIT for _WIN32.
2552
2553Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2554
2555 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2556 force a 64 bit multiplication.
2557 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2558 destination register is 0, since that is the default mips16 nop
2559 instruction.
2560
2561Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2562
2563 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2564 (build_endian_shift): Don't check proc64.
2565 (build_instruction): Always set memval to uword64. Cast op2 to
2566 uword64 when shifting it left in memory instructions. Always use
2567 the same code for stores--don't special case proc64.
2568
2569 * gencode.c (build_mips16_operands): Fix base PC value for PC
2570 relative operands.
2571 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2572 jal instruction.
2573 * interp.c (simJALDELAYSLOT): Define.
2574 (JALDELAYSLOT): Define.
2575 (INDELAYSLOT, INJALDELAYSLOT): Define.
2576 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2577
2578Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2579
2580 * interp.c (sim_open): add flush_cache as a PMON routine
2581 (sim_monitor): handle flush_cache by ignoring it
2582
2583Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2584
2585 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2586 BigEndianMem.
2587 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2588 (BigEndianMem): Rename to ByteSwapMem and change sense.
2589 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2590 BigEndianMem references to !ByteSwapMem.
2591 (set_endianness): New function, with prototype.
2592 (sim_open): Call set_endianness.
2593 (sim_info): Use simBE instead of BigEndianMem.
2594 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2595 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2596 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2597 ifdefs, keeping the prototype declaration.
2598 (swap_word): Rewrite correctly.
2599 (ColdReset): Delete references to CONFIG. Delete endianness related
2600 code; moved to set_endianness.
2601
2602Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2603
2604 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2605 * interp.c (CHECKHILO): Define away.
2606 (simSIGINT): New macro.
2607 (membank_size): Increase from 1MB to 2MB.
2608 (control_c): New function.
2609 (sim_resume): Rename parameter signal to signal_number. Add local
2610 variable prev. Call signal before and after simulate.
2611 (sim_stop_reason): Add simSIGINT support.
2612 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2613 functions always.
2614 (sim_warning): Delete call to SignalException. Do call printf_filtered
2615 if logfh is NULL.
2616 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2617 a call to sim_warning.
2618
2619Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2620
2621 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2622 16 bit instructions.
2623
2624Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2625
2626 Add support for mips16 (16 bit MIPS implementation):
2627 * gencode.c (inst_type): Add mips16 instruction encoding types.
2628 (GETDATASIZEINSN): Define.
2629 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2630 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2631 mtlo.
2632 (MIPS16_DECODE): New table, for mips16 instructions.
2633 (bitmap_val): New static function.
2634 (struct mips16_op): Define.
2635 (mips16_op_table): New table, for mips16 operands.
2636 (build_mips16_operands): New static function.
2637 (process_instructions): If PC is odd, decode a mips16
2638 instruction. Break out instruction handling into new
2639 build_instruction function.
2640 (build_instruction): New static function, broken out of
2641 process_instructions. Check modifiers rather than flags for SHIFT
2642 bit count and m[ft]{hi,lo} direction.
2643 (usage): Pass program name to fprintf.
2644 (main): Remove unused variable this_option_optind. Change
2645 ``*loptarg++'' to ``loptarg++''.
2646 (my_strtoul): Parenthesize && within ||.
2647 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2648 (simulate): If PC is odd, fetch a 16 bit instruction, and
2649 increment PC by 2 rather than 4.
2650 * configure.in: Add case for mips16*-*-*.
2651 * configure: Rebuild.
2652
2653Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2654
2655 * interp.c: Allow -t to enable tracing in standalone simulator.
2656 Fix garbage output in trace file and error messages.
2657
2658Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2659
2660 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2661 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2662 * configure.in: Simplify using macros in ../common/aclocal.m4.
2663 * configure: Regenerated.
2664 * tconfig.in: New file.
2665
2666Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2667
2668 * interp.c: Fix bugs in 64-bit port.
2669 Use ansi function declarations for msvc compiler.
2670 Initialize and test file pointer in trace code.
2671 Prevent duplicate definition of LAST_EMED_REGNUM.
2672
2673Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2674
2675 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2676
2677Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2678
2679 * interp.c (SignalException): Check for explicit terminating
2680 breakpoint value.
2681 * gencode.c: Pass instruction value through SignalException()
2682 calls for Trap, Breakpoint and Syscall.
2683
2684Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2685
2686 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2687 only used on those hosts that provide it.
2688 * configure.in: Add sqrt() to list of functions to be checked for.
2689 * config.in: Re-generated.
2690 * configure: Re-generated.
2691
2692Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2693
2694 * gencode.c (process_instructions): Call build_endian_shift when
2695 expanding STORE RIGHT, to fix swr.
2696 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2697 clear the high bits.
2698 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2699 Fix float to int conversions to produce signed values.
2700
2701Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2702
2703 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2704 (process_instructions): Correct handling of nor instruction.
2705 Correct shift count for 32 bit shift instructions. Correct sign
2706 extension for arithmetic shifts to not shift the number of bits in
2707 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2708 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2709 Fix madd.
2710 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2711 It's OK to have a mult follow a mult. What's not OK is to have a
2712 mult follow an mfhi.
2713 (Convert): Comment out incorrect rounding code.
2714
2715Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2716
2717 * interp.c (sim_monitor): Improved monitor printf
2718 simulation. Tidied up simulator warnings, and added "--log" option
2719 for directing warning message output.
2720 * gencode.c: Use sim_warning() rather than WARNING macro.
2721
2722Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2723
2724 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2725 getopt1.o, rather than on gencode.c. Link objects together.
2726 Don't link against -liberty.
2727 (gencode.o, getopt.o, getopt1.o): New targets.
2728 * gencode.c: Include <ctype.h> and "ansidecl.h".
2729 (AND): Undefine after including "ansidecl.h".
2730 (ULONG_MAX): Define if not defined.
2731 (OP_*): Don't define macros; now defined in opcode/mips.h.
2732 (main): Call my_strtoul rather than strtoul.
2733 (my_strtoul): New static function.
2734
2735Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2736
2737 * gencode.c (process_instructions): Generate word64 and uword64
2738 instead of `long long' and `unsigned long long' data types.
2739 * interp.c: #include sysdep.h to get signals, and define default
2740 for SIGBUS.
2741 * (Convert): Work around for Visual-C++ compiler bug with type
2742 conversion.
2743 * support.h: Make things compile under Visual-C++ by using
2744 __int64 instead of `long long'. Change many refs to long long
2745 into word64/uword64 typedefs.
2746
2747Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2748
2749 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2750 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2751 (docdir): Removed.
2752 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2753 (AC_PROG_INSTALL): Added.
2754 (AC_PROG_CC): Moved to before configure.host call.
2755 * configure: Rebuilt.
2756
2757Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2758
2759 * configure.in: Define @SIMCONF@ depending on mips target.
2760 * configure: Rebuild.
2761 * Makefile.in (run): Add @SIMCONF@ to control simulator
2762 construction.
2763 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2764 * interp.c: Remove some debugging, provide more detailed error
2765 messages, update memory accesses to use LOADDRMASK.
2766
2767Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2768
2769 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2770 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2771 stamp-h.
2772 * configure: Rebuild.
2773 * config.in: New file, generated by autoheader.
2774 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2775 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2776 HAVE_ANINT and HAVE_AINT, as appropriate.
2777 * Makefile.in (run): Use @LIBS@ rather than -lm.
2778 (interp.o): Depend upon config.h.
2779 (Makefile): Just rebuild Makefile.
2780 (clean): Remove stamp-h.
2781 (mostlyclean): Make the same as clean, not as distclean.
2782 (config.h, stamp-h): New targets.
2783
2784Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2785
2786 * interp.c (ColdReset): Fix boolean test. Make all simulator
2787 globals static.
2788
2789Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2790
2791 * interp.c (xfer_direct_word, xfer_direct_long,
2792 swap_direct_word, swap_direct_long, xfer_big_word,
2793 xfer_big_long, xfer_little_word, xfer_little_long,
2794 swap_word,swap_long): Added.
2795 * interp.c (ColdReset): Provide function indirection to
2796 host<->simulated_target transfer routines.
2797 * interp.c (sim_store_register, sim_fetch_register): Updated to
2798 make use of indirected transfer routines.
2799
2800Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2801
2802 * gencode.c (process_instructions): Ensure FP ABS instruction
2803 recognised.
2804 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2805 system call support.
2806
2807Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2808
2809 * interp.c (sim_do_command): Complain if callback structure not
2810 initialised.
2811
2812Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2813
2814 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2815 support for Sun hosts.
2816 * Makefile.in (gencode): Ensure the host compiler and libraries
2817 used for cross-hosted build.
2818
2819Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2820
2821 * interp.c, gencode.c: Some more (TODO) tidying.
2822
2823Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2824
2825 * gencode.c, interp.c: Replaced explicit long long references with
2826 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2827 * support.h (SET64LO, SET64HI): Macros added.
2828
2829Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2830
2831 * configure: Regenerate with autoconf 2.7.
2832
2833Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2834
2835 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2836 * support.h: Remove superfluous "1" from #if.
2837 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2838
2839Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2840
2841 * interp.c (StoreFPR): Control UndefinedResult() call on
2842 WARN_RESULT manifest.
2843
2844Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2845
2846 * gencode.c: Tidied instruction decoding, and added FP instruction
2847 support.
2848
2849 * interp.c: Added dineroIII, and BSD profiling support. Also
2850 run-time FP handling.
2851
2852Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2853
2854 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2855 gencode.c, interp.c, support.h: created.
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