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sim: mips: fix uninitialized register use
[deliverable/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
7b2298cb
MF		 12021-06-16 Mike Frysinger <vapier@gentoo.org>
2
3 * dv-tx3904irc.c (tx3904irc_io_write_buffer): Initialize
4 register_value to 0.
5
a8a3d907
MF		 62021-06-16 Mike Frysinger <vapier@gentoo.org>
7
8 * configure: Regenerate.
9
dae666c9
MF		 102021-06-16 Mike Frysinger <vapier@gentoo.org>
11
12 * interp.c (sim_open): Change %lx to %x and PRIx macros.
13
52d37d2c
MF		 142021-06-16 Mike Frysinger <vapier@gentoo.org>
15
16 * configure: Regenerate.
17 * config.in: Removed.
18
bcaa61f7
MF		 192021-06-15 Mike Frysinger <vapier@gentoo.org>
20
21 * config.in, configure: Regenerate.
22
ba307cdd
MF		 232021-06-12 Mike Frysinger <vapier@gentoo.org>
24
25 * configure.ac: Delete call to SIM_AC_OPTION_ALIGNMENT.
26
dba333c1
MF		 272021-06-12 Mike Frysinger <vapier@gentoo.org>
28
29 * aclocal.m4, config.in, configure: Regenerate.
30
b15c5d7a
MF		 312021-06-12 Mike Frysinger <vapier@gentoo.org>
32
33 * configure.ac: Delete call to AC_CHECK_FUNCS.
34 * config.in, configure: Regenerate.
35
a55b92be
MF		 362021-06-08 Mike Frysinger <vapier@gentoo.org>
37
38 * Makefile.in: Replace $(IGEN) with $(IGEN_RUN) and ../igen/igen
39 with $(IGEN).
40
8ea881d9
MF		 412021-05-29 Mike Frysinger <vapier@gentoo.org>
42
43 * interp.c [!HAVE_DV_SOCKSER] (sockser_addr): Define to NULL.
44
b312488f
FS		 452021-05-22 Faraz Shahbazker <fshahbazker@wavecomp.com>
46
168671c1
FS		 47 * interp.c (sim_open): Add shadow mappings from 32-bit
48 address space to 64-bit sign-extended address space.
49
502021-05-22 Faraz Shahbazker <fshahbazker@wavecomp.com>
51
b312488f
FS		 52 * interp.c (sim_create_inferior): Only truncate sign extension
53 bits for 32-bit target models.
54
f4fdd845
MF		 552021-05-17 Mike Frysinger <vapier@gentoo.org>
56
57 * sim-main.h (SIM_HAVE_COMMON_SIM_STATE): Delete.
58
8ea7241c
MF		 592021-05-17 Mike Frysinger <vapier@gentoo.org>
60
61 * interp.c (sim_open): Switch to sim_state_alloc_extra.
62 * micromips.igen: Change SD to mips_sim_state.
63 * micromipsrun.c (sim_engine_run): Likewise.
64 * sim-main.h (SIM_HAVE_COMMON_SIM_STATE): Define.
65 (watch_options_install): Delete.
66 (struct swatch): Delete.
67 (struct sim_state): Delete.
68 (struct mips_sim_state): New struct.
69 (MIPS_SIM_STATE): Define.
70
6df01ab8
MF		 712021-05-16 Mike Frysinger <vapier@gentoo.org>
72
73 * interp.c: Replace config.h include with defs.h.
74 * cp1.c, dsp.c, dv-tx3904cpu.c, dv-tx3904irc.c, dv-tx3904sio.c,
75 dv-tx3904tmr.c, m16run.c, mdmx.c, micromipsrun.c, sim-main.c:
76 Include defs.h.
77
79633c12
MF		 782021-05-16 Mike Frysinger <vapier@gentoo.org>
79
80 * config.in, configure: Regenerate.
81
df68e12b
MF		 822021-05-14 Mike Frysinger <vapier@gentoo.org>
83
84 * interp.c: Update include path.
85
77c0fdb7
MF		 862021-05-04 Mike Frysinger <vapier@gentoo.org>
87
88 * dv-tx3904sio.c: Include stdlib.h.
89
9b1af85c
MF		 902021-05-04 Mike Frysinger <vapier@gentoo.org>
91
92 * configure.ac (hw_extra_devices): Inline contents into
93 SIM_AC_OPTION_HARDWARE and delete.
94 * configure: Regenerate.
95
d97ba9c6
MF		 962021-05-04 Mike Frysinger <vapier@gentoo.org>
97
98 * Makefile.in (SIM_IGEN_OBJ): Change @mips_igen_engine@ to engine.o.
99 (MIPS_EXTRA_LIB, SIM_EXTRA_LIBS): Delete.
100 * configure.ac (mips_igen_engine, mips_extra_libs): Delete.
101 * configure: Regenerate.
102
4df817de
MF		 1032021-05-04 Mike Frysinger <vapier@gentoo.org>
104
105 * mdmx.c (qh_acc): Change 2nd AccAddAQH to AccAddLQH.
106
aa0fca16
MF		 1072021-05-04 Mike Frysinger <vapier@gentoo.org>
108
109 * configure: Regenerate.
110
adbaa7b8
MF		 1112021-05-01 Mike Frysinger <vapier@gentoo.org>
112
113 * cp1.c (store_fcr): Mark static.
114
fe348617
MF		 1152021-05-01 Mike Frysinger <vapier@gentoo.org>
116
117 * config.in, configure: Regenerate.
118
9d903352
MF		 1192021-04-23 Mike Frysinger <vapier@gentoo.org>
120
121 * configure.ac (hw_enabled): Delete.
122 (SIM_AC_OPTION_HARDWARE): Delete first two args.
123 * configure: Regenerate.
124
19f6a43c
TT		 1252021-04-22 Tom Tromey <tom@tromey.com>
126
127 * configure, config.in: Rebuild.
128
e7d8f1da
TT		 1292021-04-22 Tom Tromey <tom@tromey.com>
130
131 * Makefile.in (interp.o, m16run.o, micromipsrun.o, multi-run.o):
132 Remove.
133 (SIM_EXTRA_DEPS): New variable.
134
efd82ac7
TT		 1352021-04-22 Tom Tromey <tom@tromey.com>
136
137 * configure: Rebuild.
138
2662c237
MF		 1392021-04-21 Mike Frysinger <vapier@gentoo.org>
140
141 * aclocal.m4: Regenerate.
142
1f195bc3
SM		 1432021-04-21 Simon Marchi <simon.marchi@polymtl.ca>
144
145 * configure: Regenerate.
146
37e9f182
MF		 1472021-04-18 Mike Frysinger <vapier@gentoo.org>
148
149 * configure: Regenerate.
150
d5a71b11
MF		 1512021-04-12 Mike Frysinger <vapier@gentoo.org>
152
153 * interp.c (sim_open): Delete 3rd arg to sim_cpu_alloc_all.
154
2b8d134b
SM		 1552021-04-08 Simon Marchi <simon.marchi@polymtl.ca>
156
157 * Makefile.in: Set ASAN_OPTIONS when running igen.
158
5c6f091a
FS		 1592021-04-04 Steve Ellcey <sellcey@mips.com>
160 Faraz Shahbazker <fshahbazker@wavecomp.com>
161
162 * interp.c (sim_monitor): Add switch entries for unlink (13),
163 lseek (14), and stat (15).
164
b6b1c790
MF		 1652021-04-02 Mike Frysinger <vapier@gentoo.org>
166
167 * Makefile.in (../igen/igen): Delete rule.
168 (tmp-igen, tmp-m16, tmp-micromips): Delete ../igen make.
169
c2783492
MF		 1702021-04-02 Mike Frysinger <vapier@gentoo.org>
171
172 * aclocal.m4, configure: Regenerate.
173
ebe9564b
MF		 1742021-02-28 Mike Frysinger <vapier@gentoo.org>
175
176 * configure: Regenerate.
177
f8069d55
MF		 1782021-02-27 Mike Frysinger <vapier@gentoo.org>
179
180 * Makefile.in (SIM_EXTRA_ALL): Delete.
181 (all): New target.
182
760b3e8b
MF		 1832021-02-21 Mike Frysinger <vapier@gentoo.org>
184
185 * configure.ac (AC_CONFIG_MACRO_DIRS): Replace common with m4.
186 * aclocal.m4, configure: Regenerate.
187
136da8cd
MF		 1882021-02-13 Mike Frysinger <vapier@gentoo.org>
189
190 * configure.ac: Replace sinclude with AC_CONFIG_MACRO_DIRS.
191 * aclocal.m4, configure: Regenerate.
192
4c0d76b9
MF		 1932021-02-06 Mike Frysinger <vapier@gentoo.org>
194
195 * interp.c (sim_open): Delete call to STATE_WATCHPOINTS.
196
aa09469f
MF		 1972021-02-06 Mike Frysinger <vapier@gentoo.org>
198
199 * configure: Regenerate.
200
d4e3adda
MF		 2012021-01-30 Mike Frysinger <vapier@gentoo.org>
202
203 * interp.c (sim_open): Delete STATE_WATCHPOINTS (sd)->sizeof_pc.
204
68ed2854
MF		 2052021-01-11 Mike Frysinger <vapier@gentoo.org>
206
207 * config.in, configure: Regenerate.
208 * interp.c: Delete HAVE_STRING_H, HAVE_STRINGS_H, HAVE_STDLIB_H,
209 and strings.h include.
210
50df264d
MF		 2112021-01-09 Mike Frysinger <vapier@gentoo.org>
212
213 * configure: Regenerate.
214
bf470982
MF		 2152021-01-09 Mike Frysinger <vapier@gentoo.org>
216
217 * configure.ac (SIM_AC_OPTION_WARNINGS): Pass "no".
218 * configure: Regenerate.
219
46f900c0
MF		 2202021-01-08 Mike Frysinger <vapier@gentoo.org>
221
222 * configure: Regenerate.
223
dfb856ba
MF		 2242021-01-04 Mike Frysinger <vapier@gentoo.org>
225
226 * configure: Regenerate.
227
382bc56b
PK		 2282020-12-31 Pavel I. Kryukov <kryukov@frtk.ru> (tiny change)
229
230 * sim-main.c: Include <stdlib.h>.
231
ad9675dd
PK		 2322020-12-14 Pavel I. Kryukov <kryukov@frtk.ru> (tiny change)
233
234 * cp1.c: Include <stdlib.h>.
235
f693213d
SM		 2362020-07-29 Simon Marchi <simon.marchi@efficios.com>
237
238 * configure: Re-generate.
239
5c887dd5
JB		 2402017-09-06 John Baldwin <jhb@FreeBSD.org>
241
242 * configure: Regenerate.
243
91588b3a
MF		 2442016-11-11 Mike Frysinger <vapier@gentoo.org>
245
6cb2202b 246 PR sim/20808
91588b3a
MF		 247 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Define CPU to cpu
248 and SD to sd.
249
e04659e8
MF		 2502016-11-11 Mike Frysinger <vapier@gentoo.org>
251
6cb2202b 252 PR sim/20809
e04659e8
MF		 253 * mips.igen (check_u64): Enable for `r3900'.
254
1554f758
MF		 2552016-02-05 Mike Frysinger <vapier@gentoo.org>
256
257 * configure.ac (sim_engine_run): Change sd->base.prog_bfd to
258 STATE_PROG_BFD (sd).
259 * configure: Regenerate.
260
3d304f48
AB		 2612016-01-18 Andrew Bennett <andrew.bennett@imgtec.com>
262 Maciej W. Rozycki <macro@imgtec.com>
263
264 PR sim/19441
265 * micromips.igen (delayslot_micromips): Enable for `micromips32',
266 `micromips64' and `micromipsdsp' only.
267 (process_isa_mode): Enable for `micromips32' and `micromips64' only.
268 (do_micromips_jalr, do_micromips_jal): Likewise.
269 (compute_movep_src_reg): Likewise.
270 (compute_andi16_imm): Likewise.
271 (convert_fmt_micromips): Likewise.
272 (convert_fmt_micromips_cvt_d): Likewise.
273 (convert_fmt_micromips_cvt_s): Likewise.
274 (FMT_MICROMIPS): Likewise.
275 (FMT_MICROMIPS_CVT_D): Likewise.
276 (FMT_MICROMIPS_CVT_S): Likewise.
277
b36d953b
MF		 2782016-01-12 Mike Frysinger <vapier@gentoo.org>
279
280 * interp.c: Include elf-bfd.h.
281 (sim_create_inferior): Truncate pc to 32-bits when EI_CLASS is
282 ELFCLASS32.
283
ce39bd38
MF		 2842016-01-10 Mike Frysinger <vapier@gentoo.org>
285
286 * config.in, configure: Regenerate.
287
99d8e879
MF		 2882016-01-10 Mike Frysinger <vapier@gentoo.org>
289
290 * configure: Regenerate.
291
35656e95
MF		 2922016-01-10 Mike Frysinger <vapier@gentoo.org>
293
294 * configure: Regenerate.
295
16f7876d
MF		 2962016-01-10 Mike Frysinger <vapier@gentoo.org>
297
298 * configure: Regenerate.
299
e19418e0
MF		 3002016-01-10 Mike Frysinger <vapier@gentoo.org>
301
302 * configure: Regenerate.
303
6d90347b
MF		 3042016-01-10 Mike Frysinger <vapier@gentoo.org>
305
306 * configure.ac (SIM_AC_OPTION_SMP): Delete call.
307 * configure: Regenerate.
308
347fe5bb
MF		 3092016-01-10 Mike Frysinger <vapier@gentoo.org>
310
311 * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
312 * configure: Regenerate.
313
22be3fbe
MF		 3142016-01-10 Mike Frysinger <vapier@gentoo.org>
315
316 * configure: Regenerate.
317
0dc73ef7
MF		 3182016-01-10 Mike Frysinger <vapier@gentoo.org>
319
320 * configure: Regenerate.
321
936df756
MF		 3222016-01-09 Mike Frysinger <vapier@gentoo.org>
323
324 * config.in, configure: Regenerate.
325
2e3d4f4d
MF		 3262016-01-06 Mike Frysinger <vapier@gentoo.org>
327
328 * interp.c (sim_open): Mark argv const.
329 (sim_create_inferior): Mark argv and env const.
330
9bbf6f91
MF		 3312016-01-04 Mike Frysinger <vapier@gentoo.org>
332
333 * configure: Regenerate.
334
77cf2ef5
MF		 3352016-01-03 Mike Frysinger <vapier@gentoo.org>
336
337 * interp.c (sim_open): Update sim_parse_args comment.
338
0cb8d851
MF		 3392016-01-03 Mike Frysinger <vapier@gentoo.org>
340
341 * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
342 * configure: Regenerate.
343
1ac72f06
MF		 3442016-01-02 Mike Frysinger <vapier@gentoo.org>
345
346 * configure.ac (mips_endian): Change LITTLE_ENDIAN to LITTLE.
347 (default_endian): Likewise. Change BIG_ENDIAN to BIG.
348 * configure: Regenerate.
349 * sim-main.h (BigEndianMem): Change BIG_ENDIAN to BFD_ENDIAN_BIG.
350
d47f5b30
MF		 3512016-01-02 Mike Frysinger <vapier@gentoo.org>
352
353 * dv-tx3904cpu.c (CPU, SD): Delete.
354
e1211e55
MF		 3552015-12-30 Mike Frysinger <vapier@gentoo.org>
356
357 * wrapper.c (mips_reg_store, mips_reg_fetch): Define.
358 (sim_open): Call CPU_REG_FETCH/CPU_REG_STORE.
359 (sim_store_register): Rename to ...
360 (mips_reg_store): ... this. Delete local cpu var.
361 Update sim_io_eprintf calls.
362 (sim_fetch_register): Rename to ...
363 (mips_reg_fetch): ... this. Delete local cpu var.
364 Update sim_io_eprintf calls.
365
5e744ef8
MF		 3662015-12-27 Mike Frysinger <vapier@gentoo.org>
367
368 * Makefile.in (SIM_OBJS): Delete sim-hload.o.
369
1b393626
MF		 3702015-12-26 Mike Frysinger <vapier@gentoo.org>
371
372 * config.in, configure: Regenerate.
373
26f8bf63
MF		 3742015-12-26 Mike Frysinger <vapier@gentoo.org>
375
376 * interp.c (sim_write, sim_read): Delete.
377 (store_word): Delete call to AddressTranslation and set paddr=vaddr.
378 (load_word): Likewise.
379 * micromips.igen (cache): Likewise.
380 * mips.igen (do_ll, do_lld, do_sc, do_scd, do_suxc1_32, do_swc1,
381 do_swxc1, cache, do_load, do_load_left, do_load_right, do_store,
382 do_store_left, do_store_right, do_load_double, do_store_double):
383 Likewise.
384 (do_pref): Delete call to AddressTranslation and stub out Prefetch.
385 (do_prefx): Likewise.
386 * sim-main.c (address_translation, prefetch): Delete.
387 (ifetch32, ifetch16): Delete call to AddressTranslation and set
388 paddr=vaddr.
389 * sim-main.h (Uncached, CachedNoncoherent, CachedCoherent, Cached,
390 address_translation, AddressTranslation, prefetch, Prefetch): Delete.
391 (LoadMemory, StoreMemory): Delete CCA arg.
392
ef04e371
MF		 3932015-12-24 Mike Frysinger <vapier@gentoo.org>
394
395 * configure.ac (SIM_SUBTARGET): Drop -DTARGET_TX3904=1.
396 * configure: Regenerated.
397
cb379ede
MF		 3982015-12-24 Mike Frysinger <vapier@gentoo.org>
399
400 * sim-main.h (SIM_QUIET_NAN_NEGATED): Move from tconfig.h.
401 * tconfig.h: Delete.
402
26936211
MF		 4032015-12-24 Mike Frysinger <vapier@gentoo.org>
404
405 * tconfig.h (SIM_HANDLES_LMA): Delete.
406
84e8e361
MF		 4072015-12-24 Mike Frysinger <vapier@gentoo.org>
408
409 * sim-main.h (WITH_WATCHPOINTS): Delete.
410
3cabaf66
MF		 4112015-12-24 Mike Frysinger <vapier@gentoo.org>
412
413 * interp.c [SIM_HAVE_FLATMEM] (sim_open): Delete flatmem code.
414
8abe6c66
MF		 4152015-12-24 Mike Frysinger <vapier@gentoo.org>
416
417 * tconfig.h (SIM_HAVE_SIMCACHE): Delete.
418
1d19cae7
DV		 4192015-12-15 Dominik Vogt <vogt@linux.vnet.ibm.com>
420
421 * micromips.igen (process_isa_mode): Fix left shift of negative
422 value.
423
cdf850e9
MF		 4242015-11-17 Mike Frysinger <vapier@gentoo.org>
425
426 * sim-main.h (WITH_MODULO_MEMORY): Delete.
427
797eee42
MF		 4282015-11-15 Mike Frysinger <vapier@gentoo.org>
429
430 * Makefile.in (SIM_OBJS): Delete sim-reason.o and sim-stop.o.
431
6e4f085c
MF		 4322015-11-14 Mike Frysinger <vapier@gentoo.org>
433
434 * interp.c (sim_close): Rename to ...
435 (mips_sim_close): ... this. Delete calls to sim_module_uninstall and
436 sim_io_shutdown.
437 * sim-main.h (mips_sim_close): Declare.
438 (SIM_CLOSE_HOOK): Define.
439
8e394ffc
AB		 4402015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
441 Ali Lown <ali.lown@imgtec.com>
442
443 * Makefile.in (tmp-micromips): New rule.
444 (tmp-mach-multi): Add support for micromips.
445 * configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
446 that works for both mips64 and micromips64.
447 (mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
448 micromips32.
449 Add build support for micromips.
450 * dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
451 do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
452 do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
453 do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
454 do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
455 do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
456 do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
457 do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
458 Refactored instruction code to use these functions.
459 * dsp2.igen: Refactored instruction code to use the new functions.
460 * interp.c (decode_coproc): Refactored to work with any instruction
461 encoding.
462 (isa_mode): New variable
463 (RSVD_INSTRUCTION): Changed to 0x00000039.
464 * m16.igen (BREAK16): Refactored instruction to use do_break16.
465 (JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
466 * micromips.dc: New file.
467 * micromips.igen: New file.
468 * micromips16.dc: New file.
469 * micromipsdsp.igen: New file.
470 * micromipsrun.c: New file.
471 * mips.igen (do_swc1): Changed to work with any instruction encoding.
472 (do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
473 do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo,
474 do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu,
475 do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu,
476 do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub,
477 do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo,
478 do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc,
479 do_scd, do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu,
480 do_tgeu, do_tlt do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt,
481 do_add_fmt, do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1,
482 do_cvt_d_fmt, do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl,
483 do_cvt_s_pu, do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt,
484 do_luxc1_32, do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b,
485 do_mov_fmt, do_movtf, do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt,
486 do_mtc1b, do_mul_fmt, do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps,
487 do_plu_ps, do_pul_ps, do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt,
488 do_prefx, do_sdc1, do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt,
489 do_swc1, do_swxc1, do_trunc_fmt): New functions, refactored from existing
490 instructions.
491 Refactored instruction code to use these functions.
492 (RSVD): Changed to use new reserved instruction.
493 (loadstore_ea, not_word_value, unpredictable, check_mt_hilo,
494 check_mf_hilo, check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32,
495 do_sdc1, do_suxc1_32, check_fmt_p, check_fpu, do_load_double,
496 do_store_double): Added micromips32 and micromips64 models.
497 Added include for micromips.igen and micromipsdsp.igen
498 Add micromips32 and micromips64 models.
499 (DecodeCoproc): Updated to use new macro definition.
500 * mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
501 do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
502 do_seb, do_seh do_rdhwr, do_wsbh): New functions.
503 Refactored instruction code to use these functions.
504 * sim-main.h (CP0_operation): New enum.
505 (DecodeCoproc): Updated macro.
506 (IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
507 MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16,
508 MICROMIPS_DELAYSLOT_SIZE_32, ISA_MODE_MIPS32 and
509 ISA_MODE_MICROMIPS): New defines.
510 (sim_state): Add isa_mode field.
511
8d0978fb
MF		 5122015-06-23 Mike Frysinger <vapier@gentoo.org>
513
514 * configure: Regenerate.
515
306f4178
MF		 5162015-06-12 Mike Frysinger <vapier@gentoo.org>
517
518 * configure.ac: Change configure.in to configure.ac.
519 * configure: Regenerate.
520
a3487082
MF		 5212015-06-12 Mike Frysinger <vapier@gentoo.org>
522
523 * configure: Regenerate.
524
29bc024d
MF		 5252015-06-12 Mike Frysinger <vapier@gentoo.org>
526
527 * interp.c [TRACE]: Delete.
528 (TRACE): Change to WITH_TRACE_ANY_P.
529 [!WITH_TRACE_ANY_P] (open_trace): Define.
530 (mips_option_handler, open_trace, sim_close, dotrace):
531 Change defined(TRACE) to WITH_TRACE_ANY_P.
532 (sim_open): Delete TRACE ifdef check.
533 * sim-main.c (load_memory): Delete TRACE ifdef check.
534 (store_memory): Likewise.
535 * sim-main.h [WITH_TRACE_ANY_P] (dotrace, tracefh): Protect decls.
536 [!WITH_TRACE_ANY_P] (dotrace): Define.
537
3ebe2863
MF		 5382015-04-18 Mike Frysinger <vapier@gentoo.org>
539
540 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESTART_HOOK): Delete
541 comments.
542
20bca71d
MF		 5432015-04-18 Mike Frysinger <vapier@gentoo.org>
544
545 * sim-main.h (SIM_CPU): Delete.
546
7e83aa92
MF		 5472015-04-18 Mike Frysinger <vapier@gentoo.org>
548
549 * sim-main.h (sim_cia): Delete.
550
034685f9
MF		 5512015-04-17 Mike Frysinger <vapier@gentoo.org>
552
553 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Change CIA_GET to
554 PU_PC_GET.
555 * interp.c (interrupt_event): Change CIA_GET to CPU_PC_GET.
556 (sim_create_inferior): Change CIA_SET to CPU_PC_SET.
557 * m16run.c (sim_engine_run): Change CIA_GET to CPU_PC_GET and
558 CIA_SET to CPU_PC_SET.
559 * sim-main.h (CIA_GET, CIA_SET): Delete.
560
78e9aa70
MF		 5612015-04-15 Mike Frysinger <vapier@gentoo.org>
562
563 * Makefile.in (SIM_OBJS): Delete sim-cpu.o.
564 * sim-main.h (STATE_CPU): Delete.
565
bf12d44e
MF		 5662015-04-13 Mike Frysinger <vapier@gentoo.org>
567
568 * configure: Regenerate.
569
7bebb329
MF		 5702015-04-13 Mike Frysinger <vapier@gentoo.org>
571
572 * Makefile.in (SIM_OBJS): Add sim-cpu.o.
573 * interp.c (mips_pc_get, mips_pc_set): New functions.
574 (sim_open): Declare new local var i. Call sim_cpu_alloc_all.
575 Call CPU_PC_FETCH & CPU_PC_STORE for all cpus.
576 (sim_pc_get): Delete.
577 * sim-main.h (SIM_CPU): Define.
578 (struct sim_state): Change cpu to an array of pointers.
579 (STATE_CPU): Drop &.
580
8ac57fbd
MF		 5812015-04-13 Mike Frysinger <vapier@gentoo.org>
582
583 * interp.c (mips_option_handler, open_trace, sim_close,
584 sim_write, sim_read, sim_store_register, sim_fetch_register,
585 sim_create_inferior, pr_addr, pr_uword64): Convert old style
586 prototypes.
587 (sim_open): Convert old style prototype. Change casts with
588 sim_write to unsigned char *.
589 (fetch_str): Change null to unsigned char, and change cast to
590 unsigned char *.
591 (sim_monitor): Change c & ch to unsigned char. Change cast to
592 unsigned char *.
593
e787f858
MF		 5942015-04-12 Mike Frysinger <vapier@gentoo.org>
595
596 * Makefile.in (SIM_OBJS): Move interp.o to the start of the list.
597
122bbfb5
MF		 5982015-04-06 Mike Frysinger <vapier@gentoo.org>
599
600 * Makefile.in (SIM_OBJS): Delete sim-engine.o.
601
0fe84f3f
MF		 6022015-04-01 Mike Frysinger <vapier@gentoo.org>
603
604 * tconfig.h (SIM_HAVE_PROFILE): Delete.
605
aadc9410
MF		 6062015-03-31 Mike Frysinger <vapier@gentoo.org>
607
608 * config.in, configure: Regenerate.
609
05f53ed6
MF		 6102015-03-24 Mike Frysinger <vapier@gentoo.org>
611
612 * interp.c (sim_pc_get): New function.
613
c0931f26
MF		 6142015-03-24 Mike Frysinger <vapier@gentoo.org>
615
616 * sim-main.h (SIM_HAVE_BIENDIAN): Delete.
617 * tconfig.h (SIM_HAVE_BIENDIAN): Delete.
618
30452bbe
MF		 6192015-03-24 Mike Frysinger <vapier@gentoo.org>
620
621 * configure: Regenerate.
622
64dd13df
MF		 6232015-03-23 Mike Frysinger <vapier@gentoo.org>
624
625 * configure: Regenerate.
626
49cd1634
MF		 6272015-03-23 Mike Frysinger <vapier@gentoo.org>
628
629 * configure: Regenerate.
630 * configure.ac (mips_extra_objs): Delete.
631 * Makefile.in (MIPS_EXTRA_OBJS): Delete.
632 (SIM_OBJS): Delete MIPS_EXTRA_OBJS.
633
3649cb06
MF		 6342015-03-23 Mike Frysinger <vapier@gentoo.org>
635
636 * configure: Regenerate.
637 * configure.ac: Delete sim_hw checks for dv-sockser.
638
ae7d0cac
MF		 6392015-03-16 Mike Frysinger <vapier@gentoo.org>
640
641 * config.in, configure: Regenerate.
642 * tconfig.in: Rename file ...
643 * tconfig.h: ... here.
644
8406bb59
MF		 6452015-03-15 Mike Frysinger <vapier@gentoo.org>
646
647 * tconfig.in: Delete includes.
648 [HAVE_DV_SOCKSER]: Delete.
649
465fb143
MF		 6502015-03-14 Mike Frysinger <vapier@gentoo.org>
651
652 * Makefile.in (SIM_RUN_OBJS): Delete.
653
5cddc23a
MF		 6542015-03-14 Mike Frysinger <vapier@gentoo.org>
655
656 * configure.ac (AC_CHECK_HEADERS): Delete.
657 * aclocal.m4, configure: Regenerate.
658
2974be62
AM		 6592014-08-19 Alan Modra <amodra@gmail.com>
660
661 * configure: Regenerate.
662
faa743bb
RM		 6632014-08-15 Roland McGrath <mcgrathr@google.com>
664
665 * configure: Regenerate.
666 * config.in: Regenerate.
667
1a8a700e
MF		 6682014-03-04 Mike Frysinger <vapier@gentoo.org>
669
670 * configure: Regenerate.
671
bf3d9781
AM		 6722013-09-23 Alan Modra <amodra@gmail.com>
673
674 * configure: Regenerate.
675
31e6ad7d
MF		 6762013-06-03 Mike Frysinger <vapier@gentoo.org>
677
678 * aclocal.m4, configure: Regenerate.
679
d3685d60
TT		 6802013-05-10 Freddie Chopin <freddie_chopin@op.pl>
681
682 * configure: Rebuild.
683
1517bd27
MF		 6842013-03-26 Mike Frysinger <vapier@gentoo.org>
685
686 * configure: Regenerate.
687
3be31516
JS		 6882013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
689
690 * configure.ac: Address use of dv-sockser.o.
691 * tconfig.in: Conditionalize use of dv_sockser_install.
692 * configure: Regenerated.
693 * config.in: Regenerated.
694
37cb8f8e
SE		 6952012-10-04 Chao-ying Fu <fu@mips.com>
696 Steve Ellcey <sellcey@mips.com>
697
698 * mips/mips3264r2.igen (rdhwr): New.
699
87c8644f
JS		 7002012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
701
702 * configure.ac: Always link against dv-sockser.o.
703 * configure: Regenerate.
704
5f3ef9d0
JB		 7052012-06-15 Joel Brobecker <brobecker@adacore.com>
706
707 * config.in, configure: Regenerate.
708
a6ff997c
NC		 7092012-05-18 Nick Clifton <nickc@redhat.com>
710
711 PR 14072
712 * interp.c: Include config.h before system header files.
713
2232061b
MF		 7142012-03-24 Mike Frysinger <vapier@gentoo.org>
715
716 * aclocal.m4, config.in, configure: Regenerate.
717
db2e4d67
MF		 7182011-12-03 Mike Frysinger <vapier@gentoo.org>
719
720 * aclocal.m4: New file.
721 * configure: Regenerate.
722
4399a56b
MF		 7232011-10-19 Mike Frysinger <vapier@gentoo.org>
724
725 * configure: Regenerate after common/acinclude.m4 update.
726
9c082ca8
MF		 7272011-10-17 Mike Frysinger <vapier@gentoo.org>
728
729 * configure.ac: Change include to common/acinclude.m4.
730
6ffe910a
MF		 7312011-10-17 Mike Frysinger <vapier@gentoo.org>
732
733 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
734 call. Replace common.m4 include with SIM_AC_COMMON.
735 * configure: Regenerate.
736
31b28250
HPN		 7372011-07-08 Hans-Peter Nilsson <hp@axis.com>
738
3faa01e3
HPN		 739 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
740 $(SIM_EXTRA_DEPS).
741 (tmp-mach-multi): Exit early when igen fails.
31b28250 742
2419798b
MF		 7432011-07-05 Mike Frysinger <vapier@gentoo.org>
744
745 * interp.c (sim_do_command): Delete.
746
d79fe0d6
MF		 7472011-02-14 Mike Frysinger <vapier@gentoo.org>
748
749 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
750 (tx3904sio_fifo_reset): Likewise.
751 * interp.c (sim_monitor): Likewise.
752
5558e7e6
MF		 7532010-04-14 Mike Frysinger <vapier@gentoo.org>
754
755 * interp.c (sim_write): Add const to buffer arg.
756
35aafff4
JB		 7572010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
758
759 * interp.c: Don't include sysdep.h
760
3725885a
RW		 7612010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
762
763 * configure: Regenerate.
764
d6416cdc
RW		 7652009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
766
81ecdfbb
RW		 767 * config.in: Regenerate.
768 * configure: Likewise.
769
d6416cdc
RW		 770 * configure: Regenerate.
771
b5bd9624
HPN		 7722008-07-11 Hans-Peter Nilsson <hp@axis.com>
773
774 * configure: Regenerate to track ../common/common.m4 changes.
775 * config.in: Ditto.
776
6efef468 7772008-06-06 Vladimir Prus <vladimir@codesourcery.com>
72f4393d
L		 778 Daniel Jacobowitz <dan@codesourcery.com>
779 Joseph Myers <joseph@codesourcery.com>
6efef468
JM		 780
781 * configure: Regenerate.
782
60dc88db
RS		 7832007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
784
785 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
786 that unconditionally allows fmt_ps.
787 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
788 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
789 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
790 filter from 64,f to 32,f.
791 (PREFX): Change filter from 64 to 32.
792 (LDXC1, LUXC1): Provide separate mips32r2 implementations
793 that use do_load_double instead of do_load. Make both LUXC1
794 versions unpredictable if SizeFGR () != 64.
795 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
796 instead of do_store. Remove unused variable. Make both SUXC1
797 versions unpredictable if SizeFGR () != 64.
798
599ca73e
RS		 7992007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
800
801 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
802 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
803 shifts for that case.
804
2525df03
NC		 8052007-09-04 Nick Clifton <nickc@redhat.com>
806
807 * interp.c (options enum): Add OPTION_INFO_MEMORY.
808 (display_mem_info): New static variable.
809 (mips_option_handler): Handle OPTION_INFO_MEMORY.
810 (mips_options): Add info-memory and memory-info.
811 (sim_open): After processing the command line and board
812 specification, check display_mem_info. If it is set then
813 call the real handler for the --memory-info command line
814 switch.
815
35ee6e1e
JB		 8162007-08-24 Joel Brobecker <brobecker@adacore.com>
817
818 * configure.ac: Change license of multi-run.c to GPL version 3.
819 * configure: Regenerate.
820
d5fb0879
RS		 8212007-06-28 Richard Sandiford <richard@codesourcery.com>
822
823 * configure.ac, configure: Revert last patch.
824
2a2ce21b
RS		 8252007-06-26 Richard Sandiford <richard@codesourcery.com>
826
827 * configure.ac (sim_mipsisa3264_configs): New variable.
828 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
829 every configuration support all four targets, using the triplet to
830 determine the default.
831 * configure: Regenerate.
832
efdcccc9
RS		 8332007-06-25 Richard Sandiford <richard@codesourcery.com>
834
0a7692b2 835 * Makefile.in (m16run.o): New rule.
efdcccc9 836
f532a356
TS		 8372007-05-15 Thiemo Seufer <ths@mips.com>
838
839 * mips3264r2.igen (DSHD): Fix compile warning.
840
bfe9c90b
TS		 8412007-05-14 Thiemo Seufer <ths@mips.com>
842
843 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
844 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
845 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
846 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
847 for mips32r2.
848
53f4826b
TS		 8492007-03-01 Thiemo Seufer <ths@mips.com>
850
851 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
852 and mips64.
853
8bf3ddc8
TS		 8542007-02-20 Thiemo Seufer <ths@mips.com>
855
856 * dsp.igen: Update copyright notice.
857 * dsp2.igen: Fix copyright notice.
858
8b082fb1 8592007-02-20 Thiemo Seufer <ths@mips.com>
72f4393d 860 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 861
862 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
863 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
864 Add dsp2 to sim_igen_machine.
865 * configure: Regenerate.
866 * dsp.igen (do_ph_op): Add MUL support when op = 2.
867 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
868 (mulq_rs.ph): Use do_ph_mulq.
869 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
870 * mips.igen: Add dsp2 model and include dsp2.igen.
871 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
872 for *mips32r2, *mips64r2, *dsp.
873 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
874 for *mips32r2, *mips64r2, *dsp2.
875 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
876
b1004875 8772007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 878 Nigel Stephens <nigel@mips.com>
b1004875
TS		 879
880 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
881 jumps with hazard barrier.
882
f8df4c77 8832007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 884 Nigel Stephens <nigel@mips.com>
f8df4c77
TS		 885
886 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
887 after each call to sim_io_write.
888
b1004875 8892007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 890 Nigel Stephens <nigel@mips.com>
b1004875
TS		 891
892 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
893 supported by this simulator.
07802d98
TS		 894 (decode_coproc): Recognise additional CP0 Config registers
895 correctly.
896
14fb6c5a 8972007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d
L		 898 Nigel Stephens <nigel@mips.com>
899 David Ung <davidu@mips.com>
14fb6c5a
TS		 900
901 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
902 uninterpreted formats. If fmt is one of the uninterpreted types
903 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
904 fmt_word, and fmt_uninterpreted_64 like fmt_long.
905 (store_fpr): When writing an invalid odd register, set the
906 matching even register to fmt_unknown, not the following register.
907 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
908 the the memory window at offset 0 set by --memory-size command
909 line option.
910 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
911 point register.
912 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
913 register.
914 (sim_monitor): When returning the memory size to the MIPS
915 application, use the value in STATE_MEM_SIZE, not an arbitrary
916 hardcoded value.
917 (cop_lw): Don' mess around with FPR_STATE, just pass
918 fmt_uninterpreted_32 to StoreFPR.
919 (cop_sw): Similarly.
920 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
921 (cop_sd): Similarly.
922 * mips.igen (not_word_value): Single version for mips32, mips64
923 and mips16.
924
c8847145 9252007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 926 Nigel Stephens <nigel@mips.com>
c8847145
TS		 927
928 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
929 MBytes.
930
4b5d35ee
TS		 9312007-02-17 Thiemo Seufer <ths@mips.com>
932
933 * configure.ac (mips*-sde-elf*): Move in front of generic machine
934 configuration.
935 * configure: Regenerate.
936
3669427c
TS		 9372007-02-17 Thiemo Seufer <ths@mips.com>
938
939 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
940 Add mdmx to sim_igen_machine.
941 (mipsisa64*-*-*): Likewise. Remove dsp.
942 (mipsisa32*-*-*): Remove dsp.
943 * configure: Regenerate.
944
109ad085
TS		 9452007-02-13 Thiemo Seufer <ths@mips.com>
946
947 * configure.ac: Add mips*-sde-elf* target.
948 * configure: Regenerate.
949
921d7ad3
HPN		 9502006-12-21 Hans-Peter Nilsson <hp@axis.com>
951
952 * acconfig.h: Remove.
953 * config.in, configure: Regenerate.
954
02f97da7
TS		 9552006-11-07 Thiemo Seufer <ths@mips.com>
956
957 * dsp.igen (do_w_op): Fix compiler warning.
958
2d2733fc 9592006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 960 David Ung <davidu@mips.com>
2d2733fc
TS		 961
962 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
963 sim_igen_machine.
964 * configure: Regenerate.
965 * mips.igen (model): Add smartmips.
966 (MADDU): Increment ACX if carry.
967 (do_mult): Clear ACX.
968 (ROR,RORV): Add smartmips.
72f4393d 969 (include): Include smartmips.igen.
2d2733fc
TS		 970 * sim-main.h (ACX): Set to REGISTERS[89].
971 * smartmips.igen: New file.
972
d85c3a10 9732006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 974 David Ung <davidu@mips.com>
d85c3a10
TS		 975
976 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
977 mips3264r2.igen. Add missing dependency rules.
978 * m16e.igen: Support for mips16e save/restore instructions.
979
e85e3205
RE		 9802006-06-13 Richard Earnshaw <rearnsha@arm.com>
981
982 * configure: Regenerated.
983
2f0122dc
DJ		 9842006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
985
986 * configure: Regenerated.
987
20e95c23
DJ		 9882006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
989
990 * configure: Regenerated.
991
69088b17
CF		 9922006-05-15 Chao-ying Fu <fu@mips.com>
993
994 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
995
0275de4e
NC		 9962006-04-18 Nick Clifton <nickc@redhat.com>
997
998 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
999 statement.
1000
b3a3ffef
HPN		 10012006-03-29 Hans-Peter Nilsson <hp@axis.com>
1002
1003 * configure: Regenerate.
1004
40a5538e
CF		 10052005-12-14 Chao-ying Fu <fu@mips.com>
1006
1007 * Makefile.in (SIM_OBJS): Add dsp.o.
1008 (dsp.o): New dependency.
1009 (IGEN_INCLUDE): Add dsp.igen.
1010 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
1011 mipsisa64*-*-*): Add dsp to sim_igen_machine.
1012 * configure: Regenerate.
1013 * mips.igen: Add dsp model and include dsp.igen.
1014 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
1015 because these instructions are extended in DSP ASE.
1016 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
1017 adding 6 DSP accumulator registers and 1 DSP control register.
1018 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
1019 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
1020 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
1021 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
1022 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
1023 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
1024 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
1025 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
1026 DSPCR_CCOND_SMASK): New define.
1027 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
1028 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
1029
21d14896
ILT		 10302005-07-08 Ian Lance Taylor <ian@airs.com>
1031
1032 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
1033
b16d63da 10342005-06-16 David Ung <davidu@mips.com>
72f4393d
L		 1035 Nigel Stephens <nigel@mips.com>
1036
1037 * mips.igen: New mips16e model and include m16e.igen.
1038 (check_u64): Add mips16e tag.
1039 * m16e.igen: New file for MIPS16e instructions.
1040 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
1041 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
1042 models.
1043 * configure: Regenerate.
b16d63da 1044
e70cb6cd 10452005-05-26 David Ung <davidu@mips.com>
72f4393d 1046
e70cb6cd
CD		 1047 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
1048 tags to all instructions which are applicable to the new ISAs.
1049 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
1050 vr.igen.
1051 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
72f4393d 1052 instructions.
e70cb6cd
CD		 1053 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
1054 to mips.igen.
1055 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
1056 * configure: Regenerate.
72f4393d 1057
2b193c4a
MK		 10582005-03-23 Mark Kettenis <kettenis@gnu.org>
1059
1060 * configure: Regenerate.
1061
35695fd6
AC		 10622005-01-14 Andrew Cagney <cagney@gnu.org>
1063
1064 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
1065 explicit call to AC_CONFIG_HEADER.
1066 * configure: Regenerate.
1067
f0569246
AC		 10682005-01-12 Andrew Cagney <cagney@gnu.org>
1069
1070 * configure.ac: Update to use ../common/common.m4.
1071 * configure: Re-generate.
1072
38f48d72
AC		 10732005-01-11 Andrew Cagney <cagney@localhost.localdomain>
1074
1075 * configure: Regenerated to track ../common/aclocal.m4 changes.
1076
b7026657
AC		 10772005-01-07 Andrew Cagney <cagney@gnu.org>
1078
1079 * configure.ac: Rename configure.in, require autoconf 2.59.
1080 * configure: Re-generate.
1081
379832de
HPN		 10822004-12-08 Hans-Peter Nilsson <hp@axis.com>
1083
1084 * configure: Regenerate for ../common/aclocal.m4 update.
1085
cd62154c 10862004-09-24 Monika Chaddha <monika@acmet.com>
72f4393d 1087
cd62154c
AC		 1088 Committed by Andrew Cagney.
1089 * m16.igen (CMP, CMPI): Fix assembler.
1090
e5da76ec
CD		 10912004-08-18 Chris Demetriou <cgd@broadcom.com>
1092
1093 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
1094 * configure: Regenerate.
1095
139181c8
CD		 10962004-06-25 Chris Demetriou <cgd@broadcom.com>
1097
1098 * configure.in (sim_m16_machine): Include mipsIII.
1099 * configure: Regenerate.
1100
1a27f959
CD		 11012004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
1102
72f4393d 1103 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
1a27f959
CD		 1104 from COP0_BADVADDR.
1105 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
1106
5dbb7b5a
CD		 11072004-04-10 Chris Demetriou <cgd@broadcom.com>
1108
1109 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
1110
14234056
CD		 11112004-04-09 Chris Demetriou <cgd@broadcom.com>
1112
1113 * mips.igen (check_fmt): Remove.
1114 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
1115 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
1116 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
1117 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
1118 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
1119 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
1120 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1121 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
1122 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
1123 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
1124
c6f9085c
CD		 11252004-04-09 Chris Demetriou <cgd@broadcom.com>
1126
1127 * sb1.igen (check_sbx): New function.
1128 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
1129
11d66e66 11302004-03-29 Chris Demetriou <cgd@broadcom.com>
0e1b7197
RS		 1131 Richard Sandiford <rsandifo@redhat.com>
1132
1133 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
1134 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
1135 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
1136 separate implementations for mipsIV and mipsV. Use new macros to
1137 determine whether the restrictions apply.
1138
b3208fb8
CD		 11392004-01-19 Chris Demetriou <cgd@broadcom.com>
1140
1141 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
1142 (check_mult_hilo): Improve comments.
1143 (check_div_hilo): Likewise. Also, fork off a new version
1144 to handle mips32/mips64 (since there are no hazards to check
1145 in MIPS32/MIPS64).
1146
9a1d84fb
CD		 11472003-06-17 Richard Sandiford <rsandifo@redhat.com>
1148
1149 * mips.igen (do_dmultx): Fix check for negative operands.
1150
ae451ac6
ILT		 11512003-05-16 Ian Lance Taylor <ian@airs.com>
1152
1153 * Makefile.in (SHELL): Make sure this is defined.
1154 (various): Use $(SHELL) whenever we invoke move-if-change.
1155
dd69d292
CD		 11562003-05-03 Chris Demetriou <cgd@broadcom.com>
1157
1158 * cp1.c: Tweak attribution slightly.
1159 * cp1.h: Likewise.
1160 * mdmx.c: Likewise.
1161 * mdmx.igen: Likewise.
1162 * mips3d.igen: Likewise.
1163 * sb1.igen: Likewise.
1164
bcd0068e
CD		 11652003-04-15 Richard Sandiford <rsandifo@redhat.com>
1166
1167 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
1168 unsigned operands.
1169
6b4a8935
AC		 11702003-02-27 Andrew Cagney <cagney@redhat.com>
1171
601da316
AC		 1172 * interp.c (sim_open): Rename _bfd to bfd.
1173 (sim_create_inferior): Ditto.
6b4a8935 1174
d29e330f
CD		 11752003-01-14 Chris Demetriou <cgd@broadcom.com>
1176
1177 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
1178
a2353a08
CD		 11792003-01-14 Chris Demetriou <cgd@broadcom.com>
1180
1181 * mips.igen (EI, DI): Remove.
1182
80551777
CD		 11832003-01-05 Richard Sandiford <rsandifo@redhat.com>
1184
1185 * Makefile.in (tmp-run-multi): Fix mips16 filter.
1186
4c54fc26
CD		 11872003-01-04 Richard Sandiford <rsandifo@redhat.com>
1188 Andrew Cagney <ac131313@redhat.com>
1189 Gavin Romig-Koch <gavin@redhat.com>
1190 Graydon Hoare <graydon@redhat.com>
1191 Aldy Hernandez <aldyh@redhat.com>
1192 Dave Brolley <brolley@redhat.com>
1193 Chris Demetriou <cgd@broadcom.com>
1194
1195 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
1196 (sim_mach_default): New variable.
1197 (mips64vr-*-*, mips64vrel-*-*): New configurations.
1198 Add a new simulator generator, MULTI.
1199 * configure: Regenerate.
1200 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
1201 (multi-run.o): New dependency.
1202 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
1203 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
1204 (tmp-multi): Combine them.
1205 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
1206 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
1207 (distclean-extra): New rule.
1208 * sim-main.h: Include bfd.h.
1209 (MIPS_MACH): New macro.
1210 * mips.igen (vr4120, vr5400, vr5500): New models.
1211 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
1212 * vr.igen: Replace with new version.
1213
e6c674b8
CD		 12142003-01-04 Chris Demetriou <cgd@broadcom.com>
1215
1216 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
1217 * configure: Regenerate.
1218
28f50ac8
CD		 12192002-12-31 Chris Demetriou <cgd@broadcom.com>
1220
1221 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
1222 * mips.igen: Remove all invocations of check_branch_bug and
1223 mark_branch_bug.
1224
5071ffe6
CD		 12252002-12-16 Chris Demetriou <cgd@broadcom.com>
1226
72f4393d 1227 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
5071ffe6 1228
06e7837e
CD		 12292002-07-30 Chris Demetriou <cgd@broadcom.com>
1230
1231 * mips.igen (do_load_double, do_store_double): New functions.
1232 (LDC1, SDC1): Rename to...
1233 (LDC1b, SDC1b): respectively.
1234 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
1235
2265c243
MS		 12362002-07-29 Michael Snyder <msnyder@redhat.com>
1237
1238 * cp1.c (fp_recip2): Modify initialization expression so that
1239 GCC will recognize it as constant.
1240
a2f8b4f3
CD		 12412002-06-18 Chris Demetriou <cgd@broadcom.com>
1242
1243 * mdmx.c (SD_): Delete.
1244 (Unpredictable): Re-define, for now, to directly invoke
1245 unpredictable_action().
1246 (mdmx_acc_op): Fix error in .ob immediate handling.
1247
b4b6c939
AC		 12482002-06-18 Andrew Cagney <cagney@redhat.com>
1249
1250 * interp.c (sim_firmware_command): Initialize `address'.
1251
c8cca39f
AC		 12522002-06-16 Andrew Cagney <ac131313@redhat.com>
1253
1254 * configure: Regenerated to track ../common/aclocal.m4 changes.
1255
e7e81181 12562002-06-14 Chris Demetriou <cgd@broadcom.com>
72f4393d 1257 Ed Satterthwaite <ehs@broadcom.com>
e7e81181
CD		 1258
1259 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
1260 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
1261 * mips.igen: Include mips3d.igen.
1262 (mips3d): New model name for MIPS-3D ASE instructions.
1263 (CVT.W.fmt): Don't use this instruction for word (source) format
72f4393d 1264 instructions.
e7e81181
CD		 1265 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
1266 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
1267 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
1268 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
1269 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
1270 (RSquareRoot1, RSquareRoot2): New macros.
1271 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
1272 (fp_rsqrt2): New functions.
1273 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
1274 * configure: Regenerate.
1275
3a2b820e 12762002-06-13 Chris Demetriou <cgd@broadcom.com>
72f4393d 1277 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 1278
1279 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
1280 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
1281 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
1282 (convert): Note that this function is not used for paired-single
1283 format conversions.
1284 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
1285 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
1286 (check_fmt_p): Enable paired-single support.
1287 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
1288 (PUU.PS): New instructions.
1289 (CVT.S.fmt): Don't use this instruction for paired-single format
1290 destinations.
1291 * sim-main.h (FP_formats): New value 'fmt_ps.'
1292 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
1293 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
1294
d18ea9c2
CD		 12952002-06-12 Chris Demetriou <cgd@broadcom.com>
1296
1297 * mips.igen: Fix formatting of function calls in
1298 many FP operations.
1299
95fd5cee
CD		 13002002-06-12 Chris Demetriou <cgd@broadcom.com>
1301
1302 * mips.igen (MOVN, MOVZ): Trace result.
1303 (TNEI): Print "tnei" as the opcode name in traces.
1304 (CEIL.W): Add disassembly string for traces.
1305 (RSQRT.fmt): Make location of disassembly string consistent
1306 with other instructions.
1307
4f0d55ae
CD		 13082002-06-12 Chris Demetriou <cgd@broadcom.com>
1309
1310 * mips.igen (X): Delete unused function.
1311
3c25f8c7
AC		 13122002-06-08 Andrew Cagney <cagney@redhat.com>
1313
1314 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
1315
f3c08b7e 13162002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1317 Ed Satterthwaite <ehs@broadcom.com>
f3c08b7e
CD		 1318
1319 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
1320 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
1321 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
1322 (fp_nmsub): New prototypes.
1323 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
1324 (NegMultiplySub): New defines.
1325 * mips.igen (RSQRT.fmt): Use RSquareRoot().
1326 (MADD.D, MADD.S): Replace with...
1327 (MADD.fmt): New instruction.
1328 (MSUB.D, MSUB.S): Replace with...
1329 (MSUB.fmt): New instruction.
1330 (NMADD.D, NMADD.S): Replace with...
1331 (NMADD.fmt): New instruction.
1332 (NMSUB.D, MSUB.S): Replace with...
1333 (NMSUB.fmt): New instruction.
1334
52714ff9 13352002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1336 Ed Satterthwaite <ehs@broadcom.com>
52714ff9
CD		 1337
1338 * cp1.c: Fix more comment spelling and formatting.
1339 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
1340 (denorm_mode): New function.
1341 (fpu_unary, fpu_binary): Round results after operation, collect
1342 status from rounding operations, and update the FCSR.
1343 (convert): Collect status from integer conversions and rounding
1344 operations, and update the FCSR. Adjust NaN values that result
1345 from conversions. Convert to use sim_io_eprintf rather than
1346 fprintf, and remove some debugging code.
1347 * cp1.h (fenr_FS): New define.
1348
577d8c4b
CD		 13492002-06-07 Chris Demetriou <cgd@broadcom.com>
1350
1351 * cp1.c (convert): Remove unusable debugging code, and move MIPS
1352 rounding mode to sim FP rounding mode flag conversion code into...
1353 (rounding_mode): New function.
1354
196496ed
CD		 13552002-06-07 Chris Demetriou <cgd@broadcom.com>
1356
1357 * cp1.c: Clean up formatting of a few comments.
1358 (value_fpr): Reformat switch statement.
1359
cfe9ea23 13602002-06-06 Chris Demetriou <cgd@broadcom.com>
72f4393d 1361 Ed Satterthwaite <ehs@broadcom.com>
cfe9ea23
CD		 1362
1363 * cp1.h: New file.
1364 * sim-main.h: Include cp1.h.
1365 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
1366 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
1367 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
1368 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
1369 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
1370 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
1371 * cp1.c: Don't include sim-fpu.h; already included by
1372 sim-main.h. Clean up formatting of some comments.
1373 (NaN, Equal, Less): Remove.
1374 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
1375 (fp_cmp): New functions.
1376 * mips.igen (do_c_cond_fmt): Remove.
1377 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
1378 Compare. Add result tracing.
1379 (CxC1): Remove, replace with...
1380 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
1381 (DMxC1): Remove, replace with...
1382 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
72f4393d
L		 1383 (MxC1): Remove, replace with...
1384 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
cfe9ea23 1385
ee7254b0
CD		 13862002-06-04 Chris Demetriou <cgd@broadcom.com>
1387
1388 * sim-main.h (FGRIDX): Remove, replace all uses with...
1389 (FGR_BASE): New macro.
1390 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
1391 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
1392 (NR_FGR, FGR): Likewise.
1393 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
1394 * mips.igen: Likewise.
1395
d3eb724f
CD		 13962002-06-04 Chris Demetriou <cgd@broadcom.com>
1397
1398 * cp1.c: Add an FSF Copyright notice to this file.
1399
ba46ddd0 14002002-06-04 Chris Demetriou <cgd@broadcom.com>
72f4393d 1401 Ed Satterthwaite <ehs@broadcom.com>
ba46ddd0
CD		 1402
1403 * cp1.c (Infinity): Remove.
1404 * sim-main.h (Infinity): Likewise.
1405
1406 * cp1.c (fp_unary, fp_binary): New functions.
1407 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
1408 (fp_sqrt): New functions, implemented in terms of the above.
1409 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1410 (Recip, SquareRoot): Remove (replaced by functions above).
1411 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
1412 (fp_recip, fp_sqrt): New prototypes.
1413 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1414 (Recip, SquareRoot): Replace prototypes with #defines which
1415 invoke the functions above.
72f4393d 1416
18d8a52d
CD		 14172002-06-03 Chris Demetriou <cgd@broadcom.com>
1418
1419 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
1420 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
1421 file, remove PARAMS from prototypes.
1422 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
1423 simulator state arguments.
1424 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
1425 pass simulator state arguments.
1426 * cp1.c (SD): Redefine as CPU_STATE(cpu).
1427 (store_fpr, convert): Remove 'sd' argument.
1428 (value_fpr): Likewise. Convert to use 'SD' instead.
1429
0f154cbd
CD		 14302002-06-03 Chris Demetriou <cgd@broadcom.com>
1431
1432 * cp1.c (Min, Max): Remove #if 0'd functions.
1433 * sim-main.h (Min, Max): Remove.
1434
e80fc152
CD		 14352002-06-03 Chris Demetriou <cgd@broadcom.com>
1436
1437 * cp1.c: fix formatting of switch case and default labels.
1438 * interp.c: Likewise.
1439 * sim-main.c: Likewise.
1440
bad673a9
CD		 14412002-06-03 Chris Demetriou <cgd@broadcom.com>
1442
1443 * cp1.c: Clean up comments which describe FP formats.
1444 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
1445
7cbea089 14462002-06-03 Chris Demetriou <cgd@broadcom.com>
72f4393d 1447 Ed Satterthwaite <ehs@broadcom.com>
7cbea089
CD		 1448
1449 * configure.in (mipsisa64sb1*-*-*): New target for supporting
1450 Broadcom SiByte SB-1 processor configurations.
1451 * configure: Regenerate.
1452 * sb1.igen: New file.
1453 * mips.igen: Include sb1.igen.
1454 (sb1): New model.
1455 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
1456 * mdmx.igen: Add "sb1" model to all appropriate functions and
1457 instructions.
1458 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
1459 (ob_func, ob_acc): Reference the above.
1460 (qh_acc): Adjust to keep the same size as ob_acc.
1461 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
1462 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
1463
909daa82
CD		 14642002-06-03 Chris Demetriou <cgd@broadcom.com>
1465
1466 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
1467
f4f1b9f1 14682002-06-02 Chris Demetriou <cgd@broadcom.com>
72f4393d 1469 Ed Satterthwaite <ehs@broadcom.com>
f4f1b9f1
CD		 1470
1471 * mips.igen (mdmx): New (pseudo-)model.
1472 * mdmx.c, mdmx.igen: New files.
1473 * Makefile.in (SIM_OBJS): Add mdmx.o.
1474 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
1475 New typedefs.
1476 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
1477 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
1478 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
1479 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
1480 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
1481 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
1482 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
1483 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
1484 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
1485 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
1486 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
1487 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
1488 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
1489 (qh_fmtsel): New macros.
1490 (_sim_cpu): New member "acc".
1491 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
1492 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
1493
5accf1ff
CD		 14942002-05-01 Chris Demetriou <cgd@broadcom.com>
1495
1496 * interp.c: Use 'deprecated' rather than 'depreciated.'
1497 * sim-main.h: Likewise.
1498
402586aa
CD		 14992002-05-01 Chris Demetriou <cgd@broadcom.com>
1500
1501 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
1502 which wouldn't compile anyway.
1503 * sim-main.h (unpredictable_action): New function prototype.
1504 (Unpredictable): Define to call igen function unpredictable().
1505 (NotWordValue): New macro to call igen function not_word_value().
1506 (UndefinedResult): Remove.
1507 * interp.c (undefined_result): Remove.
1508 (unpredictable_action): New function.
1509 * mips.igen (not_word_value, unpredictable): New functions.
1510 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
1511 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
1512 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
1513 NotWordValue() to check for unpredictable inputs, then
1514 Unpredictable() to handle them.
1515
c9b9995a
CD		 15162002-02-24 Chris Demetriou <cgd@broadcom.com>
1517
1518 * mips.igen: Fix formatting of calls to Unpredictable().
1519
e1015982
AC		 15202002-04-20 Andrew Cagney <ac131313@redhat.com>
1521
1522 * interp.c (sim_open): Revert previous change.
1523
b882a66b
AO		 15242002-04-18 Alexandre Oliva <aoliva@redhat.com>
1525
1526 * interp.c (sim_open): Disable chunk of code that wrote code in
1527 vector table entries.
1528
c429b7dd
CD		 15292002-03-19 Chris Demetriou <cgd@broadcom.com>
1530
1531 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
1532 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
1533 unused definitions.
1534
37d146fa
CD		 15352002-03-19 Chris Demetriou <cgd@broadcom.com>
1536
1537 * cp1.c: Fix many formatting issues.
1538
07892c0b
CD		 15392002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1540
1541 * cp1.c (fpu_format_name): New function to replace...
1542 (DOFMT): This. Delete, and update all callers.
1543 (fpu_rounding_mode_name): New function to replace...
1544 (RMMODE): This. Delete, and update all callers.
1545
487f79b7
CD		 15462002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1547
1548 * interp.c: Move FPU support routines from here to...
1549 * cp1.c: Here. New file.
1550 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
1551 (cp1.o): New target.
1552
1e799e28
CD		 15532002-03-12 Chris Demetriou <cgd@broadcom.com>
1554
1555 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
1556 * mips.igen (mips32, mips64): New models, add to all instructions
1557 and functions as appropriate.
1558 (loadstore_ea, check_u64): New variant for model mips64.
1559 (check_fmt_p): New variant for models mipsV and mips64, remove
1560 mipsV model marking fro other variant.
1561 (SLL) Rename to...
1562 (SLLa) this.
1563 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
1564 for mips32 and mips64.
1565 (DCLO, DCLZ): New instructions for mips64.
1566
82f728db
CD		 15672002-03-07 Chris Demetriou <cgd@broadcom.com>
1568
1569 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
1570 immediate or code as a hex value with the "%#lx" format.
1571 (ANDI): Likewise, and fix printed instruction name.
1572
b96e7ef1
CD		 15732002-03-05 Chris Demetriou <cgd@broadcom.com>
1574
1575 * sim-main.h (UndefinedResult, Unpredictable): New macros
1576 which currently do nothing.
1577
d35d4f70
CD		 15782002-03-05 Chris Demetriou <cgd@broadcom.com>
1579
1580 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
1581 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
1582 (status_CU3): New definitions.
1583
1584 * sim-main.h (ExceptionCause): Add new values for MIPS32
1585 and MIPS64: MDMX, MCheck, CacheErr. Update comments
1586 for DebugBreakPoint and NMIReset to note their status in
1587 MIPS32 and MIPS64.
1588 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
1589 (SignalExceptionCacheErr): New exception macros.
1590
3ad6f714
CD		 15912002-03-05 Chris Demetriou <cgd@broadcom.com>
1592
1593 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
1594 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
1595 is always enabled.
1596 (SignalExceptionCoProcessorUnusable): Take as argument the
1597 unusable coprocessor number.
1598
86b77b47
CD		 15992002-03-05 Chris Demetriou <cgd@broadcom.com>
1600
1601 * mips.igen: Fix formatting of all SignalException calls.
1602
97a88e93 16032002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 1604
1605 * sim-main.h (SIGNEXTEND): Remove.
1606
97a88e93 16072002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 1608
1609 * mips.igen: Remove gencode comment from top of file, fix
1610 spelling in another comment.
1611
97a88e93 16122002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 1613
1614 * mips.igen (check_fmt, check_fmt_p): New functions to check
1615 whether specific floating point formats are usable.
1616 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1617 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
1618 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
1619 Use the new functions.
1620 (do_c_cond_fmt): Remove format checks...
1621 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
1622
97a88e93 16232002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 1624
1625 * mips.igen: Fix formatting of check_fpu calls.
1626
41774c9d
CD		 16272002-03-03 Chris Demetriou <cgd@broadcom.com>
1628
1629 * mips.igen (FLOOR.L.fmt): Store correct destination register.
1630
4a0bd876
CD		 16312002-03-03 Chris Demetriou <cgd@broadcom.com>
1632
1633 * mips.igen: Remove whitespace at end of lines.
1634
09297648
CD		 16352002-03-02 Chris Demetriou <cgd@broadcom.com>
1636
1637 * mips.igen (loadstore_ea): New function to do effective
1638 address calculations.
1639 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
1640 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
1641 CACHE): Use loadstore_ea to do effective address computations.
1642
043b7057
CD		 16432002-03-02 Chris Demetriou <cgd@broadcom.com>
1644
1645 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
1646 * mips.igen (LL, CxC1, MxC1): Likewise.
1647
c1e8ada4
CD		 16482002-03-02 Chris Demetriou <cgd@broadcom.com>
1649
1650 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
1651 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
1652 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
1653 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
1654 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
1655 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
1656 Don't split opcode fields by hand, use the opcode field values
1657 provided by igen.
1658
3e1dca16
CD		 16592002-03-01 Chris Demetriou <cgd@broadcom.com>
1660
1661 * mips.igen (do_divu): Fix spacing.
1662
1663 * mips.igen (do_dsllv): Move to be right before DSLLV,
1664 to match the rest of the do_<shift> functions.
1665
fff8d27d
CD		 16662002-03-01 Chris Demetriou <cgd@broadcom.com>
1667
1668 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
1669 DSRL32, do_dsrlv): Trace inputs and results.
1670
0d3e762b
CD		 16712002-03-01 Chris Demetriou <cgd@broadcom.com>
1672
1673 * mips.igen (CACHE): Provide instruction-printing string.
1674
1675 * interp.c (signal_exception): Comment tokens after #endif.
1676
eb5fcf93
CD		 16772002-02-28 Chris Demetriou <cgd@broadcom.com>
1678
1679 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
72f4393d
L		 1680 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
1681 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
1682 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
1683 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
1684 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
1685 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
eb5fcf93
CD		 1686 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
1687
bb22bd7d
CD		 16882002-02-28 Chris Demetriou <cgd@broadcom.com>
1689
1690 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
1691 instruction-printing string.
1692 (LWU): Use '64' as the filter flag.
1693
91a177cf
CD		 16942002-02-28 Chris Demetriou <cgd@broadcom.com>
1695
1696 * mips.igen (SDXC1): Fix instruction-printing string.
1697
387f484a
CD		 16982002-02-28 Chris Demetriou <cgd@broadcom.com>
1699
1700 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
1701 filter flags "32,f".
1702
3d81f391
CD		 17032002-02-27 Chris Demetriou <cgd@broadcom.com>
1704
1705 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1706 as the filter flag.
1707
af5107af
CD		 17082002-02-27 Chris Demetriou <cgd@broadcom.com>
1709
1710 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1711 add a comma) so that it more closely match the MIPS ISA
1712 documentation opcode partitioning.
1713 (PREF): Put useful names on opcode fields, and include
1714 instruction-printing string.
1715
ca971540
CD		 17162002-02-27 Chris Demetriou <cgd@broadcom.com>
1717
1718 * mips.igen (check_u64): New function which in the future will
1719 check whether 64-bit instructions are usable and signal an
1720 exception if not. Currently a no-op.
1721 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1722 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1723 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1724 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1725
1726 * mips.igen (check_fpu): New function which in the future will
1727 check whether FPU instructions are usable and signal an exception
1728 if not. Currently a no-op.
1729 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1730 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1731 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1732 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1733 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1734 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1735 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1736 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1737
1c47a468
CD		 17382002-02-27 Chris Demetriou <cgd@broadcom.com>
1739
1740 * mips.igen (do_load_left, do_load_right): Move to be immediately
1741 following do_load.
1742 (do_store_left, do_store_right): Move to be immediately following
1743 do_store.
1744
603a98e7
CD		 17452002-02-27 Chris Demetriou <cgd@broadcom.com>
1746
1747 * mips.igen (mipsV): New model name. Also, add it to
1748 all instructions and functions where it is appropriate.
1749
c5d00cc7
CD		 17502002-02-18 Chris Demetriou <cgd@broadcom.com>
1751
1752 * mips.igen: For all functions and instructions, list model
1753 names that support that instruction one per line.
1754
074e9cb8
CD		 17552002-02-11 Chris Demetriou <cgd@broadcom.com>
1756
1757 * mips.igen: Add some additional comments about supported
1758 models, and about which instructions go where.
1759 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1760 order as is used in the rest of the file.
1761
9805e229
CD		 17622002-02-11 Chris Demetriou <cgd@broadcom.com>
1763
1764 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1765 indicating that ALU32_END or ALU64_END are there to check
1766 for overflow.
1767 (DADD): Likewise, but also remove previous comment about
1768 overflow checking.
1769
f701dad2
CD		 17702002-02-10 Chris Demetriou <cgd@broadcom.com>
1771
1772 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1773 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1774 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1775 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1776 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1777 fields (i.e., add and move commas) so that they more closely
1778 match the MIPS ISA documentation opcode partitioning.
1779
17802002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098 1781
72f4393d
L		 1782 * mips.igen (ADDI): Print immediate value.
1783 (BREAK): Print code.
1784 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1785 (SLL): Print "nop" specially, and don't run the code
1786 that does the shift for the "nop" case.
20ae0098 1787
9e52972e
FF		 17882001-11-17 Fred Fish <fnf@redhat.com>
1789
1790 * sim-main.h (float_operation): Move enum declaration outside
1791 of _sim_cpu struct declaration.
1792
c0efbca4
JB		 17932001-04-12 Jim Blandy <jimb@redhat.com>
1794
1795 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1796 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1797 set of the FCSR.
1798 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1799 PENDING_FILL, and you can get the intended effect gracefully by
1800 calling PENDING_SCHED directly.
1801
fb891446
BE		 18022001-02-23 Ben Elliston <bje@redhat.com>
1803
1804 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1805 already defined elsewhere.
1806
8030f857
BE		 18072001-02-19 Ben Elliston <bje@redhat.com>
1808
1809 * sim-main.h (sim_monitor): Return an int.
1810 * interp.c (sim_monitor): Add return values.
1811 (signal_exception): Handle error conditions from sim_monitor.
1812
56b48a7a
CD		 18132001-02-08 Ben Elliston <bje@redhat.com>
1814
1815 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1816 (store_memory): Likewise, pass cia to sim_core_write*.
1817
d3ee60d9
FCE		 18182000-10-19 Frank Ch. Eigler <fche@redhat.com>
1819
1820 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1821 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1822
071da002
AC		 1823Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1824
1825 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1826 * Makefile.in: Don't delete *.igen when cleaning directory.
1827
a28c02cd
AC		 1828Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1829
1830 * m16.igen (break): Call SignalException not sim_engine_halt.
1831
80ee11fa
AC		 1832Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1833
1834 From Jason Eckhardt:
1835 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1836
673388c0
AC		 1837Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1838
1839 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1840
4c0deff4
NC		 18412000-05-24 Michael Hayes <mhayes@cygnus.com>
1842
1843 * mips.igen (do_dmultx): Fix typo.
1844
eb2d80b4
AC		 1845Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1846
1847 * configure: Regenerated to track ../common/aclocal.m4 changes.
1848
dd37a34b
AC		 1849Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1850
1851 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1852
4c0deff4
NC		 18532000-04-12 Frank Ch. Eigler <fche@redhat.com>
1854
1855 * sim-main.h (GPR_CLEAR): Define macro.
1856
e30db738
AC		 1857Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1858
1859 * interp.c (decode_coproc): Output long using %lx and not %s.
1860
cb7450ea
FCE		 18612000-03-21 Frank Ch. Eigler <fche@redhat.com>
1862
1863 * interp.c (sim_open): Sort & extend dummy memory regions for
1864 --board=jmr3904 for eCos.
1865
a3027dd7
FCE		 18662000-03-02 Frank Ch. Eigler <fche@redhat.com>
1867
1868 * configure: Regenerated.
1869
1870Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1871
1872 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1873 calls, conditional on the simulator being in verbose mode.
1874
dfcd3bfb
JM		 1875Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1876
1877 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1878 cache don't get ReservedInstruction traps.
1879
c2d11a7d
JM		 18801999-11-29 Mark Salter <msalter@cygnus.com>
1881
1882 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1883 to clear status bits in sdisr register. This is how the hardware works.
1884
1885 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1886 being used by cygmon.
1887
4ce44c66
JM		 18881999-11-11 Andrew Haley <aph@cygnus.com>
1889
1890 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1891 instructions.
1892
cff3e48b
JM		 1893Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1894
1895 * mips.igen (MULT): Correct previous mis-applied patch.
1896
d4f3574e
SS		 1897Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1898
1899 * mips.igen (delayslot32): Handle sequence like
1900 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1901 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1902 (MULT): Actually pass the third register...
1903
19041999-09-03 Mark Salter <msalter@cygnus.com>
1905
1906 * interp.c (sim_open): Added more memory aliases for additional
1907 hardware being touched by cygmon on jmr3904 board.
1908
1909Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1910
1911 * configure: Regenerated to track ../common/aclocal.m4 changes.
1912
a0b3c4fd
JM		 1913Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1914
1915 * interp.c (sim_store_register): Handle case where client - GDB -
1916 specifies that a 4 byte register is 8 bytes in size.
1917 (sim_fetch_register): Ditto.
72f4393d 1918
adf40b2e
JM		 19191999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1920
1921 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1922 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1923 (idt_monitor_base): Base address for IDT monitor traps.
1924 (pmon_monitor_base): Ditto for PMON.
1925 (lsipmon_monitor_base): Ditto for LSI PMON.
1926 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1927 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1928 (sim_firmware_command): New function.
1929 (mips_option_handler): Call it for OPTION_FIRMWARE.
1930 (sim_open): Allocate memory for idt_monitor region. If "--board"
1931 option was given, add no monitor by default. Add BREAK hooks only if
1932 monitors are also there.
72f4393d 1933
43e526b9
JM		 1934Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1935
1936 * interp.c (sim_monitor): Flush output before reading input.
1937
1938Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1939
1940 * tconfig.in (SIM_HANDLES_LMA): Always define.
1941
1942Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1943
1944 From Mark Salter <msalter@cygnus.com>:
1945 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1946 (sim_open): Add setup for BSP board.
1947
9846de1b
JM		 1948Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1949
1950 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1951 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1952 them as unimplemented.
1953
cd0fc7c3
SS		 19541999-05-08 Felix Lee <flee@cygnus.com>
1955
1956 * configure: Regenerated to track ../common/aclocal.m4 changes.
72f4393d 1957
7a292a7a
SS		 19581999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1959
1960 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1961
1962Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1963
1964 * configure.in: Any mips64vr5*-*-* target should have
1965 -DTARGET_ENABLE_FR=1.
1966 (default_endian): Any mips64vr*el-*-* target should default to
1967 LITTLE_ENDIAN.
1968 * configure: Re-generate.
1969
19701999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1971
1972 * mips.igen (ldl): Extend from _16_, not 32.
1973
1974Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1975
1976 * interp.c (sim_store_register): Force registers written to by GDB
1977 into an un-interpreted state.
1978
c906108c
SS		 19791999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1980
1981 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1982 CPU, start periodic background I/O polls.
72f4393d 1983 (tx3904sio_poll): New function: periodic I/O poller.
c906108c
SS		 1984
19851998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1986
1987 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
72f4393d 1988
c906108c
SS		 1989Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1990
1991 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1992 case statement.
1993
19941998-12-29 Frank Ch. Eigler <fche@cygnus.com>
72f4393d
L		 1995
1996 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
c906108c
SS		 1997 (load_word): Call SIM_CORE_SIGNAL hook on error.
1998 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1999 starting. For exception dispatching, pass PC instead of NULL_CIA.
2000 (decode_coproc): Use COP0_BADVADDR to store faulting address.
72f4393d 2001 * sim-main.h (COP0_BADVADDR): Define.
c906108c
SS		 2002 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
2003 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
72f4393d 2004 (_sim_cpu): Add exc_* fields to store register value snapshots.
c906108c
SS		 2005 * mips.igen (*): Replace memory-related SignalException* calls
2006 with references to SIM_CORE_SIGNAL hook.
72f4393d 2007
c906108c
SS		 2008 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
2009 fix.
2010 * sim-main.c (*): Minor warning cleanups.
72f4393d 2011
c906108c
SS		 20121998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
2013
2014 * m16.igen (DADDIU5): Correct type-o.
2015
2016Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
2017
2018 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
2019 variables.
2020
2021Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
2022
2023 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
2024 to include path.
2025 (interp.o): Add dependency on itable.h
2026 (oengine.c, gencode): Delete remaining references.
2027 (BUILT_SRC_FROM_GEN): Clean up.
72f4393d 2028
c906108c 20291998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
72f4393d 2030
c906108c
SS		 2031 * vr4run.c: New.
2032 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
2033 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
2034 tmp-run-hack) : New.
2035 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
72f4393d 2036 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
c906108c
SS		 2037 Drop the "64" qualifier to get the HACK generator working.
2038 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
2039 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
2040 qualifier to get the hack generator working.
2041 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
2042 (DSLL): Use do_dsll.
2043 (DSLLV): Use do_dsllv.
2044 (DSRA): Use do_dsra.
2045 (DSRL): Use do_dsrl.
2046 (DSRLV): Use do_dsrlv.
2047 (BC1): Move *vr4100 to get the HACK generator working.
72f4393d 2048 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
c906108c
SS		 2049 get the HACK generator working.
2050 (MACC) Rename to get the HACK generator working.
2051 (DMACC,MACCS,DMACCS): Add the 64.
72f4393d 2052
c906108c
SS		 20531998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
2054
2055 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
2056 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
72f4393d 2057
c906108c
SS		 20581998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
2059
2060 * mips/interp.c (DEBUG): Cleanups.
2061
20621998-12-10 Frank Ch. Eigler <fche@cygnus.com>
2063
2064 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
2065 (tx3904sio_tickle): fflush after a stdout character output.
72f4393d 2066
c906108c
SS		 20671998-12-03 Frank Ch. Eigler <fche@cygnus.com>
2068
2069 * interp.c (sim_close): Uninstall modules.
2070
2071Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
2072
2073 * sim-main.h, interp.c (sim_monitor): Change to global
2074 function.
2075
2076Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2077
2078 * configure.in (vr4100): Only include vr4100 instructions in
2079 simulator.
2080 * configure: Re-generate.
2081 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
2082
2083Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
2084
2085 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
2086 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
2087 true alternative.
2088
2089 * configure.in (sim_default_gen, sim_use_gen): Replace with
2090 sim_gen.
2091 (--enable-sim-igen): Delete config option. Always using IGEN.
2092 * configure: Re-generate.
72f4393d 2093
c906108c
SS		 2094 * Makefile.in (gencode): Kill, kill, kill.
2095 * gencode.c: Ditto.
72f4393d 2096
c906108c
SS		 2097Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
2098
2099 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
2100 bit mips16 igen simulator.
2101 * configure: Re-generate.
2102
2103 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
2104 as part of vr4100 ISA.
2105 * vr.igen: Mark all instructions as 64 bit only.
2106
2107Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2108
2109 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
2110 Pacify GCC.
2111
2112Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
2113
2114 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
2115 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
2116 * configure: Re-generate.
2117
2118 * m16.igen (BREAK): Define breakpoint instruction.
2119 (JALX32): Mark instruction as mips16 and not r3900.
2120 * mips.igen (C.cond.fmt): Fix typo in instruction format.
2121
2122 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
2123
2124Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
2125
2126 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
2127 insn as a debug breakpoint.
2128
2129 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
2130 pending.slot_size.
2131 (PENDING_SCHED): Clean up trace statement.
2132 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
2133 (PENDING_FILL): Delay write by only one cycle.
2134 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
2135
2136 * sim-main.c (pending_tick): Clean up trace statements. Add trace
2137 of pending writes.
2138 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
2139 32 & 64.
2140 (pending_tick): Move incrementing of index to FOR statement.
2141 (pending_tick): Only update PENDING_OUT after a write has occured.
72f4393d 2142
c906108c
SS		 2143 * configure.in: Add explicit mips-lsi-* target. Use gencode to
2144 build simulator.
2145 * configure: Re-generate.
72f4393d 2146
c906108c
SS		 2147 * interp.c (sim_engine_run OLD): Delete explicit call to
2148 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
72f4393d 2149
c906108c
SS		 2150Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
2151
2152 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
2153 interrupt level number to match changed SignalExceptionInterrupt
2154 macro.
2155
2156Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
2157
2158 * interp.c: #include "itable.h" if WITH_IGEN.
2159 (get_insn_name): New function.
2160 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
2161 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
2162
2163Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
2164
2165 * configure: Rebuilt to inhale new common/aclocal.m4.
2166
2167Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
2168
2169 * dv-tx3904sio.c: Include sim-assert.h.
2170
2171Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
2172
2173 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
2174 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
2175 Reorganize target-specific sim-hardware checks.
2176 * configure: rebuilt.
2177 * interp.c (sim_open): For tx39 target boards, set
2178 OPERATING_ENVIRONMENT, add tx3904sio devices.
2179 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
2180 ROM executables. Install dv-sockser into sim-modules list.
72f4393d 2181
c906108c
SS		 2182 * dv-tx3904irc.c: Compiler warning clean-up.
2183 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
2184 frequent hw-trace messages.
2185
2186Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
2187
2188 * vr.igen (MulAcc): Identify as a vr4100 specific function.
2189
2190Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2191
2192 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
2193
2194 * vr.igen: New file.
2195 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
2196 * mips.igen: Define vr4100 model. Include vr.igen.
2197Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
2198
2199 * mips.igen (check_mf_hilo): Correct check.
2200
2201Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2202
2203 * sim-main.h (interrupt_event): Add prototype.
2204
2205 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
2206 register_ptr, register_value.
2207 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
2208
2209 * sim-main.h (tracefh): Make extern.
2210
2211Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
2212
2213 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
72f4393d 2214 Reduce unnecessarily high timer event frequency.
c906108c 2215 * dv-tx3904cpu.c: Ditto for interrupt event.
72f4393d 2216
c906108c
SS		 2217Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
2218
2219 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
2220 to allay warnings.
2221 (interrupt_event): Made non-static.
72f4393d 2222
c906108c
SS		 2223 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
2224 interchange of configuration values for external vs. internal
2225 clock dividers.
72f4393d 2226
c906108c
SS		 2227Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
2228
72f4393d 2229 * mips.igen (BREAK): Moved code to here for
c906108c
SS		 2230 simulator-reserved break instructions.
2231 * gencode.c (build_instruction): Ditto.
2232 * interp.c (signal_exception): Code moved from here. Non-
72f4393d 2233 reserved instructions now use exception vector, rather
c906108c
SS		 2234 than halting sim.
2235 * sim-main.h: Moved magic constants to here.
2236
2237Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
2238
2239 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
2240 register upon non-zero interrupt event level, clear upon zero
2241 event value.
2242 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
2243 by passing zero event value.
2244 (*_io_{read,write}_buffer): Endianness fixes.
2245 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
2246 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
2247
2248 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
2249 serial I/O and timer module at base address 0xFFFF0000.
72f4393d 2250
c906108c
SS		 2251Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
2252
72f4393d 2253 * mips.igen (SWC1) : Correct the handling of ReverseEndian
c906108c
SS		 2254 and BigEndianCPU.
2255
2256Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
2257
2258 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
2259 parts.
2260 * configure: Update.
2261
2262Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
2263
2264 * dv-tx3904tmr.c: New file - implements tx3904 timer.
2265 * dv-tx3904{irc,cpu}.c: Mild reformatting.
2266 * configure.in: Include tx3904tmr in hw_device list.
2267 * configure: Rebuilt.
2268 * interp.c (sim_open): Instantiate three timer instances.
2269 Fix address typo of tx3904irc instance.
2270
2271Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
2272
2273 * interp.c (signal_exception): SystemCall exception now uses
2274 the exception vector.
2275
2276Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
2277
2278 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
2279 to allay warnings.
2280
2281Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2282
2283 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
2284
2285Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
2286
2287 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
2288
2289 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
2290 sim-main.h. Declare a struct hw_descriptor instead of struct
2291 hw_device_descriptor.
2292
2293Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
2294
2295 * mips.igen (do_store_left, do_load_left): Compute nr of left and
2296 right bits and then re-align left hand bytes to correct byte
2297 lanes. Fix incorrect computation in do_store_left when loading
2298 bytes from second word.
2299
2300Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2301
2302 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
2303 * interp.c (sim_open): Only create a device tree when HW is
2304 enabled.
2305
2306 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
2307 * interp.c (signal_exception): Ditto.
2308
2309Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
2310
2311 * gencode.c: Mark BEGEZALL as LIKELY.
2312
2313Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
2314
2315 * sim-main.h (ALU32_END): Sign extend 32 bit results.
2316 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
72f4393d 2317
c906108c
SS		 2318Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
2319
2320 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
2321 modules. Recognize TX39 target with "mips*tx39" pattern.
2322 * configure: Rebuilt.
2323 * sim-main.h (*): Added many macros defining bits in
2324 TX39 control registers.
2325 (SignalInterrupt): Send actual PC instead of NULL.
2326 (SignalNMIReset): New exception type.
2327 * interp.c (board): New variable for future use to identify
2328 a particular board being simulated.
2329 (mips_option_handler,mips_options): Added "--board" option.
2330 (interrupt_event): Send actual PC.
2331 (sim_open): Make memory layout conditional on board setting.
2332 (signal_exception): Initial implementation of hardware interrupt
2333 handling. Accept another break instruction variant for simulator
2334 exit.
2335 (decode_coproc): Implement RFE instruction for TX39.
2336 (mips.igen): Decode RFE instruction as such.
2337 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
2338 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
2339 bbegin to implement memory map.
2340 * dv-tx3904cpu.c: New file.
2341 * dv-tx3904irc.c: New file.
2342
2343Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
2344
2345 * mips.igen (check_mt_hilo): Create a separate r3900 version.
2346
2347Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
2348
2349 * tx.igen (madd,maddu): Replace calls to check_op_hilo
2350 with calls to check_div_hilo.
2351
2352Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
2353
2354 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
2355 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
72f4393d 2356 Add special r3900 version of do_mult_hilo.
c906108c
SS		 2357 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
2358 with calls to check_mult_hilo.
2359 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
2360 with calls to check_div_hilo.
2361
2362Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
2363
2364 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
2365 Document a replacement.
2366
2367Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
2368
2369 * interp.c (sim_monitor): Make mon_printf work.
2370
2371Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
2372
2373 * sim-main.h (INSN_NAME): New arg `cpu'.
2374
2375Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
2376
72f4393d 2377 * configure: Regenerated to track ../common/aclocal.m4 changes.
c906108c
SS		 2378
2379Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
2380
2381 * configure: Regenerated to track ../common/aclocal.m4 changes.
2382 * config.in: Ditto.
2383
2384Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
2385
2386 * acconfig.h: New file.
2387 * configure.in: Reverted change of Apr 24; use sinclude again.
2388
2389Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
2390
2391 * configure: Regenerated to track ../common/aclocal.m4 changes.
2392 * config.in: Ditto.
2393
2394Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
2395
2396 * configure.in: Don't call sinclude.
2397
2398Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
2399
2400 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
2401
2402Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2403
2404 * mips.igen (ERET): Implement.
2405
2406 * interp.c (decode_coproc): Return sign-extended EPC.
2407
2408 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
2409
2410 * interp.c (signal_exception): Do not ignore Trap.
2411 (signal_exception): On TRAP, restart at exception address.
2412 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
2413 (signal_exception): Update.
2414 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
2415 so that TRAP instructions are caught.
2416
2417Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
2418
2419 * sim-main.h (struct hilo_access, struct hilo_history): Define,
2420 contains HI/LO access history.
2421 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
2422 (HIACCESS, LOACCESS): Delete, replace with
2423 (HIHISTORY, LOHISTORY): New macros.
2424 (CHECKHILO): Delete all, moved to mips.igen
72f4393d 2425
c906108c
SS		 2426 * gencode.c (build_instruction): Do not generate checks for
2427 correct HI/LO register usage.
2428
2429 * interp.c (old_engine_run): Delete checks for correct HI/LO
2430 register usage.
2431
2432 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
2433 check_mf_cycles): New functions.
2434 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
2435 do_divu, domultx, do_mult, do_multu): Use.
2436
2437 * tx.igen ("madd", "maddu"): Use.
72f4393d 2438
c906108c
SS		 2439Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
2440
2441 * mips.igen (DSRAV): Use function do_dsrav.
2442 (SRAV): Use new function do_srav.
2443
2444 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
2445 (B): Sign extend 11 bit immediate.
2446 (EXT-B*): Shift 16 bit immediate left by 1.
2447 (ADDIU*): Don't sign extend immediate value.
2448
2449Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2450
2451 * m16run.c (sim_engine_run): Restore CIA after handling an event.
2452
2453 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
2454 functions.
2455
2456 * mips.igen (delayslot32, nullify_next_insn): New functions.
2457 (m16.igen): Always include.
2458 (do_*): Add more tracing.
2459
2460 * m16.igen (delayslot16): Add NIA argument, could be called by a
2461 32 bit MIPS16 instruction.
72f4393d 2462
c906108c
SS		 2463 * interp.c (ifetch16): Move function from here.
2464 * sim-main.c (ifetch16): To here.
72f4393d 2465
c906108c
SS		 2466 * sim-main.c (ifetch16, ifetch32): Update to match current
2467 implementations of LH, LW.
2468 (signal_exception): Don't print out incorrect hex value of illegal
2469 instruction.
2470
2471Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2472
2473 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
2474 instruction.
2475
2476 * m16.igen: Implement MIPS16 instructions.
72f4393d 2477
c906108c
SS		 2478 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
2479 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
2480 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
2481 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
2482 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
2483 bodies of corresponding code from 32 bit insn to these. Also used
2484 by MIPS16 versions of functions.
72f4393d 2485
c906108c
SS		 2486 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
2487 (IMEM16): Drop NR argument from macro.
2488
2489Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2490
2491 * Makefile.in (SIM_OBJS): Add sim-main.o.
2492
2493 * sim-main.h (address_translation, load_memory, store_memory,
2494 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
2495 as INLINE_SIM_MAIN.
2496 (pr_addr, pr_uword64): Declare.
2497 (sim-main.c): Include when H_REVEALS_MODULE_P.
72f4393d 2498
c906108c
SS		 2499 * interp.c (address_translation, load_memory, store_memory,
2500 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
2501 from here.
2502 * sim-main.c: To here. Fix compilation problems.
72f4393d 2503
c906108c
SS		 2504 * configure.in: Enable inlining.
2505 * configure: Re-config.
2506
2507Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2508
2509 * configure: Regenerated to track ../common/aclocal.m4 changes.
2510
2511Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2512
2513 * mips.igen: Include tx.igen.
2514 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
2515 * tx.igen: New file, contains MADD and MADDU.
2516
2517 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
2518 the hardwired constant `7'.
2519 (store_memory): Ditto.
2520 (LOADDRMASK): Move definition to sim-main.h.
2521
2522 mips.igen (MTC0): Enable for r3900.
2523 (ADDU): Add trace.
2524
2525 mips.igen (do_load_byte): Delete.
2526 (do_load, do_store, do_load_left, do_load_write, do_store_left,
2527 do_store_right): New functions.
2528 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
2529
2530 configure.in: Let the tx39 use igen again.
2531 configure: Update.
72f4393d 2532
c906108c
SS		 2533Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2534
2535 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
2536 not an address sized quantity. Return zero for cache sizes.
2537
2538Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
2539
2540 * mips.igen (r3900): r3900 does not support 64 bit integer
2541 operations.
2542
2543Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
2544
2545 * configure.in (mipstx39*-*-*): Use gencode simulator rather
2546 than igen one.
2547 * configure : Rebuild.
72f4393d 2548
c906108c
SS		 2549Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
2550
2551 * configure: Regenerated to track ../common/aclocal.m4 changes.
2552
2553Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2554
2555 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
2556
2557Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
2558
2559 * configure: Regenerated to track ../common/aclocal.m4 changes.
2560 * config.in: Regenerated to track ../common/aclocal.m4 changes.
2561
2562Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2563
2564 * configure: Regenerated to track ../common/aclocal.m4 changes.
2565
2566Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
2567
2568 * interp.c (Max, Min): Comment out functions. Not yet used.
2569
2570Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
2571
2572 * configure: Regenerated to track ../common/aclocal.m4 changes.
2573
2574Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
2575
2576 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
2577 configurable settings for stand-alone simulator.
72f4393d 2578
c906108c 2579 * configure.in: Added X11 search, just in case.
72f4393d 2580
c906108c
SS		 2581 * configure: Regenerated.
2582
2583Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
2584
2585 * interp.c (sim_write, sim_read, load_memory, store_memory):
2586 Replace sim_core_*_map with read_map, write_map, exec_map resp.
2587
2588Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
2589
2590 * sim-main.h (GETFCC): Return an unsigned value.
2591
2592Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2593
2594 * mips.igen (DIV): Fix check for -1 / MIN_INT.
2595 (DADD): Result destination is RD not RT.
2596
2597Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2598
2599 * sim-main.h (HIACCESS, LOACCESS): Always define.
2600
2601 * mdmx.igen (Maxi, Mini): Rename Max, Min.
2602
2603 * interp.c (sim_info): Delete.
2604
2605Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
2606
2607 * interp.c (DECLARE_OPTION_HANDLER): Use it.
2608 (mips_option_handler): New argument `cpu'.
2609 (sim_open): Update call to sim_add_option_table.
2610
2611Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
2612
2613 * mips.igen (CxC1): Add tracing.
2614
2615Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
2616
2617 * sim-main.h (Max, Min): Declare.
2618
2619 * interp.c (Max, Min): New functions.
2620
2621 * mips.igen (BC1): Add tracing.
72f4393d 2622
c906108c 2623Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
72f4393d 2624
c906108c 2625 * interp.c Added memory map for stack in vr4100
72f4393d 2626
c906108c
SS		 2627Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
2628
2629 * interp.c (load_memory): Add missing "break"'s.
2630
2631Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2632
2633 * interp.c (sim_store_register, sim_fetch_register): Pass in
2634 length parameter. Return -1.
2635
2636Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
2637
2638 * interp.c: Added hardware init hook, fixed warnings.
2639
2640Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2641
2642 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
2643
2644Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
2645
2646 * interp.c (ifetch16): New function.
2647
2648 * sim-main.h (IMEM32): Rename IMEM.
2649 (IMEM16_IMMED): Define.
2650 (IMEM16): Define.
2651 (DELAY_SLOT): Update.
72f4393d 2652
c906108c 2653 * m16run.c (sim_engine_run): New file.
72f4393d 2654
c906108c
SS		 2655 * m16.igen: All instructions except LB.
2656 (LB): Call do_load_byte.
2657 * mips.igen (do_load_byte): New function.
2658 (LB): Call do_load_byte.
2659
2660 * mips.igen: Move spec for insn bit size and high bit from here.
2661 * Makefile.in (tmp-igen, tmp-m16): To here.
2662
2663 * m16.dc: New file, decode mips16 instructions.
2664
2665 * Makefile.in (SIM_NO_ALL): Define.
2666 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
2667
2668Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
2669
2670 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
2671 point unit to 32 bit registers.
2672 * configure: Re-generate.
2673
2674Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2675
2676 * configure.in (sim_use_gen): Make IGEN the default simulator
2677 generator for generic 32 and 64 bit mips targets.
2678 * configure: Re-generate.
2679
2680Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2681
2682 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
2683 bitsize.
2684
2685 * interp.c (sim_fetch_register, sim_store_register): Read/write
2686 FGR from correct location.
2687 (sim_open): Set size of FGR's according to
2688 WITH_TARGET_FLOATING_POINT_BITSIZE.
72f4393d 2689
c906108c
SS		 2690 * sim-main.h (FGR): Store floating point registers in a separate
2691 array.
2692
2693Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
2694
2695 * configure: Regenerated to track ../common/aclocal.m4 changes.
2696
2697Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2698
2699 * interp.c (ColdReset): Call PENDING_INVALIDATE.
2700
2701 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
2702
2703 * interp.c (pending_tick): New function. Deliver pending writes.
2704
2705 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2706 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2707 it can handle mixed sized quantites and single bits.
72f4393d 2708
c906108c
SS		 2709Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2710
2711 * interp.c (oengine.h): Do not include when building with IGEN.
2712 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2713 (sim_info): Ditto for PROCESSOR_64BIT.
2714 (sim_monitor): Replace ut_reg with unsigned_word.
2715 (*): Ditto for t_reg.
2716 (LOADDRMASK): Define.
2717 (sim_open): Remove defunct check that host FP is IEEE compliant,
2718 using software to emulate floating point.
2719 (value_fpr, ...): Always compile, was conditional on HASFPU.
2720
2721Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2722
2723 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2724 size.
2725
2726 * interp.c (SD, CPU): Define.
2727 (mips_option_handler): Set flags in each CPU.
2728 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2729 (sim_close): Do not clear STATE, deleted anyway.
2730 (sim_write, sim_read): Assume CPU zero's vm should be used for
2731 data transfers.
2732 (sim_create_inferior): Set the PC for all processors.
2733 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2734 argument.
2735 (mips16_entry): Pass correct nr of args to store_word, load_word.
2736 (ColdReset): Cold reset all cpu's.
2737 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2738 (sim_monitor, load_memory, store_memory, signal_exception): Use
2739 `CPU' instead of STATE_CPU.
2740
2741
2742 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2743 SD or CPU_.
72f4393d 2744
c906108c
SS		 2745 * sim-main.h (signal_exception): Add sim_cpu arg.
2746 (SignalException*): Pass both SD and CPU to signal_exception.
2747 * interp.c (signal_exception): Update.
72f4393d 2748
c906108c
SS		 2749 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2750 Ditto
2751 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2752 address_translation): Ditto
2753 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
72f4393d 2754
c906108c
SS		 2755Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2756
2757 * configure: Regenerated to track ../common/aclocal.m4 changes.
2758
2759Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2760
2761 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2762
72f4393d 2763 * mips.igen (model): Map processor names onto BFD name.
c906108c
SS		 2764
2765 * sim-main.h (CPU_CIA): Delete.
2766 (SET_CIA, GET_CIA): Define
2767
2768Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2769
2770 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2771 regiser.
2772
2773 * configure.in (default_endian): Configure a big-endian simulator
2774 by default.
2775 * configure: Re-generate.
72f4393d 2776
c906108c
SS		 2777Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2778
2779 * configure: Regenerated to track ../common/aclocal.m4 changes.
2780
2781Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2782
2783 * interp.c (sim_monitor): Handle Densan monitor outbyte
2784 and inbyte functions.
2785
27861997-12-29 Felix Lee <flee@cygnus.com>
2787
2788 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2789
2790Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2791
2792 * Makefile.in (tmp-igen): Arrange for $zero to always be
2793 reset to zero after every instruction.
2794
2795Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2796
2797 * configure: Regenerated to track ../common/aclocal.m4 changes.
2798 * config.in: Ditto.
2799
2800Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2801
2802 * mips.igen (MSUB): Fix to work like MADD.
2803 * gencode.c (MSUB): Similarly.
2804
2805Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2806
2807 * configure: Regenerated to track ../common/aclocal.m4 changes.
2808
2809Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2810
2811 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2812
2813Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2814
2815 * sim-main.h (sim-fpu.h): Include.
2816
2817 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2818 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2819 using host independant sim_fpu module.
2820
2821Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2822
2823 * interp.c (signal_exception): Report internal errors with SIGABRT
2824 not SIGQUIT.
2825
2826 * sim-main.h (C0_CONFIG): New register.
2827 (signal.h): No longer include.
2828
2829 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2830
2831Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2832
2833 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2834
2835Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2836
2837 * mips.igen: Tag vr5000 instructions.
2838 (ANDI): Was missing mipsIV model, fix assembler syntax.
2839 (do_c_cond_fmt): New function.
2840 (C.cond.fmt): Handle mips I-III which do not support CC field
2841 separatly.
2842 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2843 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2844 in IV3.2 spec.
2845 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2846 vr5000 which saves LO in a GPR separatly.
72f4393d 2847
c906108c
SS		 2848 * configure.in (enable-sim-igen): For vr5000, select vr5000
2849 specific instructions.
2850 * configure: Re-generate.
72f4393d 2851
c906108c
SS		 2852Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2853
2854 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2855
2856 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2857 fmt_uninterpreted_64 bit cases to switch. Convert to
2858 fmt_formatted,
2859
2860 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2861
2862 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2863 as specified in IV3.2 spec.
2864 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2865
2866Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2867
2868 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2869 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2870 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2871 PENDING_FILL versions of instructions. Simplify.
2872 (X): New function.
2873 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2874 instructions.
2875 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2876 a signed value.
2877 (MTHI, MFHI): Disable code checking HI-LO.
72f4393d 2878
c906108c
SS		 2879 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2880 global.
2881 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2882
2883Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2884
2885 * gencode.c (build_mips16_operands): Replace IPC with cia.
2886
2887 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2888 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2889 IPC to `cia'.
2890 (UndefinedResult): Replace function with macro/function
2891 combination.
2892 (sim_engine_run): Don't save PC in IPC.
2893
2894 * sim-main.h (IPC): Delete.
2895
2896
2897 * interp.c (signal_exception, store_word, load_word,
2898 address_translation, load_memory, store_memory, cache_op,
2899 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2900 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2901 current instruction address - cia - argument.
2902 (sim_read, sim_write): Call address_translation directly.
2903 (sim_engine_run): Rename variable vaddr to cia.
2904 (signal_exception): Pass cia to sim_monitor
72f4393d 2905
c906108c
SS		 2906 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2907 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2908 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2909
2910 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2911 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2912 SIM_ASSERT.
72f4393d 2913
c906108c
SS		 2914 * interp.c (signal_exception): Pass restart address to
2915 sim_engine_restart.
2916
2917 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2918 idecode.o): Add dependency.
2919
2920 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2921 Delete definitions
2922 (DELAY_SLOT): Update NIA not PC with branch address.
2923 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2924
2925 * mips.igen: Use CIA not PC in branch calculations.
2926 (illegal): Call SignalException.
2927 (BEQ, ADDIU): Fix assembler.
2928
2929Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2930
2931 * m16.igen (JALX): Was missing.
2932
2933 * configure.in (enable-sim-igen): New configuration option.
2934 * configure: Re-generate.
72f4393d 2935
c906108c
SS		 2936 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2937
2938 * interp.c (load_memory, store_memory): Delete parameter RAW.
2939 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2940 bypassing {load,store}_memory.
2941
2942 * sim-main.h (ByteSwapMem): Delete definition.
2943
2944 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2945
2946 * interp.c (sim_do_command, sim_commands): Delete mips specific
2947 commands. Handled by module sim-options.
72f4393d 2948
c906108c
SS		 2949 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2950 (WITH_MODULO_MEMORY): Define.
2951
2952 * interp.c (sim_info): Delete code printing memory size.
2953
2954 * interp.c (mips_size): Nee sim_size, delete function.
2955 (power2): Delete.
2956 (monitor, monitor_base, monitor_size): Delete global variables.
2957 (sim_open, sim_close): Delete code creating monitor and other
2958 memory regions. Use sim-memopts module, via sim_do_commandf, to
2959 manage memory regions.
2960 (load_memory, store_memory): Use sim-core for memory model.
72f4393d 2961
c906108c
SS		 2962 * interp.c (address_translation): Delete all memory map code
2963 except line forcing 32 bit addresses.
2964
2965Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2966
2967 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2968 trace options.
2969
2970 * interp.c (logfh, logfile): Delete globals.
2971 (sim_open, sim_close): Delete code opening & closing log file.
2972 (mips_option_handler): Delete -l and -n options.
2973 (OPTION mips_options): Ditto.
2974
2975 * interp.c (OPTION mips_options): Rename option trace to dinero.
2976 (mips_option_handler): Update.
2977
2978Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2979
2980 * interp.c (fetch_str): New function.
2981 (sim_monitor): Rewrite using sim_read & sim_write.
2982 (sim_open): Check magic number.
2983 (sim_open): Write monitor vectors into memory using sim_write.
2984 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2985 (sim_read, sim_write): Simplify - transfer data one byte at a
2986 time.
2987 (load_memory, store_memory): Clarify meaning of parameter RAW.
2988
2989 * sim-main.h (isHOST): Defete definition.
2990 (isTARGET): Mark as depreciated.
2991 (address_translation): Delete parameter HOST.
2992
2993 * interp.c (address_translation): Delete parameter HOST.
2994
2995Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2996
72f4393d 2997 * mips.igen:
c906108c
SS		 2998
2999 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
3000 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
3001
3002Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
3003
3004 * mips.igen: Add model filter field to records.
3005
3006Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
3007
3008 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
72f4393d 3009
c906108c
SS		 3010 interp.c (sim_engine_run): Do not compile function sim_engine_run
3011 when WITH_IGEN == 1.
3012
3013 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
3014 target architecture.
3015
3016 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
3017 igen. Replace with configuration variables sim_igen_flags /
3018 sim_m16_flags.
3019
3020 * m16.igen: New file. Copy mips16 insns here.
3021 * mips.igen: From here.
3022
3023Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
3024
3025 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
3026 to top.
3027 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
3028
3029Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
3030
3031 * gencode.c (build_instruction): Follow sim_write's lead in using
3032 BigEndianMem instead of !ByteSwapMem.
3033
3034Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
3035
3036 * configure.in (sim_gen): Dependent on target, select type of
3037 generator. Always select old style generator.
3038
3039 configure: Re-generate.
3040
3041 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
3042 targets.
3043 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
3044 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
3045 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
3046 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
3047 SIM_@sim_gen@_*, set by autoconf.
72f4393d 3048
c906108c
SS		 3049Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
3050
3051 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
3052
3053 * interp.c (ColdReset): Remove #ifdef HASFPU, check
3054 CURRENT_FLOATING_POINT instead.
3055
3056 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
3057 (address_translation): Raise exception InstructionFetch when
3058 translation fails and isINSTRUCTION.
72f4393d 3059
c906108c
SS		 3060 * interp.c (sim_open, sim_write, sim_monitor, store_word,
3061 sim_engine_run): Change type of of vaddr and paddr to
3062 address_word.
3063 (address_translation, prefetch, load_memory, store_memory,
3064 cache_op): Change type of vAddr and pAddr to address_word.
3065
3066 * gencode.c (build_instruction): Change type of vaddr and paddr to
3067 address_word.
3068
3069Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
3070
3071 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
3072 macro to obtain result of ALU op.
3073
3074Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
3075
3076 * interp.c (sim_info): Call profile_print.
3077
3078Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3079
3080 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
3081
3082 * sim-main.h (WITH_PROFILE): Do not define, defined in
3083 common/sim-config.h. Use sim-profile module.
3084 (simPROFILE): Delete defintion.
3085
3086 * interp.c (PROFILE): Delete definition.
3087 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
3088 (sim_close): Delete code writing profile histogram.
3089 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
3090 Delete.
3091 (sim_engine_run): Delete code profiling the PC.
3092
3093Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3094
3095 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
3096
3097 * interp.c (sim_monitor): Make register pointers of type
3098 unsigned_word*.
3099
3100 * sim-main.h: Make registers of type unsigned_word not
3101 signed_word.
3102
3103Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3104
3105 * interp.c (sync_operation): Rename from SyncOperation, make
3106 global, add SD argument.
3107 (prefetch): Rename from Prefetch, make global, add SD argument.
3108 (decode_coproc): Make global.
3109
3110 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
3111
3112 * gencode.c (build_instruction): Generate DecodeCoproc not
3113 decode_coproc calls.
3114
3115 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
3116 (SizeFGR): Move to sim-main.h
3117 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
3118 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
3119 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
3120 sim-main.h.
3121 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
3122 FP_RM_TOMINF, GETRM): Move to sim-main.h.
3123 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
3124 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
3125 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
3126 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
72f4393d 3127
c906108c
SS		 3128 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
3129 exception.
3130 (sim-alu.h): Include.
3131 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
3132 (sim_cia): Typedef to instruction_address.
72f4393d 3133
c906108c
SS		 3134Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
3135
3136 * Makefile.in (interp.o): Rename generated file engine.c to
3137 oengine.c.
72f4393d 3138
c906108c 3139 * interp.c: Update.
72f4393d 3140
c906108c
SS		 3141Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
3142
3143 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
72f4393d 3144
c906108c
SS		 3145Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3146
3147 * gencode.c (build_instruction): For "FPSQRT", output correct
3148 number of arguments to Recip.
72f4393d 3149
c906108c
SS		 3150Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
3151
3152 * Makefile.in (interp.o): Depends on sim-main.h
3153
3154 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
3155
3156 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
3157 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
3158 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
3159 STATE, DSSTATE): Define
3160 (GPR, FGRIDX, ..): Define.
3161
3162 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
3163 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
3164 (GPR, FGRIDX, ...): Delete macros.
72f4393d 3165
c906108c 3166 * interp.c: Update names to match defines from sim-main.h
72f4393d 3167
c906108c
SS		 3168Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
3169
3170 * interp.c (sim_monitor): Add SD argument.
3171 (sim_warning): Delete. Replace calls with calls to
3172 sim_io_eprintf.
3173 (sim_error): Delete. Replace calls with sim_io_error.
3174 (open_trace, writeout32, writeout16, getnum): Add SD argument.
3175 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
3176 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
3177 argument.
3178 (mips_size): Rename from sim_size. Add SD argument.
3179
3180 * interp.c (simulator): Delete global variable.
3181 (callback): Delete global variable.
3182 (mips_option_handler, sim_open, sim_write, sim_read,
3183 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
3184 sim_size,sim_monitor): Use sim_io_* not callback->*.
3185 (sim_open): ZALLOC simulator struct.
3186 (PROFILE): Do not define.
3187
3188Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3189
3190 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
3191 support.h with corresponding code.
3192
3193 * sim-main.h (word64, uword64), support.h: Move definition to
3194 sim-main.h.
3195 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
3196
3197 * support.h: Delete
3198 * Makefile.in: Update dependencies
3199 * interp.c: Do not include.
72f4393d 3200
c906108c
SS		 3201Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3202
3203 * interp.c (address_translation, load_memory, store_memory,
3204 cache_op): Rename to from AddressTranslation et.al., make global,
3205 add SD argument
72f4393d 3206
c906108c
SS		 3207 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
3208 CacheOp): Define.
72f4393d 3209
c906108c
SS		 3210 * interp.c (SignalException): Rename to signal_exception, make
3211 global.
3212
3213 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
72f4393d 3214
c906108c
SS		 3215 * sim-main.h (SignalException, SignalExceptionInterrupt,
3216 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
3217 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
3218 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
3219 Define.
72f4393d 3220
c906108c 3221 * interp.c, support.h: Use.
72f4393d 3222
c906108c
SS		 3223Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3224
3225 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
3226 to value_fpr / store_fpr. Add SD argument.
3227 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
3228 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
3229
3230 * sim-main.h (ValueFPR, StoreFPR): Define.
72f4393d 3231
c906108c
SS		 3232Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
3233
3234 * interp.c (sim_engine_run): Check consistency between configure
3235 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
3236 and HASFPU.
3237
3238 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
72f4393d 3239 (mips_fpu): Configure WITH_FLOATING_POINT.
c906108c
SS		 3240 (mips_endian): Configure WITH_TARGET_ENDIAN.
3241 * configure: Update.
3242
3243Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3244
3245 * configure: Regenerated to track ../common/aclocal.m4 changes.
3246
3247Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
3248
3249 * configure: Regenerated.
3250
3251Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
3252
3253 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
3254
3255Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3256
3257 * gencode.c (print_igen_insn_models): Assume certain architectures
3258 include all mips* instructions.
3259 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
3260 instruction.
3261
3262 * Makefile.in (tmp.igen): Add target. Generate igen input from
3263 gencode file.
3264
3265 * gencode.c (FEATURE_IGEN): Define.
3266 (main): Add --igen option. Generate output in igen format.
3267 (process_instructions): Format output according to igen option.
3268 (print_igen_insn_format): New function.
3269 (print_igen_insn_models): New function.
3270 (process_instructions): Only issue warnings and ignore
3271 instructions when no FEATURE_IGEN.
3272
3273Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3274
3275 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
3276 MIPS targets.
3277
3278Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3279
3280 * configure: Regenerated to track ../common/aclocal.m4 changes.
3281
3282Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
3283
3284 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
3285 SIM_RESERVED_BITS): Delete, moved to common.
3286 (SIM_EXTRA_CFLAGS): Update.
72f4393d 3287
c906108c
SS		 3288Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3289
3290 * configure.in: Configure non-strict memory alignment.
3291 * configure: Regenerated to track ../common/aclocal.m4 changes.
3292
3293Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
3294
3295 * configure: Regenerated to track ../common/aclocal.m4 changes.
3296
3297Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
3298
3299 * gencode.c (SDBBP,DERET): Added (3900) insns.
3300 (RFE): Turn on for 3900.
3301 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
3302 (dsstate): Made global.
3303 (SUBTARGET_R3900): Added.
3304 (CANCELDELAYSLOT): New.
3305 (SignalException): Ignore SystemCall rather than ignore and
3306 terminate. Add DebugBreakPoint handling.
3307 (decode_coproc): New insns RFE, DERET; and new registers Debug
3308 and DEPC protected by SUBTARGET_R3900.
3309 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
3310 bits explicitly.
3311 * Makefile.in,configure.in: Add mips subtarget option.
72f4393d 3312 * configure: Update.
c906108c
SS		 3313
3314Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
3315
3316 * gencode.c: Add r3900 (tx39).
72f4393d 3317
c906108c
SS		 3318
3319Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
3320
3321 * gencode.c (build_instruction): Don't need to subtract 4 for
3322 JALR, just 2.
3323
3324Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
3325
3326 * interp.c: Correct some HASFPU problems.
3327
3328Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
3329
3330 * configure: Regenerated to track ../common/aclocal.m4 changes.
3331
3332Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3333
3334 * interp.c (mips_options): Fix samples option short form, should
3335 be `x'.
3336
3337Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
3338
3339 * interp.c (sim_info): Enable info code. Was just returning.
3340
3341Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3342
3343 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
3344 MFC0.
3345
3346Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
3347
3348 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
3349 constants.
3350 (build_instruction): Ditto for LL.
3351
3352Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
3353
3354 * configure: Regenerated to track ../common/aclocal.m4 changes.
3355
3356Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3357
3358 * configure: Regenerated to track ../common/aclocal.m4 changes.
3359 * config.in: Ditto.
3360
3361Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
3362
3363 * interp.c (sim_open): Add call to sim_analyze_program, update
3364 call to sim_config.
3365
3366Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
3367
3368 * interp.c (sim_kill): Delete.
3369 (sim_create_inferior): Add ABFD argument. Set PC from same.
3370 (sim_load): Move code initializing trap handlers from here.
3371 (sim_open): To here.
3372 (sim_load): Delete, use sim-hload.c.
3373
3374 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
3375
3376Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3377
3378 * configure: Regenerated to track ../common/aclocal.m4 changes.
3379 * config.in: Ditto.
3380
3381Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3382
3383 * interp.c (sim_open): Add ABFD argument.
3384 (sim_load): Move call to sim_config from here.
3385 (sim_open): To here. Check return status.
3386
3387Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
72f4393d 3388
c906108c
SS		 3389 * gencode.c (build_instruction): Two arg MADD should
3390 not assign result to $0.
72f4393d 3391
c906108c
SS		 3392Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
3393
3394 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
3395 * sim/mips/configure.in: Regenerate.
3396
3397Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
3398
3399 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
3400 signed8, unsigned8 et.al. types.
3401
3402 * interp.c (SUB_REG_FETCH): Handle both little and big endian
3403 hosts when selecting subreg.
3404
3405Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
3406
3407 * interp.c (sim_engine_run): Reset the ZERO register to zero
3408 regardless of FEATURE_WARN_ZERO.
3409 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
3410
3411Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
3412
3413 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
3414 (SignalException): For BreakPoints ignore any mode bits and just
3415 save the PC.
3416 (SignalException): Always set the CAUSE register.
3417
3418Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
3419
3420 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
3421 exception has been taken.
3422
3423 * interp.c: Implement the ERET and mt/f sr instructions.
3424
3425Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
3426
3427 * interp.c (SignalException): Don't bother restarting an
3428 interrupt.
3429
3430Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3431
3432 * interp.c (SignalException): Really take an interrupt.
3433 (interrupt_event): Only deliver interrupts when enabled.
3434
3435Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
3436
3437 * interp.c (sim_info): Only print info when verbose.
3438 (sim_info) Use sim_io_printf for output.
72f4393d 3439
c906108c
SS		 3440Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3441
3442 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
3443 mips architectures.
3444
3445Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3446
3447 * interp.c (sim_do_command): Check for common commands if a
3448 simulator specific command fails.
3449
3450Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
3451
3452 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
3453 and simBE when DEBUG is defined.
3454
3455Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
3456
3457 * interp.c (interrupt_event): New function. Pass exception event
3458 onto exception handler.
3459
3460 * configure.in: Check for stdlib.h.
3461 * configure: Regenerate.
3462
3463 * gencode.c (build_instruction): Add UNUSED attribute to tempS
3464 variable declaration.
3465 (build_instruction): Initialize memval1.
3466 (build_instruction): Add UNUSED attribute to byte, bigend,
3467 reverse.
3468 (build_operands): Ditto.
3469
3470 * interp.c: Fix GCC warnings.
3471 (sim_get_quit_code): Delete.
3472
3473 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
3474 * Makefile.in: Ditto.
3475 * configure: Re-generate.
72f4393d 3476
c906108c
SS		 3477 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
3478
3479Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
3480
3481 * interp.c (mips_option_handler): New function parse argumes using
3482 sim-options.
3483 (myname): Replace with STATE_MY_NAME.
3484 (sim_open): Delete check for host endianness - performed by
3485 sim_config.
3486 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
3487 (sim_open): Move much of the initialization from here.
3488 (sim_load): To here. After the image has been loaded and
3489 endianness set.
3490 (sim_open): Move ColdReset from here.
3491 (sim_create_inferior): To here.
3492 (sim_open): Make FP check less dependant on host endianness.
3493
3494 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
3495 run.
3496 * interp.c (sim_set_callbacks): Delete.
3497
3498 * interp.c (membank, membank_base, membank_size): Replace with
3499 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
3500 (sim_open): Remove call to callback->init. gdb/run do this.
3501
3502 * interp.c: Update
3503
3504 * sim-main.h (SIM_HAVE_FLATMEM): Define.
3505
3506 * interp.c (big_endian_p): Delete, replaced by
3507 current_target_byte_order.
3508
3509Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3510
3511 * interp.c (host_read_long, host_read_word, host_swap_word,
3512 host_swap_long): Delete. Using common sim-endian.
3513 (sim_fetch_register, sim_store_register): Use H2T.
3514 (pipeline_ticks): Delete. Handled by sim-events.
3515 (sim_info): Update.
3516 (sim_engine_run): Update.
3517
3518Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
3519
3520 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
3521 reason from here.
3522 (SignalException): To here. Signal using sim_engine_halt.
3523 (sim_stop_reason): Delete, moved to common.
72f4393d 3524
c906108c
SS		 3525Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
3526
3527 * interp.c (sim_open): Add callback argument.
3528 (sim_set_callbacks): Delete SIM_DESC argument.
3529 (sim_size): Ditto.
3530
3531Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3532
3533 * Makefile.in (SIM_OBJS): Add common modules.
3534
3535 * interp.c (sim_set_callbacks): Also set SD callback.
3536 (set_endianness, xfer_*, swap_*): Delete.
3537 (host_read_word, host_read_long, host_swap_word, host_swap_long):
3538 Change to functions using sim-endian macros.
3539 (control_c, sim_stop): Delete, use common version.
3540 (simulate): Convert into.
3541 (sim_engine_run): This function.
3542 (sim_resume): Delete.
72f4393d 3543
c906108c
SS		 3544 * interp.c (simulation): New variable - the simulator object.
3545 (sim_kind): Delete global - merged into simulation.
3546 (sim_load): Cleanup. Move PC assignment from here.
3547 (sim_create_inferior): To here.
3548
3549 * sim-main.h: New file.
3550 * interp.c (sim-main.h): Include.
72f4393d 3551
c906108c
SS		 3552Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
3553
3554 * configure: Regenerated to track ../common/aclocal.m4 changes.
3555
3556Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
3557
3558 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
3559
3560Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
3561
72f4393d
L		 3562 * gencode.c (build_instruction): DIV instructions: check
3563 for division by zero and integer overflow before using
c906108c
SS		 3564 host's division operation.
3565
3566Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
3567
3568 * Makefile.in (SIM_OBJS): Add sim-load.o.
3569 * interp.c: #include bfd.h.
3570 (target_byte_order): Delete.
3571 (sim_kind, myname, big_endian_p): New static locals.
3572 (sim_open): Set sim_kind, myname. Move call to set_endianness to
3573 after argument parsing. Recognize -E arg, set endianness accordingly.
3574 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
3575 load file into simulator. Set PC from bfd.
3576 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
3577 (set_endianness): Use big_endian_p instead of target_byte_order.
3578
3579Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
3580
3581 * interp.c (sim_size): Delete prototype - conflicts with
3582 definition in remote-sim.h. Correct definition.
3583
3584Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3585
3586 * configure: Regenerated to track ../common/aclocal.m4 changes.
3587 * config.in: Ditto.
3588
3589Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
3590
3591 * interp.c (sim_open): New arg `kind'.
3592
3593 * configure: Regenerated to track ../common/aclocal.m4 changes.
3594
3595Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3596
3597 * configure: Regenerated to track ../common/aclocal.m4 changes.
3598
3599Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
3600
3601 * interp.c (sim_open): Set optind to 0 before calling getopt.
3602
3603Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3604
3605 * configure: Regenerated to track ../common/aclocal.m4 changes.
3606
3607Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
3608
3609 * interp.c : Replace uses of pr_addr with pr_uword64
3610 where the bit length is always 64 independent of SIM_ADDR.
3611 (pr_uword64) : added.
3612
3613Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3614
3615 * configure: Re-generate.
3616
3617Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
3618
3619 * configure: Regenerate to track ../common/aclocal.m4 changes.
3620
3621Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
3622
3623 * interp.c (sim_open): New SIM_DESC result. Argument is now
3624 in argv form.
3625 (other sim_*): New SIM_DESC argument.
3626
3627Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
3628
3629 * interp.c: Fix printing of addresses for non-64-bit targets.
3630 (pr_addr): Add function to print address based on size.
3631
3632Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
3633
3634 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
3635
3636Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
3637
3638 * gencode.c (build_mips16_operands): Correct computation of base
3639 address for extended PC relative instruction.
3640
3641Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
3642
3643 * interp.c (mips16_entry): Add support for floating point cases.
3644 (SignalException): Pass floating point cases to mips16_entry.
3645 (ValueFPR): Don't restrict fmt_single and fmt_word to even
3646 registers.
3647 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
3648 or fmt_word.
3649 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
3650 and then set the state to fmt_uninterpreted.
3651 (COP_SW): Temporarily set the state to fmt_word while calling
3652 ValueFPR.
3653
3654Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
3655
3656 * gencode.c (build_instruction): The high order may be set in the
3657 comparison flags at any ISA level, not just ISA 4.
3658
3659Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
3660
3661 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
3662 COMMON_{PRE,POST}_CONFIG_FRAG instead.
3663 * configure.in: sinclude ../common/aclocal.m4.
3664 * configure: Regenerated.
3665
3666Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
3667
3668 * configure: Rebuild after change to aclocal.m4.
3669
3670Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
3671
3672 * configure configure.in Makefile.in: Update to new configure
3673 scheme which is more compatible with WinGDB builds.
3674 * configure.in: Improve comment on how to run autoconf.
3675 * configure: Re-run autoconf to get new ../common/aclocal.m4.
3676 * Makefile.in: Use autoconf substitution to install common
3677 makefile fragment.
3678
3679Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
3680
3681 * gencode.c (build_instruction): Use BigEndianCPU instead of
3682 ByteSwapMem.
3683
3684Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
3685
3686 * interp.c (sim_monitor): Make output to stdout visible in
3687 wingdb's I/O log window.
3688
3689Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
3690
3691 * support.h: Undo previous change to SIGTRAP
3692 and SIGQUIT values.
3693
3694Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
3695
3696 * interp.c (store_word, load_word): New static functions.
3697 (mips16_entry): New static function.
3698 (SignalException): Look for mips16 entry and exit instructions.
3699 (simulate): Use the correct index when setting fpr_state after
3700 doing a pending move.
3701
3702Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
3703
3704 * interp.c: Fix byte-swapping code throughout to work on
3705 both little- and big-endian hosts.
3706
3707Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
3708
3709 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3710 with gdb/config/i386/xm-windows.h.
3711
3712Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
3713
3714 * gencode.c (build_instruction): Work around MSVC++ code gen bug
3715 that messes up arithmetic shifts.
3716
3717Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
3718
3719 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
3720 SIGTRAP and SIGQUIT for _WIN32.
3721
3722Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3723
3724 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3725 force a 64 bit multiplication.
3726 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3727 destination register is 0, since that is the default mips16 nop
3728 instruction.
3729
3730Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3731
3732 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3733 (build_endian_shift): Don't check proc64.
3734 (build_instruction): Always set memval to uword64. Cast op2 to
3735 uword64 when shifting it left in memory instructions. Always use
3736 the same code for stores--don't special case proc64.
3737
3738 * gencode.c (build_mips16_operands): Fix base PC value for PC
3739 relative operands.
3740 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3741 jal instruction.
3742 * interp.c (simJALDELAYSLOT): Define.
3743 (JALDELAYSLOT): Define.
3744 (INDELAYSLOT, INJALDELAYSLOT): Define.
3745 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3746
3747Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3748
3749 * interp.c (sim_open): add flush_cache as a PMON routine
3750 (sim_monitor): handle flush_cache by ignoring it
3751
3752Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3753
3754 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3755 BigEndianMem.
3756 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3757 (BigEndianMem): Rename to ByteSwapMem and change sense.
3758 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3759 BigEndianMem references to !ByteSwapMem.
3760 (set_endianness): New function, with prototype.
3761 (sim_open): Call set_endianness.
3762 (sim_info): Use simBE instead of BigEndianMem.
3763 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3764 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3765 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3766 ifdefs, keeping the prototype declaration.
3767 (swap_word): Rewrite correctly.
3768 (ColdReset): Delete references to CONFIG. Delete endianness related
3769 code; moved to set_endianness.
72f4393d 3770
c906108c
SS		 3771Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3772
3773 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3774 * interp.c (CHECKHILO): Define away.
3775 (simSIGINT): New macro.
3776 (membank_size): Increase from 1MB to 2MB.
3777 (control_c): New function.
3778 (sim_resume): Rename parameter signal to signal_number. Add local
3779 variable prev. Call signal before and after simulate.
3780 (sim_stop_reason): Add simSIGINT support.
3781 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3782 functions always.
3783 (sim_warning): Delete call to SignalException. Do call printf_filtered
3784 if logfh is NULL.
3785 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3786 a call to sim_warning.
3787
3788Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3789
3790 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3791 16 bit instructions.
3792
3793Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3794
3795 Add support for mips16 (16 bit MIPS implementation):
3796 * gencode.c (inst_type): Add mips16 instruction encoding types.
3797 (GETDATASIZEINSN): Define.
3798 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3799 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3800 mtlo.
3801 (MIPS16_DECODE): New table, for mips16 instructions.
3802 (bitmap_val): New static function.
3803 (struct mips16_op): Define.
3804 (mips16_op_table): New table, for mips16 operands.
3805 (build_mips16_operands): New static function.
3806 (process_instructions): If PC is odd, decode a mips16
3807 instruction. Break out instruction handling into new
3808 build_instruction function.
3809 (build_instruction): New static function, broken out of
3810 process_instructions. Check modifiers rather than flags for SHIFT
3811 bit count and m[ft]{hi,lo} direction.
3812 (usage): Pass program name to fprintf.
3813 (main): Remove unused variable this_option_optind. Change
3814 ``*loptarg++'' to ``loptarg++''.
3815 (my_strtoul): Parenthesize && within ||.
3816 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3817 (simulate): If PC is odd, fetch a 16 bit instruction, and
3818 increment PC by 2 rather than 4.
3819 * configure.in: Add case for mips16*-*-*.
3820 * configure: Rebuild.
3821
3822Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3823
3824 * interp.c: Allow -t to enable tracing in standalone simulator.
3825 Fix garbage output in trace file and error messages.
3826
3827Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3828
3829 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3830 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3831 * configure.in: Simplify using macros in ../common/aclocal.m4.
3832 * configure: Regenerated.
3833 * tconfig.in: New file.
3834
3835Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3836
3837 * interp.c: Fix bugs in 64-bit port.
3838 Use ansi function declarations for msvc compiler.
3839 Initialize and test file pointer in trace code.
3840 Prevent duplicate definition of LAST_EMED_REGNUM.
3841
3842Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3843
3844 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3845
3846Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3847
3848 * interp.c (SignalException): Check for explicit terminating
3849 breakpoint value.
3850 * gencode.c: Pass instruction value through SignalException()
3851 calls for Trap, Breakpoint and Syscall.
3852
3853Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3854
3855 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3856 only used on those hosts that provide it.
3857 * configure.in: Add sqrt() to list of functions to be checked for.
3858 * config.in: Re-generated.
3859 * configure: Re-generated.
3860
3861Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3862
3863 * gencode.c (process_instructions): Call build_endian_shift when
3864 expanding STORE RIGHT, to fix swr.
3865 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3866 clear the high bits.
3867 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3868 Fix float to int conversions to produce signed values.
3869
3870Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3871
3872 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3873 (process_instructions): Correct handling of nor instruction.
3874 Correct shift count for 32 bit shift instructions. Correct sign
3875 extension for arithmetic shifts to not shift the number of bits in
3876 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3877 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3878 Fix madd.
3879 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3880 It's OK to have a mult follow a mult. What's not OK is to have a
3881 mult follow an mfhi.
3882 (Convert): Comment out incorrect rounding code.
3883
3884Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3885
3886 * interp.c (sim_monitor): Improved monitor printf
3887 simulation. Tidied up simulator warnings, and added "--log" option
3888 for directing warning message output.
3889 * gencode.c: Use sim_warning() rather than WARNING macro.
3890
3891Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3892
3893 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3894 getopt1.o, rather than on gencode.c. Link objects together.
3895 Don't link against -liberty.
3896 (gencode.o, getopt.o, getopt1.o): New targets.
3897 * gencode.c: Include <ctype.h> and "ansidecl.h".
3898 (AND): Undefine after including "ansidecl.h".
3899 (ULONG_MAX): Define if not defined.
3900 (OP_*): Don't define macros; now defined in opcode/mips.h.
3901 (main): Call my_strtoul rather than strtoul.
3902 (my_strtoul): New static function.
3903
3904Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3905
3906 * gencode.c (process_instructions): Generate word64 and uword64
3907 instead of `long long' and `unsigned long long' data types.
3908 * interp.c: #include sysdep.h to get signals, and define default
3909 for SIGBUS.
3910 * (Convert): Work around for Visual-C++ compiler bug with type
3911 conversion.
3912 * support.h: Make things compile under Visual-C++ by using
3913 __int64 instead of `long long'. Change many refs to long long
3914 into word64/uword64 typedefs.
3915
3916Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3917
72f4393d
L		 3918 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3919 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3920 (docdir): Removed.
3921 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3922 (AC_PROG_INSTALL): Added.
c906108c 3923 (AC_PROG_CC): Moved to before configure.host call.
72f4393d
L		 3924 * configure: Rebuilt.
3925
c906108c
SS		 3926Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3927
3928 * configure.in: Define @SIMCONF@ depending on mips target.
3929 * configure: Rebuild.
3930 * Makefile.in (run): Add @SIMCONF@ to control simulator
3931 construction.
3932 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3933 * interp.c: Remove some debugging, provide more detailed error
3934 messages, update memory accesses to use LOADDRMASK.
72f4393d 3935
c906108c
SS		 3936Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3937
3938 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3939 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3940 stamp-h.
3941 * configure: Rebuild.
3942 * config.in: New file, generated by autoheader.
3943 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3944 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3945 HAVE_ANINT and HAVE_AINT, as appropriate.
3946 * Makefile.in (run): Use @LIBS@ rather than -lm.
3947 (interp.o): Depend upon config.h.
3948 (Makefile): Just rebuild Makefile.
3949 (clean): Remove stamp-h.
3950 (mostlyclean): Make the same as clean, not as distclean.
3951 (config.h, stamp-h): New targets.
3952
3953Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3954
3955 * interp.c (ColdReset): Fix boolean test. Make all simulator
3956 globals static.
3957
3958Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3959
3960 * interp.c (xfer_direct_word, xfer_direct_long,
3961 swap_direct_word, swap_direct_long, xfer_big_word,
3962 xfer_big_long, xfer_little_word, xfer_little_long,
3963 swap_word,swap_long): Added.
3964 * interp.c (ColdReset): Provide function indirection to
3965 host<->simulated_target transfer routines.
3966 * interp.c (sim_store_register, sim_fetch_register): Updated to
3967 make use of indirected transfer routines.
3968
3969Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3970
3971 * gencode.c (process_instructions): Ensure FP ABS instruction
3972 recognised.
3973 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3974 system call support.
3975
3976Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3977
3978 * interp.c (sim_do_command): Complain if callback structure not
3979 initialised.
3980
3981Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3982
3983 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3984 support for Sun hosts.
3985 * Makefile.in (gencode): Ensure the host compiler and libraries
3986 used for cross-hosted build.
3987
3988Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3989
3990 * interp.c, gencode.c: Some more (TODO) tidying.
3991
3992Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3993
3994 * gencode.c, interp.c: Replaced explicit long long references with
3995 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3996 * support.h (SET64LO, SET64HI): Macros added.
3997
3998Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3999
4000 * configure: Regenerate with autoconf 2.7.
4001
4002Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
4003
4004 * interp.c (LoadMemory): Enclose text following #endif in /* */.
4005 * support.h: Remove superfluous "1" from #if.
4006 * support.h (CHECKSIM): Remove stray 'a' at end of line.
4007
4008Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
4009
4010 * interp.c (StoreFPR): Control UndefinedResult() call on
4011 WARN_RESULT manifest.
4012
4013Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
4014
4015 * gencode.c: Tidied instruction decoding, and added FP instruction
4016 support.
4017
4018 * interp.c: Added dineroIII, and BSD profiling support. Also
4019 run-time FP handling.
4020
4021Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
4022
4023 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
4024 gencode.c, interp.c, support.h: created.
GDB Binutils - Deliverables
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