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2007-10-22 H.J. Lu <hongjiu.lu@intel.com>
[deliverable/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
599ca73e
RS		 12007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
2
3 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
4 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
5 shifts for that case.
6
2525df03
NC		 72007-09-04 Nick Clifton <nickc@redhat.com>
8
9 * interp.c (options enum): Add OPTION_INFO_MEMORY.
10 (display_mem_info): New static variable.
11 (mips_option_handler): Handle OPTION_INFO_MEMORY.
12 (mips_options): Add info-memory and memory-info.
13 (sim_open): After processing the command line and board
14 specification, check display_mem_info. If it is set then
15 call the real handler for the --memory-info command line
16 switch.
17
35ee6e1e
JB		 182007-08-24 Joel Brobecker <brobecker@adacore.com>
19
20 * configure.ac: Change license of multi-run.c to GPL version 3.
21 * configure: Regenerate.
22
d5fb0879
RS		 232007-06-28 Richard Sandiford <richard@codesourcery.com>
24
25 * configure.ac, configure: Revert last patch.
26
2a2ce21b
RS		 272007-06-26 Richard Sandiford <richard@codesourcery.com>
28
29 * configure.ac (sim_mipsisa3264_configs): New variable.
30 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
31 every configuration support all four targets, using the triplet to
32 determine the default.
33 * configure: Regenerate.
34
efdcccc9
RS		 352007-06-25 Richard Sandiford <richard@codesourcery.com>
36
0a7692b2 37 * Makefile.in (m16run.o): New rule.
efdcccc9 38
f532a356
TS		 392007-05-15 Thiemo Seufer <ths@mips.com>
40
41 * mips3264r2.igen (DSHD): Fix compile warning.
42
bfe9c90b
TS		 432007-05-14 Thiemo Seufer <ths@mips.com>
44
45 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
46 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
47 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
48 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
49 for mips32r2.
50
53f4826b
TS		 512007-03-01 Thiemo Seufer <ths@mips.com>
52
53 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
54 and mips64.
55
8bf3ddc8
TS		 562007-02-20 Thiemo Seufer <ths@mips.com>
57
58 * dsp.igen: Update copyright notice.
59 * dsp2.igen: Fix copyright notice.
60
8b082fb1
TS		 612007-02-20 Thiemo Seufer <ths@mips.com>
62 Chao-Ying Fu <fu@mips.com>
63
64 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
65 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
66 Add dsp2 to sim_igen_machine.
67 * configure: Regenerate.
68 * dsp.igen (do_ph_op): Add MUL support when op = 2.
69 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
70 (mulq_rs.ph): Use do_ph_mulq.
71 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
72 * mips.igen: Add dsp2 model and include dsp2.igen.
73 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
74 for *mips32r2, *mips64r2, *dsp.
75 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
76 for *mips32r2, *mips64r2, *dsp2.
77 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
78
b1004875
TS		 792007-02-19 Thiemo Seufer <ths@mips.com>
80 Nigel Stephens <nigel@mips.com>
81
82 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
83 jumps with hazard barrier.
84
f8df4c77
TS		 852007-02-19 Thiemo Seufer <ths@mips.com>
86 Nigel Stephens <nigel@mips.com>
87
88 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
89 after each call to sim_io_write.
90
b1004875 912007-02-19 Thiemo Seufer <ths@mips.com>
07802d98 92 Nigel Stephens <nigel@mips.com>
b1004875
TS		 93
94 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
95 supported by this simulator.
07802d98
TS		 96 (decode_coproc): Recognise additional CP0 Config registers
97 correctly.
98
14fb6c5a
TS		 992007-02-19 Thiemo Seufer <ths@mips.com>
100 Nigel Stephens <nigel@mips.com>
101 David Ung <davidu@mips.com>
102
103 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
104 uninterpreted formats. If fmt is one of the uninterpreted types
105 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
106 fmt_word, and fmt_uninterpreted_64 like fmt_long.
107 (store_fpr): When writing an invalid odd register, set the
108 matching even register to fmt_unknown, not the following register.
109 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
110 the the memory window at offset 0 set by --memory-size command
111 line option.
112 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
113 point register.
114 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
115 register.
116 (sim_monitor): When returning the memory size to the MIPS
117 application, use the value in STATE_MEM_SIZE, not an arbitrary
118 hardcoded value.
119 (cop_lw): Don' mess around with FPR_STATE, just pass
120 fmt_uninterpreted_32 to StoreFPR.
121 (cop_sw): Similarly.
122 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
123 (cop_sd): Similarly.
124 * mips.igen (not_word_value): Single version for mips32, mips64
125 and mips16.
126
c8847145
TS		 1272007-02-19 Thiemo Seufer <ths@mips.com>
128 Nigel Stephens <nigel@mips.com>
129
130 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
131 MBytes.
132
4b5d35ee
TS		 1332007-02-17 Thiemo Seufer <ths@mips.com>
134
135 * configure.ac (mips*-sde-elf*): Move in front of generic machine
136 configuration.
137 * configure: Regenerate.
138
3669427c
TS		 1392007-02-17 Thiemo Seufer <ths@mips.com>
140
141 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
142 Add mdmx to sim_igen_machine.
143 (mipsisa64*-*-*): Likewise. Remove dsp.
144 (mipsisa32*-*-*): Remove dsp.
145 * configure: Regenerate.
146
109ad085
TS		 1472007-02-13 Thiemo Seufer <ths@mips.com>
148
149 * configure.ac: Add mips*-sde-elf* target.
150 * configure: Regenerate.
151
921d7ad3
HPN		 1522006-12-21 Hans-Peter Nilsson <hp@axis.com>
153
154 * acconfig.h: Remove.
155 * config.in, configure: Regenerate.
156
02f97da7
TS		 1572006-11-07 Thiemo Seufer <ths@mips.com>
158
159 * dsp.igen (do_w_op): Fix compiler warning.
160
2d2733fc
TS		 1612006-08-29 Thiemo Seufer <ths@mips.com>
162 David Ung <davidu@mips.com>
163
164 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
165 sim_igen_machine.
166 * configure: Regenerate.
167 * mips.igen (model): Add smartmips.
168 (MADDU): Increment ACX if carry.
169 (do_mult): Clear ACX.
170 (ROR,RORV): Add smartmips.
171 (include): Include smartmips.igen.
172 * sim-main.h (ACX): Set to REGISTERS[89].
173 * smartmips.igen: New file.
174
d85c3a10
TS		 1752006-08-29 Thiemo Seufer <ths@mips.com>
176 David Ung <davidu@mips.com>
177
178 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
179 mips3264r2.igen. Add missing dependency rules.
180 * m16e.igen: Support for mips16e save/restore instructions.
181
e85e3205
RE		 1822006-06-13 Richard Earnshaw <rearnsha@arm.com>
183
184 * configure: Regenerated.
185
2f0122dc
DJ		 1862006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
187
188 * configure: Regenerated.
189
20e95c23
DJ		 1902006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
191
192 * configure: Regenerated.
193
69088b17
CF		 1942006-05-15 Chao-ying Fu <fu@mips.com>
195
196 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
197
0275de4e
NC		 1982006-04-18 Nick Clifton <nickc@redhat.com>
199
200 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
201 statement.
202
b3a3ffef
HPN		 2032006-03-29 Hans-Peter Nilsson <hp@axis.com>
204
205 * configure: Regenerate.
206
40a5538e
CF		 2072005-12-14 Chao-ying Fu <fu@mips.com>
208
209 * Makefile.in (SIM_OBJS): Add dsp.o.
210 (dsp.o): New dependency.
211 (IGEN_INCLUDE): Add dsp.igen.
212 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
213 mipsisa64*-*-*): Add dsp to sim_igen_machine.
214 * configure: Regenerate.
215 * mips.igen: Add dsp model and include dsp.igen.
216 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
217 because these instructions are extended in DSP ASE.
218 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
219 adding 6 DSP accumulator registers and 1 DSP control register.
220 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
221 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
222 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
223 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
224 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
225 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
226 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
227 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
228 DSPCR_CCOND_SMASK): New define.
229 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
230 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
231
21d14896
ILT		 2322005-07-08 Ian Lance Taylor <ian@airs.com>
233
234 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
235
b16d63da
DU		 2362005-06-16 David Ung <davidu@mips.com>
237 Nigel Stephens <nigel@mips.com>
238
239 * mips.igen: New mips16e model and include m16e.igen.
240 (check_u64): Add mips16e tag.
241 * m16e.igen: New file for MIPS16e instructions.
242 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
243 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
244 models.
245 * configure: Regenerate.
246
e70cb6cd
CD		 2472005-05-26 David Ung <davidu@mips.com>
248
249 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
250 tags to all instructions which are applicable to the new ISAs.
251 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
252 vr.igen.
253 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
254 instructions.
255 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
256 to mips.igen.
257 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
258 * configure: Regenerate.
259
2b193c4a
MK		 2602005-03-23 Mark Kettenis <kettenis@gnu.org>
261
262 * configure: Regenerate.
263
35695fd6
AC		 2642005-01-14 Andrew Cagney <cagney@gnu.org>
265
266 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
267 explicit call to AC_CONFIG_HEADER.
268 * configure: Regenerate.
269
f0569246
AC		 2702005-01-12 Andrew Cagney <cagney@gnu.org>
271
272 * configure.ac: Update to use ../common/common.m4.
273 * configure: Re-generate.
274
38f48d72
AC		 2752005-01-11 Andrew Cagney <cagney@localhost.localdomain>
276
277 * configure: Regenerated to track ../common/aclocal.m4 changes.
278
b7026657
AC		 2792005-01-07 Andrew Cagney <cagney@gnu.org>
280
281 * configure.ac: Rename configure.in, require autoconf 2.59.
282 * configure: Re-generate.
283
379832de
HPN		 2842004-12-08 Hans-Peter Nilsson <hp@axis.com>
285
286 * configure: Regenerate for ../common/aclocal.m4 update.
287
cd62154c
AC		 2882004-09-24 Monika Chaddha <monika@acmet.com>
289
290 Committed by Andrew Cagney.
291 * m16.igen (CMP, CMPI): Fix assembler.
292
e5da76ec
CD		 2932004-08-18 Chris Demetriou <cgd@broadcom.com>
294
295 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
296 * configure: Regenerate.
297
139181c8
CD		 2982004-06-25 Chris Demetriou <cgd@broadcom.com>
299
300 * configure.in (sim_m16_machine): Include mipsIII.
301 * configure: Regenerate.
302
1a27f959
CD		 3032004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
304
305 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
306 from COP0_BADVADDR.
307 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
308
5dbb7b5a
CD		 3092004-04-10 Chris Demetriou <cgd@broadcom.com>
310
311 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
312
14234056
CD		 3132004-04-09 Chris Demetriou <cgd@broadcom.com>
314
315 * mips.igen (check_fmt): Remove.
316 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
317 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
318 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
319 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
320 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
321 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
322 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
323 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
324 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
325 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
326
c6f9085c
CD		 3272004-04-09 Chris Demetriou <cgd@broadcom.com>
328
329 * sb1.igen (check_sbx): New function.
330 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
331
11d66e66 3322004-03-29 Chris Demetriou <cgd@broadcom.com>
0e1b7197
RS		 333 Richard Sandiford <rsandifo@redhat.com>
334
335 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
336 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
337 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
338 separate implementations for mipsIV and mipsV. Use new macros to
339 determine whether the restrictions apply.
340
b3208fb8
CD		 3412004-01-19 Chris Demetriou <cgd@broadcom.com>
342
343 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
344 (check_mult_hilo): Improve comments.
345 (check_div_hilo): Likewise. Also, fork off a new version
346 to handle mips32/mips64 (since there are no hazards to check
347 in MIPS32/MIPS64).
348
9a1d84fb
CD		 3492003-06-17 Richard Sandiford <rsandifo@redhat.com>
350
351 * mips.igen (do_dmultx): Fix check for negative operands.
352
ae451ac6
ILT		 3532003-05-16 Ian Lance Taylor <ian@airs.com>
354
355 * Makefile.in (SHELL): Make sure this is defined.
356 (various): Use $(SHELL) whenever we invoke move-if-change.
357
dd69d292
CD		 3582003-05-03 Chris Demetriou <cgd@broadcom.com>
359
360 * cp1.c: Tweak attribution slightly.
361 * cp1.h: Likewise.
362 * mdmx.c: Likewise.
363 * mdmx.igen: Likewise.
364 * mips3d.igen: Likewise.
365 * sb1.igen: Likewise.
366
bcd0068e
CD		 3672003-04-15 Richard Sandiford <rsandifo@redhat.com>
368
369 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
370 unsigned operands.
371
6b4a8935
AC		 3722003-02-27 Andrew Cagney <cagney@redhat.com>
373
601da316
AC		 374 * interp.c (sim_open): Rename _bfd to bfd.
375 (sim_create_inferior): Ditto.
6b4a8935 376
d29e330f
CD		 3772003-01-14 Chris Demetriou <cgd@broadcom.com>
378
379 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
380
a2353a08
CD		 3812003-01-14 Chris Demetriou <cgd@broadcom.com>
382
383 * mips.igen (EI, DI): Remove.
384
80551777
CD		 3852003-01-05 Richard Sandiford <rsandifo@redhat.com>
386
387 * Makefile.in (tmp-run-multi): Fix mips16 filter.
388
4c54fc26
CD		 3892003-01-04 Richard Sandiford <rsandifo@redhat.com>
390 Andrew Cagney <ac131313@redhat.com>
391 Gavin Romig-Koch <gavin@redhat.com>
392 Graydon Hoare <graydon@redhat.com>
393 Aldy Hernandez <aldyh@redhat.com>
394 Dave Brolley <brolley@redhat.com>
395 Chris Demetriou <cgd@broadcom.com>
396
397 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
398 (sim_mach_default): New variable.
399 (mips64vr-*-*, mips64vrel-*-*): New configurations.
400 Add a new simulator generator, MULTI.
401 * configure: Regenerate.
402 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
403 (multi-run.o): New dependency.
404 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
405 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
406 (tmp-multi): Combine them.
407 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
408 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
409 (distclean-extra): New rule.
410 * sim-main.h: Include bfd.h.
411 (MIPS_MACH): New macro.
412 * mips.igen (vr4120, vr5400, vr5500): New models.
413 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
414 * vr.igen: Replace with new version.
415
e6c674b8
CD		 4162003-01-04 Chris Demetriou <cgd@broadcom.com>
417
418 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
419 * configure: Regenerate.
420
28f50ac8
CD		 4212002-12-31 Chris Demetriou <cgd@broadcom.com>
422
423 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
424 * mips.igen: Remove all invocations of check_branch_bug and
425 mark_branch_bug.
426
5071ffe6
CD		 4272002-12-16 Chris Demetriou <cgd@broadcom.com>
428
429 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
430
06e7837e
CD		 4312002-07-30 Chris Demetriou <cgd@broadcom.com>
432
433 * mips.igen (do_load_double, do_store_double): New functions.
434 (LDC1, SDC1): Rename to...
435 (LDC1b, SDC1b): respectively.
436 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
437
2265c243
MS		 4382002-07-29 Michael Snyder <msnyder@redhat.com>
439
440 * cp1.c (fp_recip2): Modify initialization expression so that
441 GCC will recognize it as constant.
442
a2f8b4f3
CD		 4432002-06-18 Chris Demetriou <cgd@broadcom.com>
444
445 * mdmx.c (SD_): Delete.
446 (Unpredictable): Re-define, for now, to directly invoke
447 unpredictable_action().
448 (mdmx_acc_op): Fix error in .ob immediate handling.
449
b4b6c939
AC		 4502002-06-18 Andrew Cagney <cagney@redhat.com>
451
452 * interp.c (sim_firmware_command): Initialize `address'.
453
c8cca39f
AC		 4542002-06-16 Andrew Cagney <ac131313@redhat.com>
455
456 * configure: Regenerated to track ../common/aclocal.m4 changes.
457
e7e81181
CD		 4582002-06-14 Chris Demetriou <cgd@broadcom.com>
459 Ed Satterthwaite <ehs@broadcom.com>
460
461 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
462 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
463 * mips.igen: Include mips3d.igen.
464 (mips3d): New model name for MIPS-3D ASE instructions.
465 (CVT.W.fmt): Don't use this instruction for word (source) format
466 instructions.
467 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
468 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
469 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
470 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
471 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
472 (RSquareRoot1, RSquareRoot2): New macros.
473 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
474 (fp_rsqrt2): New functions.
475 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
476 * configure: Regenerate.
477
3a2b820e 4782002-06-13 Chris Demetriou <cgd@broadcom.com>
eab54952 479 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 480
481 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
482 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
483 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
484 (convert): Note that this function is not used for paired-single
485 format conversions.
486 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
487 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
488 (check_fmt_p): Enable paired-single support.
489 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
490 (PUU.PS): New instructions.
491 (CVT.S.fmt): Don't use this instruction for paired-single format
492 destinations.
493 * sim-main.h (FP_formats): New value 'fmt_ps.'
494 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
495 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
496
d18ea9c2
CD		 4972002-06-12 Chris Demetriou <cgd@broadcom.com>
498
499 * mips.igen: Fix formatting of function calls in
500 many FP operations.
501
95fd5cee
CD		 5022002-06-12 Chris Demetriou <cgd@broadcom.com>
503
504 * mips.igen (MOVN, MOVZ): Trace result.
505 (TNEI): Print "tnei" as the opcode name in traces.
506 (CEIL.W): Add disassembly string for traces.
507 (RSQRT.fmt): Make location of disassembly string consistent
508 with other instructions.
509
4f0d55ae
CD		 5102002-06-12 Chris Demetriou <cgd@broadcom.com>
511
512 * mips.igen (X): Delete unused function.
513
3c25f8c7
AC		 5142002-06-08 Andrew Cagney <cagney@redhat.com>
515
516 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
517
f3c08b7e
CD		 5182002-06-07 Chris Demetriou <cgd@broadcom.com>
519 Ed Satterthwaite <ehs@broadcom.com>
520
521 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
522 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
523 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
524 (fp_nmsub): New prototypes.
525 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
526 (NegMultiplySub): New defines.
527 * mips.igen (RSQRT.fmt): Use RSquareRoot().
528 (MADD.D, MADD.S): Replace with...
529 (MADD.fmt): New instruction.
530 (MSUB.D, MSUB.S): Replace with...
531 (MSUB.fmt): New instruction.
532 (NMADD.D, NMADD.S): Replace with...
533 (NMADD.fmt): New instruction.
534 (NMSUB.D, MSUB.S): Replace with...
535 (NMSUB.fmt): New instruction.
536
52714ff9
CD		 5372002-06-07 Chris Demetriou <cgd@broadcom.com>
538 Ed Satterthwaite <ehs@broadcom.com>
539
540 * cp1.c: Fix more comment spelling and formatting.
541 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
542 (denorm_mode): New function.
543 (fpu_unary, fpu_binary): Round results after operation, collect
544 status from rounding operations, and update the FCSR.
545 (convert): Collect status from integer conversions and rounding
546 operations, and update the FCSR. Adjust NaN values that result
547 from conversions. Convert to use sim_io_eprintf rather than
548 fprintf, and remove some debugging code.
549 * cp1.h (fenr_FS): New define.
550
577d8c4b
CD		 5512002-06-07 Chris Demetriou <cgd@broadcom.com>
552
553 * cp1.c (convert): Remove unusable debugging code, and move MIPS
554 rounding mode to sim FP rounding mode flag conversion code into...
555 (rounding_mode): New function.
556
196496ed
CD		 5572002-06-07 Chris Demetriou <cgd@broadcom.com>
558
559 * cp1.c: Clean up formatting of a few comments.
560 (value_fpr): Reformat switch statement.
561
cfe9ea23
CD		 5622002-06-06 Chris Demetriou <cgd@broadcom.com>
563 Ed Satterthwaite <ehs@broadcom.com>
564
565 * cp1.h: New file.
566 * sim-main.h: Include cp1.h.
567 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
568 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
569 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
570 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
571 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
572 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
573 * cp1.c: Don't include sim-fpu.h; already included by
574 sim-main.h. Clean up formatting of some comments.
575 (NaN, Equal, Less): Remove.
576 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
577 (fp_cmp): New functions.
578 * mips.igen (do_c_cond_fmt): Remove.
579 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
580 Compare. Add result tracing.
581 (CxC1): Remove, replace with...
582 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
583 (DMxC1): Remove, replace with...
584 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
585 (MxC1): Remove, replace with...
586 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
587
ee7254b0
CD		 5882002-06-04 Chris Demetriou <cgd@broadcom.com>
589
590 * sim-main.h (FGRIDX): Remove, replace all uses with...
591 (FGR_BASE): New macro.
592 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
593 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
594 (NR_FGR, FGR): Likewise.
595 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
596 * mips.igen: Likewise.
597
d3eb724f
CD		 5982002-06-04 Chris Demetriou <cgd@broadcom.com>
599
600 * cp1.c: Add an FSF Copyright notice to this file.
601
ba46ddd0
CD		 6022002-06-04 Chris Demetriou <cgd@broadcom.com>
603 Ed Satterthwaite <ehs@broadcom.com>
604
605 * cp1.c (Infinity): Remove.
606 * sim-main.h (Infinity): Likewise.
607
608 * cp1.c (fp_unary, fp_binary): New functions.
609 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
610 (fp_sqrt): New functions, implemented in terms of the above.
611 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
612 (Recip, SquareRoot): Remove (replaced by functions above).
613 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
614 (fp_recip, fp_sqrt): New prototypes.
615 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
616 (Recip, SquareRoot): Replace prototypes with #defines which
617 invoke the functions above.
618
18d8a52d
CD		 6192002-06-03 Chris Demetriou <cgd@broadcom.com>
620
621 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
622 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
623 file, remove PARAMS from prototypes.
624 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
625 simulator state arguments.
626 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
627 pass simulator state arguments.
628 * cp1.c (SD): Redefine as CPU_STATE(cpu).
629 (store_fpr, convert): Remove 'sd' argument.
630 (value_fpr): Likewise. Convert to use 'SD' instead.
631
0f154cbd
CD		 6322002-06-03 Chris Demetriou <cgd@broadcom.com>
633
634 * cp1.c (Min, Max): Remove #if 0'd functions.
635 * sim-main.h (Min, Max): Remove.
636
e80fc152
CD		 6372002-06-03 Chris Demetriou <cgd@broadcom.com>
638
639 * cp1.c: fix formatting of switch case and default labels.
640 * interp.c: Likewise.
641 * sim-main.c: Likewise.
642
bad673a9
CD		 6432002-06-03 Chris Demetriou <cgd@broadcom.com>
644
645 * cp1.c: Clean up comments which describe FP formats.
646 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
647
7cbea089
CD		 6482002-06-03 Chris Demetriou <cgd@broadcom.com>
649 Ed Satterthwaite <ehs@broadcom.com>
650
651 * configure.in (mipsisa64sb1*-*-*): New target for supporting
652 Broadcom SiByte SB-1 processor configurations.
653 * configure: Regenerate.
654 * sb1.igen: New file.
655 * mips.igen: Include sb1.igen.
656 (sb1): New model.
657 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
658 * mdmx.igen: Add "sb1" model to all appropriate functions and
659 instructions.
660 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
661 (ob_func, ob_acc): Reference the above.
662 (qh_acc): Adjust to keep the same size as ob_acc.
663 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
664 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
665
909daa82
CD		 6662002-06-03 Chris Demetriou <cgd@broadcom.com>
667
668 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
669
f4f1b9f1
CD		 6702002-06-02 Chris Demetriou <cgd@broadcom.com>
671 Ed Satterthwaite <ehs@broadcom.com>
672
673 * mips.igen (mdmx): New (pseudo-)model.
674 * mdmx.c, mdmx.igen: New files.
675 * Makefile.in (SIM_OBJS): Add mdmx.o.
676 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
677 New typedefs.
678 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
679 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
680 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
681 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
682 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
683 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
684 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
685 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
686 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
687 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
688 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
689 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
690 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
691 (qh_fmtsel): New macros.
692 (_sim_cpu): New member "acc".
693 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
694 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
695
5accf1ff
CD		 6962002-05-01 Chris Demetriou <cgd@broadcom.com>
697
698 * interp.c: Use 'deprecated' rather than 'depreciated.'
699 * sim-main.h: Likewise.
700
402586aa
CD		 7012002-05-01 Chris Demetriou <cgd@broadcom.com>
702
703 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
704 which wouldn't compile anyway.
705 * sim-main.h (unpredictable_action): New function prototype.
706 (Unpredictable): Define to call igen function unpredictable().
707 (NotWordValue): New macro to call igen function not_word_value().
708 (UndefinedResult): Remove.
709 * interp.c (undefined_result): Remove.
710 (unpredictable_action): New function.
711 * mips.igen (not_word_value, unpredictable): New functions.
712 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
713 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
714 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
715 NotWordValue() to check for unpredictable inputs, then
716 Unpredictable() to handle them.
717
c9b9995a
CD		 7182002-02-24 Chris Demetriou <cgd@broadcom.com>
719
720 * mips.igen: Fix formatting of calls to Unpredictable().
721
e1015982
AC		 7222002-04-20 Andrew Cagney <ac131313@redhat.com>
723
724 * interp.c (sim_open): Revert previous change.
725
b882a66b
AO		 7262002-04-18 Alexandre Oliva <aoliva@redhat.com>
727
728 * interp.c (sim_open): Disable chunk of code that wrote code in
729 vector table entries.
730
c429b7dd
CD		 7312002-03-19 Chris Demetriou <cgd@broadcom.com>
732
733 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
734 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
735 unused definitions.
736
37d146fa
CD		 7372002-03-19 Chris Demetriou <cgd@broadcom.com>
738
739 * cp1.c: Fix many formatting issues.
740
07892c0b
CD		 7412002-03-19 Chris G. Demetriou <cgd@broadcom.com>
742
743 * cp1.c (fpu_format_name): New function to replace...
744 (DOFMT): This. Delete, and update all callers.
745 (fpu_rounding_mode_name): New function to replace...
746 (RMMODE): This. Delete, and update all callers.
747
487f79b7
CD		 7482002-03-19 Chris G. Demetriou <cgd@broadcom.com>
749
750 * interp.c: Move FPU support routines from here to...
751 * cp1.c: Here. New file.
752 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
753 (cp1.o): New target.
754
1e799e28
CD		 7552002-03-12 Chris Demetriou <cgd@broadcom.com>
756
757 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
758 * mips.igen (mips32, mips64): New models, add to all instructions
759 and functions as appropriate.
760 (loadstore_ea, check_u64): New variant for model mips64.
761 (check_fmt_p): New variant for models mipsV and mips64, remove
762 mipsV model marking fro other variant.
763 (SLL) Rename to...
764 (SLLa) this.
765 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
766 for mips32 and mips64.
767 (DCLO, DCLZ): New instructions for mips64.
768
82f728db
CD		 7692002-03-07 Chris Demetriou <cgd@broadcom.com>
770
771 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
772 immediate or code as a hex value with the "%#lx" format.
773 (ANDI): Likewise, and fix printed instruction name.
774
b96e7ef1
CD		 7752002-03-05 Chris Demetriou <cgd@broadcom.com>
776
777 * sim-main.h (UndefinedResult, Unpredictable): New macros
778 which currently do nothing.
779
d35d4f70
CD		 7802002-03-05 Chris Demetriou <cgd@broadcom.com>
781
782 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
783 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
784 (status_CU3): New definitions.
785
786 * sim-main.h (ExceptionCause): Add new values for MIPS32
787 and MIPS64: MDMX, MCheck, CacheErr. Update comments
788 for DebugBreakPoint and NMIReset to note their status in
789 MIPS32 and MIPS64.
790 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
791 (SignalExceptionCacheErr): New exception macros.
792
3ad6f714
CD		 7932002-03-05 Chris Demetriou <cgd@broadcom.com>
794
795 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
796 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
797 is always enabled.
798 (SignalExceptionCoProcessorUnusable): Take as argument the
799 unusable coprocessor number.
800
86b77b47
CD		 8012002-03-05 Chris Demetriou <cgd@broadcom.com>
802
803 * mips.igen: Fix formatting of all SignalException calls.
804
97a88e93 8052002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 806
807 * sim-main.h (SIGNEXTEND): Remove.
808
97a88e93 8092002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 810
811 * mips.igen: Remove gencode comment from top of file, fix
812 spelling in another comment.
813
97a88e93 8142002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 815
816 * mips.igen (check_fmt, check_fmt_p): New functions to check
817 whether specific floating point formats are usable.
818 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
819 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
820 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
821 Use the new functions.
822 (do_c_cond_fmt): Remove format checks...
823 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
824
97a88e93 8252002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 826
827 * mips.igen: Fix formatting of check_fpu calls.
828
41774c9d
CD		 8292002-03-03 Chris Demetriou <cgd@broadcom.com>
830
831 * mips.igen (FLOOR.L.fmt): Store correct destination register.
832
4a0bd876
CD		 8332002-03-03 Chris Demetriou <cgd@broadcom.com>
834
835 * mips.igen: Remove whitespace at end of lines.
836
09297648
CD		 8372002-03-02 Chris Demetriou <cgd@broadcom.com>
838
839 * mips.igen (loadstore_ea): New function to do effective
840 address calculations.
841 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
842 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
843 CACHE): Use loadstore_ea to do effective address computations.
844
043b7057
CD		 8452002-03-02 Chris Demetriou <cgd@broadcom.com>
846
847 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
848 * mips.igen (LL, CxC1, MxC1): Likewise.
849
c1e8ada4
CD		 8502002-03-02 Chris Demetriou <cgd@broadcom.com>
851
852 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
853 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
854 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
855 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
856 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
857 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
858 Don't split opcode fields by hand, use the opcode field values
859 provided by igen.
860
3e1dca16
CD		 8612002-03-01 Chris Demetriou <cgd@broadcom.com>
862
863 * mips.igen (do_divu): Fix spacing.
864
865 * mips.igen (do_dsllv): Move to be right before DSLLV,
866 to match the rest of the do_<shift> functions.
867
fff8d27d
CD		 8682002-03-01 Chris Demetriou <cgd@broadcom.com>
869
870 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
871 DSRL32, do_dsrlv): Trace inputs and results.
872
0d3e762b
CD		 8732002-03-01 Chris Demetriou <cgd@broadcom.com>
874
875 * mips.igen (CACHE): Provide instruction-printing string.
876
877 * interp.c (signal_exception): Comment tokens after #endif.
878
eb5fcf93
CD		 8792002-02-28 Chris Demetriou <cgd@broadcom.com>
880
881 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
882 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
883 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
884 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
885 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
886 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
887 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
888 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
889
bb22bd7d
CD		 8902002-02-28 Chris Demetriou <cgd@broadcom.com>
891
892 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
893 instruction-printing string.
894 (LWU): Use '64' as the filter flag.
895
91a177cf
CD		 8962002-02-28 Chris Demetriou <cgd@broadcom.com>
897
898 * mips.igen (SDXC1): Fix instruction-printing string.
899
387f484a
CD		 9002002-02-28 Chris Demetriou <cgd@broadcom.com>
901
902 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
903 filter flags "32,f".
904
3d81f391
CD		 9052002-02-27 Chris Demetriou <cgd@broadcom.com>
906
907 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
908 as the filter flag.
909
af5107af
CD		 9102002-02-27 Chris Demetriou <cgd@broadcom.com>
911
912 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
913 add a comma) so that it more closely match the MIPS ISA
914 documentation opcode partitioning.
915 (PREF): Put useful names on opcode fields, and include
916 instruction-printing string.
917
ca971540
CD		 9182002-02-27 Chris Demetriou <cgd@broadcom.com>
919
920 * mips.igen (check_u64): New function which in the future will
921 check whether 64-bit instructions are usable and signal an
922 exception if not. Currently a no-op.
923 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
924 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
925 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
926 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
927
928 * mips.igen (check_fpu): New function which in the future will
929 check whether FPU instructions are usable and signal an exception
930 if not. Currently a no-op.
931 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
932 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
933 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
934 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
935 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
936 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
937 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
938 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
939
1c47a468
CD		 9402002-02-27 Chris Demetriou <cgd@broadcom.com>
941
942 * mips.igen (do_load_left, do_load_right): Move to be immediately
943 following do_load.
944 (do_store_left, do_store_right): Move to be immediately following
945 do_store.
946
603a98e7
CD		 9472002-02-27 Chris Demetriou <cgd@broadcom.com>
948
949 * mips.igen (mipsV): New model name. Also, add it to
950 all instructions and functions where it is appropriate.
951
c5d00cc7
CD		 9522002-02-18 Chris Demetriou <cgd@broadcom.com>
953
954 * mips.igen: For all functions and instructions, list model
955 names that support that instruction one per line.
956
074e9cb8
CD		 9572002-02-11 Chris Demetriou <cgd@broadcom.com>
958
959 * mips.igen: Add some additional comments about supported
960 models, and about which instructions go where.
961 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
962 order as is used in the rest of the file.
963
9805e229
CD		 9642002-02-11 Chris Demetriou <cgd@broadcom.com>
965
966 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
967 indicating that ALU32_END or ALU64_END are there to check
968 for overflow.
969 (DADD): Likewise, but also remove previous comment about
970 overflow checking.
971
f701dad2
CD		 9722002-02-10 Chris Demetriou <cgd@broadcom.com>
973
974 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
975 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
976 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
977 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
978 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
979 fields (i.e., add and move commas) so that they more closely
980 match the MIPS ISA documentation opcode partitioning.
981
9822002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098
CD		 983
984 * mips.igen (ADDI): Print immediate value.
985 (BREAK): Print code.
986 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
987 (SLL): Print "nop" specially, and don't run the code
988 that does the shift for the "nop" case.
989
9e52972e
FF		 9902001-11-17 Fred Fish <fnf@redhat.com>
991
992 * sim-main.h (float_operation): Move enum declaration outside
993 of _sim_cpu struct declaration.
994
c0efbca4
JB		 9952001-04-12 Jim Blandy <jimb@redhat.com>
996
997 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
998 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
999 set of the FCSR.
1000 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1001 PENDING_FILL, and you can get the intended effect gracefully by
1002 calling PENDING_SCHED directly.
1003
fb891446
BE		 10042001-02-23 Ben Elliston <bje@redhat.com>
1005
1006 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1007 already defined elsewhere.
1008
8030f857
BE		 10092001-02-19 Ben Elliston <bje@redhat.com>
1010
1011 * sim-main.h (sim_monitor): Return an int.
1012 * interp.c (sim_monitor): Add return values.
1013 (signal_exception): Handle error conditions from sim_monitor.
1014
56b48a7a
CD		 10152001-02-08 Ben Elliston <bje@redhat.com>
1016
1017 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1018 (store_memory): Likewise, pass cia to sim_core_write*.
1019
d3ee60d9
FCE		 10202000-10-19 Frank Ch. Eigler <fche@redhat.com>
1021
1022 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1023 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1024
071da002
AC		 1025Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1026
1027 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1028 * Makefile.in: Don't delete *.igen when cleaning directory.
1029
a28c02cd
AC		 1030Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1031
1032 * m16.igen (break): Call SignalException not sim_engine_halt.
1033
80ee11fa
AC		 1034Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1035
1036 From Jason Eckhardt:
1037 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1038
673388c0
AC		 1039Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1040
1041 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1042
4c0deff4
NC		 10432000-05-24 Michael Hayes <mhayes@cygnus.com>
1044
1045 * mips.igen (do_dmultx): Fix typo.
1046
eb2d80b4
AC		 1047Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1048
1049 * configure: Regenerated to track ../common/aclocal.m4 changes.
1050
dd37a34b
AC		 1051Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1052
1053 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1054
4c0deff4
NC		 10552000-04-12 Frank Ch. Eigler <fche@redhat.com>
1056
1057 * sim-main.h (GPR_CLEAR): Define macro.
1058
e30db738
AC		 1059Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1060
1061 * interp.c (decode_coproc): Output long using %lx and not %s.
1062
cb7450ea
FCE		 10632000-03-21 Frank Ch. Eigler <fche@redhat.com>
1064
1065 * interp.c (sim_open): Sort & extend dummy memory regions for
1066 --board=jmr3904 for eCos.
1067
a3027dd7
FCE		 10682000-03-02 Frank Ch. Eigler <fche@redhat.com>
1069
1070 * configure: Regenerated.
1071
1072Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1073
1074 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1075 calls, conditional on the simulator being in verbose mode.
1076
dfcd3bfb
JM		 1077Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1078
1079 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1080 cache don't get ReservedInstruction traps.
1081
c2d11a7d
JM		 10821999-11-29 Mark Salter <msalter@cygnus.com>
1083
1084 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1085 to clear status bits in sdisr register. This is how the hardware works.
1086
1087 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1088 being used by cygmon.
1089
4ce44c66
JM		 10901999-11-11 Andrew Haley <aph@cygnus.com>
1091
1092 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1093 instructions.
1094
cff3e48b
JM		 1095Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1096
1097 * mips.igen (MULT): Correct previous mis-applied patch.
1098
d4f3574e
SS		 1099Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1100
1101 * mips.igen (delayslot32): Handle sequence like
1102 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1103 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1104 (MULT): Actually pass the third register...
1105
11061999-09-03 Mark Salter <msalter@cygnus.com>
1107
1108 * interp.c (sim_open): Added more memory aliases for additional
1109 hardware being touched by cygmon on jmr3904 board.
1110
1111Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1112
1113 * configure: Regenerated to track ../common/aclocal.m4 changes.
1114
a0b3c4fd
JM		 1115Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1116
1117 * interp.c (sim_store_register): Handle case where client - GDB -
1118 specifies that a 4 byte register is 8 bytes in size.
1119 (sim_fetch_register): Ditto.
1120
adf40b2e
JM		 11211999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1122
1123 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1124 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1125 (idt_monitor_base): Base address for IDT monitor traps.
1126 (pmon_monitor_base): Ditto for PMON.
1127 (lsipmon_monitor_base): Ditto for LSI PMON.
1128 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1129 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1130 (sim_firmware_command): New function.
1131 (mips_option_handler): Call it for OPTION_FIRMWARE.
1132 (sim_open): Allocate memory for idt_monitor region. If "--board"
1133 option was given, add no monitor by default. Add BREAK hooks only if
1134 monitors are also there.
1135
43e526b9
JM		 1136Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1137
1138 * interp.c (sim_monitor): Flush output before reading input.
1139
1140Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1141
1142 * tconfig.in (SIM_HANDLES_LMA): Always define.
1143
1144Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1145
1146 From Mark Salter <msalter@cygnus.com>:
1147 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1148 (sim_open): Add setup for BSP board.
1149
9846de1b
JM		 1150Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1151
1152 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1153 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1154 them as unimplemented.
1155
cd0fc7c3
SS		 11561999-05-08 Felix Lee <flee@cygnus.com>
1157
1158 * configure: Regenerated to track ../common/aclocal.m4 changes.
1159
7a292a7a
SS		 11601999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1161
1162 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1163
1164Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1165
1166 * configure.in: Any mips64vr5*-*-* target should have
1167 -DTARGET_ENABLE_FR=1.
1168 (default_endian): Any mips64vr*el-*-* target should default to
1169 LITTLE_ENDIAN.
1170 * configure: Re-generate.
1171
11721999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1173
1174 * mips.igen (ldl): Extend from _16_, not 32.
1175
1176Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1177
1178 * interp.c (sim_store_register): Force registers written to by GDB
1179 into an un-interpreted state.
1180
c906108c
SS		 11811999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1182
1183 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1184 CPU, start periodic background I/O polls.
1185 (tx3904sio_poll): New function: periodic I/O poller.
1186
11871998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1188
1189 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
1190
1191Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1192
1193 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1194 case statement.
1195
11961998-12-29 Frank Ch. Eigler <fche@cygnus.com>
1197
1198 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
1199 (load_word): Call SIM_CORE_SIGNAL hook on error.
1200 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1201 starting. For exception dispatching, pass PC instead of NULL_CIA.
1202 (decode_coproc): Use COP0_BADVADDR to store faulting address.
1203 * sim-main.h (COP0_BADVADDR): Define.
1204 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1205 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
1206 (_sim_cpu): Add exc_* fields to store register value snapshots.
1207 * mips.igen (*): Replace memory-related SignalException* calls
1208 with references to SIM_CORE_SIGNAL hook.
1209
1210 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1211 fix.
1212 * sim-main.c (*): Minor warning cleanups.
1213
12141998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1215
1216 * m16.igen (DADDIU5): Correct type-o.
1217
1218Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1219
1220 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1221 variables.
1222
1223Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1224
1225 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1226 to include path.
1227 (interp.o): Add dependency on itable.h
1228 (oengine.c, gencode): Delete remaining references.
1229 (BUILT_SRC_FROM_GEN): Clean up.
1230
12311998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
1232
1233 * vr4run.c: New.
1234 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1235 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1236 tmp-run-hack) : New.
1237 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
1238 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
1239 Drop the "64" qualifier to get the HACK generator working.
1240 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1241 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1242 qualifier to get the hack generator working.
1243 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1244 (DSLL): Use do_dsll.
1245 (DSLLV): Use do_dsllv.
1246 (DSRA): Use do_dsra.
1247 (DSRL): Use do_dsrl.
1248 (DSRLV): Use do_dsrlv.
1249 (BC1): Move *vr4100 to get the HACK generator working.
1250 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
1251 get the HACK generator working.
1252 (MACC) Rename to get the HACK generator working.
1253 (DMACC,MACCS,DMACCS): Add the 64.
1254
12551998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1256
1257 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1258 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1259
12601998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1261
1262 * mips/interp.c (DEBUG): Cleanups.
1263
12641998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1265
1266 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1267 (tx3904sio_tickle): fflush after a stdout character output.
1268
12691998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1270
1271 * interp.c (sim_close): Uninstall modules.
1272
1273Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1274
1275 * sim-main.h, interp.c (sim_monitor): Change to global
1276 function.
1277
1278Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1279
1280 * configure.in (vr4100): Only include vr4100 instructions in
1281 simulator.
1282 * configure: Re-generate.
1283 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1284
1285Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1286
1287 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1288 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1289 true alternative.
1290
1291 * configure.in (sim_default_gen, sim_use_gen): Replace with
1292 sim_gen.
1293 (--enable-sim-igen): Delete config option. Always using IGEN.
1294 * configure: Re-generate.
1295
1296 * Makefile.in (gencode): Kill, kill, kill.
1297 * gencode.c: Ditto.
1298
1299Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1300
1301 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1302 bit mips16 igen simulator.
1303 * configure: Re-generate.
1304
1305 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1306 as part of vr4100 ISA.
1307 * vr.igen: Mark all instructions as 64 bit only.
1308
1309Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1310
1311 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1312 Pacify GCC.
1313
1314Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1315
1316 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1317 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1318 * configure: Re-generate.
1319
1320 * m16.igen (BREAK): Define breakpoint instruction.
1321 (JALX32): Mark instruction as mips16 and not r3900.
1322 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1323
1324 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1325
1326Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1327
1328 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1329 insn as a debug breakpoint.
1330
1331 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1332 pending.slot_size.
1333 (PENDING_SCHED): Clean up trace statement.
1334 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1335 (PENDING_FILL): Delay write by only one cycle.
1336 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1337
1338 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1339 of pending writes.
1340 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1341 32 & 64.
1342 (pending_tick): Move incrementing of index to FOR statement.
1343 (pending_tick): Only update PENDING_OUT after a write has occured.
1344
1345 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1346 build simulator.
1347 * configure: Re-generate.
1348
1349 * interp.c (sim_engine_run OLD): Delete explicit call to
1350 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1351
1352Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1353
1354 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1355 interrupt level number to match changed SignalExceptionInterrupt
1356 macro.
1357
1358Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1359
1360 * interp.c: #include "itable.h" if WITH_IGEN.
1361 (get_insn_name): New function.
1362 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1363 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1364
1365Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1366
1367 * configure: Rebuilt to inhale new common/aclocal.m4.
1368
1369Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1370
1371 * dv-tx3904sio.c: Include sim-assert.h.
1372
1373Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1374
1375 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1376 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1377 Reorganize target-specific sim-hardware checks.
1378 * configure: rebuilt.
1379 * interp.c (sim_open): For tx39 target boards, set
1380 OPERATING_ENVIRONMENT, add tx3904sio devices.
1381 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1382 ROM executables. Install dv-sockser into sim-modules list.
1383
1384 * dv-tx3904irc.c: Compiler warning clean-up.
1385 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1386 frequent hw-trace messages.
1387
1388Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1389
1390 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1391
1392Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1393
1394 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1395
1396 * vr.igen: New file.
1397 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1398 * mips.igen: Define vr4100 model. Include vr.igen.
1399Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1400
1401 * mips.igen (check_mf_hilo): Correct check.
1402
1403Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1404
1405 * sim-main.h (interrupt_event): Add prototype.
1406
1407 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1408 register_ptr, register_value.
1409 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1410
1411 * sim-main.h (tracefh): Make extern.
1412
1413Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1414
1415 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1416 Reduce unnecessarily high timer event frequency.
1417 * dv-tx3904cpu.c: Ditto for interrupt event.
1418
1419Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1420
1421 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1422 to allay warnings.
1423 (interrupt_event): Made non-static.
1424
1425 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1426 interchange of configuration values for external vs. internal
1427 clock dividers.
1428
1429Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1430
1431 * mips.igen (BREAK): Moved code to here for
1432 simulator-reserved break instructions.
1433 * gencode.c (build_instruction): Ditto.
1434 * interp.c (signal_exception): Code moved from here. Non-
1435 reserved instructions now use exception vector, rather
1436 than halting sim.
1437 * sim-main.h: Moved magic constants to here.
1438
1439Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1440
1441 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1442 register upon non-zero interrupt event level, clear upon zero
1443 event value.
1444 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1445 by passing zero event value.
1446 (*_io_{read,write}_buffer): Endianness fixes.
1447 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1448 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1449
1450 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1451 serial I/O and timer module at base address 0xFFFF0000.
1452
1453Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1454
1455 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1456 and BigEndianCPU.
1457
1458Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1459
1460 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1461 parts.
1462 * configure: Update.
1463
1464Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1465
1466 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1467 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1468 * configure.in: Include tx3904tmr in hw_device list.
1469 * configure: Rebuilt.
1470 * interp.c (sim_open): Instantiate three timer instances.
1471 Fix address typo of tx3904irc instance.
1472
1473Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1474
1475 * interp.c (signal_exception): SystemCall exception now uses
1476 the exception vector.
1477
1478Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1479
1480 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1481 to allay warnings.
1482
1483Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1484
1485 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1486
1487Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1488
1489 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1490
1491 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1492 sim-main.h. Declare a struct hw_descriptor instead of struct
1493 hw_device_descriptor.
1494
1495Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1496
1497 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1498 right bits and then re-align left hand bytes to correct byte
1499 lanes. Fix incorrect computation in do_store_left when loading
1500 bytes from second word.
1501
1502Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1503
1504 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1505 * interp.c (sim_open): Only create a device tree when HW is
1506 enabled.
1507
1508 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1509 * interp.c (signal_exception): Ditto.
1510
1511Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1512
1513 * gencode.c: Mark BEGEZALL as LIKELY.
1514
1515Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1516
1517 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1518 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1519
1520Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1521
1522 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1523 modules. Recognize TX39 target with "mips*tx39" pattern.
1524 * configure: Rebuilt.
1525 * sim-main.h (*): Added many macros defining bits in
1526 TX39 control registers.
1527 (SignalInterrupt): Send actual PC instead of NULL.
1528 (SignalNMIReset): New exception type.
1529 * interp.c (board): New variable for future use to identify
1530 a particular board being simulated.
1531 (mips_option_handler,mips_options): Added "--board" option.
1532 (interrupt_event): Send actual PC.
1533 (sim_open): Make memory layout conditional on board setting.
1534 (signal_exception): Initial implementation of hardware interrupt
1535 handling. Accept another break instruction variant for simulator
1536 exit.
1537 (decode_coproc): Implement RFE instruction for TX39.
1538 (mips.igen): Decode RFE instruction as such.
1539 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1540 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1541 bbegin to implement memory map.
1542 * dv-tx3904cpu.c: New file.
1543 * dv-tx3904irc.c: New file.
1544
1545Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1546
1547 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1548
1549Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1550
1551 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1552 with calls to check_div_hilo.
1553
1554Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1555
1556 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1557 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1558 Add special r3900 version of do_mult_hilo.
1559 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1560 with calls to check_mult_hilo.
1561 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1562 with calls to check_div_hilo.
1563
1564Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1565
1566 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1567 Document a replacement.
1568
1569Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1570
1571 * interp.c (sim_monitor): Make mon_printf work.
1572
1573Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1574
1575 * sim-main.h (INSN_NAME): New arg `cpu'.
1576
1577Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1578
1579 * configure: Regenerated to track ../common/aclocal.m4 changes.
1580
1581Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1582
1583 * configure: Regenerated to track ../common/aclocal.m4 changes.
1584 * config.in: Ditto.
1585
1586Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1587
1588 * acconfig.h: New file.
1589 * configure.in: Reverted change of Apr 24; use sinclude again.
1590
1591Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1592
1593 * configure: Regenerated to track ../common/aclocal.m4 changes.
1594 * config.in: Ditto.
1595
1596Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1597
1598 * configure.in: Don't call sinclude.
1599
1600Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1601
1602 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1603
1604Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1605
1606 * mips.igen (ERET): Implement.
1607
1608 * interp.c (decode_coproc): Return sign-extended EPC.
1609
1610 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1611
1612 * interp.c (signal_exception): Do not ignore Trap.
1613 (signal_exception): On TRAP, restart at exception address.
1614 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1615 (signal_exception): Update.
1616 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1617 so that TRAP instructions are caught.
1618
1619Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1620
1621 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1622 contains HI/LO access history.
1623 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1624 (HIACCESS, LOACCESS): Delete, replace with
1625 (HIHISTORY, LOHISTORY): New macros.
1626 (CHECKHILO): Delete all, moved to mips.igen
1627
1628 * gencode.c (build_instruction): Do not generate checks for
1629 correct HI/LO register usage.
1630
1631 * interp.c (old_engine_run): Delete checks for correct HI/LO
1632 register usage.
1633
1634 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1635 check_mf_cycles): New functions.
1636 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1637 do_divu, domultx, do_mult, do_multu): Use.
1638
1639 * tx.igen ("madd", "maddu"): Use.
1640
1641Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1642
1643 * mips.igen (DSRAV): Use function do_dsrav.
1644 (SRAV): Use new function do_srav.
1645
1646 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1647 (B): Sign extend 11 bit immediate.
1648 (EXT-B*): Shift 16 bit immediate left by 1.
1649 (ADDIU*): Don't sign extend immediate value.
1650
1651Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1652
1653 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1654
1655 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1656 functions.
1657
1658 * mips.igen (delayslot32, nullify_next_insn): New functions.
1659 (m16.igen): Always include.
1660 (do_*): Add more tracing.
1661
1662 * m16.igen (delayslot16): Add NIA argument, could be called by a
1663 32 bit MIPS16 instruction.
1664
1665 * interp.c (ifetch16): Move function from here.
1666 * sim-main.c (ifetch16): To here.
1667
1668 * sim-main.c (ifetch16, ifetch32): Update to match current
1669 implementations of LH, LW.
1670 (signal_exception): Don't print out incorrect hex value of illegal
1671 instruction.
1672
1673Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1674
1675 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1676 instruction.
1677
1678 * m16.igen: Implement MIPS16 instructions.
1679
1680 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1681 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1682 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1683 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1684 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1685 bodies of corresponding code from 32 bit insn to these. Also used
1686 by MIPS16 versions of functions.
1687
1688 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1689 (IMEM16): Drop NR argument from macro.
1690
1691Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1692
1693 * Makefile.in (SIM_OBJS): Add sim-main.o.
1694
1695 * sim-main.h (address_translation, load_memory, store_memory,
1696 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1697 as INLINE_SIM_MAIN.
1698 (pr_addr, pr_uword64): Declare.
1699 (sim-main.c): Include when H_REVEALS_MODULE_P.
1700
1701 * interp.c (address_translation, load_memory, store_memory,
1702 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1703 from here.
1704 * sim-main.c: To here. Fix compilation problems.
1705
1706 * configure.in: Enable inlining.
1707 * configure: Re-config.
1708
1709Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1710
1711 * configure: Regenerated to track ../common/aclocal.m4 changes.
1712
1713Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1714
1715 * mips.igen: Include tx.igen.
1716 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1717 * tx.igen: New file, contains MADD and MADDU.
1718
1719 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1720 the hardwired constant `7'.
1721 (store_memory): Ditto.
1722 (LOADDRMASK): Move definition to sim-main.h.
1723
1724 mips.igen (MTC0): Enable for r3900.
1725 (ADDU): Add trace.
1726
1727 mips.igen (do_load_byte): Delete.
1728 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1729 do_store_right): New functions.
1730 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1731
1732 configure.in: Let the tx39 use igen again.
1733 configure: Update.
1734
1735Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1736
1737 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1738 not an address sized quantity. Return zero for cache sizes.
1739
1740Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1741
1742 * mips.igen (r3900): r3900 does not support 64 bit integer
1743 operations.
1744
1745Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1746
1747 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1748 than igen one.
1749 * configure : Rebuild.
1750
1751Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1752
1753 * configure: Regenerated to track ../common/aclocal.m4 changes.
1754
1755Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1756
1757 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1758
1759Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1760
1761 * configure: Regenerated to track ../common/aclocal.m4 changes.
1762 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1763
1764Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1765
1766 * configure: Regenerated to track ../common/aclocal.m4 changes.
1767
1768Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1769
1770 * interp.c (Max, Min): Comment out functions. Not yet used.
1771
1772Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1773
1774 * configure: Regenerated to track ../common/aclocal.m4 changes.
1775
1776Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1777
1778 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1779 configurable settings for stand-alone simulator.
1780
1781 * configure.in: Added X11 search, just in case.
1782
1783 * configure: Regenerated.
1784
1785Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1786
1787 * interp.c (sim_write, sim_read, load_memory, store_memory):
1788 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1789
1790Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1791
1792 * sim-main.h (GETFCC): Return an unsigned value.
1793
1794Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1795
1796 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1797 (DADD): Result destination is RD not RT.
1798
1799Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1800
1801 * sim-main.h (HIACCESS, LOACCESS): Always define.
1802
1803 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1804
1805 * interp.c (sim_info): Delete.
1806
1807Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1808
1809 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1810 (mips_option_handler): New argument `cpu'.
1811 (sim_open): Update call to sim_add_option_table.
1812
1813Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1814
1815 * mips.igen (CxC1): Add tracing.
1816
1817Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1818
1819 * sim-main.h (Max, Min): Declare.
1820
1821 * interp.c (Max, Min): New functions.
1822
1823 * mips.igen (BC1): Add tracing.
1824
1825Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1826
1827 * interp.c Added memory map for stack in vr4100
1828
1829Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1830
1831 * interp.c (load_memory): Add missing "break"'s.
1832
1833Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1834
1835 * interp.c (sim_store_register, sim_fetch_register): Pass in
1836 length parameter. Return -1.
1837
1838Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1839
1840 * interp.c: Added hardware init hook, fixed warnings.
1841
1842Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1843
1844 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1845
1846Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1847
1848 * interp.c (ifetch16): New function.
1849
1850 * sim-main.h (IMEM32): Rename IMEM.
1851 (IMEM16_IMMED): Define.
1852 (IMEM16): Define.
1853 (DELAY_SLOT): Update.
1854
1855 * m16run.c (sim_engine_run): New file.
1856
1857 * m16.igen: All instructions except LB.
1858 (LB): Call do_load_byte.
1859 * mips.igen (do_load_byte): New function.
1860 (LB): Call do_load_byte.
1861
1862 * mips.igen: Move spec for insn bit size and high bit from here.
1863 * Makefile.in (tmp-igen, tmp-m16): To here.
1864
1865 * m16.dc: New file, decode mips16 instructions.
1866
1867 * Makefile.in (SIM_NO_ALL): Define.
1868 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1869
1870Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1871
1872 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1873 point unit to 32 bit registers.
1874 * configure: Re-generate.
1875
1876Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1877
1878 * configure.in (sim_use_gen): Make IGEN the default simulator
1879 generator for generic 32 and 64 bit mips targets.
1880 * configure: Re-generate.
1881
1882Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1883
1884 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1885 bitsize.
1886
1887 * interp.c (sim_fetch_register, sim_store_register): Read/write
1888 FGR from correct location.
1889 (sim_open): Set size of FGR's according to
1890 WITH_TARGET_FLOATING_POINT_BITSIZE.
1891
1892 * sim-main.h (FGR): Store floating point registers in a separate
1893 array.
1894
1895Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1896
1897 * configure: Regenerated to track ../common/aclocal.m4 changes.
1898
1899Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1900
1901 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1902
1903 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1904
1905 * interp.c (pending_tick): New function. Deliver pending writes.
1906
1907 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1908 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1909 it can handle mixed sized quantites and single bits.
1910
1911Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1912
1913 * interp.c (oengine.h): Do not include when building with IGEN.
1914 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1915 (sim_info): Ditto for PROCESSOR_64BIT.
1916 (sim_monitor): Replace ut_reg with unsigned_word.
1917 (*): Ditto for t_reg.
1918 (LOADDRMASK): Define.
1919 (sim_open): Remove defunct check that host FP is IEEE compliant,
1920 using software to emulate floating point.
1921 (value_fpr, ...): Always compile, was conditional on HASFPU.
1922
1923Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1924
1925 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1926 size.
1927
1928 * interp.c (SD, CPU): Define.
1929 (mips_option_handler): Set flags in each CPU.
1930 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1931 (sim_close): Do not clear STATE, deleted anyway.
1932 (sim_write, sim_read): Assume CPU zero's vm should be used for
1933 data transfers.
1934 (sim_create_inferior): Set the PC for all processors.
1935 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1936 argument.
1937 (mips16_entry): Pass correct nr of args to store_word, load_word.
1938 (ColdReset): Cold reset all cpu's.
1939 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1940 (sim_monitor, load_memory, store_memory, signal_exception): Use
1941 `CPU' instead of STATE_CPU.
1942
1943
1944 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1945 SD or CPU_.
1946
1947 * sim-main.h (signal_exception): Add sim_cpu arg.
1948 (SignalException*): Pass both SD and CPU to signal_exception.
1949 * interp.c (signal_exception): Update.
1950
1951 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1952 Ditto
1953 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1954 address_translation): Ditto
1955 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1956
1957Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1958
1959 * configure: Regenerated to track ../common/aclocal.m4 changes.
1960
1961Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1962
1963 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1964
1965 * mips.igen (model): Map processor names onto BFD name.
1966
1967 * sim-main.h (CPU_CIA): Delete.
1968 (SET_CIA, GET_CIA): Define
1969
1970Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1971
1972 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1973 regiser.
1974
1975 * configure.in (default_endian): Configure a big-endian simulator
1976 by default.
1977 * configure: Re-generate.
1978
1979Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1980
1981 * configure: Regenerated to track ../common/aclocal.m4 changes.
1982
1983Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1984
1985 * interp.c (sim_monitor): Handle Densan monitor outbyte
1986 and inbyte functions.
1987
19881997-12-29 Felix Lee <flee@cygnus.com>
1989
1990 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1991
1992Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1993
1994 * Makefile.in (tmp-igen): Arrange for $zero to always be
1995 reset to zero after every instruction.
1996
1997Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1998
1999 * configure: Regenerated to track ../common/aclocal.m4 changes.
2000 * config.in: Ditto.
2001
2002Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2003
2004 * mips.igen (MSUB): Fix to work like MADD.
2005 * gencode.c (MSUB): Similarly.
2006
2007Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2008
2009 * configure: Regenerated to track ../common/aclocal.m4 changes.
2010
2011Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2012
2013 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2014
2015Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2016
2017 * sim-main.h (sim-fpu.h): Include.
2018
2019 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2020 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2021 using host independant sim_fpu module.
2022
2023Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2024
2025 * interp.c (signal_exception): Report internal errors with SIGABRT
2026 not SIGQUIT.
2027
2028 * sim-main.h (C0_CONFIG): New register.
2029 (signal.h): No longer include.
2030
2031 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2032
2033Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2034
2035 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2036
2037Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2038
2039 * mips.igen: Tag vr5000 instructions.
2040 (ANDI): Was missing mipsIV model, fix assembler syntax.
2041 (do_c_cond_fmt): New function.
2042 (C.cond.fmt): Handle mips I-III which do not support CC field
2043 separatly.
2044 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2045 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2046 in IV3.2 spec.
2047 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2048 vr5000 which saves LO in a GPR separatly.
2049
2050 * configure.in (enable-sim-igen): For vr5000, select vr5000
2051 specific instructions.
2052 * configure: Re-generate.
2053
2054Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2055
2056 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2057
2058 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2059 fmt_uninterpreted_64 bit cases to switch. Convert to
2060 fmt_formatted,
2061
2062 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2063
2064 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2065 as specified in IV3.2 spec.
2066 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2067
2068Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2069
2070 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2071 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2072 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2073 PENDING_FILL versions of instructions. Simplify.
2074 (X): New function.
2075 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2076 instructions.
2077 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2078 a signed value.
2079 (MTHI, MFHI): Disable code checking HI-LO.
2080
2081 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2082 global.
2083 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2084
2085Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2086
2087 * gencode.c (build_mips16_operands): Replace IPC with cia.
2088
2089 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2090 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2091 IPC to `cia'.
2092 (UndefinedResult): Replace function with macro/function
2093 combination.
2094 (sim_engine_run): Don't save PC in IPC.
2095
2096 * sim-main.h (IPC): Delete.
2097
2098
2099 * interp.c (signal_exception, store_word, load_word,
2100 address_translation, load_memory, store_memory, cache_op,
2101 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2102 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2103 current instruction address - cia - argument.
2104 (sim_read, sim_write): Call address_translation directly.
2105 (sim_engine_run): Rename variable vaddr to cia.
2106 (signal_exception): Pass cia to sim_monitor
2107
2108 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2109 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2110 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2111
2112 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2113 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2114 SIM_ASSERT.
2115
2116 * interp.c (signal_exception): Pass restart address to
2117 sim_engine_restart.
2118
2119 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2120 idecode.o): Add dependency.
2121
2122 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2123 Delete definitions
2124 (DELAY_SLOT): Update NIA not PC with branch address.
2125 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2126
2127 * mips.igen: Use CIA not PC in branch calculations.
2128 (illegal): Call SignalException.
2129 (BEQ, ADDIU): Fix assembler.
2130
2131Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2132
2133 * m16.igen (JALX): Was missing.
2134
2135 * configure.in (enable-sim-igen): New configuration option.
2136 * configure: Re-generate.
2137
2138 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2139
2140 * interp.c (load_memory, store_memory): Delete parameter RAW.
2141 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2142 bypassing {load,store}_memory.
2143
2144 * sim-main.h (ByteSwapMem): Delete definition.
2145
2146 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2147
2148 * interp.c (sim_do_command, sim_commands): Delete mips specific
2149 commands. Handled by module sim-options.
2150
2151 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2152 (WITH_MODULO_MEMORY): Define.
2153
2154 * interp.c (sim_info): Delete code printing memory size.
2155
2156 * interp.c (mips_size): Nee sim_size, delete function.
2157 (power2): Delete.
2158 (monitor, monitor_base, monitor_size): Delete global variables.
2159 (sim_open, sim_close): Delete code creating monitor and other
2160 memory regions. Use sim-memopts module, via sim_do_commandf, to
2161 manage memory regions.
2162 (load_memory, store_memory): Use sim-core for memory model.
2163
2164 * interp.c (address_translation): Delete all memory map code
2165 except line forcing 32 bit addresses.
2166
2167Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2168
2169 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2170 trace options.
2171
2172 * interp.c (logfh, logfile): Delete globals.
2173 (sim_open, sim_close): Delete code opening & closing log file.
2174 (mips_option_handler): Delete -l and -n options.
2175 (OPTION mips_options): Ditto.
2176
2177 * interp.c (OPTION mips_options): Rename option trace to dinero.
2178 (mips_option_handler): Update.
2179
2180Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2181
2182 * interp.c (fetch_str): New function.
2183 (sim_monitor): Rewrite using sim_read & sim_write.
2184 (sim_open): Check magic number.
2185 (sim_open): Write monitor vectors into memory using sim_write.
2186 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2187 (sim_read, sim_write): Simplify - transfer data one byte at a
2188 time.
2189 (load_memory, store_memory): Clarify meaning of parameter RAW.
2190
2191 * sim-main.h (isHOST): Defete definition.
2192 (isTARGET): Mark as depreciated.
2193 (address_translation): Delete parameter HOST.
2194
2195 * interp.c (address_translation): Delete parameter HOST.
2196
2197Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2198
2199 * mips.igen:
2200
2201 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2202 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2203
2204Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2205
2206 * mips.igen: Add model filter field to records.
2207
2208Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2209
2210 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
2211
2212 interp.c (sim_engine_run): Do not compile function sim_engine_run
2213 when WITH_IGEN == 1.
2214
2215 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2216 target architecture.
2217
2218 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2219 igen. Replace with configuration variables sim_igen_flags /
2220 sim_m16_flags.
2221
2222 * m16.igen: New file. Copy mips16 insns here.
2223 * mips.igen: From here.
2224
2225Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2226
2227 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2228 to top.
2229 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2230
2231Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2232
2233 * gencode.c (build_instruction): Follow sim_write's lead in using
2234 BigEndianMem instead of !ByteSwapMem.
2235
2236Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2237
2238 * configure.in (sim_gen): Dependent on target, select type of
2239 generator. Always select old style generator.
2240
2241 configure: Re-generate.
2242
2243 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2244 targets.
2245 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2246 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2247 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2248 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2249 SIM_@sim_gen@_*, set by autoconf.
2250
2251Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2252
2253 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2254
2255 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2256 CURRENT_FLOATING_POINT instead.
2257
2258 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2259 (address_translation): Raise exception InstructionFetch when
2260 translation fails and isINSTRUCTION.
2261
2262 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2263 sim_engine_run): Change type of of vaddr and paddr to
2264 address_word.
2265 (address_translation, prefetch, load_memory, store_memory,
2266 cache_op): Change type of vAddr and pAddr to address_word.
2267
2268 * gencode.c (build_instruction): Change type of vaddr and paddr to
2269 address_word.
2270
2271Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2272
2273 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2274 macro to obtain result of ALU op.
2275
2276Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2277
2278 * interp.c (sim_info): Call profile_print.
2279
2280Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2281
2282 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2283
2284 * sim-main.h (WITH_PROFILE): Do not define, defined in
2285 common/sim-config.h. Use sim-profile module.
2286 (simPROFILE): Delete defintion.
2287
2288 * interp.c (PROFILE): Delete definition.
2289 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2290 (sim_close): Delete code writing profile histogram.
2291 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2292 Delete.
2293 (sim_engine_run): Delete code profiling the PC.
2294
2295Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2296
2297 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2298
2299 * interp.c (sim_monitor): Make register pointers of type
2300 unsigned_word*.
2301
2302 * sim-main.h: Make registers of type unsigned_word not
2303 signed_word.
2304
2305Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2306
2307 * interp.c (sync_operation): Rename from SyncOperation, make
2308 global, add SD argument.
2309 (prefetch): Rename from Prefetch, make global, add SD argument.
2310 (decode_coproc): Make global.
2311
2312 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2313
2314 * gencode.c (build_instruction): Generate DecodeCoproc not
2315 decode_coproc calls.
2316
2317 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2318 (SizeFGR): Move to sim-main.h
2319 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2320 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2321 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2322 sim-main.h.
2323 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2324 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2325 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2326 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2327 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2328 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2329
2330 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2331 exception.
2332 (sim-alu.h): Include.
2333 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2334 (sim_cia): Typedef to instruction_address.
2335
2336Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2337
2338 * Makefile.in (interp.o): Rename generated file engine.c to
2339 oengine.c.
2340
2341 * interp.c: Update.
2342
2343Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2344
2345 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2346
2347Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2348
2349 * gencode.c (build_instruction): For "FPSQRT", output correct
2350 number of arguments to Recip.
2351
2352Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2353
2354 * Makefile.in (interp.o): Depends on sim-main.h
2355
2356 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2357
2358 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2359 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2360 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2361 STATE, DSSTATE): Define
2362 (GPR, FGRIDX, ..): Define.
2363
2364 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2365 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2366 (GPR, FGRIDX, ...): Delete macros.
2367
2368 * interp.c: Update names to match defines from sim-main.h
2369
2370Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2371
2372 * interp.c (sim_monitor): Add SD argument.
2373 (sim_warning): Delete. Replace calls with calls to
2374 sim_io_eprintf.
2375 (sim_error): Delete. Replace calls with sim_io_error.
2376 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2377 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2378 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2379 argument.
2380 (mips_size): Rename from sim_size. Add SD argument.
2381
2382 * interp.c (simulator): Delete global variable.
2383 (callback): Delete global variable.
2384 (mips_option_handler, sim_open, sim_write, sim_read,
2385 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2386 sim_size,sim_monitor): Use sim_io_* not callback->*.
2387 (sim_open): ZALLOC simulator struct.
2388 (PROFILE): Do not define.
2389
2390Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2391
2392 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2393 support.h with corresponding code.
2394
2395 * sim-main.h (word64, uword64), support.h: Move definition to
2396 sim-main.h.
2397 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2398
2399 * support.h: Delete
2400 * Makefile.in: Update dependencies
2401 * interp.c: Do not include.
2402
2403Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2404
2405 * interp.c (address_translation, load_memory, store_memory,
2406 cache_op): Rename to from AddressTranslation et.al., make global,
2407 add SD argument
2408
2409 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2410 CacheOp): Define.
2411
2412 * interp.c (SignalException): Rename to signal_exception, make
2413 global.
2414
2415 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2416
2417 * sim-main.h (SignalException, SignalExceptionInterrupt,
2418 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2419 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2420 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2421 Define.
2422
2423 * interp.c, support.h: Use.
2424
2425Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2426
2427 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2428 to value_fpr / store_fpr. Add SD argument.
2429 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2430 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2431
2432 * sim-main.h (ValueFPR, StoreFPR): Define.
2433
2434Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2435
2436 * interp.c (sim_engine_run): Check consistency between configure
2437 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2438 and HASFPU.
2439
2440 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2441 (mips_fpu): Configure WITH_FLOATING_POINT.
2442 (mips_endian): Configure WITH_TARGET_ENDIAN.
2443 * configure: Update.
2444
2445Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2446
2447 * configure: Regenerated to track ../common/aclocal.m4 changes.
2448
2449Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2450
2451 * configure: Regenerated.
2452
2453Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2454
2455 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2456
2457Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2458
2459 * gencode.c (print_igen_insn_models): Assume certain architectures
2460 include all mips* instructions.
2461 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2462 instruction.
2463
2464 * Makefile.in (tmp.igen): Add target. Generate igen input from
2465 gencode file.
2466
2467 * gencode.c (FEATURE_IGEN): Define.
2468 (main): Add --igen option. Generate output in igen format.
2469 (process_instructions): Format output according to igen option.
2470 (print_igen_insn_format): New function.
2471 (print_igen_insn_models): New function.
2472 (process_instructions): Only issue warnings and ignore
2473 instructions when no FEATURE_IGEN.
2474
2475Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2476
2477 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2478 MIPS targets.
2479
2480Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2481
2482 * configure: Regenerated to track ../common/aclocal.m4 changes.
2483
2484Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2485
2486 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2487 SIM_RESERVED_BITS): Delete, moved to common.
2488 (SIM_EXTRA_CFLAGS): Update.
2489
2490Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2491
2492 * configure.in: Configure non-strict memory alignment.
2493 * configure: Regenerated to track ../common/aclocal.m4 changes.
2494
2495Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2496
2497 * configure: Regenerated to track ../common/aclocal.m4 changes.
2498
2499Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2500
2501 * gencode.c (SDBBP,DERET): Added (3900) insns.
2502 (RFE): Turn on for 3900.
2503 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2504 (dsstate): Made global.
2505 (SUBTARGET_R3900): Added.
2506 (CANCELDELAYSLOT): New.
2507 (SignalException): Ignore SystemCall rather than ignore and
2508 terminate. Add DebugBreakPoint handling.
2509 (decode_coproc): New insns RFE, DERET; and new registers Debug
2510 and DEPC protected by SUBTARGET_R3900.
2511 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2512 bits explicitly.
2513 * Makefile.in,configure.in: Add mips subtarget option.
2514 * configure: Update.
2515
2516Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2517
2518 * gencode.c: Add r3900 (tx39).
2519
2520
2521Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2522
2523 * gencode.c (build_instruction): Don't need to subtract 4 for
2524 JALR, just 2.
2525
2526Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2527
2528 * interp.c: Correct some HASFPU problems.
2529
2530Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2531
2532 * configure: Regenerated to track ../common/aclocal.m4 changes.
2533
2534Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2535
2536 * interp.c (mips_options): Fix samples option short form, should
2537 be `x'.
2538
2539Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2540
2541 * interp.c (sim_info): Enable info code. Was just returning.
2542
2543Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2544
2545 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2546 MFC0.
2547
2548Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2549
2550 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2551 constants.
2552 (build_instruction): Ditto for LL.
2553
2554Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2555
2556 * configure: Regenerated to track ../common/aclocal.m4 changes.
2557
2558Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2559
2560 * configure: Regenerated to track ../common/aclocal.m4 changes.
2561 * config.in: Ditto.
2562
2563Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2564
2565 * interp.c (sim_open): Add call to sim_analyze_program, update
2566 call to sim_config.
2567
2568Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2569
2570 * interp.c (sim_kill): Delete.
2571 (sim_create_inferior): Add ABFD argument. Set PC from same.
2572 (sim_load): Move code initializing trap handlers from here.
2573 (sim_open): To here.
2574 (sim_load): Delete, use sim-hload.c.
2575
2576 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2577
2578Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2579
2580 * configure: Regenerated to track ../common/aclocal.m4 changes.
2581 * config.in: Ditto.
2582
2583Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2584
2585 * interp.c (sim_open): Add ABFD argument.
2586 (sim_load): Move call to sim_config from here.
2587 (sim_open): To here. Check return status.
2588
2589Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2590
2591 * gencode.c (build_instruction): Two arg MADD should
2592 not assign result to $0.
2593
2594Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2595
2596 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2597 * sim/mips/configure.in: Regenerate.
2598
2599Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2600
2601 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2602 signed8, unsigned8 et.al. types.
2603
2604 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2605 hosts when selecting subreg.
2606
2607Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2608
2609 * interp.c (sim_engine_run): Reset the ZERO register to zero
2610 regardless of FEATURE_WARN_ZERO.
2611 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2612
2613Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2614
2615 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2616 (SignalException): For BreakPoints ignore any mode bits and just
2617 save the PC.
2618 (SignalException): Always set the CAUSE register.
2619
2620Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2621
2622 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2623 exception has been taken.
2624
2625 * interp.c: Implement the ERET and mt/f sr instructions.
2626
2627Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2628
2629 * interp.c (SignalException): Don't bother restarting an
2630 interrupt.
2631
2632Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2633
2634 * interp.c (SignalException): Really take an interrupt.
2635 (interrupt_event): Only deliver interrupts when enabled.
2636
2637Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2638
2639 * interp.c (sim_info): Only print info when verbose.
2640 (sim_info) Use sim_io_printf for output.
2641
2642Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2643
2644 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2645 mips architectures.
2646
2647Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2648
2649 * interp.c (sim_do_command): Check for common commands if a
2650 simulator specific command fails.
2651
2652Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2653
2654 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2655 and simBE when DEBUG is defined.
2656
2657Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2658
2659 * interp.c (interrupt_event): New function. Pass exception event
2660 onto exception handler.
2661
2662 * configure.in: Check for stdlib.h.
2663 * configure: Regenerate.
2664
2665 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2666 variable declaration.
2667 (build_instruction): Initialize memval1.
2668 (build_instruction): Add UNUSED attribute to byte, bigend,
2669 reverse.
2670 (build_operands): Ditto.
2671
2672 * interp.c: Fix GCC warnings.
2673 (sim_get_quit_code): Delete.
2674
2675 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2676 * Makefile.in: Ditto.
2677 * configure: Re-generate.
2678
2679 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2680
2681Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2682
2683 * interp.c (mips_option_handler): New function parse argumes using
2684 sim-options.
2685 (myname): Replace with STATE_MY_NAME.
2686 (sim_open): Delete check for host endianness - performed by
2687 sim_config.
2688 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2689 (sim_open): Move much of the initialization from here.
2690 (sim_load): To here. After the image has been loaded and
2691 endianness set.
2692 (sim_open): Move ColdReset from here.
2693 (sim_create_inferior): To here.
2694 (sim_open): Make FP check less dependant on host endianness.
2695
2696 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2697 run.
2698 * interp.c (sim_set_callbacks): Delete.
2699
2700 * interp.c (membank, membank_base, membank_size): Replace with
2701 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2702 (sim_open): Remove call to callback->init. gdb/run do this.
2703
2704 * interp.c: Update
2705
2706 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2707
2708 * interp.c (big_endian_p): Delete, replaced by
2709 current_target_byte_order.
2710
2711Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2712
2713 * interp.c (host_read_long, host_read_word, host_swap_word,
2714 host_swap_long): Delete. Using common sim-endian.
2715 (sim_fetch_register, sim_store_register): Use H2T.
2716 (pipeline_ticks): Delete. Handled by sim-events.
2717 (sim_info): Update.
2718 (sim_engine_run): Update.
2719
2720Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2721
2722 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2723 reason from here.
2724 (SignalException): To here. Signal using sim_engine_halt.
2725 (sim_stop_reason): Delete, moved to common.
2726
2727Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2728
2729 * interp.c (sim_open): Add callback argument.
2730 (sim_set_callbacks): Delete SIM_DESC argument.
2731 (sim_size): Ditto.
2732
2733Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2734
2735 * Makefile.in (SIM_OBJS): Add common modules.
2736
2737 * interp.c (sim_set_callbacks): Also set SD callback.
2738 (set_endianness, xfer_*, swap_*): Delete.
2739 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2740 Change to functions using sim-endian macros.
2741 (control_c, sim_stop): Delete, use common version.
2742 (simulate): Convert into.
2743 (sim_engine_run): This function.
2744 (sim_resume): Delete.
2745
2746 * interp.c (simulation): New variable - the simulator object.
2747 (sim_kind): Delete global - merged into simulation.
2748 (sim_load): Cleanup. Move PC assignment from here.
2749 (sim_create_inferior): To here.
2750
2751 * sim-main.h: New file.
2752 * interp.c (sim-main.h): Include.
2753
2754Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2755
2756 * configure: Regenerated to track ../common/aclocal.m4 changes.
2757
2758Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2759
2760 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2761
2762Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2763
2764 * gencode.c (build_instruction): DIV instructions: check
2765 for division by zero and integer overflow before using
2766 host's division operation.
2767
2768Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2769
2770 * Makefile.in (SIM_OBJS): Add sim-load.o.
2771 * interp.c: #include bfd.h.
2772 (target_byte_order): Delete.
2773 (sim_kind, myname, big_endian_p): New static locals.
2774 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2775 after argument parsing. Recognize -E arg, set endianness accordingly.
2776 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2777 load file into simulator. Set PC from bfd.
2778 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2779 (set_endianness): Use big_endian_p instead of target_byte_order.
2780
2781Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2782
2783 * interp.c (sim_size): Delete prototype - conflicts with
2784 definition in remote-sim.h. Correct definition.
2785
2786Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2787
2788 * configure: Regenerated to track ../common/aclocal.m4 changes.
2789 * config.in: Ditto.
2790
2791Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2792
2793 * interp.c (sim_open): New arg `kind'.
2794
2795 * configure: Regenerated to track ../common/aclocal.m4 changes.
2796
2797Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2798
2799 * configure: Regenerated to track ../common/aclocal.m4 changes.
2800
2801Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2802
2803 * interp.c (sim_open): Set optind to 0 before calling getopt.
2804
2805Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2806
2807 * configure: Regenerated to track ../common/aclocal.m4 changes.
2808
2809Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2810
2811 * interp.c : Replace uses of pr_addr with pr_uword64
2812 where the bit length is always 64 independent of SIM_ADDR.
2813 (pr_uword64) : added.
2814
2815Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2816
2817 * configure: Re-generate.
2818
2819Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2820
2821 * configure: Regenerate to track ../common/aclocal.m4 changes.
2822
2823Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2824
2825 * interp.c (sim_open): New SIM_DESC result. Argument is now
2826 in argv form.
2827 (other sim_*): New SIM_DESC argument.
2828
2829Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2830
2831 * interp.c: Fix printing of addresses for non-64-bit targets.
2832 (pr_addr): Add function to print address based on size.
2833
2834Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2835
2836 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2837
2838Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2839
2840 * gencode.c (build_mips16_operands): Correct computation of base
2841 address for extended PC relative instruction.
2842
2843Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2844
2845 * interp.c (mips16_entry): Add support for floating point cases.
2846 (SignalException): Pass floating point cases to mips16_entry.
2847 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2848 registers.
2849 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2850 or fmt_word.
2851 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2852 and then set the state to fmt_uninterpreted.
2853 (COP_SW): Temporarily set the state to fmt_word while calling
2854 ValueFPR.
2855
2856Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2857
2858 * gencode.c (build_instruction): The high order may be set in the
2859 comparison flags at any ISA level, not just ISA 4.
2860
2861Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2862
2863 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2864 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2865 * configure.in: sinclude ../common/aclocal.m4.
2866 * configure: Regenerated.
2867
2868Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2869
2870 * configure: Rebuild after change to aclocal.m4.
2871
2872Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2873
2874 * configure configure.in Makefile.in: Update to new configure
2875 scheme which is more compatible with WinGDB builds.
2876 * configure.in: Improve comment on how to run autoconf.
2877 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2878 * Makefile.in: Use autoconf substitution to install common
2879 makefile fragment.
2880
2881Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2882
2883 * gencode.c (build_instruction): Use BigEndianCPU instead of
2884 ByteSwapMem.
2885
2886Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2887
2888 * interp.c (sim_monitor): Make output to stdout visible in
2889 wingdb's I/O log window.
2890
2891Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2892
2893 * support.h: Undo previous change to SIGTRAP
2894 and SIGQUIT values.
2895
2896Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2897
2898 * interp.c (store_word, load_word): New static functions.
2899 (mips16_entry): New static function.
2900 (SignalException): Look for mips16 entry and exit instructions.
2901 (simulate): Use the correct index when setting fpr_state after
2902 doing a pending move.
2903
2904Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2905
2906 * interp.c: Fix byte-swapping code throughout to work on
2907 both little- and big-endian hosts.
2908
2909Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2910
2911 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2912 with gdb/config/i386/xm-windows.h.
2913
2914Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2915
2916 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2917 that messes up arithmetic shifts.
2918
2919Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2920
2921 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2922 SIGTRAP and SIGQUIT for _WIN32.
2923
2924Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2925
2926 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2927 force a 64 bit multiplication.
2928 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2929 destination register is 0, since that is the default mips16 nop
2930 instruction.
2931
2932Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2933
2934 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2935 (build_endian_shift): Don't check proc64.
2936 (build_instruction): Always set memval to uword64. Cast op2 to
2937 uword64 when shifting it left in memory instructions. Always use
2938 the same code for stores--don't special case proc64.
2939
2940 * gencode.c (build_mips16_operands): Fix base PC value for PC
2941 relative operands.
2942 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2943 jal instruction.
2944 * interp.c (simJALDELAYSLOT): Define.
2945 (JALDELAYSLOT): Define.
2946 (INDELAYSLOT, INJALDELAYSLOT): Define.
2947 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2948
2949Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2950
2951 * interp.c (sim_open): add flush_cache as a PMON routine
2952 (sim_monitor): handle flush_cache by ignoring it
2953
2954Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2955
2956 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2957 BigEndianMem.
2958 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2959 (BigEndianMem): Rename to ByteSwapMem and change sense.
2960 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2961 BigEndianMem references to !ByteSwapMem.
2962 (set_endianness): New function, with prototype.
2963 (sim_open): Call set_endianness.
2964 (sim_info): Use simBE instead of BigEndianMem.
2965 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2966 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2967 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2968 ifdefs, keeping the prototype declaration.
2969 (swap_word): Rewrite correctly.
2970 (ColdReset): Delete references to CONFIG. Delete endianness related
2971 code; moved to set_endianness.
2972
2973Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2974
2975 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2976 * interp.c (CHECKHILO): Define away.
2977 (simSIGINT): New macro.
2978 (membank_size): Increase from 1MB to 2MB.
2979 (control_c): New function.
2980 (sim_resume): Rename parameter signal to signal_number. Add local
2981 variable prev. Call signal before and after simulate.
2982 (sim_stop_reason): Add simSIGINT support.
2983 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2984 functions always.
2985 (sim_warning): Delete call to SignalException. Do call printf_filtered
2986 if logfh is NULL.
2987 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2988 a call to sim_warning.
2989
2990Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2991
2992 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2993 16 bit instructions.
2994
2995Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2996
2997 Add support for mips16 (16 bit MIPS implementation):
2998 * gencode.c (inst_type): Add mips16 instruction encoding types.
2999 (GETDATASIZEINSN): Define.
3000 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3001 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3002 mtlo.
3003 (MIPS16_DECODE): New table, for mips16 instructions.
3004 (bitmap_val): New static function.
3005 (struct mips16_op): Define.
3006 (mips16_op_table): New table, for mips16 operands.
3007 (build_mips16_operands): New static function.
3008 (process_instructions): If PC is odd, decode a mips16
3009 instruction. Break out instruction handling into new
3010 build_instruction function.
3011 (build_instruction): New static function, broken out of
3012 process_instructions. Check modifiers rather than flags for SHIFT
3013 bit count and m[ft]{hi,lo} direction.
3014 (usage): Pass program name to fprintf.
3015 (main): Remove unused variable this_option_optind. Change
3016 ``*loptarg++'' to ``loptarg++''.
3017 (my_strtoul): Parenthesize && within ||.
3018 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3019 (simulate): If PC is odd, fetch a 16 bit instruction, and
3020 increment PC by 2 rather than 4.
3021 * configure.in: Add case for mips16*-*-*.
3022 * configure: Rebuild.
3023
3024Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3025
3026 * interp.c: Allow -t to enable tracing in standalone simulator.
3027 Fix garbage output in trace file and error messages.
3028
3029Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3030
3031 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3032 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3033 * configure.in: Simplify using macros in ../common/aclocal.m4.
3034 * configure: Regenerated.
3035 * tconfig.in: New file.
3036
3037Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3038
3039 * interp.c: Fix bugs in 64-bit port.
3040 Use ansi function declarations for msvc compiler.
3041 Initialize and test file pointer in trace code.
3042 Prevent duplicate definition of LAST_EMED_REGNUM.
3043
3044Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3045
3046 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3047
3048Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3049
3050 * interp.c (SignalException): Check for explicit terminating
3051 breakpoint value.
3052 * gencode.c: Pass instruction value through SignalException()
3053 calls for Trap, Breakpoint and Syscall.
3054
3055Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3056
3057 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3058 only used on those hosts that provide it.
3059 * configure.in: Add sqrt() to list of functions to be checked for.
3060 * config.in: Re-generated.
3061 * configure: Re-generated.
3062
3063Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3064
3065 * gencode.c (process_instructions): Call build_endian_shift when
3066 expanding STORE RIGHT, to fix swr.
3067 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3068 clear the high bits.
3069 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3070 Fix float to int conversions to produce signed values.
3071
3072Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3073
3074 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3075 (process_instructions): Correct handling of nor instruction.
3076 Correct shift count for 32 bit shift instructions. Correct sign
3077 extension for arithmetic shifts to not shift the number of bits in
3078 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3079 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3080 Fix madd.
3081 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3082 It's OK to have a mult follow a mult. What's not OK is to have a
3083 mult follow an mfhi.
3084 (Convert): Comment out incorrect rounding code.
3085
3086Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3087
3088 * interp.c (sim_monitor): Improved monitor printf
3089 simulation. Tidied up simulator warnings, and added "--log" option
3090 for directing warning message output.
3091 * gencode.c: Use sim_warning() rather than WARNING macro.
3092
3093Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3094
3095 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3096 getopt1.o, rather than on gencode.c. Link objects together.
3097 Don't link against -liberty.
3098 (gencode.o, getopt.o, getopt1.o): New targets.
3099 * gencode.c: Include <ctype.h> and "ansidecl.h".
3100 (AND): Undefine after including "ansidecl.h".
3101 (ULONG_MAX): Define if not defined.
3102 (OP_*): Don't define macros; now defined in opcode/mips.h.
3103 (main): Call my_strtoul rather than strtoul.
3104 (my_strtoul): New static function.
3105
3106Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3107
3108 * gencode.c (process_instructions): Generate word64 and uword64
3109 instead of `long long' and `unsigned long long' data types.
3110 * interp.c: #include sysdep.h to get signals, and define default
3111 for SIGBUS.
3112 * (Convert): Work around for Visual-C++ compiler bug with type
3113 conversion.
3114 * support.h: Make things compile under Visual-C++ by using
3115 __int64 instead of `long long'. Change many refs to long long
3116 into word64/uword64 typedefs.
3117
3118Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3119
3120 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3121 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3122 (docdir): Removed.
3123 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3124 (AC_PROG_INSTALL): Added.
3125 (AC_PROG_CC): Moved to before configure.host call.
3126 * configure: Rebuilt.
3127
3128Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3129
3130 * configure.in: Define @SIMCONF@ depending on mips target.
3131 * configure: Rebuild.
3132 * Makefile.in (run): Add @SIMCONF@ to control simulator
3133 construction.
3134 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3135 * interp.c: Remove some debugging, provide more detailed error
3136 messages, update memory accesses to use LOADDRMASK.
3137
3138Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3139
3140 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3141 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3142 stamp-h.
3143 * configure: Rebuild.
3144 * config.in: New file, generated by autoheader.
3145 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3146 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3147 HAVE_ANINT and HAVE_AINT, as appropriate.
3148 * Makefile.in (run): Use @LIBS@ rather than -lm.
3149 (interp.o): Depend upon config.h.
3150 (Makefile): Just rebuild Makefile.
3151 (clean): Remove stamp-h.
3152 (mostlyclean): Make the same as clean, not as distclean.
3153 (config.h, stamp-h): New targets.
3154
3155Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3156
3157 * interp.c (ColdReset): Fix boolean test. Make all simulator
3158 globals static.
3159
3160Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3161
3162 * interp.c (xfer_direct_word, xfer_direct_long,
3163 swap_direct_word, swap_direct_long, xfer_big_word,
3164 xfer_big_long, xfer_little_word, xfer_little_long,
3165 swap_word,swap_long): Added.
3166 * interp.c (ColdReset): Provide function indirection to
3167 host<->simulated_target transfer routines.
3168 * interp.c (sim_store_register, sim_fetch_register): Updated to
3169 make use of indirected transfer routines.
3170
3171Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3172
3173 * gencode.c (process_instructions): Ensure FP ABS instruction
3174 recognised.
3175 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3176 system call support.
3177
3178Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3179
3180 * interp.c (sim_do_command): Complain if callback structure not
3181 initialised.
3182
3183Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3184
3185 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3186 support for Sun hosts.
3187 * Makefile.in (gencode): Ensure the host compiler and libraries
3188 used for cross-hosted build.
3189
3190Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3191
3192 * interp.c, gencode.c: Some more (TODO) tidying.
3193
3194Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3195
3196 * gencode.c, interp.c: Replaced explicit long long references with
3197 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3198 * support.h (SET64LO, SET64HI): Macros added.
3199
3200Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3201
3202 * configure: Regenerate with autoconf 2.7.
3203
3204Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3205
3206 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3207 * support.h: Remove superfluous "1" from #if.
3208 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3209
3210Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3211
3212 * interp.c (StoreFPR): Control UndefinedResult() call on
3213 WARN_RESULT manifest.
3214
3215Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3216
3217 * gencode.c: Tidied instruction decoding, and added FP instruction
3218 support.
3219
3220 * interp.c: Added dineroIII, and BSD profiling support. Also
3221 run-time FP handling.
3222
3223Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3224
3225 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3226 gencode.c, interp.c, support.h: created.
GDB Binutils - Deliverables
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