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2002-02-11 Chris Demetriou <cgd@broadcom.com>
[deliverable/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
9805e229
CD		 12002-02-11 Chris Demetriou <cgd@broadcom.com>
2
3 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
4 indicating that ALU32_END or ALU64_END are there to check
5 for overflow.
6 (DADD): Likewise, but also remove previous comment about
7 overflow checking.
8
f701dad2
CD		 92002-02-10 Chris Demetriou <cgd@broadcom.com>
10
11 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
12 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
13 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
14 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
15 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
16 fields (i.e., add and move commas) so that they more closely
17 match the MIPS ISA documentation opcode partitioning.
18
192002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098
CD		 20
21 * mips.igen (ADDI): Print immediate value.
22 (BREAK): Print code.
23 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
24 (SLL): Print "nop" specially, and don't run the code
25 that does the shift for the "nop" case.
26
9e52972e
FF		 272001-11-17 Fred Fish <fnf@redhat.com>
28
29 * sim-main.h (float_operation): Move enum declaration outside
30 of _sim_cpu struct declaration.
31
c0efbca4
JB		 322001-04-12 Jim Blandy <jimb@redhat.com>
33
34 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
35 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
36 set of the FCSR.
37 * sim-main.h (COCIDX): Remove definition; this isn't supported by
38 PENDING_FILL, and you can get the intended effect gracefully by
39 calling PENDING_SCHED directly.
40
fb891446
BE		 412001-02-23 Ben Elliston <bje@redhat.com>
42
43 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
44 already defined elsewhere.
45
8030f857
BE		 462001-02-19 Ben Elliston <bje@redhat.com>
47
48 * sim-main.h (sim_monitor): Return an int.
49 * interp.c (sim_monitor): Add return values.
50 (signal_exception): Handle error conditions from sim_monitor.
51
56b48a7a
CD		 522001-02-08 Ben Elliston <bje@redhat.com>
53
54 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
55 (store_memory): Likewise, pass cia to sim_core_write*.
56
d3ee60d9
FCE		 572000-10-19 Frank Ch. Eigler <fche@redhat.com>
58
59 On advice from Chris G. Demetriou <cgd@sibyte.com>:
60 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
61
071da002
AC		 62Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
63
64 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
65 * Makefile.in: Don't delete *.igen when cleaning directory.
66
a28c02cd
AC		 67Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
68
69 * m16.igen (break): Call SignalException not sim_engine_halt.
70
80ee11fa
AC		 71Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
72
73 From Jason Eckhardt:
74 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
75
673388c0
AC		 76Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
77
78 * mips.igen (MxC1, DMxC1): Fix printf formatting.
79
4c0deff4
NC		 802000-05-24 Michael Hayes <mhayes@cygnus.com>
81
82 * mips.igen (do_dmultx): Fix typo.
83
eb2d80b4
AC		 84Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
85
86 * configure: Regenerated to track ../common/aclocal.m4 changes.
87
dd37a34b
AC		 88Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
89
90 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
91
4c0deff4
NC		 922000-04-12 Frank Ch. Eigler <fche@redhat.com>
93
94 * sim-main.h (GPR_CLEAR): Define macro.
95
e30db738
AC		 96Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
97
98 * interp.c (decode_coproc): Output long using %lx and not %s.
99
cb7450ea
FCE		 1002000-03-21 Frank Ch. Eigler <fche@redhat.com>
101
102 * interp.c (sim_open): Sort & extend dummy memory regions for
103 --board=jmr3904 for eCos.
104
a3027dd7
FCE		 1052000-03-02 Frank Ch. Eigler <fche@redhat.com>
106
107 * configure: Regenerated.
108
109Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
110
111 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
112 calls, conditional on the simulator being in verbose mode.
113
dfcd3bfb
JM		 114Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
115
116 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
117 cache don't get ReservedInstruction traps.
118
c2d11a7d
JM		 1191999-11-29 Mark Salter <msalter@cygnus.com>
120
121 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
122 to clear status bits in sdisr register. This is how the hardware works.
123
124 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
125 being used by cygmon.
126
4ce44c66
JM		 1271999-11-11 Andrew Haley <aph@cygnus.com>
128
129 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
130 instructions.
131
cff3e48b
JM		 132Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
133
134 * mips.igen (MULT): Correct previous mis-applied patch.
135
d4f3574e
SS		 136Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
137
138 * mips.igen (delayslot32): Handle sequence like
139 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
140 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
141 (MULT): Actually pass the third register...
142
1431999-09-03 Mark Salter <msalter@cygnus.com>
144
145 * interp.c (sim_open): Added more memory aliases for additional
146 hardware being touched by cygmon on jmr3904 board.
147
148Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
149
150 * configure: Regenerated to track ../common/aclocal.m4 changes.
151
a0b3c4fd
JM		 152Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
153
154 * interp.c (sim_store_register): Handle case where client - GDB -
155 specifies that a 4 byte register is 8 bytes in size.
156 (sim_fetch_register): Ditto.
157
adf40b2e
JM		 1581999-07-14 Frank Ch. Eigler <fche@cygnus.com>
159
160 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
161 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
162 (idt_monitor_base): Base address for IDT monitor traps.
163 (pmon_monitor_base): Ditto for PMON.
164 (lsipmon_monitor_base): Ditto for LSI PMON.
165 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
166 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
167 (sim_firmware_command): New function.
168 (mips_option_handler): Call it for OPTION_FIRMWARE.
169 (sim_open): Allocate memory for idt_monitor region. If "--board"
170 option was given, add no monitor by default. Add BREAK hooks only if
171 monitors are also there.
172
43e526b9
JM		 173Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
174
175 * interp.c (sim_monitor): Flush output before reading input.
176
177Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
178
179 * tconfig.in (SIM_HANDLES_LMA): Always define.
180
181Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
182
183 From Mark Salter <msalter@cygnus.com>:
184 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
185 (sim_open): Add setup for BSP board.
186
9846de1b
JM		 187Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
188
189 * mips.igen (MULT, MULTU): Add syntax for two operand version.
190 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
191 them as unimplemented.
192
cd0fc7c3
SS		 1931999-05-08 Felix Lee <flee@cygnus.com>
194
195 * configure: Regenerated to track ../common/aclocal.m4 changes.
196
7a292a7a
SS		 1971999-04-21 Frank Ch. Eigler <fche@cygnus.com>
198
199 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
200
201Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
202
203 * configure.in: Any mips64vr5*-*-* target should have
204 -DTARGET_ENABLE_FR=1.
205 (default_endian): Any mips64vr*el-*-* target should default to
206 LITTLE_ENDIAN.
207 * configure: Re-generate.
208
2091999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
210
211 * mips.igen (ldl): Extend from _16_, not 32.
212
213Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
214
215 * interp.c (sim_store_register): Force registers written to by GDB
216 into an un-interpreted state.
217
c906108c
SS		 2181999-02-05 Frank Ch. Eigler <fche@cygnus.com>
219
220 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
221 CPU, start periodic background I/O polls.
222 (tx3904sio_poll): New function: periodic I/O poller.
223
2241998-12-30 Frank Ch. Eigler <fche@cygnus.com>
225
226 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
227
228Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
229
230 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
231 case statement.
232
2331998-12-29 Frank Ch. Eigler <fche@cygnus.com>
234
235 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
236 (load_word): Call SIM_CORE_SIGNAL hook on error.
237 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
238 starting. For exception dispatching, pass PC instead of NULL_CIA.
239 (decode_coproc): Use COP0_BADVADDR to store faulting address.
240 * sim-main.h (COP0_BADVADDR): Define.
241 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
242 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
243 (_sim_cpu): Add exc_* fields to store register value snapshots.
244 * mips.igen (*): Replace memory-related SignalException* calls
245 with references to SIM_CORE_SIGNAL hook.
246
247 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
248 fix.
249 * sim-main.c (*): Minor warning cleanups.
250
2511998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
252
253 * m16.igen (DADDIU5): Correct type-o.
254
255Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
256
257 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
258 variables.
259
260Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
261
262 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
263 to include path.
264 (interp.o): Add dependency on itable.h
265 (oengine.c, gencode): Delete remaining references.
266 (BUILT_SRC_FROM_GEN): Clean up.
267
2681998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
269
270 * vr4run.c: New.
271 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
272 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
273 tmp-run-hack) : New.
274 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
275 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
276 Drop the "64" qualifier to get the HACK generator working.
277 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
278 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
279 qualifier to get the hack generator working.
280 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
281 (DSLL): Use do_dsll.
282 (DSLLV): Use do_dsllv.
283 (DSRA): Use do_dsra.
284 (DSRL): Use do_dsrl.
285 (DSRLV): Use do_dsrlv.
286 (BC1): Move *vr4100 to get the HACK generator working.
287 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
288 get the HACK generator working.
289 (MACC) Rename to get the HACK generator working.
290 (DMACC,MACCS,DMACCS): Add the 64.
291
2921998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
293
294 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
295 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
296
2971998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
298
299 * mips/interp.c (DEBUG): Cleanups.
300
3011998-12-10 Frank Ch. Eigler <fche@cygnus.com>
302
303 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
304 (tx3904sio_tickle): fflush after a stdout character output.
305
3061998-12-03 Frank Ch. Eigler <fche@cygnus.com>
307
308 * interp.c (sim_close): Uninstall modules.
309
310Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
311
312 * sim-main.h, interp.c (sim_monitor): Change to global
313 function.
314
315Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
316
317 * configure.in (vr4100): Only include vr4100 instructions in
318 simulator.
319 * configure: Re-generate.
320 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
321
322Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
323
324 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
325 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
326 true alternative.
327
328 * configure.in (sim_default_gen, sim_use_gen): Replace with
329 sim_gen.
330 (--enable-sim-igen): Delete config option. Always using IGEN.
331 * configure: Re-generate.
332
333 * Makefile.in (gencode): Kill, kill, kill.
334 * gencode.c: Ditto.
335
336Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
337
338 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
339 bit mips16 igen simulator.
340 * configure: Re-generate.
341
342 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
343 as part of vr4100 ISA.
344 * vr.igen: Mark all instructions as 64 bit only.
345
346Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
347
348 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
349 Pacify GCC.
350
351Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
352
353 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
354 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
355 * configure: Re-generate.
356
357 * m16.igen (BREAK): Define breakpoint instruction.
358 (JALX32): Mark instruction as mips16 and not r3900.
359 * mips.igen (C.cond.fmt): Fix typo in instruction format.
360
361 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
362
363Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
364
365 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
366 insn as a debug breakpoint.
367
368 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
369 pending.slot_size.
370 (PENDING_SCHED): Clean up trace statement.
371 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
372 (PENDING_FILL): Delay write by only one cycle.
373 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
374
375 * sim-main.c (pending_tick): Clean up trace statements. Add trace
376 of pending writes.
377 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
378 32 & 64.
379 (pending_tick): Move incrementing of index to FOR statement.
380 (pending_tick): Only update PENDING_OUT after a write has occured.
381
382 * configure.in: Add explicit mips-lsi-* target. Use gencode to
383 build simulator.
384 * configure: Re-generate.
385
386 * interp.c (sim_engine_run OLD): Delete explicit call to
387 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
388
389Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
390
391 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
392 interrupt level number to match changed SignalExceptionInterrupt
393 macro.
394
395Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
396
397 * interp.c: #include "itable.h" if WITH_IGEN.
398 (get_insn_name): New function.
399 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
400 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
401
402Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
403
404 * configure: Rebuilt to inhale new common/aclocal.m4.
405
406Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
407
408 * dv-tx3904sio.c: Include sim-assert.h.
409
410Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
411
412 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
413 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
414 Reorganize target-specific sim-hardware checks.
415 * configure: rebuilt.
416 * interp.c (sim_open): For tx39 target boards, set
417 OPERATING_ENVIRONMENT, add tx3904sio devices.
418 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
419 ROM executables. Install dv-sockser into sim-modules list.
420
421 * dv-tx3904irc.c: Compiler warning clean-up.
422 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
423 frequent hw-trace messages.
424
425Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
426
427 * vr.igen (MulAcc): Identify as a vr4100 specific function.
428
429Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
430
431 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
432
433 * vr.igen: New file.
434 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
435 * mips.igen: Define vr4100 model. Include vr.igen.
436Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
437
438 * mips.igen (check_mf_hilo): Correct check.
439
440Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
441
442 * sim-main.h (interrupt_event): Add prototype.
443
444 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
445 register_ptr, register_value.
446 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
447
448 * sim-main.h (tracefh): Make extern.
449
450Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
451
452 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
453 Reduce unnecessarily high timer event frequency.
454 * dv-tx3904cpu.c: Ditto for interrupt event.
455
456Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
457
458 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
459 to allay warnings.
460 (interrupt_event): Made non-static.
461
462 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
463 interchange of configuration values for external vs. internal
464 clock dividers.
465
466Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
467
468 * mips.igen (BREAK): Moved code to here for
469 simulator-reserved break instructions.
470 * gencode.c (build_instruction): Ditto.
471 * interp.c (signal_exception): Code moved from here. Non-
472 reserved instructions now use exception vector, rather
473 than halting sim.
474 * sim-main.h: Moved magic constants to here.
475
476Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
477
478 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
479 register upon non-zero interrupt event level, clear upon zero
480 event value.
481 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
482 by passing zero event value.
483 (*_io_{read,write}_buffer): Endianness fixes.
484 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
485 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
486
487 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
488 serial I/O and timer module at base address 0xFFFF0000.
489
490Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
491
492 * mips.igen (SWC1) : Correct the handling of ReverseEndian
493 and BigEndianCPU.
494
495Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
496
497 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
498 parts.
499 * configure: Update.
500
501Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
502
503 * dv-tx3904tmr.c: New file - implements tx3904 timer.
504 * dv-tx3904{irc,cpu}.c: Mild reformatting.
505 * configure.in: Include tx3904tmr in hw_device list.
506 * configure: Rebuilt.
507 * interp.c (sim_open): Instantiate three timer instances.
508 Fix address typo of tx3904irc instance.
509
510Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
511
512 * interp.c (signal_exception): SystemCall exception now uses
513 the exception vector.
514
515Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
516
517 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
518 to allay warnings.
519
520Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
521
522 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
523
524Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
525
526 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
527
528 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
529 sim-main.h. Declare a struct hw_descriptor instead of struct
530 hw_device_descriptor.
531
532Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
533
534 * mips.igen (do_store_left, do_load_left): Compute nr of left and
535 right bits and then re-align left hand bytes to correct byte
536 lanes. Fix incorrect computation in do_store_left when loading
537 bytes from second word.
538
539Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
540
541 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
542 * interp.c (sim_open): Only create a device tree when HW is
543 enabled.
544
545 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
546 * interp.c (signal_exception): Ditto.
547
548Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
549
550 * gencode.c: Mark BEGEZALL as LIKELY.
551
552Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
553
554 * sim-main.h (ALU32_END): Sign extend 32 bit results.
555 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
556
557Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
558
559 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
560 modules. Recognize TX39 target with "mips*tx39" pattern.
561 * configure: Rebuilt.
562 * sim-main.h (*): Added many macros defining bits in
563 TX39 control registers.
564 (SignalInterrupt): Send actual PC instead of NULL.
565 (SignalNMIReset): New exception type.
566 * interp.c (board): New variable for future use to identify
567 a particular board being simulated.
568 (mips_option_handler,mips_options): Added "--board" option.
569 (interrupt_event): Send actual PC.
570 (sim_open): Make memory layout conditional on board setting.
571 (signal_exception): Initial implementation of hardware interrupt
572 handling. Accept another break instruction variant for simulator
573 exit.
574 (decode_coproc): Implement RFE instruction for TX39.
575 (mips.igen): Decode RFE instruction as such.
576 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
577 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
578 bbegin to implement memory map.
579 * dv-tx3904cpu.c: New file.
580 * dv-tx3904irc.c: New file.
581
582Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
583
584 * mips.igen (check_mt_hilo): Create a separate r3900 version.
585
586Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
587
588 * tx.igen (madd,maddu): Replace calls to check_op_hilo
589 with calls to check_div_hilo.
590
591Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
592
593 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
594 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
595 Add special r3900 version of do_mult_hilo.
596 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
597 with calls to check_mult_hilo.
598 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
599 with calls to check_div_hilo.
600
601Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
602
603 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
604 Document a replacement.
605
606Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
607
608 * interp.c (sim_monitor): Make mon_printf work.
609
610Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
611
612 * sim-main.h (INSN_NAME): New arg `cpu'.
613
614Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
615
616 * configure: Regenerated to track ../common/aclocal.m4 changes.
617
618Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
619
620 * configure: Regenerated to track ../common/aclocal.m4 changes.
621 * config.in: Ditto.
622
623Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
624
625 * acconfig.h: New file.
626 * configure.in: Reverted change of Apr 24; use sinclude again.
627
628Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
629
630 * configure: Regenerated to track ../common/aclocal.m4 changes.
631 * config.in: Ditto.
632
633Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
634
635 * configure.in: Don't call sinclude.
636
637Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
638
639 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
640
641Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
642
643 * mips.igen (ERET): Implement.
644
645 * interp.c (decode_coproc): Return sign-extended EPC.
646
647 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
648
649 * interp.c (signal_exception): Do not ignore Trap.
650 (signal_exception): On TRAP, restart at exception address.
651 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
652 (signal_exception): Update.
653 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
654 so that TRAP instructions are caught.
655
656Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
657
658 * sim-main.h (struct hilo_access, struct hilo_history): Define,
659 contains HI/LO access history.
660 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
661 (HIACCESS, LOACCESS): Delete, replace with
662 (HIHISTORY, LOHISTORY): New macros.
663 (CHECKHILO): Delete all, moved to mips.igen
664
665 * gencode.c (build_instruction): Do not generate checks for
666 correct HI/LO register usage.
667
668 * interp.c (old_engine_run): Delete checks for correct HI/LO
669 register usage.
670
671 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
672 check_mf_cycles): New functions.
673 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
674 do_divu, domultx, do_mult, do_multu): Use.
675
676 * tx.igen ("madd", "maddu"): Use.
677
678Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
679
680 * mips.igen (DSRAV): Use function do_dsrav.
681 (SRAV): Use new function do_srav.
682
683 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
684 (B): Sign extend 11 bit immediate.
685 (EXT-B*): Shift 16 bit immediate left by 1.
686 (ADDIU*): Don't sign extend immediate value.
687
688Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
689
690 * m16run.c (sim_engine_run): Restore CIA after handling an event.
691
692 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
693 functions.
694
695 * mips.igen (delayslot32, nullify_next_insn): New functions.
696 (m16.igen): Always include.
697 (do_*): Add more tracing.
698
699 * m16.igen (delayslot16): Add NIA argument, could be called by a
700 32 bit MIPS16 instruction.
701
702 * interp.c (ifetch16): Move function from here.
703 * sim-main.c (ifetch16): To here.
704
705 * sim-main.c (ifetch16, ifetch32): Update to match current
706 implementations of LH, LW.
707 (signal_exception): Don't print out incorrect hex value of illegal
708 instruction.
709
710Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
711
712 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
713 instruction.
714
715 * m16.igen: Implement MIPS16 instructions.
716
717 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
718 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
719 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
720 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
721 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
722 bodies of corresponding code from 32 bit insn to these. Also used
723 by MIPS16 versions of functions.
724
725 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
726 (IMEM16): Drop NR argument from macro.
727
728Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
729
730 * Makefile.in (SIM_OBJS): Add sim-main.o.
731
732 * sim-main.h (address_translation, load_memory, store_memory,
733 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
734 as INLINE_SIM_MAIN.
735 (pr_addr, pr_uword64): Declare.
736 (sim-main.c): Include when H_REVEALS_MODULE_P.
737
738 * interp.c (address_translation, load_memory, store_memory,
739 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
740 from here.
741 * sim-main.c: To here. Fix compilation problems.
742
743 * configure.in: Enable inlining.
744 * configure: Re-config.
745
746Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
747
748 * configure: Regenerated to track ../common/aclocal.m4 changes.
749
750Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
751
752 * mips.igen: Include tx.igen.
753 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
754 * tx.igen: New file, contains MADD and MADDU.
755
756 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
757 the hardwired constant `7'.
758 (store_memory): Ditto.
759 (LOADDRMASK): Move definition to sim-main.h.
760
761 mips.igen (MTC0): Enable for r3900.
762 (ADDU): Add trace.
763
764 mips.igen (do_load_byte): Delete.
765 (do_load, do_store, do_load_left, do_load_write, do_store_left,
766 do_store_right): New functions.
767 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
768
769 configure.in: Let the tx39 use igen again.
770 configure: Update.
771
772Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
773
774 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
775 not an address sized quantity. Return zero for cache sizes.
776
777Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
778
779 * mips.igen (r3900): r3900 does not support 64 bit integer
780 operations.
781
782Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
783
784 * configure.in (mipstx39*-*-*): Use gencode simulator rather
785 than igen one.
786 * configure : Rebuild.
787
788Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
789
790 * configure: Regenerated to track ../common/aclocal.m4 changes.
791
792Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
793
794 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
795
796Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
797
798 * configure: Regenerated to track ../common/aclocal.m4 changes.
799 * config.in: Regenerated to track ../common/aclocal.m4 changes.
800
801Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
802
803 * configure: Regenerated to track ../common/aclocal.m4 changes.
804
805Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
806
807 * interp.c (Max, Min): Comment out functions. Not yet used.
808
809Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
810
811 * configure: Regenerated to track ../common/aclocal.m4 changes.
812
813Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
814
815 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
816 configurable settings for stand-alone simulator.
817
818 * configure.in: Added X11 search, just in case.
819
820 * configure: Regenerated.
821
822Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
823
824 * interp.c (sim_write, sim_read, load_memory, store_memory):
825 Replace sim_core_*_map with read_map, write_map, exec_map resp.
826
827Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
828
829 * sim-main.h (GETFCC): Return an unsigned value.
830
831Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
832
833 * mips.igen (DIV): Fix check for -1 / MIN_INT.
834 (DADD): Result destination is RD not RT.
835
836Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
837
838 * sim-main.h (HIACCESS, LOACCESS): Always define.
839
840 * mdmx.igen (Maxi, Mini): Rename Max, Min.
841
842 * interp.c (sim_info): Delete.
843
844Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
845
846 * interp.c (DECLARE_OPTION_HANDLER): Use it.
847 (mips_option_handler): New argument `cpu'.
848 (sim_open): Update call to sim_add_option_table.
849
850Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
851
852 * mips.igen (CxC1): Add tracing.
853
854Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
855
856 * sim-main.h (Max, Min): Declare.
857
858 * interp.c (Max, Min): New functions.
859
860 * mips.igen (BC1): Add tracing.
861
862Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
863
864 * interp.c Added memory map for stack in vr4100
865
866Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
867
868 * interp.c (load_memory): Add missing "break"'s.
869
870Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
871
872 * interp.c (sim_store_register, sim_fetch_register): Pass in
873 length parameter. Return -1.
874
875Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
876
877 * interp.c: Added hardware init hook, fixed warnings.
878
879Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
880
881 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
882
883Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
884
885 * interp.c (ifetch16): New function.
886
887 * sim-main.h (IMEM32): Rename IMEM.
888 (IMEM16_IMMED): Define.
889 (IMEM16): Define.
890 (DELAY_SLOT): Update.
891
892 * m16run.c (sim_engine_run): New file.
893
894 * m16.igen: All instructions except LB.
895 (LB): Call do_load_byte.
896 * mips.igen (do_load_byte): New function.
897 (LB): Call do_load_byte.
898
899 * mips.igen: Move spec for insn bit size and high bit from here.
900 * Makefile.in (tmp-igen, tmp-m16): To here.
901
902 * m16.dc: New file, decode mips16 instructions.
903
904 * Makefile.in (SIM_NO_ALL): Define.
905 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
906
907Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
908
909 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
910 point unit to 32 bit registers.
911 * configure: Re-generate.
912
913Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
914
915 * configure.in (sim_use_gen): Make IGEN the default simulator
916 generator for generic 32 and 64 bit mips targets.
917 * configure: Re-generate.
918
919Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
920
921 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
922 bitsize.
923
924 * interp.c (sim_fetch_register, sim_store_register): Read/write
925 FGR from correct location.
926 (sim_open): Set size of FGR's according to
927 WITH_TARGET_FLOATING_POINT_BITSIZE.
928
929 * sim-main.h (FGR): Store floating point registers in a separate
930 array.
931
932Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
933
934 * configure: Regenerated to track ../common/aclocal.m4 changes.
935
936Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
937
938 * interp.c (ColdReset): Call PENDING_INVALIDATE.
939
940 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
941
942 * interp.c (pending_tick): New function. Deliver pending writes.
943
944 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
945 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
946 it can handle mixed sized quantites and single bits.
947
948Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
949
950 * interp.c (oengine.h): Do not include when building with IGEN.
951 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
952 (sim_info): Ditto for PROCESSOR_64BIT.
953 (sim_monitor): Replace ut_reg with unsigned_word.
954 (*): Ditto for t_reg.
955 (LOADDRMASK): Define.
956 (sim_open): Remove defunct check that host FP is IEEE compliant,
957 using software to emulate floating point.
958 (value_fpr, ...): Always compile, was conditional on HASFPU.
959
960Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
961
962 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
963 size.
964
965 * interp.c (SD, CPU): Define.
966 (mips_option_handler): Set flags in each CPU.
967 (interrupt_event): Assume CPU 0 is the one being iterrupted.
968 (sim_close): Do not clear STATE, deleted anyway.
969 (sim_write, sim_read): Assume CPU zero's vm should be used for
970 data transfers.
971 (sim_create_inferior): Set the PC for all processors.
972 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
973 argument.
974 (mips16_entry): Pass correct nr of args to store_word, load_word.
975 (ColdReset): Cold reset all cpu's.
976 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
977 (sim_monitor, load_memory, store_memory, signal_exception): Use
978 `CPU' instead of STATE_CPU.
979
980
981 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
982 SD or CPU_.
983
984 * sim-main.h (signal_exception): Add sim_cpu arg.
985 (SignalException*): Pass both SD and CPU to signal_exception.
986 * interp.c (signal_exception): Update.
987
988 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
989 Ditto
990 (sync_operation, prefetch, cache_op, store_memory, load_memory,
991 address_translation): Ditto
992 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
993
994Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
995
996 * configure: Regenerated to track ../common/aclocal.m4 changes.
997
998Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
999
1000 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1001
1002 * mips.igen (model): Map processor names onto BFD name.
1003
1004 * sim-main.h (CPU_CIA): Delete.
1005 (SET_CIA, GET_CIA): Define
1006
1007Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1008
1009 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1010 regiser.
1011
1012 * configure.in (default_endian): Configure a big-endian simulator
1013 by default.
1014 * configure: Re-generate.
1015
1016Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1017
1018 * configure: Regenerated to track ../common/aclocal.m4 changes.
1019
1020Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1021
1022 * interp.c (sim_monitor): Handle Densan monitor outbyte
1023 and inbyte functions.
1024
10251997-12-29 Felix Lee <flee@cygnus.com>
1026
1027 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1028
1029Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1030
1031 * Makefile.in (tmp-igen): Arrange for $zero to always be
1032 reset to zero after every instruction.
1033
1034Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1035
1036 * configure: Regenerated to track ../common/aclocal.m4 changes.
1037 * config.in: Ditto.
1038
1039Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1040
1041 * mips.igen (MSUB): Fix to work like MADD.
1042 * gencode.c (MSUB): Similarly.
1043
1044Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1045
1046 * configure: Regenerated to track ../common/aclocal.m4 changes.
1047
1048Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1049
1050 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1051
1052Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1053
1054 * sim-main.h (sim-fpu.h): Include.
1055
1056 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1057 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1058 using host independant sim_fpu module.
1059
1060Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1061
1062 * interp.c (signal_exception): Report internal errors with SIGABRT
1063 not SIGQUIT.
1064
1065 * sim-main.h (C0_CONFIG): New register.
1066 (signal.h): No longer include.
1067
1068 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1069
1070Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1071
1072 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1073
1074Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1075
1076 * mips.igen: Tag vr5000 instructions.
1077 (ANDI): Was missing mipsIV model, fix assembler syntax.
1078 (do_c_cond_fmt): New function.
1079 (C.cond.fmt): Handle mips I-III which do not support CC field
1080 separatly.
1081 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1082 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1083 in IV3.2 spec.
1084 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1085 vr5000 which saves LO in a GPR separatly.
1086
1087 * configure.in (enable-sim-igen): For vr5000, select vr5000
1088 specific instructions.
1089 * configure: Re-generate.
1090
1091Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1092
1093 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1094
1095 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1096 fmt_uninterpreted_64 bit cases to switch. Convert to
1097 fmt_formatted,
1098
1099 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1100
1101 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1102 as specified in IV3.2 spec.
1103 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1104
1105Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1106
1107 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1108 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1109 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1110 PENDING_FILL versions of instructions. Simplify.
1111 (X): New function.
1112 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1113 instructions.
1114 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1115 a signed value.
1116 (MTHI, MFHI): Disable code checking HI-LO.
1117
1118 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1119 global.
1120 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1121
1122Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1123
1124 * gencode.c (build_mips16_operands): Replace IPC with cia.
1125
1126 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1127 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1128 IPC to `cia'.
1129 (UndefinedResult): Replace function with macro/function
1130 combination.
1131 (sim_engine_run): Don't save PC in IPC.
1132
1133 * sim-main.h (IPC): Delete.
1134
1135
1136 * interp.c (signal_exception, store_word, load_word,
1137 address_translation, load_memory, store_memory, cache_op,
1138 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1139 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1140 current instruction address - cia - argument.
1141 (sim_read, sim_write): Call address_translation directly.
1142 (sim_engine_run): Rename variable vaddr to cia.
1143 (signal_exception): Pass cia to sim_monitor
1144
1145 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1146 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1147 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1148
1149 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1150 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1151 SIM_ASSERT.
1152
1153 * interp.c (signal_exception): Pass restart address to
1154 sim_engine_restart.
1155
1156 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1157 idecode.o): Add dependency.
1158
1159 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1160 Delete definitions
1161 (DELAY_SLOT): Update NIA not PC with branch address.
1162 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1163
1164 * mips.igen: Use CIA not PC in branch calculations.
1165 (illegal): Call SignalException.
1166 (BEQ, ADDIU): Fix assembler.
1167
1168Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1169
1170 * m16.igen (JALX): Was missing.
1171
1172 * configure.in (enable-sim-igen): New configuration option.
1173 * configure: Re-generate.
1174
1175 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1176
1177 * interp.c (load_memory, store_memory): Delete parameter RAW.
1178 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1179 bypassing {load,store}_memory.
1180
1181 * sim-main.h (ByteSwapMem): Delete definition.
1182
1183 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1184
1185 * interp.c (sim_do_command, sim_commands): Delete mips specific
1186 commands. Handled by module sim-options.
1187
1188 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1189 (WITH_MODULO_MEMORY): Define.
1190
1191 * interp.c (sim_info): Delete code printing memory size.
1192
1193 * interp.c (mips_size): Nee sim_size, delete function.
1194 (power2): Delete.
1195 (monitor, monitor_base, monitor_size): Delete global variables.
1196 (sim_open, sim_close): Delete code creating monitor and other
1197 memory regions. Use sim-memopts module, via sim_do_commandf, to
1198 manage memory regions.
1199 (load_memory, store_memory): Use sim-core for memory model.
1200
1201 * interp.c (address_translation): Delete all memory map code
1202 except line forcing 32 bit addresses.
1203
1204Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1205
1206 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1207 trace options.
1208
1209 * interp.c (logfh, logfile): Delete globals.
1210 (sim_open, sim_close): Delete code opening & closing log file.
1211 (mips_option_handler): Delete -l and -n options.
1212 (OPTION mips_options): Ditto.
1213
1214 * interp.c (OPTION mips_options): Rename option trace to dinero.
1215 (mips_option_handler): Update.
1216
1217Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1218
1219 * interp.c (fetch_str): New function.
1220 (sim_monitor): Rewrite using sim_read & sim_write.
1221 (sim_open): Check magic number.
1222 (sim_open): Write monitor vectors into memory using sim_write.
1223 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1224 (sim_read, sim_write): Simplify - transfer data one byte at a
1225 time.
1226 (load_memory, store_memory): Clarify meaning of parameter RAW.
1227
1228 * sim-main.h (isHOST): Defete definition.
1229 (isTARGET): Mark as depreciated.
1230 (address_translation): Delete parameter HOST.
1231
1232 * interp.c (address_translation): Delete parameter HOST.
1233
1234Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1235
1236 * mips.igen:
1237
1238 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1239 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1240
1241Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1242
1243 * mips.igen: Add model filter field to records.
1244
1245Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1246
1247 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1248
1249 interp.c (sim_engine_run): Do not compile function sim_engine_run
1250 when WITH_IGEN == 1.
1251
1252 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1253 target architecture.
1254
1255 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1256 igen. Replace with configuration variables sim_igen_flags /
1257 sim_m16_flags.
1258
1259 * m16.igen: New file. Copy mips16 insns here.
1260 * mips.igen: From here.
1261
1262Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1263
1264 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1265 to top.
1266 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1267
1268Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1269
1270 * gencode.c (build_instruction): Follow sim_write's lead in using
1271 BigEndianMem instead of !ByteSwapMem.
1272
1273Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1274
1275 * configure.in (sim_gen): Dependent on target, select type of
1276 generator. Always select old style generator.
1277
1278 configure: Re-generate.
1279
1280 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1281 targets.
1282 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1283 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1284 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1285 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1286 SIM_@sim_gen@_*, set by autoconf.
1287
1288Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1289
1290 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1291
1292 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1293 CURRENT_FLOATING_POINT instead.
1294
1295 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1296 (address_translation): Raise exception InstructionFetch when
1297 translation fails and isINSTRUCTION.
1298
1299 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1300 sim_engine_run): Change type of of vaddr and paddr to
1301 address_word.
1302 (address_translation, prefetch, load_memory, store_memory,
1303 cache_op): Change type of vAddr and pAddr to address_word.
1304
1305 * gencode.c (build_instruction): Change type of vaddr and paddr to
1306 address_word.
1307
1308Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1309
1310 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1311 macro to obtain result of ALU op.
1312
1313Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1314
1315 * interp.c (sim_info): Call profile_print.
1316
1317Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1318
1319 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1320
1321 * sim-main.h (WITH_PROFILE): Do not define, defined in
1322 common/sim-config.h. Use sim-profile module.
1323 (simPROFILE): Delete defintion.
1324
1325 * interp.c (PROFILE): Delete definition.
1326 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1327 (sim_close): Delete code writing profile histogram.
1328 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1329 Delete.
1330 (sim_engine_run): Delete code profiling the PC.
1331
1332Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1333
1334 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1335
1336 * interp.c (sim_monitor): Make register pointers of type
1337 unsigned_word*.
1338
1339 * sim-main.h: Make registers of type unsigned_word not
1340 signed_word.
1341
1342Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1343
1344 * interp.c (sync_operation): Rename from SyncOperation, make
1345 global, add SD argument.
1346 (prefetch): Rename from Prefetch, make global, add SD argument.
1347 (decode_coproc): Make global.
1348
1349 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1350
1351 * gencode.c (build_instruction): Generate DecodeCoproc not
1352 decode_coproc calls.
1353
1354 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1355 (SizeFGR): Move to sim-main.h
1356 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1357 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1358 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1359 sim-main.h.
1360 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1361 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1362 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1363 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1364 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1365 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1366
1367 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1368 exception.
1369 (sim-alu.h): Include.
1370 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1371 (sim_cia): Typedef to instruction_address.
1372
1373Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1374
1375 * Makefile.in (interp.o): Rename generated file engine.c to
1376 oengine.c.
1377
1378 * interp.c: Update.
1379
1380Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1381
1382 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1383
1384Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1385
1386 * gencode.c (build_instruction): For "FPSQRT", output correct
1387 number of arguments to Recip.
1388
1389Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1390
1391 * Makefile.in (interp.o): Depends on sim-main.h
1392
1393 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1394
1395 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1396 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1397 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1398 STATE, DSSTATE): Define
1399 (GPR, FGRIDX, ..): Define.
1400
1401 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1402 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1403 (GPR, FGRIDX, ...): Delete macros.
1404
1405 * interp.c: Update names to match defines from sim-main.h
1406
1407Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1408
1409 * interp.c (sim_monitor): Add SD argument.
1410 (sim_warning): Delete. Replace calls with calls to
1411 sim_io_eprintf.
1412 (sim_error): Delete. Replace calls with sim_io_error.
1413 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1414 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1415 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1416 argument.
1417 (mips_size): Rename from sim_size. Add SD argument.
1418
1419 * interp.c (simulator): Delete global variable.
1420 (callback): Delete global variable.
1421 (mips_option_handler, sim_open, sim_write, sim_read,
1422 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1423 sim_size,sim_monitor): Use sim_io_* not callback->*.
1424 (sim_open): ZALLOC simulator struct.
1425 (PROFILE): Do not define.
1426
1427Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1428
1429 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1430 support.h with corresponding code.
1431
1432 * sim-main.h (word64, uword64), support.h: Move definition to
1433 sim-main.h.
1434 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1435
1436 * support.h: Delete
1437 * Makefile.in: Update dependencies
1438 * interp.c: Do not include.
1439
1440Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1441
1442 * interp.c (address_translation, load_memory, store_memory,
1443 cache_op): Rename to from AddressTranslation et.al., make global,
1444 add SD argument
1445
1446 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1447 CacheOp): Define.
1448
1449 * interp.c (SignalException): Rename to signal_exception, make
1450 global.
1451
1452 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1453
1454 * sim-main.h (SignalException, SignalExceptionInterrupt,
1455 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1456 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1457 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1458 Define.
1459
1460 * interp.c, support.h: Use.
1461
1462Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1463
1464 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1465 to value_fpr / store_fpr. Add SD argument.
1466 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1467 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1468
1469 * sim-main.h (ValueFPR, StoreFPR): Define.
1470
1471Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1472
1473 * interp.c (sim_engine_run): Check consistency between configure
1474 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1475 and HASFPU.
1476
1477 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1478 (mips_fpu): Configure WITH_FLOATING_POINT.
1479 (mips_endian): Configure WITH_TARGET_ENDIAN.
1480 * configure: Update.
1481
1482Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1483
1484 * configure: Regenerated to track ../common/aclocal.m4 changes.
1485
1486Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1487
1488 * configure: Regenerated.
1489
1490Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1491
1492 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1493
1494Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1495
1496 * gencode.c (print_igen_insn_models): Assume certain architectures
1497 include all mips* instructions.
1498 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1499 instruction.
1500
1501 * Makefile.in (tmp.igen): Add target. Generate igen input from
1502 gencode file.
1503
1504 * gencode.c (FEATURE_IGEN): Define.
1505 (main): Add --igen option. Generate output in igen format.
1506 (process_instructions): Format output according to igen option.
1507 (print_igen_insn_format): New function.
1508 (print_igen_insn_models): New function.
1509 (process_instructions): Only issue warnings and ignore
1510 instructions when no FEATURE_IGEN.
1511
1512Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1513
1514 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1515 MIPS targets.
1516
1517Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1518
1519 * configure: Regenerated to track ../common/aclocal.m4 changes.
1520
1521Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1522
1523 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1524 SIM_RESERVED_BITS): Delete, moved to common.
1525 (SIM_EXTRA_CFLAGS): Update.
1526
1527Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1528
1529 * configure.in: Configure non-strict memory alignment.
1530 * configure: Regenerated to track ../common/aclocal.m4 changes.
1531
1532Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1533
1534 * configure: Regenerated to track ../common/aclocal.m4 changes.
1535
1536Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1537
1538 * gencode.c (SDBBP,DERET): Added (3900) insns.
1539 (RFE): Turn on for 3900.
1540 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1541 (dsstate): Made global.
1542 (SUBTARGET_R3900): Added.
1543 (CANCELDELAYSLOT): New.
1544 (SignalException): Ignore SystemCall rather than ignore and
1545 terminate. Add DebugBreakPoint handling.
1546 (decode_coproc): New insns RFE, DERET; and new registers Debug
1547 and DEPC protected by SUBTARGET_R3900.
1548 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1549 bits explicitly.
1550 * Makefile.in,configure.in: Add mips subtarget option.
1551 * configure: Update.
1552
1553Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1554
1555 * gencode.c: Add r3900 (tx39).
1556
1557
1558Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1559
1560 * gencode.c (build_instruction): Don't need to subtract 4 for
1561 JALR, just 2.
1562
1563Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1564
1565 * interp.c: Correct some HASFPU problems.
1566
1567Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1568
1569 * configure: Regenerated to track ../common/aclocal.m4 changes.
1570
1571Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1572
1573 * interp.c (mips_options): Fix samples option short form, should
1574 be `x'.
1575
1576Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1577
1578 * interp.c (sim_info): Enable info code. Was just returning.
1579
1580Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1581
1582 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1583 MFC0.
1584
1585Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1586
1587 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1588 constants.
1589 (build_instruction): Ditto for LL.
1590
1591Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1592
1593 * configure: Regenerated to track ../common/aclocal.m4 changes.
1594
1595Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1596
1597 * configure: Regenerated to track ../common/aclocal.m4 changes.
1598 * config.in: Ditto.
1599
1600Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1601
1602 * interp.c (sim_open): Add call to sim_analyze_program, update
1603 call to sim_config.
1604
1605Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1606
1607 * interp.c (sim_kill): Delete.
1608 (sim_create_inferior): Add ABFD argument. Set PC from same.
1609 (sim_load): Move code initializing trap handlers from here.
1610 (sim_open): To here.
1611 (sim_load): Delete, use sim-hload.c.
1612
1613 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1614
1615Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1616
1617 * configure: Regenerated to track ../common/aclocal.m4 changes.
1618 * config.in: Ditto.
1619
1620Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1621
1622 * interp.c (sim_open): Add ABFD argument.
1623 (sim_load): Move call to sim_config from here.
1624 (sim_open): To here. Check return status.
1625
1626Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1627
1628 * gencode.c (build_instruction): Two arg MADD should
1629 not assign result to $0.
1630
1631Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1632
1633 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1634 * sim/mips/configure.in: Regenerate.
1635
1636Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1637
1638 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1639 signed8, unsigned8 et.al. types.
1640
1641 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1642 hosts when selecting subreg.
1643
1644Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1645
1646 * interp.c (sim_engine_run): Reset the ZERO register to zero
1647 regardless of FEATURE_WARN_ZERO.
1648 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1649
1650Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1651
1652 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1653 (SignalException): For BreakPoints ignore any mode bits and just
1654 save the PC.
1655 (SignalException): Always set the CAUSE register.
1656
1657Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1658
1659 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1660 exception has been taken.
1661
1662 * interp.c: Implement the ERET and mt/f sr instructions.
1663
1664Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1665
1666 * interp.c (SignalException): Don't bother restarting an
1667 interrupt.
1668
1669Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1670
1671 * interp.c (SignalException): Really take an interrupt.
1672 (interrupt_event): Only deliver interrupts when enabled.
1673
1674Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1675
1676 * interp.c (sim_info): Only print info when verbose.
1677 (sim_info) Use sim_io_printf for output.
1678
1679Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1680
1681 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1682 mips architectures.
1683
1684Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1685
1686 * interp.c (sim_do_command): Check for common commands if a
1687 simulator specific command fails.
1688
1689Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
1690
1691 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1692 and simBE when DEBUG is defined.
1693
1694Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
1695
1696 * interp.c (interrupt_event): New function. Pass exception event
1697 onto exception handler.
1698
1699 * configure.in: Check for stdlib.h.
1700 * configure: Regenerate.
1701
1702 * gencode.c (build_instruction): Add UNUSED attribute to tempS
1703 variable declaration.
1704 (build_instruction): Initialize memval1.
1705 (build_instruction): Add UNUSED attribute to byte, bigend,
1706 reverse.
1707 (build_operands): Ditto.
1708
1709 * interp.c: Fix GCC warnings.
1710 (sim_get_quit_code): Delete.
1711
1712 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1713 * Makefile.in: Ditto.
1714 * configure: Re-generate.
1715
1716 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1717
1718Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1719
1720 * interp.c (mips_option_handler): New function parse argumes using
1721 sim-options.
1722 (myname): Replace with STATE_MY_NAME.
1723 (sim_open): Delete check for host endianness - performed by
1724 sim_config.
1725 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1726 (sim_open): Move much of the initialization from here.
1727 (sim_load): To here. After the image has been loaded and
1728 endianness set.
1729 (sim_open): Move ColdReset from here.
1730 (sim_create_inferior): To here.
1731 (sim_open): Make FP check less dependant on host endianness.
1732
1733 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1734 run.
1735 * interp.c (sim_set_callbacks): Delete.
1736
1737 * interp.c (membank, membank_base, membank_size): Replace with
1738 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1739 (sim_open): Remove call to callback->init. gdb/run do this.
1740
1741 * interp.c: Update
1742
1743 * sim-main.h (SIM_HAVE_FLATMEM): Define.
1744
1745 * interp.c (big_endian_p): Delete, replaced by
1746 current_target_byte_order.
1747
1748Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1749
1750 * interp.c (host_read_long, host_read_word, host_swap_word,
1751 host_swap_long): Delete. Using common sim-endian.
1752 (sim_fetch_register, sim_store_register): Use H2T.
1753 (pipeline_ticks): Delete. Handled by sim-events.
1754 (sim_info): Update.
1755 (sim_engine_run): Update.
1756
1757Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
1758
1759 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1760 reason from here.
1761 (SignalException): To here. Signal using sim_engine_halt.
1762 (sim_stop_reason): Delete, moved to common.
1763
1764Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
1765
1766 * interp.c (sim_open): Add callback argument.
1767 (sim_set_callbacks): Delete SIM_DESC argument.
1768 (sim_size): Ditto.
1769
1770Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1771
1772 * Makefile.in (SIM_OBJS): Add common modules.
1773
1774 * interp.c (sim_set_callbacks): Also set SD callback.
1775 (set_endianness, xfer_*, swap_*): Delete.
1776 (host_read_word, host_read_long, host_swap_word, host_swap_long):
1777 Change to functions using sim-endian macros.
1778 (control_c, sim_stop): Delete, use common version.
1779 (simulate): Convert into.
1780 (sim_engine_run): This function.
1781 (sim_resume): Delete.
1782
1783 * interp.c (simulation): New variable - the simulator object.
1784 (sim_kind): Delete global - merged into simulation.
1785 (sim_load): Cleanup. Move PC assignment from here.
1786 (sim_create_inferior): To here.
1787
1788 * sim-main.h: New file.
1789 * interp.c (sim-main.h): Include.
1790
1791Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
1792
1793 * configure: Regenerated to track ../common/aclocal.m4 changes.
1794
1795Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
1796
1797 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
1798
1799Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
1800
1801 * gencode.c (build_instruction): DIV instructions: check
1802 for division by zero and integer overflow before using
1803 host's division operation.
1804
1805Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
1806
1807 * Makefile.in (SIM_OBJS): Add sim-load.o.
1808 * interp.c: #include bfd.h.
1809 (target_byte_order): Delete.
1810 (sim_kind, myname, big_endian_p): New static locals.
1811 (sim_open): Set sim_kind, myname. Move call to set_endianness to
1812 after argument parsing. Recognize -E arg, set endianness accordingly.
1813 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
1814 load file into simulator. Set PC from bfd.
1815 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
1816 (set_endianness): Use big_endian_p instead of target_byte_order.
1817
1818Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
1819
1820 * interp.c (sim_size): Delete prototype - conflicts with
1821 definition in remote-sim.h. Correct definition.
1822
1823Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1824
1825 * configure: Regenerated to track ../common/aclocal.m4 changes.
1826 * config.in: Ditto.
1827
1828Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
1829
1830 * interp.c (sim_open): New arg `kind'.
1831
1832 * configure: Regenerated to track ../common/aclocal.m4 changes.
1833
1834Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1835
1836 * configure: Regenerated to track ../common/aclocal.m4 changes.
1837
1838Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
1839
1840 * interp.c (sim_open): Set optind to 0 before calling getopt.
1841
1842Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1843
1844 * configure: Regenerated to track ../common/aclocal.m4 changes.
1845
1846Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
1847
1848 * interp.c : Replace uses of pr_addr with pr_uword64
1849 where the bit length is always 64 independent of SIM_ADDR.
1850 (pr_uword64) : added.
1851
1852Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1853
1854 * configure: Re-generate.
1855
1856Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
1857
1858 * configure: Regenerate to track ../common/aclocal.m4 changes.
1859
1860Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
1861
1862 * interp.c (sim_open): New SIM_DESC result. Argument is now
1863 in argv form.
1864 (other sim_*): New SIM_DESC argument.
1865
1866Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
1867
1868 * interp.c: Fix printing of addresses for non-64-bit targets.
1869 (pr_addr): Add function to print address based on size.
1870
1871Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
1872
1873 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
1874
1875Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
1876
1877 * gencode.c (build_mips16_operands): Correct computation of base
1878 address for extended PC relative instruction.
1879
1880Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
1881
1882 * interp.c (mips16_entry): Add support for floating point cases.
1883 (SignalException): Pass floating point cases to mips16_entry.
1884 (ValueFPR): Don't restrict fmt_single and fmt_word to even
1885 registers.
1886 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
1887 or fmt_word.
1888 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
1889 and then set the state to fmt_uninterpreted.
1890 (COP_SW): Temporarily set the state to fmt_word while calling
1891 ValueFPR.
1892
1893Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
1894
1895 * gencode.c (build_instruction): The high order may be set in the
1896 comparison flags at any ISA level, not just ISA 4.
1897
1898Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
1899
1900 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
1901 COMMON_{PRE,POST}_CONFIG_FRAG instead.
1902 * configure.in: sinclude ../common/aclocal.m4.
1903 * configure: Regenerated.
1904
1905Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
1906
1907 * configure: Rebuild after change to aclocal.m4.
1908
1909Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
1910
1911 * configure configure.in Makefile.in: Update to new configure
1912 scheme which is more compatible with WinGDB builds.
1913 * configure.in: Improve comment on how to run autoconf.
1914 * configure: Re-run autoconf to get new ../common/aclocal.m4.
1915 * Makefile.in: Use autoconf substitution to install common
1916 makefile fragment.
1917
1918Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
1919
1920 * gencode.c (build_instruction): Use BigEndianCPU instead of
1921 ByteSwapMem.
1922
1923Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
1924
1925 * interp.c (sim_monitor): Make output to stdout visible in
1926 wingdb's I/O log window.
1927
1928Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
1929
1930 * support.h: Undo previous change to SIGTRAP
1931 and SIGQUIT values.
1932
1933Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
1934
1935 * interp.c (store_word, load_word): New static functions.
1936 (mips16_entry): New static function.
1937 (SignalException): Look for mips16 entry and exit instructions.
1938 (simulate): Use the correct index when setting fpr_state after
1939 doing a pending move.
1940
1941Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
1942
1943 * interp.c: Fix byte-swapping code throughout to work on
1944 both little- and big-endian hosts.
1945
1946Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
1947
1948 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
1949 with gdb/config/i386/xm-windows.h.
1950
1951Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
1952
1953 * gencode.c (build_instruction): Work around MSVC++ code gen bug
1954 that messes up arithmetic shifts.
1955
1956Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
1957
1958 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
1959 SIGTRAP and SIGQUIT for _WIN32.
1960
1961Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
1962
1963 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
1964 force a 64 bit multiplication.
1965 (build_instruction) [OR]: In mips16 mode, don't do anything if the
1966 destination register is 0, since that is the default mips16 nop
1967 instruction.
1968
1969Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
1970
1971 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
1972 (build_endian_shift): Don't check proc64.
1973 (build_instruction): Always set memval to uword64. Cast op2 to
1974 uword64 when shifting it left in memory instructions. Always use
1975 the same code for stores--don't special case proc64.
1976
1977 * gencode.c (build_mips16_operands): Fix base PC value for PC
1978 relative operands.
1979 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
1980 jal instruction.
1981 * interp.c (simJALDELAYSLOT): Define.
1982 (JALDELAYSLOT): Define.
1983 (INDELAYSLOT, INJALDELAYSLOT): Define.
1984 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
1985
1986Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
1987
1988 * interp.c (sim_open): add flush_cache as a PMON routine
1989 (sim_monitor): handle flush_cache by ignoring it
1990
1991Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
1992
1993 * gencode.c (build_instruction): Use !ByteSwapMem instead of
1994 BigEndianMem.
1995 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
1996 (BigEndianMem): Rename to ByteSwapMem and change sense.
1997 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
1998 BigEndianMem references to !ByteSwapMem.
1999 (set_endianness): New function, with prototype.
2000 (sim_open): Call set_endianness.
2001 (sim_info): Use simBE instead of BigEndianMem.
2002 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2003 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2004 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2005 ifdefs, keeping the prototype declaration.
2006 (swap_word): Rewrite correctly.
2007 (ColdReset): Delete references to CONFIG. Delete endianness related
2008 code; moved to set_endianness.
2009
2010Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2011
2012 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2013 * interp.c (CHECKHILO): Define away.
2014 (simSIGINT): New macro.
2015 (membank_size): Increase from 1MB to 2MB.
2016 (control_c): New function.
2017 (sim_resume): Rename parameter signal to signal_number. Add local
2018 variable prev. Call signal before and after simulate.
2019 (sim_stop_reason): Add simSIGINT support.
2020 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2021 functions always.
2022 (sim_warning): Delete call to SignalException. Do call printf_filtered
2023 if logfh is NULL.
2024 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2025 a call to sim_warning.
2026
2027Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2028
2029 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2030 16 bit instructions.
2031
2032Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2033
2034 Add support for mips16 (16 bit MIPS implementation):
2035 * gencode.c (inst_type): Add mips16 instruction encoding types.
2036 (GETDATASIZEINSN): Define.
2037 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2038 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2039 mtlo.
2040 (MIPS16_DECODE): New table, for mips16 instructions.
2041 (bitmap_val): New static function.
2042 (struct mips16_op): Define.
2043 (mips16_op_table): New table, for mips16 operands.
2044 (build_mips16_operands): New static function.
2045 (process_instructions): If PC is odd, decode a mips16
2046 instruction. Break out instruction handling into new
2047 build_instruction function.
2048 (build_instruction): New static function, broken out of
2049 process_instructions. Check modifiers rather than flags for SHIFT
2050 bit count and m[ft]{hi,lo} direction.
2051 (usage): Pass program name to fprintf.
2052 (main): Remove unused variable this_option_optind. Change
2053 ``*loptarg++'' to ``loptarg++''.
2054 (my_strtoul): Parenthesize && within ||.
2055 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2056 (simulate): If PC is odd, fetch a 16 bit instruction, and
2057 increment PC by 2 rather than 4.
2058 * configure.in: Add case for mips16*-*-*.
2059 * configure: Rebuild.
2060
2061Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2062
2063 * interp.c: Allow -t to enable tracing in standalone simulator.
2064 Fix garbage output in trace file and error messages.
2065
2066Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2067
2068 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2069 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2070 * configure.in: Simplify using macros in ../common/aclocal.m4.
2071 * configure: Regenerated.
2072 * tconfig.in: New file.
2073
2074Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2075
2076 * interp.c: Fix bugs in 64-bit port.
2077 Use ansi function declarations for msvc compiler.
2078 Initialize and test file pointer in trace code.
2079 Prevent duplicate definition of LAST_EMED_REGNUM.
2080
2081Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2082
2083 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2084
2085Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2086
2087 * interp.c (SignalException): Check for explicit terminating
2088 breakpoint value.
2089 * gencode.c: Pass instruction value through SignalException()
2090 calls for Trap, Breakpoint and Syscall.
2091
2092Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2093
2094 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2095 only used on those hosts that provide it.
2096 * configure.in: Add sqrt() to list of functions to be checked for.
2097 * config.in: Re-generated.
2098 * configure: Re-generated.
2099
2100Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2101
2102 * gencode.c (process_instructions): Call build_endian_shift when
2103 expanding STORE RIGHT, to fix swr.
2104 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2105 clear the high bits.
2106 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2107 Fix float to int conversions to produce signed values.
2108
2109Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2110
2111 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2112 (process_instructions): Correct handling of nor instruction.
2113 Correct shift count for 32 bit shift instructions. Correct sign
2114 extension for arithmetic shifts to not shift the number of bits in
2115 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2116 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2117 Fix madd.
2118 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2119 It's OK to have a mult follow a mult. What's not OK is to have a
2120 mult follow an mfhi.
2121 (Convert): Comment out incorrect rounding code.
2122
2123Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2124
2125 * interp.c (sim_monitor): Improved monitor printf
2126 simulation. Tidied up simulator warnings, and added "--log" option
2127 for directing warning message output.
2128 * gencode.c: Use sim_warning() rather than WARNING macro.
2129
2130Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2131
2132 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2133 getopt1.o, rather than on gencode.c. Link objects together.
2134 Don't link against -liberty.
2135 (gencode.o, getopt.o, getopt1.o): New targets.
2136 * gencode.c: Include <ctype.h> and "ansidecl.h".
2137 (AND): Undefine after including "ansidecl.h".
2138 (ULONG_MAX): Define if not defined.
2139 (OP_*): Don't define macros; now defined in opcode/mips.h.
2140 (main): Call my_strtoul rather than strtoul.
2141 (my_strtoul): New static function.
2142
2143Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2144
2145 * gencode.c (process_instructions): Generate word64 and uword64
2146 instead of `long long' and `unsigned long long' data types.
2147 * interp.c: #include sysdep.h to get signals, and define default
2148 for SIGBUS.
2149 * (Convert): Work around for Visual-C++ compiler bug with type
2150 conversion.
2151 * support.h: Make things compile under Visual-C++ by using
2152 __int64 instead of `long long'. Change many refs to long long
2153 into word64/uword64 typedefs.
2154
2155Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2156
2157 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2158 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2159 (docdir): Removed.
2160 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2161 (AC_PROG_INSTALL): Added.
2162 (AC_PROG_CC): Moved to before configure.host call.
2163 * configure: Rebuilt.
2164
2165Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2166
2167 * configure.in: Define @SIMCONF@ depending on mips target.
2168 * configure: Rebuild.
2169 * Makefile.in (run): Add @SIMCONF@ to control simulator
2170 construction.
2171 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2172 * interp.c: Remove some debugging, provide more detailed error
2173 messages, update memory accesses to use LOADDRMASK.
2174
2175Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2176
2177 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2178 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2179 stamp-h.
2180 * configure: Rebuild.
2181 * config.in: New file, generated by autoheader.
2182 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2183 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2184 HAVE_ANINT and HAVE_AINT, as appropriate.
2185 * Makefile.in (run): Use @LIBS@ rather than -lm.
2186 (interp.o): Depend upon config.h.
2187 (Makefile): Just rebuild Makefile.
2188 (clean): Remove stamp-h.
2189 (mostlyclean): Make the same as clean, not as distclean.
2190 (config.h, stamp-h): New targets.
2191
2192Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2193
2194 * interp.c (ColdReset): Fix boolean test. Make all simulator
2195 globals static.
2196
2197Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2198
2199 * interp.c (xfer_direct_word, xfer_direct_long,
2200 swap_direct_word, swap_direct_long, xfer_big_word,
2201 xfer_big_long, xfer_little_word, xfer_little_long,
2202 swap_word,swap_long): Added.
2203 * interp.c (ColdReset): Provide function indirection to
2204 host<->simulated_target transfer routines.
2205 * interp.c (sim_store_register, sim_fetch_register): Updated to
2206 make use of indirected transfer routines.
2207
2208Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2209
2210 * gencode.c (process_instructions): Ensure FP ABS instruction
2211 recognised.
2212 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2213 system call support.
2214
2215Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2216
2217 * interp.c (sim_do_command): Complain if callback structure not
2218 initialised.
2219
2220Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2221
2222 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2223 support for Sun hosts.
2224 * Makefile.in (gencode): Ensure the host compiler and libraries
2225 used for cross-hosted build.
2226
2227Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2228
2229 * interp.c, gencode.c: Some more (TODO) tidying.
2230
2231Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2232
2233 * gencode.c, interp.c: Replaced explicit long long references with
2234 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2235 * support.h (SET64LO, SET64HI): Macros added.
2236
2237Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2238
2239 * configure: Regenerate with autoconf 2.7.
2240
2241Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2242
2243 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2244 * support.h: Remove superfluous "1" from #if.
2245 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2246
2247Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2248
2249 * interp.c (StoreFPR): Control UndefinedResult() call on
2250 WARN_RESULT manifest.
2251
2252Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2253
2254 * gencode.c: Tidied instruction decoding, and added FP instruction
2255 support.
2256
2257 * interp.c: Added dineroIII, and BSD profiling support. Also
2258 run-time FP handling.
2259
2260Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2261
2262 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2263 gencode.c, interp.c, support.h: created.
GDB Binutils - Deliverables
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