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sim: drop obsolete AC_EXEEXT call
[deliverable/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
a8a3d907
MF		 12021-06-16 Mike Frysinger <vapier@gentoo.org>
2
3 * configure: Regenerate.
4
dae666c9
MF		 52021-06-16 Mike Frysinger <vapier@gentoo.org>
6
7 * interp.c (sim_open): Change %lx to %x and PRIx macros.
8
52d37d2c
MF		 92021-06-16 Mike Frysinger <vapier@gentoo.org>
10
11 * configure: Regenerate.
12 * config.in: Removed.
13
bcaa61f7
MF		 142021-06-15 Mike Frysinger <vapier@gentoo.org>
15
16 * config.in, configure: Regenerate.
17
ba307cdd
MF		 182021-06-12 Mike Frysinger <vapier@gentoo.org>
19
20 * configure.ac: Delete call to SIM_AC_OPTION_ALIGNMENT.
21
dba333c1
MF		 222021-06-12 Mike Frysinger <vapier@gentoo.org>
23
24 * aclocal.m4, config.in, configure: Regenerate.
25
b15c5d7a
MF		 262021-06-12 Mike Frysinger <vapier@gentoo.org>
27
28 * configure.ac: Delete call to AC_CHECK_FUNCS.
29 * config.in, configure: Regenerate.
30
a55b92be
MF		 312021-06-08 Mike Frysinger <vapier@gentoo.org>
32
33 * Makefile.in: Replace $(IGEN) with $(IGEN_RUN) and ../igen/igen
34 with $(IGEN).
35
8ea881d9
MF		 362021-05-29 Mike Frysinger <vapier@gentoo.org>
37
38 * interp.c [!HAVE_DV_SOCKSER] (sockser_addr): Define to NULL.
39
b312488f
FS		 402021-05-22 Faraz Shahbazker <fshahbazker@wavecomp.com>
41
168671c1
FS		 42 * interp.c (sim_open): Add shadow mappings from 32-bit
43 address space to 64-bit sign-extended address space.
44
452021-05-22 Faraz Shahbazker <fshahbazker@wavecomp.com>
46
b312488f
FS		 47 * interp.c (sim_create_inferior): Only truncate sign extension
48 bits for 32-bit target models.
49
f4fdd845
MF		 502021-05-17 Mike Frysinger <vapier@gentoo.org>
51
52 * sim-main.h (SIM_HAVE_COMMON_SIM_STATE): Delete.
53
8ea7241c
MF		 542021-05-17 Mike Frysinger <vapier@gentoo.org>
55
56 * interp.c (sim_open): Switch to sim_state_alloc_extra.
57 * micromips.igen: Change SD to mips_sim_state.
58 * micromipsrun.c (sim_engine_run): Likewise.
59 * sim-main.h (SIM_HAVE_COMMON_SIM_STATE): Define.
60 (watch_options_install): Delete.
61 (struct swatch): Delete.
62 (struct sim_state): Delete.
63 (struct mips_sim_state): New struct.
64 (MIPS_SIM_STATE): Define.
65
6df01ab8
MF		 662021-05-16 Mike Frysinger <vapier@gentoo.org>
67
68 * interp.c: Replace config.h include with defs.h.
69 * cp1.c, dsp.c, dv-tx3904cpu.c, dv-tx3904irc.c, dv-tx3904sio.c,
70 dv-tx3904tmr.c, m16run.c, mdmx.c, micromipsrun.c, sim-main.c:
71 Include defs.h.
72
79633c12
MF		 732021-05-16 Mike Frysinger <vapier@gentoo.org>
74
75 * config.in, configure: Regenerate.
76
df68e12b
MF		 772021-05-14 Mike Frysinger <vapier@gentoo.org>
78
79 * interp.c: Update include path.
80
77c0fdb7
MF		 812021-05-04 Mike Frysinger <vapier@gentoo.org>
82
83 * dv-tx3904sio.c: Include stdlib.h.
84
9b1af85c
MF		 852021-05-04 Mike Frysinger <vapier@gentoo.org>
86
87 * configure.ac (hw_extra_devices): Inline contents into
88 SIM_AC_OPTION_HARDWARE and delete.
89 * configure: Regenerate.
90
d97ba9c6
MF		 912021-05-04 Mike Frysinger <vapier@gentoo.org>
92
93 * Makefile.in (SIM_IGEN_OBJ): Change @mips_igen_engine@ to engine.o.
94 (MIPS_EXTRA_LIB, SIM_EXTRA_LIBS): Delete.
95 * configure.ac (mips_igen_engine, mips_extra_libs): Delete.
96 * configure: Regenerate.
97
4df817de
MF		 982021-05-04 Mike Frysinger <vapier@gentoo.org>
99
100 * mdmx.c (qh_acc): Change 2nd AccAddAQH to AccAddLQH.
101
aa0fca16
MF		 1022021-05-04 Mike Frysinger <vapier@gentoo.org>
103
104 * configure: Regenerate.
105
adbaa7b8
MF		 1062021-05-01 Mike Frysinger <vapier@gentoo.org>
107
108 * cp1.c (store_fcr): Mark static.
109
fe348617
MF		 1102021-05-01 Mike Frysinger <vapier@gentoo.org>
111
112 * config.in, configure: Regenerate.
113
9d903352
MF		 1142021-04-23 Mike Frysinger <vapier@gentoo.org>
115
116 * configure.ac (hw_enabled): Delete.
117 (SIM_AC_OPTION_HARDWARE): Delete first two args.
118 * configure: Regenerate.
119
19f6a43c
TT		 1202021-04-22 Tom Tromey <tom@tromey.com>
121
122 * configure, config.in: Rebuild.
123
e7d8f1da
TT		 1242021-04-22 Tom Tromey <tom@tromey.com>
125
126 * Makefile.in (interp.o, m16run.o, micromipsrun.o, multi-run.o):
127 Remove.
128 (SIM_EXTRA_DEPS): New variable.
129
efd82ac7
TT		 1302021-04-22 Tom Tromey <tom@tromey.com>
131
132 * configure: Rebuild.
133
2662c237
MF		 1342021-04-21 Mike Frysinger <vapier@gentoo.org>
135
136 * aclocal.m4: Regenerate.
137
1f195bc3
SM		 1382021-04-21 Simon Marchi <simon.marchi@polymtl.ca>
139
140 * configure: Regenerate.
141
37e9f182
MF		 1422021-04-18 Mike Frysinger <vapier@gentoo.org>
143
144 * configure: Regenerate.
145
d5a71b11
MF		 1462021-04-12 Mike Frysinger <vapier@gentoo.org>
147
148 * interp.c (sim_open): Delete 3rd arg to sim_cpu_alloc_all.
149
2b8d134b
SM		 1502021-04-08 Simon Marchi <simon.marchi@polymtl.ca>
151
152 * Makefile.in: Set ASAN_OPTIONS when running igen.
153
5c6f091a
FS		 1542021-04-04 Steve Ellcey <sellcey@mips.com>
155 Faraz Shahbazker <fshahbazker@wavecomp.com>
156
157 * interp.c (sim_monitor): Add switch entries for unlink (13),
158 lseek (14), and stat (15).
159
b6b1c790
MF		 1602021-04-02 Mike Frysinger <vapier@gentoo.org>
161
162 * Makefile.in (../igen/igen): Delete rule.
163 (tmp-igen, tmp-m16, tmp-micromips): Delete ../igen make.
164
c2783492
MF		 1652021-04-02 Mike Frysinger <vapier@gentoo.org>
166
167 * aclocal.m4, configure: Regenerate.
168
ebe9564b
MF		 1692021-02-28 Mike Frysinger <vapier@gentoo.org>
170
171 * configure: Regenerate.
172
f8069d55
MF		 1732021-02-27 Mike Frysinger <vapier@gentoo.org>
174
175 * Makefile.in (SIM_EXTRA_ALL): Delete.
176 (all): New target.
177
760b3e8b
MF		 1782021-02-21 Mike Frysinger <vapier@gentoo.org>
179
180 * configure.ac (AC_CONFIG_MACRO_DIRS): Replace common with m4.
181 * aclocal.m4, configure: Regenerate.
182
136da8cd
MF		 1832021-02-13 Mike Frysinger <vapier@gentoo.org>
184
185 * configure.ac: Replace sinclude with AC_CONFIG_MACRO_DIRS.
186 * aclocal.m4, configure: Regenerate.
187
4c0d76b9
MF		 1882021-02-06 Mike Frysinger <vapier@gentoo.org>
189
190 * interp.c (sim_open): Delete call to STATE_WATCHPOINTS.
191
aa09469f
MF		 1922021-02-06 Mike Frysinger <vapier@gentoo.org>
193
194 * configure: Regenerate.
195
d4e3adda
MF		 1962021-01-30 Mike Frysinger <vapier@gentoo.org>
197
198 * interp.c (sim_open): Delete STATE_WATCHPOINTS (sd)->sizeof_pc.
199
68ed2854
MF		 2002021-01-11 Mike Frysinger <vapier@gentoo.org>
201
202 * config.in, configure: Regenerate.
203 * interp.c: Delete HAVE_STRING_H, HAVE_STRINGS_H, HAVE_STDLIB_H,
204 and strings.h include.
205
50df264d
MF		 2062021-01-09 Mike Frysinger <vapier@gentoo.org>
207
208 * configure: Regenerate.
209
bf470982
MF		 2102021-01-09 Mike Frysinger <vapier@gentoo.org>
211
212 * configure.ac (SIM_AC_OPTION_WARNINGS): Pass "no".
213 * configure: Regenerate.
214
46f900c0
MF		 2152021-01-08 Mike Frysinger <vapier@gentoo.org>
216
217 * configure: Regenerate.
218
dfb856ba
MF		 2192021-01-04 Mike Frysinger <vapier@gentoo.org>
220
221 * configure: Regenerate.
222
382bc56b
PK		 2232020-12-31 Pavel I. Kryukov <kryukov@frtk.ru> (tiny change)
224
225 * sim-main.c: Include <stdlib.h>.
226
ad9675dd
PK		 2272020-12-14 Pavel I. Kryukov <kryukov@frtk.ru> (tiny change)
228
229 * cp1.c: Include <stdlib.h>.
230
f693213d
SM		 2312020-07-29 Simon Marchi <simon.marchi@efficios.com>
232
233 * configure: Re-generate.
234
5c887dd5
JB		 2352017-09-06 John Baldwin <jhb@FreeBSD.org>
236
237 * configure: Regenerate.
238
91588b3a
MF		 2392016-11-11 Mike Frysinger <vapier@gentoo.org>
240
6cb2202b 241 PR sim/20808
91588b3a
MF		 242 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Define CPU to cpu
243 and SD to sd.
244
e04659e8
MF		 2452016-11-11 Mike Frysinger <vapier@gentoo.org>
246
6cb2202b 247 PR sim/20809
e04659e8
MF		 248 * mips.igen (check_u64): Enable for `r3900'.
249
1554f758
MF		 2502016-02-05 Mike Frysinger <vapier@gentoo.org>
251
252 * configure.ac (sim_engine_run): Change sd->base.prog_bfd to
253 STATE_PROG_BFD (sd).
254 * configure: Regenerate.
255
3d304f48
AB		 2562016-01-18 Andrew Bennett <andrew.bennett@imgtec.com>
257 Maciej W. Rozycki <macro@imgtec.com>
258
259 PR sim/19441
260 * micromips.igen (delayslot_micromips): Enable for `micromips32',
261 `micromips64' and `micromipsdsp' only.
262 (process_isa_mode): Enable for `micromips32' and `micromips64' only.
263 (do_micromips_jalr, do_micromips_jal): Likewise.
264 (compute_movep_src_reg): Likewise.
265 (compute_andi16_imm): Likewise.
266 (convert_fmt_micromips): Likewise.
267 (convert_fmt_micromips_cvt_d): Likewise.
268 (convert_fmt_micromips_cvt_s): Likewise.
269 (FMT_MICROMIPS): Likewise.
270 (FMT_MICROMIPS_CVT_D): Likewise.
271 (FMT_MICROMIPS_CVT_S): Likewise.
272
b36d953b
MF		 2732016-01-12 Mike Frysinger <vapier@gentoo.org>
274
275 * interp.c: Include elf-bfd.h.
276 (sim_create_inferior): Truncate pc to 32-bits when EI_CLASS is
277 ELFCLASS32.
278
ce39bd38
MF		 2792016-01-10 Mike Frysinger <vapier@gentoo.org>
280
281 * config.in, configure: Regenerate.
282
99d8e879
MF		 2832016-01-10 Mike Frysinger <vapier@gentoo.org>
284
285 * configure: Regenerate.
286
35656e95
MF		 2872016-01-10 Mike Frysinger <vapier@gentoo.org>
288
289 * configure: Regenerate.
290
16f7876d
MF		 2912016-01-10 Mike Frysinger <vapier@gentoo.org>
292
293 * configure: Regenerate.
294
e19418e0
MF		 2952016-01-10 Mike Frysinger <vapier@gentoo.org>
296
297 * configure: Regenerate.
298
6d90347b
MF		 2992016-01-10 Mike Frysinger <vapier@gentoo.org>
300
301 * configure.ac (SIM_AC_OPTION_SMP): Delete call.
302 * configure: Regenerate.
303
347fe5bb
MF		 3042016-01-10 Mike Frysinger <vapier@gentoo.org>
305
306 * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
307 * configure: Regenerate.
308
22be3fbe
MF		 3092016-01-10 Mike Frysinger <vapier@gentoo.org>
310
311 * configure: Regenerate.
312
0dc73ef7
MF		 3132016-01-10 Mike Frysinger <vapier@gentoo.org>
314
315 * configure: Regenerate.
316
936df756
MF		 3172016-01-09 Mike Frysinger <vapier@gentoo.org>
318
319 * config.in, configure: Regenerate.
320
2e3d4f4d
MF		 3212016-01-06 Mike Frysinger <vapier@gentoo.org>
322
323 * interp.c (sim_open): Mark argv const.
324 (sim_create_inferior): Mark argv and env const.
325
9bbf6f91
MF		 3262016-01-04 Mike Frysinger <vapier@gentoo.org>
327
328 * configure: Regenerate.
329
77cf2ef5
MF		 3302016-01-03 Mike Frysinger <vapier@gentoo.org>
331
332 * interp.c (sim_open): Update sim_parse_args comment.
333
0cb8d851
MF		 3342016-01-03 Mike Frysinger <vapier@gentoo.org>
335
336 * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
337 * configure: Regenerate.
338
1ac72f06
MF		 3392016-01-02 Mike Frysinger <vapier@gentoo.org>
340
341 * configure.ac (mips_endian): Change LITTLE_ENDIAN to LITTLE.
342 (default_endian): Likewise. Change BIG_ENDIAN to BIG.
343 * configure: Regenerate.
344 * sim-main.h (BigEndianMem): Change BIG_ENDIAN to BFD_ENDIAN_BIG.
345
d47f5b30
MF		 3462016-01-02 Mike Frysinger <vapier@gentoo.org>
347
348 * dv-tx3904cpu.c (CPU, SD): Delete.
349
e1211e55
MF		 3502015-12-30 Mike Frysinger <vapier@gentoo.org>
351
352 * wrapper.c (mips_reg_store, mips_reg_fetch): Define.
353 (sim_open): Call CPU_REG_FETCH/CPU_REG_STORE.
354 (sim_store_register): Rename to ...
355 (mips_reg_store): ... this. Delete local cpu var.
356 Update sim_io_eprintf calls.
357 (sim_fetch_register): Rename to ...
358 (mips_reg_fetch): ... this. Delete local cpu var.
359 Update sim_io_eprintf calls.
360
5e744ef8
MF		 3612015-12-27 Mike Frysinger <vapier@gentoo.org>
362
363 * Makefile.in (SIM_OBJS): Delete sim-hload.o.
364
1b393626
MF		 3652015-12-26 Mike Frysinger <vapier@gentoo.org>
366
367 * config.in, configure: Regenerate.
368
26f8bf63
MF		 3692015-12-26 Mike Frysinger <vapier@gentoo.org>
370
371 * interp.c (sim_write, sim_read): Delete.
372 (store_word): Delete call to AddressTranslation and set paddr=vaddr.
373 (load_word): Likewise.
374 * micromips.igen (cache): Likewise.
375 * mips.igen (do_ll, do_lld, do_sc, do_scd, do_suxc1_32, do_swc1,
376 do_swxc1, cache, do_load, do_load_left, do_load_right, do_store,
377 do_store_left, do_store_right, do_load_double, do_store_double):
378 Likewise.
379 (do_pref): Delete call to AddressTranslation and stub out Prefetch.
380 (do_prefx): Likewise.
381 * sim-main.c (address_translation, prefetch): Delete.
382 (ifetch32, ifetch16): Delete call to AddressTranslation and set
383 paddr=vaddr.
384 * sim-main.h (Uncached, CachedNoncoherent, CachedCoherent, Cached,
385 address_translation, AddressTranslation, prefetch, Prefetch): Delete.
386 (LoadMemory, StoreMemory): Delete CCA arg.
387
ef04e371
MF		 3882015-12-24 Mike Frysinger <vapier@gentoo.org>
389
390 * configure.ac (SIM_SUBTARGET): Drop -DTARGET_TX3904=1.
391 * configure: Regenerated.
392
cb379ede
MF		 3932015-12-24 Mike Frysinger <vapier@gentoo.org>
394
395 * sim-main.h (SIM_QUIET_NAN_NEGATED): Move from tconfig.h.
396 * tconfig.h: Delete.
397
26936211
MF		 3982015-12-24 Mike Frysinger <vapier@gentoo.org>
399
400 * tconfig.h (SIM_HANDLES_LMA): Delete.
401
84e8e361
MF		 4022015-12-24 Mike Frysinger <vapier@gentoo.org>
403
404 * sim-main.h (WITH_WATCHPOINTS): Delete.
405
3cabaf66
MF		 4062015-12-24 Mike Frysinger <vapier@gentoo.org>
407
408 * interp.c [SIM_HAVE_FLATMEM] (sim_open): Delete flatmem code.
409
8abe6c66
MF		 4102015-12-24 Mike Frysinger <vapier@gentoo.org>
411
412 * tconfig.h (SIM_HAVE_SIMCACHE): Delete.
413
1d19cae7
DV		 4142015-12-15 Dominik Vogt <vogt@linux.vnet.ibm.com>
415
416 * micromips.igen (process_isa_mode): Fix left shift of negative
417 value.
418
cdf850e9
MF		 4192015-11-17 Mike Frysinger <vapier@gentoo.org>
420
421 * sim-main.h (WITH_MODULO_MEMORY): Delete.
422
797eee42
MF		 4232015-11-15 Mike Frysinger <vapier@gentoo.org>
424
425 * Makefile.in (SIM_OBJS): Delete sim-reason.o and sim-stop.o.
426
6e4f085c
MF		 4272015-11-14 Mike Frysinger <vapier@gentoo.org>
428
429 * interp.c (sim_close): Rename to ...
430 (mips_sim_close): ... this. Delete calls to sim_module_uninstall and
431 sim_io_shutdown.
432 * sim-main.h (mips_sim_close): Declare.
433 (SIM_CLOSE_HOOK): Define.
434
8e394ffc
AB		 4352015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
436 Ali Lown <ali.lown@imgtec.com>
437
438 * Makefile.in (tmp-micromips): New rule.
439 (tmp-mach-multi): Add support for micromips.
440 * configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
441 that works for both mips64 and micromips64.
442 (mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
443 micromips32.
444 Add build support for micromips.
445 * dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
446 do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
447 do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
448 do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
449 do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
450 do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
451 do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
452 do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
453 Refactored instruction code to use these functions.
454 * dsp2.igen: Refactored instruction code to use the new functions.
455 * interp.c (decode_coproc): Refactored to work with any instruction
456 encoding.
457 (isa_mode): New variable
458 (RSVD_INSTRUCTION): Changed to 0x00000039.
459 * m16.igen (BREAK16): Refactored instruction to use do_break16.
460 (JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
461 * micromips.dc: New file.
462 * micromips.igen: New file.
463 * micromips16.dc: New file.
464 * micromipsdsp.igen: New file.
465 * micromipsrun.c: New file.
466 * mips.igen (do_swc1): Changed to work with any instruction encoding.
467 (do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
468 do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo,
469 do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu,
470 do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu,
471 do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub,
472 do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo,
473 do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc,
474 do_scd, do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu,
475 do_tgeu, do_tlt do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt,
476 do_add_fmt, do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1,
477 do_cvt_d_fmt, do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl,
478 do_cvt_s_pu, do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt,
479 do_luxc1_32, do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b,
480 do_mov_fmt, do_movtf, do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt,
481 do_mtc1b, do_mul_fmt, do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps,
482 do_plu_ps, do_pul_ps, do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt,
483 do_prefx, do_sdc1, do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt,
484 do_swc1, do_swxc1, do_trunc_fmt): New functions, refactored from existing
485 instructions.
486 Refactored instruction code to use these functions.
487 (RSVD): Changed to use new reserved instruction.
488 (loadstore_ea, not_word_value, unpredictable, check_mt_hilo,
489 check_mf_hilo, check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32,
490 do_sdc1, do_suxc1_32, check_fmt_p, check_fpu, do_load_double,
491 do_store_double): Added micromips32 and micromips64 models.
492 Added include for micromips.igen and micromipsdsp.igen
493 Add micromips32 and micromips64 models.
494 (DecodeCoproc): Updated to use new macro definition.
495 * mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
496 do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
497 do_seb, do_seh do_rdhwr, do_wsbh): New functions.
498 Refactored instruction code to use these functions.
499 * sim-main.h (CP0_operation): New enum.
500 (DecodeCoproc): Updated macro.
501 (IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
502 MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16,
503 MICROMIPS_DELAYSLOT_SIZE_32, ISA_MODE_MIPS32 and
504 ISA_MODE_MICROMIPS): New defines.
505 (sim_state): Add isa_mode field.
506
8d0978fb
MF		 5072015-06-23 Mike Frysinger <vapier@gentoo.org>
508
509 * configure: Regenerate.
510
306f4178
MF		 5112015-06-12 Mike Frysinger <vapier@gentoo.org>
512
513 * configure.ac: Change configure.in to configure.ac.
514 * configure: Regenerate.
515
a3487082
MF		 5162015-06-12 Mike Frysinger <vapier@gentoo.org>
517
518 * configure: Regenerate.
519
29bc024d
MF		 5202015-06-12 Mike Frysinger <vapier@gentoo.org>
521
522 * interp.c [TRACE]: Delete.
523 (TRACE): Change to WITH_TRACE_ANY_P.
524 [!WITH_TRACE_ANY_P] (open_trace): Define.
525 (mips_option_handler, open_trace, sim_close, dotrace):
526 Change defined(TRACE) to WITH_TRACE_ANY_P.
527 (sim_open): Delete TRACE ifdef check.
528 * sim-main.c (load_memory): Delete TRACE ifdef check.
529 (store_memory): Likewise.
530 * sim-main.h [WITH_TRACE_ANY_P] (dotrace, tracefh): Protect decls.
531 [!WITH_TRACE_ANY_P] (dotrace): Define.
532
3ebe2863
MF		 5332015-04-18 Mike Frysinger <vapier@gentoo.org>
534
535 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESTART_HOOK): Delete
536 comments.
537
20bca71d
MF		 5382015-04-18 Mike Frysinger <vapier@gentoo.org>
539
540 * sim-main.h (SIM_CPU): Delete.
541
7e83aa92
MF		 5422015-04-18 Mike Frysinger <vapier@gentoo.org>
543
544 * sim-main.h (sim_cia): Delete.
545
034685f9
MF		 5462015-04-17 Mike Frysinger <vapier@gentoo.org>
547
548 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Change CIA_GET to
549 PU_PC_GET.
550 * interp.c (interrupt_event): Change CIA_GET to CPU_PC_GET.
551 (sim_create_inferior): Change CIA_SET to CPU_PC_SET.
552 * m16run.c (sim_engine_run): Change CIA_GET to CPU_PC_GET and
553 CIA_SET to CPU_PC_SET.
554 * sim-main.h (CIA_GET, CIA_SET): Delete.
555
78e9aa70
MF		 5562015-04-15 Mike Frysinger <vapier@gentoo.org>
557
558 * Makefile.in (SIM_OBJS): Delete sim-cpu.o.
559 * sim-main.h (STATE_CPU): Delete.
560
bf12d44e
MF		 5612015-04-13 Mike Frysinger <vapier@gentoo.org>
562
563 * configure: Regenerate.
564
7bebb329
MF		 5652015-04-13 Mike Frysinger <vapier@gentoo.org>
566
567 * Makefile.in (SIM_OBJS): Add sim-cpu.o.
568 * interp.c (mips_pc_get, mips_pc_set): New functions.
569 (sim_open): Declare new local var i. Call sim_cpu_alloc_all.
570 Call CPU_PC_FETCH & CPU_PC_STORE for all cpus.
571 (sim_pc_get): Delete.
572 * sim-main.h (SIM_CPU): Define.
573 (struct sim_state): Change cpu to an array of pointers.
574 (STATE_CPU): Drop &.
575
8ac57fbd
MF		 5762015-04-13 Mike Frysinger <vapier@gentoo.org>
577
578 * interp.c (mips_option_handler, open_trace, sim_close,
579 sim_write, sim_read, sim_store_register, sim_fetch_register,
580 sim_create_inferior, pr_addr, pr_uword64): Convert old style
581 prototypes.
582 (sim_open): Convert old style prototype. Change casts with
583 sim_write to unsigned char *.
584 (fetch_str): Change null to unsigned char, and change cast to
585 unsigned char *.
586 (sim_monitor): Change c & ch to unsigned char. Change cast to
587 unsigned char *.
588
e787f858
MF		 5892015-04-12 Mike Frysinger <vapier@gentoo.org>
590
591 * Makefile.in (SIM_OBJS): Move interp.o to the start of the list.
592
122bbfb5
MF		 5932015-04-06 Mike Frysinger <vapier@gentoo.org>
594
595 * Makefile.in (SIM_OBJS): Delete sim-engine.o.
596
0fe84f3f
MF		 5972015-04-01 Mike Frysinger <vapier@gentoo.org>
598
599 * tconfig.h (SIM_HAVE_PROFILE): Delete.
600
aadc9410
MF		 6012015-03-31 Mike Frysinger <vapier@gentoo.org>
602
603 * config.in, configure: Regenerate.
604
05f53ed6
MF		 6052015-03-24 Mike Frysinger <vapier@gentoo.org>
606
607 * interp.c (sim_pc_get): New function.
608
c0931f26
MF		 6092015-03-24 Mike Frysinger <vapier@gentoo.org>
610
611 * sim-main.h (SIM_HAVE_BIENDIAN): Delete.
612 * tconfig.h (SIM_HAVE_BIENDIAN): Delete.
613
30452bbe
MF		 6142015-03-24 Mike Frysinger <vapier@gentoo.org>
615
616 * configure: Regenerate.
617
64dd13df
MF		 6182015-03-23 Mike Frysinger <vapier@gentoo.org>
619
620 * configure: Regenerate.
621
49cd1634
MF		 6222015-03-23 Mike Frysinger <vapier@gentoo.org>
623
624 * configure: Regenerate.
625 * configure.ac (mips_extra_objs): Delete.
626 * Makefile.in (MIPS_EXTRA_OBJS): Delete.
627 (SIM_OBJS): Delete MIPS_EXTRA_OBJS.
628
3649cb06
MF		 6292015-03-23 Mike Frysinger <vapier@gentoo.org>
630
631 * configure: Regenerate.
632 * configure.ac: Delete sim_hw checks for dv-sockser.
633
ae7d0cac
MF		 6342015-03-16 Mike Frysinger <vapier@gentoo.org>
635
636 * config.in, configure: Regenerate.
637 * tconfig.in: Rename file ...
638 * tconfig.h: ... here.
639
8406bb59
MF		 6402015-03-15 Mike Frysinger <vapier@gentoo.org>
641
642 * tconfig.in: Delete includes.
643 [HAVE_DV_SOCKSER]: Delete.
644
465fb143
MF		 6452015-03-14 Mike Frysinger <vapier@gentoo.org>
646
647 * Makefile.in (SIM_RUN_OBJS): Delete.
648
5cddc23a
MF		 6492015-03-14 Mike Frysinger <vapier@gentoo.org>
650
651 * configure.ac (AC_CHECK_HEADERS): Delete.
652 * aclocal.m4, configure: Regenerate.
653
2974be62
AM		 6542014-08-19 Alan Modra <amodra@gmail.com>
655
656 * configure: Regenerate.
657
faa743bb
RM		 6582014-08-15 Roland McGrath <mcgrathr@google.com>
659
660 * configure: Regenerate.
661 * config.in: Regenerate.
662
1a8a700e
MF		 6632014-03-04 Mike Frysinger <vapier@gentoo.org>
664
665 * configure: Regenerate.
666
bf3d9781
AM		 6672013-09-23 Alan Modra <amodra@gmail.com>
668
669 * configure: Regenerate.
670
31e6ad7d
MF		 6712013-06-03 Mike Frysinger <vapier@gentoo.org>
672
673 * aclocal.m4, configure: Regenerate.
674
d3685d60
TT		 6752013-05-10 Freddie Chopin <freddie_chopin@op.pl>
676
677 * configure: Rebuild.
678
1517bd27
MF		 6792013-03-26 Mike Frysinger <vapier@gentoo.org>
680
681 * configure: Regenerate.
682
3be31516
JS		 6832013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
684
685 * configure.ac: Address use of dv-sockser.o.
686 * tconfig.in: Conditionalize use of dv_sockser_install.
687 * configure: Regenerated.
688 * config.in: Regenerated.
689
37cb8f8e
SE		 6902012-10-04 Chao-ying Fu <fu@mips.com>
691 Steve Ellcey <sellcey@mips.com>
692
693 * mips/mips3264r2.igen (rdhwr): New.
694
87c8644f
JS		 6952012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
696
697 * configure.ac: Always link against dv-sockser.o.
698 * configure: Regenerate.
699
5f3ef9d0
JB		 7002012-06-15 Joel Brobecker <brobecker@adacore.com>
701
702 * config.in, configure: Regenerate.
703
a6ff997c
NC		 7042012-05-18 Nick Clifton <nickc@redhat.com>
705
706 PR 14072
707 * interp.c: Include config.h before system header files.
708
2232061b
MF		 7092012-03-24 Mike Frysinger <vapier@gentoo.org>
710
711 * aclocal.m4, config.in, configure: Regenerate.
712
db2e4d67
MF		 7132011-12-03 Mike Frysinger <vapier@gentoo.org>
714
715 * aclocal.m4: New file.
716 * configure: Regenerate.
717
4399a56b
MF		 7182011-10-19 Mike Frysinger <vapier@gentoo.org>
719
720 * configure: Regenerate after common/acinclude.m4 update.
721
9c082ca8
MF		 7222011-10-17 Mike Frysinger <vapier@gentoo.org>
723
724 * configure.ac: Change include to common/acinclude.m4.
725
6ffe910a
MF		 7262011-10-17 Mike Frysinger <vapier@gentoo.org>
727
728 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
729 call. Replace common.m4 include with SIM_AC_COMMON.
730 * configure: Regenerate.
731
31b28250
HPN		 7322011-07-08 Hans-Peter Nilsson <hp@axis.com>
733
3faa01e3
HPN		 734 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
735 $(SIM_EXTRA_DEPS).
736 (tmp-mach-multi): Exit early when igen fails.
31b28250 737
2419798b
MF		 7382011-07-05 Mike Frysinger <vapier@gentoo.org>
739
740 * interp.c (sim_do_command): Delete.
741
d79fe0d6
MF		 7422011-02-14 Mike Frysinger <vapier@gentoo.org>
743
744 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
745 (tx3904sio_fifo_reset): Likewise.
746 * interp.c (sim_monitor): Likewise.
747
5558e7e6
MF		 7482010-04-14 Mike Frysinger <vapier@gentoo.org>
749
750 * interp.c (sim_write): Add const to buffer arg.
751
35aafff4
JB		 7522010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
753
754 * interp.c: Don't include sysdep.h
755
3725885a
RW		 7562010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
757
758 * configure: Regenerate.
759
d6416cdc
RW		 7602009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
761
81ecdfbb
RW		 762 * config.in: Regenerate.
763 * configure: Likewise.
764
d6416cdc
RW		 765 * configure: Regenerate.
766
b5bd9624
HPN		 7672008-07-11 Hans-Peter Nilsson <hp@axis.com>
768
769 * configure: Regenerate to track ../common/common.m4 changes.
770 * config.in: Ditto.
771
6efef468 7722008-06-06 Vladimir Prus <vladimir@codesourcery.com>
72f4393d
L		 773 Daniel Jacobowitz <dan@codesourcery.com>
774 Joseph Myers <joseph@codesourcery.com>
6efef468
JM		 775
776 * configure: Regenerate.
777
60dc88db
RS		 7782007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
779
780 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
781 that unconditionally allows fmt_ps.
782 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
783 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
784 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
785 filter from 64,f to 32,f.
786 (PREFX): Change filter from 64 to 32.
787 (LDXC1, LUXC1): Provide separate mips32r2 implementations
788 that use do_load_double instead of do_load. Make both LUXC1
789 versions unpredictable if SizeFGR () != 64.
790 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
791 instead of do_store. Remove unused variable. Make both SUXC1
792 versions unpredictable if SizeFGR () != 64.
793
599ca73e
RS		 7942007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
795
796 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
797 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
798 shifts for that case.
799
2525df03
NC		 8002007-09-04 Nick Clifton <nickc@redhat.com>
801
802 * interp.c (options enum): Add OPTION_INFO_MEMORY.
803 (display_mem_info): New static variable.
804 (mips_option_handler): Handle OPTION_INFO_MEMORY.
805 (mips_options): Add info-memory and memory-info.
806 (sim_open): After processing the command line and board
807 specification, check display_mem_info. If it is set then
808 call the real handler for the --memory-info command line
809 switch.
810
35ee6e1e
JB		 8112007-08-24 Joel Brobecker <brobecker@adacore.com>
812
813 * configure.ac: Change license of multi-run.c to GPL version 3.
814 * configure: Regenerate.
815
d5fb0879
RS		 8162007-06-28 Richard Sandiford <richard@codesourcery.com>
817
818 * configure.ac, configure: Revert last patch.
819
2a2ce21b
RS		 8202007-06-26 Richard Sandiford <richard@codesourcery.com>
821
822 * configure.ac (sim_mipsisa3264_configs): New variable.
823 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
824 every configuration support all four targets, using the triplet to
825 determine the default.
826 * configure: Regenerate.
827
efdcccc9
RS		 8282007-06-25 Richard Sandiford <richard@codesourcery.com>
829
0a7692b2 830 * Makefile.in (m16run.o): New rule.
efdcccc9 831
f532a356
TS		 8322007-05-15 Thiemo Seufer <ths@mips.com>
833
834 * mips3264r2.igen (DSHD): Fix compile warning.
835
bfe9c90b
TS		 8362007-05-14 Thiemo Seufer <ths@mips.com>
837
838 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
839 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
840 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
841 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
842 for mips32r2.
843
53f4826b
TS		 8442007-03-01 Thiemo Seufer <ths@mips.com>
845
846 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
847 and mips64.
848
8bf3ddc8
TS		 8492007-02-20 Thiemo Seufer <ths@mips.com>
850
851 * dsp.igen: Update copyright notice.
852 * dsp2.igen: Fix copyright notice.
853
8b082fb1 8542007-02-20 Thiemo Seufer <ths@mips.com>
72f4393d 855 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 856
857 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
858 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
859 Add dsp2 to sim_igen_machine.
860 * configure: Regenerate.
861 * dsp.igen (do_ph_op): Add MUL support when op = 2.
862 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
863 (mulq_rs.ph): Use do_ph_mulq.
864 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
865 * mips.igen: Add dsp2 model and include dsp2.igen.
866 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
867 for *mips32r2, *mips64r2, *dsp.
868 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
869 for *mips32r2, *mips64r2, *dsp2.
870 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
871
b1004875 8722007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 873 Nigel Stephens <nigel@mips.com>
b1004875
TS		 874
875 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
876 jumps with hazard barrier.
877
f8df4c77 8782007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 879 Nigel Stephens <nigel@mips.com>
f8df4c77
TS		 880
881 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
882 after each call to sim_io_write.
883
b1004875 8842007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 885 Nigel Stephens <nigel@mips.com>
b1004875
TS		 886
887 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
888 supported by this simulator.
07802d98
TS		 889 (decode_coproc): Recognise additional CP0 Config registers
890 correctly.
891
14fb6c5a 8922007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d
L		 893 Nigel Stephens <nigel@mips.com>
894 David Ung <davidu@mips.com>
14fb6c5a
TS		 895
896 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
897 uninterpreted formats. If fmt is one of the uninterpreted types
898 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
899 fmt_word, and fmt_uninterpreted_64 like fmt_long.
900 (store_fpr): When writing an invalid odd register, set the
901 matching even register to fmt_unknown, not the following register.
902 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
903 the the memory window at offset 0 set by --memory-size command
904 line option.
905 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
906 point register.
907 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
908 register.
909 (sim_monitor): When returning the memory size to the MIPS
910 application, use the value in STATE_MEM_SIZE, not an arbitrary
911 hardcoded value.
912 (cop_lw): Don' mess around with FPR_STATE, just pass
913 fmt_uninterpreted_32 to StoreFPR.
914 (cop_sw): Similarly.
915 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
916 (cop_sd): Similarly.
917 * mips.igen (not_word_value): Single version for mips32, mips64
918 and mips16.
919
c8847145 9202007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 921 Nigel Stephens <nigel@mips.com>
c8847145
TS		 922
923 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
924 MBytes.
925
4b5d35ee
TS		 9262007-02-17 Thiemo Seufer <ths@mips.com>
927
928 * configure.ac (mips*-sde-elf*): Move in front of generic machine
929 configuration.
930 * configure: Regenerate.
931
3669427c
TS		 9322007-02-17 Thiemo Seufer <ths@mips.com>
933
934 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
935 Add mdmx to sim_igen_machine.
936 (mipsisa64*-*-*): Likewise. Remove dsp.
937 (mipsisa32*-*-*): Remove dsp.
938 * configure: Regenerate.
939
109ad085
TS		 9402007-02-13 Thiemo Seufer <ths@mips.com>
941
942 * configure.ac: Add mips*-sde-elf* target.
943 * configure: Regenerate.
944
921d7ad3
HPN		 9452006-12-21 Hans-Peter Nilsson <hp@axis.com>
946
947 * acconfig.h: Remove.
948 * config.in, configure: Regenerate.
949
02f97da7
TS		 9502006-11-07 Thiemo Seufer <ths@mips.com>
951
952 * dsp.igen (do_w_op): Fix compiler warning.
953
2d2733fc 9542006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 955 David Ung <davidu@mips.com>
2d2733fc
TS		 956
957 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
958 sim_igen_machine.
959 * configure: Regenerate.
960 * mips.igen (model): Add smartmips.
961 (MADDU): Increment ACX if carry.
962 (do_mult): Clear ACX.
963 (ROR,RORV): Add smartmips.
72f4393d 964 (include): Include smartmips.igen.
2d2733fc
TS		 965 * sim-main.h (ACX): Set to REGISTERS[89].
966 * smartmips.igen: New file.
967
d85c3a10 9682006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 969 David Ung <davidu@mips.com>
d85c3a10
TS		 970
971 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
972 mips3264r2.igen. Add missing dependency rules.
973 * m16e.igen: Support for mips16e save/restore instructions.
974
e85e3205
RE		 9752006-06-13 Richard Earnshaw <rearnsha@arm.com>
976
977 * configure: Regenerated.
978
2f0122dc
DJ		 9792006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
980
981 * configure: Regenerated.
982
20e95c23
DJ		 9832006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
984
985 * configure: Regenerated.
986
69088b17
CF		 9872006-05-15 Chao-ying Fu <fu@mips.com>
988
989 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
990
0275de4e
NC		 9912006-04-18 Nick Clifton <nickc@redhat.com>
992
993 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
994 statement.
995
b3a3ffef
HPN		 9962006-03-29 Hans-Peter Nilsson <hp@axis.com>
997
998 * configure: Regenerate.
999
40a5538e
CF		 10002005-12-14 Chao-ying Fu <fu@mips.com>
1001
1002 * Makefile.in (SIM_OBJS): Add dsp.o.
1003 (dsp.o): New dependency.
1004 (IGEN_INCLUDE): Add dsp.igen.
1005 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
1006 mipsisa64*-*-*): Add dsp to sim_igen_machine.
1007 * configure: Regenerate.
1008 * mips.igen: Add dsp model and include dsp.igen.
1009 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
1010 because these instructions are extended in DSP ASE.
1011 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
1012 adding 6 DSP accumulator registers and 1 DSP control register.
1013 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
1014 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
1015 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
1016 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
1017 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
1018 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
1019 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
1020 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
1021 DSPCR_CCOND_SMASK): New define.
1022 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
1023 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
1024
21d14896
ILT		 10252005-07-08 Ian Lance Taylor <ian@airs.com>
1026
1027 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
1028
b16d63da 10292005-06-16 David Ung <davidu@mips.com>
72f4393d
L		 1030 Nigel Stephens <nigel@mips.com>
1031
1032 * mips.igen: New mips16e model and include m16e.igen.
1033 (check_u64): Add mips16e tag.
1034 * m16e.igen: New file for MIPS16e instructions.
1035 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
1036 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
1037 models.
1038 * configure: Regenerate.
b16d63da 1039
e70cb6cd 10402005-05-26 David Ung <davidu@mips.com>
72f4393d 1041
e70cb6cd
CD		 1042 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
1043 tags to all instructions which are applicable to the new ISAs.
1044 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
1045 vr.igen.
1046 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
72f4393d 1047 instructions.
e70cb6cd
CD		 1048 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
1049 to mips.igen.
1050 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
1051 * configure: Regenerate.
72f4393d 1052
2b193c4a
MK		 10532005-03-23 Mark Kettenis <kettenis@gnu.org>
1054
1055 * configure: Regenerate.
1056
35695fd6
AC		 10572005-01-14 Andrew Cagney <cagney@gnu.org>
1058
1059 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
1060 explicit call to AC_CONFIG_HEADER.
1061 * configure: Regenerate.
1062
f0569246
AC		 10632005-01-12 Andrew Cagney <cagney@gnu.org>
1064
1065 * configure.ac: Update to use ../common/common.m4.
1066 * configure: Re-generate.
1067
38f48d72
AC		 10682005-01-11 Andrew Cagney <cagney@localhost.localdomain>
1069
1070 * configure: Regenerated to track ../common/aclocal.m4 changes.
1071
b7026657
AC		 10722005-01-07 Andrew Cagney <cagney@gnu.org>
1073
1074 * configure.ac: Rename configure.in, require autoconf 2.59.
1075 * configure: Re-generate.
1076
379832de
HPN		 10772004-12-08 Hans-Peter Nilsson <hp@axis.com>
1078
1079 * configure: Regenerate for ../common/aclocal.m4 update.
1080
cd62154c 10812004-09-24 Monika Chaddha <monika@acmet.com>
72f4393d 1082
cd62154c
AC		 1083 Committed by Andrew Cagney.
1084 * m16.igen (CMP, CMPI): Fix assembler.
1085
e5da76ec
CD		 10862004-08-18 Chris Demetriou <cgd@broadcom.com>
1087
1088 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
1089 * configure: Regenerate.
1090
139181c8
CD		 10912004-06-25 Chris Demetriou <cgd@broadcom.com>
1092
1093 * configure.in (sim_m16_machine): Include mipsIII.
1094 * configure: Regenerate.
1095
1a27f959
CD		 10962004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
1097
72f4393d 1098 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
1a27f959
CD		 1099 from COP0_BADVADDR.
1100 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
1101
5dbb7b5a
CD		 11022004-04-10 Chris Demetriou <cgd@broadcom.com>
1103
1104 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
1105
14234056
CD		 11062004-04-09 Chris Demetriou <cgd@broadcom.com>
1107
1108 * mips.igen (check_fmt): Remove.
1109 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
1110 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
1111 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
1112 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
1113 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
1114 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
1115 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1116 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
1117 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
1118 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
1119
c6f9085c
CD		 11202004-04-09 Chris Demetriou <cgd@broadcom.com>
1121
1122 * sb1.igen (check_sbx): New function.
1123 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
1124
11d66e66 11252004-03-29 Chris Demetriou <cgd@broadcom.com>
0e1b7197
RS		 1126 Richard Sandiford <rsandifo@redhat.com>
1127
1128 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
1129 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
1130 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
1131 separate implementations for mipsIV and mipsV. Use new macros to
1132 determine whether the restrictions apply.
1133
b3208fb8
CD		 11342004-01-19 Chris Demetriou <cgd@broadcom.com>
1135
1136 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
1137 (check_mult_hilo): Improve comments.
1138 (check_div_hilo): Likewise. Also, fork off a new version
1139 to handle mips32/mips64 (since there are no hazards to check
1140 in MIPS32/MIPS64).
1141
9a1d84fb
CD		 11422003-06-17 Richard Sandiford <rsandifo@redhat.com>
1143
1144 * mips.igen (do_dmultx): Fix check for negative operands.
1145
ae451ac6
ILT		 11462003-05-16 Ian Lance Taylor <ian@airs.com>
1147
1148 * Makefile.in (SHELL): Make sure this is defined.
1149 (various): Use $(SHELL) whenever we invoke move-if-change.
1150
dd69d292
CD		 11512003-05-03 Chris Demetriou <cgd@broadcom.com>
1152
1153 * cp1.c: Tweak attribution slightly.
1154 * cp1.h: Likewise.
1155 * mdmx.c: Likewise.
1156 * mdmx.igen: Likewise.
1157 * mips3d.igen: Likewise.
1158 * sb1.igen: Likewise.
1159
bcd0068e
CD		 11602003-04-15 Richard Sandiford <rsandifo@redhat.com>
1161
1162 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
1163 unsigned operands.
1164
6b4a8935
AC		 11652003-02-27 Andrew Cagney <cagney@redhat.com>
1166
601da316
AC		 1167 * interp.c (sim_open): Rename _bfd to bfd.
1168 (sim_create_inferior): Ditto.
6b4a8935 1169
d29e330f
CD		 11702003-01-14 Chris Demetriou <cgd@broadcom.com>
1171
1172 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
1173
a2353a08
CD		 11742003-01-14 Chris Demetriou <cgd@broadcom.com>
1175
1176 * mips.igen (EI, DI): Remove.
1177
80551777
CD		 11782003-01-05 Richard Sandiford <rsandifo@redhat.com>
1179
1180 * Makefile.in (tmp-run-multi): Fix mips16 filter.
1181
4c54fc26
CD		 11822003-01-04 Richard Sandiford <rsandifo@redhat.com>
1183 Andrew Cagney <ac131313@redhat.com>
1184 Gavin Romig-Koch <gavin@redhat.com>
1185 Graydon Hoare <graydon@redhat.com>
1186 Aldy Hernandez <aldyh@redhat.com>
1187 Dave Brolley <brolley@redhat.com>
1188 Chris Demetriou <cgd@broadcom.com>
1189
1190 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
1191 (sim_mach_default): New variable.
1192 (mips64vr-*-*, mips64vrel-*-*): New configurations.
1193 Add a new simulator generator, MULTI.
1194 * configure: Regenerate.
1195 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
1196 (multi-run.o): New dependency.
1197 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
1198 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
1199 (tmp-multi): Combine them.
1200 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
1201 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
1202 (distclean-extra): New rule.
1203 * sim-main.h: Include bfd.h.
1204 (MIPS_MACH): New macro.
1205 * mips.igen (vr4120, vr5400, vr5500): New models.
1206 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
1207 * vr.igen: Replace with new version.
1208
e6c674b8
CD		 12092003-01-04 Chris Demetriou <cgd@broadcom.com>
1210
1211 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
1212 * configure: Regenerate.
1213
28f50ac8
CD		 12142002-12-31 Chris Demetriou <cgd@broadcom.com>
1215
1216 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
1217 * mips.igen: Remove all invocations of check_branch_bug and
1218 mark_branch_bug.
1219
5071ffe6
CD		 12202002-12-16 Chris Demetriou <cgd@broadcom.com>
1221
72f4393d 1222 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
5071ffe6 1223
06e7837e
CD		 12242002-07-30 Chris Demetriou <cgd@broadcom.com>
1225
1226 * mips.igen (do_load_double, do_store_double): New functions.
1227 (LDC1, SDC1): Rename to...
1228 (LDC1b, SDC1b): respectively.
1229 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
1230
2265c243
MS		 12312002-07-29 Michael Snyder <msnyder@redhat.com>
1232
1233 * cp1.c (fp_recip2): Modify initialization expression so that
1234 GCC will recognize it as constant.
1235
a2f8b4f3
CD		 12362002-06-18 Chris Demetriou <cgd@broadcom.com>
1237
1238 * mdmx.c (SD_): Delete.
1239 (Unpredictable): Re-define, for now, to directly invoke
1240 unpredictable_action().
1241 (mdmx_acc_op): Fix error in .ob immediate handling.
1242
b4b6c939
AC		 12432002-06-18 Andrew Cagney <cagney@redhat.com>
1244
1245 * interp.c (sim_firmware_command): Initialize `address'.
1246
c8cca39f
AC		 12472002-06-16 Andrew Cagney <ac131313@redhat.com>
1248
1249 * configure: Regenerated to track ../common/aclocal.m4 changes.
1250
e7e81181 12512002-06-14 Chris Demetriou <cgd@broadcom.com>
72f4393d 1252 Ed Satterthwaite <ehs@broadcom.com>
e7e81181
CD		 1253
1254 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
1255 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
1256 * mips.igen: Include mips3d.igen.
1257 (mips3d): New model name for MIPS-3D ASE instructions.
1258 (CVT.W.fmt): Don't use this instruction for word (source) format
72f4393d 1259 instructions.
e7e81181
CD		 1260 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
1261 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
1262 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
1263 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
1264 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
1265 (RSquareRoot1, RSquareRoot2): New macros.
1266 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
1267 (fp_rsqrt2): New functions.
1268 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
1269 * configure: Regenerate.
1270
3a2b820e 12712002-06-13 Chris Demetriou <cgd@broadcom.com>
72f4393d 1272 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 1273
1274 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
1275 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
1276 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
1277 (convert): Note that this function is not used for paired-single
1278 format conversions.
1279 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
1280 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
1281 (check_fmt_p): Enable paired-single support.
1282 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
1283 (PUU.PS): New instructions.
1284 (CVT.S.fmt): Don't use this instruction for paired-single format
1285 destinations.
1286 * sim-main.h (FP_formats): New value 'fmt_ps.'
1287 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
1288 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
1289
d18ea9c2
CD		 12902002-06-12 Chris Demetriou <cgd@broadcom.com>
1291
1292 * mips.igen: Fix formatting of function calls in
1293 many FP operations.
1294
95fd5cee
CD		 12952002-06-12 Chris Demetriou <cgd@broadcom.com>
1296
1297 * mips.igen (MOVN, MOVZ): Trace result.
1298 (TNEI): Print "tnei" as the opcode name in traces.
1299 (CEIL.W): Add disassembly string for traces.
1300 (RSQRT.fmt): Make location of disassembly string consistent
1301 with other instructions.
1302
4f0d55ae
CD		 13032002-06-12 Chris Demetriou <cgd@broadcom.com>
1304
1305 * mips.igen (X): Delete unused function.
1306
3c25f8c7
AC		 13072002-06-08 Andrew Cagney <cagney@redhat.com>
1308
1309 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
1310
f3c08b7e 13112002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1312 Ed Satterthwaite <ehs@broadcom.com>
f3c08b7e
CD		 1313
1314 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
1315 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
1316 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
1317 (fp_nmsub): New prototypes.
1318 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
1319 (NegMultiplySub): New defines.
1320 * mips.igen (RSQRT.fmt): Use RSquareRoot().
1321 (MADD.D, MADD.S): Replace with...
1322 (MADD.fmt): New instruction.
1323 (MSUB.D, MSUB.S): Replace with...
1324 (MSUB.fmt): New instruction.
1325 (NMADD.D, NMADD.S): Replace with...
1326 (NMADD.fmt): New instruction.
1327 (NMSUB.D, MSUB.S): Replace with...
1328 (NMSUB.fmt): New instruction.
1329
52714ff9 13302002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1331 Ed Satterthwaite <ehs@broadcom.com>
52714ff9
CD		 1332
1333 * cp1.c: Fix more comment spelling and formatting.
1334 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
1335 (denorm_mode): New function.
1336 (fpu_unary, fpu_binary): Round results after operation, collect
1337 status from rounding operations, and update the FCSR.
1338 (convert): Collect status from integer conversions and rounding
1339 operations, and update the FCSR. Adjust NaN values that result
1340 from conversions. Convert to use sim_io_eprintf rather than
1341 fprintf, and remove some debugging code.
1342 * cp1.h (fenr_FS): New define.
1343
577d8c4b
CD		 13442002-06-07 Chris Demetriou <cgd@broadcom.com>
1345
1346 * cp1.c (convert): Remove unusable debugging code, and move MIPS
1347 rounding mode to sim FP rounding mode flag conversion code into...
1348 (rounding_mode): New function.
1349
196496ed
CD		 13502002-06-07 Chris Demetriou <cgd@broadcom.com>
1351
1352 * cp1.c: Clean up formatting of a few comments.
1353 (value_fpr): Reformat switch statement.
1354
cfe9ea23 13552002-06-06 Chris Demetriou <cgd@broadcom.com>
72f4393d 1356 Ed Satterthwaite <ehs@broadcom.com>
cfe9ea23
CD		 1357
1358 * cp1.h: New file.
1359 * sim-main.h: Include cp1.h.
1360 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
1361 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
1362 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
1363 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
1364 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
1365 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
1366 * cp1.c: Don't include sim-fpu.h; already included by
1367 sim-main.h. Clean up formatting of some comments.
1368 (NaN, Equal, Less): Remove.
1369 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
1370 (fp_cmp): New functions.
1371 * mips.igen (do_c_cond_fmt): Remove.
1372 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
1373 Compare. Add result tracing.
1374 (CxC1): Remove, replace with...
1375 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
1376 (DMxC1): Remove, replace with...
1377 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
72f4393d
L		 1378 (MxC1): Remove, replace with...
1379 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
cfe9ea23 1380
ee7254b0
CD		 13812002-06-04 Chris Demetriou <cgd@broadcom.com>
1382
1383 * sim-main.h (FGRIDX): Remove, replace all uses with...
1384 (FGR_BASE): New macro.
1385 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
1386 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
1387 (NR_FGR, FGR): Likewise.
1388 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
1389 * mips.igen: Likewise.
1390
d3eb724f
CD		 13912002-06-04 Chris Demetriou <cgd@broadcom.com>
1392
1393 * cp1.c: Add an FSF Copyright notice to this file.
1394
ba46ddd0 13952002-06-04 Chris Demetriou <cgd@broadcom.com>
72f4393d 1396 Ed Satterthwaite <ehs@broadcom.com>
ba46ddd0
CD		 1397
1398 * cp1.c (Infinity): Remove.
1399 * sim-main.h (Infinity): Likewise.
1400
1401 * cp1.c (fp_unary, fp_binary): New functions.
1402 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
1403 (fp_sqrt): New functions, implemented in terms of the above.
1404 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1405 (Recip, SquareRoot): Remove (replaced by functions above).
1406 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
1407 (fp_recip, fp_sqrt): New prototypes.
1408 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1409 (Recip, SquareRoot): Replace prototypes with #defines which
1410 invoke the functions above.
72f4393d 1411
18d8a52d
CD		 14122002-06-03 Chris Demetriou <cgd@broadcom.com>
1413
1414 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
1415 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
1416 file, remove PARAMS from prototypes.
1417 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
1418 simulator state arguments.
1419 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
1420 pass simulator state arguments.
1421 * cp1.c (SD): Redefine as CPU_STATE(cpu).
1422 (store_fpr, convert): Remove 'sd' argument.
1423 (value_fpr): Likewise. Convert to use 'SD' instead.
1424
0f154cbd
CD		 14252002-06-03 Chris Demetriou <cgd@broadcom.com>
1426
1427 * cp1.c (Min, Max): Remove #if 0'd functions.
1428 * sim-main.h (Min, Max): Remove.
1429
e80fc152
CD		 14302002-06-03 Chris Demetriou <cgd@broadcom.com>
1431
1432 * cp1.c: fix formatting of switch case and default labels.
1433 * interp.c: Likewise.
1434 * sim-main.c: Likewise.
1435
bad673a9
CD		 14362002-06-03 Chris Demetriou <cgd@broadcom.com>
1437
1438 * cp1.c: Clean up comments which describe FP formats.
1439 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
1440
7cbea089 14412002-06-03 Chris Demetriou <cgd@broadcom.com>
72f4393d 1442 Ed Satterthwaite <ehs@broadcom.com>
7cbea089
CD		 1443
1444 * configure.in (mipsisa64sb1*-*-*): New target for supporting
1445 Broadcom SiByte SB-1 processor configurations.
1446 * configure: Regenerate.
1447 * sb1.igen: New file.
1448 * mips.igen: Include sb1.igen.
1449 (sb1): New model.
1450 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
1451 * mdmx.igen: Add "sb1" model to all appropriate functions and
1452 instructions.
1453 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
1454 (ob_func, ob_acc): Reference the above.
1455 (qh_acc): Adjust to keep the same size as ob_acc.
1456 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
1457 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
1458
909daa82
CD		 14592002-06-03 Chris Demetriou <cgd@broadcom.com>
1460
1461 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
1462
f4f1b9f1 14632002-06-02 Chris Demetriou <cgd@broadcom.com>
72f4393d 1464 Ed Satterthwaite <ehs@broadcom.com>
f4f1b9f1
CD		 1465
1466 * mips.igen (mdmx): New (pseudo-)model.
1467 * mdmx.c, mdmx.igen: New files.
1468 * Makefile.in (SIM_OBJS): Add mdmx.o.
1469 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
1470 New typedefs.
1471 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
1472 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
1473 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
1474 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
1475 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
1476 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
1477 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
1478 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
1479 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
1480 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
1481 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
1482 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
1483 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
1484 (qh_fmtsel): New macros.
1485 (_sim_cpu): New member "acc".
1486 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
1487 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
1488
5accf1ff
CD		 14892002-05-01 Chris Demetriou <cgd@broadcom.com>
1490
1491 * interp.c: Use 'deprecated' rather than 'depreciated.'
1492 * sim-main.h: Likewise.
1493
402586aa
CD		 14942002-05-01 Chris Demetriou <cgd@broadcom.com>
1495
1496 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
1497 which wouldn't compile anyway.
1498 * sim-main.h (unpredictable_action): New function prototype.
1499 (Unpredictable): Define to call igen function unpredictable().
1500 (NotWordValue): New macro to call igen function not_word_value().
1501 (UndefinedResult): Remove.
1502 * interp.c (undefined_result): Remove.
1503 (unpredictable_action): New function.
1504 * mips.igen (not_word_value, unpredictable): New functions.
1505 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
1506 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
1507 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
1508 NotWordValue() to check for unpredictable inputs, then
1509 Unpredictable() to handle them.
1510
c9b9995a
CD		 15112002-02-24 Chris Demetriou <cgd@broadcom.com>
1512
1513 * mips.igen: Fix formatting of calls to Unpredictable().
1514
e1015982
AC		 15152002-04-20 Andrew Cagney <ac131313@redhat.com>
1516
1517 * interp.c (sim_open): Revert previous change.
1518
b882a66b
AO		 15192002-04-18 Alexandre Oliva <aoliva@redhat.com>
1520
1521 * interp.c (sim_open): Disable chunk of code that wrote code in
1522 vector table entries.
1523
c429b7dd
CD		 15242002-03-19 Chris Demetriou <cgd@broadcom.com>
1525
1526 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
1527 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
1528 unused definitions.
1529
37d146fa
CD		 15302002-03-19 Chris Demetriou <cgd@broadcom.com>
1531
1532 * cp1.c: Fix many formatting issues.
1533
07892c0b
CD		 15342002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1535
1536 * cp1.c (fpu_format_name): New function to replace...
1537 (DOFMT): This. Delete, and update all callers.
1538 (fpu_rounding_mode_name): New function to replace...
1539 (RMMODE): This. Delete, and update all callers.
1540
487f79b7
CD		 15412002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1542
1543 * interp.c: Move FPU support routines from here to...
1544 * cp1.c: Here. New file.
1545 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
1546 (cp1.o): New target.
1547
1e799e28
CD		 15482002-03-12 Chris Demetriou <cgd@broadcom.com>
1549
1550 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
1551 * mips.igen (mips32, mips64): New models, add to all instructions
1552 and functions as appropriate.
1553 (loadstore_ea, check_u64): New variant for model mips64.
1554 (check_fmt_p): New variant for models mipsV and mips64, remove
1555 mipsV model marking fro other variant.
1556 (SLL) Rename to...
1557 (SLLa) this.
1558 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
1559 for mips32 and mips64.
1560 (DCLO, DCLZ): New instructions for mips64.
1561
82f728db
CD		 15622002-03-07 Chris Demetriou <cgd@broadcom.com>
1563
1564 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
1565 immediate or code as a hex value with the "%#lx" format.
1566 (ANDI): Likewise, and fix printed instruction name.
1567
b96e7ef1
CD		 15682002-03-05 Chris Demetriou <cgd@broadcom.com>
1569
1570 * sim-main.h (UndefinedResult, Unpredictable): New macros
1571 which currently do nothing.
1572
d35d4f70
CD		 15732002-03-05 Chris Demetriou <cgd@broadcom.com>
1574
1575 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
1576 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
1577 (status_CU3): New definitions.
1578
1579 * sim-main.h (ExceptionCause): Add new values for MIPS32
1580 and MIPS64: MDMX, MCheck, CacheErr. Update comments
1581 for DebugBreakPoint and NMIReset to note their status in
1582 MIPS32 and MIPS64.
1583 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
1584 (SignalExceptionCacheErr): New exception macros.
1585
3ad6f714
CD		 15862002-03-05 Chris Demetriou <cgd@broadcom.com>
1587
1588 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
1589 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
1590 is always enabled.
1591 (SignalExceptionCoProcessorUnusable): Take as argument the
1592 unusable coprocessor number.
1593
86b77b47
CD		 15942002-03-05 Chris Demetriou <cgd@broadcom.com>
1595
1596 * mips.igen: Fix formatting of all SignalException calls.
1597
97a88e93 15982002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 1599
1600 * sim-main.h (SIGNEXTEND): Remove.
1601
97a88e93 16022002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 1603
1604 * mips.igen: Remove gencode comment from top of file, fix
1605 spelling in another comment.
1606
97a88e93 16072002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 1608
1609 * mips.igen (check_fmt, check_fmt_p): New functions to check
1610 whether specific floating point formats are usable.
1611 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1612 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
1613 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
1614 Use the new functions.
1615 (do_c_cond_fmt): Remove format checks...
1616 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
1617
97a88e93 16182002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 1619
1620 * mips.igen: Fix formatting of check_fpu calls.
1621
41774c9d
CD		 16222002-03-03 Chris Demetriou <cgd@broadcom.com>
1623
1624 * mips.igen (FLOOR.L.fmt): Store correct destination register.
1625
4a0bd876
CD		 16262002-03-03 Chris Demetriou <cgd@broadcom.com>
1627
1628 * mips.igen: Remove whitespace at end of lines.
1629
09297648
CD		 16302002-03-02 Chris Demetriou <cgd@broadcom.com>
1631
1632 * mips.igen (loadstore_ea): New function to do effective
1633 address calculations.
1634 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
1635 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
1636 CACHE): Use loadstore_ea to do effective address computations.
1637
043b7057
CD		 16382002-03-02 Chris Demetriou <cgd@broadcom.com>
1639
1640 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
1641 * mips.igen (LL, CxC1, MxC1): Likewise.
1642
c1e8ada4
CD		 16432002-03-02 Chris Demetriou <cgd@broadcom.com>
1644
1645 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
1646 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
1647 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
1648 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
1649 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
1650 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
1651 Don't split opcode fields by hand, use the opcode field values
1652 provided by igen.
1653
3e1dca16
CD		 16542002-03-01 Chris Demetriou <cgd@broadcom.com>
1655
1656 * mips.igen (do_divu): Fix spacing.
1657
1658 * mips.igen (do_dsllv): Move to be right before DSLLV,
1659 to match the rest of the do_<shift> functions.
1660
fff8d27d
CD		 16612002-03-01 Chris Demetriou <cgd@broadcom.com>
1662
1663 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
1664 DSRL32, do_dsrlv): Trace inputs and results.
1665
0d3e762b
CD		 16662002-03-01 Chris Demetriou <cgd@broadcom.com>
1667
1668 * mips.igen (CACHE): Provide instruction-printing string.
1669
1670 * interp.c (signal_exception): Comment tokens after #endif.
1671
eb5fcf93
CD		 16722002-02-28 Chris Demetriou <cgd@broadcom.com>
1673
1674 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
72f4393d
L		 1675 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
1676 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
1677 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
1678 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
1679 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
1680 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
eb5fcf93
CD		 1681 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
1682
bb22bd7d
CD		 16832002-02-28 Chris Demetriou <cgd@broadcom.com>
1684
1685 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
1686 instruction-printing string.
1687 (LWU): Use '64' as the filter flag.
1688
91a177cf
CD		 16892002-02-28 Chris Demetriou <cgd@broadcom.com>
1690
1691 * mips.igen (SDXC1): Fix instruction-printing string.
1692
387f484a
CD		 16932002-02-28 Chris Demetriou <cgd@broadcom.com>
1694
1695 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
1696 filter flags "32,f".
1697
3d81f391
CD		 16982002-02-27 Chris Demetriou <cgd@broadcom.com>
1699
1700 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1701 as the filter flag.
1702
af5107af
CD		 17032002-02-27 Chris Demetriou <cgd@broadcom.com>
1704
1705 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1706 add a comma) so that it more closely match the MIPS ISA
1707 documentation opcode partitioning.
1708 (PREF): Put useful names on opcode fields, and include
1709 instruction-printing string.
1710
ca971540
CD		 17112002-02-27 Chris Demetriou <cgd@broadcom.com>
1712
1713 * mips.igen (check_u64): New function which in the future will
1714 check whether 64-bit instructions are usable and signal an
1715 exception if not. Currently a no-op.
1716 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1717 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1718 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1719 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1720
1721 * mips.igen (check_fpu): New function which in the future will
1722 check whether FPU instructions are usable and signal an exception
1723 if not. Currently a no-op.
1724 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1725 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1726 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1727 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1728 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1729 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1730 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1731 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1732
1c47a468
CD		 17332002-02-27 Chris Demetriou <cgd@broadcom.com>
1734
1735 * mips.igen (do_load_left, do_load_right): Move to be immediately
1736 following do_load.
1737 (do_store_left, do_store_right): Move to be immediately following
1738 do_store.
1739
603a98e7
CD		 17402002-02-27 Chris Demetriou <cgd@broadcom.com>
1741
1742 * mips.igen (mipsV): New model name. Also, add it to
1743 all instructions and functions where it is appropriate.
1744
c5d00cc7
CD		 17452002-02-18 Chris Demetriou <cgd@broadcom.com>
1746
1747 * mips.igen: For all functions and instructions, list model
1748 names that support that instruction one per line.
1749
074e9cb8
CD		 17502002-02-11 Chris Demetriou <cgd@broadcom.com>
1751
1752 * mips.igen: Add some additional comments about supported
1753 models, and about which instructions go where.
1754 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1755 order as is used in the rest of the file.
1756
9805e229
CD		 17572002-02-11 Chris Demetriou <cgd@broadcom.com>
1758
1759 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1760 indicating that ALU32_END or ALU64_END are there to check
1761 for overflow.
1762 (DADD): Likewise, but also remove previous comment about
1763 overflow checking.
1764
f701dad2
CD		 17652002-02-10 Chris Demetriou <cgd@broadcom.com>
1766
1767 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1768 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1769 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1770 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1771 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1772 fields (i.e., add and move commas) so that they more closely
1773 match the MIPS ISA documentation opcode partitioning.
1774
17752002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098 1776
72f4393d
L		 1777 * mips.igen (ADDI): Print immediate value.
1778 (BREAK): Print code.
1779 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1780 (SLL): Print "nop" specially, and don't run the code
1781 that does the shift for the "nop" case.
20ae0098 1782
9e52972e
FF		 17832001-11-17 Fred Fish <fnf@redhat.com>
1784
1785 * sim-main.h (float_operation): Move enum declaration outside
1786 of _sim_cpu struct declaration.
1787
c0efbca4
JB		 17882001-04-12 Jim Blandy <jimb@redhat.com>
1789
1790 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1791 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1792 set of the FCSR.
1793 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1794 PENDING_FILL, and you can get the intended effect gracefully by
1795 calling PENDING_SCHED directly.
1796
fb891446
BE		 17972001-02-23 Ben Elliston <bje@redhat.com>
1798
1799 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1800 already defined elsewhere.
1801
8030f857
BE		 18022001-02-19 Ben Elliston <bje@redhat.com>
1803
1804 * sim-main.h (sim_monitor): Return an int.
1805 * interp.c (sim_monitor): Add return values.
1806 (signal_exception): Handle error conditions from sim_monitor.
1807
56b48a7a
CD		 18082001-02-08 Ben Elliston <bje@redhat.com>
1809
1810 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1811 (store_memory): Likewise, pass cia to sim_core_write*.
1812
d3ee60d9
FCE		 18132000-10-19 Frank Ch. Eigler <fche@redhat.com>
1814
1815 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1816 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1817
071da002
AC		 1818Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1819
1820 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1821 * Makefile.in: Don't delete *.igen when cleaning directory.
1822
a28c02cd
AC		 1823Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1824
1825 * m16.igen (break): Call SignalException not sim_engine_halt.
1826
80ee11fa
AC		 1827Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1828
1829 From Jason Eckhardt:
1830 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1831
673388c0
AC		 1832Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1833
1834 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1835
4c0deff4
NC		 18362000-05-24 Michael Hayes <mhayes@cygnus.com>
1837
1838 * mips.igen (do_dmultx): Fix typo.
1839
eb2d80b4
AC		 1840Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1841
1842 * configure: Regenerated to track ../common/aclocal.m4 changes.
1843
dd37a34b
AC		 1844Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1845
1846 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1847
4c0deff4
NC		 18482000-04-12 Frank Ch. Eigler <fche@redhat.com>
1849
1850 * sim-main.h (GPR_CLEAR): Define macro.
1851
e30db738
AC		 1852Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1853
1854 * interp.c (decode_coproc): Output long using %lx and not %s.
1855
cb7450ea
FCE		 18562000-03-21 Frank Ch. Eigler <fche@redhat.com>
1857
1858 * interp.c (sim_open): Sort & extend dummy memory regions for
1859 --board=jmr3904 for eCos.
1860
a3027dd7
FCE		 18612000-03-02 Frank Ch. Eigler <fche@redhat.com>
1862
1863 * configure: Regenerated.
1864
1865Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1866
1867 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1868 calls, conditional on the simulator being in verbose mode.
1869
dfcd3bfb
JM		 1870Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1871
1872 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1873 cache don't get ReservedInstruction traps.
1874
c2d11a7d
JM		 18751999-11-29 Mark Salter <msalter@cygnus.com>
1876
1877 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1878 to clear status bits in sdisr register. This is how the hardware works.
1879
1880 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1881 being used by cygmon.
1882
4ce44c66
JM		 18831999-11-11 Andrew Haley <aph@cygnus.com>
1884
1885 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1886 instructions.
1887
cff3e48b
JM		 1888Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1889
1890 * mips.igen (MULT): Correct previous mis-applied patch.
1891
d4f3574e
SS		 1892Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1893
1894 * mips.igen (delayslot32): Handle sequence like
1895 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1896 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1897 (MULT): Actually pass the third register...
1898
18991999-09-03 Mark Salter <msalter@cygnus.com>
1900
1901 * interp.c (sim_open): Added more memory aliases for additional
1902 hardware being touched by cygmon on jmr3904 board.
1903
1904Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1905
1906 * configure: Regenerated to track ../common/aclocal.m4 changes.
1907
a0b3c4fd
JM		 1908Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1909
1910 * interp.c (sim_store_register): Handle case where client - GDB -
1911 specifies that a 4 byte register is 8 bytes in size.
1912 (sim_fetch_register): Ditto.
72f4393d 1913
adf40b2e
JM		 19141999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1915
1916 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1917 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1918 (idt_monitor_base): Base address for IDT monitor traps.
1919 (pmon_monitor_base): Ditto for PMON.
1920 (lsipmon_monitor_base): Ditto for LSI PMON.
1921 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1922 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1923 (sim_firmware_command): New function.
1924 (mips_option_handler): Call it for OPTION_FIRMWARE.
1925 (sim_open): Allocate memory for idt_monitor region. If "--board"
1926 option was given, add no monitor by default. Add BREAK hooks only if
1927 monitors are also there.
72f4393d 1928
43e526b9
JM		 1929Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1930
1931 * interp.c (sim_monitor): Flush output before reading input.
1932
1933Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1934
1935 * tconfig.in (SIM_HANDLES_LMA): Always define.
1936
1937Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1938
1939 From Mark Salter <msalter@cygnus.com>:
1940 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1941 (sim_open): Add setup for BSP board.
1942
9846de1b
JM		 1943Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1944
1945 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1946 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1947 them as unimplemented.
1948
cd0fc7c3
SS		 19491999-05-08 Felix Lee <flee@cygnus.com>
1950
1951 * configure: Regenerated to track ../common/aclocal.m4 changes.
72f4393d 1952
7a292a7a
SS		 19531999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1954
1955 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1956
1957Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1958
1959 * configure.in: Any mips64vr5*-*-* target should have
1960 -DTARGET_ENABLE_FR=1.
1961 (default_endian): Any mips64vr*el-*-* target should default to
1962 LITTLE_ENDIAN.
1963 * configure: Re-generate.
1964
19651999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1966
1967 * mips.igen (ldl): Extend from _16_, not 32.
1968
1969Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1970
1971 * interp.c (sim_store_register): Force registers written to by GDB
1972 into an un-interpreted state.
1973
c906108c
SS		 19741999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1975
1976 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1977 CPU, start periodic background I/O polls.
72f4393d 1978 (tx3904sio_poll): New function: periodic I/O poller.
c906108c
SS		 1979
19801998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1981
1982 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
72f4393d 1983
c906108c
SS		 1984Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1985
1986 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1987 case statement.
1988
19891998-12-29 Frank Ch. Eigler <fche@cygnus.com>
72f4393d
L		 1990
1991 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
c906108c
SS		 1992 (load_word): Call SIM_CORE_SIGNAL hook on error.
1993 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1994 starting. For exception dispatching, pass PC instead of NULL_CIA.
1995 (decode_coproc): Use COP0_BADVADDR to store faulting address.
72f4393d 1996 * sim-main.h (COP0_BADVADDR): Define.
c906108c
SS		 1997 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1998 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
72f4393d 1999 (_sim_cpu): Add exc_* fields to store register value snapshots.
c906108c
SS		 2000 * mips.igen (*): Replace memory-related SignalException* calls
2001 with references to SIM_CORE_SIGNAL hook.
72f4393d 2002
c906108c
SS		 2003 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
2004 fix.
2005 * sim-main.c (*): Minor warning cleanups.
72f4393d 2006
c906108c
SS		 20071998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
2008
2009 * m16.igen (DADDIU5): Correct type-o.
2010
2011Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
2012
2013 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
2014 variables.
2015
2016Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
2017
2018 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
2019 to include path.
2020 (interp.o): Add dependency on itable.h
2021 (oengine.c, gencode): Delete remaining references.
2022 (BUILT_SRC_FROM_GEN): Clean up.
72f4393d 2023
c906108c 20241998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
72f4393d 2025
c906108c
SS		 2026 * vr4run.c: New.
2027 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
2028 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
2029 tmp-run-hack) : New.
2030 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
72f4393d 2031 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
c906108c
SS		 2032 Drop the "64" qualifier to get the HACK generator working.
2033 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
2034 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
2035 qualifier to get the hack generator working.
2036 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
2037 (DSLL): Use do_dsll.
2038 (DSLLV): Use do_dsllv.
2039 (DSRA): Use do_dsra.
2040 (DSRL): Use do_dsrl.
2041 (DSRLV): Use do_dsrlv.
2042 (BC1): Move *vr4100 to get the HACK generator working.
72f4393d 2043 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
c906108c
SS		 2044 get the HACK generator working.
2045 (MACC) Rename to get the HACK generator working.
2046 (DMACC,MACCS,DMACCS): Add the 64.
72f4393d 2047
c906108c
SS		 20481998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
2049
2050 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
2051 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
72f4393d 2052
c906108c
SS		 20531998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
2054
2055 * mips/interp.c (DEBUG): Cleanups.
2056
20571998-12-10 Frank Ch. Eigler <fche@cygnus.com>
2058
2059 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
2060 (tx3904sio_tickle): fflush after a stdout character output.
72f4393d 2061
c906108c
SS		 20621998-12-03 Frank Ch. Eigler <fche@cygnus.com>
2063
2064 * interp.c (sim_close): Uninstall modules.
2065
2066Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
2067
2068 * sim-main.h, interp.c (sim_monitor): Change to global
2069 function.
2070
2071Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2072
2073 * configure.in (vr4100): Only include vr4100 instructions in
2074 simulator.
2075 * configure: Re-generate.
2076 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
2077
2078Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
2079
2080 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
2081 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
2082 true alternative.
2083
2084 * configure.in (sim_default_gen, sim_use_gen): Replace with
2085 sim_gen.
2086 (--enable-sim-igen): Delete config option. Always using IGEN.
2087 * configure: Re-generate.
72f4393d 2088
c906108c
SS		 2089 * Makefile.in (gencode): Kill, kill, kill.
2090 * gencode.c: Ditto.
72f4393d 2091
c906108c
SS		 2092Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
2093
2094 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
2095 bit mips16 igen simulator.
2096 * configure: Re-generate.
2097
2098 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
2099 as part of vr4100 ISA.
2100 * vr.igen: Mark all instructions as 64 bit only.
2101
2102Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2103
2104 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
2105 Pacify GCC.
2106
2107Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
2108
2109 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
2110 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
2111 * configure: Re-generate.
2112
2113 * m16.igen (BREAK): Define breakpoint instruction.
2114 (JALX32): Mark instruction as mips16 and not r3900.
2115 * mips.igen (C.cond.fmt): Fix typo in instruction format.
2116
2117 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
2118
2119Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
2120
2121 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
2122 insn as a debug breakpoint.
2123
2124 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
2125 pending.slot_size.
2126 (PENDING_SCHED): Clean up trace statement.
2127 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
2128 (PENDING_FILL): Delay write by only one cycle.
2129 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
2130
2131 * sim-main.c (pending_tick): Clean up trace statements. Add trace
2132 of pending writes.
2133 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
2134 32 & 64.
2135 (pending_tick): Move incrementing of index to FOR statement.
2136 (pending_tick): Only update PENDING_OUT after a write has occured.
72f4393d 2137
c906108c
SS		 2138 * configure.in: Add explicit mips-lsi-* target. Use gencode to
2139 build simulator.
2140 * configure: Re-generate.
72f4393d 2141
c906108c
SS		 2142 * interp.c (sim_engine_run OLD): Delete explicit call to
2143 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
72f4393d 2144
c906108c
SS		 2145Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
2146
2147 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
2148 interrupt level number to match changed SignalExceptionInterrupt
2149 macro.
2150
2151Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
2152
2153 * interp.c: #include "itable.h" if WITH_IGEN.
2154 (get_insn_name): New function.
2155 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
2156 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
2157
2158Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
2159
2160 * configure: Rebuilt to inhale new common/aclocal.m4.
2161
2162Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
2163
2164 * dv-tx3904sio.c: Include sim-assert.h.
2165
2166Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
2167
2168 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
2169 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
2170 Reorganize target-specific sim-hardware checks.
2171 * configure: rebuilt.
2172 * interp.c (sim_open): For tx39 target boards, set
2173 OPERATING_ENVIRONMENT, add tx3904sio devices.
2174 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
2175 ROM executables. Install dv-sockser into sim-modules list.
72f4393d 2176
c906108c
SS		 2177 * dv-tx3904irc.c: Compiler warning clean-up.
2178 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
2179 frequent hw-trace messages.
2180
2181Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
2182
2183 * vr.igen (MulAcc): Identify as a vr4100 specific function.
2184
2185Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2186
2187 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
2188
2189 * vr.igen: New file.
2190 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
2191 * mips.igen: Define vr4100 model. Include vr.igen.
2192Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
2193
2194 * mips.igen (check_mf_hilo): Correct check.
2195
2196Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2197
2198 * sim-main.h (interrupt_event): Add prototype.
2199
2200 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
2201 register_ptr, register_value.
2202 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
2203
2204 * sim-main.h (tracefh): Make extern.
2205
2206Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
2207
2208 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
72f4393d 2209 Reduce unnecessarily high timer event frequency.
c906108c 2210 * dv-tx3904cpu.c: Ditto for interrupt event.
72f4393d 2211
c906108c
SS		 2212Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
2213
2214 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
2215 to allay warnings.
2216 (interrupt_event): Made non-static.
72f4393d 2217
c906108c
SS		 2218 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
2219 interchange of configuration values for external vs. internal
2220 clock dividers.
72f4393d 2221
c906108c
SS		 2222Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
2223
72f4393d 2224 * mips.igen (BREAK): Moved code to here for
c906108c
SS		 2225 simulator-reserved break instructions.
2226 * gencode.c (build_instruction): Ditto.
2227 * interp.c (signal_exception): Code moved from here. Non-
72f4393d 2228 reserved instructions now use exception vector, rather
c906108c
SS		 2229 than halting sim.
2230 * sim-main.h: Moved magic constants to here.
2231
2232Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
2233
2234 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
2235 register upon non-zero interrupt event level, clear upon zero
2236 event value.
2237 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
2238 by passing zero event value.
2239 (*_io_{read,write}_buffer): Endianness fixes.
2240 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
2241 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
2242
2243 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
2244 serial I/O and timer module at base address 0xFFFF0000.
72f4393d 2245
c906108c
SS		 2246Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
2247
72f4393d 2248 * mips.igen (SWC1) : Correct the handling of ReverseEndian
c906108c
SS		 2249 and BigEndianCPU.
2250
2251Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
2252
2253 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
2254 parts.
2255 * configure: Update.
2256
2257Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
2258
2259 * dv-tx3904tmr.c: New file - implements tx3904 timer.
2260 * dv-tx3904{irc,cpu}.c: Mild reformatting.
2261 * configure.in: Include tx3904tmr in hw_device list.
2262 * configure: Rebuilt.
2263 * interp.c (sim_open): Instantiate three timer instances.
2264 Fix address typo of tx3904irc instance.
2265
2266Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
2267
2268 * interp.c (signal_exception): SystemCall exception now uses
2269 the exception vector.
2270
2271Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
2272
2273 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
2274 to allay warnings.
2275
2276Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2277
2278 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
2279
2280Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
2281
2282 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
2283
2284 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
2285 sim-main.h. Declare a struct hw_descriptor instead of struct
2286 hw_device_descriptor.
2287
2288Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
2289
2290 * mips.igen (do_store_left, do_load_left): Compute nr of left and
2291 right bits and then re-align left hand bytes to correct byte
2292 lanes. Fix incorrect computation in do_store_left when loading
2293 bytes from second word.
2294
2295Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2296
2297 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
2298 * interp.c (sim_open): Only create a device tree when HW is
2299 enabled.
2300
2301 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
2302 * interp.c (signal_exception): Ditto.
2303
2304Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
2305
2306 * gencode.c: Mark BEGEZALL as LIKELY.
2307
2308Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
2309
2310 * sim-main.h (ALU32_END): Sign extend 32 bit results.
2311 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
72f4393d 2312
c906108c
SS		 2313Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
2314
2315 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
2316 modules. Recognize TX39 target with "mips*tx39" pattern.
2317 * configure: Rebuilt.
2318 * sim-main.h (*): Added many macros defining bits in
2319 TX39 control registers.
2320 (SignalInterrupt): Send actual PC instead of NULL.
2321 (SignalNMIReset): New exception type.
2322 * interp.c (board): New variable for future use to identify
2323 a particular board being simulated.
2324 (mips_option_handler,mips_options): Added "--board" option.
2325 (interrupt_event): Send actual PC.
2326 (sim_open): Make memory layout conditional on board setting.
2327 (signal_exception): Initial implementation of hardware interrupt
2328 handling. Accept another break instruction variant for simulator
2329 exit.
2330 (decode_coproc): Implement RFE instruction for TX39.
2331 (mips.igen): Decode RFE instruction as such.
2332 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
2333 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
2334 bbegin to implement memory map.
2335 * dv-tx3904cpu.c: New file.
2336 * dv-tx3904irc.c: New file.
2337
2338Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
2339
2340 * mips.igen (check_mt_hilo): Create a separate r3900 version.
2341
2342Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
2343
2344 * tx.igen (madd,maddu): Replace calls to check_op_hilo
2345 with calls to check_div_hilo.
2346
2347Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
2348
2349 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
2350 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
72f4393d 2351 Add special r3900 version of do_mult_hilo.
c906108c
SS		 2352 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
2353 with calls to check_mult_hilo.
2354 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
2355 with calls to check_div_hilo.
2356
2357Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
2358
2359 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
2360 Document a replacement.
2361
2362Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
2363
2364 * interp.c (sim_monitor): Make mon_printf work.
2365
2366Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
2367
2368 * sim-main.h (INSN_NAME): New arg `cpu'.
2369
2370Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
2371
72f4393d 2372 * configure: Regenerated to track ../common/aclocal.m4 changes.
c906108c
SS		 2373
2374Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
2375
2376 * configure: Regenerated to track ../common/aclocal.m4 changes.
2377 * config.in: Ditto.
2378
2379Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
2380
2381 * acconfig.h: New file.
2382 * configure.in: Reverted change of Apr 24; use sinclude again.
2383
2384Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
2385
2386 * configure: Regenerated to track ../common/aclocal.m4 changes.
2387 * config.in: Ditto.
2388
2389Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
2390
2391 * configure.in: Don't call sinclude.
2392
2393Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
2394
2395 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
2396
2397Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2398
2399 * mips.igen (ERET): Implement.
2400
2401 * interp.c (decode_coproc): Return sign-extended EPC.
2402
2403 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
2404
2405 * interp.c (signal_exception): Do not ignore Trap.
2406 (signal_exception): On TRAP, restart at exception address.
2407 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
2408 (signal_exception): Update.
2409 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
2410 so that TRAP instructions are caught.
2411
2412Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
2413
2414 * sim-main.h (struct hilo_access, struct hilo_history): Define,
2415 contains HI/LO access history.
2416 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
2417 (HIACCESS, LOACCESS): Delete, replace with
2418 (HIHISTORY, LOHISTORY): New macros.
2419 (CHECKHILO): Delete all, moved to mips.igen
72f4393d 2420
c906108c
SS		 2421 * gencode.c (build_instruction): Do not generate checks for
2422 correct HI/LO register usage.
2423
2424 * interp.c (old_engine_run): Delete checks for correct HI/LO
2425 register usage.
2426
2427 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
2428 check_mf_cycles): New functions.
2429 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
2430 do_divu, domultx, do_mult, do_multu): Use.
2431
2432 * tx.igen ("madd", "maddu"): Use.
72f4393d 2433
c906108c
SS		 2434Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
2435
2436 * mips.igen (DSRAV): Use function do_dsrav.
2437 (SRAV): Use new function do_srav.
2438
2439 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
2440 (B): Sign extend 11 bit immediate.
2441 (EXT-B*): Shift 16 bit immediate left by 1.
2442 (ADDIU*): Don't sign extend immediate value.
2443
2444Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2445
2446 * m16run.c (sim_engine_run): Restore CIA after handling an event.
2447
2448 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
2449 functions.
2450
2451 * mips.igen (delayslot32, nullify_next_insn): New functions.
2452 (m16.igen): Always include.
2453 (do_*): Add more tracing.
2454
2455 * m16.igen (delayslot16): Add NIA argument, could be called by a
2456 32 bit MIPS16 instruction.
72f4393d 2457
c906108c
SS		 2458 * interp.c (ifetch16): Move function from here.
2459 * sim-main.c (ifetch16): To here.
72f4393d 2460
c906108c
SS		 2461 * sim-main.c (ifetch16, ifetch32): Update to match current
2462 implementations of LH, LW.
2463 (signal_exception): Don't print out incorrect hex value of illegal
2464 instruction.
2465
2466Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2467
2468 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
2469 instruction.
2470
2471 * m16.igen: Implement MIPS16 instructions.
72f4393d 2472
c906108c
SS		 2473 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
2474 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
2475 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
2476 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
2477 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
2478 bodies of corresponding code from 32 bit insn to these. Also used
2479 by MIPS16 versions of functions.
72f4393d 2480
c906108c
SS		 2481 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
2482 (IMEM16): Drop NR argument from macro.
2483
2484Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2485
2486 * Makefile.in (SIM_OBJS): Add sim-main.o.
2487
2488 * sim-main.h (address_translation, load_memory, store_memory,
2489 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
2490 as INLINE_SIM_MAIN.
2491 (pr_addr, pr_uword64): Declare.
2492 (sim-main.c): Include when H_REVEALS_MODULE_P.
72f4393d 2493
c906108c
SS		 2494 * interp.c (address_translation, load_memory, store_memory,
2495 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
2496 from here.
2497 * sim-main.c: To here. Fix compilation problems.
72f4393d 2498
c906108c
SS		 2499 * configure.in: Enable inlining.
2500 * configure: Re-config.
2501
2502Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2503
2504 * configure: Regenerated to track ../common/aclocal.m4 changes.
2505
2506Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2507
2508 * mips.igen: Include tx.igen.
2509 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
2510 * tx.igen: New file, contains MADD and MADDU.
2511
2512 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
2513 the hardwired constant `7'.
2514 (store_memory): Ditto.
2515 (LOADDRMASK): Move definition to sim-main.h.
2516
2517 mips.igen (MTC0): Enable for r3900.
2518 (ADDU): Add trace.
2519
2520 mips.igen (do_load_byte): Delete.
2521 (do_load, do_store, do_load_left, do_load_write, do_store_left,
2522 do_store_right): New functions.
2523 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
2524
2525 configure.in: Let the tx39 use igen again.
2526 configure: Update.
72f4393d 2527
c906108c
SS		 2528Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2529
2530 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
2531 not an address sized quantity. Return zero for cache sizes.
2532
2533Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
2534
2535 * mips.igen (r3900): r3900 does not support 64 bit integer
2536 operations.
2537
2538Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
2539
2540 * configure.in (mipstx39*-*-*): Use gencode simulator rather
2541 than igen one.
2542 * configure : Rebuild.
72f4393d 2543
c906108c
SS		 2544Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
2545
2546 * configure: Regenerated to track ../common/aclocal.m4 changes.
2547
2548Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2549
2550 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
2551
2552Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
2553
2554 * configure: Regenerated to track ../common/aclocal.m4 changes.
2555 * config.in: Regenerated to track ../common/aclocal.m4 changes.
2556
2557Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2558
2559 * configure: Regenerated to track ../common/aclocal.m4 changes.
2560
2561Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
2562
2563 * interp.c (Max, Min): Comment out functions. Not yet used.
2564
2565Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
2566
2567 * configure: Regenerated to track ../common/aclocal.m4 changes.
2568
2569Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
2570
2571 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
2572 configurable settings for stand-alone simulator.
72f4393d 2573
c906108c 2574 * configure.in: Added X11 search, just in case.
72f4393d 2575
c906108c
SS		 2576 * configure: Regenerated.
2577
2578Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
2579
2580 * interp.c (sim_write, sim_read, load_memory, store_memory):
2581 Replace sim_core_*_map with read_map, write_map, exec_map resp.
2582
2583Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
2584
2585 * sim-main.h (GETFCC): Return an unsigned value.
2586
2587Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2588
2589 * mips.igen (DIV): Fix check for -1 / MIN_INT.
2590 (DADD): Result destination is RD not RT.
2591
2592Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2593
2594 * sim-main.h (HIACCESS, LOACCESS): Always define.
2595
2596 * mdmx.igen (Maxi, Mini): Rename Max, Min.
2597
2598 * interp.c (sim_info): Delete.
2599
2600Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
2601
2602 * interp.c (DECLARE_OPTION_HANDLER): Use it.
2603 (mips_option_handler): New argument `cpu'.
2604 (sim_open): Update call to sim_add_option_table.
2605
2606Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
2607
2608 * mips.igen (CxC1): Add tracing.
2609
2610Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
2611
2612 * sim-main.h (Max, Min): Declare.
2613
2614 * interp.c (Max, Min): New functions.
2615
2616 * mips.igen (BC1): Add tracing.
72f4393d 2617
c906108c 2618Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
72f4393d 2619
c906108c 2620 * interp.c Added memory map for stack in vr4100
72f4393d 2621
c906108c
SS		 2622Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
2623
2624 * interp.c (load_memory): Add missing "break"'s.
2625
2626Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2627
2628 * interp.c (sim_store_register, sim_fetch_register): Pass in
2629 length parameter. Return -1.
2630
2631Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
2632
2633 * interp.c: Added hardware init hook, fixed warnings.
2634
2635Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2636
2637 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
2638
2639Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
2640
2641 * interp.c (ifetch16): New function.
2642
2643 * sim-main.h (IMEM32): Rename IMEM.
2644 (IMEM16_IMMED): Define.
2645 (IMEM16): Define.
2646 (DELAY_SLOT): Update.
72f4393d 2647
c906108c 2648 * m16run.c (sim_engine_run): New file.
72f4393d 2649
c906108c
SS		 2650 * m16.igen: All instructions except LB.
2651 (LB): Call do_load_byte.
2652 * mips.igen (do_load_byte): New function.
2653 (LB): Call do_load_byte.
2654
2655 * mips.igen: Move spec for insn bit size and high bit from here.
2656 * Makefile.in (tmp-igen, tmp-m16): To here.
2657
2658 * m16.dc: New file, decode mips16 instructions.
2659
2660 * Makefile.in (SIM_NO_ALL): Define.
2661 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
2662
2663Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
2664
2665 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
2666 point unit to 32 bit registers.
2667 * configure: Re-generate.
2668
2669Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2670
2671 * configure.in (sim_use_gen): Make IGEN the default simulator
2672 generator for generic 32 and 64 bit mips targets.
2673 * configure: Re-generate.
2674
2675Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2676
2677 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
2678 bitsize.
2679
2680 * interp.c (sim_fetch_register, sim_store_register): Read/write
2681 FGR from correct location.
2682 (sim_open): Set size of FGR's according to
2683 WITH_TARGET_FLOATING_POINT_BITSIZE.
72f4393d 2684
c906108c
SS		 2685 * sim-main.h (FGR): Store floating point registers in a separate
2686 array.
2687
2688Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
2689
2690 * configure: Regenerated to track ../common/aclocal.m4 changes.
2691
2692Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2693
2694 * interp.c (ColdReset): Call PENDING_INVALIDATE.
2695
2696 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
2697
2698 * interp.c (pending_tick): New function. Deliver pending writes.
2699
2700 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2701 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2702 it can handle mixed sized quantites and single bits.
72f4393d 2703
c906108c
SS		 2704Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2705
2706 * interp.c (oengine.h): Do not include when building with IGEN.
2707 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2708 (sim_info): Ditto for PROCESSOR_64BIT.
2709 (sim_monitor): Replace ut_reg with unsigned_word.
2710 (*): Ditto for t_reg.
2711 (LOADDRMASK): Define.
2712 (sim_open): Remove defunct check that host FP is IEEE compliant,
2713 using software to emulate floating point.
2714 (value_fpr, ...): Always compile, was conditional on HASFPU.
2715
2716Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2717
2718 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2719 size.
2720
2721 * interp.c (SD, CPU): Define.
2722 (mips_option_handler): Set flags in each CPU.
2723 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2724 (sim_close): Do not clear STATE, deleted anyway.
2725 (sim_write, sim_read): Assume CPU zero's vm should be used for
2726 data transfers.
2727 (sim_create_inferior): Set the PC for all processors.
2728 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2729 argument.
2730 (mips16_entry): Pass correct nr of args to store_word, load_word.
2731 (ColdReset): Cold reset all cpu's.
2732 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2733 (sim_monitor, load_memory, store_memory, signal_exception): Use
2734 `CPU' instead of STATE_CPU.
2735
2736
2737 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2738 SD or CPU_.
72f4393d 2739
c906108c
SS		 2740 * sim-main.h (signal_exception): Add sim_cpu arg.
2741 (SignalException*): Pass both SD and CPU to signal_exception.
2742 * interp.c (signal_exception): Update.
72f4393d 2743
c906108c
SS		 2744 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2745 Ditto
2746 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2747 address_translation): Ditto
2748 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
72f4393d 2749
c906108c
SS		 2750Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2751
2752 * configure: Regenerated to track ../common/aclocal.m4 changes.
2753
2754Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2755
2756 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2757
72f4393d 2758 * mips.igen (model): Map processor names onto BFD name.
c906108c
SS		 2759
2760 * sim-main.h (CPU_CIA): Delete.
2761 (SET_CIA, GET_CIA): Define
2762
2763Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2764
2765 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2766 regiser.
2767
2768 * configure.in (default_endian): Configure a big-endian simulator
2769 by default.
2770 * configure: Re-generate.
72f4393d 2771
c906108c
SS		 2772Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2773
2774 * configure: Regenerated to track ../common/aclocal.m4 changes.
2775
2776Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2777
2778 * interp.c (sim_monitor): Handle Densan monitor outbyte
2779 and inbyte functions.
2780
27811997-12-29 Felix Lee <flee@cygnus.com>
2782
2783 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2784
2785Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2786
2787 * Makefile.in (tmp-igen): Arrange for $zero to always be
2788 reset to zero after every instruction.
2789
2790Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2791
2792 * configure: Regenerated to track ../common/aclocal.m4 changes.
2793 * config.in: Ditto.
2794
2795Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2796
2797 * mips.igen (MSUB): Fix to work like MADD.
2798 * gencode.c (MSUB): Similarly.
2799
2800Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2801
2802 * configure: Regenerated to track ../common/aclocal.m4 changes.
2803
2804Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2805
2806 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2807
2808Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2809
2810 * sim-main.h (sim-fpu.h): Include.
2811
2812 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2813 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2814 using host independant sim_fpu module.
2815
2816Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2817
2818 * interp.c (signal_exception): Report internal errors with SIGABRT
2819 not SIGQUIT.
2820
2821 * sim-main.h (C0_CONFIG): New register.
2822 (signal.h): No longer include.
2823
2824 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2825
2826Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2827
2828 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2829
2830Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2831
2832 * mips.igen: Tag vr5000 instructions.
2833 (ANDI): Was missing mipsIV model, fix assembler syntax.
2834 (do_c_cond_fmt): New function.
2835 (C.cond.fmt): Handle mips I-III which do not support CC field
2836 separatly.
2837 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2838 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2839 in IV3.2 spec.
2840 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2841 vr5000 which saves LO in a GPR separatly.
72f4393d 2842
c906108c
SS		 2843 * configure.in (enable-sim-igen): For vr5000, select vr5000
2844 specific instructions.
2845 * configure: Re-generate.
72f4393d 2846
c906108c
SS		 2847Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2848
2849 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2850
2851 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2852 fmt_uninterpreted_64 bit cases to switch. Convert to
2853 fmt_formatted,
2854
2855 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2856
2857 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2858 as specified in IV3.2 spec.
2859 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2860
2861Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2862
2863 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2864 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2865 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2866 PENDING_FILL versions of instructions. Simplify.
2867 (X): New function.
2868 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2869 instructions.
2870 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2871 a signed value.
2872 (MTHI, MFHI): Disable code checking HI-LO.
72f4393d 2873
c906108c
SS		 2874 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2875 global.
2876 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2877
2878Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2879
2880 * gencode.c (build_mips16_operands): Replace IPC with cia.
2881
2882 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2883 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2884 IPC to `cia'.
2885 (UndefinedResult): Replace function with macro/function
2886 combination.
2887 (sim_engine_run): Don't save PC in IPC.
2888
2889 * sim-main.h (IPC): Delete.
2890
2891
2892 * interp.c (signal_exception, store_word, load_word,
2893 address_translation, load_memory, store_memory, cache_op,
2894 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2895 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2896 current instruction address - cia - argument.
2897 (sim_read, sim_write): Call address_translation directly.
2898 (sim_engine_run): Rename variable vaddr to cia.
2899 (signal_exception): Pass cia to sim_monitor
72f4393d 2900
c906108c
SS		 2901 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2902 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2903 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2904
2905 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2906 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2907 SIM_ASSERT.
72f4393d 2908
c906108c
SS		 2909 * interp.c (signal_exception): Pass restart address to
2910 sim_engine_restart.
2911
2912 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2913 idecode.o): Add dependency.
2914
2915 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2916 Delete definitions
2917 (DELAY_SLOT): Update NIA not PC with branch address.
2918 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2919
2920 * mips.igen: Use CIA not PC in branch calculations.
2921 (illegal): Call SignalException.
2922 (BEQ, ADDIU): Fix assembler.
2923
2924Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2925
2926 * m16.igen (JALX): Was missing.
2927
2928 * configure.in (enable-sim-igen): New configuration option.
2929 * configure: Re-generate.
72f4393d 2930
c906108c
SS		 2931 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2932
2933 * interp.c (load_memory, store_memory): Delete parameter RAW.
2934 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2935 bypassing {load,store}_memory.
2936
2937 * sim-main.h (ByteSwapMem): Delete definition.
2938
2939 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2940
2941 * interp.c (sim_do_command, sim_commands): Delete mips specific
2942 commands. Handled by module sim-options.
72f4393d 2943
c906108c
SS		 2944 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2945 (WITH_MODULO_MEMORY): Define.
2946
2947 * interp.c (sim_info): Delete code printing memory size.
2948
2949 * interp.c (mips_size): Nee sim_size, delete function.
2950 (power2): Delete.
2951 (monitor, monitor_base, monitor_size): Delete global variables.
2952 (sim_open, sim_close): Delete code creating monitor and other
2953 memory regions. Use sim-memopts module, via sim_do_commandf, to
2954 manage memory regions.
2955 (load_memory, store_memory): Use sim-core for memory model.
72f4393d 2956
c906108c
SS		 2957 * interp.c (address_translation): Delete all memory map code
2958 except line forcing 32 bit addresses.
2959
2960Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2961
2962 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2963 trace options.
2964
2965 * interp.c (logfh, logfile): Delete globals.
2966 (sim_open, sim_close): Delete code opening & closing log file.
2967 (mips_option_handler): Delete -l and -n options.
2968 (OPTION mips_options): Ditto.
2969
2970 * interp.c (OPTION mips_options): Rename option trace to dinero.
2971 (mips_option_handler): Update.
2972
2973Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2974
2975 * interp.c (fetch_str): New function.
2976 (sim_monitor): Rewrite using sim_read & sim_write.
2977 (sim_open): Check magic number.
2978 (sim_open): Write monitor vectors into memory using sim_write.
2979 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2980 (sim_read, sim_write): Simplify - transfer data one byte at a
2981 time.
2982 (load_memory, store_memory): Clarify meaning of parameter RAW.
2983
2984 * sim-main.h (isHOST): Defete definition.
2985 (isTARGET): Mark as depreciated.
2986 (address_translation): Delete parameter HOST.
2987
2988 * interp.c (address_translation): Delete parameter HOST.
2989
2990Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2991
72f4393d 2992 * mips.igen:
c906108c
SS		 2993
2994 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2995 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2996
2997Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2998
2999 * mips.igen: Add model filter field to records.
3000
3001Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
3002
3003 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
72f4393d 3004
c906108c
SS		 3005 interp.c (sim_engine_run): Do not compile function sim_engine_run
3006 when WITH_IGEN == 1.
3007
3008 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
3009 target architecture.
3010
3011 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
3012 igen. Replace with configuration variables sim_igen_flags /
3013 sim_m16_flags.
3014
3015 * m16.igen: New file. Copy mips16 insns here.
3016 * mips.igen: From here.
3017
3018Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
3019
3020 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
3021 to top.
3022 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
3023
3024Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
3025
3026 * gencode.c (build_instruction): Follow sim_write's lead in using
3027 BigEndianMem instead of !ByteSwapMem.
3028
3029Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
3030
3031 * configure.in (sim_gen): Dependent on target, select type of
3032 generator. Always select old style generator.
3033
3034 configure: Re-generate.
3035
3036 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
3037 targets.
3038 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
3039 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
3040 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
3041 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
3042 SIM_@sim_gen@_*, set by autoconf.
72f4393d 3043
c906108c
SS		 3044Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
3045
3046 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
3047
3048 * interp.c (ColdReset): Remove #ifdef HASFPU, check
3049 CURRENT_FLOATING_POINT instead.
3050
3051 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
3052 (address_translation): Raise exception InstructionFetch when
3053 translation fails and isINSTRUCTION.
72f4393d 3054
c906108c
SS		 3055 * interp.c (sim_open, sim_write, sim_monitor, store_word,
3056 sim_engine_run): Change type of of vaddr and paddr to
3057 address_word.
3058 (address_translation, prefetch, load_memory, store_memory,
3059 cache_op): Change type of vAddr and pAddr to address_word.
3060
3061 * gencode.c (build_instruction): Change type of vaddr and paddr to
3062 address_word.
3063
3064Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
3065
3066 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
3067 macro to obtain result of ALU op.
3068
3069Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
3070
3071 * interp.c (sim_info): Call profile_print.
3072
3073Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3074
3075 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
3076
3077 * sim-main.h (WITH_PROFILE): Do not define, defined in
3078 common/sim-config.h. Use sim-profile module.
3079 (simPROFILE): Delete defintion.
3080
3081 * interp.c (PROFILE): Delete definition.
3082 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
3083 (sim_close): Delete code writing profile histogram.
3084 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
3085 Delete.
3086 (sim_engine_run): Delete code profiling the PC.
3087
3088Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3089
3090 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
3091
3092 * interp.c (sim_monitor): Make register pointers of type
3093 unsigned_word*.
3094
3095 * sim-main.h: Make registers of type unsigned_word not
3096 signed_word.
3097
3098Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3099
3100 * interp.c (sync_operation): Rename from SyncOperation, make
3101 global, add SD argument.
3102 (prefetch): Rename from Prefetch, make global, add SD argument.
3103 (decode_coproc): Make global.
3104
3105 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
3106
3107 * gencode.c (build_instruction): Generate DecodeCoproc not
3108 decode_coproc calls.
3109
3110 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
3111 (SizeFGR): Move to sim-main.h
3112 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
3113 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
3114 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
3115 sim-main.h.
3116 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
3117 FP_RM_TOMINF, GETRM): Move to sim-main.h.
3118 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
3119 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
3120 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
3121 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
72f4393d 3122
c906108c
SS		 3123 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
3124 exception.
3125 (sim-alu.h): Include.
3126 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
3127 (sim_cia): Typedef to instruction_address.
72f4393d 3128
c906108c
SS		 3129Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
3130
3131 * Makefile.in (interp.o): Rename generated file engine.c to
3132 oengine.c.
72f4393d 3133
c906108c 3134 * interp.c: Update.
72f4393d 3135
c906108c
SS		 3136Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
3137
3138 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
72f4393d 3139
c906108c
SS		 3140Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3141
3142 * gencode.c (build_instruction): For "FPSQRT", output correct
3143 number of arguments to Recip.
72f4393d 3144
c906108c
SS		 3145Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
3146
3147 * Makefile.in (interp.o): Depends on sim-main.h
3148
3149 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
3150
3151 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
3152 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
3153 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
3154 STATE, DSSTATE): Define
3155 (GPR, FGRIDX, ..): Define.
3156
3157 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
3158 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
3159 (GPR, FGRIDX, ...): Delete macros.
72f4393d 3160
c906108c 3161 * interp.c: Update names to match defines from sim-main.h
72f4393d 3162
c906108c
SS		 3163Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
3164
3165 * interp.c (sim_monitor): Add SD argument.
3166 (sim_warning): Delete. Replace calls with calls to
3167 sim_io_eprintf.
3168 (sim_error): Delete. Replace calls with sim_io_error.
3169 (open_trace, writeout32, writeout16, getnum): Add SD argument.
3170 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
3171 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
3172 argument.
3173 (mips_size): Rename from sim_size. Add SD argument.
3174
3175 * interp.c (simulator): Delete global variable.
3176 (callback): Delete global variable.
3177 (mips_option_handler, sim_open, sim_write, sim_read,
3178 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
3179 sim_size,sim_monitor): Use sim_io_* not callback->*.
3180 (sim_open): ZALLOC simulator struct.
3181 (PROFILE): Do not define.
3182
3183Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3184
3185 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
3186 support.h with corresponding code.
3187
3188 * sim-main.h (word64, uword64), support.h: Move definition to
3189 sim-main.h.
3190 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
3191
3192 * support.h: Delete
3193 * Makefile.in: Update dependencies
3194 * interp.c: Do not include.
72f4393d 3195
c906108c
SS		 3196Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3197
3198 * interp.c (address_translation, load_memory, store_memory,
3199 cache_op): Rename to from AddressTranslation et.al., make global,
3200 add SD argument
72f4393d 3201
c906108c
SS		 3202 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
3203 CacheOp): Define.
72f4393d 3204
c906108c
SS		 3205 * interp.c (SignalException): Rename to signal_exception, make
3206 global.
3207
3208 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
72f4393d 3209
c906108c
SS		 3210 * sim-main.h (SignalException, SignalExceptionInterrupt,
3211 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
3212 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
3213 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
3214 Define.
72f4393d 3215
c906108c 3216 * interp.c, support.h: Use.
72f4393d 3217
c906108c
SS		 3218Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3219
3220 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
3221 to value_fpr / store_fpr. Add SD argument.
3222 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
3223 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
3224
3225 * sim-main.h (ValueFPR, StoreFPR): Define.
72f4393d 3226
c906108c
SS		 3227Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
3228
3229 * interp.c (sim_engine_run): Check consistency between configure
3230 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
3231 and HASFPU.
3232
3233 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
72f4393d 3234 (mips_fpu): Configure WITH_FLOATING_POINT.
c906108c
SS		 3235 (mips_endian): Configure WITH_TARGET_ENDIAN.
3236 * configure: Update.
3237
3238Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3239
3240 * configure: Regenerated to track ../common/aclocal.m4 changes.
3241
3242Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
3243
3244 * configure: Regenerated.
3245
3246Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
3247
3248 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
3249
3250Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3251
3252 * gencode.c (print_igen_insn_models): Assume certain architectures
3253 include all mips* instructions.
3254 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
3255 instruction.
3256
3257 * Makefile.in (tmp.igen): Add target. Generate igen input from
3258 gencode file.
3259
3260 * gencode.c (FEATURE_IGEN): Define.
3261 (main): Add --igen option. Generate output in igen format.
3262 (process_instructions): Format output according to igen option.
3263 (print_igen_insn_format): New function.
3264 (print_igen_insn_models): New function.
3265 (process_instructions): Only issue warnings and ignore
3266 instructions when no FEATURE_IGEN.
3267
3268Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3269
3270 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
3271 MIPS targets.
3272
3273Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3274
3275 * configure: Regenerated to track ../common/aclocal.m4 changes.
3276
3277Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
3278
3279 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
3280 SIM_RESERVED_BITS): Delete, moved to common.
3281 (SIM_EXTRA_CFLAGS): Update.
72f4393d 3282
c906108c
SS		 3283Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3284
3285 * configure.in: Configure non-strict memory alignment.
3286 * configure: Regenerated to track ../common/aclocal.m4 changes.
3287
3288Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
3289
3290 * configure: Regenerated to track ../common/aclocal.m4 changes.
3291
3292Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
3293
3294 * gencode.c (SDBBP,DERET): Added (3900) insns.
3295 (RFE): Turn on for 3900.
3296 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
3297 (dsstate): Made global.
3298 (SUBTARGET_R3900): Added.
3299 (CANCELDELAYSLOT): New.
3300 (SignalException): Ignore SystemCall rather than ignore and
3301 terminate. Add DebugBreakPoint handling.
3302 (decode_coproc): New insns RFE, DERET; and new registers Debug
3303 and DEPC protected by SUBTARGET_R3900.
3304 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
3305 bits explicitly.
3306 * Makefile.in,configure.in: Add mips subtarget option.
72f4393d 3307 * configure: Update.
c906108c
SS		 3308
3309Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
3310
3311 * gencode.c: Add r3900 (tx39).
72f4393d 3312
c906108c
SS		 3313
3314Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
3315
3316 * gencode.c (build_instruction): Don't need to subtract 4 for
3317 JALR, just 2.
3318
3319Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
3320
3321 * interp.c: Correct some HASFPU problems.
3322
3323Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
3324
3325 * configure: Regenerated to track ../common/aclocal.m4 changes.
3326
3327Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3328
3329 * interp.c (mips_options): Fix samples option short form, should
3330 be `x'.
3331
3332Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
3333
3334 * interp.c (sim_info): Enable info code. Was just returning.
3335
3336Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3337
3338 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
3339 MFC0.
3340
3341Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
3342
3343 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
3344 constants.
3345 (build_instruction): Ditto for LL.
3346
3347Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
3348
3349 * configure: Regenerated to track ../common/aclocal.m4 changes.
3350
3351Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3352
3353 * configure: Regenerated to track ../common/aclocal.m4 changes.
3354 * config.in: Ditto.
3355
3356Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
3357
3358 * interp.c (sim_open): Add call to sim_analyze_program, update
3359 call to sim_config.
3360
3361Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
3362
3363 * interp.c (sim_kill): Delete.
3364 (sim_create_inferior): Add ABFD argument. Set PC from same.
3365 (sim_load): Move code initializing trap handlers from here.
3366 (sim_open): To here.
3367 (sim_load): Delete, use sim-hload.c.
3368
3369 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
3370
3371Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3372
3373 * configure: Regenerated to track ../common/aclocal.m4 changes.
3374 * config.in: Ditto.
3375
3376Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3377
3378 * interp.c (sim_open): Add ABFD argument.
3379 (sim_load): Move call to sim_config from here.
3380 (sim_open): To here. Check return status.
3381
3382Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
72f4393d 3383
c906108c
SS		 3384 * gencode.c (build_instruction): Two arg MADD should
3385 not assign result to $0.
72f4393d 3386
c906108c
SS		 3387Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
3388
3389 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
3390 * sim/mips/configure.in: Regenerate.
3391
3392Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
3393
3394 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
3395 signed8, unsigned8 et.al. types.
3396
3397 * interp.c (SUB_REG_FETCH): Handle both little and big endian
3398 hosts when selecting subreg.
3399
3400Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
3401
3402 * interp.c (sim_engine_run): Reset the ZERO register to zero
3403 regardless of FEATURE_WARN_ZERO.
3404 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
3405
3406Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
3407
3408 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
3409 (SignalException): For BreakPoints ignore any mode bits and just
3410 save the PC.
3411 (SignalException): Always set the CAUSE register.
3412
3413Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
3414
3415 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
3416 exception has been taken.
3417
3418 * interp.c: Implement the ERET and mt/f sr instructions.
3419
3420Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
3421
3422 * interp.c (SignalException): Don't bother restarting an
3423 interrupt.
3424
3425Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3426
3427 * interp.c (SignalException): Really take an interrupt.
3428 (interrupt_event): Only deliver interrupts when enabled.
3429
3430Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
3431
3432 * interp.c (sim_info): Only print info when verbose.
3433 (sim_info) Use sim_io_printf for output.
72f4393d 3434
c906108c
SS		 3435Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3436
3437 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
3438 mips architectures.
3439
3440Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3441
3442 * interp.c (sim_do_command): Check for common commands if a
3443 simulator specific command fails.
3444
3445Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
3446
3447 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
3448 and simBE when DEBUG is defined.
3449
3450Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
3451
3452 * interp.c (interrupt_event): New function. Pass exception event
3453 onto exception handler.
3454
3455 * configure.in: Check for stdlib.h.
3456 * configure: Regenerate.
3457
3458 * gencode.c (build_instruction): Add UNUSED attribute to tempS
3459 variable declaration.
3460 (build_instruction): Initialize memval1.
3461 (build_instruction): Add UNUSED attribute to byte, bigend,
3462 reverse.
3463 (build_operands): Ditto.
3464
3465 * interp.c: Fix GCC warnings.
3466 (sim_get_quit_code): Delete.
3467
3468 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
3469 * Makefile.in: Ditto.
3470 * configure: Re-generate.
72f4393d 3471
c906108c
SS		 3472 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
3473
3474Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
3475
3476 * interp.c (mips_option_handler): New function parse argumes using
3477 sim-options.
3478 (myname): Replace with STATE_MY_NAME.
3479 (sim_open): Delete check for host endianness - performed by
3480 sim_config.
3481 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
3482 (sim_open): Move much of the initialization from here.
3483 (sim_load): To here. After the image has been loaded and
3484 endianness set.
3485 (sim_open): Move ColdReset from here.
3486 (sim_create_inferior): To here.
3487 (sim_open): Make FP check less dependant on host endianness.
3488
3489 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
3490 run.
3491 * interp.c (sim_set_callbacks): Delete.
3492
3493 * interp.c (membank, membank_base, membank_size): Replace with
3494 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
3495 (sim_open): Remove call to callback->init. gdb/run do this.
3496
3497 * interp.c: Update
3498
3499 * sim-main.h (SIM_HAVE_FLATMEM): Define.
3500
3501 * interp.c (big_endian_p): Delete, replaced by
3502 current_target_byte_order.
3503
3504Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3505
3506 * interp.c (host_read_long, host_read_word, host_swap_word,
3507 host_swap_long): Delete. Using common sim-endian.
3508 (sim_fetch_register, sim_store_register): Use H2T.
3509 (pipeline_ticks): Delete. Handled by sim-events.
3510 (sim_info): Update.
3511 (sim_engine_run): Update.
3512
3513Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
3514
3515 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
3516 reason from here.
3517 (SignalException): To here. Signal using sim_engine_halt.
3518 (sim_stop_reason): Delete, moved to common.
72f4393d 3519
c906108c
SS		 3520Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
3521
3522 * interp.c (sim_open): Add callback argument.
3523 (sim_set_callbacks): Delete SIM_DESC argument.
3524 (sim_size): Ditto.
3525
3526Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3527
3528 * Makefile.in (SIM_OBJS): Add common modules.
3529
3530 * interp.c (sim_set_callbacks): Also set SD callback.
3531 (set_endianness, xfer_*, swap_*): Delete.
3532 (host_read_word, host_read_long, host_swap_word, host_swap_long):
3533 Change to functions using sim-endian macros.
3534 (control_c, sim_stop): Delete, use common version.
3535 (simulate): Convert into.
3536 (sim_engine_run): This function.
3537 (sim_resume): Delete.
72f4393d 3538
c906108c
SS		 3539 * interp.c (simulation): New variable - the simulator object.
3540 (sim_kind): Delete global - merged into simulation.
3541 (sim_load): Cleanup. Move PC assignment from here.
3542 (sim_create_inferior): To here.
3543
3544 * sim-main.h: New file.
3545 * interp.c (sim-main.h): Include.
72f4393d 3546
c906108c
SS		 3547Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
3548
3549 * configure: Regenerated to track ../common/aclocal.m4 changes.
3550
3551Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
3552
3553 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
3554
3555Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
3556
72f4393d
L		 3557 * gencode.c (build_instruction): DIV instructions: check
3558 for division by zero and integer overflow before using
c906108c
SS		 3559 host's division operation.
3560
3561Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
3562
3563 * Makefile.in (SIM_OBJS): Add sim-load.o.
3564 * interp.c: #include bfd.h.
3565 (target_byte_order): Delete.
3566 (sim_kind, myname, big_endian_p): New static locals.
3567 (sim_open): Set sim_kind, myname. Move call to set_endianness to
3568 after argument parsing. Recognize -E arg, set endianness accordingly.
3569 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
3570 load file into simulator. Set PC from bfd.
3571 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
3572 (set_endianness): Use big_endian_p instead of target_byte_order.
3573
3574Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
3575
3576 * interp.c (sim_size): Delete prototype - conflicts with
3577 definition in remote-sim.h. Correct definition.
3578
3579Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3580
3581 * configure: Regenerated to track ../common/aclocal.m4 changes.
3582 * config.in: Ditto.
3583
3584Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
3585
3586 * interp.c (sim_open): New arg `kind'.
3587
3588 * configure: Regenerated to track ../common/aclocal.m4 changes.
3589
3590Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3591
3592 * configure: Regenerated to track ../common/aclocal.m4 changes.
3593
3594Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
3595
3596 * interp.c (sim_open): Set optind to 0 before calling getopt.
3597
3598Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3599
3600 * configure: Regenerated to track ../common/aclocal.m4 changes.
3601
3602Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
3603
3604 * interp.c : Replace uses of pr_addr with pr_uword64
3605 where the bit length is always 64 independent of SIM_ADDR.
3606 (pr_uword64) : added.
3607
3608Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3609
3610 * configure: Re-generate.
3611
3612Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
3613
3614 * configure: Regenerate to track ../common/aclocal.m4 changes.
3615
3616Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
3617
3618 * interp.c (sim_open): New SIM_DESC result. Argument is now
3619 in argv form.
3620 (other sim_*): New SIM_DESC argument.
3621
3622Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
3623
3624 * interp.c: Fix printing of addresses for non-64-bit targets.
3625 (pr_addr): Add function to print address based on size.
3626
3627Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
3628
3629 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
3630
3631Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
3632
3633 * gencode.c (build_mips16_operands): Correct computation of base
3634 address for extended PC relative instruction.
3635
3636Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
3637
3638 * interp.c (mips16_entry): Add support for floating point cases.
3639 (SignalException): Pass floating point cases to mips16_entry.
3640 (ValueFPR): Don't restrict fmt_single and fmt_word to even
3641 registers.
3642 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
3643 or fmt_word.
3644 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
3645 and then set the state to fmt_uninterpreted.
3646 (COP_SW): Temporarily set the state to fmt_word while calling
3647 ValueFPR.
3648
3649Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
3650
3651 * gencode.c (build_instruction): The high order may be set in the
3652 comparison flags at any ISA level, not just ISA 4.
3653
3654Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
3655
3656 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
3657 COMMON_{PRE,POST}_CONFIG_FRAG instead.
3658 * configure.in: sinclude ../common/aclocal.m4.
3659 * configure: Regenerated.
3660
3661Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
3662
3663 * configure: Rebuild after change to aclocal.m4.
3664
3665Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
3666
3667 * configure configure.in Makefile.in: Update to new configure
3668 scheme which is more compatible with WinGDB builds.
3669 * configure.in: Improve comment on how to run autoconf.
3670 * configure: Re-run autoconf to get new ../common/aclocal.m4.
3671 * Makefile.in: Use autoconf substitution to install common
3672 makefile fragment.
3673
3674Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
3675
3676 * gencode.c (build_instruction): Use BigEndianCPU instead of
3677 ByteSwapMem.
3678
3679Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
3680
3681 * interp.c (sim_monitor): Make output to stdout visible in
3682 wingdb's I/O log window.
3683
3684Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
3685
3686 * support.h: Undo previous change to SIGTRAP
3687 and SIGQUIT values.
3688
3689Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
3690
3691 * interp.c (store_word, load_word): New static functions.
3692 (mips16_entry): New static function.
3693 (SignalException): Look for mips16 entry and exit instructions.
3694 (simulate): Use the correct index when setting fpr_state after
3695 doing a pending move.
3696
3697Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
3698
3699 * interp.c: Fix byte-swapping code throughout to work on
3700 both little- and big-endian hosts.
3701
3702Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
3703
3704 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3705 with gdb/config/i386/xm-windows.h.
3706
3707Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
3708
3709 * gencode.c (build_instruction): Work around MSVC++ code gen bug
3710 that messes up arithmetic shifts.
3711
3712Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
3713
3714 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
3715 SIGTRAP and SIGQUIT for _WIN32.
3716
3717Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3718
3719 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3720 force a 64 bit multiplication.
3721 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3722 destination register is 0, since that is the default mips16 nop
3723 instruction.
3724
3725Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3726
3727 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3728 (build_endian_shift): Don't check proc64.
3729 (build_instruction): Always set memval to uword64. Cast op2 to
3730 uword64 when shifting it left in memory instructions. Always use
3731 the same code for stores--don't special case proc64.
3732
3733 * gencode.c (build_mips16_operands): Fix base PC value for PC
3734 relative operands.
3735 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3736 jal instruction.
3737 * interp.c (simJALDELAYSLOT): Define.
3738 (JALDELAYSLOT): Define.
3739 (INDELAYSLOT, INJALDELAYSLOT): Define.
3740 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3741
3742Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3743
3744 * interp.c (sim_open): add flush_cache as a PMON routine
3745 (sim_monitor): handle flush_cache by ignoring it
3746
3747Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3748
3749 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3750 BigEndianMem.
3751 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3752 (BigEndianMem): Rename to ByteSwapMem and change sense.
3753 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3754 BigEndianMem references to !ByteSwapMem.
3755 (set_endianness): New function, with prototype.
3756 (sim_open): Call set_endianness.
3757 (sim_info): Use simBE instead of BigEndianMem.
3758 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3759 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3760 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3761 ifdefs, keeping the prototype declaration.
3762 (swap_word): Rewrite correctly.
3763 (ColdReset): Delete references to CONFIG. Delete endianness related
3764 code; moved to set_endianness.
72f4393d 3765
c906108c
SS		 3766Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3767
3768 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3769 * interp.c (CHECKHILO): Define away.
3770 (simSIGINT): New macro.
3771 (membank_size): Increase from 1MB to 2MB.
3772 (control_c): New function.
3773 (sim_resume): Rename parameter signal to signal_number. Add local
3774 variable prev. Call signal before and after simulate.
3775 (sim_stop_reason): Add simSIGINT support.
3776 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3777 functions always.
3778 (sim_warning): Delete call to SignalException. Do call printf_filtered
3779 if logfh is NULL.
3780 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3781 a call to sim_warning.
3782
3783Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3784
3785 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3786 16 bit instructions.
3787
3788Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3789
3790 Add support for mips16 (16 bit MIPS implementation):
3791 * gencode.c (inst_type): Add mips16 instruction encoding types.
3792 (GETDATASIZEINSN): Define.
3793 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3794 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3795 mtlo.
3796 (MIPS16_DECODE): New table, for mips16 instructions.
3797 (bitmap_val): New static function.
3798 (struct mips16_op): Define.
3799 (mips16_op_table): New table, for mips16 operands.
3800 (build_mips16_operands): New static function.
3801 (process_instructions): If PC is odd, decode a mips16
3802 instruction. Break out instruction handling into new
3803 build_instruction function.
3804 (build_instruction): New static function, broken out of
3805 process_instructions. Check modifiers rather than flags for SHIFT
3806 bit count and m[ft]{hi,lo} direction.
3807 (usage): Pass program name to fprintf.
3808 (main): Remove unused variable this_option_optind. Change
3809 ``*loptarg++'' to ``loptarg++''.
3810 (my_strtoul): Parenthesize && within ||.
3811 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3812 (simulate): If PC is odd, fetch a 16 bit instruction, and
3813 increment PC by 2 rather than 4.
3814 * configure.in: Add case for mips16*-*-*.
3815 * configure: Rebuild.
3816
3817Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3818
3819 * interp.c: Allow -t to enable tracing in standalone simulator.
3820 Fix garbage output in trace file and error messages.
3821
3822Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3823
3824 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3825 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3826 * configure.in: Simplify using macros in ../common/aclocal.m4.
3827 * configure: Regenerated.
3828 * tconfig.in: New file.
3829
3830Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3831
3832 * interp.c: Fix bugs in 64-bit port.
3833 Use ansi function declarations for msvc compiler.
3834 Initialize and test file pointer in trace code.
3835 Prevent duplicate definition of LAST_EMED_REGNUM.
3836
3837Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3838
3839 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3840
3841Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3842
3843 * interp.c (SignalException): Check for explicit terminating
3844 breakpoint value.
3845 * gencode.c: Pass instruction value through SignalException()
3846 calls for Trap, Breakpoint and Syscall.
3847
3848Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3849
3850 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3851 only used on those hosts that provide it.
3852 * configure.in: Add sqrt() to list of functions to be checked for.
3853 * config.in: Re-generated.
3854 * configure: Re-generated.
3855
3856Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3857
3858 * gencode.c (process_instructions): Call build_endian_shift when
3859 expanding STORE RIGHT, to fix swr.
3860 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3861 clear the high bits.
3862 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3863 Fix float to int conversions to produce signed values.
3864
3865Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3866
3867 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3868 (process_instructions): Correct handling of nor instruction.
3869 Correct shift count for 32 bit shift instructions. Correct sign
3870 extension for arithmetic shifts to not shift the number of bits in
3871 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3872 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3873 Fix madd.
3874 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3875 It's OK to have a mult follow a mult. What's not OK is to have a
3876 mult follow an mfhi.
3877 (Convert): Comment out incorrect rounding code.
3878
3879Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3880
3881 * interp.c (sim_monitor): Improved monitor printf
3882 simulation. Tidied up simulator warnings, and added "--log" option
3883 for directing warning message output.
3884 * gencode.c: Use sim_warning() rather than WARNING macro.
3885
3886Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3887
3888 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3889 getopt1.o, rather than on gencode.c. Link objects together.
3890 Don't link against -liberty.
3891 (gencode.o, getopt.o, getopt1.o): New targets.
3892 * gencode.c: Include <ctype.h> and "ansidecl.h".
3893 (AND): Undefine after including "ansidecl.h".
3894 (ULONG_MAX): Define if not defined.
3895 (OP_*): Don't define macros; now defined in opcode/mips.h.
3896 (main): Call my_strtoul rather than strtoul.
3897 (my_strtoul): New static function.
3898
3899Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3900
3901 * gencode.c (process_instructions): Generate word64 and uword64
3902 instead of `long long' and `unsigned long long' data types.
3903 * interp.c: #include sysdep.h to get signals, and define default
3904 for SIGBUS.
3905 * (Convert): Work around for Visual-C++ compiler bug with type
3906 conversion.
3907 * support.h: Make things compile under Visual-C++ by using
3908 __int64 instead of `long long'. Change many refs to long long
3909 into word64/uword64 typedefs.
3910
3911Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3912
72f4393d
L		 3913 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3914 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3915 (docdir): Removed.
3916 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3917 (AC_PROG_INSTALL): Added.
c906108c 3918 (AC_PROG_CC): Moved to before configure.host call.
72f4393d
L		 3919 * configure: Rebuilt.
3920
c906108c
SS		 3921Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3922
3923 * configure.in: Define @SIMCONF@ depending on mips target.
3924 * configure: Rebuild.
3925 * Makefile.in (run): Add @SIMCONF@ to control simulator
3926 construction.
3927 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3928 * interp.c: Remove some debugging, provide more detailed error
3929 messages, update memory accesses to use LOADDRMASK.
72f4393d 3930
c906108c
SS		 3931Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3932
3933 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3934 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3935 stamp-h.
3936 * configure: Rebuild.
3937 * config.in: New file, generated by autoheader.
3938 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3939 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3940 HAVE_ANINT and HAVE_AINT, as appropriate.
3941 * Makefile.in (run): Use @LIBS@ rather than -lm.
3942 (interp.o): Depend upon config.h.
3943 (Makefile): Just rebuild Makefile.
3944 (clean): Remove stamp-h.
3945 (mostlyclean): Make the same as clean, not as distclean.
3946 (config.h, stamp-h): New targets.
3947
3948Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3949
3950 * interp.c (ColdReset): Fix boolean test. Make all simulator
3951 globals static.
3952
3953Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3954
3955 * interp.c (xfer_direct_word, xfer_direct_long,
3956 swap_direct_word, swap_direct_long, xfer_big_word,
3957 xfer_big_long, xfer_little_word, xfer_little_long,
3958 swap_word,swap_long): Added.
3959 * interp.c (ColdReset): Provide function indirection to
3960 host<->simulated_target transfer routines.
3961 * interp.c (sim_store_register, sim_fetch_register): Updated to
3962 make use of indirected transfer routines.
3963
3964Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3965
3966 * gencode.c (process_instructions): Ensure FP ABS instruction
3967 recognised.
3968 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3969 system call support.
3970
3971Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3972
3973 * interp.c (sim_do_command): Complain if callback structure not
3974 initialised.
3975
3976Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3977
3978 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3979 support for Sun hosts.
3980 * Makefile.in (gencode): Ensure the host compiler and libraries
3981 used for cross-hosted build.
3982
3983Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3984
3985 * interp.c, gencode.c: Some more (TODO) tidying.
3986
3987Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3988
3989 * gencode.c, interp.c: Replaced explicit long long references with
3990 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3991 * support.h (SET64LO, SET64HI): Macros added.
3992
3993Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3994
3995 * configure: Regenerate with autoconf 2.7.
3996
3997Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3998
3999 * interp.c (LoadMemory): Enclose text following #endif in /* */.
4000 * support.h: Remove superfluous "1" from #if.
4001 * support.h (CHECKSIM): Remove stray 'a' at end of line.
4002
4003Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
4004
4005 * interp.c (StoreFPR): Control UndefinedResult() call on
4006 WARN_RESULT manifest.
4007
4008Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
4009
4010 * gencode.c: Tidied instruction decoding, and added FP instruction
4011 support.
4012
4013 * interp.c: Added dineroIII, and BSD profiling support. Also
4014 run-time FP handling.
4015
4016Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
4017
4018 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
4019 gencode.c, interp.c, support.h: created.
GDB Binutils - Deliverables
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