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sim/mips/cp1.c: Include <stdlib.h> for abort() declaration
[deliverable/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
ad9675dd
PK		 12020-12-14 Pavel I. Kryukov <kryukov@frtk.ru> (tiny change)
2
3 * cp1.c: Include <stdlib.h>.
4
f693213d
SM		 52020-07-29 Simon Marchi <simon.marchi@efficios.com>
6
7 * configure: Re-generate.
8
5c887dd5
JB		 92017-09-06 John Baldwin <jhb@FreeBSD.org>
10
11 * configure: Regenerate.
12
91588b3a
MF		 132016-11-11 Mike Frysinger <vapier@gentoo.org>
14
6cb2202b 15 PR sim/20808
91588b3a
MF		 16 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Define CPU to cpu
17 and SD to sd.
18
e04659e8
MF		 192016-11-11 Mike Frysinger <vapier@gentoo.org>
20
6cb2202b 21 PR sim/20809
e04659e8
MF		 22 * mips.igen (check_u64): Enable for `r3900'.
23
1554f758
MF		 242016-02-05 Mike Frysinger <vapier@gentoo.org>
25
26 * configure.ac (sim_engine_run): Change sd->base.prog_bfd to
27 STATE_PROG_BFD (sd).
28 * configure: Regenerate.
29
3d304f48
AB		 302016-01-18 Andrew Bennett <andrew.bennett@imgtec.com>
31 Maciej W. Rozycki <macro@imgtec.com>
32
33 PR sim/19441
34 * micromips.igen (delayslot_micromips): Enable for `micromips32',
35 `micromips64' and `micromipsdsp' only.
36 (process_isa_mode): Enable for `micromips32' and `micromips64' only.
37 (do_micromips_jalr, do_micromips_jal): Likewise.
38 (compute_movep_src_reg): Likewise.
39 (compute_andi16_imm): Likewise.
40 (convert_fmt_micromips): Likewise.
41 (convert_fmt_micromips_cvt_d): Likewise.
42 (convert_fmt_micromips_cvt_s): Likewise.
43 (FMT_MICROMIPS): Likewise.
44 (FMT_MICROMIPS_CVT_D): Likewise.
45 (FMT_MICROMIPS_CVT_S): Likewise.
46
b36d953b
MF		 472016-01-12 Mike Frysinger <vapier@gentoo.org>
48
49 * interp.c: Include elf-bfd.h.
50 (sim_create_inferior): Truncate pc to 32-bits when EI_CLASS is
51 ELFCLASS32.
52
ce39bd38
MF		 532016-01-10 Mike Frysinger <vapier@gentoo.org>
54
55 * config.in, configure: Regenerate.
56
99d8e879
MF		 572016-01-10 Mike Frysinger <vapier@gentoo.org>
58
59 * configure: Regenerate.
60
35656e95
MF		 612016-01-10 Mike Frysinger <vapier@gentoo.org>
62
63 * configure: Regenerate.
64
16f7876d
MF		 652016-01-10 Mike Frysinger <vapier@gentoo.org>
66
67 * configure: Regenerate.
68
e19418e0
MF		 692016-01-10 Mike Frysinger <vapier@gentoo.org>
70
71 * configure: Regenerate.
72
6d90347b
MF		 732016-01-10 Mike Frysinger <vapier@gentoo.org>
74
75 * configure.ac (SIM_AC_OPTION_SMP): Delete call.
76 * configure: Regenerate.
77
347fe5bb
MF		 782016-01-10 Mike Frysinger <vapier@gentoo.org>
79
80 * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
81 * configure: Regenerate.
82
22be3fbe
MF		 832016-01-10 Mike Frysinger <vapier@gentoo.org>
84
85 * configure: Regenerate.
86
0dc73ef7
MF		 872016-01-10 Mike Frysinger <vapier@gentoo.org>
88
89 * configure: Regenerate.
90
936df756
MF		 912016-01-09 Mike Frysinger <vapier@gentoo.org>
92
93 * config.in, configure: Regenerate.
94
2e3d4f4d
MF		 952016-01-06 Mike Frysinger <vapier@gentoo.org>
96
97 * interp.c (sim_open): Mark argv const.
98 (sim_create_inferior): Mark argv and env const.
99
9bbf6f91
MF		 1002016-01-04 Mike Frysinger <vapier@gentoo.org>
101
102 * configure: Regenerate.
103
77cf2ef5
MF		 1042016-01-03 Mike Frysinger <vapier@gentoo.org>
105
106 * interp.c (sim_open): Update sim_parse_args comment.
107
0cb8d851
MF		 1082016-01-03 Mike Frysinger <vapier@gentoo.org>
109
110 * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
111 * configure: Regenerate.
112
1ac72f06
MF		 1132016-01-02 Mike Frysinger <vapier@gentoo.org>
114
115 * configure.ac (mips_endian): Change LITTLE_ENDIAN to LITTLE.
116 (default_endian): Likewise. Change BIG_ENDIAN to BIG.
117 * configure: Regenerate.
118 * sim-main.h (BigEndianMem): Change BIG_ENDIAN to BFD_ENDIAN_BIG.
119
d47f5b30
MF		 1202016-01-02 Mike Frysinger <vapier@gentoo.org>
121
122 * dv-tx3904cpu.c (CPU, SD): Delete.
123
e1211e55
MF		 1242015-12-30 Mike Frysinger <vapier@gentoo.org>
125
126 * wrapper.c (mips_reg_store, mips_reg_fetch): Define.
127 (sim_open): Call CPU_REG_FETCH/CPU_REG_STORE.
128 (sim_store_register): Rename to ...
129 (mips_reg_store): ... this. Delete local cpu var.
130 Update sim_io_eprintf calls.
131 (sim_fetch_register): Rename to ...
132 (mips_reg_fetch): ... this. Delete local cpu var.
133 Update sim_io_eprintf calls.
134
5e744ef8
MF		 1352015-12-27 Mike Frysinger <vapier@gentoo.org>
136
137 * Makefile.in (SIM_OBJS): Delete sim-hload.o.
138
1b393626
MF		 1392015-12-26 Mike Frysinger <vapier@gentoo.org>
140
141 * config.in, configure: Regenerate.
142
26f8bf63
MF		 1432015-12-26 Mike Frysinger <vapier@gentoo.org>
144
145 * interp.c (sim_write, sim_read): Delete.
146 (store_word): Delete call to AddressTranslation and set paddr=vaddr.
147 (load_word): Likewise.
148 * micromips.igen (cache): Likewise.
149 * mips.igen (do_ll, do_lld, do_sc, do_scd, do_suxc1_32, do_swc1,
150 do_swxc1, cache, do_load, do_load_left, do_load_right, do_store,
151 do_store_left, do_store_right, do_load_double, do_store_double):
152 Likewise.
153 (do_pref): Delete call to AddressTranslation and stub out Prefetch.
154 (do_prefx): Likewise.
155 * sim-main.c (address_translation, prefetch): Delete.
156 (ifetch32, ifetch16): Delete call to AddressTranslation and set
157 paddr=vaddr.
158 * sim-main.h (Uncached, CachedNoncoherent, CachedCoherent, Cached,
159 address_translation, AddressTranslation, prefetch, Prefetch): Delete.
160 (LoadMemory, StoreMemory): Delete CCA arg.
161
ef04e371
MF		 1622015-12-24 Mike Frysinger <vapier@gentoo.org>
163
164 * configure.ac (SIM_SUBTARGET): Drop -DTARGET_TX3904=1.
165 * configure: Regenerated.
166
cb379ede
MF		 1672015-12-24 Mike Frysinger <vapier@gentoo.org>
168
169 * sim-main.h (SIM_QUIET_NAN_NEGATED): Move from tconfig.h.
170 * tconfig.h: Delete.
171
26936211
MF		 1722015-12-24 Mike Frysinger <vapier@gentoo.org>
173
174 * tconfig.h (SIM_HANDLES_LMA): Delete.
175
84e8e361
MF		 1762015-12-24 Mike Frysinger <vapier@gentoo.org>
177
178 * sim-main.h (WITH_WATCHPOINTS): Delete.
179
3cabaf66
MF		 1802015-12-24 Mike Frysinger <vapier@gentoo.org>
181
182 * interp.c [SIM_HAVE_FLATMEM] (sim_open): Delete flatmem code.
183
8abe6c66
MF		 1842015-12-24 Mike Frysinger <vapier@gentoo.org>
185
186 * tconfig.h (SIM_HAVE_SIMCACHE): Delete.
187
1d19cae7
DV		 1882015-12-15 Dominik Vogt <vogt@linux.vnet.ibm.com>
189
190 * micromips.igen (process_isa_mode): Fix left shift of negative
191 value.
192
cdf850e9
MF		 1932015-11-17 Mike Frysinger <vapier@gentoo.org>
194
195 * sim-main.h (WITH_MODULO_MEMORY): Delete.
196
797eee42
MF		 1972015-11-15 Mike Frysinger <vapier@gentoo.org>
198
199 * Makefile.in (SIM_OBJS): Delete sim-reason.o and sim-stop.o.
200
6e4f085c
MF		 2012015-11-14 Mike Frysinger <vapier@gentoo.org>
202
203 * interp.c (sim_close): Rename to ...
204 (mips_sim_close): ... this. Delete calls to sim_module_uninstall and
205 sim_io_shutdown.
206 * sim-main.h (mips_sim_close): Declare.
207 (SIM_CLOSE_HOOK): Define.
208
8e394ffc
AB		 2092015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
210 Ali Lown <ali.lown@imgtec.com>
211
212 * Makefile.in (tmp-micromips): New rule.
213 (tmp-mach-multi): Add support for micromips.
214 * configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
215 that works for both mips64 and micromips64.
216 (mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
217 micromips32.
218 Add build support for micromips.
219 * dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
220 do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
221 do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
222 do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
223 do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
224 do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
225 do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
226 do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
227 Refactored instruction code to use these functions.
228 * dsp2.igen: Refactored instruction code to use the new functions.
229 * interp.c (decode_coproc): Refactored to work with any instruction
230 encoding.
231 (isa_mode): New variable
232 (RSVD_INSTRUCTION): Changed to 0x00000039.
233 * m16.igen (BREAK16): Refactored instruction to use do_break16.
234 (JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
235 * micromips.dc: New file.
236 * micromips.igen: New file.
237 * micromips16.dc: New file.
238 * micromipsdsp.igen: New file.
239 * micromipsrun.c: New file.
240 * mips.igen (do_swc1): Changed to work with any instruction encoding.
241 (do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
242 do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo,
243 do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu,
244 do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu,
245 do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub,
246 do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo,
247 do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc,
248 do_scd, do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu,
249 do_tgeu, do_tlt do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt,
250 do_add_fmt, do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1,
251 do_cvt_d_fmt, do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl,
252 do_cvt_s_pu, do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt,
253 do_luxc1_32, do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b,
254 do_mov_fmt, do_movtf, do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt,
255 do_mtc1b, do_mul_fmt, do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps,
256 do_plu_ps, do_pul_ps, do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt,
257 do_prefx, do_sdc1, do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt,
258 do_swc1, do_swxc1, do_trunc_fmt): New functions, refactored from existing
259 instructions.
260 Refactored instruction code to use these functions.
261 (RSVD): Changed to use new reserved instruction.
262 (loadstore_ea, not_word_value, unpredictable, check_mt_hilo,
263 check_mf_hilo, check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32,
264 do_sdc1, do_suxc1_32, check_fmt_p, check_fpu, do_load_double,
265 do_store_double): Added micromips32 and micromips64 models.
266 Added include for micromips.igen and micromipsdsp.igen
267 Add micromips32 and micromips64 models.
268 (DecodeCoproc): Updated to use new macro definition.
269 * mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
270 do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
271 do_seb, do_seh do_rdhwr, do_wsbh): New functions.
272 Refactored instruction code to use these functions.
273 * sim-main.h (CP0_operation): New enum.
274 (DecodeCoproc): Updated macro.
275 (IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
276 MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16,
277 MICROMIPS_DELAYSLOT_SIZE_32, ISA_MODE_MIPS32 and
278 ISA_MODE_MICROMIPS): New defines.
279 (sim_state): Add isa_mode field.
280
8d0978fb
MF		 2812015-06-23 Mike Frysinger <vapier@gentoo.org>
282
283 * configure: Regenerate.
284
306f4178
MF		 2852015-06-12 Mike Frysinger <vapier@gentoo.org>
286
287 * configure.ac: Change configure.in to configure.ac.
288 * configure: Regenerate.
289
a3487082
MF		 2902015-06-12 Mike Frysinger <vapier@gentoo.org>
291
292 * configure: Regenerate.
293
29bc024d
MF		 2942015-06-12 Mike Frysinger <vapier@gentoo.org>
295
296 * interp.c [TRACE]: Delete.
297 (TRACE): Change to WITH_TRACE_ANY_P.
298 [!WITH_TRACE_ANY_P] (open_trace): Define.
299 (mips_option_handler, open_trace, sim_close, dotrace):
300 Change defined(TRACE) to WITH_TRACE_ANY_P.
301 (sim_open): Delete TRACE ifdef check.
302 * sim-main.c (load_memory): Delete TRACE ifdef check.
303 (store_memory): Likewise.
304 * sim-main.h [WITH_TRACE_ANY_P] (dotrace, tracefh): Protect decls.
305 [!WITH_TRACE_ANY_P] (dotrace): Define.
306
3ebe2863
MF		 3072015-04-18 Mike Frysinger <vapier@gentoo.org>
308
309 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESTART_HOOK): Delete
310 comments.
311
20bca71d
MF		 3122015-04-18 Mike Frysinger <vapier@gentoo.org>
313
314 * sim-main.h (SIM_CPU): Delete.
315
7e83aa92
MF		 3162015-04-18 Mike Frysinger <vapier@gentoo.org>
317
318 * sim-main.h (sim_cia): Delete.
319
034685f9
MF		 3202015-04-17 Mike Frysinger <vapier@gentoo.org>
321
322 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Change CIA_GET to
323 PU_PC_GET.
324 * interp.c (interrupt_event): Change CIA_GET to CPU_PC_GET.
325 (sim_create_inferior): Change CIA_SET to CPU_PC_SET.
326 * m16run.c (sim_engine_run): Change CIA_GET to CPU_PC_GET and
327 CIA_SET to CPU_PC_SET.
328 * sim-main.h (CIA_GET, CIA_SET): Delete.
329
78e9aa70
MF		 3302015-04-15 Mike Frysinger <vapier@gentoo.org>
331
332 * Makefile.in (SIM_OBJS): Delete sim-cpu.o.
333 * sim-main.h (STATE_CPU): Delete.
334
bf12d44e
MF		 3352015-04-13 Mike Frysinger <vapier@gentoo.org>
336
337 * configure: Regenerate.
338
7bebb329
MF		 3392015-04-13 Mike Frysinger <vapier@gentoo.org>
340
341 * Makefile.in (SIM_OBJS): Add sim-cpu.o.
342 * interp.c (mips_pc_get, mips_pc_set): New functions.
343 (sim_open): Declare new local var i. Call sim_cpu_alloc_all.
344 Call CPU_PC_FETCH & CPU_PC_STORE for all cpus.
345 (sim_pc_get): Delete.
346 * sim-main.h (SIM_CPU): Define.
347 (struct sim_state): Change cpu to an array of pointers.
348 (STATE_CPU): Drop &.
349
8ac57fbd
MF		 3502015-04-13 Mike Frysinger <vapier@gentoo.org>
351
352 * interp.c (mips_option_handler, open_trace, sim_close,
353 sim_write, sim_read, sim_store_register, sim_fetch_register,
354 sim_create_inferior, pr_addr, pr_uword64): Convert old style
355 prototypes.
356 (sim_open): Convert old style prototype. Change casts with
357 sim_write to unsigned char *.
358 (fetch_str): Change null to unsigned char, and change cast to
359 unsigned char *.
360 (sim_monitor): Change c & ch to unsigned char. Change cast to
361 unsigned char *.
362
e787f858
MF		 3632015-04-12 Mike Frysinger <vapier@gentoo.org>
364
365 * Makefile.in (SIM_OBJS): Move interp.o to the start of the list.
366
122bbfb5
MF		 3672015-04-06 Mike Frysinger <vapier@gentoo.org>
368
369 * Makefile.in (SIM_OBJS): Delete sim-engine.o.
370
0fe84f3f
MF		 3712015-04-01 Mike Frysinger <vapier@gentoo.org>
372
373 * tconfig.h (SIM_HAVE_PROFILE): Delete.
374
aadc9410
MF		 3752015-03-31 Mike Frysinger <vapier@gentoo.org>
376
377 * config.in, configure: Regenerate.
378
05f53ed6
MF		 3792015-03-24 Mike Frysinger <vapier@gentoo.org>
380
381 * interp.c (sim_pc_get): New function.
382
c0931f26
MF		 3832015-03-24 Mike Frysinger <vapier@gentoo.org>
384
385 * sim-main.h (SIM_HAVE_BIENDIAN): Delete.
386 * tconfig.h (SIM_HAVE_BIENDIAN): Delete.
387
30452bbe
MF		 3882015-03-24 Mike Frysinger <vapier@gentoo.org>
389
390 * configure: Regenerate.
391
64dd13df
MF		 3922015-03-23 Mike Frysinger <vapier@gentoo.org>
393
394 * configure: Regenerate.
395
49cd1634
MF		 3962015-03-23 Mike Frysinger <vapier@gentoo.org>
397
398 * configure: Regenerate.
399 * configure.ac (mips_extra_objs): Delete.
400 * Makefile.in (MIPS_EXTRA_OBJS): Delete.
401 (SIM_OBJS): Delete MIPS_EXTRA_OBJS.
402
3649cb06
MF		 4032015-03-23 Mike Frysinger <vapier@gentoo.org>
404
405 * configure: Regenerate.
406 * configure.ac: Delete sim_hw checks for dv-sockser.
407
ae7d0cac
MF		 4082015-03-16 Mike Frysinger <vapier@gentoo.org>
409
410 * config.in, configure: Regenerate.
411 * tconfig.in: Rename file ...
412 * tconfig.h: ... here.
413
8406bb59
MF		 4142015-03-15 Mike Frysinger <vapier@gentoo.org>
415
416 * tconfig.in: Delete includes.
417 [HAVE_DV_SOCKSER]: Delete.
418
465fb143
MF		 4192015-03-14 Mike Frysinger <vapier@gentoo.org>
420
421 * Makefile.in (SIM_RUN_OBJS): Delete.
422
5cddc23a
MF		 4232015-03-14 Mike Frysinger <vapier@gentoo.org>
424
425 * configure.ac (AC_CHECK_HEADERS): Delete.
426 * aclocal.m4, configure: Regenerate.
427
2974be62
AM		 4282014-08-19 Alan Modra <amodra@gmail.com>
429
430 * configure: Regenerate.
431
faa743bb
RM		 4322014-08-15 Roland McGrath <mcgrathr@google.com>
433
434 * configure: Regenerate.
435 * config.in: Regenerate.
436
1a8a700e
MF		 4372014-03-04 Mike Frysinger <vapier@gentoo.org>
438
439 * configure: Regenerate.
440
bf3d9781
AM		 4412013-09-23 Alan Modra <amodra@gmail.com>
442
443 * configure: Regenerate.
444
31e6ad7d
MF		 4452013-06-03 Mike Frysinger <vapier@gentoo.org>
446
447 * aclocal.m4, configure: Regenerate.
448
d3685d60
TT		 4492013-05-10 Freddie Chopin <freddie_chopin@op.pl>
450
451 * configure: Rebuild.
452
1517bd27
MF		 4532013-03-26 Mike Frysinger <vapier@gentoo.org>
454
455 * configure: Regenerate.
456
3be31516
JS		 4572013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
458
459 * configure.ac: Address use of dv-sockser.o.
460 * tconfig.in: Conditionalize use of dv_sockser_install.
461 * configure: Regenerated.
462 * config.in: Regenerated.
463
37cb8f8e
SE		 4642012-10-04 Chao-ying Fu <fu@mips.com>
465 Steve Ellcey <sellcey@mips.com>
466
467 * mips/mips3264r2.igen (rdhwr): New.
468
87c8644f
JS		 4692012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
470
471 * configure.ac: Always link against dv-sockser.o.
472 * configure: Regenerate.
473
5f3ef9d0
JB		 4742012-06-15 Joel Brobecker <brobecker@adacore.com>
475
476 * config.in, configure: Regenerate.
477
a6ff997c
NC		 4782012-05-18 Nick Clifton <nickc@redhat.com>
479
480 PR 14072
481 * interp.c: Include config.h before system header files.
482
2232061b
MF		 4832012-03-24 Mike Frysinger <vapier@gentoo.org>
484
485 * aclocal.m4, config.in, configure: Regenerate.
486
db2e4d67
MF		 4872011-12-03 Mike Frysinger <vapier@gentoo.org>
488
489 * aclocal.m4: New file.
490 * configure: Regenerate.
491
4399a56b
MF		 4922011-10-19 Mike Frysinger <vapier@gentoo.org>
493
494 * configure: Regenerate after common/acinclude.m4 update.
495
9c082ca8
MF		 4962011-10-17 Mike Frysinger <vapier@gentoo.org>
497
498 * configure.ac: Change include to common/acinclude.m4.
499
6ffe910a
MF		 5002011-10-17 Mike Frysinger <vapier@gentoo.org>
501
502 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
503 call. Replace common.m4 include with SIM_AC_COMMON.
504 * configure: Regenerate.
505
31b28250
HPN		 5062011-07-08 Hans-Peter Nilsson <hp@axis.com>
507
3faa01e3
HPN		 508 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
509 $(SIM_EXTRA_DEPS).
510 (tmp-mach-multi): Exit early when igen fails.
31b28250 511
2419798b
MF		 5122011-07-05 Mike Frysinger <vapier@gentoo.org>
513
514 * interp.c (sim_do_command): Delete.
515
d79fe0d6
MF		 5162011-02-14 Mike Frysinger <vapier@gentoo.org>
517
518 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
519 (tx3904sio_fifo_reset): Likewise.
520 * interp.c (sim_monitor): Likewise.
521
5558e7e6
MF		 5222010-04-14 Mike Frysinger <vapier@gentoo.org>
523
524 * interp.c (sim_write): Add const to buffer arg.
525
35aafff4
JB		 5262010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
527
528 * interp.c: Don't include sysdep.h
529
3725885a
RW		 5302010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
531
532 * configure: Regenerate.
533
d6416cdc
RW		 5342009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
535
81ecdfbb
RW		 536 * config.in: Regenerate.
537 * configure: Likewise.
538
d6416cdc
RW		 539 * configure: Regenerate.
540
b5bd9624
HPN		 5412008-07-11 Hans-Peter Nilsson <hp@axis.com>
542
543 * configure: Regenerate to track ../common/common.m4 changes.
544 * config.in: Ditto.
545
6efef468 5462008-06-06 Vladimir Prus <vladimir@codesourcery.com>
72f4393d
L		 547 Daniel Jacobowitz <dan@codesourcery.com>
548 Joseph Myers <joseph@codesourcery.com>
6efef468
JM		 549
550 * configure: Regenerate.
551
60dc88db
RS		 5522007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
553
554 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
555 that unconditionally allows fmt_ps.
556 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
557 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
558 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
559 filter from 64,f to 32,f.
560 (PREFX): Change filter from 64 to 32.
561 (LDXC1, LUXC1): Provide separate mips32r2 implementations
562 that use do_load_double instead of do_load. Make both LUXC1
563 versions unpredictable if SizeFGR () != 64.
564 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
565 instead of do_store. Remove unused variable. Make both SUXC1
566 versions unpredictable if SizeFGR () != 64.
567
599ca73e
RS		 5682007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
569
570 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
571 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
572 shifts for that case.
573
2525df03
NC		 5742007-09-04 Nick Clifton <nickc@redhat.com>
575
576 * interp.c (options enum): Add OPTION_INFO_MEMORY.
577 (display_mem_info): New static variable.
578 (mips_option_handler): Handle OPTION_INFO_MEMORY.
579 (mips_options): Add info-memory and memory-info.
580 (sim_open): After processing the command line and board
581 specification, check display_mem_info. If it is set then
582 call the real handler for the --memory-info command line
583 switch.
584
35ee6e1e
JB		 5852007-08-24 Joel Brobecker <brobecker@adacore.com>
586
587 * configure.ac: Change license of multi-run.c to GPL version 3.
588 * configure: Regenerate.
589
d5fb0879
RS		 5902007-06-28 Richard Sandiford <richard@codesourcery.com>
591
592 * configure.ac, configure: Revert last patch.
593
2a2ce21b
RS		 5942007-06-26 Richard Sandiford <richard@codesourcery.com>
595
596 * configure.ac (sim_mipsisa3264_configs): New variable.
597 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
598 every configuration support all four targets, using the triplet to
599 determine the default.
600 * configure: Regenerate.
601
efdcccc9
RS		 6022007-06-25 Richard Sandiford <richard@codesourcery.com>
603
0a7692b2 604 * Makefile.in (m16run.o): New rule.
efdcccc9 605
f532a356
TS		 6062007-05-15 Thiemo Seufer <ths@mips.com>
607
608 * mips3264r2.igen (DSHD): Fix compile warning.
609
bfe9c90b
TS		 6102007-05-14 Thiemo Seufer <ths@mips.com>
611
612 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
613 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
614 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
615 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
616 for mips32r2.
617
53f4826b
TS		 6182007-03-01 Thiemo Seufer <ths@mips.com>
619
620 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
621 and mips64.
622
8bf3ddc8
TS		 6232007-02-20 Thiemo Seufer <ths@mips.com>
624
625 * dsp.igen: Update copyright notice.
626 * dsp2.igen: Fix copyright notice.
627
8b082fb1 6282007-02-20 Thiemo Seufer <ths@mips.com>
72f4393d 629 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 630
631 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
632 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
633 Add dsp2 to sim_igen_machine.
634 * configure: Regenerate.
635 * dsp.igen (do_ph_op): Add MUL support when op = 2.
636 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
637 (mulq_rs.ph): Use do_ph_mulq.
638 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
639 * mips.igen: Add dsp2 model and include dsp2.igen.
640 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
641 for *mips32r2, *mips64r2, *dsp.
642 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
643 for *mips32r2, *mips64r2, *dsp2.
644 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
645
b1004875 6462007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 647 Nigel Stephens <nigel@mips.com>
b1004875
TS		 648
649 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
650 jumps with hazard barrier.
651
f8df4c77 6522007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 653 Nigel Stephens <nigel@mips.com>
f8df4c77
TS		 654
655 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
656 after each call to sim_io_write.
657
b1004875 6582007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 659 Nigel Stephens <nigel@mips.com>
b1004875
TS		 660
661 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
662 supported by this simulator.
07802d98
TS		 663 (decode_coproc): Recognise additional CP0 Config registers
664 correctly.
665
14fb6c5a 6662007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d
L		 667 Nigel Stephens <nigel@mips.com>
668 David Ung <davidu@mips.com>
14fb6c5a
TS		 669
670 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
671 uninterpreted formats. If fmt is one of the uninterpreted types
672 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
673 fmt_word, and fmt_uninterpreted_64 like fmt_long.
674 (store_fpr): When writing an invalid odd register, set the
675 matching even register to fmt_unknown, not the following register.
676 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
677 the the memory window at offset 0 set by --memory-size command
678 line option.
679 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
680 point register.
681 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
682 register.
683 (sim_monitor): When returning the memory size to the MIPS
684 application, use the value in STATE_MEM_SIZE, not an arbitrary
685 hardcoded value.
686 (cop_lw): Don' mess around with FPR_STATE, just pass
687 fmt_uninterpreted_32 to StoreFPR.
688 (cop_sw): Similarly.
689 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
690 (cop_sd): Similarly.
691 * mips.igen (not_word_value): Single version for mips32, mips64
692 and mips16.
693
c8847145 6942007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 695 Nigel Stephens <nigel@mips.com>
c8847145
TS		 696
697 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
698 MBytes.
699
4b5d35ee
TS		 7002007-02-17 Thiemo Seufer <ths@mips.com>
701
702 * configure.ac (mips*-sde-elf*): Move in front of generic machine
703 configuration.
704 * configure: Regenerate.
705
3669427c
TS		 7062007-02-17 Thiemo Seufer <ths@mips.com>
707
708 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
709 Add mdmx to sim_igen_machine.
710 (mipsisa64*-*-*): Likewise. Remove dsp.
711 (mipsisa32*-*-*): Remove dsp.
712 * configure: Regenerate.
713
109ad085
TS		 7142007-02-13 Thiemo Seufer <ths@mips.com>
715
716 * configure.ac: Add mips*-sde-elf* target.
717 * configure: Regenerate.
718
921d7ad3
HPN		 7192006-12-21 Hans-Peter Nilsson <hp@axis.com>
720
721 * acconfig.h: Remove.
722 * config.in, configure: Regenerate.
723
02f97da7
TS		 7242006-11-07 Thiemo Seufer <ths@mips.com>
725
726 * dsp.igen (do_w_op): Fix compiler warning.
727
2d2733fc 7282006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 729 David Ung <davidu@mips.com>
2d2733fc
TS		 730
731 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
732 sim_igen_machine.
733 * configure: Regenerate.
734 * mips.igen (model): Add smartmips.
735 (MADDU): Increment ACX if carry.
736 (do_mult): Clear ACX.
737 (ROR,RORV): Add smartmips.
72f4393d 738 (include): Include smartmips.igen.
2d2733fc
TS		 739 * sim-main.h (ACX): Set to REGISTERS[89].
740 * smartmips.igen: New file.
741
d85c3a10 7422006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 743 David Ung <davidu@mips.com>
d85c3a10
TS		 744
745 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
746 mips3264r2.igen. Add missing dependency rules.
747 * m16e.igen: Support for mips16e save/restore instructions.
748
e85e3205
RE		 7492006-06-13 Richard Earnshaw <rearnsha@arm.com>
750
751 * configure: Regenerated.
752
2f0122dc
DJ		 7532006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
754
755 * configure: Regenerated.
756
20e95c23
DJ		 7572006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
758
759 * configure: Regenerated.
760
69088b17
CF		 7612006-05-15 Chao-ying Fu <fu@mips.com>
762
763 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
764
0275de4e
NC		 7652006-04-18 Nick Clifton <nickc@redhat.com>
766
767 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
768 statement.
769
b3a3ffef
HPN		 7702006-03-29 Hans-Peter Nilsson <hp@axis.com>
771
772 * configure: Regenerate.
773
40a5538e
CF		 7742005-12-14 Chao-ying Fu <fu@mips.com>
775
776 * Makefile.in (SIM_OBJS): Add dsp.o.
777 (dsp.o): New dependency.
778 (IGEN_INCLUDE): Add dsp.igen.
779 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
780 mipsisa64*-*-*): Add dsp to sim_igen_machine.
781 * configure: Regenerate.
782 * mips.igen: Add dsp model and include dsp.igen.
783 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
784 because these instructions are extended in DSP ASE.
785 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
786 adding 6 DSP accumulator registers and 1 DSP control register.
787 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
788 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
789 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
790 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
791 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
792 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
793 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
794 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
795 DSPCR_CCOND_SMASK): New define.
796 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
797 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
798
21d14896
ILT		 7992005-07-08 Ian Lance Taylor <ian@airs.com>
800
801 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
802
b16d63da 8032005-06-16 David Ung <davidu@mips.com>
72f4393d
L		 804 Nigel Stephens <nigel@mips.com>
805
806 * mips.igen: New mips16e model and include m16e.igen.
807 (check_u64): Add mips16e tag.
808 * m16e.igen: New file for MIPS16e instructions.
809 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
810 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
811 models.
812 * configure: Regenerate.
b16d63da 813
e70cb6cd 8142005-05-26 David Ung <davidu@mips.com>
72f4393d 815
e70cb6cd
CD		 816 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
817 tags to all instructions which are applicable to the new ISAs.
818 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
819 vr.igen.
820 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
72f4393d 821 instructions.
e70cb6cd
CD		 822 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
823 to mips.igen.
824 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
825 * configure: Regenerate.
72f4393d 826
2b193c4a
MK		 8272005-03-23 Mark Kettenis <kettenis@gnu.org>
828
829 * configure: Regenerate.
830
35695fd6
AC		 8312005-01-14 Andrew Cagney <cagney@gnu.org>
832
833 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
834 explicit call to AC_CONFIG_HEADER.
835 * configure: Regenerate.
836
f0569246
AC		 8372005-01-12 Andrew Cagney <cagney@gnu.org>
838
839 * configure.ac: Update to use ../common/common.m4.
840 * configure: Re-generate.
841
38f48d72
AC		 8422005-01-11 Andrew Cagney <cagney@localhost.localdomain>
843
844 * configure: Regenerated to track ../common/aclocal.m4 changes.
845
b7026657
AC		 8462005-01-07 Andrew Cagney <cagney@gnu.org>
847
848 * configure.ac: Rename configure.in, require autoconf 2.59.
849 * configure: Re-generate.
850
379832de
HPN		 8512004-12-08 Hans-Peter Nilsson <hp@axis.com>
852
853 * configure: Regenerate for ../common/aclocal.m4 update.
854
cd62154c 8552004-09-24 Monika Chaddha <monika@acmet.com>
72f4393d 856
cd62154c
AC		 857 Committed by Andrew Cagney.
858 * m16.igen (CMP, CMPI): Fix assembler.
859
e5da76ec
CD		 8602004-08-18 Chris Demetriou <cgd@broadcom.com>
861
862 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
863 * configure: Regenerate.
864
139181c8
CD		 8652004-06-25 Chris Demetriou <cgd@broadcom.com>
866
867 * configure.in (sim_m16_machine): Include mipsIII.
868 * configure: Regenerate.
869
1a27f959
CD		 8702004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
871
72f4393d 872 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
1a27f959
CD		 873 from COP0_BADVADDR.
874 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
875
5dbb7b5a
CD		 8762004-04-10 Chris Demetriou <cgd@broadcom.com>
877
878 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
879
14234056
CD		 8802004-04-09 Chris Demetriou <cgd@broadcom.com>
881
882 * mips.igen (check_fmt): Remove.
883 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
884 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
885 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
886 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
887 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
888 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
889 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
890 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
891 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
892 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
893
c6f9085c
CD		 8942004-04-09 Chris Demetriou <cgd@broadcom.com>
895
896 * sb1.igen (check_sbx): New function.
897 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
898
11d66e66 8992004-03-29 Chris Demetriou <cgd@broadcom.com>
0e1b7197
RS		 900 Richard Sandiford <rsandifo@redhat.com>
901
902 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
903 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
904 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
905 separate implementations for mipsIV and mipsV. Use new macros to
906 determine whether the restrictions apply.
907
b3208fb8
CD		 9082004-01-19 Chris Demetriou <cgd@broadcom.com>
909
910 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
911 (check_mult_hilo): Improve comments.
912 (check_div_hilo): Likewise. Also, fork off a new version
913 to handle mips32/mips64 (since there are no hazards to check
914 in MIPS32/MIPS64).
915
9a1d84fb
CD		 9162003-06-17 Richard Sandiford <rsandifo@redhat.com>
917
918 * mips.igen (do_dmultx): Fix check for negative operands.
919
ae451ac6
ILT		 9202003-05-16 Ian Lance Taylor <ian@airs.com>
921
922 * Makefile.in (SHELL): Make sure this is defined.
923 (various): Use $(SHELL) whenever we invoke move-if-change.
924
dd69d292
CD		 9252003-05-03 Chris Demetriou <cgd@broadcom.com>
926
927 * cp1.c: Tweak attribution slightly.
928 * cp1.h: Likewise.
929 * mdmx.c: Likewise.
930 * mdmx.igen: Likewise.
931 * mips3d.igen: Likewise.
932 * sb1.igen: Likewise.
933
bcd0068e
CD		 9342003-04-15 Richard Sandiford <rsandifo@redhat.com>
935
936 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
937 unsigned operands.
938
6b4a8935
AC		 9392003-02-27 Andrew Cagney <cagney@redhat.com>
940
601da316
AC		 941 * interp.c (sim_open): Rename _bfd to bfd.
942 (sim_create_inferior): Ditto.
6b4a8935 943
d29e330f
CD		 9442003-01-14 Chris Demetriou <cgd@broadcom.com>
945
946 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
947
a2353a08
CD		 9482003-01-14 Chris Demetriou <cgd@broadcom.com>
949
950 * mips.igen (EI, DI): Remove.
951
80551777
CD		 9522003-01-05 Richard Sandiford <rsandifo@redhat.com>
953
954 * Makefile.in (tmp-run-multi): Fix mips16 filter.
955
4c54fc26
CD		 9562003-01-04 Richard Sandiford <rsandifo@redhat.com>
957 Andrew Cagney <ac131313@redhat.com>
958 Gavin Romig-Koch <gavin@redhat.com>
959 Graydon Hoare <graydon@redhat.com>
960 Aldy Hernandez <aldyh@redhat.com>
961 Dave Brolley <brolley@redhat.com>
962 Chris Demetriou <cgd@broadcom.com>
963
964 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
965 (sim_mach_default): New variable.
966 (mips64vr-*-*, mips64vrel-*-*): New configurations.
967 Add a new simulator generator, MULTI.
968 * configure: Regenerate.
969 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
970 (multi-run.o): New dependency.
971 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
972 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
973 (tmp-multi): Combine them.
974 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
975 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
976 (distclean-extra): New rule.
977 * sim-main.h: Include bfd.h.
978 (MIPS_MACH): New macro.
979 * mips.igen (vr4120, vr5400, vr5500): New models.
980 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
981 * vr.igen: Replace with new version.
982
e6c674b8
CD		 9832003-01-04 Chris Demetriou <cgd@broadcom.com>
984
985 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
986 * configure: Regenerate.
987
28f50ac8
CD		 9882002-12-31 Chris Demetriou <cgd@broadcom.com>
989
990 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
991 * mips.igen: Remove all invocations of check_branch_bug and
992 mark_branch_bug.
993
5071ffe6
CD		 9942002-12-16 Chris Demetriou <cgd@broadcom.com>
995
72f4393d 996 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
5071ffe6 997
06e7837e
CD		 9982002-07-30 Chris Demetriou <cgd@broadcom.com>
999
1000 * mips.igen (do_load_double, do_store_double): New functions.
1001 (LDC1, SDC1): Rename to...
1002 (LDC1b, SDC1b): respectively.
1003 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
1004
2265c243
MS		 10052002-07-29 Michael Snyder <msnyder@redhat.com>
1006
1007 * cp1.c (fp_recip2): Modify initialization expression so that
1008 GCC will recognize it as constant.
1009
a2f8b4f3
CD		 10102002-06-18 Chris Demetriou <cgd@broadcom.com>
1011
1012 * mdmx.c (SD_): Delete.
1013 (Unpredictable): Re-define, for now, to directly invoke
1014 unpredictable_action().
1015 (mdmx_acc_op): Fix error in .ob immediate handling.
1016
b4b6c939
AC		 10172002-06-18 Andrew Cagney <cagney@redhat.com>
1018
1019 * interp.c (sim_firmware_command): Initialize `address'.
1020
c8cca39f
AC		 10212002-06-16 Andrew Cagney <ac131313@redhat.com>
1022
1023 * configure: Regenerated to track ../common/aclocal.m4 changes.
1024
e7e81181 10252002-06-14 Chris Demetriou <cgd@broadcom.com>
72f4393d 1026 Ed Satterthwaite <ehs@broadcom.com>
e7e81181
CD		 1027
1028 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
1029 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
1030 * mips.igen: Include mips3d.igen.
1031 (mips3d): New model name for MIPS-3D ASE instructions.
1032 (CVT.W.fmt): Don't use this instruction for word (source) format
72f4393d 1033 instructions.
e7e81181
CD		 1034 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
1035 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
1036 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
1037 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
1038 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
1039 (RSquareRoot1, RSquareRoot2): New macros.
1040 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
1041 (fp_rsqrt2): New functions.
1042 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
1043 * configure: Regenerate.
1044
3a2b820e 10452002-06-13 Chris Demetriou <cgd@broadcom.com>
72f4393d 1046 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 1047
1048 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
1049 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
1050 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
1051 (convert): Note that this function is not used for paired-single
1052 format conversions.
1053 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
1054 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
1055 (check_fmt_p): Enable paired-single support.
1056 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
1057 (PUU.PS): New instructions.
1058 (CVT.S.fmt): Don't use this instruction for paired-single format
1059 destinations.
1060 * sim-main.h (FP_formats): New value 'fmt_ps.'
1061 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
1062 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
1063
d18ea9c2
CD		 10642002-06-12 Chris Demetriou <cgd@broadcom.com>
1065
1066 * mips.igen: Fix formatting of function calls in
1067 many FP operations.
1068
95fd5cee
CD		 10692002-06-12 Chris Demetriou <cgd@broadcom.com>
1070
1071 * mips.igen (MOVN, MOVZ): Trace result.
1072 (TNEI): Print "tnei" as the opcode name in traces.
1073 (CEIL.W): Add disassembly string for traces.
1074 (RSQRT.fmt): Make location of disassembly string consistent
1075 with other instructions.
1076
4f0d55ae
CD		 10772002-06-12 Chris Demetriou <cgd@broadcom.com>
1078
1079 * mips.igen (X): Delete unused function.
1080
3c25f8c7
AC		 10812002-06-08 Andrew Cagney <cagney@redhat.com>
1082
1083 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
1084
f3c08b7e 10852002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1086 Ed Satterthwaite <ehs@broadcom.com>
f3c08b7e
CD		 1087
1088 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
1089 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
1090 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
1091 (fp_nmsub): New prototypes.
1092 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
1093 (NegMultiplySub): New defines.
1094 * mips.igen (RSQRT.fmt): Use RSquareRoot().
1095 (MADD.D, MADD.S): Replace with...
1096 (MADD.fmt): New instruction.
1097 (MSUB.D, MSUB.S): Replace with...
1098 (MSUB.fmt): New instruction.
1099 (NMADD.D, NMADD.S): Replace with...
1100 (NMADD.fmt): New instruction.
1101 (NMSUB.D, MSUB.S): Replace with...
1102 (NMSUB.fmt): New instruction.
1103
52714ff9 11042002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1105 Ed Satterthwaite <ehs@broadcom.com>
52714ff9
CD		 1106
1107 * cp1.c: Fix more comment spelling and formatting.
1108 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
1109 (denorm_mode): New function.
1110 (fpu_unary, fpu_binary): Round results after operation, collect
1111 status from rounding operations, and update the FCSR.
1112 (convert): Collect status from integer conversions and rounding
1113 operations, and update the FCSR. Adjust NaN values that result
1114 from conversions. Convert to use sim_io_eprintf rather than
1115 fprintf, and remove some debugging code.
1116 * cp1.h (fenr_FS): New define.
1117
577d8c4b
CD		 11182002-06-07 Chris Demetriou <cgd@broadcom.com>
1119
1120 * cp1.c (convert): Remove unusable debugging code, and move MIPS
1121 rounding mode to sim FP rounding mode flag conversion code into...
1122 (rounding_mode): New function.
1123
196496ed
CD		 11242002-06-07 Chris Demetriou <cgd@broadcom.com>
1125
1126 * cp1.c: Clean up formatting of a few comments.
1127 (value_fpr): Reformat switch statement.
1128
cfe9ea23 11292002-06-06 Chris Demetriou <cgd@broadcom.com>
72f4393d 1130 Ed Satterthwaite <ehs@broadcom.com>
cfe9ea23
CD		 1131
1132 * cp1.h: New file.
1133 * sim-main.h: Include cp1.h.
1134 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
1135 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
1136 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
1137 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
1138 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
1139 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
1140 * cp1.c: Don't include sim-fpu.h; already included by
1141 sim-main.h. Clean up formatting of some comments.
1142 (NaN, Equal, Less): Remove.
1143 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
1144 (fp_cmp): New functions.
1145 * mips.igen (do_c_cond_fmt): Remove.
1146 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
1147 Compare. Add result tracing.
1148 (CxC1): Remove, replace with...
1149 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
1150 (DMxC1): Remove, replace with...
1151 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
72f4393d
L		 1152 (MxC1): Remove, replace with...
1153 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
cfe9ea23 1154
ee7254b0
CD		 11552002-06-04 Chris Demetriou <cgd@broadcom.com>
1156
1157 * sim-main.h (FGRIDX): Remove, replace all uses with...
1158 (FGR_BASE): New macro.
1159 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
1160 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
1161 (NR_FGR, FGR): Likewise.
1162 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
1163 * mips.igen: Likewise.
1164
d3eb724f
CD		 11652002-06-04 Chris Demetriou <cgd@broadcom.com>
1166
1167 * cp1.c: Add an FSF Copyright notice to this file.
1168
ba46ddd0 11692002-06-04 Chris Demetriou <cgd@broadcom.com>
72f4393d 1170 Ed Satterthwaite <ehs@broadcom.com>
ba46ddd0
CD		 1171
1172 * cp1.c (Infinity): Remove.
1173 * sim-main.h (Infinity): Likewise.
1174
1175 * cp1.c (fp_unary, fp_binary): New functions.
1176 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
1177 (fp_sqrt): New functions, implemented in terms of the above.
1178 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1179 (Recip, SquareRoot): Remove (replaced by functions above).
1180 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
1181 (fp_recip, fp_sqrt): New prototypes.
1182 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1183 (Recip, SquareRoot): Replace prototypes with #defines which
1184 invoke the functions above.
72f4393d 1185
18d8a52d
CD		 11862002-06-03 Chris Demetriou <cgd@broadcom.com>
1187
1188 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
1189 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
1190 file, remove PARAMS from prototypes.
1191 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
1192 simulator state arguments.
1193 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
1194 pass simulator state arguments.
1195 * cp1.c (SD): Redefine as CPU_STATE(cpu).
1196 (store_fpr, convert): Remove 'sd' argument.
1197 (value_fpr): Likewise. Convert to use 'SD' instead.
1198
0f154cbd
CD		 11992002-06-03 Chris Demetriou <cgd@broadcom.com>
1200
1201 * cp1.c (Min, Max): Remove #if 0'd functions.
1202 * sim-main.h (Min, Max): Remove.
1203
e80fc152
CD		 12042002-06-03 Chris Demetriou <cgd@broadcom.com>
1205
1206 * cp1.c: fix formatting of switch case and default labels.
1207 * interp.c: Likewise.
1208 * sim-main.c: Likewise.
1209
bad673a9
CD		 12102002-06-03 Chris Demetriou <cgd@broadcom.com>
1211
1212 * cp1.c: Clean up comments which describe FP formats.
1213 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
1214
7cbea089 12152002-06-03 Chris Demetriou <cgd@broadcom.com>
72f4393d 1216 Ed Satterthwaite <ehs@broadcom.com>
7cbea089
CD		 1217
1218 * configure.in (mipsisa64sb1*-*-*): New target for supporting
1219 Broadcom SiByte SB-1 processor configurations.
1220 * configure: Regenerate.
1221 * sb1.igen: New file.
1222 * mips.igen: Include sb1.igen.
1223 (sb1): New model.
1224 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
1225 * mdmx.igen: Add "sb1" model to all appropriate functions and
1226 instructions.
1227 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
1228 (ob_func, ob_acc): Reference the above.
1229 (qh_acc): Adjust to keep the same size as ob_acc.
1230 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
1231 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
1232
909daa82
CD		 12332002-06-03 Chris Demetriou <cgd@broadcom.com>
1234
1235 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
1236
f4f1b9f1 12372002-06-02 Chris Demetriou <cgd@broadcom.com>
72f4393d 1238 Ed Satterthwaite <ehs@broadcom.com>
f4f1b9f1
CD		 1239
1240 * mips.igen (mdmx): New (pseudo-)model.
1241 * mdmx.c, mdmx.igen: New files.
1242 * Makefile.in (SIM_OBJS): Add mdmx.o.
1243 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
1244 New typedefs.
1245 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
1246 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
1247 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
1248 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
1249 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
1250 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
1251 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
1252 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
1253 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
1254 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
1255 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
1256 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
1257 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
1258 (qh_fmtsel): New macros.
1259 (_sim_cpu): New member "acc".
1260 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
1261 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
1262
5accf1ff
CD		 12632002-05-01 Chris Demetriou <cgd@broadcom.com>
1264
1265 * interp.c: Use 'deprecated' rather than 'depreciated.'
1266 * sim-main.h: Likewise.
1267
402586aa
CD		 12682002-05-01 Chris Demetriou <cgd@broadcom.com>
1269
1270 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
1271 which wouldn't compile anyway.
1272 * sim-main.h (unpredictable_action): New function prototype.
1273 (Unpredictable): Define to call igen function unpredictable().
1274 (NotWordValue): New macro to call igen function not_word_value().
1275 (UndefinedResult): Remove.
1276 * interp.c (undefined_result): Remove.
1277 (unpredictable_action): New function.
1278 * mips.igen (not_word_value, unpredictable): New functions.
1279 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
1280 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
1281 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
1282 NotWordValue() to check for unpredictable inputs, then
1283 Unpredictable() to handle them.
1284
c9b9995a
CD		 12852002-02-24 Chris Demetriou <cgd@broadcom.com>
1286
1287 * mips.igen: Fix formatting of calls to Unpredictable().
1288
e1015982
AC		 12892002-04-20 Andrew Cagney <ac131313@redhat.com>
1290
1291 * interp.c (sim_open): Revert previous change.
1292
b882a66b
AO		 12932002-04-18 Alexandre Oliva <aoliva@redhat.com>
1294
1295 * interp.c (sim_open): Disable chunk of code that wrote code in
1296 vector table entries.
1297
c429b7dd
CD		 12982002-03-19 Chris Demetriou <cgd@broadcom.com>
1299
1300 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
1301 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
1302 unused definitions.
1303
37d146fa
CD		 13042002-03-19 Chris Demetriou <cgd@broadcom.com>
1305
1306 * cp1.c: Fix many formatting issues.
1307
07892c0b
CD		 13082002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1309
1310 * cp1.c (fpu_format_name): New function to replace...
1311 (DOFMT): This. Delete, and update all callers.
1312 (fpu_rounding_mode_name): New function to replace...
1313 (RMMODE): This. Delete, and update all callers.
1314
487f79b7
CD		 13152002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1316
1317 * interp.c: Move FPU support routines from here to...
1318 * cp1.c: Here. New file.
1319 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
1320 (cp1.o): New target.
1321
1e799e28
CD		 13222002-03-12 Chris Demetriou <cgd@broadcom.com>
1323
1324 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
1325 * mips.igen (mips32, mips64): New models, add to all instructions
1326 and functions as appropriate.
1327 (loadstore_ea, check_u64): New variant for model mips64.
1328 (check_fmt_p): New variant for models mipsV and mips64, remove
1329 mipsV model marking fro other variant.
1330 (SLL) Rename to...
1331 (SLLa) this.
1332 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
1333 for mips32 and mips64.
1334 (DCLO, DCLZ): New instructions for mips64.
1335
82f728db
CD		 13362002-03-07 Chris Demetriou <cgd@broadcom.com>
1337
1338 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
1339 immediate or code as a hex value with the "%#lx" format.
1340 (ANDI): Likewise, and fix printed instruction name.
1341
b96e7ef1
CD		 13422002-03-05 Chris Demetriou <cgd@broadcom.com>
1343
1344 * sim-main.h (UndefinedResult, Unpredictable): New macros
1345 which currently do nothing.
1346
d35d4f70
CD		 13472002-03-05 Chris Demetriou <cgd@broadcom.com>
1348
1349 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
1350 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
1351 (status_CU3): New definitions.
1352
1353 * sim-main.h (ExceptionCause): Add new values for MIPS32
1354 and MIPS64: MDMX, MCheck, CacheErr. Update comments
1355 for DebugBreakPoint and NMIReset to note their status in
1356 MIPS32 and MIPS64.
1357 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
1358 (SignalExceptionCacheErr): New exception macros.
1359
3ad6f714
CD		 13602002-03-05 Chris Demetriou <cgd@broadcom.com>
1361
1362 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
1363 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
1364 is always enabled.
1365 (SignalExceptionCoProcessorUnusable): Take as argument the
1366 unusable coprocessor number.
1367
86b77b47
CD		 13682002-03-05 Chris Demetriou <cgd@broadcom.com>
1369
1370 * mips.igen: Fix formatting of all SignalException calls.
1371
97a88e93 13722002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 1373
1374 * sim-main.h (SIGNEXTEND): Remove.
1375
97a88e93 13762002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 1377
1378 * mips.igen: Remove gencode comment from top of file, fix
1379 spelling in another comment.
1380
97a88e93 13812002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 1382
1383 * mips.igen (check_fmt, check_fmt_p): New functions to check
1384 whether specific floating point formats are usable.
1385 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1386 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
1387 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
1388 Use the new functions.
1389 (do_c_cond_fmt): Remove format checks...
1390 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
1391
97a88e93 13922002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 1393
1394 * mips.igen: Fix formatting of check_fpu calls.
1395
41774c9d
CD		 13962002-03-03 Chris Demetriou <cgd@broadcom.com>
1397
1398 * mips.igen (FLOOR.L.fmt): Store correct destination register.
1399
4a0bd876
CD		 14002002-03-03 Chris Demetriou <cgd@broadcom.com>
1401
1402 * mips.igen: Remove whitespace at end of lines.
1403
09297648
CD		 14042002-03-02 Chris Demetriou <cgd@broadcom.com>
1405
1406 * mips.igen (loadstore_ea): New function to do effective
1407 address calculations.
1408 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
1409 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
1410 CACHE): Use loadstore_ea to do effective address computations.
1411
043b7057
CD		 14122002-03-02 Chris Demetriou <cgd@broadcom.com>
1413
1414 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
1415 * mips.igen (LL, CxC1, MxC1): Likewise.
1416
c1e8ada4
CD		 14172002-03-02 Chris Demetriou <cgd@broadcom.com>
1418
1419 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
1420 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
1421 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
1422 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
1423 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
1424 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
1425 Don't split opcode fields by hand, use the opcode field values
1426 provided by igen.
1427
3e1dca16
CD		 14282002-03-01 Chris Demetriou <cgd@broadcom.com>
1429
1430 * mips.igen (do_divu): Fix spacing.
1431
1432 * mips.igen (do_dsllv): Move to be right before DSLLV,
1433 to match the rest of the do_<shift> functions.
1434
fff8d27d
CD		 14352002-03-01 Chris Demetriou <cgd@broadcom.com>
1436
1437 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
1438 DSRL32, do_dsrlv): Trace inputs and results.
1439
0d3e762b
CD		 14402002-03-01 Chris Demetriou <cgd@broadcom.com>
1441
1442 * mips.igen (CACHE): Provide instruction-printing string.
1443
1444 * interp.c (signal_exception): Comment tokens after #endif.
1445
eb5fcf93
CD		 14462002-02-28 Chris Demetriou <cgd@broadcom.com>
1447
1448 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
72f4393d
L		 1449 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
1450 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
1451 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
1452 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
1453 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
1454 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
eb5fcf93
CD		 1455 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
1456
bb22bd7d
CD		 14572002-02-28 Chris Demetriou <cgd@broadcom.com>
1458
1459 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
1460 instruction-printing string.
1461 (LWU): Use '64' as the filter flag.
1462
91a177cf
CD		 14632002-02-28 Chris Demetriou <cgd@broadcom.com>
1464
1465 * mips.igen (SDXC1): Fix instruction-printing string.
1466
387f484a
CD		 14672002-02-28 Chris Demetriou <cgd@broadcom.com>
1468
1469 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
1470 filter flags "32,f".
1471
3d81f391
CD		 14722002-02-27 Chris Demetriou <cgd@broadcom.com>
1473
1474 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1475 as the filter flag.
1476
af5107af
CD		 14772002-02-27 Chris Demetriou <cgd@broadcom.com>
1478
1479 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1480 add a comma) so that it more closely match the MIPS ISA
1481 documentation opcode partitioning.
1482 (PREF): Put useful names on opcode fields, and include
1483 instruction-printing string.
1484
ca971540
CD		 14852002-02-27 Chris Demetriou <cgd@broadcom.com>
1486
1487 * mips.igen (check_u64): New function which in the future will
1488 check whether 64-bit instructions are usable and signal an
1489 exception if not. Currently a no-op.
1490 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1491 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1492 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1493 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1494
1495 * mips.igen (check_fpu): New function which in the future will
1496 check whether FPU instructions are usable and signal an exception
1497 if not. Currently a no-op.
1498 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1499 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1500 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1501 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1502 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1503 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1504 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1505 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1506
1c47a468
CD		 15072002-02-27 Chris Demetriou <cgd@broadcom.com>
1508
1509 * mips.igen (do_load_left, do_load_right): Move to be immediately
1510 following do_load.
1511 (do_store_left, do_store_right): Move to be immediately following
1512 do_store.
1513
603a98e7
CD		 15142002-02-27 Chris Demetriou <cgd@broadcom.com>
1515
1516 * mips.igen (mipsV): New model name. Also, add it to
1517 all instructions and functions where it is appropriate.
1518
c5d00cc7
CD		 15192002-02-18 Chris Demetriou <cgd@broadcom.com>
1520
1521 * mips.igen: For all functions and instructions, list model
1522 names that support that instruction one per line.
1523
074e9cb8
CD		 15242002-02-11 Chris Demetriou <cgd@broadcom.com>
1525
1526 * mips.igen: Add some additional comments about supported
1527 models, and about which instructions go where.
1528 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1529 order as is used in the rest of the file.
1530
9805e229
CD		 15312002-02-11 Chris Demetriou <cgd@broadcom.com>
1532
1533 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1534 indicating that ALU32_END or ALU64_END are there to check
1535 for overflow.
1536 (DADD): Likewise, but also remove previous comment about
1537 overflow checking.
1538
f701dad2
CD		 15392002-02-10 Chris Demetriou <cgd@broadcom.com>
1540
1541 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1542 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1543 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1544 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1545 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1546 fields (i.e., add and move commas) so that they more closely
1547 match the MIPS ISA documentation opcode partitioning.
1548
15492002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098 1550
72f4393d
L		 1551 * mips.igen (ADDI): Print immediate value.
1552 (BREAK): Print code.
1553 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1554 (SLL): Print "nop" specially, and don't run the code
1555 that does the shift for the "nop" case.
20ae0098 1556
9e52972e
FF		 15572001-11-17 Fred Fish <fnf@redhat.com>
1558
1559 * sim-main.h (float_operation): Move enum declaration outside
1560 of _sim_cpu struct declaration.
1561
c0efbca4
JB		 15622001-04-12 Jim Blandy <jimb@redhat.com>
1563
1564 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1565 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1566 set of the FCSR.
1567 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1568 PENDING_FILL, and you can get the intended effect gracefully by
1569 calling PENDING_SCHED directly.
1570
fb891446
BE		 15712001-02-23 Ben Elliston <bje@redhat.com>
1572
1573 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1574 already defined elsewhere.
1575
8030f857
BE		 15762001-02-19 Ben Elliston <bje@redhat.com>
1577
1578 * sim-main.h (sim_monitor): Return an int.
1579 * interp.c (sim_monitor): Add return values.
1580 (signal_exception): Handle error conditions from sim_monitor.
1581
56b48a7a
CD		 15822001-02-08 Ben Elliston <bje@redhat.com>
1583
1584 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1585 (store_memory): Likewise, pass cia to sim_core_write*.
1586
d3ee60d9
FCE		 15872000-10-19 Frank Ch. Eigler <fche@redhat.com>
1588
1589 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1590 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1591
071da002
AC		 1592Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1593
1594 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1595 * Makefile.in: Don't delete *.igen when cleaning directory.
1596
a28c02cd
AC		 1597Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1598
1599 * m16.igen (break): Call SignalException not sim_engine_halt.
1600
80ee11fa
AC		 1601Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1602
1603 From Jason Eckhardt:
1604 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1605
673388c0
AC		 1606Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1607
1608 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1609
4c0deff4
NC		 16102000-05-24 Michael Hayes <mhayes@cygnus.com>
1611
1612 * mips.igen (do_dmultx): Fix typo.
1613
eb2d80b4
AC		 1614Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1615
1616 * configure: Regenerated to track ../common/aclocal.m4 changes.
1617
dd37a34b
AC		 1618Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1619
1620 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1621
4c0deff4
NC		 16222000-04-12 Frank Ch. Eigler <fche@redhat.com>
1623
1624 * sim-main.h (GPR_CLEAR): Define macro.
1625
e30db738
AC		 1626Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1627
1628 * interp.c (decode_coproc): Output long using %lx and not %s.
1629
cb7450ea
FCE		 16302000-03-21 Frank Ch. Eigler <fche@redhat.com>
1631
1632 * interp.c (sim_open): Sort & extend dummy memory regions for
1633 --board=jmr3904 for eCos.
1634
a3027dd7
FCE		 16352000-03-02 Frank Ch. Eigler <fche@redhat.com>
1636
1637 * configure: Regenerated.
1638
1639Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1640
1641 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1642 calls, conditional on the simulator being in verbose mode.
1643
dfcd3bfb
JM		 1644Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1645
1646 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1647 cache don't get ReservedInstruction traps.
1648
c2d11a7d
JM		 16491999-11-29 Mark Salter <msalter@cygnus.com>
1650
1651 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1652 to clear status bits in sdisr register. This is how the hardware works.
1653
1654 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1655 being used by cygmon.
1656
4ce44c66
JM		 16571999-11-11 Andrew Haley <aph@cygnus.com>
1658
1659 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1660 instructions.
1661
cff3e48b
JM		 1662Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1663
1664 * mips.igen (MULT): Correct previous mis-applied patch.
1665
d4f3574e
SS		 1666Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1667
1668 * mips.igen (delayslot32): Handle sequence like
1669 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1670 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1671 (MULT): Actually pass the third register...
1672
16731999-09-03 Mark Salter <msalter@cygnus.com>
1674
1675 * interp.c (sim_open): Added more memory aliases for additional
1676 hardware being touched by cygmon on jmr3904 board.
1677
1678Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1679
1680 * configure: Regenerated to track ../common/aclocal.m4 changes.
1681
a0b3c4fd
JM		 1682Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1683
1684 * interp.c (sim_store_register): Handle case where client - GDB -
1685 specifies that a 4 byte register is 8 bytes in size.
1686 (sim_fetch_register): Ditto.
72f4393d 1687
adf40b2e
JM		 16881999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1689
1690 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1691 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1692 (idt_monitor_base): Base address for IDT monitor traps.
1693 (pmon_monitor_base): Ditto for PMON.
1694 (lsipmon_monitor_base): Ditto for LSI PMON.
1695 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1696 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1697 (sim_firmware_command): New function.
1698 (mips_option_handler): Call it for OPTION_FIRMWARE.
1699 (sim_open): Allocate memory for idt_monitor region. If "--board"
1700 option was given, add no monitor by default. Add BREAK hooks only if
1701 monitors are also there.
72f4393d 1702
43e526b9
JM		 1703Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1704
1705 * interp.c (sim_monitor): Flush output before reading input.
1706
1707Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1708
1709 * tconfig.in (SIM_HANDLES_LMA): Always define.
1710
1711Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1712
1713 From Mark Salter <msalter@cygnus.com>:
1714 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1715 (sim_open): Add setup for BSP board.
1716
9846de1b
JM		 1717Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1718
1719 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1720 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1721 them as unimplemented.
1722
cd0fc7c3
SS		 17231999-05-08 Felix Lee <flee@cygnus.com>
1724
1725 * configure: Regenerated to track ../common/aclocal.m4 changes.
72f4393d 1726
7a292a7a
SS		 17271999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1728
1729 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1730
1731Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1732
1733 * configure.in: Any mips64vr5*-*-* target should have
1734 -DTARGET_ENABLE_FR=1.
1735 (default_endian): Any mips64vr*el-*-* target should default to
1736 LITTLE_ENDIAN.
1737 * configure: Re-generate.
1738
17391999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1740
1741 * mips.igen (ldl): Extend from _16_, not 32.
1742
1743Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1744
1745 * interp.c (sim_store_register): Force registers written to by GDB
1746 into an un-interpreted state.
1747
c906108c
SS		 17481999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1749
1750 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1751 CPU, start periodic background I/O polls.
72f4393d 1752 (tx3904sio_poll): New function: periodic I/O poller.
c906108c
SS		 1753
17541998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1755
1756 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
72f4393d 1757
c906108c
SS		 1758Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1759
1760 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1761 case statement.
1762
17631998-12-29 Frank Ch. Eigler <fche@cygnus.com>
72f4393d
L		 1764
1765 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
c906108c
SS		 1766 (load_word): Call SIM_CORE_SIGNAL hook on error.
1767 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1768 starting. For exception dispatching, pass PC instead of NULL_CIA.
1769 (decode_coproc): Use COP0_BADVADDR to store faulting address.
72f4393d 1770 * sim-main.h (COP0_BADVADDR): Define.
c906108c
SS		 1771 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1772 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
72f4393d 1773 (_sim_cpu): Add exc_* fields to store register value snapshots.
c906108c
SS		 1774 * mips.igen (*): Replace memory-related SignalException* calls
1775 with references to SIM_CORE_SIGNAL hook.
72f4393d 1776
c906108c
SS		 1777 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1778 fix.
1779 * sim-main.c (*): Minor warning cleanups.
72f4393d 1780
c906108c
SS		 17811998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1782
1783 * m16.igen (DADDIU5): Correct type-o.
1784
1785Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1786
1787 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1788 variables.
1789
1790Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1791
1792 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1793 to include path.
1794 (interp.o): Add dependency on itable.h
1795 (oengine.c, gencode): Delete remaining references.
1796 (BUILT_SRC_FROM_GEN): Clean up.
72f4393d 1797
c906108c 17981998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
72f4393d 1799
c906108c
SS		 1800 * vr4run.c: New.
1801 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1802 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1803 tmp-run-hack) : New.
1804 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
72f4393d 1805 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
c906108c
SS		 1806 Drop the "64" qualifier to get the HACK generator working.
1807 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1808 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1809 qualifier to get the hack generator working.
1810 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1811 (DSLL): Use do_dsll.
1812 (DSLLV): Use do_dsllv.
1813 (DSRA): Use do_dsra.
1814 (DSRL): Use do_dsrl.
1815 (DSRLV): Use do_dsrlv.
1816 (BC1): Move *vr4100 to get the HACK generator working.
72f4393d 1817 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
c906108c
SS		 1818 get the HACK generator working.
1819 (MACC) Rename to get the HACK generator working.
1820 (DMACC,MACCS,DMACCS): Add the 64.
72f4393d 1821
c906108c
SS		 18221998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1823
1824 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1825 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
72f4393d 1826
c906108c
SS		 18271998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1828
1829 * mips/interp.c (DEBUG): Cleanups.
1830
18311998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1832
1833 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1834 (tx3904sio_tickle): fflush after a stdout character output.
72f4393d 1835
c906108c
SS		 18361998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1837
1838 * interp.c (sim_close): Uninstall modules.
1839
1840Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1841
1842 * sim-main.h, interp.c (sim_monitor): Change to global
1843 function.
1844
1845Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1846
1847 * configure.in (vr4100): Only include vr4100 instructions in
1848 simulator.
1849 * configure: Re-generate.
1850 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1851
1852Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1853
1854 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1855 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1856 true alternative.
1857
1858 * configure.in (sim_default_gen, sim_use_gen): Replace with
1859 sim_gen.
1860 (--enable-sim-igen): Delete config option. Always using IGEN.
1861 * configure: Re-generate.
72f4393d 1862
c906108c
SS		 1863 * Makefile.in (gencode): Kill, kill, kill.
1864 * gencode.c: Ditto.
72f4393d 1865
c906108c
SS		 1866Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1867
1868 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1869 bit mips16 igen simulator.
1870 * configure: Re-generate.
1871
1872 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1873 as part of vr4100 ISA.
1874 * vr.igen: Mark all instructions as 64 bit only.
1875
1876Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1877
1878 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1879 Pacify GCC.
1880
1881Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1882
1883 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1884 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1885 * configure: Re-generate.
1886
1887 * m16.igen (BREAK): Define breakpoint instruction.
1888 (JALX32): Mark instruction as mips16 and not r3900.
1889 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1890
1891 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1892
1893Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1894
1895 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1896 insn as a debug breakpoint.
1897
1898 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1899 pending.slot_size.
1900 (PENDING_SCHED): Clean up trace statement.
1901 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1902 (PENDING_FILL): Delay write by only one cycle.
1903 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1904
1905 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1906 of pending writes.
1907 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1908 32 & 64.
1909 (pending_tick): Move incrementing of index to FOR statement.
1910 (pending_tick): Only update PENDING_OUT after a write has occured.
72f4393d 1911
c906108c
SS		 1912 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1913 build simulator.
1914 * configure: Re-generate.
72f4393d 1915
c906108c
SS		 1916 * interp.c (sim_engine_run OLD): Delete explicit call to
1917 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
72f4393d 1918
c906108c
SS		 1919Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1920
1921 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1922 interrupt level number to match changed SignalExceptionInterrupt
1923 macro.
1924
1925Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1926
1927 * interp.c: #include "itable.h" if WITH_IGEN.
1928 (get_insn_name): New function.
1929 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1930 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1931
1932Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1933
1934 * configure: Rebuilt to inhale new common/aclocal.m4.
1935
1936Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1937
1938 * dv-tx3904sio.c: Include sim-assert.h.
1939
1940Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1941
1942 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1943 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1944 Reorganize target-specific sim-hardware checks.
1945 * configure: rebuilt.
1946 * interp.c (sim_open): For tx39 target boards, set
1947 OPERATING_ENVIRONMENT, add tx3904sio devices.
1948 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1949 ROM executables. Install dv-sockser into sim-modules list.
72f4393d 1950
c906108c
SS		 1951 * dv-tx3904irc.c: Compiler warning clean-up.
1952 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1953 frequent hw-trace messages.
1954
1955Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1956
1957 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1958
1959Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1960
1961 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1962
1963 * vr.igen: New file.
1964 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1965 * mips.igen: Define vr4100 model. Include vr.igen.
1966Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1967
1968 * mips.igen (check_mf_hilo): Correct check.
1969
1970Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1971
1972 * sim-main.h (interrupt_event): Add prototype.
1973
1974 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1975 register_ptr, register_value.
1976 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1977
1978 * sim-main.h (tracefh): Make extern.
1979
1980Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1981
1982 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
72f4393d 1983 Reduce unnecessarily high timer event frequency.
c906108c 1984 * dv-tx3904cpu.c: Ditto for interrupt event.
72f4393d 1985
c906108c
SS		 1986Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1987
1988 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1989 to allay warnings.
1990 (interrupt_event): Made non-static.
72f4393d 1991
c906108c
SS		 1992 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1993 interchange of configuration values for external vs. internal
1994 clock dividers.
72f4393d 1995
c906108c
SS		 1996Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1997
72f4393d 1998 * mips.igen (BREAK): Moved code to here for
c906108c
SS		 1999 simulator-reserved break instructions.
2000 * gencode.c (build_instruction): Ditto.
2001 * interp.c (signal_exception): Code moved from here. Non-
72f4393d 2002 reserved instructions now use exception vector, rather
c906108c
SS		 2003 than halting sim.
2004 * sim-main.h: Moved magic constants to here.
2005
2006Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
2007
2008 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
2009 register upon non-zero interrupt event level, clear upon zero
2010 event value.
2011 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
2012 by passing zero event value.
2013 (*_io_{read,write}_buffer): Endianness fixes.
2014 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
2015 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
2016
2017 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
2018 serial I/O and timer module at base address 0xFFFF0000.
72f4393d 2019
c906108c
SS		 2020Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
2021
72f4393d 2022 * mips.igen (SWC1) : Correct the handling of ReverseEndian
c906108c
SS		 2023 and BigEndianCPU.
2024
2025Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
2026
2027 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
2028 parts.
2029 * configure: Update.
2030
2031Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
2032
2033 * dv-tx3904tmr.c: New file - implements tx3904 timer.
2034 * dv-tx3904{irc,cpu}.c: Mild reformatting.
2035 * configure.in: Include tx3904tmr in hw_device list.
2036 * configure: Rebuilt.
2037 * interp.c (sim_open): Instantiate three timer instances.
2038 Fix address typo of tx3904irc instance.
2039
2040Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
2041
2042 * interp.c (signal_exception): SystemCall exception now uses
2043 the exception vector.
2044
2045Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
2046
2047 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
2048 to allay warnings.
2049
2050Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2051
2052 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
2053
2054Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
2055
2056 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
2057
2058 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
2059 sim-main.h. Declare a struct hw_descriptor instead of struct
2060 hw_device_descriptor.
2061
2062Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
2063
2064 * mips.igen (do_store_left, do_load_left): Compute nr of left and
2065 right bits and then re-align left hand bytes to correct byte
2066 lanes. Fix incorrect computation in do_store_left when loading
2067 bytes from second word.
2068
2069Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2070
2071 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
2072 * interp.c (sim_open): Only create a device tree when HW is
2073 enabled.
2074
2075 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
2076 * interp.c (signal_exception): Ditto.
2077
2078Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
2079
2080 * gencode.c: Mark BEGEZALL as LIKELY.
2081
2082Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
2083
2084 * sim-main.h (ALU32_END): Sign extend 32 bit results.
2085 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
72f4393d 2086
c906108c
SS		 2087Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
2088
2089 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
2090 modules. Recognize TX39 target with "mips*tx39" pattern.
2091 * configure: Rebuilt.
2092 * sim-main.h (*): Added many macros defining bits in
2093 TX39 control registers.
2094 (SignalInterrupt): Send actual PC instead of NULL.
2095 (SignalNMIReset): New exception type.
2096 * interp.c (board): New variable for future use to identify
2097 a particular board being simulated.
2098 (mips_option_handler,mips_options): Added "--board" option.
2099 (interrupt_event): Send actual PC.
2100 (sim_open): Make memory layout conditional on board setting.
2101 (signal_exception): Initial implementation of hardware interrupt
2102 handling. Accept another break instruction variant for simulator
2103 exit.
2104 (decode_coproc): Implement RFE instruction for TX39.
2105 (mips.igen): Decode RFE instruction as such.
2106 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
2107 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
2108 bbegin to implement memory map.
2109 * dv-tx3904cpu.c: New file.
2110 * dv-tx3904irc.c: New file.
2111
2112Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
2113
2114 * mips.igen (check_mt_hilo): Create a separate r3900 version.
2115
2116Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
2117
2118 * tx.igen (madd,maddu): Replace calls to check_op_hilo
2119 with calls to check_div_hilo.
2120
2121Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
2122
2123 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
2124 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
72f4393d 2125 Add special r3900 version of do_mult_hilo.
c906108c
SS		 2126 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
2127 with calls to check_mult_hilo.
2128 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
2129 with calls to check_div_hilo.
2130
2131Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
2132
2133 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
2134 Document a replacement.
2135
2136Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
2137
2138 * interp.c (sim_monitor): Make mon_printf work.
2139
2140Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
2141
2142 * sim-main.h (INSN_NAME): New arg `cpu'.
2143
2144Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
2145
72f4393d 2146 * configure: Regenerated to track ../common/aclocal.m4 changes.
c906108c
SS		 2147
2148Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
2149
2150 * configure: Regenerated to track ../common/aclocal.m4 changes.
2151 * config.in: Ditto.
2152
2153Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
2154
2155 * acconfig.h: New file.
2156 * configure.in: Reverted change of Apr 24; use sinclude again.
2157
2158Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
2159
2160 * configure: Regenerated to track ../common/aclocal.m4 changes.
2161 * config.in: Ditto.
2162
2163Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
2164
2165 * configure.in: Don't call sinclude.
2166
2167Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
2168
2169 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
2170
2171Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2172
2173 * mips.igen (ERET): Implement.
2174
2175 * interp.c (decode_coproc): Return sign-extended EPC.
2176
2177 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
2178
2179 * interp.c (signal_exception): Do not ignore Trap.
2180 (signal_exception): On TRAP, restart at exception address.
2181 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
2182 (signal_exception): Update.
2183 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
2184 so that TRAP instructions are caught.
2185
2186Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
2187
2188 * sim-main.h (struct hilo_access, struct hilo_history): Define,
2189 contains HI/LO access history.
2190 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
2191 (HIACCESS, LOACCESS): Delete, replace with
2192 (HIHISTORY, LOHISTORY): New macros.
2193 (CHECKHILO): Delete all, moved to mips.igen
72f4393d 2194
c906108c
SS		 2195 * gencode.c (build_instruction): Do not generate checks for
2196 correct HI/LO register usage.
2197
2198 * interp.c (old_engine_run): Delete checks for correct HI/LO
2199 register usage.
2200
2201 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
2202 check_mf_cycles): New functions.
2203 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
2204 do_divu, domultx, do_mult, do_multu): Use.
2205
2206 * tx.igen ("madd", "maddu"): Use.
72f4393d 2207
c906108c
SS		 2208Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
2209
2210 * mips.igen (DSRAV): Use function do_dsrav.
2211 (SRAV): Use new function do_srav.
2212
2213 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
2214 (B): Sign extend 11 bit immediate.
2215 (EXT-B*): Shift 16 bit immediate left by 1.
2216 (ADDIU*): Don't sign extend immediate value.
2217
2218Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2219
2220 * m16run.c (sim_engine_run): Restore CIA after handling an event.
2221
2222 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
2223 functions.
2224
2225 * mips.igen (delayslot32, nullify_next_insn): New functions.
2226 (m16.igen): Always include.
2227 (do_*): Add more tracing.
2228
2229 * m16.igen (delayslot16): Add NIA argument, could be called by a
2230 32 bit MIPS16 instruction.
72f4393d 2231
c906108c
SS		 2232 * interp.c (ifetch16): Move function from here.
2233 * sim-main.c (ifetch16): To here.
72f4393d 2234
c906108c
SS		 2235 * sim-main.c (ifetch16, ifetch32): Update to match current
2236 implementations of LH, LW.
2237 (signal_exception): Don't print out incorrect hex value of illegal
2238 instruction.
2239
2240Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2241
2242 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
2243 instruction.
2244
2245 * m16.igen: Implement MIPS16 instructions.
72f4393d 2246
c906108c
SS		 2247 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
2248 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
2249 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
2250 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
2251 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
2252 bodies of corresponding code from 32 bit insn to these. Also used
2253 by MIPS16 versions of functions.
72f4393d 2254
c906108c
SS		 2255 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
2256 (IMEM16): Drop NR argument from macro.
2257
2258Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2259
2260 * Makefile.in (SIM_OBJS): Add sim-main.o.
2261
2262 * sim-main.h (address_translation, load_memory, store_memory,
2263 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
2264 as INLINE_SIM_MAIN.
2265 (pr_addr, pr_uword64): Declare.
2266 (sim-main.c): Include when H_REVEALS_MODULE_P.
72f4393d 2267
c906108c
SS		 2268 * interp.c (address_translation, load_memory, store_memory,
2269 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
2270 from here.
2271 * sim-main.c: To here. Fix compilation problems.
72f4393d 2272
c906108c
SS		 2273 * configure.in: Enable inlining.
2274 * configure: Re-config.
2275
2276Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2277
2278 * configure: Regenerated to track ../common/aclocal.m4 changes.
2279
2280Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2281
2282 * mips.igen: Include tx.igen.
2283 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
2284 * tx.igen: New file, contains MADD and MADDU.
2285
2286 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
2287 the hardwired constant `7'.
2288 (store_memory): Ditto.
2289 (LOADDRMASK): Move definition to sim-main.h.
2290
2291 mips.igen (MTC0): Enable for r3900.
2292 (ADDU): Add trace.
2293
2294 mips.igen (do_load_byte): Delete.
2295 (do_load, do_store, do_load_left, do_load_write, do_store_left,
2296 do_store_right): New functions.
2297 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
2298
2299 configure.in: Let the tx39 use igen again.
2300 configure: Update.
72f4393d 2301
c906108c
SS		 2302Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2303
2304 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
2305 not an address sized quantity. Return zero for cache sizes.
2306
2307Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
2308
2309 * mips.igen (r3900): r3900 does not support 64 bit integer
2310 operations.
2311
2312Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
2313
2314 * configure.in (mipstx39*-*-*): Use gencode simulator rather
2315 than igen one.
2316 * configure : Rebuild.
72f4393d 2317
c906108c
SS		 2318Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
2319
2320 * configure: Regenerated to track ../common/aclocal.m4 changes.
2321
2322Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2323
2324 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
2325
2326Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
2327
2328 * configure: Regenerated to track ../common/aclocal.m4 changes.
2329 * config.in: Regenerated to track ../common/aclocal.m4 changes.
2330
2331Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2332
2333 * configure: Regenerated to track ../common/aclocal.m4 changes.
2334
2335Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
2336
2337 * interp.c (Max, Min): Comment out functions. Not yet used.
2338
2339Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
2340
2341 * configure: Regenerated to track ../common/aclocal.m4 changes.
2342
2343Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
2344
2345 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
2346 configurable settings for stand-alone simulator.
72f4393d 2347
c906108c 2348 * configure.in: Added X11 search, just in case.
72f4393d 2349
c906108c
SS		 2350 * configure: Regenerated.
2351
2352Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
2353
2354 * interp.c (sim_write, sim_read, load_memory, store_memory):
2355 Replace sim_core_*_map with read_map, write_map, exec_map resp.
2356
2357Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
2358
2359 * sim-main.h (GETFCC): Return an unsigned value.
2360
2361Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2362
2363 * mips.igen (DIV): Fix check for -1 / MIN_INT.
2364 (DADD): Result destination is RD not RT.
2365
2366Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2367
2368 * sim-main.h (HIACCESS, LOACCESS): Always define.
2369
2370 * mdmx.igen (Maxi, Mini): Rename Max, Min.
2371
2372 * interp.c (sim_info): Delete.
2373
2374Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
2375
2376 * interp.c (DECLARE_OPTION_HANDLER): Use it.
2377 (mips_option_handler): New argument `cpu'.
2378 (sim_open): Update call to sim_add_option_table.
2379
2380Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
2381
2382 * mips.igen (CxC1): Add tracing.
2383
2384Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
2385
2386 * sim-main.h (Max, Min): Declare.
2387
2388 * interp.c (Max, Min): New functions.
2389
2390 * mips.igen (BC1): Add tracing.
72f4393d 2391
c906108c 2392Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
72f4393d 2393
c906108c 2394 * interp.c Added memory map for stack in vr4100
72f4393d 2395
c906108c
SS		 2396Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
2397
2398 * interp.c (load_memory): Add missing "break"'s.
2399
2400Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2401
2402 * interp.c (sim_store_register, sim_fetch_register): Pass in
2403 length parameter. Return -1.
2404
2405Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
2406
2407 * interp.c: Added hardware init hook, fixed warnings.
2408
2409Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2410
2411 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
2412
2413Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
2414
2415 * interp.c (ifetch16): New function.
2416
2417 * sim-main.h (IMEM32): Rename IMEM.
2418 (IMEM16_IMMED): Define.
2419 (IMEM16): Define.
2420 (DELAY_SLOT): Update.
72f4393d 2421
c906108c 2422 * m16run.c (sim_engine_run): New file.
72f4393d 2423
c906108c
SS		 2424 * m16.igen: All instructions except LB.
2425 (LB): Call do_load_byte.
2426 * mips.igen (do_load_byte): New function.
2427 (LB): Call do_load_byte.
2428
2429 * mips.igen: Move spec for insn bit size and high bit from here.
2430 * Makefile.in (tmp-igen, tmp-m16): To here.
2431
2432 * m16.dc: New file, decode mips16 instructions.
2433
2434 * Makefile.in (SIM_NO_ALL): Define.
2435 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
2436
2437Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
2438
2439 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
2440 point unit to 32 bit registers.
2441 * configure: Re-generate.
2442
2443Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2444
2445 * configure.in (sim_use_gen): Make IGEN the default simulator
2446 generator for generic 32 and 64 bit mips targets.
2447 * configure: Re-generate.
2448
2449Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2450
2451 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
2452 bitsize.
2453
2454 * interp.c (sim_fetch_register, sim_store_register): Read/write
2455 FGR from correct location.
2456 (sim_open): Set size of FGR's according to
2457 WITH_TARGET_FLOATING_POINT_BITSIZE.
72f4393d 2458
c906108c
SS		 2459 * sim-main.h (FGR): Store floating point registers in a separate
2460 array.
2461
2462Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
2463
2464 * configure: Regenerated to track ../common/aclocal.m4 changes.
2465
2466Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2467
2468 * interp.c (ColdReset): Call PENDING_INVALIDATE.
2469
2470 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
2471
2472 * interp.c (pending_tick): New function. Deliver pending writes.
2473
2474 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2475 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2476 it can handle mixed sized quantites and single bits.
72f4393d 2477
c906108c
SS		 2478Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2479
2480 * interp.c (oengine.h): Do not include when building with IGEN.
2481 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2482 (sim_info): Ditto for PROCESSOR_64BIT.
2483 (sim_monitor): Replace ut_reg with unsigned_word.
2484 (*): Ditto for t_reg.
2485 (LOADDRMASK): Define.
2486 (sim_open): Remove defunct check that host FP is IEEE compliant,
2487 using software to emulate floating point.
2488 (value_fpr, ...): Always compile, was conditional on HASFPU.
2489
2490Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2491
2492 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2493 size.
2494
2495 * interp.c (SD, CPU): Define.
2496 (mips_option_handler): Set flags in each CPU.
2497 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2498 (sim_close): Do not clear STATE, deleted anyway.
2499 (sim_write, sim_read): Assume CPU zero's vm should be used for
2500 data transfers.
2501 (sim_create_inferior): Set the PC for all processors.
2502 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2503 argument.
2504 (mips16_entry): Pass correct nr of args to store_word, load_word.
2505 (ColdReset): Cold reset all cpu's.
2506 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2507 (sim_monitor, load_memory, store_memory, signal_exception): Use
2508 `CPU' instead of STATE_CPU.
2509
2510
2511 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2512 SD or CPU_.
72f4393d 2513
c906108c
SS		 2514 * sim-main.h (signal_exception): Add sim_cpu arg.
2515 (SignalException*): Pass both SD and CPU to signal_exception.
2516 * interp.c (signal_exception): Update.
72f4393d 2517
c906108c
SS		 2518 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2519 Ditto
2520 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2521 address_translation): Ditto
2522 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
72f4393d 2523
c906108c
SS		 2524Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2525
2526 * configure: Regenerated to track ../common/aclocal.m4 changes.
2527
2528Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2529
2530 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2531
72f4393d 2532 * mips.igen (model): Map processor names onto BFD name.
c906108c
SS		 2533
2534 * sim-main.h (CPU_CIA): Delete.
2535 (SET_CIA, GET_CIA): Define
2536
2537Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2538
2539 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2540 regiser.
2541
2542 * configure.in (default_endian): Configure a big-endian simulator
2543 by default.
2544 * configure: Re-generate.
72f4393d 2545
c906108c
SS		 2546Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2547
2548 * configure: Regenerated to track ../common/aclocal.m4 changes.
2549
2550Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2551
2552 * interp.c (sim_monitor): Handle Densan monitor outbyte
2553 and inbyte functions.
2554
25551997-12-29 Felix Lee <flee@cygnus.com>
2556
2557 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2558
2559Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2560
2561 * Makefile.in (tmp-igen): Arrange for $zero to always be
2562 reset to zero after every instruction.
2563
2564Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2565
2566 * configure: Regenerated to track ../common/aclocal.m4 changes.
2567 * config.in: Ditto.
2568
2569Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2570
2571 * mips.igen (MSUB): Fix to work like MADD.
2572 * gencode.c (MSUB): Similarly.
2573
2574Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2575
2576 * configure: Regenerated to track ../common/aclocal.m4 changes.
2577
2578Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2579
2580 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2581
2582Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2583
2584 * sim-main.h (sim-fpu.h): Include.
2585
2586 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2587 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2588 using host independant sim_fpu module.
2589
2590Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2591
2592 * interp.c (signal_exception): Report internal errors with SIGABRT
2593 not SIGQUIT.
2594
2595 * sim-main.h (C0_CONFIG): New register.
2596 (signal.h): No longer include.
2597
2598 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2599
2600Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2601
2602 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2603
2604Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2605
2606 * mips.igen: Tag vr5000 instructions.
2607 (ANDI): Was missing mipsIV model, fix assembler syntax.
2608 (do_c_cond_fmt): New function.
2609 (C.cond.fmt): Handle mips I-III which do not support CC field
2610 separatly.
2611 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2612 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2613 in IV3.2 spec.
2614 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2615 vr5000 which saves LO in a GPR separatly.
72f4393d 2616
c906108c
SS		 2617 * configure.in (enable-sim-igen): For vr5000, select vr5000
2618 specific instructions.
2619 * configure: Re-generate.
72f4393d 2620
c906108c
SS		 2621Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2622
2623 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2624
2625 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2626 fmt_uninterpreted_64 bit cases to switch. Convert to
2627 fmt_formatted,
2628
2629 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2630
2631 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2632 as specified in IV3.2 spec.
2633 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2634
2635Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2636
2637 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2638 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2639 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2640 PENDING_FILL versions of instructions. Simplify.
2641 (X): New function.
2642 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2643 instructions.
2644 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2645 a signed value.
2646 (MTHI, MFHI): Disable code checking HI-LO.
72f4393d 2647
c906108c
SS		 2648 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2649 global.
2650 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2651
2652Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2653
2654 * gencode.c (build_mips16_operands): Replace IPC with cia.
2655
2656 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2657 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2658 IPC to `cia'.
2659 (UndefinedResult): Replace function with macro/function
2660 combination.
2661 (sim_engine_run): Don't save PC in IPC.
2662
2663 * sim-main.h (IPC): Delete.
2664
2665
2666 * interp.c (signal_exception, store_word, load_word,
2667 address_translation, load_memory, store_memory, cache_op,
2668 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2669 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2670 current instruction address - cia - argument.
2671 (sim_read, sim_write): Call address_translation directly.
2672 (sim_engine_run): Rename variable vaddr to cia.
2673 (signal_exception): Pass cia to sim_monitor
72f4393d 2674
c906108c
SS		 2675 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2676 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2677 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2678
2679 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2680 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2681 SIM_ASSERT.
72f4393d 2682
c906108c
SS		 2683 * interp.c (signal_exception): Pass restart address to
2684 sim_engine_restart.
2685
2686 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2687 idecode.o): Add dependency.
2688
2689 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2690 Delete definitions
2691 (DELAY_SLOT): Update NIA not PC with branch address.
2692 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2693
2694 * mips.igen: Use CIA not PC in branch calculations.
2695 (illegal): Call SignalException.
2696 (BEQ, ADDIU): Fix assembler.
2697
2698Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2699
2700 * m16.igen (JALX): Was missing.
2701
2702 * configure.in (enable-sim-igen): New configuration option.
2703 * configure: Re-generate.
72f4393d 2704
c906108c
SS		 2705 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2706
2707 * interp.c (load_memory, store_memory): Delete parameter RAW.
2708 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2709 bypassing {load,store}_memory.
2710
2711 * sim-main.h (ByteSwapMem): Delete definition.
2712
2713 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2714
2715 * interp.c (sim_do_command, sim_commands): Delete mips specific
2716 commands. Handled by module sim-options.
72f4393d 2717
c906108c
SS		 2718 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2719 (WITH_MODULO_MEMORY): Define.
2720
2721 * interp.c (sim_info): Delete code printing memory size.
2722
2723 * interp.c (mips_size): Nee sim_size, delete function.
2724 (power2): Delete.
2725 (monitor, monitor_base, monitor_size): Delete global variables.
2726 (sim_open, sim_close): Delete code creating monitor and other
2727 memory regions. Use sim-memopts module, via sim_do_commandf, to
2728 manage memory regions.
2729 (load_memory, store_memory): Use sim-core for memory model.
72f4393d 2730
c906108c
SS		 2731 * interp.c (address_translation): Delete all memory map code
2732 except line forcing 32 bit addresses.
2733
2734Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2735
2736 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2737 trace options.
2738
2739 * interp.c (logfh, logfile): Delete globals.
2740 (sim_open, sim_close): Delete code opening & closing log file.
2741 (mips_option_handler): Delete -l and -n options.
2742 (OPTION mips_options): Ditto.
2743
2744 * interp.c (OPTION mips_options): Rename option trace to dinero.
2745 (mips_option_handler): Update.
2746
2747Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2748
2749 * interp.c (fetch_str): New function.
2750 (sim_monitor): Rewrite using sim_read & sim_write.
2751 (sim_open): Check magic number.
2752 (sim_open): Write monitor vectors into memory using sim_write.
2753 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2754 (sim_read, sim_write): Simplify - transfer data one byte at a
2755 time.
2756 (load_memory, store_memory): Clarify meaning of parameter RAW.
2757
2758 * sim-main.h (isHOST): Defete definition.
2759 (isTARGET): Mark as depreciated.
2760 (address_translation): Delete parameter HOST.
2761
2762 * interp.c (address_translation): Delete parameter HOST.
2763
2764Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2765
72f4393d 2766 * mips.igen:
c906108c
SS		 2767
2768 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2769 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2770
2771Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2772
2773 * mips.igen: Add model filter field to records.
2774
2775Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2776
2777 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
72f4393d 2778
c906108c
SS		 2779 interp.c (sim_engine_run): Do not compile function sim_engine_run
2780 when WITH_IGEN == 1.
2781
2782 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2783 target architecture.
2784
2785 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2786 igen. Replace with configuration variables sim_igen_flags /
2787 sim_m16_flags.
2788
2789 * m16.igen: New file. Copy mips16 insns here.
2790 * mips.igen: From here.
2791
2792Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2793
2794 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2795 to top.
2796 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2797
2798Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2799
2800 * gencode.c (build_instruction): Follow sim_write's lead in using
2801 BigEndianMem instead of !ByteSwapMem.
2802
2803Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2804
2805 * configure.in (sim_gen): Dependent on target, select type of
2806 generator. Always select old style generator.
2807
2808 configure: Re-generate.
2809
2810 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2811 targets.
2812 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2813 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2814 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2815 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2816 SIM_@sim_gen@_*, set by autoconf.
72f4393d 2817
c906108c
SS		 2818Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2819
2820 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2821
2822 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2823 CURRENT_FLOATING_POINT instead.
2824
2825 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2826 (address_translation): Raise exception InstructionFetch when
2827 translation fails and isINSTRUCTION.
72f4393d 2828
c906108c
SS		 2829 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2830 sim_engine_run): Change type of of vaddr and paddr to
2831 address_word.
2832 (address_translation, prefetch, load_memory, store_memory,
2833 cache_op): Change type of vAddr and pAddr to address_word.
2834
2835 * gencode.c (build_instruction): Change type of vaddr and paddr to
2836 address_word.
2837
2838Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2839
2840 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2841 macro to obtain result of ALU op.
2842
2843Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2844
2845 * interp.c (sim_info): Call profile_print.
2846
2847Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2848
2849 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2850
2851 * sim-main.h (WITH_PROFILE): Do not define, defined in
2852 common/sim-config.h. Use sim-profile module.
2853 (simPROFILE): Delete defintion.
2854
2855 * interp.c (PROFILE): Delete definition.
2856 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2857 (sim_close): Delete code writing profile histogram.
2858 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2859 Delete.
2860 (sim_engine_run): Delete code profiling the PC.
2861
2862Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2863
2864 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2865
2866 * interp.c (sim_monitor): Make register pointers of type
2867 unsigned_word*.
2868
2869 * sim-main.h: Make registers of type unsigned_word not
2870 signed_word.
2871
2872Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2873
2874 * interp.c (sync_operation): Rename from SyncOperation, make
2875 global, add SD argument.
2876 (prefetch): Rename from Prefetch, make global, add SD argument.
2877 (decode_coproc): Make global.
2878
2879 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2880
2881 * gencode.c (build_instruction): Generate DecodeCoproc not
2882 decode_coproc calls.
2883
2884 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2885 (SizeFGR): Move to sim-main.h
2886 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2887 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2888 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2889 sim-main.h.
2890 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2891 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2892 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2893 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2894 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2895 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
72f4393d 2896
c906108c
SS		 2897 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2898 exception.
2899 (sim-alu.h): Include.
2900 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2901 (sim_cia): Typedef to instruction_address.
72f4393d 2902
c906108c
SS		 2903Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2904
2905 * Makefile.in (interp.o): Rename generated file engine.c to
2906 oengine.c.
72f4393d 2907
c906108c 2908 * interp.c: Update.
72f4393d 2909
c906108c
SS		 2910Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2911
2912 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
72f4393d 2913
c906108c
SS		 2914Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2915
2916 * gencode.c (build_instruction): For "FPSQRT", output correct
2917 number of arguments to Recip.
72f4393d 2918
c906108c
SS		 2919Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2920
2921 * Makefile.in (interp.o): Depends on sim-main.h
2922
2923 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2924
2925 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2926 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2927 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2928 STATE, DSSTATE): Define
2929 (GPR, FGRIDX, ..): Define.
2930
2931 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2932 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2933 (GPR, FGRIDX, ...): Delete macros.
72f4393d 2934
c906108c 2935 * interp.c: Update names to match defines from sim-main.h
72f4393d 2936
c906108c
SS		 2937Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2938
2939 * interp.c (sim_monitor): Add SD argument.
2940 (sim_warning): Delete. Replace calls with calls to
2941 sim_io_eprintf.
2942 (sim_error): Delete. Replace calls with sim_io_error.
2943 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2944 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2945 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2946 argument.
2947 (mips_size): Rename from sim_size. Add SD argument.
2948
2949 * interp.c (simulator): Delete global variable.
2950 (callback): Delete global variable.
2951 (mips_option_handler, sim_open, sim_write, sim_read,
2952 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2953 sim_size,sim_monitor): Use sim_io_* not callback->*.
2954 (sim_open): ZALLOC simulator struct.
2955 (PROFILE): Do not define.
2956
2957Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2958
2959 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2960 support.h with corresponding code.
2961
2962 * sim-main.h (word64, uword64), support.h: Move definition to
2963 sim-main.h.
2964 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2965
2966 * support.h: Delete
2967 * Makefile.in: Update dependencies
2968 * interp.c: Do not include.
72f4393d 2969
c906108c
SS		 2970Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2971
2972 * interp.c (address_translation, load_memory, store_memory,
2973 cache_op): Rename to from AddressTranslation et.al., make global,
2974 add SD argument
72f4393d 2975
c906108c
SS		 2976 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2977 CacheOp): Define.
72f4393d 2978
c906108c
SS		 2979 * interp.c (SignalException): Rename to signal_exception, make
2980 global.
2981
2982 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
72f4393d 2983
c906108c
SS		 2984 * sim-main.h (SignalException, SignalExceptionInterrupt,
2985 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2986 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2987 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2988 Define.
72f4393d 2989
c906108c 2990 * interp.c, support.h: Use.
72f4393d 2991
c906108c
SS		 2992Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2993
2994 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2995 to value_fpr / store_fpr. Add SD argument.
2996 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2997 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2998
2999 * sim-main.h (ValueFPR, StoreFPR): Define.
72f4393d 3000
c906108c
SS		 3001Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
3002
3003 * interp.c (sim_engine_run): Check consistency between configure
3004 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
3005 and HASFPU.
3006
3007 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
72f4393d 3008 (mips_fpu): Configure WITH_FLOATING_POINT.
c906108c
SS		 3009 (mips_endian): Configure WITH_TARGET_ENDIAN.
3010 * configure: Update.
3011
3012Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3013
3014 * configure: Regenerated to track ../common/aclocal.m4 changes.
3015
3016Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
3017
3018 * configure: Regenerated.
3019
3020Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
3021
3022 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
3023
3024Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3025
3026 * gencode.c (print_igen_insn_models): Assume certain architectures
3027 include all mips* instructions.
3028 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
3029 instruction.
3030
3031 * Makefile.in (tmp.igen): Add target. Generate igen input from
3032 gencode file.
3033
3034 * gencode.c (FEATURE_IGEN): Define.
3035 (main): Add --igen option. Generate output in igen format.
3036 (process_instructions): Format output according to igen option.
3037 (print_igen_insn_format): New function.
3038 (print_igen_insn_models): New function.
3039 (process_instructions): Only issue warnings and ignore
3040 instructions when no FEATURE_IGEN.
3041
3042Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3043
3044 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
3045 MIPS targets.
3046
3047Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3048
3049 * configure: Regenerated to track ../common/aclocal.m4 changes.
3050
3051Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
3052
3053 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
3054 SIM_RESERVED_BITS): Delete, moved to common.
3055 (SIM_EXTRA_CFLAGS): Update.
72f4393d 3056
c906108c
SS		 3057Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3058
3059 * configure.in: Configure non-strict memory alignment.
3060 * configure: Regenerated to track ../common/aclocal.m4 changes.
3061
3062Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
3063
3064 * configure: Regenerated to track ../common/aclocal.m4 changes.
3065
3066Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
3067
3068 * gencode.c (SDBBP,DERET): Added (3900) insns.
3069 (RFE): Turn on for 3900.
3070 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
3071 (dsstate): Made global.
3072 (SUBTARGET_R3900): Added.
3073 (CANCELDELAYSLOT): New.
3074 (SignalException): Ignore SystemCall rather than ignore and
3075 terminate. Add DebugBreakPoint handling.
3076 (decode_coproc): New insns RFE, DERET; and new registers Debug
3077 and DEPC protected by SUBTARGET_R3900.
3078 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
3079 bits explicitly.
3080 * Makefile.in,configure.in: Add mips subtarget option.
72f4393d 3081 * configure: Update.
c906108c
SS		 3082
3083Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
3084
3085 * gencode.c: Add r3900 (tx39).
72f4393d 3086
c906108c
SS		 3087
3088Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
3089
3090 * gencode.c (build_instruction): Don't need to subtract 4 for
3091 JALR, just 2.
3092
3093Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
3094
3095 * interp.c: Correct some HASFPU problems.
3096
3097Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
3098
3099 * configure: Regenerated to track ../common/aclocal.m4 changes.
3100
3101Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3102
3103 * interp.c (mips_options): Fix samples option short form, should
3104 be `x'.
3105
3106Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
3107
3108 * interp.c (sim_info): Enable info code. Was just returning.
3109
3110Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3111
3112 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
3113 MFC0.
3114
3115Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
3116
3117 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
3118 constants.
3119 (build_instruction): Ditto for LL.
3120
3121Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
3122
3123 * configure: Regenerated to track ../common/aclocal.m4 changes.
3124
3125Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3126
3127 * configure: Regenerated to track ../common/aclocal.m4 changes.
3128 * config.in: Ditto.
3129
3130Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
3131
3132 * interp.c (sim_open): Add call to sim_analyze_program, update
3133 call to sim_config.
3134
3135Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
3136
3137 * interp.c (sim_kill): Delete.
3138 (sim_create_inferior): Add ABFD argument. Set PC from same.
3139 (sim_load): Move code initializing trap handlers from here.
3140 (sim_open): To here.
3141 (sim_load): Delete, use sim-hload.c.
3142
3143 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
3144
3145Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3146
3147 * configure: Regenerated to track ../common/aclocal.m4 changes.
3148 * config.in: Ditto.
3149
3150Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3151
3152 * interp.c (sim_open): Add ABFD argument.
3153 (sim_load): Move call to sim_config from here.
3154 (sim_open): To here. Check return status.
3155
3156Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
72f4393d 3157
c906108c
SS		 3158 * gencode.c (build_instruction): Two arg MADD should
3159 not assign result to $0.
72f4393d 3160
c906108c
SS		 3161Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
3162
3163 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
3164 * sim/mips/configure.in: Regenerate.
3165
3166Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
3167
3168 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
3169 signed8, unsigned8 et.al. types.
3170
3171 * interp.c (SUB_REG_FETCH): Handle both little and big endian
3172 hosts when selecting subreg.
3173
3174Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
3175
3176 * interp.c (sim_engine_run): Reset the ZERO register to zero
3177 regardless of FEATURE_WARN_ZERO.
3178 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
3179
3180Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
3181
3182 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
3183 (SignalException): For BreakPoints ignore any mode bits and just
3184 save the PC.
3185 (SignalException): Always set the CAUSE register.
3186
3187Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
3188
3189 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
3190 exception has been taken.
3191
3192 * interp.c: Implement the ERET and mt/f sr instructions.
3193
3194Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
3195
3196 * interp.c (SignalException): Don't bother restarting an
3197 interrupt.
3198
3199Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3200
3201 * interp.c (SignalException): Really take an interrupt.
3202 (interrupt_event): Only deliver interrupts when enabled.
3203
3204Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
3205
3206 * interp.c (sim_info): Only print info when verbose.
3207 (sim_info) Use sim_io_printf for output.
72f4393d 3208
c906108c
SS		 3209Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3210
3211 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
3212 mips architectures.
3213
3214Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3215
3216 * interp.c (sim_do_command): Check for common commands if a
3217 simulator specific command fails.
3218
3219Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
3220
3221 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
3222 and simBE when DEBUG is defined.
3223
3224Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
3225
3226 * interp.c (interrupt_event): New function. Pass exception event
3227 onto exception handler.
3228
3229 * configure.in: Check for stdlib.h.
3230 * configure: Regenerate.
3231
3232 * gencode.c (build_instruction): Add UNUSED attribute to tempS
3233 variable declaration.
3234 (build_instruction): Initialize memval1.
3235 (build_instruction): Add UNUSED attribute to byte, bigend,
3236 reverse.
3237 (build_operands): Ditto.
3238
3239 * interp.c: Fix GCC warnings.
3240 (sim_get_quit_code): Delete.
3241
3242 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
3243 * Makefile.in: Ditto.
3244 * configure: Re-generate.
72f4393d 3245
c906108c
SS		 3246 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
3247
3248Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
3249
3250 * interp.c (mips_option_handler): New function parse argumes using
3251 sim-options.
3252 (myname): Replace with STATE_MY_NAME.
3253 (sim_open): Delete check for host endianness - performed by
3254 sim_config.
3255 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
3256 (sim_open): Move much of the initialization from here.
3257 (sim_load): To here. After the image has been loaded and
3258 endianness set.
3259 (sim_open): Move ColdReset from here.
3260 (sim_create_inferior): To here.
3261 (sim_open): Make FP check less dependant on host endianness.
3262
3263 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
3264 run.
3265 * interp.c (sim_set_callbacks): Delete.
3266
3267 * interp.c (membank, membank_base, membank_size): Replace with
3268 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
3269 (sim_open): Remove call to callback->init. gdb/run do this.
3270
3271 * interp.c: Update
3272
3273 * sim-main.h (SIM_HAVE_FLATMEM): Define.
3274
3275 * interp.c (big_endian_p): Delete, replaced by
3276 current_target_byte_order.
3277
3278Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3279
3280 * interp.c (host_read_long, host_read_word, host_swap_word,
3281 host_swap_long): Delete. Using common sim-endian.
3282 (sim_fetch_register, sim_store_register): Use H2T.
3283 (pipeline_ticks): Delete. Handled by sim-events.
3284 (sim_info): Update.
3285 (sim_engine_run): Update.
3286
3287Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
3288
3289 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
3290 reason from here.
3291 (SignalException): To here. Signal using sim_engine_halt.
3292 (sim_stop_reason): Delete, moved to common.
72f4393d 3293
c906108c
SS		 3294Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
3295
3296 * interp.c (sim_open): Add callback argument.
3297 (sim_set_callbacks): Delete SIM_DESC argument.
3298 (sim_size): Ditto.
3299
3300Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3301
3302 * Makefile.in (SIM_OBJS): Add common modules.
3303
3304 * interp.c (sim_set_callbacks): Also set SD callback.
3305 (set_endianness, xfer_*, swap_*): Delete.
3306 (host_read_word, host_read_long, host_swap_word, host_swap_long):
3307 Change to functions using sim-endian macros.
3308 (control_c, sim_stop): Delete, use common version.
3309 (simulate): Convert into.
3310 (sim_engine_run): This function.
3311 (sim_resume): Delete.
72f4393d 3312
c906108c
SS		 3313 * interp.c (simulation): New variable - the simulator object.
3314 (sim_kind): Delete global - merged into simulation.
3315 (sim_load): Cleanup. Move PC assignment from here.
3316 (sim_create_inferior): To here.
3317
3318 * sim-main.h: New file.
3319 * interp.c (sim-main.h): Include.
72f4393d 3320
c906108c
SS		 3321Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
3322
3323 * configure: Regenerated to track ../common/aclocal.m4 changes.
3324
3325Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
3326
3327 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
3328
3329Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
3330
72f4393d
L		 3331 * gencode.c (build_instruction): DIV instructions: check
3332 for division by zero and integer overflow before using
c906108c
SS		 3333 host's division operation.
3334
3335Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
3336
3337 * Makefile.in (SIM_OBJS): Add sim-load.o.
3338 * interp.c: #include bfd.h.
3339 (target_byte_order): Delete.
3340 (sim_kind, myname, big_endian_p): New static locals.
3341 (sim_open): Set sim_kind, myname. Move call to set_endianness to
3342 after argument parsing. Recognize -E arg, set endianness accordingly.
3343 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
3344 load file into simulator. Set PC from bfd.
3345 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
3346 (set_endianness): Use big_endian_p instead of target_byte_order.
3347
3348Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
3349
3350 * interp.c (sim_size): Delete prototype - conflicts with
3351 definition in remote-sim.h. Correct definition.
3352
3353Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3354
3355 * configure: Regenerated to track ../common/aclocal.m4 changes.
3356 * config.in: Ditto.
3357
3358Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
3359
3360 * interp.c (sim_open): New arg `kind'.
3361
3362 * configure: Regenerated to track ../common/aclocal.m4 changes.
3363
3364Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3365
3366 * configure: Regenerated to track ../common/aclocal.m4 changes.
3367
3368Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
3369
3370 * interp.c (sim_open): Set optind to 0 before calling getopt.
3371
3372Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3373
3374 * configure: Regenerated to track ../common/aclocal.m4 changes.
3375
3376Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
3377
3378 * interp.c : Replace uses of pr_addr with pr_uword64
3379 where the bit length is always 64 independent of SIM_ADDR.
3380 (pr_uword64) : added.
3381
3382Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3383
3384 * configure: Re-generate.
3385
3386Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
3387
3388 * configure: Regenerate to track ../common/aclocal.m4 changes.
3389
3390Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
3391
3392 * interp.c (sim_open): New SIM_DESC result. Argument is now
3393 in argv form.
3394 (other sim_*): New SIM_DESC argument.
3395
3396Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
3397
3398 * interp.c: Fix printing of addresses for non-64-bit targets.
3399 (pr_addr): Add function to print address based on size.
3400
3401Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
3402
3403 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
3404
3405Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
3406
3407 * gencode.c (build_mips16_operands): Correct computation of base
3408 address for extended PC relative instruction.
3409
3410Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
3411
3412 * interp.c (mips16_entry): Add support for floating point cases.
3413 (SignalException): Pass floating point cases to mips16_entry.
3414 (ValueFPR): Don't restrict fmt_single and fmt_word to even
3415 registers.
3416 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
3417 or fmt_word.
3418 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
3419 and then set the state to fmt_uninterpreted.
3420 (COP_SW): Temporarily set the state to fmt_word while calling
3421 ValueFPR.
3422
3423Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
3424
3425 * gencode.c (build_instruction): The high order may be set in the
3426 comparison flags at any ISA level, not just ISA 4.
3427
3428Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
3429
3430 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
3431 COMMON_{PRE,POST}_CONFIG_FRAG instead.
3432 * configure.in: sinclude ../common/aclocal.m4.
3433 * configure: Regenerated.
3434
3435Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
3436
3437 * configure: Rebuild after change to aclocal.m4.
3438
3439Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
3440
3441 * configure configure.in Makefile.in: Update to new configure
3442 scheme which is more compatible with WinGDB builds.
3443 * configure.in: Improve comment on how to run autoconf.
3444 * configure: Re-run autoconf to get new ../common/aclocal.m4.
3445 * Makefile.in: Use autoconf substitution to install common
3446 makefile fragment.
3447
3448Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
3449
3450 * gencode.c (build_instruction): Use BigEndianCPU instead of
3451 ByteSwapMem.
3452
3453Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
3454
3455 * interp.c (sim_monitor): Make output to stdout visible in
3456 wingdb's I/O log window.
3457
3458Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
3459
3460 * support.h: Undo previous change to SIGTRAP
3461 and SIGQUIT values.
3462
3463Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
3464
3465 * interp.c (store_word, load_word): New static functions.
3466 (mips16_entry): New static function.
3467 (SignalException): Look for mips16 entry and exit instructions.
3468 (simulate): Use the correct index when setting fpr_state after
3469 doing a pending move.
3470
3471Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
3472
3473 * interp.c: Fix byte-swapping code throughout to work on
3474 both little- and big-endian hosts.
3475
3476Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
3477
3478 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3479 with gdb/config/i386/xm-windows.h.
3480
3481Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
3482
3483 * gencode.c (build_instruction): Work around MSVC++ code gen bug
3484 that messes up arithmetic shifts.
3485
3486Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
3487
3488 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
3489 SIGTRAP and SIGQUIT for _WIN32.
3490
3491Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3492
3493 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3494 force a 64 bit multiplication.
3495 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3496 destination register is 0, since that is the default mips16 nop
3497 instruction.
3498
3499Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3500
3501 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3502 (build_endian_shift): Don't check proc64.
3503 (build_instruction): Always set memval to uword64. Cast op2 to
3504 uword64 when shifting it left in memory instructions. Always use
3505 the same code for stores--don't special case proc64.
3506
3507 * gencode.c (build_mips16_operands): Fix base PC value for PC
3508 relative operands.
3509 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3510 jal instruction.
3511 * interp.c (simJALDELAYSLOT): Define.
3512 (JALDELAYSLOT): Define.
3513 (INDELAYSLOT, INJALDELAYSLOT): Define.
3514 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3515
3516Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3517
3518 * interp.c (sim_open): add flush_cache as a PMON routine
3519 (sim_monitor): handle flush_cache by ignoring it
3520
3521Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3522
3523 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3524 BigEndianMem.
3525 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3526 (BigEndianMem): Rename to ByteSwapMem and change sense.
3527 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3528 BigEndianMem references to !ByteSwapMem.
3529 (set_endianness): New function, with prototype.
3530 (sim_open): Call set_endianness.
3531 (sim_info): Use simBE instead of BigEndianMem.
3532 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3533 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3534 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3535 ifdefs, keeping the prototype declaration.
3536 (swap_word): Rewrite correctly.
3537 (ColdReset): Delete references to CONFIG. Delete endianness related
3538 code; moved to set_endianness.
72f4393d 3539
c906108c
SS		 3540Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3541
3542 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3543 * interp.c (CHECKHILO): Define away.
3544 (simSIGINT): New macro.
3545 (membank_size): Increase from 1MB to 2MB.
3546 (control_c): New function.
3547 (sim_resume): Rename parameter signal to signal_number. Add local
3548 variable prev. Call signal before and after simulate.
3549 (sim_stop_reason): Add simSIGINT support.
3550 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3551 functions always.
3552 (sim_warning): Delete call to SignalException. Do call printf_filtered
3553 if logfh is NULL.
3554 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3555 a call to sim_warning.
3556
3557Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3558
3559 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3560 16 bit instructions.
3561
3562Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3563
3564 Add support for mips16 (16 bit MIPS implementation):
3565 * gencode.c (inst_type): Add mips16 instruction encoding types.
3566 (GETDATASIZEINSN): Define.
3567 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3568 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3569 mtlo.
3570 (MIPS16_DECODE): New table, for mips16 instructions.
3571 (bitmap_val): New static function.
3572 (struct mips16_op): Define.
3573 (mips16_op_table): New table, for mips16 operands.
3574 (build_mips16_operands): New static function.
3575 (process_instructions): If PC is odd, decode a mips16
3576 instruction. Break out instruction handling into new
3577 build_instruction function.
3578 (build_instruction): New static function, broken out of
3579 process_instructions. Check modifiers rather than flags for SHIFT
3580 bit count and m[ft]{hi,lo} direction.
3581 (usage): Pass program name to fprintf.
3582 (main): Remove unused variable this_option_optind. Change
3583 ``*loptarg++'' to ``loptarg++''.
3584 (my_strtoul): Parenthesize && within ||.
3585 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3586 (simulate): If PC is odd, fetch a 16 bit instruction, and
3587 increment PC by 2 rather than 4.
3588 * configure.in: Add case for mips16*-*-*.
3589 * configure: Rebuild.
3590
3591Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3592
3593 * interp.c: Allow -t to enable tracing in standalone simulator.
3594 Fix garbage output in trace file and error messages.
3595
3596Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3597
3598 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3599 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3600 * configure.in: Simplify using macros in ../common/aclocal.m4.
3601 * configure: Regenerated.
3602 * tconfig.in: New file.
3603
3604Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3605
3606 * interp.c: Fix bugs in 64-bit port.
3607 Use ansi function declarations for msvc compiler.
3608 Initialize and test file pointer in trace code.
3609 Prevent duplicate definition of LAST_EMED_REGNUM.
3610
3611Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3612
3613 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3614
3615Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3616
3617 * interp.c (SignalException): Check for explicit terminating
3618 breakpoint value.
3619 * gencode.c: Pass instruction value through SignalException()
3620 calls for Trap, Breakpoint and Syscall.
3621
3622Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3623
3624 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3625 only used on those hosts that provide it.
3626 * configure.in: Add sqrt() to list of functions to be checked for.
3627 * config.in: Re-generated.
3628 * configure: Re-generated.
3629
3630Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3631
3632 * gencode.c (process_instructions): Call build_endian_shift when
3633 expanding STORE RIGHT, to fix swr.
3634 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3635 clear the high bits.
3636 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3637 Fix float to int conversions to produce signed values.
3638
3639Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3640
3641 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3642 (process_instructions): Correct handling of nor instruction.
3643 Correct shift count for 32 bit shift instructions. Correct sign
3644 extension for arithmetic shifts to not shift the number of bits in
3645 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3646 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3647 Fix madd.
3648 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3649 It's OK to have a mult follow a mult. What's not OK is to have a
3650 mult follow an mfhi.
3651 (Convert): Comment out incorrect rounding code.
3652
3653Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3654
3655 * interp.c (sim_monitor): Improved monitor printf
3656 simulation. Tidied up simulator warnings, and added "--log" option
3657 for directing warning message output.
3658 * gencode.c: Use sim_warning() rather than WARNING macro.
3659
3660Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3661
3662 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3663 getopt1.o, rather than on gencode.c. Link objects together.
3664 Don't link against -liberty.
3665 (gencode.o, getopt.o, getopt1.o): New targets.
3666 * gencode.c: Include <ctype.h> and "ansidecl.h".
3667 (AND): Undefine after including "ansidecl.h".
3668 (ULONG_MAX): Define if not defined.
3669 (OP_*): Don't define macros; now defined in opcode/mips.h.
3670 (main): Call my_strtoul rather than strtoul.
3671 (my_strtoul): New static function.
3672
3673Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3674
3675 * gencode.c (process_instructions): Generate word64 and uword64
3676 instead of `long long' and `unsigned long long' data types.
3677 * interp.c: #include sysdep.h to get signals, and define default
3678 for SIGBUS.
3679 * (Convert): Work around for Visual-C++ compiler bug with type
3680 conversion.
3681 * support.h: Make things compile under Visual-C++ by using
3682 __int64 instead of `long long'. Change many refs to long long
3683 into word64/uword64 typedefs.
3684
3685Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3686
72f4393d
L		 3687 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3688 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3689 (docdir): Removed.
3690 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3691 (AC_PROG_INSTALL): Added.
c906108c 3692 (AC_PROG_CC): Moved to before configure.host call.
72f4393d
L		 3693 * configure: Rebuilt.
3694
c906108c
SS		 3695Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3696
3697 * configure.in: Define @SIMCONF@ depending on mips target.
3698 * configure: Rebuild.
3699 * Makefile.in (run): Add @SIMCONF@ to control simulator
3700 construction.
3701 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3702 * interp.c: Remove some debugging, provide more detailed error
3703 messages, update memory accesses to use LOADDRMASK.
72f4393d 3704
c906108c
SS		 3705Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3706
3707 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3708 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3709 stamp-h.
3710 * configure: Rebuild.
3711 * config.in: New file, generated by autoheader.
3712 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3713 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3714 HAVE_ANINT and HAVE_AINT, as appropriate.
3715 * Makefile.in (run): Use @LIBS@ rather than -lm.
3716 (interp.o): Depend upon config.h.
3717 (Makefile): Just rebuild Makefile.
3718 (clean): Remove stamp-h.
3719 (mostlyclean): Make the same as clean, not as distclean.
3720 (config.h, stamp-h): New targets.
3721
3722Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3723
3724 * interp.c (ColdReset): Fix boolean test. Make all simulator
3725 globals static.
3726
3727Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3728
3729 * interp.c (xfer_direct_word, xfer_direct_long,
3730 swap_direct_word, swap_direct_long, xfer_big_word,
3731 xfer_big_long, xfer_little_word, xfer_little_long,
3732 swap_word,swap_long): Added.
3733 * interp.c (ColdReset): Provide function indirection to
3734 host<->simulated_target transfer routines.
3735 * interp.c (sim_store_register, sim_fetch_register): Updated to
3736 make use of indirected transfer routines.
3737
3738Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3739
3740 * gencode.c (process_instructions): Ensure FP ABS instruction
3741 recognised.
3742 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3743 system call support.
3744
3745Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3746
3747 * interp.c (sim_do_command): Complain if callback structure not
3748 initialised.
3749
3750Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3751
3752 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3753 support for Sun hosts.
3754 * Makefile.in (gencode): Ensure the host compiler and libraries
3755 used for cross-hosted build.
3756
3757Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3758
3759 * interp.c, gencode.c: Some more (TODO) tidying.
3760
3761Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3762
3763 * gencode.c, interp.c: Replaced explicit long long references with
3764 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3765 * support.h (SET64LO, SET64HI): Macros added.
3766
3767Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3768
3769 * configure: Regenerate with autoconf 2.7.
3770
3771Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3772
3773 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3774 * support.h: Remove superfluous "1" from #if.
3775 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3776
3777Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3778
3779 * interp.c (StoreFPR): Control UndefinedResult() call on
3780 WARN_RESULT manifest.
3781
3782Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3783
3784 * gencode.c: Tidied instruction decoding, and added FP instruction
3785 support.
3786
3787 * interp.c: Added dineroIII, and BSD profiling support. Also
3788 run-time FP handling.
3789
3790Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3791
3792 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3793 gencode.c, interp.c, support.h: created.
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