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sim: bfin: fix signed warning
[deliverable/binutils-gdb.git] / sim / mips / ChangeLog
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465fb143
MF		 12015-03-14 Mike Frysinger <vapier@gentoo.org>
2
3 * Makefile.in (SIM_RUN_OBJS): Delete.
4
5cddc23a
MF		 52015-03-14 Mike Frysinger <vapier@gentoo.org>
6
7 * configure.ac (AC_CHECK_HEADERS): Delete.
8 * aclocal.m4, configure: Regenerate.
9
2974be62
AM		 102014-08-19 Alan Modra <amodra@gmail.com>
11
12 * configure: Regenerate.
13
faa743bb
RM		 142014-08-15 Roland McGrath <mcgrathr@google.com>
15
16 * configure: Regenerate.
17 * config.in: Regenerate.
18
1a8a700e
MF		 192014-03-04 Mike Frysinger <vapier@gentoo.org>
20
21 * configure: Regenerate.
22
bf3d9781
AM		 232013-09-23 Alan Modra <amodra@gmail.com>
24
25 * configure: Regenerate.
26
31e6ad7d
MF		 272013-06-03 Mike Frysinger <vapier@gentoo.org>
28
29 * aclocal.m4, configure: Regenerate.
30
d3685d60
TT		 312013-05-10 Freddie Chopin <freddie_chopin@op.pl>
32
33 * configure: Rebuild.
34
1517bd27
MF		 352013-03-26 Mike Frysinger <vapier@gentoo.org>
36
37 * configure: Regenerate.
38
3be31516
JS		 392013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
40
41 * configure.ac: Address use of dv-sockser.o.
42 * tconfig.in: Conditionalize use of dv_sockser_install.
43 * configure: Regenerated.
44 * config.in: Regenerated.
45
37cb8f8e
SE		 462012-10-04 Chao-ying Fu <fu@mips.com>
47 Steve Ellcey <sellcey@mips.com>
48
49 * mips/mips3264r2.igen (rdhwr): New.
50
87c8644f
JS		 512012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
52
53 * configure.ac: Always link against dv-sockser.o.
54 * configure: Regenerate.
55
5f3ef9d0
JB		 562012-06-15 Joel Brobecker <brobecker@adacore.com>
57
58 * config.in, configure: Regenerate.
59
a6ff997c
NC		 602012-05-18 Nick Clifton <nickc@redhat.com>
61
62 PR 14072
63 * interp.c: Include config.h before system header files.
64
2232061b
MF		 652012-03-24 Mike Frysinger <vapier@gentoo.org>
66
67 * aclocal.m4, config.in, configure: Regenerate.
68
db2e4d67
MF		 692011-12-03 Mike Frysinger <vapier@gentoo.org>
70
71 * aclocal.m4: New file.
72 * configure: Regenerate.
73
4399a56b
MF		 742011-10-19 Mike Frysinger <vapier@gentoo.org>
75
76 * configure: Regenerate after common/acinclude.m4 update.
77
9c082ca8
MF		 782011-10-17 Mike Frysinger <vapier@gentoo.org>
79
80 * configure.ac: Change include to common/acinclude.m4.
81
6ffe910a
MF		 822011-10-17 Mike Frysinger <vapier@gentoo.org>
83
84 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
85 call. Replace common.m4 include with SIM_AC_COMMON.
86 * configure: Regenerate.
87
31b28250
HPN		 882011-07-08 Hans-Peter Nilsson <hp@axis.com>
89
3faa01e3
HPN		 90 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
91 $(SIM_EXTRA_DEPS).
92 (tmp-mach-multi): Exit early when igen fails.
31b28250 93
2419798b
MF		 942011-07-05 Mike Frysinger <vapier@gentoo.org>
95
96 * interp.c (sim_do_command): Delete.
97
d79fe0d6
MF		 982011-02-14 Mike Frysinger <vapier@gentoo.org>
99
100 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
101 (tx3904sio_fifo_reset): Likewise.
102 * interp.c (sim_monitor): Likewise.
103
5558e7e6
MF		 1042010-04-14 Mike Frysinger <vapier@gentoo.org>
105
106 * interp.c (sim_write): Add const to buffer arg.
107
35aafff4
JB		 1082010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
109
110 * interp.c: Don't include sysdep.h
111
3725885a
RW		 1122010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
113
114 * configure: Regenerate.
115
d6416cdc
RW		 1162009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
117
81ecdfbb
RW		 118 * config.in: Regenerate.
119 * configure: Likewise.
120
d6416cdc
RW		 121 * configure: Regenerate.
122
b5bd9624
HPN		 1232008-07-11 Hans-Peter Nilsson <hp@axis.com>
124
125 * configure: Regenerate to track ../common/common.m4 changes.
126 * config.in: Ditto.
127
6efef468
JM		 1282008-06-06 Vladimir Prus <vladimir@codesourcery.com>
129 Daniel Jacobowitz <dan@codesourcery.com>
130 Joseph Myers <joseph@codesourcery.com>
131
132 * configure: Regenerate.
133
60dc88db
RS		 1342007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
135
136 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
137 that unconditionally allows fmt_ps.
138 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
139 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
140 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
141 filter from 64,f to 32,f.
142 (PREFX): Change filter from 64 to 32.
143 (LDXC1, LUXC1): Provide separate mips32r2 implementations
144 that use do_load_double instead of do_load. Make both LUXC1
145 versions unpredictable if SizeFGR () != 64.
146 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
147 instead of do_store. Remove unused variable. Make both SUXC1
148 versions unpredictable if SizeFGR () != 64.
149
599ca73e
RS		 1502007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
151
152 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
153 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
154 shifts for that case.
155
2525df03
NC		 1562007-09-04 Nick Clifton <nickc@redhat.com>
157
158 * interp.c (options enum): Add OPTION_INFO_MEMORY.
159 (display_mem_info): New static variable.
160 (mips_option_handler): Handle OPTION_INFO_MEMORY.
161 (mips_options): Add info-memory and memory-info.
162 (sim_open): After processing the command line and board
163 specification, check display_mem_info. If it is set then
164 call the real handler for the --memory-info command line
165 switch.
166
35ee6e1e
JB		 1672007-08-24 Joel Brobecker <brobecker@adacore.com>
168
169 * configure.ac: Change license of multi-run.c to GPL version 3.
170 * configure: Regenerate.
171
d5fb0879
RS		 1722007-06-28 Richard Sandiford <richard@codesourcery.com>
173
174 * configure.ac, configure: Revert last patch.
175
2a2ce21b
RS		 1762007-06-26 Richard Sandiford <richard@codesourcery.com>
177
178 * configure.ac (sim_mipsisa3264_configs): New variable.
179 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
180 every configuration support all four targets, using the triplet to
181 determine the default.
182 * configure: Regenerate.
183
efdcccc9
RS		 1842007-06-25 Richard Sandiford <richard@codesourcery.com>
185
0a7692b2 186 * Makefile.in (m16run.o): New rule.
efdcccc9 187
f532a356
TS		 1882007-05-15 Thiemo Seufer <ths@mips.com>
189
190 * mips3264r2.igen (DSHD): Fix compile warning.
191
bfe9c90b
TS		 1922007-05-14 Thiemo Seufer <ths@mips.com>
193
194 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
195 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
196 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
197 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
198 for mips32r2.
199
53f4826b
TS		 2002007-03-01 Thiemo Seufer <ths@mips.com>
201
202 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
203 and mips64.
204
8bf3ddc8
TS		 2052007-02-20 Thiemo Seufer <ths@mips.com>
206
207 * dsp.igen: Update copyright notice.
208 * dsp2.igen: Fix copyright notice.
209
8b082fb1
TS		 2102007-02-20 Thiemo Seufer <ths@mips.com>
211 Chao-Ying Fu <fu@mips.com>
212
213 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
214 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
215 Add dsp2 to sim_igen_machine.
216 * configure: Regenerate.
217 * dsp.igen (do_ph_op): Add MUL support when op = 2.
218 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
219 (mulq_rs.ph): Use do_ph_mulq.
220 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
221 * mips.igen: Add dsp2 model and include dsp2.igen.
222 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
223 for *mips32r2, *mips64r2, *dsp.
224 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
225 for *mips32r2, *mips64r2, *dsp2.
226 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
227
b1004875
TS		 2282007-02-19 Thiemo Seufer <ths@mips.com>
229 Nigel Stephens <nigel@mips.com>
230
231 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
232 jumps with hazard barrier.
233
f8df4c77
TS		 2342007-02-19 Thiemo Seufer <ths@mips.com>
235 Nigel Stephens <nigel@mips.com>
236
237 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
238 after each call to sim_io_write.
239
b1004875 2402007-02-19 Thiemo Seufer <ths@mips.com>
07802d98 241 Nigel Stephens <nigel@mips.com>
b1004875
TS		 242
243 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
244 supported by this simulator.
07802d98
TS		 245 (decode_coproc): Recognise additional CP0 Config registers
246 correctly.
247
14fb6c5a
TS		 2482007-02-19 Thiemo Seufer <ths@mips.com>
249 Nigel Stephens <nigel@mips.com>
250 David Ung <davidu@mips.com>
251
252 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
253 uninterpreted formats. If fmt is one of the uninterpreted types
254 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
255 fmt_word, and fmt_uninterpreted_64 like fmt_long.
256 (store_fpr): When writing an invalid odd register, set the
257 matching even register to fmt_unknown, not the following register.
258 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
259 the the memory window at offset 0 set by --memory-size command
260 line option.
261 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
262 point register.
263 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
264 register.
265 (sim_monitor): When returning the memory size to the MIPS
266 application, use the value in STATE_MEM_SIZE, not an arbitrary
267 hardcoded value.
268 (cop_lw): Don' mess around with FPR_STATE, just pass
269 fmt_uninterpreted_32 to StoreFPR.
270 (cop_sw): Similarly.
271 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
272 (cop_sd): Similarly.
273 * mips.igen (not_word_value): Single version for mips32, mips64
274 and mips16.
275
c8847145
TS		 2762007-02-19 Thiemo Seufer <ths@mips.com>
277 Nigel Stephens <nigel@mips.com>
278
279 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
280 MBytes.
281
4b5d35ee
TS		 2822007-02-17 Thiemo Seufer <ths@mips.com>
283
284 * configure.ac (mips*-sde-elf*): Move in front of generic machine
285 configuration.
286 * configure: Regenerate.
287
3669427c
TS		 2882007-02-17 Thiemo Seufer <ths@mips.com>
289
290 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
291 Add mdmx to sim_igen_machine.
292 (mipsisa64*-*-*): Likewise. Remove dsp.
293 (mipsisa32*-*-*): Remove dsp.
294 * configure: Regenerate.
295
109ad085
TS		 2962007-02-13 Thiemo Seufer <ths@mips.com>
297
298 * configure.ac: Add mips*-sde-elf* target.
299 * configure: Regenerate.
300
921d7ad3
HPN		 3012006-12-21 Hans-Peter Nilsson <hp@axis.com>
302
303 * acconfig.h: Remove.
304 * config.in, configure: Regenerate.
305
02f97da7
TS		 3062006-11-07 Thiemo Seufer <ths@mips.com>
307
308 * dsp.igen (do_w_op): Fix compiler warning.
309
2d2733fc
TS		 3102006-08-29 Thiemo Seufer <ths@mips.com>
311 David Ung <davidu@mips.com>
312
313 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
314 sim_igen_machine.
315 * configure: Regenerate.
316 * mips.igen (model): Add smartmips.
317 (MADDU): Increment ACX if carry.
318 (do_mult): Clear ACX.
319 (ROR,RORV): Add smartmips.
320 (include): Include smartmips.igen.
321 * sim-main.h (ACX): Set to REGISTERS[89].
322 * smartmips.igen: New file.
323
d85c3a10
TS		 3242006-08-29 Thiemo Seufer <ths@mips.com>
325 David Ung <davidu@mips.com>
326
327 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
328 mips3264r2.igen. Add missing dependency rules.
329 * m16e.igen: Support for mips16e save/restore instructions.
330
e85e3205
RE		 3312006-06-13 Richard Earnshaw <rearnsha@arm.com>
332
333 * configure: Regenerated.
334
2f0122dc
DJ		 3352006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
336
337 * configure: Regenerated.
338
20e95c23
DJ		 3392006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
340
341 * configure: Regenerated.
342
69088b17
CF		 3432006-05-15 Chao-ying Fu <fu@mips.com>
344
345 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
346
0275de4e
NC		 3472006-04-18 Nick Clifton <nickc@redhat.com>
348
349 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
350 statement.
351
b3a3ffef
HPN		 3522006-03-29 Hans-Peter Nilsson <hp@axis.com>
353
354 * configure: Regenerate.
355
40a5538e
CF		 3562005-12-14 Chao-ying Fu <fu@mips.com>
357
358 * Makefile.in (SIM_OBJS): Add dsp.o.
359 (dsp.o): New dependency.
360 (IGEN_INCLUDE): Add dsp.igen.
361 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
362 mipsisa64*-*-*): Add dsp to sim_igen_machine.
363 * configure: Regenerate.
364 * mips.igen: Add dsp model and include dsp.igen.
365 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
366 because these instructions are extended in DSP ASE.
367 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
368 adding 6 DSP accumulator registers and 1 DSP control register.
369 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
370 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
371 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
372 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
373 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
374 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
375 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
376 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
377 DSPCR_CCOND_SMASK): New define.
378 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
379 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
380
21d14896
ILT		 3812005-07-08 Ian Lance Taylor <ian@airs.com>
382
383 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
384
b16d63da
DU		 3852005-06-16 David Ung <davidu@mips.com>
386 Nigel Stephens <nigel@mips.com>
387
388 * mips.igen: New mips16e model and include m16e.igen.
389 (check_u64): Add mips16e tag.
390 * m16e.igen: New file for MIPS16e instructions.
391 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
392 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
393 models.
394 * configure: Regenerate.
395
e70cb6cd
CD		 3962005-05-26 David Ung <davidu@mips.com>
397
398 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
399 tags to all instructions which are applicable to the new ISAs.
400 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
401 vr.igen.
402 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
403 instructions.
404 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
405 to mips.igen.
406 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
407 * configure: Regenerate.
408
2b193c4a
MK		 4092005-03-23 Mark Kettenis <kettenis@gnu.org>
410
411 * configure: Regenerate.
412
35695fd6
AC		 4132005-01-14 Andrew Cagney <cagney@gnu.org>
414
415 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
416 explicit call to AC_CONFIG_HEADER.
417 * configure: Regenerate.
418
f0569246
AC		 4192005-01-12 Andrew Cagney <cagney@gnu.org>
420
421 * configure.ac: Update to use ../common/common.m4.
422 * configure: Re-generate.
423
38f48d72
AC		 4242005-01-11 Andrew Cagney <cagney@localhost.localdomain>
425
426 * configure: Regenerated to track ../common/aclocal.m4 changes.
427
b7026657
AC		 4282005-01-07 Andrew Cagney <cagney@gnu.org>
429
430 * configure.ac: Rename configure.in, require autoconf 2.59.
431 * configure: Re-generate.
432
379832de
HPN		 4332004-12-08 Hans-Peter Nilsson <hp@axis.com>
434
435 * configure: Regenerate for ../common/aclocal.m4 update.
436
cd62154c
AC		 4372004-09-24 Monika Chaddha <monika@acmet.com>
438
439 Committed by Andrew Cagney.
440 * m16.igen (CMP, CMPI): Fix assembler.
441
e5da76ec
CD		 4422004-08-18 Chris Demetriou <cgd@broadcom.com>
443
444 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
445 * configure: Regenerate.
446
139181c8
CD		 4472004-06-25 Chris Demetriou <cgd@broadcom.com>
448
449 * configure.in (sim_m16_machine): Include mipsIII.
450 * configure: Regenerate.
451
1a27f959
CD		 4522004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
453
454 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
455 from COP0_BADVADDR.
456 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
457
5dbb7b5a
CD		 4582004-04-10 Chris Demetriou <cgd@broadcom.com>
459
460 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
461
14234056
CD		 4622004-04-09 Chris Demetriou <cgd@broadcom.com>
463
464 * mips.igen (check_fmt): Remove.
465 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
466 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
467 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
468 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
469 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
470 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
471 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
472 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
473 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
474 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
475
c6f9085c
CD		 4762004-04-09 Chris Demetriou <cgd@broadcom.com>
477
478 * sb1.igen (check_sbx): New function.
479 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
480
11d66e66 4812004-03-29 Chris Demetriou <cgd@broadcom.com>
0e1b7197
RS		 482 Richard Sandiford <rsandifo@redhat.com>
483
484 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
485 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
486 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
487 separate implementations for mipsIV and mipsV. Use new macros to
488 determine whether the restrictions apply.
489
b3208fb8
CD		 4902004-01-19 Chris Demetriou <cgd@broadcom.com>
491
492 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
493 (check_mult_hilo): Improve comments.
494 (check_div_hilo): Likewise. Also, fork off a new version
495 to handle mips32/mips64 (since there are no hazards to check
496 in MIPS32/MIPS64).
497
9a1d84fb
CD		 4982003-06-17 Richard Sandiford <rsandifo@redhat.com>
499
500 * mips.igen (do_dmultx): Fix check for negative operands.
501
ae451ac6
ILT		 5022003-05-16 Ian Lance Taylor <ian@airs.com>
503
504 * Makefile.in (SHELL): Make sure this is defined.
505 (various): Use $(SHELL) whenever we invoke move-if-change.
506
dd69d292
CD		 5072003-05-03 Chris Demetriou <cgd@broadcom.com>
508
509 * cp1.c: Tweak attribution slightly.
510 * cp1.h: Likewise.
511 * mdmx.c: Likewise.
512 * mdmx.igen: Likewise.
513 * mips3d.igen: Likewise.
514 * sb1.igen: Likewise.
515
bcd0068e
CD		 5162003-04-15 Richard Sandiford <rsandifo@redhat.com>
517
518 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
519 unsigned operands.
520
6b4a8935
AC		 5212003-02-27 Andrew Cagney <cagney@redhat.com>
522
601da316
AC		 523 * interp.c (sim_open): Rename _bfd to bfd.
524 (sim_create_inferior): Ditto.
6b4a8935 525
d29e330f
CD		 5262003-01-14 Chris Demetriou <cgd@broadcom.com>
527
528 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
529
a2353a08
CD		 5302003-01-14 Chris Demetriou <cgd@broadcom.com>
531
532 * mips.igen (EI, DI): Remove.
533
80551777
CD		 5342003-01-05 Richard Sandiford <rsandifo@redhat.com>
535
536 * Makefile.in (tmp-run-multi): Fix mips16 filter.
537
4c54fc26
CD		 5382003-01-04 Richard Sandiford <rsandifo@redhat.com>
539 Andrew Cagney <ac131313@redhat.com>
540 Gavin Romig-Koch <gavin@redhat.com>
541 Graydon Hoare <graydon@redhat.com>
542 Aldy Hernandez <aldyh@redhat.com>
543 Dave Brolley <brolley@redhat.com>
544 Chris Demetriou <cgd@broadcom.com>
545
546 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
547 (sim_mach_default): New variable.
548 (mips64vr-*-*, mips64vrel-*-*): New configurations.
549 Add a new simulator generator, MULTI.
550 * configure: Regenerate.
551 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
552 (multi-run.o): New dependency.
553 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
554 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
555 (tmp-multi): Combine them.
556 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
557 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
558 (distclean-extra): New rule.
559 * sim-main.h: Include bfd.h.
560 (MIPS_MACH): New macro.
561 * mips.igen (vr4120, vr5400, vr5500): New models.
562 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
563 * vr.igen: Replace with new version.
564
e6c674b8
CD		 5652003-01-04 Chris Demetriou <cgd@broadcom.com>
566
567 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
568 * configure: Regenerate.
569
28f50ac8
CD		 5702002-12-31 Chris Demetriou <cgd@broadcom.com>
571
572 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
573 * mips.igen: Remove all invocations of check_branch_bug and
574 mark_branch_bug.
575
5071ffe6
CD		 5762002-12-16 Chris Demetriou <cgd@broadcom.com>
577
578 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
579
06e7837e
CD		 5802002-07-30 Chris Demetriou <cgd@broadcom.com>
581
582 * mips.igen (do_load_double, do_store_double): New functions.
583 (LDC1, SDC1): Rename to...
584 (LDC1b, SDC1b): respectively.
585 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
586
2265c243
MS		 5872002-07-29 Michael Snyder <msnyder@redhat.com>
588
589 * cp1.c (fp_recip2): Modify initialization expression so that
590 GCC will recognize it as constant.
591
a2f8b4f3
CD		 5922002-06-18 Chris Demetriou <cgd@broadcom.com>
593
594 * mdmx.c (SD_): Delete.
595 (Unpredictable): Re-define, for now, to directly invoke
596 unpredictable_action().
597 (mdmx_acc_op): Fix error in .ob immediate handling.
598
b4b6c939
AC		 5992002-06-18 Andrew Cagney <cagney@redhat.com>
600
601 * interp.c (sim_firmware_command): Initialize `address'.
602
c8cca39f
AC		 6032002-06-16 Andrew Cagney <ac131313@redhat.com>
604
605 * configure: Regenerated to track ../common/aclocal.m4 changes.
606
e7e81181
CD		 6072002-06-14 Chris Demetriou <cgd@broadcom.com>
608 Ed Satterthwaite <ehs@broadcom.com>
609
610 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
611 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
612 * mips.igen: Include mips3d.igen.
613 (mips3d): New model name for MIPS-3D ASE instructions.
614 (CVT.W.fmt): Don't use this instruction for word (source) format
615 instructions.
616 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
617 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
618 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
619 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
620 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
621 (RSquareRoot1, RSquareRoot2): New macros.
622 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
623 (fp_rsqrt2): New functions.
624 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
625 * configure: Regenerate.
626
3a2b820e 6272002-06-13 Chris Demetriou <cgd@broadcom.com>
eab54952 628 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 629
630 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
631 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
632 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
633 (convert): Note that this function is not used for paired-single
634 format conversions.
635 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
636 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
637 (check_fmt_p): Enable paired-single support.
638 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
639 (PUU.PS): New instructions.
640 (CVT.S.fmt): Don't use this instruction for paired-single format
641 destinations.
642 * sim-main.h (FP_formats): New value 'fmt_ps.'
643 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
644 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
645
d18ea9c2
CD		 6462002-06-12 Chris Demetriou <cgd@broadcom.com>
647
648 * mips.igen: Fix formatting of function calls in
649 many FP operations.
650
95fd5cee
CD		 6512002-06-12 Chris Demetriou <cgd@broadcom.com>
652
653 * mips.igen (MOVN, MOVZ): Trace result.
654 (TNEI): Print "tnei" as the opcode name in traces.
655 (CEIL.W): Add disassembly string for traces.
656 (RSQRT.fmt): Make location of disassembly string consistent
657 with other instructions.
658
4f0d55ae
CD		 6592002-06-12 Chris Demetriou <cgd@broadcom.com>
660
661 * mips.igen (X): Delete unused function.
662
3c25f8c7
AC		 6632002-06-08 Andrew Cagney <cagney@redhat.com>
664
665 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
666
f3c08b7e
CD		 6672002-06-07 Chris Demetriou <cgd@broadcom.com>
668 Ed Satterthwaite <ehs@broadcom.com>
669
670 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
671 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
672 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
673 (fp_nmsub): New prototypes.
674 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
675 (NegMultiplySub): New defines.
676 * mips.igen (RSQRT.fmt): Use RSquareRoot().
677 (MADD.D, MADD.S): Replace with...
678 (MADD.fmt): New instruction.
679 (MSUB.D, MSUB.S): Replace with...
680 (MSUB.fmt): New instruction.
681 (NMADD.D, NMADD.S): Replace with...
682 (NMADD.fmt): New instruction.
683 (NMSUB.D, MSUB.S): Replace with...
684 (NMSUB.fmt): New instruction.
685
52714ff9
CD		 6862002-06-07 Chris Demetriou <cgd@broadcom.com>
687 Ed Satterthwaite <ehs@broadcom.com>
688
689 * cp1.c: Fix more comment spelling and formatting.
690 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
691 (denorm_mode): New function.
692 (fpu_unary, fpu_binary): Round results after operation, collect
693 status from rounding operations, and update the FCSR.
694 (convert): Collect status from integer conversions and rounding
695 operations, and update the FCSR. Adjust NaN values that result
696 from conversions. Convert to use sim_io_eprintf rather than
697 fprintf, and remove some debugging code.
698 * cp1.h (fenr_FS): New define.
699
577d8c4b
CD		 7002002-06-07 Chris Demetriou <cgd@broadcom.com>
701
702 * cp1.c (convert): Remove unusable debugging code, and move MIPS
703 rounding mode to sim FP rounding mode flag conversion code into...
704 (rounding_mode): New function.
705
196496ed
CD		 7062002-06-07 Chris Demetriou <cgd@broadcom.com>
707
708 * cp1.c: Clean up formatting of a few comments.
709 (value_fpr): Reformat switch statement.
710
cfe9ea23
CD		 7112002-06-06 Chris Demetriou <cgd@broadcom.com>
712 Ed Satterthwaite <ehs@broadcom.com>
713
714 * cp1.h: New file.
715 * sim-main.h: Include cp1.h.
716 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
717 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
718 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
719 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
720 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
721 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
722 * cp1.c: Don't include sim-fpu.h; already included by
723 sim-main.h. Clean up formatting of some comments.
724 (NaN, Equal, Less): Remove.
725 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
726 (fp_cmp): New functions.
727 * mips.igen (do_c_cond_fmt): Remove.
728 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
729 Compare. Add result tracing.
730 (CxC1): Remove, replace with...
731 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
732 (DMxC1): Remove, replace with...
733 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
734 (MxC1): Remove, replace with...
735 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
736
ee7254b0
CD		 7372002-06-04 Chris Demetriou <cgd@broadcom.com>
738
739 * sim-main.h (FGRIDX): Remove, replace all uses with...
740 (FGR_BASE): New macro.
741 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
742 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
743 (NR_FGR, FGR): Likewise.
744 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
745 * mips.igen: Likewise.
746
d3eb724f
CD		 7472002-06-04 Chris Demetriou <cgd@broadcom.com>
748
749 * cp1.c: Add an FSF Copyright notice to this file.
750
ba46ddd0
CD		 7512002-06-04 Chris Demetriou <cgd@broadcom.com>
752 Ed Satterthwaite <ehs@broadcom.com>
753
754 * cp1.c (Infinity): Remove.
755 * sim-main.h (Infinity): Likewise.
756
757 * cp1.c (fp_unary, fp_binary): New functions.
758 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
759 (fp_sqrt): New functions, implemented in terms of the above.
760 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
761 (Recip, SquareRoot): Remove (replaced by functions above).
762 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
763 (fp_recip, fp_sqrt): New prototypes.
764 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
765 (Recip, SquareRoot): Replace prototypes with #defines which
766 invoke the functions above.
767
18d8a52d
CD		 7682002-06-03 Chris Demetriou <cgd@broadcom.com>
769
770 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
771 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
772 file, remove PARAMS from prototypes.
773 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
774 simulator state arguments.
775 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
776 pass simulator state arguments.
777 * cp1.c (SD): Redefine as CPU_STATE(cpu).
778 (store_fpr, convert): Remove 'sd' argument.
779 (value_fpr): Likewise. Convert to use 'SD' instead.
780
0f154cbd
CD		 7812002-06-03 Chris Demetriou <cgd@broadcom.com>
782
783 * cp1.c (Min, Max): Remove #if 0'd functions.
784 * sim-main.h (Min, Max): Remove.
785
e80fc152
CD		 7862002-06-03 Chris Demetriou <cgd@broadcom.com>
787
788 * cp1.c: fix formatting of switch case and default labels.
789 * interp.c: Likewise.
790 * sim-main.c: Likewise.
791
bad673a9
CD		 7922002-06-03 Chris Demetriou <cgd@broadcom.com>
793
794 * cp1.c: Clean up comments which describe FP formats.
795 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
796
7cbea089
CD		 7972002-06-03 Chris Demetriou <cgd@broadcom.com>
798 Ed Satterthwaite <ehs@broadcom.com>
799
800 * configure.in (mipsisa64sb1*-*-*): New target for supporting
801 Broadcom SiByte SB-1 processor configurations.
802 * configure: Regenerate.
803 * sb1.igen: New file.
804 * mips.igen: Include sb1.igen.
805 (sb1): New model.
806 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
807 * mdmx.igen: Add "sb1" model to all appropriate functions and
808 instructions.
809 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
810 (ob_func, ob_acc): Reference the above.
811 (qh_acc): Adjust to keep the same size as ob_acc.
812 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
813 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
814
909daa82
CD		 8152002-06-03 Chris Demetriou <cgd@broadcom.com>
816
817 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
818
f4f1b9f1
CD		 8192002-06-02 Chris Demetriou <cgd@broadcom.com>
820 Ed Satterthwaite <ehs@broadcom.com>
821
822 * mips.igen (mdmx): New (pseudo-)model.
823 * mdmx.c, mdmx.igen: New files.
824 * Makefile.in (SIM_OBJS): Add mdmx.o.
825 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
826 New typedefs.
827 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
828 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
829 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
830 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
831 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
832 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
833 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
834 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
835 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
836 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
837 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
838 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
839 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
840 (qh_fmtsel): New macros.
841 (_sim_cpu): New member "acc".
842 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
843 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
844
5accf1ff
CD		 8452002-05-01 Chris Demetriou <cgd@broadcom.com>
846
847 * interp.c: Use 'deprecated' rather than 'depreciated.'
848 * sim-main.h: Likewise.
849
402586aa
CD		 8502002-05-01 Chris Demetriou <cgd@broadcom.com>
851
852 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
853 which wouldn't compile anyway.
854 * sim-main.h (unpredictable_action): New function prototype.
855 (Unpredictable): Define to call igen function unpredictable().
856 (NotWordValue): New macro to call igen function not_word_value().
857 (UndefinedResult): Remove.
858 * interp.c (undefined_result): Remove.
859 (unpredictable_action): New function.
860 * mips.igen (not_word_value, unpredictable): New functions.
861 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
862 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
863 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
864 NotWordValue() to check for unpredictable inputs, then
865 Unpredictable() to handle them.
866
c9b9995a
CD		 8672002-02-24 Chris Demetriou <cgd@broadcom.com>
868
869 * mips.igen: Fix formatting of calls to Unpredictable().
870
e1015982
AC		 8712002-04-20 Andrew Cagney <ac131313@redhat.com>
872
873 * interp.c (sim_open): Revert previous change.
874
b882a66b
AO		 8752002-04-18 Alexandre Oliva <aoliva@redhat.com>
876
877 * interp.c (sim_open): Disable chunk of code that wrote code in
878 vector table entries.
879
c429b7dd
CD		 8802002-03-19 Chris Demetriou <cgd@broadcom.com>
881
882 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
883 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
884 unused definitions.
885
37d146fa
CD		 8862002-03-19 Chris Demetriou <cgd@broadcom.com>
887
888 * cp1.c: Fix many formatting issues.
889
07892c0b
CD		 8902002-03-19 Chris G. Demetriou <cgd@broadcom.com>
891
892 * cp1.c (fpu_format_name): New function to replace...
893 (DOFMT): This. Delete, and update all callers.
894 (fpu_rounding_mode_name): New function to replace...
895 (RMMODE): This. Delete, and update all callers.
896
487f79b7
CD		 8972002-03-19 Chris G. Demetriou <cgd@broadcom.com>
898
899 * interp.c: Move FPU support routines from here to...
900 * cp1.c: Here. New file.
901 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
902 (cp1.o): New target.
903
1e799e28
CD		 9042002-03-12 Chris Demetriou <cgd@broadcom.com>
905
906 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
907 * mips.igen (mips32, mips64): New models, add to all instructions
908 and functions as appropriate.
909 (loadstore_ea, check_u64): New variant for model mips64.
910 (check_fmt_p): New variant for models mipsV and mips64, remove
911 mipsV model marking fro other variant.
912 (SLL) Rename to...
913 (SLLa) this.
914 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
915 for mips32 and mips64.
916 (DCLO, DCLZ): New instructions for mips64.
917
82f728db
CD		 9182002-03-07 Chris Demetriou <cgd@broadcom.com>
919
920 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
921 immediate or code as a hex value with the "%#lx" format.
922 (ANDI): Likewise, and fix printed instruction name.
923
b96e7ef1
CD		 9242002-03-05 Chris Demetriou <cgd@broadcom.com>
925
926 * sim-main.h (UndefinedResult, Unpredictable): New macros
927 which currently do nothing.
928
d35d4f70
CD		 9292002-03-05 Chris Demetriou <cgd@broadcom.com>
930
931 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
932 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
933 (status_CU3): New definitions.
934
935 * sim-main.h (ExceptionCause): Add new values for MIPS32
936 and MIPS64: MDMX, MCheck, CacheErr. Update comments
937 for DebugBreakPoint and NMIReset to note their status in
938 MIPS32 and MIPS64.
939 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
940 (SignalExceptionCacheErr): New exception macros.
941
3ad6f714
CD		 9422002-03-05 Chris Demetriou <cgd@broadcom.com>
943
944 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
945 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
946 is always enabled.
947 (SignalExceptionCoProcessorUnusable): Take as argument the
948 unusable coprocessor number.
949
86b77b47
CD		 9502002-03-05 Chris Demetriou <cgd@broadcom.com>
951
952 * mips.igen: Fix formatting of all SignalException calls.
953
97a88e93 9542002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 955
956 * sim-main.h (SIGNEXTEND): Remove.
957
97a88e93 9582002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 959
960 * mips.igen: Remove gencode comment from top of file, fix
961 spelling in another comment.
962
97a88e93 9632002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 964
965 * mips.igen (check_fmt, check_fmt_p): New functions to check
966 whether specific floating point formats are usable.
967 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
968 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
969 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
970 Use the new functions.
971 (do_c_cond_fmt): Remove format checks...
972 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
973
97a88e93 9742002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 975
976 * mips.igen: Fix formatting of check_fpu calls.
977
41774c9d
CD		 9782002-03-03 Chris Demetriou <cgd@broadcom.com>
979
980 * mips.igen (FLOOR.L.fmt): Store correct destination register.
981
4a0bd876
CD		 9822002-03-03 Chris Demetriou <cgd@broadcom.com>
983
984 * mips.igen: Remove whitespace at end of lines.
985
09297648
CD		 9862002-03-02 Chris Demetriou <cgd@broadcom.com>
987
988 * mips.igen (loadstore_ea): New function to do effective
989 address calculations.
990 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
991 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
992 CACHE): Use loadstore_ea to do effective address computations.
993
043b7057
CD		 9942002-03-02 Chris Demetriou <cgd@broadcom.com>
995
996 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
997 * mips.igen (LL, CxC1, MxC1): Likewise.
998
c1e8ada4
CD		 9992002-03-02 Chris Demetriou <cgd@broadcom.com>
1000
1001 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
1002 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
1003 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
1004 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
1005 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
1006 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
1007 Don't split opcode fields by hand, use the opcode field values
1008 provided by igen.
1009
3e1dca16
CD		 10102002-03-01 Chris Demetriou <cgd@broadcom.com>
1011
1012 * mips.igen (do_divu): Fix spacing.
1013
1014 * mips.igen (do_dsllv): Move to be right before DSLLV,
1015 to match the rest of the do_<shift> functions.
1016
fff8d27d
CD		 10172002-03-01 Chris Demetriou <cgd@broadcom.com>
1018
1019 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
1020 DSRL32, do_dsrlv): Trace inputs and results.
1021
0d3e762b
CD		 10222002-03-01 Chris Demetriou <cgd@broadcom.com>
1023
1024 * mips.igen (CACHE): Provide instruction-printing string.
1025
1026 * interp.c (signal_exception): Comment tokens after #endif.
1027
eb5fcf93
CD		 10282002-02-28 Chris Demetriou <cgd@broadcom.com>
1029
1030 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
1031 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
1032 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
1033 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
1034 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
1035 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
1036 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
1037 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
1038
bb22bd7d
CD		 10392002-02-28 Chris Demetriou <cgd@broadcom.com>
1040
1041 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
1042 instruction-printing string.
1043 (LWU): Use '64' as the filter flag.
1044
91a177cf
CD		 10452002-02-28 Chris Demetriou <cgd@broadcom.com>
1046
1047 * mips.igen (SDXC1): Fix instruction-printing string.
1048
387f484a
CD		 10492002-02-28 Chris Demetriou <cgd@broadcom.com>
1050
1051 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
1052 filter flags "32,f".
1053
3d81f391
CD		 10542002-02-27 Chris Demetriou <cgd@broadcom.com>
1055
1056 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1057 as the filter flag.
1058
af5107af
CD		 10592002-02-27 Chris Demetriou <cgd@broadcom.com>
1060
1061 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1062 add a comma) so that it more closely match the MIPS ISA
1063 documentation opcode partitioning.
1064 (PREF): Put useful names on opcode fields, and include
1065 instruction-printing string.
1066
ca971540
CD		 10672002-02-27 Chris Demetriou <cgd@broadcom.com>
1068
1069 * mips.igen (check_u64): New function which in the future will
1070 check whether 64-bit instructions are usable and signal an
1071 exception if not. Currently a no-op.
1072 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1073 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1074 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1075 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1076
1077 * mips.igen (check_fpu): New function which in the future will
1078 check whether FPU instructions are usable and signal an exception
1079 if not. Currently a no-op.
1080 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1081 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1082 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1083 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1084 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1085 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1086 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1087 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1088
1c47a468
CD		 10892002-02-27 Chris Demetriou <cgd@broadcom.com>
1090
1091 * mips.igen (do_load_left, do_load_right): Move to be immediately
1092 following do_load.
1093 (do_store_left, do_store_right): Move to be immediately following
1094 do_store.
1095
603a98e7
CD		 10962002-02-27 Chris Demetriou <cgd@broadcom.com>
1097
1098 * mips.igen (mipsV): New model name. Also, add it to
1099 all instructions and functions where it is appropriate.
1100
c5d00cc7
CD		 11012002-02-18 Chris Demetriou <cgd@broadcom.com>
1102
1103 * mips.igen: For all functions and instructions, list model
1104 names that support that instruction one per line.
1105
074e9cb8
CD		 11062002-02-11 Chris Demetriou <cgd@broadcom.com>
1107
1108 * mips.igen: Add some additional comments about supported
1109 models, and about which instructions go where.
1110 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1111 order as is used in the rest of the file.
1112
9805e229
CD		 11132002-02-11 Chris Demetriou <cgd@broadcom.com>
1114
1115 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1116 indicating that ALU32_END or ALU64_END are there to check
1117 for overflow.
1118 (DADD): Likewise, but also remove previous comment about
1119 overflow checking.
1120
f701dad2
CD		 11212002-02-10 Chris Demetriou <cgd@broadcom.com>
1122
1123 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1124 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1125 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1126 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1127 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1128 fields (i.e., add and move commas) so that they more closely
1129 match the MIPS ISA documentation opcode partitioning.
1130
11312002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098
CD		 1132
1133 * mips.igen (ADDI): Print immediate value.
1134 (BREAK): Print code.
1135 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1136 (SLL): Print "nop" specially, and don't run the code
1137 that does the shift for the "nop" case.
1138
9e52972e
FF		 11392001-11-17 Fred Fish <fnf@redhat.com>
1140
1141 * sim-main.h (float_operation): Move enum declaration outside
1142 of _sim_cpu struct declaration.
1143
c0efbca4
JB		 11442001-04-12 Jim Blandy <jimb@redhat.com>
1145
1146 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1147 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1148 set of the FCSR.
1149 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1150 PENDING_FILL, and you can get the intended effect gracefully by
1151 calling PENDING_SCHED directly.
1152
fb891446
BE		 11532001-02-23 Ben Elliston <bje@redhat.com>
1154
1155 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1156 already defined elsewhere.
1157
8030f857
BE		 11582001-02-19 Ben Elliston <bje@redhat.com>
1159
1160 * sim-main.h (sim_monitor): Return an int.
1161 * interp.c (sim_monitor): Add return values.
1162 (signal_exception): Handle error conditions from sim_monitor.
1163
56b48a7a
CD		 11642001-02-08 Ben Elliston <bje@redhat.com>
1165
1166 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1167 (store_memory): Likewise, pass cia to sim_core_write*.
1168
d3ee60d9
FCE		 11692000-10-19 Frank Ch. Eigler <fche@redhat.com>
1170
1171 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1172 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1173
071da002
AC		 1174Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1175
1176 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1177 * Makefile.in: Don't delete *.igen when cleaning directory.
1178
a28c02cd
AC		 1179Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1180
1181 * m16.igen (break): Call SignalException not sim_engine_halt.
1182
80ee11fa
AC		 1183Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1184
1185 From Jason Eckhardt:
1186 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1187
673388c0
AC		 1188Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1189
1190 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1191
4c0deff4
NC		 11922000-05-24 Michael Hayes <mhayes@cygnus.com>
1193
1194 * mips.igen (do_dmultx): Fix typo.
1195
eb2d80b4
AC		 1196Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1197
1198 * configure: Regenerated to track ../common/aclocal.m4 changes.
1199
dd37a34b
AC		 1200Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1201
1202 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1203
4c0deff4
NC		 12042000-04-12 Frank Ch. Eigler <fche@redhat.com>
1205
1206 * sim-main.h (GPR_CLEAR): Define macro.
1207
e30db738
AC		 1208Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1209
1210 * interp.c (decode_coproc): Output long using %lx and not %s.
1211
cb7450ea
FCE		 12122000-03-21 Frank Ch. Eigler <fche@redhat.com>
1213
1214 * interp.c (sim_open): Sort & extend dummy memory regions for
1215 --board=jmr3904 for eCos.
1216
a3027dd7
FCE		 12172000-03-02 Frank Ch. Eigler <fche@redhat.com>
1218
1219 * configure: Regenerated.
1220
1221Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1222
1223 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1224 calls, conditional on the simulator being in verbose mode.
1225
dfcd3bfb
JM		 1226Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1227
1228 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1229 cache don't get ReservedInstruction traps.
1230
c2d11a7d
JM		 12311999-11-29 Mark Salter <msalter@cygnus.com>
1232
1233 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1234 to clear status bits in sdisr register. This is how the hardware works.
1235
1236 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1237 being used by cygmon.
1238
4ce44c66
JM		 12391999-11-11 Andrew Haley <aph@cygnus.com>
1240
1241 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1242 instructions.
1243
cff3e48b
JM		 1244Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1245
1246 * mips.igen (MULT): Correct previous mis-applied patch.
1247
d4f3574e
SS		 1248Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1249
1250 * mips.igen (delayslot32): Handle sequence like
1251 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1252 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1253 (MULT): Actually pass the third register...
1254
12551999-09-03 Mark Salter <msalter@cygnus.com>
1256
1257 * interp.c (sim_open): Added more memory aliases for additional
1258 hardware being touched by cygmon on jmr3904 board.
1259
1260Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1261
1262 * configure: Regenerated to track ../common/aclocal.m4 changes.
1263
a0b3c4fd
JM		 1264Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1265
1266 * interp.c (sim_store_register): Handle case where client - GDB -
1267 specifies that a 4 byte register is 8 bytes in size.
1268 (sim_fetch_register): Ditto.
1269
adf40b2e
JM		 12701999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1271
1272 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1273 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1274 (idt_monitor_base): Base address for IDT monitor traps.
1275 (pmon_monitor_base): Ditto for PMON.
1276 (lsipmon_monitor_base): Ditto for LSI PMON.
1277 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1278 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1279 (sim_firmware_command): New function.
1280 (mips_option_handler): Call it for OPTION_FIRMWARE.
1281 (sim_open): Allocate memory for idt_monitor region. If "--board"
1282 option was given, add no monitor by default. Add BREAK hooks only if
1283 monitors are also there.
1284
43e526b9
JM		 1285Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1286
1287 * interp.c (sim_monitor): Flush output before reading input.
1288
1289Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1290
1291 * tconfig.in (SIM_HANDLES_LMA): Always define.
1292
1293Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1294
1295 From Mark Salter <msalter@cygnus.com>:
1296 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1297 (sim_open): Add setup for BSP board.
1298
9846de1b
JM		 1299Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1300
1301 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1302 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1303 them as unimplemented.
1304
cd0fc7c3
SS		 13051999-05-08 Felix Lee <flee@cygnus.com>
1306
1307 * configure: Regenerated to track ../common/aclocal.m4 changes.
1308
7a292a7a
SS		 13091999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1310
1311 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1312
1313Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1314
1315 * configure.in: Any mips64vr5*-*-* target should have
1316 -DTARGET_ENABLE_FR=1.
1317 (default_endian): Any mips64vr*el-*-* target should default to
1318 LITTLE_ENDIAN.
1319 * configure: Re-generate.
1320
13211999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1322
1323 * mips.igen (ldl): Extend from _16_, not 32.
1324
1325Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1326
1327 * interp.c (sim_store_register): Force registers written to by GDB
1328 into an un-interpreted state.
1329
c906108c
SS		 13301999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1331
1332 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1333 CPU, start periodic background I/O polls.
1334 (tx3904sio_poll): New function: periodic I/O poller.
1335
13361998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1337
1338 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
1339
1340Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1341
1342 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1343 case statement.
1344
13451998-12-29 Frank Ch. Eigler <fche@cygnus.com>
1346
1347 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
1348 (load_word): Call SIM_CORE_SIGNAL hook on error.
1349 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1350 starting. For exception dispatching, pass PC instead of NULL_CIA.
1351 (decode_coproc): Use COP0_BADVADDR to store faulting address.
1352 * sim-main.h (COP0_BADVADDR): Define.
1353 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1354 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
1355 (_sim_cpu): Add exc_* fields to store register value snapshots.
1356 * mips.igen (*): Replace memory-related SignalException* calls
1357 with references to SIM_CORE_SIGNAL hook.
1358
1359 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1360 fix.
1361 * sim-main.c (*): Minor warning cleanups.
1362
13631998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1364
1365 * m16.igen (DADDIU5): Correct type-o.
1366
1367Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1368
1369 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1370 variables.
1371
1372Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1373
1374 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1375 to include path.
1376 (interp.o): Add dependency on itable.h
1377 (oengine.c, gencode): Delete remaining references.
1378 (BUILT_SRC_FROM_GEN): Clean up.
1379
13801998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
1381
1382 * vr4run.c: New.
1383 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1384 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1385 tmp-run-hack) : New.
1386 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
1387 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
1388 Drop the "64" qualifier to get the HACK generator working.
1389 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1390 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1391 qualifier to get the hack generator working.
1392 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1393 (DSLL): Use do_dsll.
1394 (DSLLV): Use do_dsllv.
1395 (DSRA): Use do_dsra.
1396 (DSRL): Use do_dsrl.
1397 (DSRLV): Use do_dsrlv.
1398 (BC1): Move *vr4100 to get the HACK generator working.
1399 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
1400 get the HACK generator working.
1401 (MACC) Rename to get the HACK generator working.
1402 (DMACC,MACCS,DMACCS): Add the 64.
1403
14041998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1405
1406 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1407 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1408
14091998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1410
1411 * mips/interp.c (DEBUG): Cleanups.
1412
14131998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1414
1415 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1416 (tx3904sio_tickle): fflush after a stdout character output.
1417
14181998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1419
1420 * interp.c (sim_close): Uninstall modules.
1421
1422Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1423
1424 * sim-main.h, interp.c (sim_monitor): Change to global
1425 function.
1426
1427Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1428
1429 * configure.in (vr4100): Only include vr4100 instructions in
1430 simulator.
1431 * configure: Re-generate.
1432 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1433
1434Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1435
1436 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1437 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1438 true alternative.
1439
1440 * configure.in (sim_default_gen, sim_use_gen): Replace with
1441 sim_gen.
1442 (--enable-sim-igen): Delete config option. Always using IGEN.
1443 * configure: Re-generate.
1444
1445 * Makefile.in (gencode): Kill, kill, kill.
1446 * gencode.c: Ditto.
1447
1448Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1449
1450 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1451 bit mips16 igen simulator.
1452 * configure: Re-generate.
1453
1454 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1455 as part of vr4100 ISA.
1456 * vr.igen: Mark all instructions as 64 bit only.
1457
1458Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1459
1460 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1461 Pacify GCC.
1462
1463Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1464
1465 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1466 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1467 * configure: Re-generate.
1468
1469 * m16.igen (BREAK): Define breakpoint instruction.
1470 (JALX32): Mark instruction as mips16 and not r3900.
1471 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1472
1473 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1474
1475Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1476
1477 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1478 insn as a debug breakpoint.
1479
1480 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1481 pending.slot_size.
1482 (PENDING_SCHED): Clean up trace statement.
1483 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1484 (PENDING_FILL): Delay write by only one cycle.
1485 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1486
1487 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1488 of pending writes.
1489 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1490 32 & 64.
1491 (pending_tick): Move incrementing of index to FOR statement.
1492 (pending_tick): Only update PENDING_OUT after a write has occured.
1493
1494 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1495 build simulator.
1496 * configure: Re-generate.
1497
1498 * interp.c (sim_engine_run OLD): Delete explicit call to
1499 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1500
1501Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1502
1503 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1504 interrupt level number to match changed SignalExceptionInterrupt
1505 macro.
1506
1507Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1508
1509 * interp.c: #include "itable.h" if WITH_IGEN.
1510 (get_insn_name): New function.
1511 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1512 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1513
1514Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1515
1516 * configure: Rebuilt to inhale new common/aclocal.m4.
1517
1518Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1519
1520 * dv-tx3904sio.c: Include sim-assert.h.
1521
1522Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1523
1524 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1525 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1526 Reorganize target-specific sim-hardware checks.
1527 * configure: rebuilt.
1528 * interp.c (sim_open): For tx39 target boards, set
1529 OPERATING_ENVIRONMENT, add tx3904sio devices.
1530 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1531 ROM executables. Install dv-sockser into sim-modules list.
1532
1533 * dv-tx3904irc.c: Compiler warning clean-up.
1534 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1535 frequent hw-trace messages.
1536
1537Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1538
1539 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1540
1541Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1542
1543 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1544
1545 * vr.igen: New file.
1546 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1547 * mips.igen: Define vr4100 model. Include vr.igen.
1548Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1549
1550 * mips.igen (check_mf_hilo): Correct check.
1551
1552Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1553
1554 * sim-main.h (interrupt_event): Add prototype.
1555
1556 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1557 register_ptr, register_value.
1558 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1559
1560 * sim-main.h (tracefh): Make extern.
1561
1562Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1563
1564 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1565 Reduce unnecessarily high timer event frequency.
1566 * dv-tx3904cpu.c: Ditto for interrupt event.
1567
1568Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1569
1570 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1571 to allay warnings.
1572 (interrupt_event): Made non-static.
1573
1574 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1575 interchange of configuration values for external vs. internal
1576 clock dividers.
1577
1578Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1579
1580 * mips.igen (BREAK): Moved code to here for
1581 simulator-reserved break instructions.
1582 * gencode.c (build_instruction): Ditto.
1583 * interp.c (signal_exception): Code moved from here. Non-
1584 reserved instructions now use exception vector, rather
1585 than halting sim.
1586 * sim-main.h: Moved magic constants to here.
1587
1588Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1589
1590 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1591 register upon non-zero interrupt event level, clear upon zero
1592 event value.
1593 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1594 by passing zero event value.
1595 (*_io_{read,write}_buffer): Endianness fixes.
1596 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1597 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1598
1599 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1600 serial I/O and timer module at base address 0xFFFF0000.
1601
1602Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1603
1604 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1605 and BigEndianCPU.
1606
1607Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1608
1609 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1610 parts.
1611 * configure: Update.
1612
1613Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1614
1615 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1616 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1617 * configure.in: Include tx3904tmr in hw_device list.
1618 * configure: Rebuilt.
1619 * interp.c (sim_open): Instantiate three timer instances.
1620 Fix address typo of tx3904irc instance.
1621
1622Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1623
1624 * interp.c (signal_exception): SystemCall exception now uses
1625 the exception vector.
1626
1627Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1628
1629 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1630 to allay warnings.
1631
1632Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1633
1634 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1635
1636Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1637
1638 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1639
1640 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1641 sim-main.h. Declare a struct hw_descriptor instead of struct
1642 hw_device_descriptor.
1643
1644Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1645
1646 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1647 right bits and then re-align left hand bytes to correct byte
1648 lanes. Fix incorrect computation in do_store_left when loading
1649 bytes from second word.
1650
1651Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1652
1653 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1654 * interp.c (sim_open): Only create a device tree when HW is
1655 enabled.
1656
1657 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1658 * interp.c (signal_exception): Ditto.
1659
1660Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1661
1662 * gencode.c: Mark BEGEZALL as LIKELY.
1663
1664Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1665
1666 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1667 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1668
1669Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1670
1671 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1672 modules. Recognize TX39 target with "mips*tx39" pattern.
1673 * configure: Rebuilt.
1674 * sim-main.h (*): Added many macros defining bits in
1675 TX39 control registers.
1676 (SignalInterrupt): Send actual PC instead of NULL.
1677 (SignalNMIReset): New exception type.
1678 * interp.c (board): New variable for future use to identify
1679 a particular board being simulated.
1680 (mips_option_handler,mips_options): Added "--board" option.
1681 (interrupt_event): Send actual PC.
1682 (sim_open): Make memory layout conditional on board setting.
1683 (signal_exception): Initial implementation of hardware interrupt
1684 handling. Accept another break instruction variant for simulator
1685 exit.
1686 (decode_coproc): Implement RFE instruction for TX39.
1687 (mips.igen): Decode RFE instruction as such.
1688 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1689 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1690 bbegin to implement memory map.
1691 * dv-tx3904cpu.c: New file.
1692 * dv-tx3904irc.c: New file.
1693
1694Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1695
1696 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1697
1698Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1699
1700 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1701 with calls to check_div_hilo.
1702
1703Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1704
1705 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1706 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1707 Add special r3900 version of do_mult_hilo.
1708 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1709 with calls to check_mult_hilo.
1710 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1711 with calls to check_div_hilo.
1712
1713Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1714
1715 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1716 Document a replacement.
1717
1718Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1719
1720 * interp.c (sim_monitor): Make mon_printf work.
1721
1722Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1723
1724 * sim-main.h (INSN_NAME): New arg `cpu'.
1725
1726Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1727
1728 * configure: Regenerated to track ../common/aclocal.m4 changes.
1729
1730Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1731
1732 * configure: Regenerated to track ../common/aclocal.m4 changes.
1733 * config.in: Ditto.
1734
1735Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1736
1737 * acconfig.h: New file.
1738 * configure.in: Reverted change of Apr 24; use sinclude again.
1739
1740Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1741
1742 * configure: Regenerated to track ../common/aclocal.m4 changes.
1743 * config.in: Ditto.
1744
1745Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1746
1747 * configure.in: Don't call sinclude.
1748
1749Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1750
1751 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1752
1753Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1754
1755 * mips.igen (ERET): Implement.
1756
1757 * interp.c (decode_coproc): Return sign-extended EPC.
1758
1759 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1760
1761 * interp.c (signal_exception): Do not ignore Trap.
1762 (signal_exception): On TRAP, restart at exception address.
1763 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1764 (signal_exception): Update.
1765 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1766 so that TRAP instructions are caught.
1767
1768Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1769
1770 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1771 contains HI/LO access history.
1772 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1773 (HIACCESS, LOACCESS): Delete, replace with
1774 (HIHISTORY, LOHISTORY): New macros.
1775 (CHECKHILO): Delete all, moved to mips.igen
1776
1777 * gencode.c (build_instruction): Do not generate checks for
1778 correct HI/LO register usage.
1779
1780 * interp.c (old_engine_run): Delete checks for correct HI/LO
1781 register usage.
1782
1783 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1784 check_mf_cycles): New functions.
1785 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1786 do_divu, domultx, do_mult, do_multu): Use.
1787
1788 * tx.igen ("madd", "maddu"): Use.
1789
1790Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1791
1792 * mips.igen (DSRAV): Use function do_dsrav.
1793 (SRAV): Use new function do_srav.
1794
1795 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1796 (B): Sign extend 11 bit immediate.
1797 (EXT-B*): Shift 16 bit immediate left by 1.
1798 (ADDIU*): Don't sign extend immediate value.
1799
1800Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1801
1802 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1803
1804 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1805 functions.
1806
1807 * mips.igen (delayslot32, nullify_next_insn): New functions.
1808 (m16.igen): Always include.
1809 (do_*): Add more tracing.
1810
1811 * m16.igen (delayslot16): Add NIA argument, could be called by a
1812 32 bit MIPS16 instruction.
1813
1814 * interp.c (ifetch16): Move function from here.
1815 * sim-main.c (ifetch16): To here.
1816
1817 * sim-main.c (ifetch16, ifetch32): Update to match current
1818 implementations of LH, LW.
1819 (signal_exception): Don't print out incorrect hex value of illegal
1820 instruction.
1821
1822Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1823
1824 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1825 instruction.
1826
1827 * m16.igen: Implement MIPS16 instructions.
1828
1829 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1830 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1831 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1832 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1833 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1834 bodies of corresponding code from 32 bit insn to these. Also used
1835 by MIPS16 versions of functions.
1836
1837 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1838 (IMEM16): Drop NR argument from macro.
1839
1840Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1841
1842 * Makefile.in (SIM_OBJS): Add sim-main.o.
1843
1844 * sim-main.h (address_translation, load_memory, store_memory,
1845 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1846 as INLINE_SIM_MAIN.
1847 (pr_addr, pr_uword64): Declare.
1848 (sim-main.c): Include when H_REVEALS_MODULE_P.
1849
1850 * interp.c (address_translation, load_memory, store_memory,
1851 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1852 from here.
1853 * sim-main.c: To here. Fix compilation problems.
1854
1855 * configure.in: Enable inlining.
1856 * configure: Re-config.
1857
1858Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1859
1860 * configure: Regenerated to track ../common/aclocal.m4 changes.
1861
1862Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1863
1864 * mips.igen: Include tx.igen.
1865 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1866 * tx.igen: New file, contains MADD and MADDU.
1867
1868 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1869 the hardwired constant `7'.
1870 (store_memory): Ditto.
1871 (LOADDRMASK): Move definition to sim-main.h.
1872
1873 mips.igen (MTC0): Enable for r3900.
1874 (ADDU): Add trace.
1875
1876 mips.igen (do_load_byte): Delete.
1877 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1878 do_store_right): New functions.
1879 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1880
1881 configure.in: Let the tx39 use igen again.
1882 configure: Update.
1883
1884Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1885
1886 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1887 not an address sized quantity. Return zero for cache sizes.
1888
1889Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1890
1891 * mips.igen (r3900): r3900 does not support 64 bit integer
1892 operations.
1893
1894Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1895
1896 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1897 than igen one.
1898 * configure : Rebuild.
1899
1900Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1901
1902 * configure: Regenerated to track ../common/aclocal.m4 changes.
1903
1904Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1905
1906 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1907
1908Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1909
1910 * configure: Regenerated to track ../common/aclocal.m4 changes.
1911 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1912
1913Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1914
1915 * configure: Regenerated to track ../common/aclocal.m4 changes.
1916
1917Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1918
1919 * interp.c (Max, Min): Comment out functions. Not yet used.
1920
1921Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1922
1923 * configure: Regenerated to track ../common/aclocal.m4 changes.
1924
1925Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1926
1927 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1928 configurable settings for stand-alone simulator.
1929
1930 * configure.in: Added X11 search, just in case.
1931
1932 * configure: Regenerated.
1933
1934Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1935
1936 * interp.c (sim_write, sim_read, load_memory, store_memory):
1937 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1938
1939Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1940
1941 * sim-main.h (GETFCC): Return an unsigned value.
1942
1943Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1944
1945 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1946 (DADD): Result destination is RD not RT.
1947
1948Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1949
1950 * sim-main.h (HIACCESS, LOACCESS): Always define.
1951
1952 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1953
1954 * interp.c (sim_info): Delete.
1955
1956Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1957
1958 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1959 (mips_option_handler): New argument `cpu'.
1960 (sim_open): Update call to sim_add_option_table.
1961
1962Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1963
1964 * mips.igen (CxC1): Add tracing.
1965
1966Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1967
1968 * sim-main.h (Max, Min): Declare.
1969
1970 * interp.c (Max, Min): New functions.
1971
1972 * mips.igen (BC1): Add tracing.
1973
1974Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1975
1976 * interp.c Added memory map for stack in vr4100
1977
1978Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1979
1980 * interp.c (load_memory): Add missing "break"'s.
1981
1982Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1983
1984 * interp.c (sim_store_register, sim_fetch_register): Pass in
1985 length parameter. Return -1.
1986
1987Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1988
1989 * interp.c: Added hardware init hook, fixed warnings.
1990
1991Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1992
1993 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1994
1995Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1996
1997 * interp.c (ifetch16): New function.
1998
1999 * sim-main.h (IMEM32): Rename IMEM.
2000 (IMEM16_IMMED): Define.
2001 (IMEM16): Define.
2002 (DELAY_SLOT): Update.
2003
2004 * m16run.c (sim_engine_run): New file.
2005
2006 * m16.igen: All instructions except LB.
2007 (LB): Call do_load_byte.
2008 * mips.igen (do_load_byte): New function.
2009 (LB): Call do_load_byte.
2010
2011 * mips.igen: Move spec for insn bit size and high bit from here.
2012 * Makefile.in (tmp-igen, tmp-m16): To here.
2013
2014 * m16.dc: New file, decode mips16 instructions.
2015
2016 * Makefile.in (SIM_NO_ALL): Define.
2017 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
2018
2019Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
2020
2021 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
2022 point unit to 32 bit registers.
2023 * configure: Re-generate.
2024
2025Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2026
2027 * configure.in (sim_use_gen): Make IGEN the default simulator
2028 generator for generic 32 and 64 bit mips targets.
2029 * configure: Re-generate.
2030
2031Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2032
2033 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
2034 bitsize.
2035
2036 * interp.c (sim_fetch_register, sim_store_register): Read/write
2037 FGR from correct location.
2038 (sim_open): Set size of FGR's according to
2039 WITH_TARGET_FLOATING_POINT_BITSIZE.
2040
2041 * sim-main.h (FGR): Store floating point registers in a separate
2042 array.
2043
2044Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
2045
2046 * configure: Regenerated to track ../common/aclocal.m4 changes.
2047
2048Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2049
2050 * interp.c (ColdReset): Call PENDING_INVALIDATE.
2051
2052 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
2053
2054 * interp.c (pending_tick): New function. Deliver pending writes.
2055
2056 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2057 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2058 it can handle mixed sized quantites and single bits.
2059
2060Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2061
2062 * interp.c (oengine.h): Do not include when building with IGEN.
2063 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2064 (sim_info): Ditto for PROCESSOR_64BIT.
2065 (sim_monitor): Replace ut_reg with unsigned_word.
2066 (*): Ditto for t_reg.
2067 (LOADDRMASK): Define.
2068 (sim_open): Remove defunct check that host FP is IEEE compliant,
2069 using software to emulate floating point.
2070 (value_fpr, ...): Always compile, was conditional on HASFPU.
2071
2072Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2073
2074 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2075 size.
2076
2077 * interp.c (SD, CPU): Define.
2078 (mips_option_handler): Set flags in each CPU.
2079 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2080 (sim_close): Do not clear STATE, deleted anyway.
2081 (sim_write, sim_read): Assume CPU zero's vm should be used for
2082 data transfers.
2083 (sim_create_inferior): Set the PC for all processors.
2084 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2085 argument.
2086 (mips16_entry): Pass correct nr of args to store_word, load_word.
2087 (ColdReset): Cold reset all cpu's.
2088 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2089 (sim_monitor, load_memory, store_memory, signal_exception): Use
2090 `CPU' instead of STATE_CPU.
2091
2092
2093 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2094 SD or CPU_.
2095
2096 * sim-main.h (signal_exception): Add sim_cpu arg.
2097 (SignalException*): Pass both SD and CPU to signal_exception.
2098 * interp.c (signal_exception): Update.
2099
2100 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2101 Ditto
2102 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2103 address_translation): Ditto
2104 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
2105
2106Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2107
2108 * configure: Regenerated to track ../common/aclocal.m4 changes.
2109
2110Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2111
2112 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2113
2114 * mips.igen (model): Map processor names onto BFD name.
2115
2116 * sim-main.h (CPU_CIA): Delete.
2117 (SET_CIA, GET_CIA): Define
2118
2119Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2120
2121 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2122 regiser.
2123
2124 * configure.in (default_endian): Configure a big-endian simulator
2125 by default.
2126 * configure: Re-generate.
2127
2128Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2129
2130 * configure: Regenerated to track ../common/aclocal.m4 changes.
2131
2132Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2133
2134 * interp.c (sim_monitor): Handle Densan monitor outbyte
2135 and inbyte functions.
2136
21371997-12-29 Felix Lee <flee@cygnus.com>
2138
2139 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2140
2141Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2142
2143 * Makefile.in (tmp-igen): Arrange for $zero to always be
2144 reset to zero after every instruction.
2145
2146Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2147
2148 * configure: Regenerated to track ../common/aclocal.m4 changes.
2149 * config.in: Ditto.
2150
2151Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2152
2153 * mips.igen (MSUB): Fix to work like MADD.
2154 * gencode.c (MSUB): Similarly.
2155
2156Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2157
2158 * configure: Regenerated to track ../common/aclocal.m4 changes.
2159
2160Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2161
2162 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2163
2164Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2165
2166 * sim-main.h (sim-fpu.h): Include.
2167
2168 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2169 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2170 using host independant sim_fpu module.
2171
2172Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2173
2174 * interp.c (signal_exception): Report internal errors with SIGABRT
2175 not SIGQUIT.
2176
2177 * sim-main.h (C0_CONFIG): New register.
2178 (signal.h): No longer include.
2179
2180 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2181
2182Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2183
2184 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2185
2186Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2187
2188 * mips.igen: Tag vr5000 instructions.
2189 (ANDI): Was missing mipsIV model, fix assembler syntax.
2190 (do_c_cond_fmt): New function.
2191 (C.cond.fmt): Handle mips I-III which do not support CC field
2192 separatly.
2193 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2194 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2195 in IV3.2 spec.
2196 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2197 vr5000 which saves LO in a GPR separatly.
2198
2199 * configure.in (enable-sim-igen): For vr5000, select vr5000
2200 specific instructions.
2201 * configure: Re-generate.
2202
2203Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2204
2205 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2206
2207 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2208 fmt_uninterpreted_64 bit cases to switch. Convert to
2209 fmt_formatted,
2210
2211 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2212
2213 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2214 as specified in IV3.2 spec.
2215 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2216
2217Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2218
2219 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2220 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2221 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2222 PENDING_FILL versions of instructions. Simplify.
2223 (X): New function.
2224 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2225 instructions.
2226 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2227 a signed value.
2228 (MTHI, MFHI): Disable code checking HI-LO.
2229
2230 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2231 global.
2232 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2233
2234Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2235
2236 * gencode.c (build_mips16_operands): Replace IPC with cia.
2237
2238 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2239 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2240 IPC to `cia'.
2241 (UndefinedResult): Replace function with macro/function
2242 combination.
2243 (sim_engine_run): Don't save PC in IPC.
2244
2245 * sim-main.h (IPC): Delete.
2246
2247
2248 * interp.c (signal_exception, store_word, load_word,
2249 address_translation, load_memory, store_memory, cache_op,
2250 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2251 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2252 current instruction address - cia - argument.
2253 (sim_read, sim_write): Call address_translation directly.
2254 (sim_engine_run): Rename variable vaddr to cia.
2255 (signal_exception): Pass cia to sim_monitor
2256
2257 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2258 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2259 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2260
2261 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2262 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2263 SIM_ASSERT.
2264
2265 * interp.c (signal_exception): Pass restart address to
2266 sim_engine_restart.
2267
2268 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2269 idecode.o): Add dependency.
2270
2271 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2272 Delete definitions
2273 (DELAY_SLOT): Update NIA not PC with branch address.
2274 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2275
2276 * mips.igen: Use CIA not PC in branch calculations.
2277 (illegal): Call SignalException.
2278 (BEQ, ADDIU): Fix assembler.
2279
2280Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2281
2282 * m16.igen (JALX): Was missing.
2283
2284 * configure.in (enable-sim-igen): New configuration option.
2285 * configure: Re-generate.
2286
2287 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2288
2289 * interp.c (load_memory, store_memory): Delete parameter RAW.
2290 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2291 bypassing {load,store}_memory.
2292
2293 * sim-main.h (ByteSwapMem): Delete definition.
2294
2295 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2296
2297 * interp.c (sim_do_command, sim_commands): Delete mips specific
2298 commands. Handled by module sim-options.
2299
2300 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2301 (WITH_MODULO_MEMORY): Define.
2302
2303 * interp.c (sim_info): Delete code printing memory size.
2304
2305 * interp.c (mips_size): Nee sim_size, delete function.
2306 (power2): Delete.
2307 (monitor, monitor_base, monitor_size): Delete global variables.
2308 (sim_open, sim_close): Delete code creating monitor and other
2309 memory regions. Use sim-memopts module, via sim_do_commandf, to
2310 manage memory regions.
2311 (load_memory, store_memory): Use sim-core for memory model.
2312
2313 * interp.c (address_translation): Delete all memory map code
2314 except line forcing 32 bit addresses.
2315
2316Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2317
2318 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2319 trace options.
2320
2321 * interp.c (logfh, logfile): Delete globals.
2322 (sim_open, sim_close): Delete code opening & closing log file.
2323 (mips_option_handler): Delete -l and -n options.
2324 (OPTION mips_options): Ditto.
2325
2326 * interp.c (OPTION mips_options): Rename option trace to dinero.
2327 (mips_option_handler): Update.
2328
2329Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2330
2331 * interp.c (fetch_str): New function.
2332 (sim_monitor): Rewrite using sim_read & sim_write.
2333 (sim_open): Check magic number.
2334 (sim_open): Write monitor vectors into memory using sim_write.
2335 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2336 (sim_read, sim_write): Simplify - transfer data one byte at a
2337 time.
2338 (load_memory, store_memory): Clarify meaning of parameter RAW.
2339
2340 * sim-main.h (isHOST): Defete definition.
2341 (isTARGET): Mark as depreciated.
2342 (address_translation): Delete parameter HOST.
2343
2344 * interp.c (address_translation): Delete parameter HOST.
2345
2346Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2347
2348 * mips.igen:
2349
2350 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2351 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2352
2353Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2354
2355 * mips.igen: Add model filter field to records.
2356
2357Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2358
2359 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
2360
2361 interp.c (sim_engine_run): Do not compile function sim_engine_run
2362 when WITH_IGEN == 1.
2363
2364 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2365 target architecture.
2366
2367 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2368 igen. Replace with configuration variables sim_igen_flags /
2369 sim_m16_flags.
2370
2371 * m16.igen: New file. Copy mips16 insns here.
2372 * mips.igen: From here.
2373
2374Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2375
2376 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2377 to top.
2378 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2379
2380Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2381
2382 * gencode.c (build_instruction): Follow sim_write's lead in using
2383 BigEndianMem instead of !ByteSwapMem.
2384
2385Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2386
2387 * configure.in (sim_gen): Dependent on target, select type of
2388 generator. Always select old style generator.
2389
2390 configure: Re-generate.
2391
2392 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2393 targets.
2394 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2395 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2396 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2397 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2398 SIM_@sim_gen@_*, set by autoconf.
2399
2400Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2401
2402 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2403
2404 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2405 CURRENT_FLOATING_POINT instead.
2406
2407 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2408 (address_translation): Raise exception InstructionFetch when
2409 translation fails and isINSTRUCTION.
2410
2411 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2412 sim_engine_run): Change type of of vaddr and paddr to
2413 address_word.
2414 (address_translation, prefetch, load_memory, store_memory,
2415 cache_op): Change type of vAddr and pAddr to address_word.
2416
2417 * gencode.c (build_instruction): Change type of vaddr and paddr to
2418 address_word.
2419
2420Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2421
2422 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2423 macro to obtain result of ALU op.
2424
2425Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2426
2427 * interp.c (sim_info): Call profile_print.
2428
2429Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2430
2431 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2432
2433 * sim-main.h (WITH_PROFILE): Do not define, defined in
2434 common/sim-config.h. Use sim-profile module.
2435 (simPROFILE): Delete defintion.
2436
2437 * interp.c (PROFILE): Delete definition.
2438 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2439 (sim_close): Delete code writing profile histogram.
2440 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2441 Delete.
2442 (sim_engine_run): Delete code profiling the PC.
2443
2444Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2445
2446 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2447
2448 * interp.c (sim_monitor): Make register pointers of type
2449 unsigned_word*.
2450
2451 * sim-main.h: Make registers of type unsigned_word not
2452 signed_word.
2453
2454Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2455
2456 * interp.c (sync_operation): Rename from SyncOperation, make
2457 global, add SD argument.
2458 (prefetch): Rename from Prefetch, make global, add SD argument.
2459 (decode_coproc): Make global.
2460
2461 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2462
2463 * gencode.c (build_instruction): Generate DecodeCoproc not
2464 decode_coproc calls.
2465
2466 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2467 (SizeFGR): Move to sim-main.h
2468 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2469 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2470 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2471 sim-main.h.
2472 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2473 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2474 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2475 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2476 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2477 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2478
2479 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2480 exception.
2481 (sim-alu.h): Include.
2482 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2483 (sim_cia): Typedef to instruction_address.
2484
2485Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2486
2487 * Makefile.in (interp.o): Rename generated file engine.c to
2488 oengine.c.
2489
2490 * interp.c: Update.
2491
2492Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2493
2494 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2495
2496Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2497
2498 * gencode.c (build_instruction): For "FPSQRT", output correct
2499 number of arguments to Recip.
2500
2501Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2502
2503 * Makefile.in (interp.o): Depends on sim-main.h
2504
2505 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2506
2507 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2508 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2509 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2510 STATE, DSSTATE): Define
2511 (GPR, FGRIDX, ..): Define.
2512
2513 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2514 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2515 (GPR, FGRIDX, ...): Delete macros.
2516
2517 * interp.c: Update names to match defines from sim-main.h
2518
2519Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2520
2521 * interp.c (sim_monitor): Add SD argument.
2522 (sim_warning): Delete. Replace calls with calls to
2523 sim_io_eprintf.
2524 (sim_error): Delete. Replace calls with sim_io_error.
2525 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2526 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2527 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2528 argument.
2529 (mips_size): Rename from sim_size. Add SD argument.
2530
2531 * interp.c (simulator): Delete global variable.
2532 (callback): Delete global variable.
2533 (mips_option_handler, sim_open, sim_write, sim_read,
2534 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2535 sim_size,sim_monitor): Use sim_io_* not callback->*.
2536 (sim_open): ZALLOC simulator struct.
2537 (PROFILE): Do not define.
2538
2539Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2540
2541 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2542 support.h with corresponding code.
2543
2544 * sim-main.h (word64, uword64), support.h: Move definition to
2545 sim-main.h.
2546 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2547
2548 * support.h: Delete
2549 * Makefile.in: Update dependencies
2550 * interp.c: Do not include.
2551
2552Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2553
2554 * interp.c (address_translation, load_memory, store_memory,
2555 cache_op): Rename to from AddressTranslation et.al., make global,
2556 add SD argument
2557
2558 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2559 CacheOp): Define.
2560
2561 * interp.c (SignalException): Rename to signal_exception, make
2562 global.
2563
2564 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2565
2566 * sim-main.h (SignalException, SignalExceptionInterrupt,
2567 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2568 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2569 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2570 Define.
2571
2572 * interp.c, support.h: Use.
2573
2574Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2575
2576 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2577 to value_fpr / store_fpr. Add SD argument.
2578 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2579 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2580
2581 * sim-main.h (ValueFPR, StoreFPR): Define.
2582
2583Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2584
2585 * interp.c (sim_engine_run): Check consistency between configure
2586 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2587 and HASFPU.
2588
2589 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2590 (mips_fpu): Configure WITH_FLOATING_POINT.
2591 (mips_endian): Configure WITH_TARGET_ENDIAN.
2592 * configure: Update.
2593
2594Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2595
2596 * configure: Regenerated to track ../common/aclocal.m4 changes.
2597
2598Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2599
2600 * configure: Regenerated.
2601
2602Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2603
2604 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2605
2606Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2607
2608 * gencode.c (print_igen_insn_models): Assume certain architectures
2609 include all mips* instructions.
2610 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2611 instruction.
2612
2613 * Makefile.in (tmp.igen): Add target. Generate igen input from
2614 gencode file.
2615
2616 * gencode.c (FEATURE_IGEN): Define.
2617 (main): Add --igen option. Generate output in igen format.
2618 (process_instructions): Format output according to igen option.
2619 (print_igen_insn_format): New function.
2620 (print_igen_insn_models): New function.
2621 (process_instructions): Only issue warnings and ignore
2622 instructions when no FEATURE_IGEN.
2623
2624Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2625
2626 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2627 MIPS targets.
2628
2629Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2630
2631 * configure: Regenerated to track ../common/aclocal.m4 changes.
2632
2633Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2634
2635 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2636 SIM_RESERVED_BITS): Delete, moved to common.
2637 (SIM_EXTRA_CFLAGS): Update.
2638
2639Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2640
2641 * configure.in: Configure non-strict memory alignment.
2642 * configure: Regenerated to track ../common/aclocal.m4 changes.
2643
2644Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2645
2646 * configure: Regenerated to track ../common/aclocal.m4 changes.
2647
2648Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2649
2650 * gencode.c (SDBBP,DERET): Added (3900) insns.
2651 (RFE): Turn on for 3900.
2652 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2653 (dsstate): Made global.
2654 (SUBTARGET_R3900): Added.
2655 (CANCELDELAYSLOT): New.
2656 (SignalException): Ignore SystemCall rather than ignore and
2657 terminate. Add DebugBreakPoint handling.
2658 (decode_coproc): New insns RFE, DERET; and new registers Debug
2659 and DEPC protected by SUBTARGET_R3900.
2660 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2661 bits explicitly.
2662 * Makefile.in,configure.in: Add mips subtarget option.
2663 * configure: Update.
2664
2665Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2666
2667 * gencode.c: Add r3900 (tx39).
2668
2669
2670Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2671
2672 * gencode.c (build_instruction): Don't need to subtract 4 for
2673 JALR, just 2.
2674
2675Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2676
2677 * interp.c: Correct some HASFPU problems.
2678
2679Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2680
2681 * configure: Regenerated to track ../common/aclocal.m4 changes.
2682
2683Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2684
2685 * interp.c (mips_options): Fix samples option short form, should
2686 be `x'.
2687
2688Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2689
2690 * interp.c (sim_info): Enable info code. Was just returning.
2691
2692Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2693
2694 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2695 MFC0.
2696
2697Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2698
2699 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2700 constants.
2701 (build_instruction): Ditto for LL.
2702
2703Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2704
2705 * configure: Regenerated to track ../common/aclocal.m4 changes.
2706
2707Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2708
2709 * configure: Regenerated to track ../common/aclocal.m4 changes.
2710 * config.in: Ditto.
2711
2712Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2713
2714 * interp.c (sim_open): Add call to sim_analyze_program, update
2715 call to sim_config.
2716
2717Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2718
2719 * interp.c (sim_kill): Delete.
2720 (sim_create_inferior): Add ABFD argument. Set PC from same.
2721 (sim_load): Move code initializing trap handlers from here.
2722 (sim_open): To here.
2723 (sim_load): Delete, use sim-hload.c.
2724
2725 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2726
2727Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2728
2729 * configure: Regenerated to track ../common/aclocal.m4 changes.
2730 * config.in: Ditto.
2731
2732Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2733
2734 * interp.c (sim_open): Add ABFD argument.
2735 (sim_load): Move call to sim_config from here.
2736 (sim_open): To here. Check return status.
2737
2738Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2739
2740 * gencode.c (build_instruction): Two arg MADD should
2741 not assign result to $0.
2742
2743Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2744
2745 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2746 * sim/mips/configure.in: Regenerate.
2747
2748Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2749
2750 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2751 signed8, unsigned8 et.al. types.
2752
2753 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2754 hosts when selecting subreg.
2755
2756Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2757
2758 * interp.c (sim_engine_run): Reset the ZERO register to zero
2759 regardless of FEATURE_WARN_ZERO.
2760 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2761
2762Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2763
2764 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2765 (SignalException): For BreakPoints ignore any mode bits and just
2766 save the PC.
2767 (SignalException): Always set the CAUSE register.
2768
2769Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2770
2771 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2772 exception has been taken.
2773
2774 * interp.c: Implement the ERET and mt/f sr instructions.
2775
2776Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2777
2778 * interp.c (SignalException): Don't bother restarting an
2779 interrupt.
2780
2781Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2782
2783 * interp.c (SignalException): Really take an interrupt.
2784 (interrupt_event): Only deliver interrupts when enabled.
2785
2786Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2787
2788 * interp.c (sim_info): Only print info when verbose.
2789 (sim_info) Use sim_io_printf for output.
2790
2791Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2792
2793 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2794 mips architectures.
2795
2796Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2797
2798 * interp.c (sim_do_command): Check for common commands if a
2799 simulator specific command fails.
2800
2801Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2802
2803 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2804 and simBE when DEBUG is defined.
2805
2806Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2807
2808 * interp.c (interrupt_event): New function. Pass exception event
2809 onto exception handler.
2810
2811 * configure.in: Check for stdlib.h.
2812 * configure: Regenerate.
2813
2814 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2815 variable declaration.
2816 (build_instruction): Initialize memval1.
2817 (build_instruction): Add UNUSED attribute to byte, bigend,
2818 reverse.
2819 (build_operands): Ditto.
2820
2821 * interp.c: Fix GCC warnings.
2822 (sim_get_quit_code): Delete.
2823
2824 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2825 * Makefile.in: Ditto.
2826 * configure: Re-generate.
2827
2828 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2829
2830Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2831
2832 * interp.c (mips_option_handler): New function parse argumes using
2833 sim-options.
2834 (myname): Replace with STATE_MY_NAME.
2835 (sim_open): Delete check for host endianness - performed by
2836 sim_config.
2837 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2838 (sim_open): Move much of the initialization from here.
2839 (sim_load): To here. After the image has been loaded and
2840 endianness set.
2841 (sim_open): Move ColdReset from here.
2842 (sim_create_inferior): To here.
2843 (sim_open): Make FP check less dependant on host endianness.
2844
2845 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2846 run.
2847 * interp.c (sim_set_callbacks): Delete.
2848
2849 * interp.c (membank, membank_base, membank_size): Replace with
2850 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2851 (sim_open): Remove call to callback->init. gdb/run do this.
2852
2853 * interp.c: Update
2854
2855 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2856
2857 * interp.c (big_endian_p): Delete, replaced by
2858 current_target_byte_order.
2859
2860Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2861
2862 * interp.c (host_read_long, host_read_word, host_swap_word,
2863 host_swap_long): Delete. Using common sim-endian.
2864 (sim_fetch_register, sim_store_register): Use H2T.
2865 (pipeline_ticks): Delete. Handled by sim-events.
2866 (sim_info): Update.
2867 (sim_engine_run): Update.
2868
2869Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2870
2871 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2872 reason from here.
2873 (SignalException): To here. Signal using sim_engine_halt.
2874 (sim_stop_reason): Delete, moved to common.
2875
2876Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2877
2878 * interp.c (sim_open): Add callback argument.
2879 (sim_set_callbacks): Delete SIM_DESC argument.
2880 (sim_size): Ditto.
2881
2882Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2883
2884 * Makefile.in (SIM_OBJS): Add common modules.
2885
2886 * interp.c (sim_set_callbacks): Also set SD callback.
2887 (set_endianness, xfer_*, swap_*): Delete.
2888 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2889 Change to functions using sim-endian macros.
2890 (control_c, sim_stop): Delete, use common version.
2891 (simulate): Convert into.
2892 (sim_engine_run): This function.
2893 (sim_resume): Delete.
2894
2895 * interp.c (simulation): New variable - the simulator object.
2896 (sim_kind): Delete global - merged into simulation.
2897 (sim_load): Cleanup. Move PC assignment from here.
2898 (sim_create_inferior): To here.
2899
2900 * sim-main.h: New file.
2901 * interp.c (sim-main.h): Include.
2902
2903Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2904
2905 * configure: Regenerated to track ../common/aclocal.m4 changes.
2906
2907Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2908
2909 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2910
2911Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2912
2913 * gencode.c (build_instruction): DIV instructions: check
2914 for division by zero and integer overflow before using
2915 host's division operation.
2916
2917Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2918
2919 * Makefile.in (SIM_OBJS): Add sim-load.o.
2920 * interp.c: #include bfd.h.
2921 (target_byte_order): Delete.
2922 (sim_kind, myname, big_endian_p): New static locals.
2923 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2924 after argument parsing. Recognize -E arg, set endianness accordingly.
2925 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2926 load file into simulator. Set PC from bfd.
2927 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2928 (set_endianness): Use big_endian_p instead of target_byte_order.
2929
2930Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2931
2932 * interp.c (sim_size): Delete prototype - conflicts with
2933 definition in remote-sim.h. Correct definition.
2934
2935Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2936
2937 * configure: Regenerated to track ../common/aclocal.m4 changes.
2938 * config.in: Ditto.
2939
2940Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2941
2942 * interp.c (sim_open): New arg `kind'.
2943
2944 * configure: Regenerated to track ../common/aclocal.m4 changes.
2945
2946Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2947
2948 * configure: Regenerated to track ../common/aclocal.m4 changes.
2949
2950Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2951
2952 * interp.c (sim_open): Set optind to 0 before calling getopt.
2953
2954Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2955
2956 * configure: Regenerated to track ../common/aclocal.m4 changes.
2957
2958Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2959
2960 * interp.c : Replace uses of pr_addr with pr_uword64
2961 where the bit length is always 64 independent of SIM_ADDR.
2962 (pr_uword64) : added.
2963
2964Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2965
2966 * configure: Re-generate.
2967
2968Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2969
2970 * configure: Regenerate to track ../common/aclocal.m4 changes.
2971
2972Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2973
2974 * interp.c (sim_open): New SIM_DESC result. Argument is now
2975 in argv form.
2976 (other sim_*): New SIM_DESC argument.
2977
2978Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2979
2980 * interp.c: Fix printing of addresses for non-64-bit targets.
2981 (pr_addr): Add function to print address based on size.
2982
2983Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2984
2985 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2986
2987Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2988
2989 * gencode.c (build_mips16_operands): Correct computation of base
2990 address for extended PC relative instruction.
2991
2992Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2993
2994 * interp.c (mips16_entry): Add support for floating point cases.
2995 (SignalException): Pass floating point cases to mips16_entry.
2996 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2997 registers.
2998 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2999 or fmt_word.
3000 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
3001 and then set the state to fmt_uninterpreted.
3002 (COP_SW): Temporarily set the state to fmt_word while calling
3003 ValueFPR.
3004
3005Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
3006
3007 * gencode.c (build_instruction): The high order may be set in the
3008 comparison flags at any ISA level, not just ISA 4.
3009
3010Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
3011
3012 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
3013 COMMON_{PRE,POST}_CONFIG_FRAG instead.
3014 * configure.in: sinclude ../common/aclocal.m4.
3015 * configure: Regenerated.
3016
3017Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
3018
3019 * configure: Rebuild after change to aclocal.m4.
3020
3021Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
3022
3023 * configure configure.in Makefile.in: Update to new configure
3024 scheme which is more compatible with WinGDB builds.
3025 * configure.in: Improve comment on how to run autoconf.
3026 * configure: Re-run autoconf to get new ../common/aclocal.m4.
3027 * Makefile.in: Use autoconf substitution to install common
3028 makefile fragment.
3029
3030Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
3031
3032 * gencode.c (build_instruction): Use BigEndianCPU instead of
3033 ByteSwapMem.
3034
3035Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
3036
3037 * interp.c (sim_monitor): Make output to stdout visible in
3038 wingdb's I/O log window.
3039
3040Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
3041
3042 * support.h: Undo previous change to SIGTRAP
3043 and SIGQUIT values.
3044
3045Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
3046
3047 * interp.c (store_word, load_word): New static functions.
3048 (mips16_entry): New static function.
3049 (SignalException): Look for mips16 entry and exit instructions.
3050 (simulate): Use the correct index when setting fpr_state after
3051 doing a pending move.
3052
3053Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
3054
3055 * interp.c: Fix byte-swapping code throughout to work on
3056 both little- and big-endian hosts.
3057
3058Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
3059
3060 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3061 with gdb/config/i386/xm-windows.h.
3062
3063Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
3064
3065 * gencode.c (build_instruction): Work around MSVC++ code gen bug
3066 that messes up arithmetic shifts.
3067
3068Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
3069
3070 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
3071 SIGTRAP and SIGQUIT for _WIN32.
3072
3073Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3074
3075 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3076 force a 64 bit multiplication.
3077 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3078 destination register is 0, since that is the default mips16 nop
3079 instruction.
3080
3081Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3082
3083 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3084 (build_endian_shift): Don't check proc64.
3085 (build_instruction): Always set memval to uword64. Cast op2 to
3086 uword64 when shifting it left in memory instructions. Always use
3087 the same code for stores--don't special case proc64.
3088
3089 * gencode.c (build_mips16_operands): Fix base PC value for PC
3090 relative operands.
3091 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3092 jal instruction.
3093 * interp.c (simJALDELAYSLOT): Define.
3094 (JALDELAYSLOT): Define.
3095 (INDELAYSLOT, INJALDELAYSLOT): Define.
3096 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3097
3098Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3099
3100 * interp.c (sim_open): add flush_cache as a PMON routine
3101 (sim_monitor): handle flush_cache by ignoring it
3102
3103Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3104
3105 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3106 BigEndianMem.
3107 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3108 (BigEndianMem): Rename to ByteSwapMem and change sense.
3109 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3110 BigEndianMem references to !ByteSwapMem.
3111 (set_endianness): New function, with prototype.
3112 (sim_open): Call set_endianness.
3113 (sim_info): Use simBE instead of BigEndianMem.
3114 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3115 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3116 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3117 ifdefs, keeping the prototype declaration.
3118 (swap_word): Rewrite correctly.
3119 (ColdReset): Delete references to CONFIG. Delete endianness related
3120 code; moved to set_endianness.
3121
3122Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3123
3124 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3125 * interp.c (CHECKHILO): Define away.
3126 (simSIGINT): New macro.
3127 (membank_size): Increase from 1MB to 2MB.
3128 (control_c): New function.
3129 (sim_resume): Rename parameter signal to signal_number. Add local
3130 variable prev. Call signal before and after simulate.
3131 (sim_stop_reason): Add simSIGINT support.
3132 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3133 functions always.
3134 (sim_warning): Delete call to SignalException. Do call printf_filtered
3135 if logfh is NULL.
3136 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3137 a call to sim_warning.
3138
3139Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3140
3141 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3142 16 bit instructions.
3143
3144Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3145
3146 Add support for mips16 (16 bit MIPS implementation):
3147 * gencode.c (inst_type): Add mips16 instruction encoding types.
3148 (GETDATASIZEINSN): Define.
3149 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3150 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3151 mtlo.
3152 (MIPS16_DECODE): New table, for mips16 instructions.
3153 (bitmap_val): New static function.
3154 (struct mips16_op): Define.
3155 (mips16_op_table): New table, for mips16 operands.
3156 (build_mips16_operands): New static function.
3157 (process_instructions): If PC is odd, decode a mips16
3158 instruction. Break out instruction handling into new
3159 build_instruction function.
3160 (build_instruction): New static function, broken out of
3161 process_instructions. Check modifiers rather than flags for SHIFT
3162 bit count and m[ft]{hi,lo} direction.
3163 (usage): Pass program name to fprintf.
3164 (main): Remove unused variable this_option_optind. Change
3165 ``*loptarg++'' to ``loptarg++''.
3166 (my_strtoul): Parenthesize && within ||.
3167 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3168 (simulate): If PC is odd, fetch a 16 bit instruction, and
3169 increment PC by 2 rather than 4.
3170 * configure.in: Add case for mips16*-*-*.
3171 * configure: Rebuild.
3172
3173Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3174
3175 * interp.c: Allow -t to enable tracing in standalone simulator.
3176 Fix garbage output in trace file and error messages.
3177
3178Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3179
3180 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3181 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3182 * configure.in: Simplify using macros in ../common/aclocal.m4.
3183 * configure: Regenerated.
3184 * tconfig.in: New file.
3185
3186Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3187
3188 * interp.c: Fix bugs in 64-bit port.
3189 Use ansi function declarations for msvc compiler.
3190 Initialize and test file pointer in trace code.
3191 Prevent duplicate definition of LAST_EMED_REGNUM.
3192
3193Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3194
3195 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3196
3197Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3198
3199 * interp.c (SignalException): Check for explicit terminating
3200 breakpoint value.
3201 * gencode.c: Pass instruction value through SignalException()
3202 calls for Trap, Breakpoint and Syscall.
3203
3204Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3205
3206 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3207 only used on those hosts that provide it.
3208 * configure.in: Add sqrt() to list of functions to be checked for.
3209 * config.in: Re-generated.
3210 * configure: Re-generated.
3211
3212Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3213
3214 * gencode.c (process_instructions): Call build_endian_shift when
3215 expanding STORE RIGHT, to fix swr.
3216 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3217 clear the high bits.
3218 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3219 Fix float to int conversions to produce signed values.
3220
3221Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3222
3223 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3224 (process_instructions): Correct handling of nor instruction.
3225 Correct shift count for 32 bit shift instructions. Correct sign
3226 extension for arithmetic shifts to not shift the number of bits in
3227 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3228 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3229 Fix madd.
3230 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3231 It's OK to have a mult follow a mult. What's not OK is to have a
3232 mult follow an mfhi.
3233 (Convert): Comment out incorrect rounding code.
3234
3235Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3236
3237 * interp.c (sim_monitor): Improved monitor printf
3238 simulation. Tidied up simulator warnings, and added "--log" option
3239 for directing warning message output.
3240 * gencode.c: Use sim_warning() rather than WARNING macro.
3241
3242Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3243
3244 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3245 getopt1.o, rather than on gencode.c. Link objects together.
3246 Don't link against -liberty.
3247 (gencode.o, getopt.o, getopt1.o): New targets.
3248 * gencode.c: Include <ctype.h> and "ansidecl.h".
3249 (AND): Undefine after including "ansidecl.h".
3250 (ULONG_MAX): Define if not defined.
3251 (OP_*): Don't define macros; now defined in opcode/mips.h.
3252 (main): Call my_strtoul rather than strtoul.
3253 (my_strtoul): New static function.
3254
3255Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3256
3257 * gencode.c (process_instructions): Generate word64 and uword64
3258 instead of `long long' and `unsigned long long' data types.
3259 * interp.c: #include sysdep.h to get signals, and define default
3260 for SIGBUS.
3261 * (Convert): Work around for Visual-C++ compiler bug with type
3262 conversion.
3263 * support.h: Make things compile under Visual-C++ by using
3264 __int64 instead of `long long'. Change many refs to long long
3265 into word64/uword64 typedefs.
3266
3267Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3268
3269 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3270 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3271 (docdir): Removed.
3272 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3273 (AC_PROG_INSTALL): Added.
3274 (AC_PROG_CC): Moved to before configure.host call.
3275 * configure: Rebuilt.
3276
3277Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3278
3279 * configure.in: Define @SIMCONF@ depending on mips target.
3280 * configure: Rebuild.
3281 * Makefile.in (run): Add @SIMCONF@ to control simulator
3282 construction.
3283 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3284 * interp.c: Remove some debugging, provide more detailed error
3285 messages, update memory accesses to use LOADDRMASK.
3286
3287Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3288
3289 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3290 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3291 stamp-h.
3292 * configure: Rebuild.
3293 * config.in: New file, generated by autoheader.
3294 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3295 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3296 HAVE_ANINT and HAVE_AINT, as appropriate.
3297 * Makefile.in (run): Use @LIBS@ rather than -lm.
3298 (interp.o): Depend upon config.h.
3299 (Makefile): Just rebuild Makefile.
3300 (clean): Remove stamp-h.
3301 (mostlyclean): Make the same as clean, not as distclean.
3302 (config.h, stamp-h): New targets.
3303
3304Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3305
3306 * interp.c (ColdReset): Fix boolean test. Make all simulator
3307 globals static.
3308
3309Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3310
3311 * interp.c (xfer_direct_word, xfer_direct_long,
3312 swap_direct_word, swap_direct_long, xfer_big_word,
3313 xfer_big_long, xfer_little_word, xfer_little_long,
3314 swap_word,swap_long): Added.
3315 * interp.c (ColdReset): Provide function indirection to
3316 host<->simulated_target transfer routines.
3317 * interp.c (sim_store_register, sim_fetch_register): Updated to
3318 make use of indirected transfer routines.
3319
3320Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3321
3322 * gencode.c (process_instructions): Ensure FP ABS instruction
3323 recognised.
3324 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3325 system call support.
3326
3327Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3328
3329 * interp.c (sim_do_command): Complain if callback structure not
3330 initialised.
3331
3332Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3333
3334 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3335 support for Sun hosts.
3336 * Makefile.in (gencode): Ensure the host compiler and libraries
3337 used for cross-hosted build.
3338
3339Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3340
3341 * interp.c, gencode.c: Some more (TODO) tidying.
3342
3343Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3344
3345 * gencode.c, interp.c: Replaced explicit long long references with
3346 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3347 * support.h (SET64LO, SET64HI): Macros added.
3348
3349Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3350
3351 * configure: Regenerate with autoconf 2.7.
3352
3353Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3354
3355 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3356 * support.h: Remove superfluous "1" from #if.
3357 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3358
3359Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3360
3361 * interp.c (StoreFPR): Control UndefinedResult() call on
3362 WARN_RESULT manifest.
3363
3364Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3365
3366 * gencode.c: Tidied instruction decoding, and added FP instruction
3367 support.
3368
3369 * interp.c: Added dineroIII, and BSD profiling support. Also
3370 run-time FP handling.
3371
3372Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3373
3374 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3375 gencode.c, interp.c, support.h: created.
GDB Binutils - Deliverables
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