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2004-04-09 Chris Demetriou <cgd@broadcom.com>
[deliverable/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
c6f9085c
CD		 12004-04-09 Chris Demetriou <cgd@broadcom.com>
2
3 * sb1.igen (check_sbx): New function.
4 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
5
11d66e66 62004-03-29 Chris Demetriou <cgd@broadcom.com>
0e1b7197
RS		 7 Richard Sandiford <rsandifo@redhat.com>
8
9 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
10 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
11 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
12 separate implementations for mipsIV and mipsV. Use new macros to
13 determine whether the restrictions apply.
14
b3208fb8
CD		 152004-01-19 Chris Demetriou <cgd@broadcom.com>
16
17 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
18 (check_mult_hilo): Improve comments.
19 (check_div_hilo): Likewise. Also, fork off a new version
20 to handle mips32/mips64 (since there are no hazards to check
21 in MIPS32/MIPS64).
22
9a1d84fb
CD		 232003-06-17 Richard Sandiford <rsandifo@redhat.com>
24
25 * mips.igen (do_dmultx): Fix check for negative operands.
26
ae451ac6
ILT		 272003-05-16 Ian Lance Taylor <ian@airs.com>
28
29 * Makefile.in (SHELL): Make sure this is defined.
30 (various): Use $(SHELL) whenever we invoke move-if-change.
31
dd69d292
CD		 322003-05-03 Chris Demetriou <cgd@broadcom.com>
33
34 * cp1.c: Tweak attribution slightly.
35 * cp1.h: Likewise.
36 * mdmx.c: Likewise.
37 * mdmx.igen: Likewise.
38 * mips3d.igen: Likewise.
39 * sb1.igen: Likewise.
40
bcd0068e
CD		 412003-04-15 Richard Sandiford <rsandifo@redhat.com>
42
43 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
44 unsigned operands.
45
6b4a8935
AC		 462003-02-27 Andrew Cagney <cagney@redhat.com>
47
601da316
AC		 48 * interp.c (sim_open): Rename _bfd to bfd.
49 (sim_create_inferior): Ditto.
6b4a8935 50
d29e330f
CD		 512003-01-14 Chris Demetriou <cgd@broadcom.com>
52
53 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
54
a2353a08
CD		 552003-01-14 Chris Demetriou <cgd@broadcom.com>
56
57 * mips.igen (EI, DI): Remove.
58
80551777
CD		 592003-01-05 Richard Sandiford <rsandifo@redhat.com>
60
61 * Makefile.in (tmp-run-multi): Fix mips16 filter.
62
4c54fc26
CD		 632003-01-04 Richard Sandiford <rsandifo@redhat.com>
64 Andrew Cagney <ac131313@redhat.com>
65 Gavin Romig-Koch <gavin@redhat.com>
66 Graydon Hoare <graydon@redhat.com>
67 Aldy Hernandez <aldyh@redhat.com>
68 Dave Brolley <brolley@redhat.com>
69 Chris Demetriou <cgd@broadcom.com>
70
71 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
72 (sim_mach_default): New variable.
73 (mips64vr-*-*, mips64vrel-*-*): New configurations.
74 Add a new simulator generator, MULTI.
75 * configure: Regenerate.
76 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
77 (multi-run.o): New dependency.
78 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
79 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
80 (tmp-multi): Combine them.
81 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
82 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
83 (distclean-extra): New rule.
84 * sim-main.h: Include bfd.h.
85 (MIPS_MACH): New macro.
86 * mips.igen (vr4120, vr5400, vr5500): New models.
87 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
88 * vr.igen: Replace with new version.
89
e6c674b8
CD		 902003-01-04 Chris Demetriou <cgd@broadcom.com>
91
92 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
93 * configure: Regenerate.
94
28f50ac8
CD		 952002-12-31 Chris Demetriou <cgd@broadcom.com>
96
97 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
98 * mips.igen: Remove all invocations of check_branch_bug and
99 mark_branch_bug.
100
5071ffe6
CD		 1012002-12-16 Chris Demetriou <cgd@broadcom.com>
102
103 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
104
06e7837e
CD		 1052002-07-30 Chris Demetriou <cgd@broadcom.com>
106
107 * mips.igen (do_load_double, do_store_double): New functions.
108 (LDC1, SDC1): Rename to...
109 (LDC1b, SDC1b): respectively.
110 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
111
2265c243
MS		 1122002-07-29 Michael Snyder <msnyder@redhat.com>
113
114 * cp1.c (fp_recip2): Modify initialization expression so that
115 GCC will recognize it as constant.
116
a2f8b4f3
CD		 1172002-06-18 Chris Demetriou <cgd@broadcom.com>
118
119 * mdmx.c (SD_): Delete.
120 (Unpredictable): Re-define, for now, to directly invoke
121 unpredictable_action().
122 (mdmx_acc_op): Fix error in .ob immediate handling.
123
b4b6c939
AC		 1242002-06-18 Andrew Cagney <cagney@redhat.com>
125
126 * interp.c (sim_firmware_command): Initialize `address'.
127
c8cca39f
AC		 1282002-06-16 Andrew Cagney <ac131313@redhat.com>
129
130 * configure: Regenerated to track ../common/aclocal.m4 changes.
131
e7e81181
CD		 1322002-06-14 Chris Demetriou <cgd@broadcom.com>
133 Ed Satterthwaite <ehs@broadcom.com>
134
135 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
136 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
137 * mips.igen: Include mips3d.igen.
138 (mips3d): New model name for MIPS-3D ASE instructions.
139 (CVT.W.fmt): Don't use this instruction for word (source) format
140 instructions.
141 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
142 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
143 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
144 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
145 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
146 (RSquareRoot1, RSquareRoot2): New macros.
147 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
148 (fp_rsqrt2): New functions.
149 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
150 * configure: Regenerate.
151
3a2b820e 1522002-06-13 Chris Demetriou <cgd@broadcom.com>
eab54952 153 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 154
155 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
156 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
157 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
158 (convert): Note that this function is not used for paired-single
159 format conversions.
160 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
161 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
162 (check_fmt_p): Enable paired-single support.
163 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
164 (PUU.PS): New instructions.
165 (CVT.S.fmt): Don't use this instruction for paired-single format
166 destinations.
167 * sim-main.h (FP_formats): New value 'fmt_ps.'
168 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
169 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
170
d18ea9c2
CD		 1712002-06-12 Chris Demetriou <cgd@broadcom.com>
172
173 * mips.igen: Fix formatting of function calls in
174 many FP operations.
175
95fd5cee
CD		 1762002-06-12 Chris Demetriou <cgd@broadcom.com>
177
178 * mips.igen (MOVN, MOVZ): Trace result.
179 (TNEI): Print "tnei" as the opcode name in traces.
180 (CEIL.W): Add disassembly string for traces.
181 (RSQRT.fmt): Make location of disassembly string consistent
182 with other instructions.
183
4f0d55ae
CD		 1842002-06-12 Chris Demetriou <cgd@broadcom.com>
185
186 * mips.igen (X): Delete unused function.
187
3c25f8c7
AC		 1882002-06-08 Andrew Cagney <cagney@redhat.com>
189
190 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
191
f3c08b7e
CD		 1922002-06-07 Chris Demetriou <cgd@broadcom.com>
193 Ed Satterthwaite <ehs@broadcom.com>
194
195 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
196 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
197 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
198 (fp_nmsub): New prototypes.
199 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
200 (NegMultiplySub): New defines.
201 * mips.igen (RSQRT.fmt): Use RSquareRoot().
202 (MADD.D, MADD.S): Replace with...
203 (MADD.fmt): New instruction.
204 (MSUB.D, MSUB.S): Replace with...
205 (MSUB.fmt): New instruction.
206 (NMADD.D, NMADD.S): Replace with...
207 (NMADD.fmt): New instruction.
208 (NMSUB.D, MSUB.S): Replace with...
209 (NMSUB.fmt): New instruction.
210
52714ff9
CD		 2112002-06-07 Chris Demetriou <cgd@broadcom.com>
212 Ed Satterthwaite <ehs@broadcom.com>
213
214 * cp1.c: Fix more comment spelling and formatting.
215 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
216 (denorm_mode): New function.
217 (fpu_unary, fpu_binary): Round results after operation, collect
218 status from rounding operations, and update the FCSR.
219 (convert): Collect status from integer conversions and rounding
220 operations, and update the FCSR. Adjust NaN values that result
221 from conversions. Convert to use sim_io_eprintf rather than
222 fprintf, and remove some debugging code.
223 * cp1.h (fenr_FS): New define.
224
577d8c4b
CD		 2252002-06-07 Chris Demetriou <cgd@broadcom.com>
226
227 * cp1.c (convert): Remove unusable debugging code, and move MIPS
228 rounding mode to sim FP rounding mode flag conversion code into...
229 (rounding_mode): New function.
230
196496ed
CD		 2312002-06-07 Chris Demetriou <cgd@broadcom.com>
232
233 * cp1.c: Clean up formatting of a few comments.
234 (value_fpr): Reformat switch statement.
235
cfe9ea23
CD		 2362002-06-06 Chris Demetriou <cgd@broadcom.com>
237 Ed Satterthwaite <ehs@broadcom.com>
238
239 * cp1.h: New file.
240 * sim-main.h: Include cp1.h.
241 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
242 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
243 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
244 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
245 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
246 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
247 * cp1.c: Don't include sim-fpu.h; already included by
248 sim-main.h. Clean up formatting of some comments.
249 (NaN, Equal, Less): Remove.
250 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
251 (fp_cmp): New functions.
252 * mips.igen (do_c_cond_fmt): Remove.
253 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
254 Compare. Add result tracing.
255 (CxC1): Remove, replace with...
256 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
257 (DMxC1): Remove, replace with...
258 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
259 (MxC1): Remove, replace with...
260 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
261
ee7254b0
CD		 2622002-06-04 Chris Demetriou <cgd@broadcom.com>
263
264 * sim-main.h (FGRIDX): Remove, replace all uses with...
265 (FGR_BASE): New macro.
266 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
267 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
268 (NR_FGR, FGR): Likewise.
269 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
270 * mips.igen: Likewise.
271
d3eb724f
CD		 2722002-06-04 Chris Demetriou <cgd@broadcom.com>
273
274 * cp1.c: Add an FSF Copyright notice to this file.
275
ba46ddd0
CD		 2762002-06-04 Chris Demetriou <cgd@broadcom.com>
277 Ed Satterthwaite <ehs@broadcom.com>
278
279 * cp1.c (Infinity): Remove.
280 * sim-main.h (Infinity): Likewise.
281
282 * cp1.c (fp_unary, fp_binary): New functions.
283 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
284 (fp_sqrt): New functions, implemented in terms of the above.
285 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
286 (Recip, SquareRoot): Remove (replaced by functions above).
287 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
288 (fp_recip, fp_sqrt): New prototypes.
289 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
290 (Recip, SquareRoot): Replace prototypes with #defines which
291 invoke the functions above.
292
18d8a52d
CD		 2932002-06-03 Chris Demetriou <cgd@broadcom.com>
294
295 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
296 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
297 file, remove PARAMS from prototypes.
298 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
299 simulator state arguments.
300 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
301 pass simulator state arguments.
302 * cp1.c (SD): Redefine as CPU_STATE(cpu).
303 (store_fpr, convert): Remove 'sd' argument.
304 (value_fpr): Likewise. Convert to use 'SD' instead.
305
0f154cbd
CD		 3062002-06-03 Chris Demetriou <cgd@broadcom.com>
307
308 * cp1.c (Min, Max): Remove #if 0'd functions.
309 * sim-main.h (Min, Max): Remove.
310
e80fc152
CD		 3112002-06-03 Chris Demetriou <cgd@broadcom.com>
312
313 * cp1.c: fix formatting of switch case and default labels.
314 * interp.c: Likewise.
315 * sim-main.c: Likewise.
316
bad673a9
CD		 3172002-06-03 Chris Demetriou <cgd@broadcom.com>
318
319 * cp1.c: Clean up comments which describe FP formats.
320 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
321
7cbea089
CD		 3222002-06-03 Chris Demetriou <cgd@broadcom.com>
323 Ed Satterthwaite <ehs@broadcom.com>
324
325 * configure.in (mipsisa64sb1*-*-*): New target for supporting
326 Broadcom SiByte SB-1 processor configurations.
327 * configure: Regenerate.
328 * sb1.igen: New file.
329 * mips.igen: Include sb1.igen.
330 (sb1): New model.
331 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
332 * mdmx.igen: Add "sb1" model to all appropriate functions and
333 instructions.
334 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
335 (ob_func, ob_acc): Reference the above.
336 (qh_acc): Adjust to keep the same size as ob_acc.
337 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
338 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
339
909daa82
CD		 3402002-06-03 Chris Demetriou <cgd@broadcom.com>
341
342 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
343
f4f1b9f1
CD		 3442002-06-02 Chris Demetriou <cgd@broadcom.com>
345 Ed Satterthwaite <ehs@broadcom.com>
346
347 * mips.igen (mdmx): New (pseudo-)model.
348 * mdmx.c, mdmx.igen: New files.
349 * Makefile.in (SIM_OBJS): Add mdmx.o.
350 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
351 New typedefs.
352 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
353 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
354 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
355 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
356 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
357 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
358 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
359 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
360 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
361 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
362 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
363 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
364 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
365 (qh_fmtsel): New macros.
366 (_sim_cpu): New member "acc".
367 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
368 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
369
5accf1ff
CD		 3702002-05-01 Chris Demetriou <cgd@broadcom.com>
371
372 * interp.c: Use 'deprecated' rather than 'depreciated.'
373 * sim-main.h: Likewise.
374
402586aa
CD		 3752002-05-01 Chris Demetriou <cgd@broadcom.com>
376
377 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
378 which wouldn't compile anyway.
379 * sim-main.h (unpredictable_action): New function prototype.
380 (Unpredictable): Define to call igen function unpredictable().
381 (NotWordValue): New macro to call igen function not_word_value().
382 (UndefinedResult): Remove.
383 * interp.c (undefined_result): Remove.
384 (unpredictable_action): New function.
385 * mips.igen (not_word_value, unpredictable): New functions.
386 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
387 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
388 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
389 NotWordValue() to check for unpredictable inputs, then
390 Unpredictable() to handle them.
391
c9b9995a
CD		 3922002-02-24 Chris Demetriou <cgd@broadcom.com>
393
394 * mips.igen: Fix formatting of calls to Unpredictable().
395
e1015982
AC		 3962002-04-20 Andrew Cagney <ac131313@redhat.com>
397
398 * interp.c (sim_open): Revert previous change.
399
b882a66b
AO		 4002002-04-18 Alexandre Oliva <aoliva@redhat.com>
401
402 * interp.c (sim_open): Disable chunk of code that wrote code in
403 vector table entries.
404
c429b7dd
CD		 4052002-03-19 Chris Demetriou <cgd@broadcom.com>
406
407 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
408 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
409 unused definitions.
410
37d146fa
CD		 4112002-03-19 Chris Demetriou <cgd@broadcom.com>
412
413 * cp1.c: Fix many formatting issues.
414
07892c0b
CD		 4152002-03-19 Chris G. Demetriou <cgd@broadcom.com>
416
417 * cp1.c (fpu_format_name): New function to replace...
418 (DOFMT): This. Delete, and update all callers.
419 (fpu_rounding_mode_name): New function to replace...
420 (RMMODE): This. Delete, and update all callers.
421
487f79b7
CD		 4222002-03-19 Chris G. Demetriou <cgd@broadcom.com>
423
424 * interp.c: Move FPU support routines from here to...
425 * cp1.c: Here. New file.
426 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
427 (cp1.o): New target.
428
1e799e28
CD		 4292002-03-12 Chris Demetriou <cgd@broadcom.com>
430
431 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
432 * mips.igen (mips32, mips64): New models, add to all instructions
433 and functions as appropriate.
434 (loadstore_ea, check_u64): New variant for model mips64.
435 (check_fmt_p): New variant for models mipsV and mips64, remove
436 mipsV model marking fro other variant.
437 (SLL) Rename to...
438 (SLLa) this.
439 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
440 for mips32 and mips64.
441 (DCLO, DCLZ): New instructions for mips64.
442
82f728db
CD		 4432002-03-07 Chris Demetriou <cgd@broadcom.com>
444
445 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
446 immediate or code as a hex value with the "%#lx" format.
447 (ANDI): Likewise, and fix printed instruction name.
448
b96e7ef1
CD		 4492002-03-05 Chris Demetriou <cgd@broadcom.com>
450
451 * sim-main.h (UndefinedResult, Unpredictable): New macros
452 which currently do nothing.
453
d35d4f70
CD		 4542002-03-05 Chris Demetriou <cgd@broadcom.com>
455
456 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
457 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
458 (status_CU3): New definitions.
459
460 * sim-main.h (ExceptionCause): Add new values for MIPS32
461 and MIPS64: MDMX, MCheck, CacheErr. Update comments
462 for DebugBreakPoint and NMIReset to note their status in
463 MIPS32 and MIPS64.
464 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
465 (SignalExceptionCacheErr): New exception macros.
466
3ad6f714
CD		 4672002-03-05 Chris Demetriou <cgd@broadcom.com>
468
469 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
470 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
471 is always enabled.
472 (SignalExceptionCoProcessorUnusable): Take as argument the
473 unusable coprocessor number.
474
86b77b47
CD		 4752002-03-05 Chris Demetriou <cgd@broadcom.com>
476
477 * mips.igen: Fix formatting of all SignalException calls.
478
97a88e93 4792002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 480
481 * sim-main.h (SIGNEXTEND): Remove.
482
97a88e93 4832002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 484
485 * mips.igen: Remove gencode comment from top of file, fix
486 spelling in another comment.
487
97a88e93 4882002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 489
490 * mips.igen (check_fmt, check_fmt_p): New functions to check
491 whether specific floating point formats are usable.
492 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
493 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
494 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
495 Use the new functions.
496 (do_c_cond_fmt): Remove format checks...
497 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
498
97a88e93 4992002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 500
501 * mips.igen: Fix formatting of check_fpu calls.
502
41774c9d
CD		 5032002-03-03 Chris Demetriou <cgd@broadcom.com>
504
505 * mips.igen (FLOOR.L.fmt): Store correct destination register.
506
4a0bd876
CD		 5072002-03-03 Chris Demetriou <cgd@broadcom.com>
508
509 * mips.igen: Remove whitespace at end of lines.
510
09297648
CD		 5112002-03-02 Chris Demetriou <cgd@broadcom.com>
512
513 * mips.igen (loadstore_ea): New function to do effective
514 address calculations.
515 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
516 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
517 CACHE): Use loadstore_ea to do effective address computations.
518
043b7057
CD		 5192002-03-02 Chris Demetriou <cgd@broadcom.com>
520
521 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
522 * mips.igen (LL, CxC1, MxC1): Likewise.
523
c1e8ada4
CD		 5242002-03-02 Chris Demetriou <cgd@broadcom.com>
525
526 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
527 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
528 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
529 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
530 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
531 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
532 Don't split opcode fields by hand, use the opcode field values
533 provided by igen.
534
3e1dca16
CD		 5352002-03-01 Chris Demetriou <cgd@broadcom.com>
536
537 * mips.igen (do_divu): Fix spacing.
538
539 * mips.igen (do_dsllv): Move to be right before DSLLV,
540 to match the rest of the do_<shift> functions.
541
fff8d27d
CD		 5422002-03-01 Chris Demetriou <cgd@broadcom.com>
543
544 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
545 DSRL32, do_dsrlv): Trace inputs and results.
546
0d3e762b
CD		 5472002-03-01 Chris Demetriou <cgd@broadcom.com>
548
549 * mips.igen (CACHE): Provide instruction-printing string.
550
551 * interp.c (signal_exception): Comment tokens after #endif.
552
eb5fcf93
CD		 5532002-02-28 Chris Demetriou <cgd@broadcom.com>
554
555 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
556 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
557 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
558 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
559 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
560 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
561 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
562 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
563
bb22bd7d
CD		 5642002-02-28 Chris Demetriou <cgd@broadcom.com>
565
566 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
567 instruction-printing string.
568 (LWU): Use '64' as the filter flag.
569
91a177cf
CD		 5702002-02-28 Chris Demetriou <cgd@broadcom.com>
571
572 * mips.igen (SDXC1): Fix instruction-printing string.
573
387f484a
CD		 5742002-02-28 Chris Demetriou <cgd@broadcom.com>
575
576 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
577 filter flags "32,f".
578
3d81f391
CD		 5792002-02-27 Chris Demetriou <cgd@broadcom.com>
580
581 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
582 as the filter flag.
583
af5107af
CD		 5842002-02-27 Chris Demetriou <cgd@broadcom.com>
585
586 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
587 add a comma) so that it more closely match the MIPS ISA
588 documentation opcode partitioning.
589 (PREF): Put useful names on opcode fields, and include
590 instruction-printing string.
591
ca971540
CD		 5922002-02-27 Chris Demetriou <cgd@broadcom.com>
593
594 * mips.igen (check_u64): New function which in the future will
595 check whether 64-bit instructions are usable and signal an
596 exception if not. Currently a no-op.
597 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
598 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
599 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
600 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
601
602 * mips.igen (check_fpu): New function which in the future will
603 check whether FPU instructions are usable and signal an exception
604 if not. Currently a no-op.
605 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
606 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
607 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
608 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
609 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
610 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
611 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
612 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
613
1c47a468
CD		 6142002-02-27 Chris Demetriou <cgd@broadcom.com>
615
616 * mips.igen (do_load_left, do_load_right): Move to be immediately
617 following do_load.
618 (do_store_left, do_store_right): Move to be immediately following
619 do_store.
620
603a98e7
CD		 6212002-02-27 Chris Demetriou <cgd@broadcom.com>
622
623 * mips.igen (mipsV): New model name. Also, add it to
624 all instructions and functions where it is appropriate.
625
c5d00cc7
CD		 6262002-02-18 Chris Demetriou <cgd@broadcom.com>
627
628 * mips.igen: For all functions and instructions, list model
629 names that support that instruction one per line.
630
074e9cb8
CD		 6312002-02-11 Chris Demetriou <cgd@broadcom.com>
632
633 * mips.igen: Add some additional comments about supported
634 models, and about which instructions go where.
635 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
636 order as is used in the rest of the file.
637
9805e229
CD		 6382002-02-11 Chris Demetriou <cgd@broadcom.com>
639
640 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
641 indicating that ALU32_END or ALU64_END are there to check
642 for overflow.
643 (DADD): Likewise, but also remove previous comment about
644 overflow checking.
645
f701dad2
CD		 6462002-02-10 Chris Demetriou <cgd@broadcom.com>
647
648 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
649 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
650 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
651 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
652 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
653 fields (i.e., add and move commas) so that they more closely
654 match the MIPS ISA documentation opcode partitioning.
655
6562002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098
CD		 657
658 * mips.igen (ADDI): Print immediate value.
659 (BREAK): Print code.
660 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
661 (SLL): Print "nop" specially, and don't run the code
662 that does the shift for the "nop" case.
663
9e52972e
FF		 6642001-11-17 Fred Fish <fnf@redhat.com>
665
666 * sim-main.h (float_operation): Move enum declaration outside
667 of _sim_cpu struct declaration.
668
c0efbca4
JB		 6692001-04-12 Jim Blandy <jimb@redhat.com>
670
671 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
672 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
673 set of the FCSR.
674 * sim-main.h (COCIDX): Remove definition; this isn't supported by
675 PENDING_FILL, and you can get the intended effect gracefully by
676 calling PENDING_SCHED directly.
677
fb891446
BE		 6782001-02-23 Ben Elliston <bje@redhat.com>
679
680 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
681 already defined elsewhere.
682
8030f857
BE		 6832001-02-19 Ben Elliston <bje@redhat.com>
684
685 * sim-main.h (sim_monitor): Return an int.
686 * interp.c (sim_monitor): Add return values.
687 (signal_exception): Handle error conditions from sim_monitor.
688
56b48a7a
CD		 6892001-02-08 Ben Elliston <bje@redhat.com>
690
691 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
692 (store_memory): Likewise, pass cia to sim_core_write*.
693
d3ee60d9
FCE		 6942000-10-19 Frank Ch. Eigler <fche@redhat.com>
695
696 On advice from Chris G. Demetriou <cgd@sibyte.com>:
697 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
698
071da002
AC		 699Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
700
701 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
702 * Makefile.in: Don't delete *.igen when cleaning directory.
703
a28c02cd
AC		 704Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
705
706 * m16.igen (break): Call SignalException not sim_engine_halt.
707
80ee11fa
AC		 708Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
709
710 From Jason Eckhardt:
711 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
712
673388c0
AC		 713Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
714
715 * mips.igen (MxC1, DMxC1): Fix printf formatting.
716
4c0deff4
NC		 7172000-05-24 Michael Hayes <mhayes@cygnus.com>
718
719 * mips.igen (do_dmultx): Fix typo.
720
eb2d80b4
AC		 721Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
722
723 * configure: Regenerated to track ../common/aclocal.m4 changes.
724
dd37a34b
AC		 725Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
726
727 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
728
4c0deff4
NC		 7292000-04-12 Frank Ch. Eigler <fche@redhat.com>
730
731 * sim-main.h (GPR_CLEAR): Define macro.
732
e30db738
AC		 733Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
734
735 * interp.c (decode_coproc): Output long using %lx and not %s.
736
cb7450ea
FCE		 7372000-03-21 Frank Ch. Eigler <fche@redhat.com>
738
739 * interp.c (sim_open): Sort & extend dummy memory regions for
740 --board=jmr3904 for eCos.
741
a3027dd7
FCE		 7422000-03-02 Frank Ch. Eigler <fche@redhat.com>
743
744 * configure: Regenerated.
745
746Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
747
748 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
749 calls, conditional on the simulator being in verbose mode.
750
dfcd3bfb
JM		 751Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
752
753 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
754 cache don't get ReservedInstruction traps.
755
c2d11a7d
JM		 7561999-11-29 Mark Salter <msalter@cygnus.com>
757
758 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
759 to clear status bits in sdisr register. This is how the hardware works.
760
761 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
762 being used by cygmon.
763
4ce44c66
JM		 7641999-11-11 Andrew Haley <aph@cygnus.com>
765
766 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
767 instructions.
768
cff3e48b
JM		 769Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
770
771 * mips.igen (MULT): Correct previous mis-applied patch.
772
d4f3574e
SS		 773Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
774
775 * mips.igen (delayslot32): Handle sequence like
776 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
777 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
778 (MULT): Actually pass the third register...
779
7801999-09-03 Mark Salter <msalter@cygnus.com>
781
782 * interp.c (sim_open): Added more memory aliases for additional
783 hardware being touched by cygmon on jmr3904 board.
784
785Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
786
787 * configure: Regenerated to track ../common/aclocal.m4 changes.
788
a0b3c4fd
JM		 789Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
790
791 * interp.c (sim_store_register): Handle case where client - GDB -
792 specifies that a 4 byte register is 8 bytes in size.
793 (sim_fetch_register): Ditto.
794
adf40b2e
JM		 7951999-07-14 Frank Ch. Eigler <fche@cygnus.com>
796
797 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
798 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
799 (idt_monitor_base): Base address for IDT monitor traps.
800 (pmon_monitor_base): Ditto for PMON.
801 (lsipmon_monitor_base): Ditto for LSI PMON.
802 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
803 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
804 (sim_firmware_command): New function.
805 (mips_option_handler): Call it for OPTION_FIRMWARE.
806 (sim_open): Allocate memory for idt_monitor region. If "--board"
807 option was given, add no monitor by default. Add BREAK hooks only if
808 monitors are also there.
809
43e526b9
JM		 810Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
811
812 * interp.c (sim_monitor): Flush output before reading input.
813
814Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
815
816 * tconfig.in (SIM_HANDLES_LMA): Always define.
817
818Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
819
820 From Mark Salter <msalter@cygnus.com>:
821 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
822 (sim_open): Add setup for BSP board.
823
9846de1b
JM		 824Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
825
826 * mips.igen (MULT, MULTU): Add syntax for two operand version.
827 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
828 them as unimplemented.
829
cd0fc7c3
SS		 8301999-05-08 Felix Lee <flee@cygnus.com>
831
832 * configure: Regenerated to track ../common/aclocal.m4 changes.
833
7a292a7a
SS		 8341999-04-21 Frank Ch. Eigler <fche@cygnus.com>
835
836 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
837
838Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
839
840 * configure.in: Any mips64vr5*-*-* target should have
841 -DTARGET_ENABLE_FR=1.
842 (default_endian): Any mips64vr*el-*-* target should default to
843 LITTLE_ENDIAN.
844 * configure: Re-generate.
845
8461999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
847
848 * mips.igen (ldl): Extend from _16_, not 32.
849
850Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
851
852 * interp.c (sim_store_register): Force registers written to by GDB
853 into an un-interpreted state.
854
c906108c
SS		 8551999-02-05 Frank Ch. Eigler <fche@cygnus.com>
856
857 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
858 CPU, start periodic background I/O polls.
859 (tx3904sio_poll): New function: periodic I/O poller.
860
8611998-12-30 Frank Ch. Eigler <fche@cygnus.com>
862
863 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
864
865Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
866
867 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
868 case statement.
869
8701998-12-29 Frank Ch. Eigler <fche@cygnus.com>
871
872 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
873 (load_word): Call SIM_CORE_SIGNAL hook on error.
874 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
875 starting. For exception dispatching, pass PC instead of NULL_CIA.
876 (decode_coproc): Use COP0_BADVADDR to store faulting address.
877 * sim-main.h (COP0_BADVADDR): Define.
878 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
879 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
880 (_sim_cpu): Add exc_* fields to store register value snapshots.
881 * mips.igen (*): Replace memory-related SignalException* calls
882 with references to SIM_CORE_SIGNAL hook.
883
884 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
885 fix.
886 * sim-main.c (*): Minor warning cleanups.
887
8881998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
889
890 * m16.igen (DADDIU5): Correct type-o.
891
892Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
893
894 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
895 variables.
896
897Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
898
899 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
900 to include path.
901 (interp.o): Add dependency on itable.h
902 (oengine.c, gencode): Delete remaining references.
903 (BUILT_SRC_FROM_GEN): Clean up.
904
9051998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
906
907 * vr4run.c: New.
908 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
909 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
910 tmp-run-hack) : New.
911 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
912 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
913 Drop the "64" qualifier to get the HACK generator working.
914 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
915 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
916 qualifier to get the hack generator working.
917 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
918 (DSLL): Use do_dsll.
919 (DSLLV): Use do_dsllv.
920 (DSRA): Use do_dsra.
921 (DSRL): Use do_dsrl.
922 (DSRLV): Use do_dsrlv.
923 (BC1): Move *vr4100 to get the HACK generator working.
924 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
925 get the HACK generator working.
926 (MACC) Rename to get the HACK generator working.
927 (DMACC,MACCS,DMACCS): Add the 64.
928
9291998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
930
931 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
932 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
933
9341998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
935
936 * mips/interp.c (DEBUG): Cleanups.
937
9381998-12-10 Frank Ch. Eigler <fche@cygnus.com>
939
940 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
941 (tx3904sio_tickle): fflush after a stdout character output.
942
9431998-12-03 Frank Ch. Eigler <fche@cygnus.com>
944
945 * interp.c (sim_close): Uninstall modules.
946
947Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
948
949 * sim-main.h, interp.c (sim_monitor): Change to global
950 function.
951
952Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
953
954 * configure.in (vr4100): Only include vr4100 instructions in
955 simulator.
956 * configure: Re-generate.
957 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
958
959Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
960
961 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
962 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
963 true alternative.
964
965 * configure.in (sim_default_gen, sim_use_gen): Replace with
966 sim_gen.
967 (--enable-sim-igen): Delete config option. Always using IGEN.
968 * configure: Re-generate.
969
970 * Makefile.in (gencode): Kill, kill, kill.
971 * gencode.c: Ditto.
972
973Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
974
975 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
976 bit mips16 igen simulator.
977 * configure: Re-generate.
978
979 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
980 as part of vr4100 ISA.
981 * vr.igen: Mark all instructions as 64 bit only.
982
983Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
984
985 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
986 Pacify GCC.
987
988Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
989
990 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
991 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
992 * configure: Re-generate.
993
994 * m16.igen (BREAK): Define breakpoint instruction.
995 (JALX32): Mark instruction as mips16 and not r3900.
996 * mips.igen (C.cond.fmt): Fix typo in instruction format.
997
998 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
999
1000Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1001
1002 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1003 insn as a debug breakpoint.
1004
1005 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1006 pending.slot_size.
1007 (PENDING_SCHED): Clean up trace statement.
1008 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1009 (PENDING_FILL): Delay write by only one cycle.
1010 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1011
1012 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1013 of pending writes.
1014 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1015 32 & 64.
1016 (pending_tick): Move incrementing of index to FOR statement.
1017 (pending_tick): Only update PENDING_OUT after a write has occured.
1018
1019 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1020 build simulator.
1021 * configure: Re-generate.
1022
1023 * interp.c (sim_engine_run OLD): Delete explicit call to
1024 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1025
1026Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1027
1028 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1029 interrupt level number to match changed SignalExceptionInterrupt
1030 macro.
1031
1032Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1033
1034 * interp.c: #include "itable.h" if WITH_IGEN.
1035 (get_insn_name): New function.
1036 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1037 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1038
1039Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1040
1041 * configure: Rebuilt to inhale new common/aclocal.m4.
1042
1043Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1044
1045 * dv-tx3904sio.c: Include sim-assert.h.
1046
1047Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1048
1049 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1050 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1051 Reorganize target-specific sim-hardware checks.
1052 * configure: rebuilt.
1053 * interp.c (sim_open): For tx39 target boards, set
1054 OPERATING_ENVIRONMENT, add tx3904sio devices.
1055 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1056 ROM executables. Install dv-sockser into sim-modules list.
1057
1058 * dv-tx3904irc.c: Compiler warning clean-up.
1059 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1060 frequent hw-trace messages.
1061
1062Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1063
1064 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1065
1066Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1067
1068 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1069
1070 * vr.igen: New file.
1071 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1072 * mips.igen: Define vr4100 model. Include vr.igen.
1073Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1074
1075 * mips.igen (check_mf_hilo): Correct check.
1076
1077Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1078
1079 * sim-main.h (interrupt_event): Add prototype.
1080
1081 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1082 register_ptr, register_value.
1083 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1084
1085 * sim-main.h (tracefh): Make extern.
1086
1087Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1088
1089 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1090 Reduce unnecessarily high timer event frequency.
1091 * dv-tx3904cpu.c: Ditto for interrupt event.
1092
1093Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1094
1095 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1096 to allay warnings.
1097 (interrupt_event): Made non-static.
1098
1099 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1100 interchange of configuration values for external vs. internal
1101 clock dividers.
1102
1103Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1104
1105 * mips.igen (BREAK): Moved code to here for
1106 simulator-reserved break instructions.
1107 * gencode.c (build_instruction): Ditto.
1108 * interp.c (signal_exception): Code moved from here. Non-
1109 reserved instructions now use exception vector, rather
1110 than halting sim.
1111 * sim-main.h: Moved magic constants to here.
1112
1113Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1114
1115 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1116 register upon non-zero interrupt event level, clear upon zero
1117 event value.
1118 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1119 by passing zero event value.
1120 (*_io_{read,write}_buffer): Endianness fixes.
1121 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1122 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1123
1124 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1125 serial I/O and timer module at base address 0xFFFF0000.
1126
1127Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1128
1129 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1130 and BigEndianCPU.
1131
1132Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1133
1134 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1135 parts.
1136 * configure: Update.
1137
1138Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1139
1140 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1141 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1142 * configure.in: Include tx3904tmr in hw_device list.
1143 * configure: Rebuilt.
1144 * interp.c (sim_open): Instantiate three timer instances.
1145 Fix address typo of tx3904irc instance.
1146
1147Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1148
1149 * interp.c (signal_exception): SystemCall exception now uses
1150 the exception vector.
1151
1152Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1153
1154 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1155 to allay warnings.
1156
1157Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1158
1159 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1160
1161Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1162
1163 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1164
1165 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1166 sim-main.h. Declare a struct hw_descriptor instead of struct
1167 hw_device_descriptor.
1168
1169Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1170
1171 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1172 right bits and then re-align left hand bytes to correct byte
1173 lanes. Fix incorrect computation in do_store_left when loading
1174 bytes from second word.
1175
1176Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1177
1178 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1179 * interp.c (sim_open): Only create a device tree when HW is
1180 enabled.
1181
1182 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1183 * interp.c (signal_exception): Ditto.
1184
1185Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1186
1187 * gencode.c: Mark BEGEZALL as LIKELY.
1188
1189Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1190
1191 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1192 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1193
1194Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1195
1196 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1197 modules. Recognize TX39 target with "mips*tx39" pattern.
1198 * configure: Rebuilt.
1199 * sim-main.h (*): Added many macros defining bits in
1200 TX39 control registers.
1201 (SignalInterrupt): Send actual PC instead of NULL.
1202 (SignalNMIReset): New exception type.
1203 * interp.c (board): New variable for future use to identify
1204 a particular board being simulated.
1205 (mips_option_handler,mips_options): Added "--board" option.
1206 (interrupt_event): Send actual PC.
1207 (sim_open): Make memory layout conditional on board setting.
1208 (signal_exception): Initial implementation of hardware interrupt
1209 handling. Accept another break instruction variant for simulator
1210 exit.
1211 (decode_coproc): Implement RFE instruction for TX39.
1212 (mips.igen): Decode RFE instruction as such.
1213 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1214 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1215 bbegin to implement memory map.
1216 * dv-tx3904cpu.c: New file.
1217 * dv-tx3904irc.c: New file.
1218
1219Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1220
1221 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1222
1223Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1224
1225 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1226 with calls to check_div_hilo.
1227
1228Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1229
1230 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1231 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1232 Add special r3900 version of do_mult_hilo.
1233 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1234 with calls to check_mult_hilo.
1235 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1236 with calls to check_div_hilo.
1237
1238Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1239
1240 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1241 Document a replacement.
1242
1243Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1244
1245 * interp.c (sim_monitor): Make mon_printf work.
1246
1247Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1248
1249 * sim-main.h (INSN_NAME): New arg `cpu'.
1250
1251Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1252
1253 * configure: Regenerated to track ../common/aclocal.m4 changes.
1254
1255Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1256
1257 * configure: Regenerated to track ../common/aclocal.m4 changes.
1258 * config.in: Ditto.
1259
1260Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1261
1262 * acconfig.h: New file.
1263 * configure.in: Reverted change of Apr 24; use sinclude again.
1264
1265Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1266
1267 * configure: Regenerated to track ../common/aclocal.m4 changes.
1268 * config.in: Ditto.
1269
1270Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1271
1272 * configure.in: Don't call sinclude.
1273
1274Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1275
1276 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1277
1278Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1279
1280 * mips.igen (ERET): Implement.
1281
1282 * interp.c (decode_coproc): Return sign-extended EPC.
1283
1284 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1285
1286 * interp.c (signal_exception): Do not ignore Trap.
1287 (signal_exception): On TRAP, restart at exception address.
1288 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1289 (signal_exception): Update.
1290 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1291 so that TRAP instructions are caught.
1292
1293Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1294
1295 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1296 contains HI/LO access history.
1297 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1298 (HIACCESS, LOACCESS): Delete, replace with
1299 (HIHISTORY, LOHISTORY): New macros.
1300 (CHECKHILO): Delete all, moved to mips.igen
1301
1302 * gencode.c (build_instruction): Do not generate checks for
1303 correct HI/LO register usage.
1304
1305 * interp.c (old_engine_run): Delete checks for correct HI/LO
1306 register usage.
1307
1308 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1309 check_mf_cycles): New functions.
1310 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1311 do_divu, domultx, do_mult, do_multu): Use.
1312
1313 * tx.igen ("madd", "maddu"): Use.
1314
1315Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1316
1317 * mips.igen (DSRAV): Use function do_dsrav.
1318 (SRAV): Use new function do_srav.
1319
1320 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1321 (B): Sign extend 11 bit immediate.
1322 (EXT-B*): Shift 16 bit immediate left by 1.
1323 (ADDIU*): Don't sign extend immediate value.
1324
1325Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1326
1327 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1328
1329 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1330 functions.
1331
1332 * mips.igen (delayslot32, nullify_next_insn): New functions.
1333 (m16.igen): Always include.
1334 (do_*): Add more tracing.
1335
1336 * m16.igen (delayslot16): Add NIA argument, could be called by a
1337 32 bit MIPS16 instruction.
1338
1339 * interp.c (ifetch16): Move function from here.
1340 * sim-main.c (ifetch16): To here.
1341
1342 * sim-main.c (ifetch16, ifetch32): Update to match current
1343 implementations of LH, LW.
1344 (signal_exception): Don't print out incorrect hex value of illegal
1345 instruction.
1346
1347Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1348
1349 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1350 instruction.
1351
1352 * m16.igen: Implement MIPS16 instructions.
1353
1354 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1355 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1356 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1357 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1358 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1359 bodies of corresponding code from 32 bit insn to these. Also used
1360 by MIPS16 versions of functions.
1361
1362 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1363 (IMEM16): Drop NR argument from macro.
1364
1365Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1366
1367 * Makefile.in (SIM_OBJS): Add sim-main.o.
1368
1369 * sim-main.h (address_translation, load_memory, store_memory,
1370 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1371 as INLINE_SIM_MAIN.
1372 (pr_addr, pr_uword64): Declare.
1373 (sim-main.c): Include when H_REVEALS_MODULE_P.
1374
1375 * interp.c (address_translation, load_memory, store_memory,
1376 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1377 from here.
1378 * sim-main.c: To here. Fix compilation problems.
1379
1380 * configure.in: Enable inlining.
1381 * configure: Re-config.
1382
1383Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1384
1385 * configure: Regenerated to track ../common/aclocal.m4 changes.
1386
1387Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1388
1389 * mips.igen: Include tx.igen.
1390 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1391 * tx.igen: New file, contains MADD and MADDU.
1392
1393 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1394 the hardwired constant `7'.
1395 (store_memory): Ditto.
1396 (LOADDRMASK): Move definition to sim-main.h.
1397
1398 mips.igen (MTC0): Enable for r3900.
1399 (ADDU): Add trace.
1400
1401 mips.igen (do_load_byte): Delete.
1402 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1403 do_store_right): New functions.
1404 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1405
1406 configure.in: Let the tx39 use igen again.
1407 configure: Update.
1408
1409Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1410
1411 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1412 not an address sized quantity. Return zero for cache sizes.
1413
1414Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1415
1416 * mips.igen (r3900): r3900 does not support 64 bit integer
1417 operations.
1418
1419Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1420
1421 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1422 than igen one.
1423 * configure : Rebuild.
1424
1425Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1426
1427 * configure: Regenerated to track ../common/aclocal.m4 changes.
1428
1429Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1430
1431 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1432
1433Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1434
1435 * configure: Regenerated to track ../common/aclocal.m4 changes.
1436 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1437
1438Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1439
1440 * configure: Regenerated to track ../common/aclocal.m4 changes.
1441
1442Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1443
1444 * interp.c (Max, Min): Comment out functions. Not yet used.
1445
1446Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1447
1448 * configure: Regenerated to track ../common/aclocal.m4 changes.
1449
1450Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1451
1452 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1453 configurable settings for stand-alone simulator.
1454
1455 * configure.in: Added X11 search, just in case.
1456
1457 * configure: Regenerated.
1458
1459Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1460
1461 * interp.c (sim_write, sim_read, load_memory, store_memory):
1462 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1463
1464Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1465
1466 * sim-main.h (GETFCC): Return an unsigned value.
1467
1468Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1469
1470 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1471 (DADD): Result destination is RD not RT.
1472
1473Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1474
1475 * sim-main.h (HIACCESS, LOACCESS): Always define.
1476
1477 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1478
1479 * interp.c (sim_info): Delete.
1480
1481Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1482
1483 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1484 (mips_option_handler): New argument `cpu'.
1485 (sim_open): Update call to sim_add_option_table.
1486
1487Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1488
1489 * mips.igen (CxC1): Add tracing.
1490
1491Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1492
1493 * sim-main.h (Max, Min): Declare.
1494
1495 * interp.c (Max, Min): New functions.
1496
1497 * mips.igen (BC1): Add tracing.
1498
1499Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1500
1501 * interp.c Added memory map for stack in vr4100
1502
1503Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1504
1505 * interp.c (load_memory): Add missing "break"'s.
1506
1507Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1508
1509 * interp.c (sim_store_register, sim_fetch_register): Pass in
1510 length parameter. Return -1.
1511
1512Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1513
1514 * interp.c: Added hardware init hook, fixed warnings.
1515
1516Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1517
1518 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1519
1520Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1521
1522 * interp.c (ifetch16): New function.
1523
1524 * sim-main.h (IMEM32): Rename IMEM.
1525 (IMEM16_IMMED): Define.
1526 (IMEM16): Define.
1527 (DELAY_SLOT): Update.
1528
1529 * m16run.c (sim_engine_run): New file.
1530
1531 * m16.igen: All instructions except LB.
1532 (LB): Call do_load_byte.
1533 * mips.igen (do_load_byte): New function.
1534 (LB): Call do_load_byte.
1535
1536 * mips.igen: Move spec for insn bit size and high bit from here.
1537 * Makefile.in (tmp-igen, tmp-m16): To here.
1538
1539 * m16.dc: New file, decode mips16 instructions.
1540
1541 * Makefile.in (SIM_NO_ALL): Define.
1542 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1543
1544Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1545
1546 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1547 point unit to 32 bit registers.
1548 * configure: Re-generate.
1549
1550Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1551
1552 * configure.in (sim_use_gen): Make IGEN the default simulator
1553 generator for generic 32 and 64 bit mips targets.
1554 * configure: Re-generate.
1555
1556Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1557
1558 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1559 bitsize.
1560
1561 * interp.c (sim_fetch_register, sim_store_register): Read/write
1562 FGR from correct location.
1563 (sim_open): Set size of FGR's according to
1564 WITH_TARGET_FLOATING_POINT_BITSIZE.
1565
1566 * sim-main.h (FGR): Store floating point registers in a separate
1567 array.
1568
1569Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1570
1571 * configure: Regenerated to track ../common/aclocal.m4 changes.
1572
1573Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1574
1575 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1576
1577 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1578
1579 * interp.c (pending_tick): New function. Deliver pending writes.
1580
1581 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1582 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1583 it can handle mixed sized quantites and single bits.
1584
1585Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1586
1587 * interp.c (oengine.h): Do not include when building with IGEN.
1588 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1589 (sim_info): Ditto for PROCESSOR_64BIT.
1590 (sim_monitor): Replace ut_reg with unsigned_word.
1591 (*): Ditto for t_reg.
1592 (LOADDRMASK): Define.
1593 (sim_open): Remove defunct check that host FP is IEEE compliant,
1594 using software to emulate floating point.
1595 (value_fpr, ...): Always compile, was conditional on HASFPU.
1596
1597Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1598
1599 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1600 size.
1601
1602 * interp.c (SD, CPU): Define.
1603 (mips_option_handler): Set flags in each CPU.
1604 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1605 (sim_close): Do not clear STATE, deleted anyway.
1606 (sim_write, sim_read): Assume CPU zero's vm should be used for
1607 data transfers.
1608 (sim_create_inferior): Set the PC for all processors.
1609 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1610 argument.
1611 (mips16_entry): Pass correct nr of args to store_word, load_word.
1612 (ColdReset): Cold reset all cpu's.
1613 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1614 (sim_monitor, load_memory, store_memory, signal_exception): Use
1615 `CPU' instead of STATE_CPU.
1616
1617
1618 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1619 SD or CPU_.
1620
1621 * sim-main.h (signal_exception): Add sim_cpu arg.
1622 (SignalException*): Pass both SD and CPU to signal_exception.
1623 * interp.c (signal_exception): Update.
1624
1625 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1626 Ditto
1627 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1628 address_translation): Ditto
1629 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1630
1631Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1632
1633 * configure: Regenerated to track ../common/aclocal.m4 changes.
1634
1635Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1636
1637 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1638
1639 * mips.igen (model): Map processor names onto BFD name.
1640
1641 * sim-main.h (CPU_CIA): Delete.
1642 (SET_CIA, GET_CIA): Define
1643
1644Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1645
1646 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1647 regiser.
1648
1649 * configure.in (default_endian): Configure a big-endian simulator
1650 by default.
1651 * configure: Re-generate.
1652
1653Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1654
1655 * configure: Regenerated to track ../common/aclocal.m4 changes.
1656
1657Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1658
1659 * interp.c (sim_monitor): Handle Densan monitor outbyte
1660 and inbyte functions.
1661
16621997-12-29 Felix Lee <flee@cygnus.com>
1663
1664 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1665
1666Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1667
1668 * Makefile.in (tmp-igen): Arrange for $zero to always be
1669 reset to zero after every instruction.
1670
1671Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1672
1673 * configure: Regenerated to track ../common/aclocal.m4 changes.
1674 * config.in: Ditto.
1675
1676Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1677
1678 * mips.igen (MSUB): Fix to work like MADD.
1679 * gencode.c (MSUB): Similarly.
1680
1681Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1682
1683 * configure: Regenerated to track ../common/aclocal.m4 changes.
1684
1685Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1686
1687 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1688
1689Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1690
1691 * sim-main.h (sim-fpu.h): Include.
1692
1693 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1694 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1695 using host independant sim_fpu module.
1696
1697Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1698
1699 * interp.c (signal_exception): Report internal errors with SIGABRT
1700 not SIGQUIT.
1701
1702 * sim-main.h (C0_CONFIG): New register.
1703 (signal.h): No longer include.
1704
1705 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1706
1707Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1708
1709 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1710
1711Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1712
1713 * mips.igen: Tag vr5000 instructions.
1714 (ANDI): Was missing mipsIV model, fix assembler syntax.
1715 (do_c_cond_fmt): New function.
1716 (C.cond.fmt): Handle mips I-III which do not support CC field
1717 separatly.
1718 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1719 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1720 in IV3.2 spec.
1721 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1722 vr5000 which saves LO in a GPR separatly.
1723
1724 * configure.in (enable-sim-igen): For vr5000, select vr5000
1725 specific instructions.
1726 * configure: Re-generate.
1727
1728Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1729
1730 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1731
1732 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1733 fmt_uninterpreted_64 bit cases to switch. Convert to
1734 fmt_formatted,
1735
1736 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1737
1738 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1739 as specified in IV3.2 spec.
1740 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1741
1742Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1743
1744 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1745 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1746 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1747 PENDING_FILL versions of instructions. Simplify.
1748 (X): New function.
1749 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1750 instructions.
1751 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1752 a signed value.
1753 (MTHI, MFHI): Disable code checking HI-LO.
1754
1755 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1756 global.
1757 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1758
1759Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1760
1761 * gencode.c (build_mips16_operands): Replace IPC with cia.
1762
1763 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1764 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1765 IPC to `cia'.
1766 (UndefinedResult): Replace function with macro/function
1767 combination.
1768 (sim_engine_run): Don't save PC in IPC.
1769
1770 * sim-main.h (IPC): Delete.
1771
1772
1773 * interp.c (signal_exception, store_word, load_word,
1774 address_translation, load_memory, store_memory, cache_op,
1775 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1776 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1777 current instruction address - cia - argument.
1778 (sim_read, sim_write): Call address_translation directly.
1779 (sim_engine_run): Rename variable vaddr to cia.
1780 (signal_exception): Pass cia to sim_monitor
1781
1782 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1783 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1784 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1785
1786 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1787 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1788 SIM_ASSERT.
1789
1790 * interp.c (signal_exception): Pass restart address to
1791 sim_engine_restart.
1792
1793 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1794 idecode.o): Add dependency.
1795
1796 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1797 Delete definitions
1798 (DELAY_SLOT): Update NIA not PC with branch address.
1799 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1800
1801 * mips.igen: Use CIA not PC in branch calculations.
1802 (illegal): Call SignalException.
1803 (BEQ, ADDIU): Fix assembler.
1804
1805Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1806
1807 * m16.igen (JALX): Was missing.
1808
1809 * configure.in (enable-sim-igen): New configuration option.
1810 * configure: Re-generate.
1811
1812 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1813
1814 * interp.c (load_memory, store_memory): Delete parameter RAW.
1815 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1816 bypassing {load,store}_memory.
1817
1818 * sim-main.h (ByteSwapMem): Delete definition.
1819
1820 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1821
1822 * interp.c (sim_do_command, sim_commands): Delete mips specific
1823 commands. Handled by module sim-options.
1824
1825 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1826 (WITH_MODULO_MEMORY): Define.
1827
1828 * interp.c (sim_info): Delete code printing memory size.
1829
1830 * interp.c (mips_size): Nee sim_size, delete function.
1831 (power2): Delete.
1832 (monitor, monitor_base, monitor_size): Delete global variables.
1833 (sim_open, sim_close): Delete code creating monitor and other
1834 memory regions. Use sim-memopts module, via sim_do_commandf, to
1835 manage memory regions.
1836 (load_memory, store_memory): Use sim-core for memory model.
1837
1838 * interp.c (address_translation): Delete all memory map code
1839 except line forcing 32 bit addresses.
1840
1841Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1842
1843 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1844 trace options.
1845
1846 * interp.c (logfh, logfile): Delete globals.
1847 (sim_open, sim_close): Delete code opening & closing log file.
1848 (mips_option_handler): Delete -l and -n options.
1849 (OPTION mips_options): Ditto.
1850
1851 * interp.c (OPTION mips_options): Rename option trace to dinero.
1852 (mips_option_handler): Update.
1853
1854Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1855
1856 * interp.c (fetch_str): New function.
1857 (sim_monitor): Rewrite using sim_read & sim_write.
1858 (sim_open): Check magic number.
1859 (sim_open): Write monitor vectors into memory using sim_write.
1860 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1861 (sim_read, sim_write): Simplify - transfer data one byte at a
1862 time.
1863 (load_memory, store_memory): Clarify meaning of parameter RAW.
1864
1865 * sim-main.h (isHOST): Defete definition.
1866 (isTARGET): Mark as depreciated.
1867 (address_translation): Delete parameter HOST.
1868
1869 * interp.c (address_translation): Delete parameter HOST.
1870
1871Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1872
1873 * mips.igen:
1874
1875 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1876 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1877
1878Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1879
1880 * mips.igen: Add model filter field to records.
1881
1882Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1883
1884 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1885
1886 interp.c (sim_engine_run): Do not compile function sim_engine_run
1887 when WITH_IGEN == 1.
1888
1889 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1890 target architecture.
1891
1892 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1893 igen. Replace with configuration variables sim_igen_flags /
1894 sim_m16_flags.
1895
1896 * m16.igen: New file. Copy mips16 insns here.
1897 * mips.igen: From here.
1898
1899Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1900
1901 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1902 to top.
1903 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1904
1905Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1906
1907 * gencode.c (build_instruction): Follow sim_write's lead in using
1908 BigEndianMem instead of !ByteSwapMem.
1909
1910Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1911
1912 * configure.in (sim_gen): Dependent on target, select type of
1913 generator. Always select old style generator.
1914
1915 configure: Re-generate.
1916
1917 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1918 targets.
1919 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1920 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1921 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1922 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1923 SIM_@sim_gen@_*, set by autoconf.
1924
1925Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1926
1927 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1928
1929 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1930 CURRENT_FLOATING_POINT instead.
1931
1932 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1933 (address_translation): Raise exception InstructionFetch when
1934 translation fails and isINSTRUCTION.
1935
1936 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1937 sim_engine_run): Change type of of vaddr and paddr to
1938 address_word.
1939 (address_translation, prefetch, load_memory, store_memory,
1940 cache_op): Change type of vAddr and pAddr to address_word.
1941
1942 * gencode.c (build_instruction): Change type of vaddr and paddr to
1943 address_word.
1944
1945Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1946
1947 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1948 macro to obtain result of ALU op.
1949
1950Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1951
1952 * interp.c (sim_info): Call profile_print.
1953
1954Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1955
1956 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1957
1958 * sim-main.h (WITH_PROFILE): Do not define, defined in
1959 common/sim-config.h. Use sim-profile module.
1960 (simPROFILE): Delete defintion.
1961
1962 * interp.c (PROFILE): Delete definition.
1963 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1964 (sim_close): Delete code writing profile histogram.
1965 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1966 Delete.
1967 (sim_engine_run): Delete code profiling the PC.
1968
1969Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1970
1971 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1972
1973 * interp.c (sim_monitor): Make register pointers of type
1974 unsigned_word*.
1975
1976 * sim-main.h: Make registers of type unsigned_word not
1977 signed_word.
1978
1979Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1980
1981 * interp.c (sync_operation): Rename from SyncOperation, make
1982 global, add SD argument.
1983 (prefetch): Rename from Prefetch, make global, add SD argument.
1984 (decode_coproc): Make global.
1985
1986 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1987
1988 * gencode.c (build_instruction): Generate DecodeCoproc not
1989 decode_coproc calls.
1990
1991 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1992 (SizeFGR): Move to sim-main.h
1993 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1994 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1995 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1996 sim-main.h.
1997 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1998 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1999 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2000 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2001 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2002 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2003
2004 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2005 exception.
2006 (sim-alu.h): Include.
2007 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2008 (sim_cia): Typedef to instruction_address.
2009
2010Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2011
2012 * Makefile.in (interp.o): Rename generated file engine.c to
2013 oengine.c.
2014
2015 * interp.c: Update.
2016
2017Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2018
2019 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2020
2021Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2022
2023 * gencode.c (build_instruction): For "FPSQRT", output correct
2024 number of arguments to Recip.
2025
2026Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2027
2028 * Makefile.in (interp.o): Depends on sim-main.h
2029
2030 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2031
2032 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2033 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2034 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2035 STATE, DSSTATE): Define
2036 (GPR, FGRIDX, ..): Define.
2037
2038 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2039 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2040 (GPR, FGRIDX, ...): Delete macros.
2041
2042 * interp.c: Update names to match defines from sim-main.h
2043
2044Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2045
2046 * interp.c (sim_monitor): Add SD argument.
2047 (sim_warning): Delete. Replace calls with calls to
2048 sim_io_eprintf.
2049 (sim_error): Delete. Replace calls with sim_io_error.
2050 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2051 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2052 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2053 argument.
2054 (mips_size): Rename from sim_size. Add SD argument.
2055
2056 * interp.c (simulator): Delete global variable.
2057 (callback): Delete global variable.
2058 (mips_option_handler, sim_open, sim_write, sim_read,
2059 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2060 sim_size,sim_monitor): Use sim_io_* not callback->*.
2061 (sim_open): ZALLOC simulator struct.
2062 (PROFILE): Do not define.
2063
2064Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2065
2066 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2067 support.h with corresponding code.
2068
2069 * sim-main.h (word64, uword64), support.h: Move definition to
2070 sim-main.h.
2071 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2072
2073 * support.h: Delete
2074 * Makefile.in: Update dependencies
2075 * interp.c: Do not include.
2076
2077Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2078
2079 * interp.c (address_translation, load_memory, store_memory,
2080 cache_op): Rename to from AddressTranslation et.al., make global,
2081 add SD argument
2082
2083 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2084 CacheOp): Define.
2085
2086 * interp.c (SignalException): Rename to signal_exception, make
2087 global.
2088
2089 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2090
2091 * sim-main.h (SignalException, SignalExceptionInterrupt,
2092 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2093 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2094 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2095 Define.
2096
2097 * interp.c, support.h: Use.
2098
2099Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2100
2101 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2102 to value_fpr / store_fpr. Add SD argument.
2103 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2104 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2105
2106 * sim-main.h (ValueFPR, StoreFPR): Define.
2107
2108Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2109
2110 * interp.c (sim_engine_run): Check consistency between configure
2111 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2112 and HASFPU.
2113
2114 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2115 (mips_fpu): Configure WITH_FLOATING_POINT.
2116 (mips_endian): Configure WITH_TARGET_ENDIAN.
2117 * configure: Update.
2118
2119Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2120
2121 * configure: Regenerated to track ../common/aclocal.m4 changes.
2122
2123Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2124
2125 * configure: Regenerated.
2126
2127Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2128
2129 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2130
2131Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2132
2133 * gencode.c (print_igen_insn_models): Assume certain architectures
2134 include all mips* instructions.
2135 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2136 instruction.
2137
2138 * Makefile.in (tmp.igen): Add target. Generate igen input from
2139 gencode file.
2140
2141 * gencode.c (FEATURE_IGEN): Define.
2142 (main): Add --igen option. Generate output in igen format.
2143 (process_instructions): Format output according to igen option.
2144 (print_igen_insn_format): New function.
2145 (print_igen_insn_models): New function.
2146 (process_instructions): Only issue warnings and ignore
2147 instructions when no FEATURE_IGEN.
2148
2149Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2150
2151 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2152 MIPS targets.
2153
2154Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2155
2156 * configure: Regenerated to track ../common/aclocal.m4 changes.
2157
2158Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2159
2160 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2161 SIM_RESERVED_BITS): Delete, moved to common.
2162 (SIM_EXTRA_CFLAGS): Update.
2163
2164Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2165
2166 * configure.in: Configure non-strict memory alignment.
2167 * configure: Regenerated to track ../common/aclocal.m4 changes.
2168
2169Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2170
2171 * configure: Regenerated to track ../common/aclocal.m4 changes.
2172
2173Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2174
2175 * gencode.c (SDBBP,DERET): Added (3900) insns.
2176 (RFE): Turn on for 3900.
2177 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2178 (dsstate): Made global.
2179 (SUBTARGET_R3900): Added.
2180 (CANCELDELAYSLOT): New.
2181 (SignalException): Ignore SystemCall rather than ignore and
2182 terminate. Add DebugBreakPoint handling.
2183 (decode_coproc): New insns RFE, DERET; and new registers Debug
2184 and DEPC protected by SUBTARGET_R3900.
2185 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2186 bits explicitly.
2187 * Makefile.in,configure.in: Add mips subtarget option.
2188 * configure: Update.
2189
2190Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2191
2192 * gencode.c: Add r3900 (tx39).
2193
2194
2195Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2196
2197 * gencode.c (build_instruction): Don't need to subtract 4 for
2198 JALR, just 2.
2199
2200Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2201
2202 * interp.c: Correct some HASFPU problems.
2203
2204Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2205
2206 * configure: Regenerated to track ../common/aclocal.m4 changes.
2207
2208Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2209
2210 * interp.c (mips_options): Fix samples option short form, should
2211 be `x'.
2212
2213Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2214
2215 * interp.c (sim_info): Enable info code. Was just returning.
2216
2217Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2218
2219 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2220 MFC0.
2221
2222Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2223
2224 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2225 constants.
2226 (build_instruction): Ditto for LL.
2227
2228Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2229
2230 * configure: Regenerated to track ../common/aclocal.m4 changes.
2231
2232Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2233
2234 * configure: Regenerated to track ../common/aclocal.m4 changes.
2235 * config.in: Ditto.
2236
2237Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2238
2239 * interp.c (sim_open): Add call to sim_analyze_program, update
2240 call to sim_config.
2241
2242Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2243
2244 * interp.c (sim_kill): Delete.
2245 (sim_create_inferior): Add ABFD argument. Set PC from same.
2246 (sim_load): Move code initializing trap handlers from here.
2247 (sim_open): To here.
2248 (sim_load): Delete, use sim-hload.c.
2249
2250 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2251
2252Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2253
2254 * configure: Regenerated to track ../common/aclocal.m4 changes.
2255 * config.in: Ditto.
2256
2257Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2258
2259 * interp.c (sim_open): Add ABFD argument.
2260 (sim_load): Move call to sim_config from here.
2261 (sim_open): To here. Check return status.
2262
2263Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2264
2265 * gencode.c (build_instruction): Two arg MADD should
2266 not assign result to $0.
2267
2268Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2269
2270 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2271 * sim/mips/configure.in: Regenerate.
2272
2273Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2274
2275 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2276 signed8, unsigned8 et.al. types.
2277
2278 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2279 hosts when selecting subreg.
2280
2281Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2282
2283 * interp.c (sim_engine_run): Reset the ZERO register to zero
2284 regardless of FEATURE_WARN_ZERO.
2285 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2286
2287Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2288
2289 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2290 (SignalException): For BreakPoints ignore any mode bits and just
2291 save the PC.
2292 (SignalException): Always set the CAUSE register.
2293
2294Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2295
2296 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2297 exception has been taken.
2298
2299 * interp.c: Implement the ERET and mt/f sr instructions.
2300
2301Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2302
2303 * interp.c (SignalException): Don't bother restarting an
2304 interrupt.
2305
2306Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2307
2308 * interp.c (SignalException): Really take an interrupt.
2309 (interrupt_event): Only deliver interrupts when enabled.
2310
2311Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2312
2313 * interp.c (sim_info): Only print info when verbose.
2314 (sim_info) Use sim_io_printf for output.
2315
2316Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2317
2318 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2319 mips architectures.
2320
2321Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2322
2323 * interp.c (sim_do_command): Check for common commands if a
2324 simulator specific command fails.
2325
2326Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2327
2328 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2329 and simBE when DEBUG is defined.
2330
2331Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2332
2333 * interp.c (interrupt_event): New function. Pass exception event
2334 onto exception handler.
2335
2336 * configure.in: Check for stdlib.h.
2337 * configure: Regenerate.
2338
2339 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2340 variable declaration.
2341 (build_instruction): Initialize memval1.
2342 (build_instruction): Add UNUSED attribute to byte, bigend,
2343 reverse.
2344 (build_operands): Ditto.
2345
2346 * interp.c: Fix GCC warnings.
2347 (sim_get_quit_code): Delete.
2348
2349 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2350 * Makefile.in: Ditto.
2351 * configure: Re-generate.
2352
2353 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2354
2355Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2356
2357 * interp.c (mips_option_handler): New function parse argumes using
2358 sim-options.
2359 (myname): Replace with STATE_MY_NAME.
2360 (sim_open): Delete check for host endianness - performed by
2361 sim_config.
2362 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2363 (sim_open): Move much of the initialization from here.
2364 (sim_load): To here. After the image has been loaded and
2365 endianness set.
2366 (sim_open): Move ColdReset from here.
2367 (sim_create_inferior): To here.
2368 (sim_open): Make FP check less dependant on host endianness.
2369
2370 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2371 run.
2372 * interp.c (sim_set_callbacks): Delete.
2373
2374 * interp.c (membank, membank_base, membank_size): Replace with
2375 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2376 (sim_open): Remove call to callback->init. gdb/run do this.
2377
2378 * interp.c: Update
2379
2380 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2381
2382 * interp.c (big_endian_p): Delete, replaced by
2383 current_target_byte_order.
2384
2385Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2386
2387 * interp.c (host_read_long, host_read_word, host_swap_word,
2388 host_swap_long): Delete. Using common sim-endian.
2389 (sim_fetch_register, sim_store_register): Use H2T.
2390 (pipeline_ticks): Delete. Handled by sim-events.
2391 (sim_info): Update.
2392 (sim_engine_run): Update.
2393
2394Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2395
2396 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2397 reason from here.
2398 (SignalException): To here. Signal using sim_engine_halt.
2399 (sim_stop_reason): Delete, moved to common.
2400
2401Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2402
2403 * interp.c (sim_open): Add callback argument.
2404 (sim_set_callbacks): Delete SIM_DESC argument.
2405 (sim_size): Ditto.
2406
2407Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2408
2409 * Makefile.in (SIM_OBJS): Add common modules.
2410
2411 * interp.c (sim_set_callbacks): Also set SD callback.
2412 (set_endianness, xfer_*, swap_*): Delete.
2413 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2414 Change to functions using sim-endian macros.
2415 (control_c, sim_stop): Delete, use common version.
2416 (simulate): Convert into.
2417 (sim_engine_run): This function.
2418 (sim_resume): Delete.
2419
2420 * interp.c (simulation): New variable - the simulator object.
2421 (sim_kind): Delete global - merged into simulation.
2422 (sim_load): Cleanup. Move PC assignment from here.
2423 (sim_create_inferior): To here.
2424
2425 * sim-main.h: New file.
2426 * interp.c (sim-main.h): Include.
2427
2428Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2429
2430 * configure: Regenerated to track ../common/aclocal.m4 changes.
2431
2432Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2433
2434 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2435
2436Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2437
2438 * gencode.c (build_instruction): DIV instructions: check
2439 for division by zero and integer overflow before using
2440 host's division operation.
2441
2442Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2443
2444 * Makefile.in (SIM_OBJS): Add sim-load.o.
2445 * interp.c: #include bfd.h.
2446 (target_byte_order): Delete.
2447 (sim_kind, myname, big_endian_p): New static locals.
2448 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2449 after argument parsing. Recognize -E arg, set endianness accordingly.
2450 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2451 load file into simulator. Set PC from bfd.
2452 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2453 (set_endianness): Use big_endian_p instead of target_byte_order.
2454
2455Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2456
2457 * interp.c (sim_size): Delete prototype - conflicts with
2458 definition in remote-sim.h. Correct definition.
2459
2460Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2461
2462 * configure: Regenerated to track ../common/aclocal.m4 changes.
2463 * config.in: Ditto.
2464
2465Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2466
2467 * interp.c (sim_open): New arg `kind'.
2468
2469 * configure: Regenerated to track ../common/aclocal.m4 changes.
2470
2471Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2472
2473 * configure: Regenerated to track ../common/aclocal.m4 changes.
2474
2475Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2476
2477 * interp.c (sim_open): Set optind to 0 before calling getopt.
2478
2479Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2480
2481 * configure: Regenerated to track ../common/aclocal.m4 changes.
2482
2483Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2484
2485 * interp.c : Replace uses of pr_addr with pr_uword64
2486 where the bit length is always 64 independent of SIM_ADDR.
2487 (pr_uword64) : added.
2488
2489Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2490
2491 * configure: Re-generate.
2492
2493Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2494
2495 * configure: Regenerate to track ../common/aclocal.m4 changes.
2496
2497Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2498
2499 * interp.c (sim_open): New SIM_DESC result. Argument is now
2500 in argv form.
2501 (other sim_*): New SIM_DESC argument.
2502
2503Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2504
2505 * interp.c: Fix printing of addresses for non-64-bit targets.
2506 (pr_addr): Add function to print address based on size.
2507
2508Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2509
2510 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2511
2512Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2513
2514 * gencode.c (build_mips16_operands): Correct computation of base
2515 address for extended PC relative instruction.
2516
2517Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2518
2519 * interp.c (mips16_entry): Add support for floating point cases.
2520 (SignalException): Pass floating point cases to mips16_entry.
2521 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2522 registers.
2523 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2524 or fmt_word.
2525 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2526 and then set the state to fmt_uninterpreted.
2527 (COP_SW): Temporarily set the state to fmt_word while calling
2528 ValueFPR.
2529
2530Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2531
2532 * gencode.c (build_instruction): The high order may be set in the
2533 comparison flags at any ISA level, not just ISA 4.
2534
2535Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2536
2537 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2538 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2539 * configure.in: sinclude ../common/aclocal.m4.
2540 * configure: Regenerated.
2541
2542Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2543
2544 * configure: Rebuild after change to aclocal.m4.
2545
2546Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2547
2548 * configure configure.in Makefile.in: Update to new configure
2549 scheme which is more compatible with WinGDB builds.
2550 * configure.in: Improve comment on how to run autoconf.
2551 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2552 * Makefile.in: Use autoconf substitution to install common
2553 makefile fragment.
2554
2555Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2556
2557 * gencode.c (build_instruction): Use BigEndianCPU instead of
2558 ByteSwapMem.
2559
2560Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2561
2562 * interp.c (sim_monitor): Make output to stdout visible in
2563 wingdb's I/O log window.
2564
2565Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2566
2567 * support.h: Undo previous change to SIGTRAP
2568 and SIGQUIT values.
2569
2570Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2571
2572 * interp.c (store_word, load_word): New static functions.
2573 (mips16_entry): New static function.
2574 (SignalException): Look for mips16 entry and exit instructions.
2575 (simulate): Use the correct index when setting fpr_state after
2576 doing a pending move.
2577
2578Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2579
2580 * interp.c: Fix byte-swapping code throughout to work on
2581 both little- and big-endian hosts.
2582
2583Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2584
2585 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2586 with gdb/config/i386/xm-windows.h.
2587
2588Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2589
2590 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2591 that messes up arithmetic shifts.
2592
2593Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2594
2595 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2596 SIGTRAP and SIGQUIT for _WIN32.
2597
2598Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2599
2600 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2601 force a 64 bit multiplication.
2602 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2603 destination register is 0, since that is the default mips16 nop
2604 instruction.
2605
2606Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2607
2608 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2609 (build_endian_shift): Don't check proc64.
2610 (build_instruction): Always set memval to uword64. Cast op2 to
2611 uword64 when shifting it left in memory instructions. Always use
2612 the same code for stores--don't special case proc64.
2613
2614 * gencode.c (build_mips16_operands): Fix base PC value for PC
2615 relative operands.
2616 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2617 jal instruction.
2618 * interp.c (simJALDELAYSLOT): Define.
2619 (JALDELAYSLOT): Define.
2620 (INDELAYSLOT, INJALDELAYSLOT): Define.
2621 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2622
2623Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2624
2625 * interp.c (sim_open): add flush_cache as a PMON routine
2626 (sim_monitor): handle flush_cache by ignoring it
2627
2628Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2629
2630 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2631 BigEndianMem.
2632 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2633 (BigEndianMem): Rename to ByteSwapMem and change sense.
2634 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2635 BigEndianMem references to !ByteSwapMem.
2636 (set_endianness): New function, with prototype.
2637 (sim_open): Call set_endianness.
2638 (sim_info): Use simBE instead of BigEndianMem.
2639 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2640 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2641 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2642 ifdefs, keeping the prototype declaration.
2643 (swap_word): Rewrite correctly.
2644 (ColdReset): Delete references to CONFIG. Delete endianness related
2645 code; moved to set_endianness.
2646
2647Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2648
2649 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2650 * interp.c (CHECKHILO): Define away.
2651 (simSIGINT): New macro.
2652 (membank_size): Increase from 1MB to 2MB.
2653 (control_c): New function.
2654 (sim_resume): Rename parameter signal to signal_number. Add local
2655 variable prev. Call signal before and after simulate.
2656 (sim_stop_reason): Add simSIGINT support.
2657 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2658 functions always.
2659 (sim_warning): Delete call to SignalException. Do call printf_filtered
2660 if logfh is NULL.
2661 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2662 a call to sim_warning.
2663
2664Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2665
2666 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2667 16 bit instructions.
2668
2669Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2670
2671 Add support for mips16 (16 bit MIPS implementation):
2672 * gencode.c (inst_type): Add mips16 instruction encoding types.
2673 (GETDATASIZEINSN): Define.
2674 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2675 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2676 mtlo.
2677 (MIPS16_DECODE): New table, for mips16 instructions.
2678 (bitmap_val): New static function.
2679 (struct mips16_op): Define.
2680 (mips16_op_table): New table, for mips16 operands.
2681 (build_mips16_operands): New static function.
2682 (process_instructions): If PC is odd, decode a mips16
2683 instruction. Break out instruction handling into new
2684 build_instruction function.
2685 (build_instruction): New static function, broken out of
2686 process_instructions. Check modifiers rather than flags for SHIFT
2687 bit count and m[ft]{hi,lo} direction.
2688 (usage): Pass program name to fprintf.
2689 (main): Remove unused variable this_option_optind. Change
2690 ``*loptarg++'' to ``loptarg++''.
2691 (my_strtoul): Parenthesize && within ||.
2692 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2693 (simulate): If PC is odd, fetch a 16 bit instruction, and
2694 increment PC by 2 rather than 4.
2695 * configure.in: Add case for mips16*-*-*.
2696 * configure: Rebuild.
2697
2698Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2699
2700 * interp.c: Allow -t to enable tracing in standalone simulator.
2701 Fix garbage output in trace file and error messages.
2702
2703Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2704
2705 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2706 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2707 * configure.in: Simplify using macros in ../common/aclocal.m4.
2708 * configure: Regenerated.
2709 * tconfig.in: New file.
2710
2711Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2712
2713 * interp.c: Fix bugs in 64-bit port.
2714 Use ansi function declarations for msvc compiler.
2715 Initialize and test file pointer in trace code.
2716 Prevent duplicate definition of LAST_EMED_REGNUM.
2717
2718Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2719
2720 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2721
2722Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2723
2724 * interp.c (SignalException): Check for explicit terminating
2725 breakpoint value.
2726 * gencode.c: Pass instruction value through SignalException()
2727 calls for Trap, Breakpoint and Syscall.
2728
2729Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2730
2731 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2732 only used on those hosts that provide it.
2733 * configure.in: Add sqrt() to list of functions to be checked for.
2734 * config.in: Re-generated.
2735 * configure: Re-generated.
2736
2737Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2738
2739 * gencode.c (process_instructions): Call build_endian_shift when
2740 expanding STORE RIGHT, to fix swr.
2741 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2742 clear the high bits.
2743 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2744 Fix float to int conversions to produce signed values.
2745
2746Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2747
2748 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2749 (process_instructions): Correct handling of nor instruction.
2750 Correct shift count for 32 bit shift instructions. Correct sign
2751 extension for arithmetic shifts to not shift the number of bits in
2752 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2753 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2754 Fix madd.
2755 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2756 It's OK to have a mult follow a mult. What's not OK is to have a
2757 mult follow an mfhi.
2758 (Convert): Comment out incorrect rounding code.
2759
2760Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2761
2762 * interp.c (sim_monitor): Improved monitor printf
2763 simulation. Tidied up simulator warnings, and added "--log" option
2764 for directing warning message output.
2765 * gencode.c: Use sim_warning() rather than WARNING macro.
2766
2767Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2768
2769 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2770 getopt1.o, rather than on gencode.c. Link objects together.
2771 Don't link against -liberty.
2772 (gencode.o, getopt.o, getopt1.o): New targets.
2773 * gencode.c: Include <ctype.h> and "ansidecl.h".
2774 (AND): Undefine after including "ansidecl.h".
2775 (ULONG_MAX): Define if not defined.
2776 (OP_*): Don't define macros; now defined in opcode/mips.h.
2777 (main): Call my_strtoul rather than strtoul.
2778 (my_strtoul): New static function.
2779
2780Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2781
2782 * gencode.c (process_instructions): Generate word64 and uword64
2783 instead of `long long' and `unsigned long long' data types.
2784 * interp.c: #include sysdep.h to get signals, and define default
2785 for SIGBUS.
2786 * (Convert): Work around for Visual-C++ compiler bug with type
2787 conversion.
2788 * support.h: Make things compile under Visual-C++ by using
2789 __int64 instead of `long long'. Change many refs to long long
2790 into word64/uword64 typedefs.
2791
2792Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2793
2794 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2795 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2796 (docdir): Removed.
2797 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2798 (AC_PROG_INSTALL): Added.
2799 (AC_PROG_CC): Moved to before configure.host call.
2800 * configure: Rebuilt.
2801
2802Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2803
2804 * configure.in: Define @SIMCONF@ depending on mips target.
2805 * configure: Rebuild.
2806 * Makefile.in (run): Add @SIMCONF@ to control simulator
2807 construction.
2808 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2809 * interp.c: Remove some debugging, provide more detailed error
2810 messages, update memory accesses to use LOADDRMASK.
2811
2812Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2813
2814 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2815 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2816 stamp-h.
2817 * configure: Rebuild.
2818 * config.in: New file, generated by autoheader.
2819 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2820 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2821 HAVE_ANINT and HAVE_AINT, as appropriate.
2822 * Makefile.in (run): Use @LIBS@ rather than -lm.
2823 (interp.o): Depend upon config.h.
2824 (Makefile): Just rebuild Makefile.
2825 (clean): Remove stamp-h.
2826 (mostlyclean): Make the same as clean, not as distclean.
2827 (config.h, stamp-h): New targets.
2828
2829Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2830
2831 * interp.c (ColdReset): Fix boolean test. Make all simulator
2832 globals static.
2833
2834Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2835
2836 * interp.c (xfer_direct_word, xfer_direct_long,
2837 swap_direct_word, swap_direct_long, xfer_big_word,
2838 xfer_big_long, xfer_little_word, xfer_little_long,
2839 swap_word,swap_long): Added.
2840 * interp.c (ColdReset): Provide function indirection to
2841 host<->simulated_target transfer routines.
2842 * interp.c (sim_store_register, sim_fetch_register): Updated to
2843 make use of indirected transfer routines.
2844
2845Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2846
2847 * gencode.c (process_instructions): Ensure FP ABS instruction
2848 recognised.
2849 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2850 system call support.
2851
2852Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2853
2854 * interp.c (sim_do_command): Complain if callback structure not
2855 initialised.
2856
2857Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2858
2859 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2860 support for Sun hosts.
2861 * Makefile.in (gencode): Ensure the host compiler and libraries
2862 used for cross-hosted build.
2863
2864Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2865
2866 * interp.c, gencode.c: Some more (TODO) tidying.
2867
2868Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2869
2870 * gencode.c, interp.c: Replaced explicit long long references with
2871 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2872 * support.h (SET64LO, SET64HI): Macros added.
2873
2874Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2875
2876 * configure: Regenerate with autoconf 2.7.
2877
2878Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2879
2880 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2881 * support.h: Remove superfluous "1" from #if.
2882 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2883
2884Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2885
2886 * interp.c (StoreFPR): Control UndefinedResult() call on
2887 WARN_RESULT manifest.
2888
2889Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2890
2891 * gencode.c: Tidied instruction decoding, and added FP instruction
2892 support.
2893
2894 * interp.c: Added dineroIII, and BSD profiling support. Also
2895 run-time FP handling.
2896
2897Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2898
2899 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2900 gencode.c, interp.c, support.h: created.
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