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gnulib: import select
[deliverable/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
8ea881d9
MF		 12021-05-29 Mike Frysinger <vapier@gentoo.org>
2
3 * interp.c [!HAVE_DV_SOCKSER] (sockser_addr): Define to NULL.
4
b312488f
FS		 52021-05-22 Faraz Shahbazker <fshahbazker@wavecomp.com>
6
168671c1
FS		 7 * interp.c (sim_open): Add shadow mappings from 32-bit
8 address space to 64-bit sign-extended address space.
9
102021-05-22 Faraz Shahbazker <fshahbazker@wavecomp.com>
11
b312488f
FS		 12 * interp.c (sim_create_inferior): Only truncate sign extension
13 bits for 32-bit target models.
14
f4fdd845
MF		 152021-05-17 Mike Frysinger <vapier@gentoo.org>
16
17 * sim-main.h (SIM_HAVE_COMMON_SIM_STATE): Delete.
18
8ea7241c
MF		 192021-05-17 Mike Frysinger <vapier@gentoo.org>
20
21 * interp.c (sim_open): Switch to sim_state_alloc_extra.
22 * micromips.igen: Change SD to mips_sim_state.
23 * micromipsrun.c (sim_engine_run): Likewise.
24 * sim-main.h (SIM_HAVE_COMMON_SIM_STATE): Define.
25 (watch_options_install): Delete.
26 (struct swatch): Delete.
27 (struct sim_state): Delete.
28 (struct mips_sim_state): New struct.
29 (MIPS_SIM_STATE): Define.
30
6df01ab8
MF		 312021-05-16 Mike Frysinger <vapier@gentoo.org>
32
33 * interp.c: Replace config.h include with defs.h.
34 * cp1.c, dsp.c, dv-tx3904cpu.c, dv-tx3904irc.c, dv-tx3904sio.c,
35 dv-tx3904tmr.c, m16run.c, mdmx.c, micromipsrun.c, sim-main.c:
36 Include defs.h.
37
79633c12
MF		 382021-05-16 Mike Frysinger <vapier@gentoo.org>
39
40 * config.in, configure: Regenerate.
41
df68e12b
MF		 422021-05-14 Mike Frysinger <vapier@gentoo.org>
43
44 * interp.c: Update include path.
45
77c0fdb7
MF		 462021-05-04 Mike Frysinger <vapier@gentoo.org>
47
48 * dv-tx3904sio.c: Include stdlib.h.
49
9b1af85c
MF		 502021-05-04 Mike Frysinger <vapier@gentoo.org>
51
52 * configure.ac (hw_extra_devices): Inline contents into
53 SIM_AC_OPTION_HARDWARE and delete.
54 * configure: Regenerate.
55
d97ba9c6
MF		 562021-05-04 Mike Frysinger <vapier@gentoo.org>
57
58 * Makefile.in (SIM_IGEN_OBJ): Change @mips_igen_engine@ to engine.o.
59 (MIPS_EXTRA_LIB, SIM_EXTRA_LIBS): Delete.
60 * configure.ac (mips_igen_engine, mips_extra_libs): Delete.
61 * configure: Regenerate.
62
4df817de
MF		 632021-05-04 Mike Frysinger <vapier@gentoo.org>
64
65 * mdmx.c (qh_acc): Change 2nd AccAddAQH to AccAddLQH.
66
aa0fca16
MF		 672021-05-04 Mike Frysinger <vapier@gentoo.org>
68
69 * configure: Regenerate.
70
adbaa7b8
MF		 712021-05-01 Mike Frysinger <vapier@gentoo.org>
72
73 * cp1.c (store_fcr): Mark static.
74
fe348617
MF		 752021-05-01 Mike Frysinger <vapier@gentoo.org>
76
77 * config.in, configure: Regenerate.
78
9d903352
MF		 792021-04-23 Mike Frysinger <vapier@gentoo.org>
80
81 * configure.ac (hw_enabled): Delete.
82 (SIM_AC_OPTION_HARDWARE): Delete first two args.
83 * configure: Regenerate.
84
19f6a43c
TT		 852021-04-22 Tom Tromey <tom@tromey.com>
86
87 * configure, config.in: Rebuild.
88
e7d8f1da
TT		 892021-04-22 Tom Tromey <tom@tromey.com>
90
91 * Makefile.in (interp.o, m16run.o, micromipsrun.o, multi-run.o):
92 Remove.
93 (SIM_EXTRA_DEPS): New variable.
94
efd82ac7
TT		 952021-04-22 Tom Tromey <tom@tromey.com>
96
97 * configure: Rebuild.
98
2662c237
MF		 992021-04-21 Mike Frysinger <vapier@gentoo.org>
100
101 * aclocal.m4: Regenerate.
102
1f195bc3
SM		 1032021-04-21 Simon Marchi <simon.marchi@polymtl.ca>
104
105 * configure: Regenerate.
106
37e9f182
MF		 1072021-04-18 Mike Frysinger <vapier@gentoo.org>
108
109 * configure: Regenerate.
110
d5a71b11
MF		 1112021-04-12 Mike Frysinger <vapier@gentoo.org>
112
113 * interp.c (sim_open): Delete 3rd arg to sim_cpu_alloc_all.
114
2b8d134b
SM		 1152021-04-08 Simon Marchi <simon.marchi@polymtl.ca>
116
117 * Makefile.in: Set ASAN_OPTIONS when running igen.
118
5c6f091a
FS		 1192021-04-04 Steve Ellcey <sellcey@mips.com>
120 Faraz Shahbazker <fshahbazker@wavecomp.com>
121
122 * interp.c (sim_monitor): Add switch entries for unlink (13),
123 lseek (14), and stat (15).
124
b6b1c790
MF		 1252021-04-02 Mike Frysinger <vapier@gentoo.org>
126
127 * Makefile.in (../igen/igen): Delete rule.
128 (tmp-igen, tmp-m16, tmp-micromips): Delete ../igen make.
129
c2783492
MF		 1302021-04-02 Mike Frysinger <vapier@gentoo.org>
131
132 * aclocal.m4, configure: Regenerate.
133
ebe9564b
MF		 1342021-02-28 Mike Frysinger <vapier@gentoo.org>
135
136 * configure: Regenerate.
137
f8069d55
MF		 1382021-02-27 Mike Frysinger <vapier@gentoo.org>
139
140 * Makefile.in (SIM_EXTRA_ALL): Delete.
141 (all): New target.
142
760b3e8b
MF		 1432021-02-21 Mike Frysinger <vapier@gentoo.org>
144
145 * configure.ac (AC_CONFIG_MACRO_DIRS): Replace common with m4.
146 * aclocal.m4, configure: Regenerate.
147
136da8cd
MF		 1482021-02-13 Mike Frysinger <vapier@gentoo.org>
149
150 * configure.ac: Replace sinclude with AC_CONFIG_MACRO_DIRS.
151 * aclocal.m4, configure: Regenerate.
152
4c0d76b9
MF		 1532021-02-06 Mike Frysinger <vapier@gentoo.org>
154
155 * interp.c (sim_open): Delete call to STATE_WATCHPOINTS.
156
aa09469f
MF		 1572021-02-06 Mike Frysinger <vapier@gentoo.org>
158
159 * configure: Regenerate.
160
d4e3adda
MF		 1612021-01-30 Mike Frysinger <vapier@gentoo.org>
162
163 * interp.c (sim_open): Delete STATE_WATCHPOINTS (sd)->sizeof_pc.
164
68ed2854
MF		 1652021-01-11 Mike Frysinger <vapier@gentoo.org>
166
167 * config.in, configure: Regenerate.
168 * interp.c: Delete HAVE_STRING_H, HAVE_STRINGS_H, HAVE_STDLIB_H,
169 and strings.h include.
170
50df264d
MF		 1712021-01-09 Mike Frysinger <vapier@gentoo.org>
172
173 * configure: Regenerate.
174
bf470982
MF		 1752021-01-09 Mike Frysinger <vapier@gentoo.org>
176
177 * configure.ac (SIM_AC_OPTION_WARNINGS): Pass "no".
178 * configure: Regenerate.
179
46f900c0
MF		 1802021-01-08 Mike Frysinger <vapier@gentoo.org>
181
182 * configure: Regenerate.
183
dfb856ba
MF		 1842021-01-04 Mike Frysinger <vapier@gentoo.org>
185
186 * configure: Regenerate.
187
382bc56b
PK		 1882020-12-31 Pavel I. Kryukov <kryukov@frtk.ru> (tiny change)
189
190 * sim-main.c: Include <stdlib.h>.
191
ad9675dd
PK		 1922020-12-14 Pavel I. Kryukov <kryukov@frtk.ru> (tiny change)
193
194 * cp1.c: Include <stdlib.h>.
195
f693213d
SM		 1962020-07-29 Simon Marchi <simon.marchi@efficios.com>
197
198 * configure: Re-generate.
199
5c887dd5
JB		 2002017-09-06 John Baldwin <jhb@FreeBSD.org>
201
202 * configure: Regenerate.
203
91588b3a
MF		 2042016-11-11 Mike Frysinger <vapier@gentoo.org>
205
6cb2202b 206 PR sim/20808
91588b3a
MF		 207 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Define CPU to cpu
208 and SD to sd.
209
e04659e8
MF		 2102016-11-11 Mike Frysinger <vapier@gentoo.org>
211
6cb2202b 212 PR sim/20809
e04659e8
MF		 213 * mips.igen (check_u64): Enable for `r3900'.
214
1554f758
MF		 2152016-02-05 Mike Frysinger <vapier@gentoo.org>
216
217 * configure.ac (sim_engine_run): Change sd->base.prog_bfd to
218 STATE_PROG_BFD (sd).
219 * configure: Regenerate.
220
3d304f48
AB		 2212016-01-18 Andrew Bennett <andrew.bennett@imgtec.com>
222 Maciej W. Rozycki <macro@imgtec.com>
223
224 PR sim/19441
225 * micromips.igen (delayslot_micromips): Enable for `micromips32',
226 `micromips64' and `micromipsdsp' only.
227 (process_isa_mode): Enable for `micromips32' and `micromips64' only.
228 (do_micromips_jalr, do_micromips_jal): Likewise.
229 (compute_movep_src_reg): Likewise.
230 (compute_andi16_imm): Likewise.
231 (convert_fmt_micromips): Likewise.
232 (convert_fmt_micromips_cvt_d): Likewise.
233 (convert_fmt_micromips_cvt_s): Likewise.
234 (FMT_MICROMIPS): Likewise.
235 (FMT_MICROMIPS_CVT_D): Likewise.
236 (FMT_MICROMIPS_CVT_S): Likewise.
237
b36d953b
MF		 2382016-01-12 Mike Frysinger <vapier@gentoo.org>
239
240 * interp.c: Include elf-bfd.h.
241 (sim_create_inferior): Truncate pc to 32-bits when EI_CLASS is
242 ELFCLASS32.
243
ce39bd38
MF		 2442016-01-10 Mike Frysinger <vapier@gentoo.org>
245
246 * config.in, configure: Regenerate.
247
99d8e879
MF		 2482016-01-10 Mike Frysinger <vapier@gentoo.org>
249
250 * configure: Regenerate.
251
35656e95
MF		 2522016-01-10 Mike Frysinger <vapier@gentoo.org>
253
254 * configure: Regenerate.
255
16f7876d
MF		 2562016-01-10 Mike Frysinger <vapier@gentoo.org>
257
258 * configure: Regenerate.
259
e19418e0
MF		 2602016-01-10 Mike Frysinger <vapier@gentoo.org>
261
262 * configure: Regenerate.
263
6d90347b
MF		 2642016-01-10 Mike Frysinger <vapier@gentoo.org>
265
266 * configure.ac (SIM_AC_OPTION_SMP): Delete call.
267 * configure: Regenerate.
268
347fe5bb
MF		 2692016-01-10 Mike Frysinger <vapier@gentoo.org>
270
271 * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
272 * configure: Regenerate.
273
22be3fbe
MF		 2742016-01-10 Mike Frysinger <vapier@gentoo.org>
275
276 * configure: Regenerate.
277
0dc73ef7
MF		 2782016-01-10 Mike Frysinger <vapier@gentoo.org>
279
280 * configure: Regenerate.
281
936df756
MF		 2822016-01-09 Mike Frysinger <vapier@gentoo.org>
283
284 * config.in, configure: Regenerate.
285
2e3d4f4d
MF		 2862016-01-06 Mike Frysinger <vapier@gentoo.org>
287
288 * interp.c (sim_open): Mark argv const.
289 (sim_create_inferior): Mark argv and env const.
290
9bbf6f91
MF		 2912016-01-04 Mike Frysinger <vapier@gentoo.org>
292
293 * configure: Regenerate.
294
77cf2ef5
MF		 2952016-01-03 Mike Frysinger <vapier@gentoo.org>
296
297 * interp.c (sim_open): Update sim_parse_args comment.
298
0cb8d851
MF		 2992016-01-03 Mike Frysinger <vapier@gentoo.org>
300
301 * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
302 * configure: Regenerate.
303
1ac72f06
MF		 3042016-01-02 Mike Frysinger <vapier@gentoo.org>
305
306 * configure.ac (mips_endian): Change LITTLE_ENDIAN to LITTLE.
307 (default_endian): Likewise. Change BIG_ENDIAN to BIG.
308 * configure: Regenerate.
309 * sim-main.h (BigEndianMem): Change BIG_ENDIAN to BFD_ENDIAN_BIG.
310
d47f5b30
MF		 3112016-01-02 Mike Frysinger <vapier@gentoo.org>
312
313 * dv-tx3904cpu.c (CPU, SD): Delete.
314
e1211e55
MF		 3152015-12-30 Mike Frysinger <vapier@gentoo.org>
316
317 * wrapper.c (mips_reg_store, mips_reg_fetch): Define.
318 (sim_open): Call CPU_REG_FETCH/CPU_REG_STORE.
319 (sim_store_register): Rename to ...
320 (mips_reg_store): ... this. Delete local cpu var.
321 Update sim_io_eprintf calls.
322 (sim_fetch_register): Rename to ...
323 (mips_reg_fetch): ... this. Delete local cpu var.
324 Update sim_io_eprintf calls.
325
5e744ef8
MF		 3262015-12-27 Mike Frysinger <vapier@gentoo.org>
327
328 * Makefile.in (SIM_OBJS): Delete sim-hload.o.
329
1b393626
MF		 3302015-12-26 Mike Frysinger <vapier@gentoo.org>
331
332 * config.in, configure: Regenerate.
333
26f8bf63
MF		 3342015-12-26 Mike Frysinger <vapier@gentoo.org>
335
336 * interp.c (sim_write, sim_read): Delete.
337 (store_word): Delete call to AddressTranslation and set paddr=vaddr.
338 (load_word): Likewise.
339 * micromips.igen (cache): Likewise.
340 * mips.igen (do_ll, do_lld, do_sc, do_scd, do_suxc1_32, do_swc1,
341 do_swxc1, cache, do_load, do_load_left, do_load_right, do_store,
342 do_store_left, do_store_right, do_load_double, do_store_double):
343 Likewise.
344 (do_pref): Delete call to AddressTranslation and stub out Prefetch.
345 (do_prefx): Likewise.
346 * sim-main.c (address_translation, prefetch): Delete.
347 (ifetch32, ifetch16): Delete call to AddressTranslation and set
348 paddr=vaddr.
349 * sim-main.h (Uncached, CachedNoncoherent, CachedCoherent, Cached,
350 address_translation, AddressTranslation, prefetch, Prefetch): Delete.
351 (LoadMemory, StoreMemory): Delete CCA arg.
352
ef04e371
MF		 3532015-12-24 Mike Frysinger <vapier@gentoo.org>
354
355 * configure.ac (SIM_SUBTARGET): Drop -DTARGET_TX3904=1.
356 * configure: Regenerated.
357
cb379ede
MF		 3582015-12-24 Mike Frysinger <vapier@gentoo.org>
359
360 * sim-main.h (SIM_QUIET_NAN_NEGATED): Move from tconfig.h.
361 * tconfig.h: Delete.
362
26936211
MF		 3632015-12-24 Mike Frysinger <vapier@gentoo.org>
364
365 * tconfig.h (SIM_HANDLES_LMA): Delete.
366
84e8e361
MF		 3672015-12-24 Mike Frysinger <vapier@gentoo.org>
368
369 * sim-main.h (WITH_WATCHPOINTS): Delete.
370
3cabaf66
MF		 3712015-12-24 Mike Frysinger <vapier@gentoo.org>
372
373 * interp.c [SIM_HAVE_FLATMEM] (sim_open): Delete flatmem code.
374
8abe6c66
MF		 3752015-12-24 Mike Frysinger <vapier@gentoo.org>
376
377 * tconfig.h (SIM_HAVE_SIMCACHE): Delete.
378
1d19cae7
DV		 3792015-12-15 Dominik Vogt <vogt@linux.vnet.ibm.com>
380
381 * micromips.igen (process_isa_mode): Fix left shift of negative
382 value.
383
cdf850e9
MF		 3842015-11-17 Mike Frysinger <vapier@gentoo.org>
385
386 * sim-main.h (WITH_MODULO_MEMORY): Delete.
387
797eee42
MF		 3882015-11-15 Mike Frysinger <vapier@gentoo.org>
389
390 * Makefile.in (SIM_OBJS): Delete sim-reason.o and sim-stop.o.
391
6e4f085c
MF		 3922015-11-14 Mike Frysinger <vapier@gentoo.org>
393
394 * interp.c (sim_close): Rename to ...
395 (mips_sim_close): ... this. Delete calls to sim_module_uninstall and
396 sim_io_shutdown.
397 * sim-main.h (mips_sim_close): Declare.
398 (SIM_CLOSE_HOOK): Define.
399
8e394ffc
AB		 4002015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
401 Ali Lown <ali.lown@imgtec.com>
402
403 * Makefile.in (tmp-micromips): New rule.
404 (tmp-mach-multi): Add support for micromips.
405 * configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
406 that works for both mips64 and micromips64.
407 (mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
408 micromips32.
409 Add build support for micromips.
410 * dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
411 do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
412 do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
413 do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
414 do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
415 do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
416 do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
417 do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
418 Refactored instruction code to use these functions.
419 * dsp2.igen: Refactored instruction code to use the new functions.
420 * interp.c (decode_coproc): Refactored to work with any instruction
421 encoding.
422 (isa_mode): New variable
423 (RSVD_INSTRUCTION): Changed to 0x00000039.
424 * m16.igen (BREAK16): Refactored instruction to use do_break16.
425 (JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
426 * micromips.dc: New file.
427 * micromips.igen: New file.
428 * micromips16.dc: New file.
429 * micromipsdsp.igen: New file.
430 * micromipsrun.c: New file.
431 * mips.igen (do_swc1): Changed to work with any instruction encoding.
432 (do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
433 do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo,
434 do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu,
435 do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu,
436 do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub,
437 do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo,
438 do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc,
439 do_scd, do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu,
440 do_tgeu, do_tlt do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt,
441 do_add_fmt, do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1,
442 do_cvt_d_fmt, do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl,
443 do_cvt_s_pu, do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt,
444 do_luxc1_32, do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b,
445 do_mov_fmt, do_movtf, do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt,
446 do_mtc1b, do_mul_fmt, do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps,
447 do_plu_ps, do_pul_ps, do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt,
448 do_prefx, do_sdc1, do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt,
449 do_swc1, do_swxc1, do_trunc_fmt): New functions, refactored from existing
450 instructions.
451 Refactored instruction code to use these functions.
452 (RSVD): Changed to use new reserved instruction.
453 (loadstore_ea, not_word_value, unpredictable, check_mt_hilo,
454 check_mf_hilo, check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32,
455 do_sdc1, do_suxc1_32, check_fmt_p, check_fpu, do_load_double,
456 do_store_double): Added micromips32 and micromips64 models.
457 Added include for micromips.igen and micromipsdsp.igen
458 Add micromips32 and micromips64 models.
459 (DecodeCoproc): Updated to use new macro definition.
460 * mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
461 do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
462 do_seb, do_seh do_rdhwr, do_wsbh): New functions.
463 Refactored instruction code to use these functions.
464 * sim-main.h (CP0_operation): New enum.
465 (DecodeCoproc): Updated macro.
466 (IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
467 MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16,
468 MICROMIPS_DELAYSLOT_SIZE_32, ISA_MODE_MIPS32 and
469 ISA_MODE_MICROMIPS): New defines.
470 (sim_state): Add isa_mode field.
471
8d0978fb
MF		 4722015-06-23 Mike Frysinger <vapier@gentoo.org>
473
474 * configure: Regenerate.
475
306f4178
MF		 4762015-06-12 Mike Frysinger <vapier@gentoo.org>
477
478 * configure.ac: Change configure.in to configure.ac.
479 * configure: Regenerate.
480
a3487082
MF		 4812015-06-12 Mike Frysinger <vapier@gentoo.org>
482
483 * configure: Regenerate.
484
29bc024d
MF		 4852015-06-12 Mike Frysinger <vapier@gentoo.org>
486
487 * interp.c [TRACE]: Delete.
488 (TRACE): Change to WITH_TRACE_ANY_P.
489 [!WITH_TRACE_ANY_P] (open_trace): Define.
490 (mips_option_handler, open_trace, sim_close, dotrace):
491 Change defined(TRACE) to WITH_TRACE_ANY_P.
492 (sim_open): Delete TRACE ifdef check.
493 * sim-main.c (load_memory): Delete TRACE ifdef check.
494 (store_memory): Likewise.
495 * sim-main.h [WITH_TRACE_ANY_P] (dotrace, tracefh): Protect decls.
496 [!WITH_TRACE_ANY_P] (dotrace): Define.
497
3ebe2863
MF		 4982015-04-18 Mike Frysinger <vapier@gentoo.org>
499
500 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESTART_HOOK): Delete
501 comments.
502
20bca71d
MF		 5032015-04-18 Mike Frysinger <vapier@gentoo.org>
504
505 * sim-main.h (SIM_CPU): Delete.
506
7e83aa92
MF		 5072015-04-18 Mike Frysinger <vapier@gentoo.org>
508
509 * sim-main.h (sim_cia): Delete.
510
034685f9
MF		 5112015-04-17 Mike Frysinger <vapier@gentoo.org>
512
513 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Change CIA_GET to
514 PU_PC_GET.
515 * interp.c (interrupt_event): Change CIA_GET to CPU_PC_GET.
516 (sim_create_inferior): Change CIA_SET to CPU_PC_SET.
517 * m16run.c (sim_engine_run): Change CIA_GET to CPU_PC_GET and
518 CIA_SET to CPU_PC_SET.
519 * sim-main.h (CIA_GET, CIA_SET): Delete.
520
78e9aa70
MF		 5212015-04-15 Mike Frysinger <vapier@gentoo.org>
522
523 * Makefile.in (SIM_OBJS): Delete sim-cpu.o.
524 * sim-main.h (STATE_CPU): Delete.
525
bf12d44e
MF		 5262015-04-13 Mike Frysinger <vapier@gentoo.org>
527
528 * configure: Regenerate.
529
7bebb329
MF		 5302015-04-13 Mike Frysinger <vapier@gentoo.org>
531
532 * Makefile.in (SIM_OBJS): Add sim-cpu.o.
533 * interp.c (mips_pc_get, mips_pc_set): New functions.
534 (sim_open): Declare new local var i. Call sim_cpu_alloc_all.
535 Call CPU_PC_FETCH & CPU_PC_STORE for all cpus.
536 (sim_pc_get): Delete.
537 * sim-main.h (SIM_CPU): Define.
538 (struct sim_state): Change cpu to an array of pointers.
539 (STATE_CPU): Drop &.
540
8ac57fbd
MF		 5412015-04-13 Mike Frysinger <vapier@gentoo.org>
542
543 * interp.c (mips_option_handler, open_trace, sim_close,
544 sim_write, sim_read, sim_store_register, sim_fetch_register,
545 sim_create_inferior, pr_addr, pr_uword64): Convert old style
546 prototypes.
547 (sim_open): Convert old style prototype. Change casts with
548 sim_write to unsigned char *.
549 (fetch_str): Change null to unsigned char, and change cast to
550 unsigned char *.
551 (sim_monitor): Change c & ch to unsigned char. Change cast to
552 unsigned char *.
553
e787f858
MF		 5542015-04-12 Mike Frysinger <vapier@gentoo.org>
555
556 * Makefile.in (SIM_OBJS): Move interp.o to the start of the list.
557
122bbfb5
MF		 5582015-04-06 Mike Frysinger <vapier@gentoo.org>
559
560 * Makefile.in (SIM_OBJS): Delete sim-engine.o.
561
0fe84f3f
MF		 5622015-04-01 Mike Frysinger <vapier@gentoo.org>
563
564 * tconfig.h (SIM_HAVE_PROFILE): Delete.
565
aadc9410
MF		 5662015-03-31 Mike Frysinger <vapier@gentoo.org>
567
568 * config.in, configure: Regenerate.
569
05f53ed6
MF		 5702015-03-24 Mike Frysinger <vapier@gentoo.org>
571
572 * interp.c (sim_pc_get): New function.
573
c0931f26
MF		 5742015-03-24 Mike Frysinger <vapier@gentoo.org>
575
576 * sim-main.h (SIM_HAVE_BIENDIAN): Delete.
577 * tconfig.h (SIM_HAVE_BIENDIAN): Delete.
578
30452bbe
MF		 5792015-03-24 Mike Frysinger <vapier@gentoo.org>
580
581 * configure: Regenerate.
582
64dd13df
MF		 5832015-03-23 Mike Frysinger <vapier@gentoo.org>
584
585 * configure: Regenerate.
586
49cd1634
MF		 5872015-03-23 Mike Frysinger <vapier@gentoo.org>
588
589 * configure: Regenerate.
590 * configure.ac (mips_extra_objs): Delete.
591 * Makefile.in (MIPS_EXTRA_OBJS): Delete.
592 (SIM_OBJS): Delete MIPS_EXTRA_OBJS.
593
3649cb06
MF		 5942015-03-23 Mike Frysinger <vapier@gentoo.org>
595
596 * configure: Regenerate.
597 * configure.ac: Delete sim_hw checks for dv-sockser.
598
ae7d0cac
MF		 5992015-03-16 Mike Frysinger <vapier@gentoo.org>
600
601 * config.in, configure: Regenerate.
602 * tconfig.in: Rename file ...
603 * tconfig.h: ... here.
604
8406bb59
MF		 6052015-03-15 Mike Frysinger <vapier@gentoo.org>
606
607 * tconfig.in: Delete includes.
608 [HAVE_DV_SOCKSER]: Delete.
609
465fb143
MF		 6102015-03-14 Mike Frysinger <vapier@gentoo.org>
611
612 * Makefile.in (SIM_RUN_OBJS): Delete.
613
5cddc23a
MF		 6142015-03-14 Mike Frysinger <vapier@gentoo.org>
615
616 * configure.ac (AC_CHECK_HEADERS): Delete.
617 * aclocal.m4, configure: Regenerate.
618
2974be62
AM		 6192014-08-19 Alan Modra <amodra@gmail.com>
620
621 * configure: Regenerate.
622
faa743bb
RM		 6232014-08-15 Roland McGrath <mcgrathr@google.com>
624
625 * configure: Regenerate.
626 * config.in: Regenerate.
627
1a8a700e
MF		 6282014-03-04 Mike Frysinger <vapier@gentoo.org>
629
630 * configure: Regenerate.
631
bf3d9781
AM		 6322013-09-23 Alan Modra <amodra@gmail.com>
633
634 * configure: Regenerate.
635
31e6ad7d
MF		 6362013-06-03 Mike Frysinger <vapier@gentoo.org>
637
638 * aclocal.m4, configure: Regenerate.
639
d3685d60
TT		 6402013-05-10 Freddie Chopin <freddie_chopin@op.pl>
641
642 * configure: Rebuild.
643
1517bd27
MF		 6442013-03-26 Mike Frysinger <vapier@gentoo.org>
645
646 * configure: Regenerate.
647
3be31516
JS		 6482013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
649
650 * configure.ac: Address use of dv-sockser.o.
651 * tconfig.in: Conditionalize use of dv_sockser_install.
652 * configure: Regenerated.
653 * config.in: Regenerated.
654
37cb8f8e
SE		 6552012-10-04 Chao-ying Fu <fu@mips.com>
656 Steve Ellcey <sellcey@mips.com>
657
658 * mips/mips3264r2.igen (rdhwr): New.
659
87c8644f
JS		 6602012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
661
662 * configure.ac: Always link against dv-sockser.o.
663 * configure: Regenerate.
664
5f3ef9d0
JB		 6652012-06-15 Joel Brobecker <brobecker@adacore.com>
666
667 * config.in, configure: Regenerate.
668
a6ff997c
NC		 6692012-05-18 Nick Clifton <nickc@redhat.com>
670
671 PR 14072
672 * interp.c: Include config.h before system header files.
673
2232061b
MF		 6742012-03-24 Mike Frysinger <vapier@gentoo.org>
675
676 * aclocal.m4, config.in, configure: Regenerate.
677
db2e4d67
MF		 6782011-12-03 Mike Frysinger <vapier@gentoo.org>
679
680 * aclocal.m4: New file.
681 * configure: Regenerate.
682
4399a56b
MF		 6832011-10-19 Mike Frysinger <vapier@gentoo.org>
684
685 * configure: Regenerate after common/acinclude.m4 update.
686
9c082ca8
MF		 6872011-10-17 Mike Frysinger <vapier@gentoo.org>
688
689 * configure.ac: Change include to common/acinclude.m4.
690
6ffe910a
MF		 6912011-10-17 Mike Frysinger <vapier@gentoo.org>
692
693 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
694 call. Replace common.m4 include with SIM_AC_COMMON.
695 * configure: Regenerate.
696
31b28250
HPN		 6972011-07-08 Hans-Peter Nilsson <hp@axis.com>
698
3faa01e3
HPN		 699 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
700 $(SIM_EXTRA_DEPS).
701 (tmp-mach-multi): Exit early when igen fails.
31b28250 702
2419798b
MF		 7032011-07-05 Mike Frysinger <vapier@gentoo.org>
704
705 * interp.c (sim_do_command): Delete.
706
d79fe0d6
MF		 7072011-02-14 Mike Frysinger <vapier@gentoo.org>
708
709 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
710 (tx3904sio_fifo_reset): Likewise.
711 * interp.c (sim_monitor): Likewise.
712
5558e7e6
MF		 7132010-04-14 Mike Frysinger <vapier@gentoo.org>
714
715 * interp.c (sim_write): Add const to buffer arg.
716
35aafff4
JB		 7172010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
718
719 * interp.c: Don't include sysdep.h
720
3725885a
RW		 7212010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
722
723 * configure: Regenerate.
724
d6416cdc
RW		 7252009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
726
81ecdfbb
RW		 727 * config.in: Regenerate.
728 * configure: Likewise.
729
d6416cdc
RW		 730 * configure: Regenerate.
731
b5bd9624
HPN		 7322008-07-11 Hans-Peter Nilsson <hp@axis.com>
733
734 * configure: Regenerate to track ../common/common.m4 changes.
735 * config.in: Ditto.
736
6efef468 7372008-06-06 Vladimir Prus <vladimir@codesourcery.com>
72f4393d
L		 738 Daniel Jacobowitz <dan@codesourcery.com>
739 Joseph Myers <joseph@codesourcery.com>
6efef468
JM		 740
741 * configure: Regenerate.
742
60dc88db
RS		 7432007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
744
745 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
746 that unconditionally allows fmt_ps.
747 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
748 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
749 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
750 filter from 64,f to 32,f.
751 (PREFX): Change filter from 64 to 32.
752 (LDXC1, LUXC1): Provide separate mips32r2 implementations
753 that use do_load_double instead of do_load. Make both LUXC1
754 versions unpredictable if SizeFGR () != 64.
755 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
756 instead of do_store. Remove unused variable. Make both SUXC1
757 versions unpredictable if SizeFGR () != 64.
758
599ca73e
RS		 7592007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
760
761 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
762 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
763 shifts for that case.
764
2525df03
NC		 7652007-09-04 Nick Clifton <nickc@redhat.com>
766
767 * interp.c (options enum): Add OPTION_INFO_MEMORY.
768 (display_mem_info): New static variable.
769 (mips_option_handler): Handle OPTION_INFO_MEMORY.
770 (mips_options): Add info-memory and memory-info.
771 (sim_open): After processing the command line and board
772 specification, check display_mem_info. If it is set then
773 call the real handler for the --memory-info command line
774 switch.
775
35ee6e1e
JB		 7762007-08-24 Joel Brobecker <brobecker@adacore.com>
777
778 * configure.ac: Change license of multi-run.c to GPL version 3.
779 * configure: Regenerate.
780
d5fb0879
RS		 7812007-06-28 Richard Sandiford <richard@codesourcery.com>
782
783 * configure.ac, configure: Revert last patch.
784
2a2ce21b
RS		 7852007-06-26 Richard Sandiford <richard@codesourcery.com>
786
787 * configure.ac (sim_mipsisa3264_configs): New variable.
788 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
789 every configuration support all four targets, using the triplet to
790 determine the default.
791 * configure: Regenerate.
792
efdcccc9
RS		 7932007-06-25 Richard Sandiford <richard@codesourcery.com>
794
0a7692b2 795 * Makefile.in (m16run.o): New rule.
efdcccc9 796
f532a356
TS		 7972007-05-15 Thiemo Seufer <ths@mips.com>
798
799 * mips3264r2.igen (DSHD): Fix compile warning.
800
bfe9c90b
TS		 8012007-05-14 Thiemo Seufer <ths@mips.com>
802
803 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
804 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
805 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
806 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
807 for mips32r2.
808
53f4826b
TS		 8092007-03-01 Thiemo Seufer <ths@mips.com>
810
811 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
812 and mips64.
813
8bf3ddc8
TS		 8142007-02-20 Thiemo Seufer <ths@mips.com>
815
816 * dsp.igen: Update copyright notice.
817 * dsp2.igen: Fix copyright notice.
818
8b082fb1 8192007-02-20 Thiemo Seufer <ths@mips.com>
72f4393d 820 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 821
822 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
823 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
824 Add dsp2 to sim_igen_machine.
825 * configure: Regenerate.
826 * dsp.igen (do_ph_op): Add MUL support when op = 2.
827 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
828 (mulq_rs.ph): Use do_ph_mulq.
829 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
830 * mips.igen: Add dsp2 model and include dsp2.igen.
831 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
832 for *mips32r2, *mips64r2, *dsp.
833 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
834 for *mips32r2, *mips64r2, *dsp2.
835 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
836
b1004875 8372007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 838 Nigel Stephens <nigel@mips.com>
b1004875
TS		 839
840 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
841 jumps with hazard barrier.
842
f8df4c77 8432007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 844 Nigel Stephens <nigel@mips.com>
f8df4c77
TS		 845
846 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
847 after each call to sim_io_write.
848
b1004875 8492007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 850 Nigel Stephens <nigel@mips.com>
b1004875
TS		 851
852 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
853 supported by this simulator.
07802d98
TS		 854 (decode_coproc): Recognise additional CP0 Config registers
855 correctly.
856
14fb6c5a 8572007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d
L		 858 Nigel Stephens <nigel@mips.com>
859 David Ung <davidu@mips.com>
14fb6c5a
TS		 860
861 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
862 uninterpreted formats. If fmt is one of the uninterpreted types
863 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
864 fmt_word, and fmt_uninterpreted_64 like fmt_long.
865 (store_fpr): When writing an invalid odd register, set the
866 matching even register to fmt_unknown, not the following register.
867 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
868 the the memory window at offset 0 set by --memory-size command
869 line option.
870 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
871 point register.
872 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
873 register.
874 (sim_monitor): When returning the memory size to the MIPS
875 application, use the value in STATE_MEM_SIZE, not an arbitrary
876 hardcoded value.
877 (cop_lw): Don' mess around with FPR_STATE, just pass
878 fmt_uninterpreted_32 to StoreFPR.
879 (cop_sw): Similarly.
880 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
881 (cop_sd): Similarly.
882 * mips.igen (not_word_value): Single version for mips32, mips64
883 and mips16.
884
c8847145 8852007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 886 Nigel Stephens <nigel@mips.com>
c8847145
TS		 887
888 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
889 MBytes.
890
4b5d35ee
TS		 8912007-02-17 Thiemo Seufer <ths@mips.com>
892
893 * configure.ac (mips*-sde-elf*): Move in front of generic machine
894 configuration.
895 * configure: Regenerate.
896
3669427c
TS		 8972007-02-17 Thiemo Seufer <ths@mips.com>
898
899 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
900 Add mdmx to sim_igen_machine.
901 (mipsisa64*-*-*): Likewise. Remove dsp.
902 (mipsisa32*-*-*): Remove dsp.
903 * configure: Regenerate.
904
109ad085
TS		 9052007-02-13 Thiemo Seufer <ths@mips.com>
906
907 * configure.ac: Add mips*-sde-elf* target.
908 * configure: Regenerate.
909
921d7ad3
HPN		 9102006-12-21 Hans-Peter Nilsson <hp@axis.com>
911
912 * acconfig.h: Remove.
913 * config.in, configure: Regenerate.
914
02f97da7
TS		 9152006-11-07 Thiemo Seufer <ths@mips.com>
916
917 * dsp.igen (do_w_op): Fix compiler warning.
918
2d2733fc 9192006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 920 David Ung <davidu@mips.com>
2d2733fc
TS		 921
922 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
923 sim_igen_machine.
924 * configure: Regenerate.
925 * mips.igen (model): Add smartmips.
926 (MADDU): Increment ACX if carry.
927 (do_mult): Clear ACX.
928 (ROR,RORV): Add smartmips.
72f4393d 929 (include): Include smartmips.igen.
2d2733fc
TS		 930 * sim-main.h (ACX): Set to REGISTERS[89].
931 * smartmips.igen: New file.
932
d85c3a10 9332006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 934 David Ung <davidu@mips.com>
d85c3a10
TS		 935
936 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
937 mips3264r2.igen. Add missing dependency rules.
938 * m16e.igen: Support for mips16e save/restore instructions.
939
e85e3205
RE		 9402006-06-13 Richard Earnshaw <rearnsha@arm.com>
941
942 * configure: Regenerated.
943
2f0122dc
DJ		 9442006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
945
946 * configure: Regenerated.
947
20e95c23
DJ		 9482006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
949
950 * configure: Regenerated.
951
69088b17
CF		 9522006-05-15 Chao-ying Fu <fu@mips.com>
953
954 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
955
0275de4e
NC		 9562006-04-18 Nick Clifton <nickc@redhat.com>
957
958 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
959 statement.
960
b3a3ffef
HPN		 9612006-03-29 Hans-Peter Nilsson <hp@axis.com>
962
963 * configure: Regenerate.
964
40a5538e
CF		 9652005-12-14 Chao-ying Fu <fu@mips.com>
966
967 * Makefile.in (SIM_OBJS): Add dsp.o.
968 (dsp.o): New dependency.
969 (IGEN_INCLUDE): Add dsp.igen.
970 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
971 mipsisa64*-*-*): Add dsp to sim_igen_machine.
972 * configure: Regenerate.
973 * mips.igen: Add dsp model and include dsp.igen.
974 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
975 because these instructions are extended in DSP ASE.
976 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
977 adding 6 DSP accumulator registers and 1 DSP control register.
978 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
979 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
980 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
981 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
982 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
983 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
984 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
985 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
986 DSPCR_CCOND_SMASK): New define.
987 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
988 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
989
21d14896
ILT		 9902005-07-08 Ian Lance Taylor <ian@airs.com>
991
992 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
993
b16d63da 9942005-06-16 David Ung <davidu@mips.com>
72f4393d
L		 995 Nigel Stephens <nigel@mips.com>
996
997 * mips.igen: New mips16e model and include m16e.igen.
998 (check_u64): Add mips16e tag.
999 * m16e.igen: New file for MIPS16e instructions.
1000 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
1001 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
1002 models.
1003 * configure: Regenerate.
b16d63da 1004
e70cb6cd 10052005-05-26 David Ung <davidu@mips.com>
72f4393d 1006
e70cb6cd
CD		 1007 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
1008 tags to all instructions which are applicable to the new ISAs.
1009 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
1010 vr.igen.
1011 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
72f4393d 1012 instructions.
e70cb6cd
CD		 1013 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
1014 to mips.igen.
1015 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
1016 * configure: Regenerate.
72f4393d 1017
2b193c4a
MK		 10182005-03-23 Mark Kettenis <kettenis@gnu.org>
1019
1020 * configure: Regenerate.
1021
35695fd6
AC		 10222005-01-14 Andrew Cagney <cagney@gnu.org>
1023
1024 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
1025 explicit call to AC_CONFIG_HEADER.
1026 * configure: Regenerate.
1027
f0569246
AC		 10282005-01-12 Andrew Cagney <cagney@gnu.org>
1029
1030 * configure.ac: Update to use ../common/common.m4.
1031 * configure: Re-generate.
1032
38f48d72
AC		 10332005-01-11 Andrew Cagney <cagney@localhost.localdomain>
1034
1035 * configure: Regenerated to track ../common/aclocal.m4 changes.
1036
b7026657
AC		 10372005-01-07 Andrew Cagney <cagney@gnu.org>
1038
1039 * configure.ac: Rename configure.in, require autoconf 2.59.
1040 * configure: Re-generate.
1041
379832de
HPN		 10422004-12-08 Hans-Peter Nilsson <hp@axis.com>
1043
1044 * configure: Regenerate for ../common/aclocal.m4 update.
1045
cd62154c 10462004-09-24 Monika Chaddha <monika@acmet.com>
72f4393d 1047
cd62154c
AC		 1048 Committed by Andrew Cagney.
1049 * m16.igen (CMP, CMPI): Fix assembler.
1050
e5da76ec
CD		 10512004-08-18 Chris Demetriou <cgd@broadcom.com>
1052
1053 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
1054 * configure: Regenerate.
1055
139181c8
CD		 10562004-06-25 Chris Demetriou <cgd@broadcom.com>
1057
1058 * configure.in (sim_m16_machine): Include mipsIII.
1059 * configure: Regenerate.
1060
1a27f959
CD		 10612004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
1062
72f4393d 1063 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
1a27f959
CD		 1064 from COP0_BADVADDR.
1065 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
1066
5dbb7b5a
CD		 10672004-04-10 Chris Demetriou <cgd@broadcom.com>
1068
1069 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
1070
14234056
CD		 10712004-04-09 Chris Demetriou <cgd@broadcom.com>
1072
1073 * mips.igen (check_fmt): Remove.
1074 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
1075 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
1076 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
1077 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
1078 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
1079 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
1080 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1081 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
1082 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
1083 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
1084
c6f9085c
CD		 10852004-04-09 Chris Demetriou <cgd@broadcom.com>
1086
1087 * sb1.igen (check_sbx): New function.
1088 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
1089
11d66e66 10902004-03-29 Chris Demetriou <cgd@broadcom.com>
0e1b7197
RS		 1091 Richard Sandiford <rsandifo@redhat.com>
1092
1093 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
1094 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
1095 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
1096 separate implementations for mipsIV and mipsV. Use new macros to
1097 determine whether the restrictions apply.
1098
b3208fb8
CD		 10992004-01-19 Chris Demetriou <cgd@broadcom.com>
1100
1101 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
1102 (check_mult_hilo): Improve comments.
1103 (check_div_hilo): Likewise. Also, fork off a new version
1104 to handle mips32/mips64 (since there are no hazards to check
1105 in MIPS32/MIPS64).
1106
9a1d84fb
CD		 11072003-06-17 Richard Sandiford <rsandifo@redhat.com>
1108
1109 * mips.igen (do_dmultx): Fix check for negative operands.
1110
ae451ac6
ILT		 11112003-05-16 Ian Lance Taylor <ian@airs.com>
1112
1113 * Makefile.in (SHELL): Make sure this is defined.
1114 (various): Use $(SHELL) whenever we invoke move-if-change.
1115
dd69d292
CD		 11162003-05-03 Chris Demetriou <cgd@broadcom.com>
1117
1118 * cp1.c: Tweak attribution slightly.
1119 * cp1.h: Likewise.
1120 * mdmx.c: Likewise.
1121 * mdmx.igen: Likewise.
1122 * mips3d.igen: Likewise.
1123 * sb1.igen: Likewise.
1124
bcd0068e
CD		 11252003-04-15 Richard Sandiford <rsandifo@redhat.com>
1126
1127 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
1128 unsigned operands.
1129
6b4a8935
AC		 11302003-02-27 Andrew Cagney <cagney@redhat.com>
1131
601da316
AC		 1132 * interp.c (sim_open): Rename _bfd to bfd.
1133 (sim_create_inferior): Ditto.
6b4a8935 1134
d29e330f
CD		 11352003-01-14 Chris Demetriou <cgd@broadcom.com>
1136
1137 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
1138
a2353a08
CD		 11392003-01-14 Chris Demetriou <cgd@broadcom.com>
1140
1141 * mips.igen (EI, DI): Remove.
1142
80551777
CD		 11432003-01-05 Richard Sandiford <rsandifo@redhat.com>
1144
1145 * Makefile.in (tmp-run-multi): Fix mips16 filter.
1146
4c54fc26
CD		 11472003-01-04 Richard Sandiford <rsandifo@redhat.com>
1148 Andrew Cagney <ac131313@redhat.com>
1149 Gavin Romig-Koch <gavin@redhat.com>
1150 Graydon Hoare <graydon@redhat.com>
1151 Aldy Hernandez <aldyh@redhat.com>
1152 Dave Brolley <brolley@redhat.com>
1153 Chris Demetriou <cgd@broadcom.com>
1154
1155 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
1156 (sim_mach_default): New variable.
1157 (mips64vr-*-*, mips64vrel-*-*): New configurations.
1158 Add a new simulator generator, MULTI.
1159 * configure: Regenerate.
1160 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
1161 (multi-run.o): New dependency.
1162 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
1163 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
1164 (tmp-multi): Combine them.
1165 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
1166 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
1167 (distclean-extra): New rule.
1168 * sim-main.h: Include bfd.h.
1169 (MIPS_MACH): New macro.
1170 * mips.igen (vr4120, vr5400, vr5500): New models.
1171 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
1172 * vr.igen: Replace with new version.
1173
e6c674b8
CD		 11742003-01-04 Chris Demetriou <cgd@broadcom.com>
1175
1176 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
1177 * configure: Regenerate.
1178
28f50ac8
CD		 11792002-12-31 Chris Demetriou <cgd@broadcom.com>
1180
1181 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
1182 * mips.igen: Remove all invocations of check_branch_bug and
1183 mark_branch_bug.
1184
5071ffe6
CD		 11852002-12-16 Chris Demetriou <cgd@broadcom.com>
1186
72f4393d 1187 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
5071ffe6 1188
06e7837e
CD		 11892002-07-30 Chris Demetriou <cgd@broadcom.com>
1190
1191 * mips.igen (do_load_double, do_store_double): New functions.
1192 (LDC1, SDC1): Rename to...
1193 (LDC1b, SDC1b): respectively.
1194 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
1195
2265c243
MS		 11962002-07-29 Michael Snyder <msnyder@redhat.com>
1197
1198 * cp1.c (fp_recip2): Modify initialization expression so that
1199 GCC will recognize it as constant.
1200
a2f8b4f3
CD		 12012002-06-18 Chris Demetriou <cgd@broadcom.com>
1202
1203 * mdmx.c (SD_): Delete.
1204 (Unpredictable): Re-define, for now, to directly invoke
1205 unpredictable_action().
1206 (mdmx_acc_op): Fix error in .ob immediate handling.
1207
b4b6c939
AC		 12082002-06-18 Andrew Cagney <cagney@redhat.com>
1209
1210 * interp.c (sim_firmware_command): Initialize `address'.
1211
c8cca39f
AC		 12122002-06-16 Andrew Cagney <ac131313@redhat.com>
1213
1214 * configure: Regenerated to track ../common/aclocal.m4 changes.
1215
e7e81181 12162002-06-14 Chris Demetriou <cgd@broadcom.com>
72f4393d 1217 Ed Satterthwaite <ehs@broadcom.com>
e7e81181
CD		 1218
1219 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
1220 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
1221 * mips.igen: Include mips3d.igen.
1222 (mips3d): New model name for MIPS-3D ASE instructions.
1223 (CVT.W.fmt): Don't use this instruction for word (source) format
72f4393d 1224 instructions.
e7e81181
CD		 1225 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
1226 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
1227 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
1228 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
1229 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
1230 (RSquareRoot1, RSquareRoot2): New macros.
1231 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
1232 (fp_rsqrt2): New functions.
1233 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
1234 * configure: Regenerate.
1235
3a2b820e 12362002-06-13 Chris Demetriou <cgd@broadcom.com>
72f4393d 1237 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 1238
1239 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
1240 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
1241 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
1242 (convert): Note that this function is not used for paired-single
1243 format conversions.
1244 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
1245 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
1246 (check_fmt_p): Enable paired-single support.
1247 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
1248 (PUU.PS): New instructions.
1249 (CVT.S.fmt): Don't use this instruction for paired-single format
1250 destinations.
1251 * sim-main.h (FP_formats): New value 'fmt_ps.'
1252 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
1253 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
1254
d18ea9c2
CD		 12552002-06-12 Chris Demetriou <cgd@broadcom.com>
1256
1257 * mips.igen: Fix formatting of function calls in
1258 many FP operations.
1259
95fd5cee
CD		 12602002-06-12 Chris Demetriou <cgd@broadcom.com>
1261
1262 * mips.igen (MOVN, MOVZ): Trace result.
1263 (TNEI): Print "tnei" as the opcode name in traces.
1264 (CEIL.W): Add disassembly string for traces.
1265 (RSQRT.fmt): Make location of disassembly string consistent
1266 with other instructions.
1267
4f0d55ae
CD		 12682002-06-12 Chris Demetriou <cgd@broadcom.com>
1269
1270 * mips.igen (X): Delete unused function.
1271
3c25f8c7
AC		 12722002-06-08 Andrew Cagney <cagney@redhat.com>
1273
1274 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
1275
f3c08b7e 12762002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1277 Ed Satterthwaite <ehs@broadcom.com>
f3c08b7e
CD		 1278
1279 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
1280 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
1281 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
1282 (fp_nmsub): New prototypes.
1283 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
1284 (NegMultiplySub): New defines.
1285 * mips.igen (RSQRT.fmt): Use RSquareRoot().
1286 (MADD.D, MADD.S): Replace with...
1287 (MADD.fmt): New instruction.
1288 (MSUB.D, MSUB.S): Replace with...
1289 (MSUB.fmt): New instruction.
1290 (NMADD.D, NMADD.S): Replace with...
1291 (NMADD.fmt): New instruction.
1292 (NMSUB.D, MSUB.S): Replace with...
1293 (NMSUB.fmt): New instruction.
1294
52714ff9 12952002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1296 Ed Satterthwaite <ehs@broadcom.com>
52714ff9
CD		 1297
1298 * cp1.c: Fix more comment spelling and formatting.
1299 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
1300 (denorm_mode): New function.
1301 (fpu_unary, fpu_binary): Round results after operation, collect
1302 status from rounding operations, and update the FCSR.
1303 (convert): Collect status from integer conversions and rounding
1304 operations, and update the FCSR. Adjust NaN values that result
1305 from conversions. Convert to use sim_io_eprintf rather than
1306 fprintf, and remove some debugging code.
1307 * cp1.h (fenr_FS): New define.
1308
577d8c4b
CD		 13092002-06-07 Chris Demetriou <cgd@broadcom.com>
1310
1311 * cp1.c (convert): Remove unusable debugging code, and move MIPS
1312 rounding mode to sim FP rounding mode flag conversion code into...
1313 (rounding_mode): New function.
1314
196496ed
CD		 13152002-06-07 Chris Demetriou <cgd@broadcom.com>
1316
1317 * cp1.c: Clean up formatting of a few comments.
1318 (value_fpr): Reformat switch statement.
1319
cfe9ea23 13202002-06-06 Chris Demetriou <cgd@broadcom.com>
72f4393d 1321 Ed Satterthwaite <ehs@broadcom.com>
cfe9ea23
CD		 1322
1323 * cp1.h: New file.
1324 * sim-main.h: Include cp1.h.
1325 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
1326 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
1327 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
1328 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
1329 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
1330 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
1331 * cp1.c: Don't include sim-fpu.h; already included by
1332 sim-main.h. Clean up formatting of some comments.
1333 (NaN, Equal, Less): Remove.
1334 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
1335 (fp_cmp): New functions.
1336 * mips.igen (do_c_cond_fmt): Remove.
1337 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
1338 Compare. Add result tracing.
1339 (CxC1): Remove, replace with...
1340 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
1341 (DMxC1): Remove, replace with...
1342 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
72f4393d
L		 1343 (MxC1): Remove, replace with...
1344 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
cfe9ea23 1345
ee7254b0
CD		 13462002-06-04 Chris Demetriou <cgd@broadcom.com>
1347
1348 * sim-main.h (FGRIDX): Remove, replace all uses with...
1349 (FGR_BASE): New macro.
1350 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
1351 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
1352 (NR_FGR, FGR): Likewise.
1353 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
1354 * mips.igen: Likewise.
1355
d3eb724f
CD		 13562002-06-04 Chris Demetriou <cgd@broadcom.com>
1357
1358 * cp1.c: Add an FSF Copyright notice to this file.
1359
ba46ddd0 13602002-06-04 Chris Demetriou <cgd@broadcom.com>
72f4393d 1361 Ed Satterthwaite <ehs@broadcom.com>
ba46ddd0
CD		 1362
1363 * cp1.c (Infinity): Remove.
1364 * sim-main.h (Infinity): Likewise.
1365
1366 * cp1.c (fp_unary, fp_binary): New functions.
1367 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
1368 (fp_sqrt): New functions, implemented in terms of the above.
1369 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1370 (Recip, SquareRoot): Remove (replaced by functions above).
1371 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
1372 (fp_recip, fp_sqrt): New prototypes.
1373 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1374 (Recip, SquareRoot): Replace prototypes with #defines which
1375 invoke the functions above.
72f4393d 1376
18d8a52d
CD		 13772002-06-03 Chris Demetriou <cgd@broadcom.com>
1378
1379 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
1380 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
1381 file, remove PARAMS from prototypes.
1382 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
1383 simulator state arguments.
1384 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
1385 pass simulator state arguments.
1386 * cp1.c (SD): Redefine as CPU_STATE(cpu).
1387 (store_fpr, convert): Remove 'sd' argument.
1388 (value_fpr): Likewise. Convert to use 'SD' instead.
1389
0f154cbd
CD		 13902002-06-03 Chris Demetriou <cgd@broadcom.com>
1391
1392 * cp1.c (Min, Max): Remove #if 0'd functions.
1393 * sim-main.h (Min, Max): Remove.
1394
e80fc152
CD		 13952002-06-03 Chris Demetriou <cgd@broadcom.com>
1396
1397 * cp1.c: fix formatting of switch case and default labels.
1398 * interp.c: Likewise.
1399 * sim-main.c: Likewise.
1400
bad673a9
CD		 14012002-06-03 Chris Demetriou <cgd@broadcom.com>
1402
1403 * cp1.c: Clean up comments which describe FP formats.
1404 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
1405
7cbea089 14062002-06-03 Chris Demetriou <cgd@broadcom.com>
72f4393d 1407 Ed Satterthwaite <ehs@broadcom.com>
7cbea089
CD		 1408
1409 * configure.in (mipsisa64sb1*-*-*): New target for supporting
1410 Broadcom SiByte SB-1 processor configurations.
1411 * configure: Regenerate.
1412 * sb1.igen: New file.
1413 * mips.igen: Include sb1.igen.
1414 (sb1): New model.
1415 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
1416 * mdmx.igen: Add "sb1" model to all appropriate functions and
1417 instructions.
1418 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
1419 (ob_func, ob_acc): Reference the above.
1420 (qh_acc): Adjust to keep the same size as ob_acc.
1421 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
1422 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
1423
909daa82
CD		 14242002-06-03 Chris Demetriou <cgd@broadcom.com>
1425
1426 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
1427
f4f1b9f1 14282002-06-02 Chris Demetriou <cgd@broadcom.com>
72f4393d 1429 Ed Satterthwaite <ehs@broadcom.com>
f4f1b9f1
CD		 1430
1431 * mips.igen (mdmx): New (pseudo-)model.
1432 * mdmx.c, mdmx.igen: New files.
1433 * Makefile.in (SIM_OBJS): Add mdmx.o.
1434 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
1435 New typedefs.
1436 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
1437 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
1438 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
1439 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
1440 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
1441 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
1442 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
1443 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
1444 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
1445 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
1446 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
1447 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
1448 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
1449 (qh_fmtsel): New macros.
1450 (_sim_cpu): New member "acc".
1451 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
1452 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
1453
5accf1ff
CD		 14542002-05-01 Chris Demetriou <cgd@broadcom.com>
1455
1456 * interp.c: Use 'deprecated' rather than 'depreciated.'
1457 * sim-main.h: Likewise.
1458
402586aa
CD		 14592002-05-01 Chris Demetriou <cgd@broadcom.com>
1460
1461 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
1462 which wouldn't compile anyway.
1463 * sim-main.h (unpredictable_action): New function prototype.
1464 (Unpredictable): Define to call igen function unpredictable().
1465 (NotWordValue): New macro to call igen function not_word_value().
1466 (UndefinedResult): Remove.
1467 * interp.c (undefined_result): Remove.
1468 (unpredictable_action): New function.
1469 * mips.igen (not_word_value, unpredictable): New functions.
1470 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
1471 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
1472 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
1473 NotWordValue() to check for unpredictable inputs, then
1474 Unpredictable() to handle them.
1475
c9b9995a
CD		 14762002-02-24 Chris Demetriou <cgd@broadcom.com>
1477
1478 * mips.igen: Fix formatting of calls to Unpredictable().
1479
e1015982
AC		 14802002-04-20 Andrew Cagney <ac131313@redhat.com>
1481
1482 * interp.c (sim_open): Revert previous change.
1483
b882a66b
AO		 14842002-04-18 Alexandre Oliva <aoliva@redhat.com>
1485
1486 * interp.c (sim_open): Disable chunk of code that wrote code in
1487 vector table entries.
1488
c429b7dd
CD		 14892002-03-19 Chris Demetriou <cgd@broadcom.com>
1490
1491 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
1492 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
1493 unused definitions.
1494
37d146fa
CD		 14952002-03-19 Chris Demetriou <cgd@broadcom.com>
1496
1497 * cp1.c: Fix many formatting issues.
1498
07892c0b
CD		 14992002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1500
1501 * cp1.c (fpu_format_name): New function to replace...
1502 (DOFMT): This. Delete, and update all callers.
1503 (fpu_rounding_mode_name): New function to replace...
1504 (RMMODE): This. Delete, and update all callers.
1505
487f79b7
CD		 15062002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1507
1508 * interp.c: Move FPU support routines from here to...
1509 * cp1.c: Here. New file.
1510 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
1511 (cp1.o): New target.
1512
1e799e28
CD		 15132002-03-12 Chris Demetriou <cgd@broadcom.com>
1514
1515 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
1516 * mips.igen (mips32, mips64): New models, add to all instructions
1517 and functions as appropriate.
1518 (loadstore_ea, check_u64): New variant for model mips64.
1519 (check_fmt_p): New variant for models mipsV and mips64, remove
1520 mipsV model marking fro other variant.
1521 (SLL) Rename to...
1522 (SLLa) this.
1523 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
1524 for mips32 and mips64.
1525 (DCLO, DCLZ): New instructions for mips64.
1526
82f728db
CD		 15272002-03-07 Chris Demetriou <cgd@broadcom.com>
1528
1529 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
1530 immediate or code as a hex value with the "%#lx" format.
1531 (ANDI): Likewise, and fix printed instruction name.
1532
b96e7ef1
CD		 15332002-03-05 Chris Demetriou <cgd@broadcom.com>
1534
1535 * sim-main.h (UndefinedResult, Unpredictable): New macros
1536 which currently do nothing.
1537
d35d4f70
CD		 15382002-03-05 Chris Demetriou <cgd@broadcom.com>
1539
1540 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
1541 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
1542 (status_CU3): New definitions.
1543
1544 * sim-main.h (ExceptionCause): Add new values for MIPS32
1545 and MIPS64: MDMX, MCheck, CacheErr. Update comments
1546 for DebugBreakPoint and NMIReset to note their status in
1547 MIPS32 and MIPS64.
1548 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
1549 (SignalExceptionCacheErr): New exception macros.
1550
3ad6f714
CD		 15512002-03-05 Chris Demetriou <cgd@broadcom.com>
1552
1553 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
1554 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
1555 is always enabled.
1556 (SignalExceptionCoProcessorUnusable): Take as argument the
1557 unusable coprocessor number.
1558
86b77b47
CD		 15592002-03-05 Chris Demetriou <cgd@broadcom.com>
1560
1561 * mips.igen: Fix formatting of all SignalException calls.
1562
97a88e93 15632002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 1564
1565 * sim-main.h (SIGNEXTEND): Remove.
1566
97a88e93 15672002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 1568
1569 * mips.igen: Remove gencode comment from top of file, fix
1570 spelling in another comment.
1571
97a88e93 15722002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 1573
1574 * mips.igen (check_fmt, check_fmt_p): New functions to check
1575 whether specific floating point formats are usable.
1576 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1577 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
1578 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
1579 Use the new functions.
1580 (do_c_cond_fmt): Remove format checks...
1581 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
1582
97a88e93 15832002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 1584
1585 * mips.igen: Fix formatting of check_fpu calls.
1586
41774c9d
CD		 15872002-03-03 Chris Demetriou <cgd@broadcom.com>
1588
1589 * mips.igen (FLOOR.L.fmt): Store correct destination register.
1590
4a0bd876
CD		 15912002-03-03 Chris Demetriou <cgd@broadcom.com>
1592
1593 * mips.igen: Remove whitespace at end of lines.
1594
09297648
CD		 15952002-03-02 Chris Demetriou <cgd@broadcom.com>
1596
1597 * mips.igen (loadstore_ea): New function to do effective
1598 address calculations.
1599 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
1600 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
1601 CACHE): Use loadstore_ea to do effective address computations.
1602
043b7057
CD		 16032002-03-02 Chris Demetriou <cgd@broadcom.com>
1604
1605 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
1606 * mips.igen (LL, CxC1, MxC1): Likewise.
1607
c1e8ada4
CD		 16082002-03-02 Chris Demetriou <cgd@broadcom.com>
1609
1610 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
1611 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
1612 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
1613 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
1614 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
1615 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
1616 Don't split opcode fields by hand, use the opcode field values
1617 provided by igen.
1618
3e1dca16
CD		 16192002-03-01 Chris Demetriou <cgd@broadcom.com>
1620
1621 * mips.igen (do_divu): Fix spacing.
1622
1623 * mips.igen (do_dsllv): Move to be right before DSLLV,
1624 to match the rest of the do_<shift> functions.
1625
fff8d27d
CD		 16262002-03-01 Chris Demetriou <cgd@broadcom.com>
1627
1628 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
1629 DSRL32, do_dsrlv): Trace inputs and results.
1630
0d3e762b
CD		 16312002-03-01 Chris Demetriou <cgd@broadcom.com>
1632
1633 * mips.igen (CACHE): Provide instruction-printing string.
1634
1635 * interp.c (signal_exception): Comment tokens after #endif.
1636
eb5fcf93
CD		 16372002-02-28 Chris Demetriou <cgd@broadcom.com>
1638
1639 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
72f4393d
L		 1640 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
1641 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
1642 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
1643 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
1644 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
1645 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
eb5fcf93
CD		 1646 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
1647
bb22bd7d
CD		 16482002-02-28 Chris Demetriou <cgd@broadcom.com>
1649
1650 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
1651 instruction-printing string.
1652 (LWU): Use '64' as the filter flag.
1653
91a177cf
CD		 16542002-02-28 Chris Demetriou <cgd@broadcom.com>
1655
1656 * mips.igen (SDXC1): Fix instruction-printing string.
1657
387f484a
CD		 16582002-02-28 Chris Demetriou <cgd@broadcom.com>
1659
1660 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
1661 filter flags "32,f".
1662
3d81f391
CD		 16632002-02-27 Chris Demetriou <cgd@broadcom.com>
1664
1665 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1666 as the filter flag.
1667
af5107af
CD		 16682002-02-27 Chris Demetriou <cgd@broadcom.com>
1669
1670 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1671 add a comma) so that it more closely match the MIPS ISA
1672 documentation opcode partitioning.
1673 (PREF): Put useful names on opcode fields, and include
1674 instruction-printing string.
1675
ca971540
CD		 16762002-02-27 Chris Demetriou <cgd@broadcom.com>
1677
1678 * mips.igen (check_u64): New function which in the future will
1679 check whether 64-bit instructions are usable and signal an
1680 exception if not. Currently a no-op.
1681 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1682 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1683 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1684 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1685
1686 * mips.igen (check_fpu): New function which in the future will
1687 check whether FPU instructions are usable and signal an exception
1688 if not. Currently a no-op.
1689 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1690 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1691 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1692 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1693 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1694 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1695 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1696 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1697
1c47a468
CD		 16982002-02-27 Chris Demetriou <cgd@broadcom.com>
1699
1700 * mips.igen (do_load_left, do_load_right): Move to be immediately
1701 following do_load.
1702 (do_store_left, do_store_right): Move to be immediately following
1703 do_store.
1704
603a98e7
CD		 17052002-02-27 Chris Demetriou <cgd@broadcom.com>
1706
1707 * mips.igen (mipsV): New model name. Also, add it to
1708 all instructions and functions where it is appropriate.
1709
c5d00cc7
CD		 17102002-02-18 Chris Demetriou <cgd@broadcom.com>
1711
1712 * mips.igen: For all functions and instructions, list model
1713 names that support that instruction one per line.
1714
074e9cb8
CD		 17152002-02-11 Chris Demetriou <cgd@broadcom.com>
1716
1717 * mips.igen: Add some additional comments about supported
1718 models, and about which instructions go where.
1719 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1720 order as is used in the rest of the file.
1721
9805e229
CD		 17222002-02-11 Chris Demetriou <cgd@broadcom.com>
1723
1724 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1725 indicating that ALU32_END or ALU64_END are there to check
1726 for overflow.
1727 (DADD): Likewise, but also remove previous comment about
1728 overflow checking.
1729
f701dad2
CD		 17302002-02-10 Chris Demetriou <cgd@broadcom.com>
1731
1732 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1733 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1734 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1735 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1736 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1737 fields (i.e., add and move commas) so that they more closely
1738 match the MIPS ISA documentation opcode partitioning.
1739
17402002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098 1741
72f4393d
L		 1742 * mips.igen (ADDI): Print immediate value.
1743 (BREAK): Print code.
1744 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1745 (SLL): Print "nop" specially, and don't run the code
1746 that does the shift for the "nop" case.
20ae0098 1747
9e52972e
FF		 17482001-11-17 Fred Fish <fnf@redhat.com>
1749
1750 * sim-main.h (float_operation): Move enum declaration outside
1751 of _sim_cpu struct declaration.
1752
c0efbca4
JB		 17532001-04-12 Jim Blandy <jimb@redhat.com>
1754
1755 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1756 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1757 set of the FCSR.
1758 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1759 PENDING_FILL, and you can get the intended effect gracefully by
1760 calling PENDING_SCHED directly.
1761
fb891446
BE		 17622001-02-23 Ben Elliston <bje@redhat.com>
1763
1764 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1765 already defined elsewhere.
1766
8030f857
BE		 17672001-02-19 Ben Elliston <bje@redhat.com>
1768
1769 * sim-main.h (sim_monitor): Return an int.
1770 * interp.c (sim_monitor): Add return values.
1771 (signal_exception): Handle error conditions from sim_monitor.
1772
56b48a7a
CD		 17732001-02-08 Ben Elliston <bje@redhat.com>
1774
1775 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1776 (store_memory): Likewise, pass cia to sim_core_write*.
1777
d3ee60d9
FCE		 17782000-10-19 Frank Ch. Eigler <fche@redhat.com>
1779
1780 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1781 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1782
071da002
AC		 1783Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1784
1785 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1786 * Makefile.in: Don't delete *.igen when cleaning directory.
1787
a28c02cd
AC		 1788Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1789
1790 * m16.igen (break): Call SignalException not sim_engine_halt.
1791
80ee11fa
AC		 1792Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1793
1794 From Jason Eckhardt:
1795 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1796
673388c0
AC		 1797Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1798
1799 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1800
4c0deff4
NC		 18012000-05-24 Michael Hayes <mhayes@cygnus.com>
1802
1803 * mips.igen (do_dmultx): Fix typo.
1804
eb2d80b4
AC		 1805Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1806
1807 * configure: Regenerated to track ../common/aclocal.m4 changes.
1808
dd37a34b
AC		 1809Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1810
1811 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1812
4c0deff4
NC		 18132000-04-12 Frank Ch. Eigler <fche@redhat.com>
1814
1815 * sim-main.h (GPR_CLEAR): Define macro.
1816
e30db738
AC		 1817Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1818
1819 * interp.c (decode_coproc): Output long using %lx and not %s.
1820
cb7450ea
FCE		 18212000-03-21 Frank Ch. Eigler <fche@redhat.com>
1822
1823 * interp.c (sim_open): Sort & extend dummy memory regions for
1824 --board=jmr3904 for eCos.
1825
a3027dd7
FCE		 18262000-03-02 Frank Ch. Eigler <fche@redhat.com>
1827
1828 * configure: Regenerated.
1829
1830Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1831
1832 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1833 calls, conditional on the simulator being in verbose mode.
1834
dfcd3bfb
JM		 1835Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1836
1837 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1838 cache don't get ReservedInstruction traps.
1839
c2d11a7d
JM		 18401999-11-29 Mark Salter <msalter@cygnus.com>
1841
1842 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1843 to clear status bits in sdisr register. This is how the hardware works.
1844
1845 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1846 being used by cygmon.
1847
4ce44c66
JM		 18481999-11-11 Andrew Haley <aph@cygnus.com>
1849
1850 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1851 instructions.
1852
cff3e48b
JM		 1853Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1854
1855 * mips.igen (MULT): Correct previous mis-applied patch.
1856
d4f3574e
SS		 1857Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1858
1859 * mips.igen (delayslot32): Handle sequence like
1860 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1861 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1862 (MULT): Actually pass the third register...
1863
18641999-09-03 Mark Salter <msalter@cygnus.com>
1865
1866 * interp.c (sim_open): Added more memory aliases for additional
1867 hardware being touched by cygmon on jmr3904 board.
1868
1869Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1870
1871 * configure: Regenerated to track ../common/aclocal.m4 changes.
1872
a0b3c4fd
JM		 1873Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1874
1875 * interp.c (sim_store_register): Handle case where client - GDB -
1876 specifies that a 4 byte register is 8 bytes in size.
1877 (sim_fetch_register): Ditto.
72f4393d 1878
adf40b2e
JM		 18791999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1880
1881 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1882 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1883 (idt_monitor_base): Base address for IDT monitor traps.
1884 (pmon_monitor_base): Ditto for PMON.
1885 (lsipmon_monitor_base): Ditto for LSI PMON.
1886 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1887 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1888 (sim_firmware_command): New function.
1889 (mips_option_handler): Call it for OPTION_FIRMWARE.
1890 (sim_open): Allocate memory for idt_monitor region. If "--board"
1891 option was given, add no monitor by default. Add BREAK hooks only if
1892 monitors are also there.
72f4393d 1893
43e526b9
JM		 1894Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1895
1896 * interp.c (sim_monitor): Flush output before reading input.
1897
1898Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1899
1900 * tconfig.in (SIM_HANDLES_LMA): Always define.
1901
1902Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1903
1904 From Mark Salter <msalter@cygnus.com>:
1905 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1906 (sim_open): Add setup for BSP board.
1907
9846de1b
JM		 1908Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1909
1910 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1911 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1912 them as unimplemented.
1913
cd0fc7c3
SS		 19141999-05-08 Felix Lee <flee@cygnus.com>
1915
1916 * configure: Regenerated to track ../common/aclocal.m4 changes.
72f4393d 1917
7a292a7a
SS		 19181999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1919
1920 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1921
1922Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1923
1924 * configure.in: Any mips64vr5*-*-* target should have
1925 -DTARGET_ENABLE_FR=1.
1926 (default_endian): Any mips64vr*el-*-* target should default to
1927 LITTLE_ENDIAN.
1928 * configure: Re-generate.
1929
19301999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1931
1932 * mips.igen (ldl): Extend from _16_, not 32.
1933
1934Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1935
1936 * interp.c (sim_store_register): Force registers written to by GDB
1937 into an un-interpreted state.
1938
c906108c
SS		 19391999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1940
1941 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1942 CPU, start periodic background I/O polls.
72f4393d 1943 (tx3904sio_poll): New function: periodic I/O poller.
c906108c
SS		 1944
19451998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1946
1947 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
72f4393d 1948
c906108c
SS		 1949Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1950
1951 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1952 case statement.
1953
19541998-12-29 Frank Ch. Eigler <fche@cygnus.com>
72f4393d
L		 1955
1956 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
c906108c
SS		 1957 (load_word): Call SIM_CORE_SIGNAL hook on error.
1958 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1959 starting. For exception dispatching, pass PC instead of NULL_CIA.
1960 (decode_coproc): Use COP0_BADVADDR to store faulting address.
72f4393d 1961 * sim-main.h (COP0_BADVADDR): Define.
c906108c
SS		 1962 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1963 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
72f4393d 1964 (_sim_cpu): Add exc_* fields to store register value snapshots.
c906108c
SS		 1965 * mips.igen (*): Replace memory-related SignalException* calls
1966 with references to SIM_CORE_SIGNAL hook.
72f4393d 1967
c906108c
SS		 1968 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1969 fix.
1970 * sim-main.c (*): Minor warning cleanups.
72f4393d 1971
c906108c
SS		 19721998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1973
1974 * m16.igen (DADDIU5): Correct type-o.
1975
1976Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1977
1978 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1979 variables.
1980
1981Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1982
1983 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1984 to include path.
1985 (interp.o): Add dependency on itable.h
1986 (oengine.c, gencode): Delete remaining references.
1987 (BUILT_SRC_FROM_GEN): Clean up.
72f4393d 1988
c906108c 19891998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
72f4393d 1990
c906108c
SS		 1991 * vr4run.c: New.
1992 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1993 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1994 tmp-run-hack) : New.
1995 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
72f4393d 1996 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
c906108c
SS		 1997 Drop the "64" qualifier to get the HACK generator working.
1998 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1999 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
2000 qualifier to get the hack generator working.
2001 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
2002 (DSLL): Use do_dsll.
2003 (DSLLV): Use do_dsllv.
2004 (DSRA): Use do_dsra.
2005 (DSRL): Use do_dsrl.
2006 (DSRLV): Use do_dsrlv.
2007 (BC1): Move *vr4100 to get the HACK generator working.
72f4393d 2008 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
c906108c
SS		 2009 get the HACK generator working.
2010 (MACC) Rename to get the HACK generator working.
2011 (DMACC,MACCS,DMACCS): Add the 64.
72f4393d 2012
c906108c
SS		 20131998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
2014
2015 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
2016 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
72f4393d 2017
c906108c
SS		 20181998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
2019
2020 * mips/interp.c (DEBUG): Cleanups.
2021
20221998-12-10 Frank Ch. Eigler <fche@cygnus.com>
2023
2024 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
2025 (tx3904sio_tickle): fflush after a stdout character output.
72f4393d 2026
c906108c
SS		 20271998-12-03 Frank Ch. Eigler <fche@cygnus.com>
2028
2029 * interp.c (sim_close): Uninstall modules.
2030
2031Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
2032
2033 * sim-main.h, interp.c (sim_monitor): Change to global
2034 function.
2035
2036Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2037
2038 * configure.in (vr4100): Only include vr4100 instructions in
2039 simulator.
2040 * configure: Re-generate.
2041 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
2042
2043Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
2044
2045 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
2046 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
2047 true alternative.
2048
2049 * configure.in (sim_default_gen, sim_use_gen): Replace with
2050 sim_gen.
2051 (--enable-sim-igen): Delete config option. Always using IGEN.
2052 * configure: Re-generate.
72f4393d 2053
c906108c
SS		 2054 * Makefile.in (gencode): Kill, kill, kill.
2055 * gencode.c: Ditto.
72f4393d 2056
c906108c
SS		 2057Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
2058
2059 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
2060 bit mips16 igen simulator.
2061 * configure: Re-generate.
2062
2063 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
2064 as part of vr4100 ISA.
2065 * vr.igen: Mark all instructions as 64 bit only.
2066
2067Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2068
2069 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
2070 Pacify GCC.
2071
2072Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
2073
2074 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
2075 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
2076 * configure: Re-generate.
2077
2078 * m16.igen (BREAK): Define breakpoint instruction.
2079 (JALX32): Mark instruction as mips16 and not r3900.
2080 * mips.igen (C.cond.fmt): Fix typo in instruction format.
2081
2082 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
2083
2084Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
2085
2086 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
2087 insn as a debug breakpoint.
2088
2089 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
2090 pending.slot_size.
2091 (PENDING_SCHED): Clean up trace statement.
2092 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
2093 (PENDING_FILL): Delay write by only one cycle.
2094 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
2095
2096 * sim-main.c (pending_tick): Clean up trace statements. Add trace
2097 of pending writes.
2098 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
2099 32 & 64.
2100 (pending_tick): Move incrementing of index to FOR statement.
2101 (pending_tick): Only update PENDING_OUT after a write has occured.
72f4393d 2102
c906108c
SS		 2103 * configure.in: Add explicit mips-lsi-* target. Use gencode to
2104 build simulator.
2105 * configure: Re-generate.
72f4393d 2106
c906108c
SS		 2107 * interp.c (sim_engine_run OLD): Delete explicit call to
2108 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
72f4393d 2109
c906108c
SS		 2110Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
2111
2112 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
2113 interrupt level number to match changed SignalExceptionInterrupt
2114 macro.
2115
2116Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
2117
2118 * interp.c: #include "itable.h" if WITH_IGEN.
2119 (get_insn_name): New function.
2120 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
2121 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
2122
2123Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
2124
2125 * configure: Rebuilt to inhale new common/aclocal.m4.
2126
2127Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
2128
2129 * dv-tx3904sio.c: Include sim-assert.h.
2130
2131Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
2132
2133 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
2134 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
2135 Reorganize target-specific sim-hardware checks.
2136 * configure: rebuilt.
2137 * interp.c (sim_open): For tx39 target boards, set
2138 OPERATING_ENVIRONMENT, add tx3904sio devices.
2139 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
2140 ROM executables. Install dv-sockser into sim-modules list.
72f4393d 2141
c906108c
SS		 2142 * dv-tx3904irc.c: Compiler warning clean-up.
2143 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
2144 frequent hw-trace messages.
2145
2146Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
2147
2148 * vr.igen (MulAcc): Identify as a vr4100 specific function.
2149
2150Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2151
2152 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
2153
2154 * vr.igen: New file.
2155 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
2156 * mips.igen: Define vr4100 model. Include vr.igen.
2157Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
2158
2159 * mips.igen (check_mf_hilo): Correct check.
2160
2161Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2162
2163 * sim-main.h (interrupt_event): Add prototype.
2164
2165 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
2166 register_ptr, register_value.
2167 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
2168
2169 * sim-main.h (tracefh): Make extern.
2170
2171Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
2172
2173 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
72f4393d 2174 Reduce unnecessarily high timer event frequency.
c906108c 2175 * dv-tx3904cpu.c: Ditto for interrupt event.
72f4393d 2176
c906108c
SS		 2177Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
2178
2179 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
2180 to allay warnings.
2181 (interrupt_event): Made non-static.
72f4393d 2182
c906108c
SS		 2183 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
2184 interchange of configuration values for external vs. internal
2185 clock dividers.
72f4393d 2186
c906108c
SS		 2187Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
2188
72f4393d 2189 * mips.igen (BREAK): Moved code to here for
c906108c
SS		 2190 simulator-reserved break instructions.
2191 * gencode.c (build_instruction): Ditto.
2192 * interp.c (signal_exception): Code moved from here. Non-
72f4393d 2193 reserved instructions now use exception vector, rather
c906108c
SS		 2194 than halting sim.
2195 * sim-main.h: Moved magic constants to here.
2196
2197Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
2198
2199 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
2200 register upon non-zero interrupt event level, clear upon zero
2201 event value.
2202 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
2203 by passing zero event value.
2204 (*_io_{read,write}_buffer): Endianness fixes.
2205 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
2206 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
2207
2208 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
2209 serial I/O and timer module at base address 0xFFFF0000.
72f4393d 2210
c906108c
SS		 2211Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
2212
72f4393d 2213 * mips.igen (SWC1) : Correct the handling of ReverseEndian
c906108c
SS		 2214 and BigEndianCPU.
2215
2216Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
2217
2218 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
2219 parts.
2220 * configure: Update.
2221
2222Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
2223
2224 * dv-tx3904tmr.c: New file - implements tx3904 timer.
2225 * dv-tx3904{irc,cpu}.c: Mild reformatting.
2226 * configure.in: Include tx3904tmr in hw_device list.
2227 * configure: Rebuilt.
2228 * interp.c (sim_open): Instantiate three timer instances.
2229 Fix address typo of tx3904irc instance.
2230
2231Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
2232
2233 * interp.c (signal_exception): SystemCall exception now uses
2234 the exception vector.
2235
2236Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
2237
2238 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
2239 to allay warnings.
2240
2241Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2242
2243 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
2244
2245Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
2246
2247 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
2248
2249 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
2250 sim-main.h. Declare a struct hw_descriptor instead of struct
2251 hw_device_descriptor.
2252
2253Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
2254
2255 * mips.igen (do_store_left, do_load_left): Compute nr of left and
2256 right bits and then re-align left hand bytes to correct byte
2257 lanes. Fix incorrect computation in do_store_left when loading
2258 bytes from second word.
2259
2260Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2261
2262 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
2263 * interp.c (sim_open): Only create a device tree when HW is
2264 enabled.
2265
2266 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
2267 * interp.c (signal_exception): Ditto.
2268
2269Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
2270
2271 * gencode.c: Mark BEGEZALL as LIKELY.
2272
2273Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
2274
2275 * sim-main.h (ALU32_END): Sign extend 32 bit results.
2276 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
72f4393d 2277
c906108c
SS		 2278Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
2279
2280 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
2281 modules. Recognize TX39 target with "mips*tx39" pattern.
2282 * configure: Rebuilt.
2283 * sim-main.h (*): Added many macros defining bits in
2284 TX39 control registers.
2285 (SignalInterrupt): Send actual PC instead of NULL.
2286 (SignalNMIReset): New exception type.
2287 * interp.c (board): New variable for future use to identify
2288 a particular board being simulated.
2289 (mips_option_handler,mips_options): Added "--board" option.
2290 (interrupt_event): Send actual PC.
2291 (sim_open): Make memory layout conditional on board setting.
2292 (signal_exception): Initial implementation of hardware interrupt
2293 handling. Accept another break instruction variant for simulator
2294 exit.
2295 (decode_coproc): Implement RFE instruction for TX39.
2296 (mips.igen): Decode RFE instruction as such.
2297 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
2298 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
2299 bbegin to implement memory map.
2300 * dv-tx3904cpu.c: New file.
2301 * dv-tx3904irc.c: New file.
2302
2303Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
2304
2305 * mips.igen (check_mt_hilo): Create a separate r3900 version.
2306
2307Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
2308
2309 * tx.igen (madd,maddu): Replace calls to check_op_hilo
2310 with calls to check_div_hilo.
2311
2312Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
2313
2314 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
2315 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
72f4393d 2316 Add special r3900 version of do_mult_hilo.
c906108c
SS		 2317 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
2318 with calls to check_mult_hilo.
2319 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
2320 with calls to check_div_hilo.
2321
2322Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
2323
2324 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
2325 Document a replacement.
2326
2327Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
2328
2329 * interp.c (sim_monitor): Make mon_printf work.
2330
2331Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
2332
2333 * sim-main.h (INSN_NAME): New arg `cpu'.
2334
2335Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
2336
72f4393d 2337 * configure: Regenerated to track ../common/aclocal.m4 changes.
c906108c
SS		 2338
2339Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
2340
2341 * configure: Regenerated to track ../common/aclocal.m4 changes.
2342 * config.in: Ditto.
2343
2344Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
2345
2346 * acconfig.h: New file.
2347 * configure.in: Reverted change of Apr 24; use sinclude again.
2348
2349Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
2350
2351 * configure: Regenerated to track ../common/aclocal.m4 changes.
2352 * config.in: Ditto.
2353
2354Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
2355
2356 * configure.in: Don't call sinclude.
2357
2358Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
2359
2360 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
2361
2362Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2363
2364 * mips.igen (ERET): Implement.
2365
2366 * interp.c (decode_coproc): Return sign-extended EPC.
2367
2368 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
2369
2370 * interp.c (signal_exception): Do not ignore Trap.
2371 (signal_exception): On TRAP, restart at exception address.
2372 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
2373 (signal_exception): Update.
2374 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
2375 so that TRAP instructions are caught.
2376
2377Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
2378
2379 * sim-main.h (struct hilo_access, struct hilo_history): Define,
2380 contains HI/LO access history.
2381 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
2382 (HIACCESS, LOACCESS): Delete, replace with
2383 (HIHISTORY, LOHISTORY): New macros.
2384 (CHECKHILO): Delete all, moved to mips.igen
72f4393d 2385
c906108c
SS		 2386 * gencode.c (build_instruction): Do not generate checks for
2387 correct HI/LO register usage.
2388
2389 * interp.c (old_engine_run): Delete checks for correct HI/LO
2390 register usage.
2391
2392 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
2393 check_mf_cycles): New functions.
2394 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
2395 do_divu, domultx, do_mult, do_multu): Use.
2396
2397 * tx.igen ("madd", "maddu"): Use.
72f4393d 2398
c906108c
SS		 2399Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
2400
2401 * mips.igen (DSRAV): Use function do_dsrav.
2402 (SRAV): Use new function do_srav.
2403
2404 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
2405 (B): Sign extend 11 bit immediate.
2406 (EXT-B*): Shift 16 bit immediate left by 1.
2407 (ADDIU*): Don't sign extend immediate value.
2408
2409Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2410
2411 * m16run.c (sim_engine_run): Restore CIA after handling an event.
2412
2413 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
2414 functions.
2415
2416 * mips.igen (delayslot32, nullify_next_insn): New functions.
2417 (m16.igen): Always include.
2418 (do_*): Add more tracing.
2419
2420 * m16.igen (delayslot16): Add NIA argument, could be called by a
2421 32 bit MIPS16 instruction.
72f4393d 2422
c906108c
SS		 2423 * interp.c (ifetch16): Move function from here.
2424 * sim-main.c (ifetch16): To here.
72f4393d 2425
c906108c
SS		 2426 * sim-main.c (ifetch16, ifetch32): Update to match current
2427 implementations of LH, LW.
2428 (signal_exception): Don't print out incorrect hex value of illegal
2429 instruction.
2430
2431Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2432
2433 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
2434 instruction.
2435
2436 * m16.igen: Implement MIPS16 instructions.
72f4393d 2437
c906108c
SS		 2438 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
2439 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
2440 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
2441 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
2442 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
2443 bodies of corresponding code from 32 bit insn to these. Also used
2444 by MIPS16 versions of functions.
72f4393d 2445
c906108c
SS		 2446 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
2447 (IMEM16): Drop NR argument from macro.
2448
2449Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2450
2451 * Makefile.in (SIM_OBJS): Add sim-main.o.
2452
2453 * sim-main.h (address_translation, load_memory, store_memory,
2454 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
2455 as INLINE_SIM_MAIN.
2456 (pr_addr, pr_uword64): Declare.
2457 (sim-main.c): Include when H_REVEALS_MODULE_P.
72f4393d 2458
c906108c
SS		 2459 * interp.c (address_translation, load_memory, store_memory,
2460 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
2461 from here.
2462 * sim-main.c: To here. Fix compilation problems.
72f4393d 2463
c906108c
SS		 2464 * configure.in: Enable inlining.
2465 * configure: Re-config.
2466
2467Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2468
2469 * configure: Regenerated to track ../common/aclocal.m4 changes.
2470
2471Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2472
2473 * mips.igen: Include tx.igen.
2474 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
2475 * tx.igen: New file, contains MADD and MADDU.
2476
2477 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
2478 the hardwired constant `7'.
2479 (store_memory): Ditto.
2480 (LOADDRMASK): Move definition to sim-main.h.
2481
2482 mips.igen (MTC0): Enable for r3900.
2483 (ADDU): Add trace.
2484
2485 mips.igen (do_load_byte): Delete.
2486 (do_load, do_store, do_load_left, do_load_write, do_store_left,
2487 do_store_right): New functions.
2488 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
2489
2490 configure.in: Let the tx39 use igen again.
2491 configure: Update.
72f4393d 2492
c906108c
SS		 2493Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2494
2495 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
2496 not an address sized quantity. Return zero for cache sizes.
2497
2498Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
2499
2500 * mips.igen (r3900): r3900 does not support 64 bit integer
2501 operations.
2502
2503Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
2504
2505 * configure.in (mipstx39*-*-*): Use gencode simulator rather
2506 than igen one.
2507 * configure : Rebuild.
72f4393d 2508
c906108c
SS		 2509Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
2510
2511 * configure: Regenerated to track ../common/aclocal.m4 changes.
2512
2513Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2514
2515 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
2516
2517Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
2518
2519 * configure: Regenerated to track ../common/aclocal.m4 changes.
2520 * config.in: Regenerated to track ../common/aclocal.m4 changes.
2521
2522Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2523
2524 * configure: Regenerated to track ../common/aclocal.m4 changes.
2525
2526Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
2527
2528 * interp.c (Max, Min): Comment out functions. Not yet used.
2529
2530Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
2531
2532 * configure: Regenerated to track ../common/aclocal.m4 changes.
2533
2534Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
2535
2536 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
2537 configurable settings for stand-alone simulator.
72f4393d 2538
c906108c 2539 * configure.in: Added X11 search, just in case.
72f4393d 2540
c906108c
SS		 2541 * configure: Regenerated.
2542
2543Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
2544
2545 * interp.c (sim_write, sim_read, load_memory, store_memory):
2546 Replace sim_core_*_map with read_map, write_map, exec_map resp.
2547
2548Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
2549
2550 * sim-main.h (GETFCC): Return an unsigned value.
2551
2552Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2553
2554 * mips.igen (DIV): Fix check for -1 / MIN_INT.
2555 (DADD): Result destination is RD not RT.
2556
2557Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2558
2559 * sim-main.h (HIACCESS, LOACCESS): Always define.
2560
2561 * mdmx.igen (Maxi, Mini): Rename Max, Min.
2562
2563 * interp.c (sim_info): Delete.
2564
2565Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
2566
2567 * interp.c (DECLARE_OPTION_HANDLER): Use it.
2568 (mips_option_handler): New argument `cpu'.
2569 (sim_open): Update call to sim_add_option_table.
2570
2571Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
2572
2573 * mips.igen (CxC1): Add tracing.
2574
2575Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
2576
2577 * sim-main.h (Max, Min): Declare.
2578
2579 * interp.c (Max, Min): New functions.
2580
2581 * mips.igen (BC1): Add tracing.
72f4393d 2582
c906108c 2583Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
72f4393d 2584
c906108c 2585 * interp.c Added memory map for stack in vr4100
72f4393d 2586
c906108c
SS		 2587Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
2588
2589 * interp.c (load_memory): Add missing "break"'s.
2590
2591Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2592
2593 * interp.c (sim_store_register, sim_fetch_register): Pass in
2594 length parameter. Return -1.
2595
2596Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
2597
2598 * interp.c: Added hardware init hook, fixed warnings.
2599
2600Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2601
2602 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
2603
2604Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
2605
2606 * interp.c (ifetch16): New function.
2607
2608 * sim-main.h (IMEM32): Rename IMEM.
2609 (IMEM16_IMMED): Define.
2610 (IMEM16): Define.
2611 (DELAY_SLOT): Update.
72f4393d 2612
c906108c 2613 * m16run.c (sim_engine_run): New file.
72f4393d 2614
c906108c
SS		 2615 * m16.igen: All instructions except LB.
2616 (LB): Call do_load_byte.
2617 * mips.igen (do_load_byte): New function.
2618 (LB): Call do_load_byte.
2619
2620 * mips.igen: Move spec for insn bit size and high bit from here.
2621 * Makefile.in (tmp-igen, tmp-m16): To here.
2622
2623 * m16.dc: New file, decode mips16 instructions.
2624
2625 * Makefile.in (SIM_NO_ALL): Define.
2626 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
2627
2628Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
2629
2630 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
2631 point unit to 32 bit registers.
2632 * configure: Re-generate.
2633
2634Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2635
2636 * configure.in (sim_use_gen): Make IGEN the default simulator
2637 generator for generic 32 and 64 bit mips targets.
2638 * configure: Re-generate.
2639
2640Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2641
2642 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
2643 bitsize.
2644
2645 * interp.c (sim_fetch_register, sim_store_register): Read/write
2646 FGR from correct location.
2647 (sim_open): Set size of FGR's according to
2648 WITH_TARGET_FLOATING_POINT_BITSIZE.
72f4393d 2649
c906108c
SS		 2650 * sim-main.h (FGR): Store floating point registers in a separate
2651 array.
2652
2653Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
2654
2655 * configure: Regenerated to track ../common/aclocal.m4 changes.
2656
2657Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2658
2659 * interp.c (ColdReset): Call PENDING_INVALIDATE.
2660
2661 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
2662
2663 * interp.c (pending_tick): New function. Deliver pending writes.
2664
2665 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2666 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2667 it can handle mixed sized quantites and single bits.
72f4393d 2668
c906108c
SS		 2669Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2670
2671 * interp.c (oengine.h): Do not include when building with IGEN.
2672 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2673 (sim_info): Ditto for PROCESSOR_64BIT.
2674 (sim_monitor): Replace ut_reg with unsigned_word.
2675 (*): Ditto for t_reg.
2676 (LOADDRMASK): Define.
2677 (sim_open): Remove defunct check that host FP is IEEE compliant,
2678 using software to emulate floating point.
2679 (value_fpr, ...): Always compile, was conditional on HASFPU.
2680
2681Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2682
2683 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2684 size.
2685
2686 * interp.c (SD, CPU): Define.
2687 (mips_option_handler): Set flags in each CPU.
2688 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2689 (sim_close): Do not clear STATE, deleted anyway.
2690 (sim_write, sim_read): Assume CPU zero's vm should be used for
2691 data transfers.
2692 (sim_create_inferior): Set the PC for all processors.
2693 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2694 argument.
2695 (mips16_entry): Pass correct nr of args to store_word, load_word.
2696 (ColdReset): Cold reset all cpu's.
2697 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2698 (sim_monitor, load_memory, store_memory, signal_exception): Use
2699 `CPU' instead of STATE_CPU.
2700
2701
2702 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2703 SD or CPU_.
72f4393d 2704
c906108c
SS		 2705 * sim-main.h (signal_exception): Add sim_cpu arg.
2706 (SignalException*): Pass both SD and CPU to signal_exception.
2707 * interp.c (signal_exception): Update.
72f4393d 2708
c906108c
SS		 2709 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2710 Ditto
2711 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2712 address_translation): Ditto
2713 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
72f4393d 2714
c906108c
SS		 2715Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2716
2717 * configure: Regenerated to track ../common/aclocal.m4 changes.
2718
2719Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2720
2721 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2722
72f4393d 2723 * mips.igen (model): Map processor names onto BFD name.
c906108c
SS		 2724
2725 * sim-main.h (CPU_CIA): Delete.
2726 (SET_CIA, GET_CIA): Define
2727
2728Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2729
2730 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2731 regiser.
2732
2733 * configure.in (default_endian): Configure a big-endian simulator
2734 by default.
2735 * configure: Re-generate.
72f4393d 2736
c906108c
SS		 2737Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2738
2739 * configure: Regenerated to track ../common/aclocal.m4 changes.
2740
2741Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2742
2743 * interp.c (sim_monitor): Handle Densan monitor outbyte
2744 and inbyte functions.
2745
27461997-12-29 Felix Lee <flee@cygnus.com>
2747
2748 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2749
2750Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2751
2752 * Makefile.in (tmp-igen): Arrange for $zero to always be
2753 reset to zero after every instruction.
2754
2755Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2756
2757 * configure: Regenerated to track ../common/aclocal.m4 changes.
2758 * config.in: Ditto.
2759
2760Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2761
2762 * mips.igen (MSUB): Fix to work like MADD.
2763 * gencode.c (MSUB): Similarly.
2764
2765Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2766
2767 * configure: Regenerated to track ../common/aclocal.m4 changes.
2768
2769Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2770
2771 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2772
2773Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2774
2775 * sim-main.h (sim-fpu.h): Include.
2776
2777 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2778 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2779 using host independant sim_fpu module.
2780
2781Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2782
2783 * interp.c (signal_exception): Report internal errors with SIGABRT
2784 not SIGQUIT.
2785
2786 * sim-main.h (C0_CONFIG): New register.
2787 (signal.h): No longer include.
2788
2789 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2790
2791Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2792
2793 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2794
2795Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2796
2797 * mips.igen: Tag vr5000 instructions.
2798 (ANDI): Was missing mipsIV model, fix assembler syntax.
2799 (do_c_cond_fmt): New function.
2800 (C.cond.fmt): Handle mips I-III which do not support CC field
2801 separatly.
2802 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2803 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2804 in IV3.2 spec.
2805 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2806 vr5000 which saves LO in a GPR separatly.
72f4393d 2807
c906108c
SS		 2808 * configure.in (enable-sim-igen): For vr5000, select vr5000
2809 specific instructions.
2810 * configure: Re-generate.
72f4393d 2811
c906108c
SS		 2812Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2813
2814 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2815
2816 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2817 fmt_uninterpreted_64 bit cases to switch. Convert to
2818 fmt_formatted,
2819
2820 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2821
2822 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2823 as specified in IV3.2 spec.
2824 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2825
2826Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2827
2828 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2829 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2830 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2831 PENDING_FILL versions of instructions. Simplify.
2832 (X): New function.
2833 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2834 instructions.
2835 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2836 a signed value.
2837 (MTHI, MFHI): Disable code checking HI-LO.
72f4393d 2838
c906108c
SS		 2839 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2840 global.
2841 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2842
2843Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2844
2845 * gencode.c (build_mips16_operands): Replace IPC with cia.
2846
2847 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2848 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2849 IPC to `cia'.
2850 (UndefinedResult): Replace function with macro/function
2851 combination.
2852 (sim_engine_run): Don't save PC in IPC.
2853
2854 * sim-main.h (IPC): Delete.
2855
2856
2857 * interp.c (signal_exception, store_word, load_word,
2858 address_translation, load_memory, store_memory, cache_op,
2859 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2860 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2861 current instruction address - cia - argument.
2862 (sim_read, sim_write): Call address_translation directly.
2863 (sim_engine_run): Rename variable vaddr to cia.
2864 (signal_exception): Pass cia to sim_monitor
72f4393d 2865
c906108c
SS		 2866 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2867 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2868 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2869
2870 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2871 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2872 SIM_ASSERT.
72f4393d 2873
c906108c
SS		 2874 * interp.c (signal_exception): Pass restart address to
2875 sim_engine_restart.
2876
2877 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2878 idecode.o): Add dependency.
2879
2880 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2881 Delete definitions
2882 (DELAY_SLOT): Update NIA not PC with branch address.
2883 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2884
2885 * mips.igen: Use CIA not PC in branch calculations.
2886 (illegal): Call SignalException.
2887 (BEQ, ADDIU): Fix assembler.
2888
2889Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2890
2891 * m16.igen (JALX): Was missing.
2892
2893 * configure.in (enable-sim-igen): New configuration option.
2894 * configure: Re-generate.
72f4393d 2895
c906108c
SS		 2896 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2897
2898 * interp.c (load_memory, store_memory): Delete parameter RAW.
2899 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2900 bypassing {load,store}_memory.
2901
2902 * sim-main.h (ByteSwapMem): Delete definition.
2903
2904 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2905
2906 * interp.c (sim_do_command, sim_commands): Delete mips specific
2907 commands. Handled by module sim-options.
72f4393d 2908
c906108c
SS		 2909 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2910 (WITH_MODULO_MEMORY): Define.
2911
2912 * interp.c (sim_info): Delete code printing memory size.
2913
2914 * interp.c (mips_size): Nee sim_size, delete function.
2915 (power2): Delete.
2916 (monitor, monitor_base, monitor_size): Delete global variables.
2917 (sim_open, sim_close): Delete code creating monitor and other
2918 memory regions. Use sim-memopts module, via sim_do_commandf, to
2919 manage memory regions.
2920 (load_memory, store_memory): Use sim-core for memory model.
72f4393d 2921
c906108c
SS		 2922 * interp.c (address_translation): Delete all memory map code
2923 except line forcing 32 bit addresses.
2924
2925Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2926
2927 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2928 trace options.
2929
2930 * interp.c (logfh, logfile): Delete globals.
2931 (sim_open, sim_close): Delete code opening & closing log file.
2932 (mips_option_handler): Delete -l and -n options.
2933 (OPTION mips_options): Ditto.
2934
2935 * interp.c (OPTION mips_options): Rename option trace to dinero.
2936 (mips_option_handler): Update.
2937
2938Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2939
2940 * interp.c (fetch_str): New function.
2941 (sim_monitor): Rewrite using sim_read & sim_write.
2942 (sim_open): Check magic number.
2943 (sim_open): Write monitor vectors into memory using sim_write.
2944 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2945 (sim_read, sim_write): Simplify - transfer data one byte at a
2946 time.
2947 (load_memory, store_memory): Clarify meaning of parameter RAW.
2948
2949 * sim-main.h (isHOST): Defete definition.
2950 (isTARGET): Mark as depreciated.
2951 (address_translation): Delete parameter HOST.
2952
2953 * interp.c (address_translation): Delete parameter HOST.
2954
2955Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2956
72f4393d 2957 * mips.igen:
c906108c
SS		 2958
2959 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2960 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2961
2962Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2963
2964 * mips.igen: Add model filter field to records.
2965
2966Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2967
2968 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
72f4393d 2969
c906108c
SS		 2970 interp.c (sim_engine_run): Do not compile function sim_engine_run
2971 when WITH_IGEN == 1.
2972
2973 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2974 target architecture.
2975
2976 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2977 igen. Replace with configuration variables sim_igen_flags /
2978 sim_m16_flags.
2979
2980 * m16.igen: New file. Copy mips16 insns here.
2981 * mips.igen: From here.
2982
2983Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2984
2985 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2986 to top.
2987 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2988
2989Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2990
2991 * gencode.c (build_instruction): Follow sim_write's lead in using
2992 BigEndianMem instead of !ByteSwapMem.
2993
2994Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2995
2996 * configure.in (sim_gen): Dependent on target, select type of
2997 generator. Always select old style generator.
2998
2999 configure: Re-generate.
3000
3001 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
3002 targets.
3003 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
3004 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
3005 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
3006 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
3007 SIM_@sim_gen@_*, set by autoconf.
72f4393d 3008
c906108c
SS		 3009Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
3010
3011 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
3012
3013 * interp.c (ColdReset): Remove #ifdef HASFPU, check
3014 CURRENT_FLOATING_POINT instead.
3015
3016 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
3017 (address_translation): Raise exception InstructionFetch when
3018 translation fails and isINSTRUCTION.
72f4393d 3019
c906108c
SS		 3020 * interp.c (sim_open, sim_write, sim_monitor, store_word,
3021 sim_engine_run): Change type of of vaddr and paddr to
3022 address_word.
3023 (address_translation, prefetch, load_memory, store_memory,
3024 cache_op): Change type of vAddr and pAddr to address_word.
3025
3026 * gencode.c (build_instruction): Change type of vaddr and paddr to
3027 address_word.
3028
3029Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
3030
3031 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
3032 macro to obtain result of ALU op.
3033
3034Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
3035
3036 * interp.c (sim_info): Call profile_print.
3037
3038Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3039
3040 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
3041
3042 * sim-main.h (WITH_PROFILE): Do not define, defined in
3043 common/sim-config.h. Use sim-profile module.
3044 (simPROFILE): Delete defintion.
3045
3046 * interp.c (PROFILE): Delete definition.
3047 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
3048 (sim_close): Delete code writing profile histogram.
3049 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
3050 Delete.
3051 (sim_engine_run): Delete code profiling the PC.
3052
3053Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3054
3055 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
3056
3057 * interp.c (sim_monitor): Make register pointers of type
3058 unsigned_word*.
3059
3060 * sim-main.h: Make registers of type unsigned_word not
3061 signed_word.
3062
3063Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3064
3065 * interp.c (sync_operation): Rename from SyncOperation, make
3066 global, add SD argument.
3067 (prefetch): Rename from Prefetch, make global, add SD argument.
3068 (decode_coproc): Make global.
3069
3070 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
3071
3072 * gencode.c (build_instruction): Generate DecodeCoproc not
3073 decode_coproc calls.
3074
3075 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
3076 (SizeFGR): Move to sim-main.h
3077 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
3078 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
3079 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
3080 sim-main.h.
3081 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
3082 FP_RM_TOMINF, GETRM): Move to sim-main.h.
3083 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
3084 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
3085 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
3086 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
72f4393d 3087
c906108c
SS		 3088 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
3089 exception.
3090 (sim-alu.h): Include.
3091 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
3092 (sim_cia): Typedef to instruction_address.
72f4393d 3093
c906108c
SS		 3094Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
3095
3096 * Makefile.in (interp.o): Rename generated file engine.c to
3097 oengine.c.
72f4393d 3098
c906108c 3099 * interp.c: Update.
72f4393d 3100
c906108c
SS		 3101Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
3102
3103 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
72f4393d 3104
c906108c
SS		 3105Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3106
3107 * gencode.c (build_instruction): For "FPSQRT", output correct
3108 number of arguments to Recip.
72f4393d 3109
c906108c
SS		 3110Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
3111
3112 * Makefile.in (interp.o): Depends on sim-main.h
3113
3114 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
3115
3116 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
3117 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
3118 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
3119 STATE, DSSTATE): Define
3120 (GPR, FGRIDX, ..): Define.
3121
3122 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
3123 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
3124 (GPR, FGRIDX, ...): Delete macros.
72f4393d 3125
c906108c 3126 * interp.c: Update names to match defines from sim-main.h
72f4393d 3127
c906108c
SS		 3128Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
3129
3130 * interp.c (sim_monitor): Add SD argument.
3131 (sim_warning): Delete. Replace calls with calls to
3132 sim_io_eprintf.
3133 (sim_error): Delete. Replace calls with sim_io_error.
3134 (open_trace, writeout32, writeout16, getnum): Add SD argument.
3135 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
3136 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
3137 argument.
3138 (mips_size): Rename from sim_size. Add SD argument.
3139
3140 * interp.c (simulator): Delete global variable.
3141 (callback): Delete global variable.
3142 (mips_option_handler, sim_open, sim_write, sim_read,
3143 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
3144 sim_size,sim_monitor): Use sim_io_* not callback->*.
3145 (sim_open): ZALLOC simulator struct.
3146 (PROFILE): Do not define.
3147
3148Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3149
3150 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
3151 support.h with corresponding code.
3152
3153 * sim-main.h (word64, uword64), support.h: Move definition to
3154 sim-main.h.
3155 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
3156
3157 * support.h: Delete
3158 * Makefile.in: Update dependencies
3159 * interp.c: Do not include.
72f4393d 3160
c906108c
SS		 3161Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3162
3163 * interp.c (address_translation, load_memory, store_memory,
3164 cache_op): Rename to from AddressTranslation et.al., make global,
3165 add SD argument
72f4393d 3166
c906108c
SS		 3167 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
3168 CacheOp): Define.
72f4393d 3169
c906108c
SS		 3170 * interp.c (SignalException): Rename to signal_exception, make
3171 global.
3172
3173 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
72f4393d 3174
c906108c
SS		 3175 * sim-main.h (SignalException, SignalExceptionInterrupt,
3176 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
3177 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
3178 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
3179 Define.
72f4393d 3180
c906108c 3181 * interp.c, support.h: Use.
72f4393d 3182
c906108c
SS		 3183Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3184
3185 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
3186 to value_fpr / store_fpr. Add SD argument.
3187 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
3188 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
3189
3190 * sim-main.h (ValueFPR, StoreFPR): Define.
72f4393d 3191
c906108c
SS		 3192Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
3193
3194 * interp.c (sim_engine_run): Check consistency between configure
3195 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
3196 and HASFPU.
3197
3198 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
72f4393d 3199 (mips_fpu): Configure WITH_FLOATING_POINT.
c906108c
SS		 3200 (mips_endian): Configure WITH_TARGET_ENDIAN.
3201 * configure: Update.
3202
3203Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3204
3205 * configure: Regenerated to track ../common/aclocal.m4 changes.
3206
3207Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
3208
3209 * configure: Regenerated.
3210
3211Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
3212
3213 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
3214
3215Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3216
3217 * gencode.c (print_igen_insn_models): Assume certain architectures
3218 include all mips* instructions.
3219 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
3220 instruction.
3221
3222 * Makefile.in (tmp.igen): Add target. Generate igen input from
3223 gencode file.
3224
3225 * gencode.c (FEATURE_IGEN): Define.
3226 (main): Add --igen option. Generate output in igen format.
3227 (process_instructions): Format output according to igen option.
3228 (print_igen_insn_format): New function.
3229 (print_igen_insn_models): New function.
3230 (process_instructions): Only issue warnings and ignore
3231 instructions when no FEATURE_IGEN.
3232
3233Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3234
3235 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
3236 MIPS targets.
3237
3238Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3239
3240 * configure: Regenerated to track ../common/aclocal.m4 changes.
3241
3242Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
3243
3244 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
3245 SIM_RESERVED_BITS): Delete, moved to common.
3246 (SIM_EXTRA_CFLAGS): Update.
72f4393d 3247
c906108c
SS		 3248Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3249
3250 * configure.in: Configure non-strict memory alignment.
3251 * configure: Regenerated to track ../common/aclocal.m4 changes.
3252
3253Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
3254
3255 * configure: Regenerated to track ../common/aclocal.m4 changes.
3256
3257Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
3258
3259 * gencode.c (SDBBP,DERET): Added (3900) insns.
3260 (RFE): Turn on for 3900.
3261 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
3262 (dsstate): Made global.
3263 (SUBTARGET_R3900): Added.
3264 (CANCELDELAYSLOT): New.
3265 (SignalException): Ignore SystemCall rather than ignore and
3266 terminate. Add DebugBreakPoint handling.
3267 (decode_coproc): New insns RFE, DERET; and new registers Debug
3268 and DEPC protected by SUBTARGET_R3900.
3269 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
3270 bits explicitly.
3271 * Makefile.in,configure.in: Add mips subtarget option.
72f4393d 3272 * configure: Update.
c906108c
SS		 3273
3274Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
3275
3276 * gencode.c: Add r3900 (tx39).
72f4393d 3277
c906108c
SS		 3278
3279Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
3280
3281 * gencode.c (build_instruction): Don't need to subtract 4 for
3282 JALR, just 2.
3283
3284Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
3285
3286 * interp.c: Correct some HASFPU problems.
3287
3288Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
3289
3290 * configure: Regenerated to track ../common/aclocal.m4 changes.
3291
3292Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3293
3294 * interp.c (mips_options): Fix samples option short form, should
3295 be `x'.
3296
3297Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
3298
3299 * interp.c (sim_info): Enable info code. Was just returning.
3300
3301Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3302
3303 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
3304 MFC0.
3305
3306Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
3307
3308 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
3309 constants.
3310 (build_instruction): Ditto for LL.
3311
3312Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
3313
3314 * configure: Regenerated to track ../common/aclocal.m4 changes.
3315
3316Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3317
3318 * configure: Regenerated to track ../common/aclocal.m4 changes.
3319 * config.in: Ditto.
3320
3321Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
3322
3323 * interp.c (sim_open): Add call to sim_analyze_program, update
3324 call to sim_config.
3325
3326Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
3327
3328 * interp.c (sim_kill): Delete.
3329 (sim_create_inferior): Add ABFD argument. Set PC from same.
3330 (sim_load): Move code initializing trap handlers from here.
3331 (sim_open): To here.
3332 (sim_load): Delete, use sim-hload.c.
3333
3334 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
3335
3336Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3337
3338 * configure: Regenerated to track ../common/aclocal.m4 changes.
3339 * config.in: Ditto.
3340
3341Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3342
3343 * interp.c (sim_open): Add ABFD argument.
3344 (sim_load): Move call to sim_config from here.
3345 (sim_open): To here. Check return status.
3346
3347Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
72f4393d 3348
c906108c
SS		 3349 * gencode.c (build_instruction): Two arg MADD should
3350 not assign result to $0.
72f4393d 3351
c906108c
SS		 3352Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
3353
3354 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
3355 * sim/mips/configure.in: Regenerate.
3356
3357Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
3358
3359 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
3360 signed8, unsigned8 et.al. types.
3361
3362 * interp.c (SUB_REG_FETCH): Handle both little and big endian
3363 hosts when selecting subreg.
3364
3365Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
3366
3367 * interp.c (sim_engine_run): Reset the ZERO register to zero
3368 regardless of FEATURE_WARN_ZERO.
3369 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
3370
3371Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
3372
3373 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
3374 (SignalException): For BreakPoints ignore any mode bits and just
3375 save the PC.
3376 (SignalException): Always set the CAUSE register.
3377
3378Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
3379
3380 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
3381 exception has been taken.
3382
3383 * interp.c: Implement the ERET and mt/f sr instructions.
3384
3385Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
3386
3387 * interp.c (SignalException): Don't bother restarting an
3388 interrupt.
3389
3390Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3391
3392 * interp.c (SignalException): Really take an interrupt.
3393 (interrupt_event): Only deliver interrupts when enabled.
3394
3395Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
3396
3397 * interp.c (sim_info): Only print info when verbose.
3398 (sim_info) Use sim_io_printf for output.
72f4393d 3399
c906108c
SS		 3400Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3401
3402 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
3403 mips architectures.
3404
3405Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3406
3407 * interp.c (sim_do_command): Check for common commands if a
3408 simulator specific command fails.
3409
3410Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
3411
3412 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
3413 and simBE when DEBUG is defined.
3414
3415Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
3416
3417 * interp.c (interrupt_event): New function. Pass exception event
3418 onto exception handler.
3419
3420 * configure.in: Check for stdlib.h.
3421 * configure: Regenerate.
3422
3423 * gencode.c (build_instruction): Add UNUSED attribute to tempS
3424 variable declaration.
3425 (build_instruction): Initialize memval1.
3426 (build_instruction): Add UNUSED attribute to byte, bigend,
3427 reverse.
3428 (build_operands): Ditto.
3429
3430 * interp.c: Fix GCC warnings.
3431 (sim_get_quit_code): Delete.
3432
3433 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
3434 * Makefile.in: Ditto.
3435 * configure: Re-generate.
72f4393d 3436
c906108c
SS		 3437 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
3438
3439Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
3440
3441 * interp.c (mips_option_handler): New function parse argumes using
3442 sim-options.
3443 (myname): Replace with STATE_MY_NAME.
3444 (sim_open): Delete check for host endianness - performed by
3445 sim_config.
3446 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
3447 (sim_open): Move much of the initialization from here.
3448 (sim_load): To here. After the image has been loaded and
3449 endianness set.
3450 (sim_open): Move ColdReset from here.
3451 (sim_create_inferior): To here.
3452 (sim_open): Make FP check less dependant on host endianness.
3453
3454 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
3455 run.
3456 * interp.c (sim_set_callbacks): Delete.
3457
3458 * interp.c (membank, membank_base, membank_size): Replace with
3459 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
3460 (sim_open): Remove call to callback->init. gdb/run do this.
3461
3462 * interp.c: Update
3463
3464 * sim-main.h (SIM_HAVE_FLATMEM): Define.
3465
3466 * interp.c (big_endian_p): Delete, replaced by
3467 current_target_byte_order.
3468
3469Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3470
3471 * interp.c (host_read_long, host_read_word, host_swap_word,
3472 host_swap_long): Delete. Using common sim-endian.
3473 (sim_fetch_register, sim_store_register): Use H2T.
3474 (pipeline_ticks): Delete. Handled by sim-events.
3475 (sim_info): Update.
3476 (sim_engine_run): Update.
3477
3478Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
3479
3480 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
3481 reason from here.
3482 (SignalException): To here. Signal using sim_engine_halt.
3483 (sim_stop_reason): Delete, moved to common.
72f4393d 3484
c906108c
SS		 3485Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
3486
3487 * interp.c (sim_open): Add callback argument.
3488 (sim_set_callbacks): Delete SIM_DESC argument.
3489 (sim_size): Ditto.
3490
3491Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3492
3493 * Makefile.in (SIM_OBJS): Add common modules.
3494
3495 * interp.c (sim_set_callbacks): Also set SD callback.
3496 (set_endianness, xfer_*, swap_*): Delete.
3497 (host_read_word, host_read_long, host_swap_word, host_swap_long):
3498 Change to functions using sim-endian macros.
3499 (control_c, sim_stop): Delete, use common version.
3500 (simulate): Convert into.
3501 (sim_engine_run): This function.
3502 (sim_resume): Delete.
72f4393d 3503
c906108c
SS		 3504 * interp.c (simulation): New variable - the simulator object.
3505 (sim_kind): Delete global - merged into simulation.
3506 (sim_load): Cleanup. Move PC assignment from here.
3507 (sim_create_inferior): To here.
3508
3509 * sim-main.h: New file.
3510 * interp.c (sim-main.h): Include.
72f4393d 3511
c906108c
SS		 3512Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
3513
3514 * configure: Regenerated to track ../common/aclocal.m4 changes.
3515
3516Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
3517
3518 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
3519
3520Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
3521
72f4393d
L		 3522 * gencode.c (build_instruction): DIV instructions: check
3523 for division by zero and integer overflow before using
c906108c
SS		 3524 host's division operation.
3525
3526Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
3527
3528 * Makefile.in (SIM_OBJS): Add sim-load.o.
3529 * interp.c: #include bfd.h.
3530 (target_byte_order): Delete.
3531 (sim_kind, myname, big_endian_p): New static locals.
3532 (sim_open): Set sim_kind, myname. Move call to set_endianness to
3533 after argument parsing. Recognize -E arg, set endianness accordingly.
3534 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
3535 load file into simulator. Set PC from bfd.
3536 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
3537 (set_endianness): Use big_endian_p instead of target_byte_order.
3538
3539Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
3540
3541 * interp.c (sim_size): Delete prototype - conflicts with
3542 definition in remote-sim.h. Correct definition.
3543
3544Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3545
3546 * configure: Regenerated to track ../common/aclocal.m4 changes.
3547 * config.in: Ditto.
3548
3549Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
3550
3551 * interp.c (sim_open): New arg `kind'.
3552
3553 * configure: Regenerated to track ../common/aclocal.m4 changes.
3554
3555Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3556
3557 * configure: Regenerated to track ../common/aclocal.m4 changes.
3558
3559Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
3560
3561 * interp.c (sim_open): Set optind to 0 before calling getopt.
3562
3563Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3564
3565 * configure: Regenerated to track ../common/aclocal.m4 changes.
3566
3567Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
3568
3569 * interp.c : Replace uses of pr_addr with pr_uword64
3570 where the bit length is always 64 independent of SIM_ADDR.
3571 (pr_uword64) : added.
3572
3573Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3574
3575 * configure: Re-generate.
3576
3577Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
3578
3579 * configure: Regenerate to track ../common/aclocal.m4 changes.
3580
3581Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
3582
3583 * interp.c (sim_open): New SIM_DESC result. Argument is now
3584 in argv form.
3585 (other sim_*): New SIM_DESC argument.
3586
3587Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
3588
3589 * interp.c: Fix printing of addresses for non-64-bit targets.
3590 (pr_addr): Add function to print address based on size.
3591
3592Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
3593
3594 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
3595
3596Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
3597
3598 * gencode.c (build_mips16_operands): Correct computation of base
3599 address for extended PC relative instruction.
3600
3601Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
3602
3603 * interp.c (mips16_entry): Add support for floating point cases.
3604 (SignalException): Pass floating point cases to mips16_entry.
3605 (ValueFPR): Don't restrict fmt_single and fmt_word to even
3606 registers.
3607 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
3608 or fmt_word.
3609 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
3610 and then set the state to fmt_uninterpreted.
3611 (COP_SW): Temporarily set the state to fmt_word while calling
3612 ValueFPR.
3613
3614Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
3615
3616 * gencode.c (build_instruction): The high order may be set in the
3617 comparison flags at any ISA level, not just ISA 4.
3618
3619Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
3620
3621 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
3622 COMMON_{PRE,POST}_CONFIG_FRAG instead.
3623 * configure.in: sinclude ../common/aclocal.m4.
3624 * configure: Regenerated.
3625
3626Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
3627
3628 * configure: Rebuild after change to aclocal.m4.
3629
3630Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
3631
3632 * configure configure.in Makefile.in: Update to new configure
3633 scheme which is more compatible with WinGDB builds.
3634 * configure.in: Improve comment on how to run autoconf.
3635 * configure: Re-run autoconf to get new ../common/aclocal.m4.
3636 * Makefile.in: Use autoconf substitution to install common
3637 makefile fragment.
3638
3639Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
3640
3641 * gencode.c (build_instruction): Use BigEndianCPU instead of
3642 ByteSwapMem.
3643
3644Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
3645
3646 * interp.c (sim_monitor): Make output to stdout visible in
3647 wingdb's I/O log window.
3648
3649Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
3650
3651 * support.h: Undo previous change to SIGTRAP
3652 and SIGQUIT values.
3653
3654Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
3655
3656 * interp.c (store_word, load_word): New static functions.
3657 (mips16_entry): New static function.
3658 (SignalException): Look for mips16 entry and exit instructions.
3659 (simulate): Use the correct index when setting fpr_state after
3660 doing a pending move.
3661
3662Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
3663
3664 * interp.c: Fix byte-swapping code throughout to work on
3665 both little- and big-endian hosts.
3666
3667Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
3668
3669 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3670 with gdb/config/i386/xm-windows.h.
3671
3672Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
3673
3674 * gencode.c (build_instruction): Work around MSVC++ code gen bug
3675 that messes up arithmetic shifts.
3676
3677Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
3678
3679 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
3680 SIGTRAP and SIGQUIT for _WIN32.
3681
3682Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3683
3684 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3685 force a 64 bit multiplication.
3686 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3687 destination register is 0, since that is the default mips16 nop
3688 instruction.
3689
3690Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3691
3692 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3693 (build_endian_shift): Don't check proc64.
3694 (build_instruction): Always set memval to uword64. Cast op2 to
3695 uword64 when shifting it left in memory instructions. Always use
3696 the same code for stores--don't special case proc64.
3697
3698 * gencode.c (build_mips16_operands): Fix base PC value for PC
3699 relative operands.
3700 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3701 jal instruction.
3702 * interp.c (simJALDELAYSLOT): Define.
3703 (JALDELAYSLOT): Define.
3704 (INDELAYSLOT, INJALDELAYSLOT): Define.
3705 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3706
3707Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3708
3709 * interp.c (sim_open): add flush_cache as a PMON routine
3710 (sim_monitor): handle flush_cache by ignoring it
3711
3712Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3713
3714 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3715 BigEndianMem.
3716 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3717 (BigEndianMem): Rename to ByteSwapMem and change sense.
3718 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3719 BigEndianMem references to !ByteSwapMem.
3720 (set_endianness): New function, with prototype.
3721 (sim_open): Call set_endianness.
3722 (sim_info): Use simBE instead of BigEndianMem.
3723 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3724 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3725 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3726 ifdefs, keeping the prototype declaration.
3727 (swap_word): Rewrite correctly.
3728 (ColdReset): Delete references to CONFIG. Delete endianness related
3729 code; moved to set_endianness.
72f4393d 3730
c906108c
SS		 3731Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3732
3733 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3734 * interp.c (CHECKHILO): Define away.
3735 (simSIGINT): New macro.
3736 (membank_size): Increase from 1MB to 2MB.
3737 (control_c): New function.
3738 (sim_resume): Rename parameter signal to signal_number. Add local
3739 variable prev. Call signal before and after simulate.
3740 (sim_stop_reason): Add simSIGINT support.
3741 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3742 functions always.
3743 (sim_warning): Delete call to SignalException. Do call printf_filtered
3744 if logfh is NULL.
3745 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3746 a call to sim_warning.
3747
3748Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3749
3750 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3751 16 bit instructions.
3752
3753Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3754
3755 Add support for mips16 (16 bit MIPS implementation):
3756 * gencode.c (inst_type): Add mips16 instruction encoding types.
3757 (GETDATASIZEINSN): Define.
3758 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3759 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3760 mtlo.
3761 (MIPS16_DECODE): New table, for mips16 instructions.
3762 (bitmap_val): New static function.
3763 (struct mips16_op): Define.
3764 (mips16_op_table): New table, for mips16 operands.
3765 (build_mips16_operands): New static function.
3766 (process_instructions): If PC is odd, decode a mips16
3767 instruction. Break out instruction handling into new
3768 build_instruction function.
3769 (build_instruction): New static function, broken out of
3770 process_instructions. Check modifiers rather than flags for SHIFT
3771 bit count and m[ft]{hi,lo} direction.
3772 (usage): Pass program name to fprintf.
3773 (main): Remove unused variable this_option_optind. Change
3774 ``*loptarg++'' to ``loptarg++''.
3775 (my_strtoul): Parenthesize && within ||.
3776 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3777 (simulate): If PC is odd, fetch a 16 bit instruction, and
3778 increment PC by 2 rather than 4.
3779 * configure.in: Add case for mips16*-*-*.
3780 * configure: Rebuild.
3781
3782Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3783
3784 * interp.c: Allow -t to enable tracing in standalone simulator.
3785 Fix garbage output in trace file and error messages.
3786
3787Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3788
3789 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3790 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3791 * configure.in: Simplify using macros in ../common/aclocal.m4.
3792 * configure: Regenerated.
3793 * tconfig.in: New file.
3794
3795Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3796
3797 * interp.c: Fix bugs in 64-bit port.
3798 Use ansi function declarations for msvc compiler.
3799 Initialize and test file pointer in trace code.
3800 Prevent duplicate definition of LAST_EMED_REGNUM.
3801
3802Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3803
3804 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3805
3806Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3807
3808 * interp.c (SignalException): Check for explicit terminating
3809 breakpoint value.
3810 * gencode.c: Pass instruction value through SignalException()
3811 calls for Trap, Breakpoint and Syscall.
3812
3813Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3814
3815 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3816 only used on those hosts that provide it.
3817 * configure.in: Add sqrt() to list of functions to be checked for.
3818 * config.in: Re-generated.
3819 * configure: Re-generated.
3820
3821Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3822
3823 * gencode.c (process_instructions): Call build_endian_shift when
3824 expanding STORE RIGHT, to fix swr.
3825 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3826 clear the high bits.
3827 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3828 Fix float to int conversions to produce signed values.
3829
3830Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3831
3832 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3833 (process_instructions): Correct handling of nor instruction.
3834 Correct shift count for 32 bit shift instructions. Correct sign
3835 extension for arithmetic shifts to not shift the number of bits in
3836 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3837 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3838 Fix madd.
3839 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3840 It's OK to have a mult follow a mult. What's not OK is to have a
3841 mult follow an mfhi.
3842 (Convert): Comment out incorrect rounding code.
3843
3844Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3845
3846 * interp.c (sim_monitor): Improved monitor printf
3847 simulation. Tidied up simulator warnings, and added "--log" option
3848 for directing warning message output.
3849 * gencode.c: Use sim_warning() rather than WARNING macro.
3850
3851Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3852
3853 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3854 getopt1.o, rather than on gencode.c. Link objects together.
3855 Don't link against -liberty.
3856 (gencode.o, getopt.o, getopt1.o): New targets.
3857 * gencode.c: Include <ctype.h> and "ansidecl.h".
3858 (AND): Undefine after including "ansidecl.h".
3859 (ULONG_MAX): Define if not defined.
3860 (OP_*): Don't define macros; now defined in opcode/mips.h.
3861 (main): Call my_strtoul rather than strtoul.
3862 (my_strtoul): New static function.
3863
3864Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3865
3866 * gencode.c (process_instructions): Generate word64 and uword64
3867 instead of `long long' and `unsigned long long' data types.
3868 * interp.c: #include sysdep.h to get signals, and define default
3869 for SIGBUS.
3870 * (Convert): Work around for Visual-C++ compiler bug with type
3871 conversion.
3872 * support.h: Make things compile under Visual-C++ by using
3873 __int64 instead of `long long'. Change many refs to long long
3874 into word64/uword64 typedefs.
3875
3876Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3877
72f4393d
L		 3878 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3879 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3880 (docdir): Removed.
3881 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3882 (AC_PROG_INSTALL): Added.
c906108c 3883 (AC_PROG_CC): Moved to before configure.host call.
72f4393d
L		 3884 * configure: Rebuilt.
3885
c906108c
SS		 3886Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3887
3888 * configure.in: Define @SIMCONF@ depending on mips target.
3889 * configure: Rebuild.
3890 * Makefile.in (run): Add @SIMCONF@ to control simulator
3891 construction.
3892 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3893 * interp.c: Remove some debugging, provide more detailed error
3894 messages, update memory accesses to use LOADDRMASK.
72f4393d 3895
c906108c
SS		 3896Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3897
3898 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3899 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3900 stamp-h.
3901 * configure: Rebuild.
3902 * config.in: New file, generated by autoheader.
3903 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3904 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3905 HAVE_ANINT and HAVE_AINT, as appropriate.
3906 * Makefile.in (run): Use @LIBS@ rather than -lm.
3907 (interp.o): Depend upon config.h.
3908 (Makefile): Just rebuild Makefile.
3909 (clean): Remove stamp-h.
3910 (mostlyclean): Make the same as clean, not as distclean.
3911 (config.h, stamp-h): New targets.
3912
3913Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3914
3915 * interp.c (ColdReset): Fix boolean test. Make all simulator
3916 globals static.
3917
3918Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3919
3920 * interp.c (xfer_direct_word, xfer_direct_long,
3921 swap_direct_word, swap_direct_long, xfer_big_word,
3922 xfer_big_long, xfer_little_word, xfer_little_long,
3923 swap_word,swap_long): Added.
3924 * interp.c (ColdReset): Provide function indirection to
3925 host<->simulated_target transfer routines.
3926 * interp.c (sim_store_register, sim_fetch_register): Updated to
3927 make use of indirected transfer routines.
3928
3929Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3930
3931 * gencode.c (process_instructions): Ensure FP ABS instruction
3932 recognised.
3933 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3934 system call support.
3935
3936Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3937
3938 * interp.c (sim_do_command): Complain if callback structure not
3939 initialised.
3940
3941Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3942
3943 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3944 support for Sun hosts.
3945 * Makefile.in (gencode): Ensure the host compiler and libraries
3946 used for cross-hosted build.
3947
3948Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3949
3950 * interp.c, gencode.c: Some more (TODO) tidying.
3951
3952Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3953
3954 * gencode.c, interp.c: Replaced explicit long long references with
3955 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3956 * support.h (SET64LO, SET64HI): Macros added.
3957
3958Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3959
3960 * configure: Regenerate with autoconf 2.7.
3961
3962Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3963
3964 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3965 * support.h: Remove superfluous "1" from #if.
3966 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3967
3968Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3969
3970 * interp.c (StoreFPR): Control UndefinedResult() call on
3971 WARN_RESULT manifest.
3972
3973Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3974
3975 * gencode.c: Tidied instruction decoding, and added FP instruction
3976 support.
3977
3978 * interp.c: Added dineroIII, and BSD profiling support. Also
3979 run-time FP handling.
3980
3981Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3982
3983 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3984 gencode.c, interp.c, support.h: created.
GDB Binutils - Deliverables
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