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[igen/ChangeLog]
[deliverable/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
dd69d292
CD		 12003-05-03 Chris Demetriou <cgd@broadcom.com>
2
3 * cp1.c: Tweak attribution slightly.
4 * cp1.h: Likewise.
5 * mdmx.c: Likewise.
6 * mdmx.igen: Likewise.
7 * mips3d.igen: Likewise.
8 * sb1.igen: Likewise.
9
bcd0068e
CD		 102003-04-15 Richard Sandiford <rsandifo@redhat.com>
11
12 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
13 unsigned operands.
14
6b4a8935
AC		 152003-02-27 Andrew Cagney <cagney@redhat.com>
16
601da316
AC		 17 * interp.c (sim_open): Rename _bfd to bfd.
18 (sim_create_inferior): Ditto.
6b4a8935 19
d29e330f
CD		 202003-01-14 Chris Demetriou <cgd@broadcom.com>
21
22 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
23
a2353a08
CD		 242003-01-14 Chris Demetriou <cgd@broadcom.com>
25
26 * mips.igen (EI, DI): Remove.
27
80551777
CD		 282003-01-05 Richard Sandiford <rsandifo@redhat.com>
29
30 * Makefile.in (tmp-run-multi): Fix mips16 filter.
31
4c54fc26
CD		 322003-01-04 Richard Sandiford <rsandifo@redhat.com>
33 Andrew Cagney <ac131313@redhat.com>
34 Gavin Romig-Koch <gavin@redhat.com>
35 Graydon Hoare <graydon@redhat.com>
36 Aldy Hernandez <aldyh@redhat.com>
37 Dave Brolley <brolley@redhat.com>
38 Chris Demetriou <cgd@broadcom.com>
39
40 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
41 (sim_mach_default): New variable.
42 (mips64vr-*-*, mips64vrel-*-*): New configurations.
43 Add a new simulator generator, MULTI.
44 * configure: Regenerate.
45 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
46 (multi-run.o): New dependency.
47 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
48 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
49 (tmp-multi): Combine them.
50 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
51 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
52 (distclean-extra): New rule.
53 * sim-main.h: Include bfd.h.
54 (MIPS_MACH): New macro.
55 * mips.igen (vr4120, vr5400, vr5500): New models.
56 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
57 * vr.igen: Replace with new version.
58
e6c674b8
CD		 592003-01-04 Chris Demetriou <cgd@broadcom.com>
60
61 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
62 * configure: Regenerate.
63
28f50ac8
CD		 642002-12-31 Chris Demetriou <cgd@broadcom.com>
65
66 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
67 * mips.igen: Remove all invocations of check_branch_bug and
68 mark_branch_bug.
69
5071ffe6
CD		 702002-12-16 Chris Demetriou <cgd@broadcom.com>
71
72 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
73
06e7837e
CD		 742002-07-30 Chris Demetriou <cgd@broadcom.com>
75
76 * mips.igen (do_load_double, do_store_double): New functions.
77 (LDC1, SDC1): Rename to...
78 (LDC1b, SDC1b): respectively.
79 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
80
2265c243
MS		 812002-07-29 Michael Snyder <msnyder@redhat.com>
82
83 * cp1.c (fp_recip2): Modify initialization expression so that
84 GCC will recognize it as constant.
85
a2f8b4f3
CD		 862002-06-18 Chris Demetriou <cgd@broadcom.com>
87
88 * mdmx.c (SD_): Delete.
89 (Unpredictable): Re-define, for now, to directly invoke
90 unpredictable_action().
91 (mdmx_acc_op): Fix error in .ob immediate handling.
92
b4b6c939
AC		 932002-06-18 Andrew Cagney <cagney@redhat.com>
94
95 * interp.c (sim_firmware_command): Initialize `address'.
96
c8cca39f
AC		 972002-06-16 Andrew Cagney <ac131313@redhat.com>
98
99 * configure: Regenerated to track ../common/aclocal.m4 changes.
100
e7e81181
CD		 1012002-06-14 Chris Demetriou <cgd@broadcom.com>
102 Ed Satterthwaite <ehs@broadcom.com>
103
104 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
105 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
106 * mips.igen: Include mips3d.igen.
107 (mips3d): New model name for MIPS-3D ASE instructions.
108 (CVT.W.fmt): Don't use this instruction for word (source) format
109 instructions.
110 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
111 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
112 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
113 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
114 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
115 (RSquareRoot1, RSquareRoot2): New macros.
116 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
117 (fp_rsqrt2): New functions.
118 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
119 * configure: Regenerate.
120
3a2b820e 1212002-06-13 Chris Demetriou <cgd@broadcom.com>
eab54952 122 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 123
124 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
125 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
126 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
127 (convert): Note that this function is not used for paired-single
128 format conversions.
129 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
130 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
131 (check_fmt_p): Enable paired-single support.
132 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
133 (PUU.PS): New instructions.
134 (CVT.S.fmt): Don't use this instruction for paired-single format
135 destinations.
136 * sim-main.h (FP_formats): New value 'fmt_ps.'
137 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
138 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
139
d18ea9c2
CD		 1402002-06-12 Chris Demetriou <cgd@broadcom.com>
141
142 * mips.igen: Fix formatting of function calls in
143 many FP operations.
144
95fd5cee
CD		 1452002-06-12 Chris Demetriou <cgd@broadcom.com>
146
147 * mips.igen (MOVN, MOVZ): Trace result.
148 (TNEI): Print "tnei" as the opcode name in traces.
149 (CEIL.W): Add disassembly string for traces.
150 (RSQRT.fmt): Make location of disassembly string consistent
151 with other instructions.
152
4f0d55ae
CD		 1532002-06-12 Chris Demetriou <cgd@broadcom.com>
154
155 * mips.igen (X): Delete unused function.
156
3c25f8c7
AC		 1572002-06-08 Andrew Cagney <cagney@redhat.com>
158
159 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
160
f3c08b7e
CD		 1612002-06-07 Chris Demetriou <cgd@broadcom.com>
162 Ed Satterthwaite <ehs@broadcom.com>
163
164 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
165 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
166 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
167 (fp_nmsub): New prototypes.
168 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
169 (NegMultiplySub): New defines.
170 * mips.igen (RSQRT.fmt): Use RSquareRoot().
171 (MADD.D, MADD.S): Replace with...
172 (MADD.fmt): New instruction.
173 (MSUB.D, MSUB.S): Replace with...
174 (MSUB.fmt): New instruction.
175 (NMADD.D, NMADD.S): Replace with...
176 (NMADD.fmt): New instruction.
177 (NMSUB.D, MSUB.S): Replace with...
178 (NMSUB.fmt): New instruction.
179
52714ff9
CD		 1802002-06-07 Chris Demetriou <cgd@broadcom.com>
181 Ed Satterthwaite <ehs@broadcom.com>
182
183 * cp1.c: Fix more comment spelling and formatting.
184 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
185 (denorm_mode): New function.
186 (fpu_unary, fpu_binary): Round results after operation, collect
187 status from rounding operations, and update the FCSR.
188 (convert): Collect status from integer conversions and rounding
189 operations, and update the FCSR. Adjust NaN values that result
190 from conversions. Convert to use sim_io_eprintf rather than
191 fprintf, and remove some debugging code.
192 * cp1.h (fenr_FS): New define.
193
577d8c4b
CD		 1942002-06-07 Chris Demetriou <cgd@broadcom.com>
195
196 * cp1.c (convert): Remove unusable debugging code, and move MIPS
197 rounding mode to sim FP rounding mode flag conversion code into...
198 (rounding_mode): New function.
199
196496ed
CD		 2002002-06-07 Chris Demetriou <cgd@broadcom.com>
201
202 * cp1.c: Clean up formatting of a few comments.
203 (value_fpr): Reformat switch statement.
204
cfe9ea23
CD		 2052002-06-06 Chris Demetriou <cgd@broadcom.com>
206 Ed Satterthwaite <ehs@broadcom.com>
207
208 * cp1.h: New file.
209 * sim-main.h: Include cp1.h.
210 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
211 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
212 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
213 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
214 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
215 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
216 * cp1.c: Don't include sim-fpu.h; already included by
217 sim-main.h. Clean up formatting of some comments.
218 (NaN, Equal, Less): Remove.
219 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
220 (fp_cmp): New functions.
221 * mips.igen (do_c_cond_fmt): Remove.
222 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
223 Compare. Add result tracing.
224 (CxC1): Remove, replace with...
225 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
226 (DMxC1): Remove, replace with...
227 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
228 (MxC1): Remove, replace with...
229 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
230
ee7254b0
CD		 2312002-06-04 Chris Demetriou <cgd@broadcom.com>
232
233 * sim-main.h (FGRIDX): Remove, replace all uses with...
234 (FGR_BASE): New macro.
235 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
236 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
237 (NR_FGR, FGR): Likewise.
238 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
239 * mips.igen: Likewise.
240
d3eb724f
CD		 2412002-06-04 Chris Demetriou <cgd@broadcom.com>
242
243 * cp1.c: Add an FSF Copyright notice to this file.
244
ba46ddd0
CD		 2452002-06-04 Chris Demetriou <cgd@broadcom.com>
246 Ed Satterthwaite <ehs@broadcom.com>
247
248 * cp1.c (Infinity): Remove.
249 * sim-main.h (Infinity): Likewise.
250
251 * cp1.c (fp_unary, fp_binary): New functions.
252 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
253 (fp_sqrt): New functions, implemented in terms of the above.
254 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
255 (Recip, SquareRoot): Remove (replaced by functions above).
256 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
257 (fp_recip, fp_sqrt): New prototypes.
258 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
259 (Recip, SquareRoot): Replace prototypes with #defines which
260 invoke the functions above.
261
18d8a52d
CD		 2622002-06-03 Chris Demetriou <cgd@broadcom.com>
263
264 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
265 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
266 file, remove PARAMS from prototypes.
267 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
268 simulator state arguments.
269 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
270 pass simulator state arguments.
271 * cp1.c (SD): Redefine as CPU_STATE(cpu).
272 (store_fpr, convert): Remove 'sd' argument.
273 (value_fpr): Likewise. Convert to use 'SD' instead.
274
0f154cbd
CD		 2752002-06-03 Chris Demetriou <cgd@broadcom.com>
276
277 * cp1.c (Min, Max): Remove #if 0'd functions.
278 * sim-main.h (Min, Max): Remove.
279
e80fc152
CD		 2802002-06-03 Chris Demetriou <cgd@broadcom.com>
281
282 * cp1.c: fix formatting of switch case and default labels.
283 * interp.c: Likewise.
284 * sim-main.c: Likewise.
285
bad673a9
CD		 2862002-06-03 Chris Demetriou <cgd@broadcom.com>
287
288 * cp1.c: Clean up comments which describe FP formats.
289 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
290
7cbea089
CD		 2912002-06-03 Chris Demetriou <cgd@broadcom.com>
292 Ed Satterthwaite <ehs@broadcom.com>
293
294 * configure.in (mipsisa64sb1*-*-*): New target for supporting
295 Broadcom SiByte SB-1 processor configurations.
296 * configure: Regenerate.
297 * sb1.igen: New file.
298 * mips.igen: Include sb1.igen.
299 (sb1): New model.
300 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
301 * mdmx.igen: Add "sb1" model to all appropriate functions and
302 instructions.
303 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
304 (ob_func, ob_acc): Reference the above.
305 (qh_acc): Adjust to keep the same size as ob_acc.
306 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
307 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
308
909daa82
CD		 3092002-06-03 Chris Demetriou <cgd@broadcom.com>
310
311 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
312
f4f1b9f1
CD		 3132002-06-02 Chris Demetriou <cgd@broadcom.com>
314 Ed Satterthwaite <ehs@broadcom.com>
315
316 * mips.igen (mdmx): New (pseudo-)model.
317 * mdmx.c, mdmx.igen: New files.
318 * Makefile.in (SIM_OBJS): Add mdmx.o.
319 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
320 New typedefs.
321 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
322 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
323 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
324 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
325 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
326 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
327 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
328 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
329 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
330 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
331 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
332 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
333 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
334 (qh_fmtsel): New macros.
335 (_sim_cpu): New member "acc".
336 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
337 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
338
5accf1ff
CD		 3392002-05-01 Chris Demetriou <cgd@broadcom.com>
340
341 * interp.c: Use 'deprecated' rather than 'depreciated.'
342 * sim-main.h: Likewise.
343
402586aa
CD		 3442002-05-01 Chris Demetriou <cgd@broadcom.com>
345
346 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
347 which wouldn't compile anyway.
348 * sim-main.h (unpredictable_action): New function prototype.
349 (Unpredictable): Define to call igen function unpredictable().
350 (NotWordValue): New macro to call igen function not_word_value().
351 (UndefinedResult): Remove.
352 * interp.c (undefined_result): Remove.
353 (unpredictable_action): New function.
354 * mips.igen (not_word_value, unpredictable): New functions.
355 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
356 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
357 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
358 NotWordValue() to check for unpredictable inputs, then
359 Unpredictable() to handle them.
360
c9b9995a
CD		 3612002-02-24 Chris Demetriou <cgd@broadcom.com>
362
363 * mips.igen: Fix formatting of calls to Unpredictable().
364
e1015982
AC		 3652002-04-20 Andrew Cagney <ac131313@redhat.com>
366
367 * interp.c (sim_open): Revert previous change.
368
b882a66b
AO		 3692002-04-18 Alexandre Oliva <aoliva@redhat.com>
370
371 * interp.c (sim_open): Disable chunk of code that wrote code in
372 vector table entries.
373
c429b7dd
CD		 3742002-03-19 Chris Demetriou <cgd@broadcom.com>
375
376 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
377 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
378 unused definitions.
379
37d146fa
CD		 3802002-03-19 Chris Demetriou <cgd@broadcom.com>
381
382 * cp1.c: Fix many formatting issues.
383
07892c0b
CD		 3842002-03-19 Chris G. Demetriou <cgd@broadcom.com>
385
386 * cp1.c (fpu_format_name): New function to replace...
387 (DOFMT): This. Delete, and update all callers.
388 (fpu_rounding_mode_name): New function to replace...
389 (RMMODE): This. Delete, and update all callers.
390
487f79b7
CD		 3912002-03-19 Chris G. Demetriou <cgd@broadcom.com>
392
393 * interp.c: Move FPU support routines from here to...
394 * cp1.c: Here. New file.
395 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
396 (cp1.o): New target.
397
1e799e28
CD		 3982002-03-12 Chris Demetriou <cgd@broadcom.com>
399
400 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
401 * mips.igen (mips32, mips64): New models, add to all instructions
402 and functions as appropriate.
403 (loadstore_ea, check_u64): New variant for model mips64.
404 (check_fmt_p): New variant for models mipsV and mips64, remove
405 mipsV model marking fro other variant.
406 (SLL) Rename to...
407 (SLLa) this.
408 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
409 for mips32 and mips64.
410 (DCLO, DCLZ): New instructions for mips64.
411
82f728db
CD		 4122002-03-07 Chris Demetriou <cgd@broadcom.com>
413
414 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
415 immediate or code as a hex value with the "%#lx" format.
416 (ANDI): Likewise, and fix printed instruction name.
417
b96e7ef1
CD		 4182002-03-05 Chris Demetriou <cgd@broadcom.com>
419
420 * sim-main.h (UndefinedResult, Unpredictable): New macros
421 which currently do nothing.
422
d35d4f70
CD		 4232002-03-05 Chris Demetriou <cgd@broadcom.com>
424
425 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
426 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
427 (status_CU3): New definitions.
428
429 * sim-main.h (ExceptionCause): Add new values for MIPS32
430 and MIPS64: MDMX, MCheck, CacheErr. Update comments
431 for DebugBreakPoint and NMIReset to note their status in
432 MIPS32 and MIPS64.
433 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
434 (SignalExceptionCacheErr): New exception macros.
435
3ad6f714
CD		 4362002-03-05 Chris Demetriou <cgd@broadcom.com>
437
438 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
439 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
440 is always enabled.
441 (SignalExceptionCoProcessorUnusable): Take as argument the
442 unusable coprocessor number.
443
86b77b47
CD		 4442002-03-05 Chris Demetriou <cgd@broadcom.com>
445
446 * mips.igen: Fix formatting of all SignalException calls.
447
97a88e93 4482002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 449
450 * sim-main.h (SIGNEXTEND): Remove.
451
97a88e93 4522002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 453
454 * mips.igen: Remove gencode comment from top of file, fix
455 spelling in another comment.
456
97a88e93 4572002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 458
459 * mips.igen (check_fmt, check_fmt_p): New functions to check
460 whether specific floating point formats are usable.
461 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
462 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
463 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
464 Use the new functions.
465 (do_c_cond_fmt): Remove format checks...
466 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
467
97a88e93 4682002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 469
470 * mips.igen: Fix formatting of check_fpu calls.
471
41774c9d
CD		 4722002-03-03 Chris Demetriou <cgd@broadcom.com>
473
474 * mips.igen (FLOOR.L.fmt): Store correct destination register.
475
4a0bd876
CD		 4762002-03-03 Chris Demetriou <cgd@broadcom.com>
477
478 * mips.igen: Remove whitespace at end of lines.
479
09297648
CD		 4802002-03-02 Chris Demetriou <cgd@broadcom.com>
481
482 * mips.igen (loadstore_ea): New function to do effective
483 address calculations.
484 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
485 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
486 CACHE): Use loadstore_ea to do effective address computations.
487
043b7057
CD		 4882002-03-02 Chris Demetriou <cgd@broadcom.com>
489
490 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
491 * mips.igen (LL, CxC1, MxC1): Likewise.
492
c1e8ada4
CD		 4932002-03-02 Chris Demetriou <cgd@broadcom.com>
494
495 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
496 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
497 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
498 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
499 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
500 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
501 Don't split opcode fields by hand, use the opcode field values
502 provided by igen.
503
3e1dca16
CD		 5042002-03-01 Chris Demetriou <cgd@broadcom.com>
505
506 * mips.igen (do_divu): Fix spacing.
507
508 * mips.igen (do_dsllv): Move to be right before DSLLV,
509 to match the rest of the do_<shift> functions.
510
fff8d27d
CD		 5112002-03-01 Chris Demetriou <cgd@broadcom.com>
512
513 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
514 DSRL32, do_dsrlv): Trace inputs and results.
515
0d3e762b
CD		 5162002-03-01 Chris Demetriou <cgd@broadcom.com>
517
518 * mips.igen (CACHE): Provide instruction-printing string.
519
520 * interp.c (signal_exception): Comment tokens after #endif.
521
eb5fcf93
CD		 5222002-02-28 Chris Demetriou <cgd@broadcom.com>
523
524 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
525 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
526 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
527 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
528 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
529 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
530 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
531 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
532
bb22bd7d
CD		 5332002-02-28 Chris Demetriou <cgd@broadcom.com>
534
535 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
536 instruction-printing string.
537 (LWU): Use '64' as the filter flag.
538
91a177cf
CD		 5392002-02-28 Chris Demetriou <cgd@broadcom.com>
540
541 * mips.igen (SDXC1): Fix instruction-printing string.
542
387f484a
CD		 5432002-02-28 Chris Demetriou <cgd@broadcom.com>
544
545 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
546 filter flags "32,f".
547
3d81f391
CD		 5482002-02-27 Chris Demetriou <cgd@broadcom.com>
549
550 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
551 as the filter flag.
552
af5107af
CD		 5532002-02-27 Chris Demetriou <cgd@broadcom.com>
554
555 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
556 add a comma) so that it more closely match the MIPS ISA
557 documentation opcode partitioning.
558 (PREF): Put useful names on opcode fields, and include
559 instruction-printing string.
560
ca971540
CD		 5612002-02-27 Chris Demetriou <cgd@broadcom.com>
562
563 * mips.igen (check_u64): New function which in the future will
564 check whether 64-bit instructions are usable and signal an
565 exception if not. Currently a no-op.
566 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
567 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
568 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
569 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
570
571 * mips.igen (check_fpu): New function which in the future will
572 check whether FPU instructions are usable and signal an exception
573 if not. Currently a no-op.
574 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
575 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
576 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
577 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
578 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
579 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
580 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
581 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
582
1c47a468
CD		 5832002-02-27 Chris Demetriou <cgd@broadcom.com>
584
585 * mips.igen (do_load_left, do_load_right): Move to be immediately
586 following do_load.
587 (do_store_left, do_store_right): Move to be immediately following
588 do_store.
589
603a98e7
CD		 5902002-02-27 Chris Demetriou <cgd@broadcom.com>
591
592 * mips.igen (mipsV): New model name. Also, add it to
593 all instructions and functions where it is appropriate.
594
c5d00cc7
CD		 5952002-02-18 Chris Demetriou <cgd@broadcom.com>
596
597 * mips.igen: For all functions and instructions, list model
598 names that support that instruction one per line.
599
074e9cb8
CD		 6002002-02-11 Chris Demetriou <cgd@broadcom.com>
601
602 * mips.igen: Add some additional comments about supported
603 models, and about which instructions go where.
604 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
605 order as is used in the rest of the file.
606
9805e229
CD		 6072002-02-11 Chris Demetriou <cgd@broadcom.com>
608
609 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
610 indicating that ALU32_END or ALU64_END are there to check
611 for overflow.
612 (DADD): Likewise, but also remove previous comment about
613 overflow checking.
614
f701dad2
CD		 6152002-02-10 Chris Demetriou <cgd@broadcom.com>
616
617 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
618 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
619 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
620 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
621 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
622 fields (i.e., add and move commas) so that they more closely
623 match the MIPS ISA documentation opcode partitioning.
624
6252002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098
CD		 626
627 * mips.igen (ADDI): Print immediate value.
628 (BREAK): Print code.
629 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
630 (SLL): Print "nop" specially, and don't run the code
631 that does the shift for the "nop" case.
632
9e52972e
FF		 6332001-11-17 Fred Fish <fnf@redhat.com>
634
635 * sim-main.h (float_operation): Move enum declaration outside
636 of _sim_cpu struct declaration.
637
c0efbca4
JB		 6382001-04-12 Jim Blandy <jimb@redhat.com>
639
640 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
641 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
642 set of the FCSR.
643 * sim-main.h (COCIDX): Remove definition; this isn't supported by
644 PENDING_FILL, and you can get the intended effect gracefully by
645 calling PENDING_SCHED directly.
646
fb891446
BE		 6472001-02-23 Ben Elliston <bje@redhat.com>
648
649 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
650 already defined elsewhere.
651
8030f857
BE		 6522001-02-19 Ben Elliston <bje@redhat.com>
653
654 * sim-main.h (sim_monitor): Return an int.
655 * interp.c (sim_monitor): Add return values.
656 (signal_exception): Handle error conditions from sim_monitor.
657
56b48a7a
CD		 6582001-02-08 Ben Elliston <bje@redhat.com>
659
660 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
661 (store_memory): Likewise, pass cia to sim_core_write*.
662
d3ee60d9
FCE		 6632000-10-19 Frank Ch. Eigler <fche@redhat.com>
664
665 On advice from Chris G. Demetriou <cgd@sibyte.com>:
666 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
667
071da002
AC		 668Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
669
670 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
671 * Makefile.in: Don't delete *.igen when cleaning directory.
672
a28c02cd
AC		 673Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
674
675 * m16.igen (break): Call SignalException not sim_engine_halt.
676
80ee11fa
AC		 677Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
678
679 From Jason Eckhardt:
680 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
681
673388c0
AC		 682Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
683
684 * mips.igen (MxC1, DMxC1): Fix printf formatting.
685
4c0deff4
NC		 6862000-05-24 Michael Hayes <mhayes@cygnus.com>
687
688 * mips.igen (do_dmultx): Fix typo.
689
eb2d80b4
AC		 690Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
691
692 * configure: Regenerated to track ../common/aclocal.m4 changes.
693
dd37a34b
AC		 694Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
695
696 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
697
4c0deff4
NC		 6982000-04-12 Frank Ch. Eigler <fche@redhat.com>
699
700 * sim-main.h (GPR_CLEAR): Define macro.
701
e30db738
AC		 702Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
703
704 * interp.c (decode_coproc): Output long using %lx and not %s.
705
cb7450ea
FCE		 7062000-03-21 Frank Ch. Eigler <fche@redhat.com>
707
708 * interp.c (sim_open): Sort & extend dummy memory regions for
709 --board=jmr3904 for eCos.
710
a3027dd7
FCE		 7112000-03-02 Frank Ch. Eigler <fche@redhat.com>
712
713 * configure: Regenerated.
714
715Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
716
717 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
718 calls, conditional on the simulator being in verbose mode.
719
dfcd3bfb
JM		 720Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
721
722 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
723 cache don't get ReservedInstruction traps.
724
c2d11a7d
JM		 7251999-11-29 Mark Salter <msalter@cygnus.com>
726
727 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
728 to clear status bits in sdisr register. This is how the hardware works.
729
730 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
731 being used by cygmon.
732
4ce44c66
JM		 7331999-11-11 Andrew Haley <aph@cygnus.com>
734
735 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
736 instructions.
737
cff3e48b
JM		 738Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
739
740 * mips.igen (MULT): Correct previous mis-applied patch.
741
d4f3574e
SS		 742Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
743
744 * mips.igen (delayslot32): Handle sequence like
745 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
746 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
747 (MULT): Actually pass the third register...
748
7491999-09-03 Mark Salter <msalter@cygnus.com>
750
751 * interp.c (sim_open): Added more memory aliases for additional
752 hardware being touched by cygmon on jmr3904 board.
753
754Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
755
756 * configure: Regenerated to track ../common/aclocal.m4 changes.
757
a0b3c4fd
JM		 758Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
759
760 * interp.c (sim_store_register): Handle case where client - GDB -
761 specifies that a 4 byte register is 8 bytes in size.
762 (sim_fetch_register): Ditto.
763
adf40b2e
JM		 7641999-07-14 Frank Ch. Eigler <fche@cygnus.com>
765
766 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
767 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
768 (idt_monitor_base): Base address for IDT monitor traps.
769 (pmon_monitor_base): Ditto for PMON.
770 (lsipmon_monitor_base): Ditto for LSI PMON.
771 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
772 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
773 (sim_firmware_command): New function.
774 (mips_option_handler): Call it for OPTION_FIRMWARE.
775 (sim_open): Allocate memory for idt_monitor region. If "--board"
776 option was given, add no monitor by default. Add BREAK hooks only if
777 monitors are also there.
778
43e526b9
JM		 779Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
780
781 * interp.c (sim_monitor): Flush output before reading input.
782
783Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
784
785 * tconfig.in (SIM_HANDLES_LMA): Always define.
786
787Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
788
789 From Mark Salter <msalter@cygnus.com>:
790 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
791 (sim_open): Add setup for BSP board.
792
9846de1b
JM		 793Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
794
795 * mips.igen (MULT, MULTU): Add syntax for two operand version.
796 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
797 them as unimplemented.
798
cd0fc7c3
SS		 7991999-05-08 Felix Lee <flee@cygnus.com>
800
801 * configure: Regenerated to track ../common/aclocal.m4 changes.
802
7a292a7a
SS		 8031999-04-21 Frank Ch. Eigler <fche@cygnus.com>
804
805 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
806
807Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
808
809 * configure.in: Any mips64vr5*-*-* target should have
810 -DTARGET_ENABLE_FR=1.
811 (default_endian): Any mips64vr*el-*-* target should default to
812 LITTLE_ENDIAN.
813 * configure: Re-generate.
814
8151999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
816
817 * mips.igen (ldl): Extend from _16_, not 32.
818
819Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
820
821 * interp.c (sim_store_register): Force registers written to by GDB
822 into an un-interpreted state.
823
c906108c
SS		 8241999-02-05 Frank Ch. Eigler <fche@cygnus.com>
825
826 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
827 CPU, start periodic background I/O polls.
828 (tx3904sio_poll): New function: periodic I/O poller.
829
8301998-12-30 Frank Ch. Eigler <fche@cygnus.com>
831
832 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
833
834Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
835
836 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
837 case statement.
838
8391998-12-29 Frank Ch. Eigler <fche@cygnus.com>
840
841 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
842 (load_word): Call SIM_CORE_SIGNAL hook on error.
843 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
844 starting. For exception dispatching, pass PC instead of NULL_CIA.
845 (decode_coproc): Use COP0_BADVADDR to store faulting address.
846 * sim-main.h (COP0_BADVADDR): Define.
847 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
848 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
849 (_sim_cpu): Add exc_* fields to store register value snapshots.
850 * mips.igen (*): Replace memory-related SignalException* calls
851 with references to SIM_CORE_SIGNAL hook.
852
853 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
854 fix.
855 * sim-main.c (*): Minor warning cleanups.
856
8571998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
858
859 * m16.igen (DADDIU5): Correct type-o.
860
861Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
862
863 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
864 variables.
865
866Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
867
868 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
869 to include path.
870 (interp.o): Add dependency on itable.h
871 (oengine.c, gencode): Delete remaining references.
872 (BUILT_SRC_FROM_GEN): Clean up.
873
8741998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
875
876 * vr4run.c: New.
877 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
878 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
879 tmp-run-hack) : New.
880 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
881 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
882 Drop the "64" qualifier to get the HACK generator working.
883 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
884 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
885 qualifier to get the hack generator working.
886 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
887 (DSLL): Use do_dsll.
888 (DSLLV): Use do_dsllv.
889 (DSRA): Use do_dsra.
890 (DSRL): Use do_dsrl.
891 (DSRLV): Use do_dsrlv.
892 (BC1): Move *vr4100 to get the HACK generator working.
893 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
894 get the HACK generator working.
895 (MACC) Rename to get the HACK generator working.
896 (DMACC,MACCS,DMACCS): Add the 64.
897
8981998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
899
900 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
901 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
902
9031998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
904
905 * mips/interp.c (DEBUG): Cleanups.
906
9071998-12-10 Frank Ch. Eigler <fche@cygnus.com>
908
909 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
910 (tx3904sio_tickle): fflush after a stdout character output.
911
9121998-12-03 Frank Ch. Eigler <fche@cygnus.com>
913
914 * interp.c (sim_close): Uninstall modules.
915
916Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
917
918 * sim-main.h, interp.c (sim_monitor): Change to global
919 function.
920
921Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
922
923 * configure.in (vr4100): Only include vr4100 instructions in
924 simulator.
925 * configure: Re-generate.
926 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
927
928Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
929
930 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
931 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
932 true alternative.
933
934 * configure.in (sim_default_gen, sim_use_gen): Replace with
935 sim_gen.
936 (--enable-sim-igen): Delete config option. Always using IGEN.
937 * configure: Re-generate.
938
939 * Makefile.in (gencode): Kill, kill, kill.
940 * gencode.c: Ditto.
941
942Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
943
944 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
945 bit mips16 igen simulator.
946 * configure: Re-generate.
947
948 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
949 as part of vr4100 ISA.
950 * vr.igen: Mark all instructions as 64 bit only.
951
952Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
953
954 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
955 Pacify GCC.
956
957Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
958
959 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
960 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
961 * configure: Re-generate.
962
963 * m16.igen (BREAK): Define breakpoint instruction.
964 (JALX32): Mark instruction as mips16 and not r3900.
965 * mips.igen (C.cond.fmt): Fix typo in instruction format.
966
967 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
968
969Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
970
971 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
972 insn as a debug breakpoint.
973
974 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
975 pending.slot_size.
976 (PENDING_SCHED): Clean up trace statement.
977 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
978 (PENDING_FILL): Delay write by only one cycle.
979 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
980
981 * sim-main.c (pending_tick): Clean up trace statements. Add trace
982 of pending writes.
983 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
984 32 & 64.
985 (pending_tick): Move incrementing of index to FOR statement.
986 (pending_tick): Only update PENDING_OUT after a write has occured.
987
988 * configure.in: Add explicit mips-lsi-* target. Use gencode to
989 build simulator.
990 * configure: Re-generate.
991
992 * interp.c (sim_engine_run OLD): Delete explicit call to
993 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
994
995Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
996
997 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
998 interrupt level number to match changed SignalExceptionInterrupt
999 macro.
1000
1001Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1002
1003 * interp.c: #include "itable.h" if WITH_IGEN.
1004 (get_insn_name): New function.
1005 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1006 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1007
1008Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1009
1010 * configure: Rebuilt to inhale new common/aclocal.m4.
1011
1012Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1013
1014 * dv-tx3904sio.c: Include sim-assert.h.
1015
1016Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1017
1018 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1019 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1020 Reorganize target-specific sim-hardware checks.
1021 * configure: rebuilt.
1022 * interp.c (sim_open): For tx39 target boards, set
1023 OPERATING_ENVIRONMENT, add tx3904sio devices.
1024 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1025 ROM executables. Install dv-sockser into sim-modules list.
1026
1027 * dv-tx3904irc.c: Compiler warning clean-up.
1028 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1029 frequent hw-trace messages.
1030
1031Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1032
1033 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1034
1035Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1036
1037 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1038
1039 * vr.igen: New file.
1040 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1041 * mips.igen: Define vr4100 model. Include vr.igen.
1042Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1043
1044 * mips.igen (check_mf_hilo): Correct check.
1045
1046Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1047
1048 * sim-main.h (interrupt_event): Add prototype.
1049
1050 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1051 register_ptr, register_value.
1052 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1053
1054 * sim-main.h (tracefh): Make extern.
1055
1056Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1057
1058 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1059 Reduce unnecessarily high timer event frequency.
1060 * dv-tx3904cpu.c: Ditto for interrupt event.
1061
1062Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1063
1064 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1065 to allay warnings.
1066 (interrupt_event): Made non-static.
1067
1068 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1069 interchange of configuration values for external vs. internal
1070 clock dividers.
1071
1072Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1073
1074 * mips.igen (BREAK): Moved code to here for
1075 simulator-reserved break instructions.
1076 * gencode.c (build_instruction): Ditto.
1077 * interp.c (signal_exception): Code moved from here. Non-
1078 reserved instructions now use exception vector, rather
1079 than halting sim.
1080 * sim-main.h: Moved magic constants to here.
1081
1082Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1083
1084 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1085 register upon non-zero interrupt event level, clear upon zero
1086 event value.
1087 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1088 by passing zero event value.
1089 (*_io_{read,write}_buffer): Endianness fixes.
1090 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1091 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1092
1093 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1094 serial I/O and timer module at base address 0xFFFF0000.
1095
1096Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1097
1098 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1099 and BigEndianCPU.
1100
1101Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1102
1103 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1104 parts.
1105 * configure: Update.
1106
1107Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1108
1109 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1110 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1111 * configure.in: Include tx3904tmr in hw_device list.
1112 * configure: Rebuilt.
1113 * interp.c (sim_open): Instantiate three timer instances.
1114 Fix address typo of tx3904irc instance.
1115
1116Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1117
1118 * interp.c (signal_exception): SystemCall exception now uses
1119 the exception vector.
1120
1121Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1122
1123 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1124 to allay warnings.
1125
1126Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1127
1128 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1129
1130Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1131
1132 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1133
1134 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1135 sim-main.h. Declare a struct hw_descriptor instead of struct
1136 hw_device_descriptor.
1137
1138Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1139
1140 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1141 right bits and then re-align left hand bytes to correct byte
1142 lanes. Fix incorrect computation in do_store_left when loading
1143 bytes from second word.
1144
1145Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1146
1147 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1148 * interp.c (sim_open): Only create a device tree when HW is
1149 enabled.
1150
1151 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1152 * interp.c (signal_exception): Ditto.
1153
1154Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1155
1156 * gencode.c: Mark BEGEZALL as LIKELY.
1157
1158Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1159
1160 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1161 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1162
1163Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1164
1165 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1166 modules. Recognize TX39 target with "mips*tx39" pattern.
1167 * configure: Rebuilt.
1168 * sim-main.h (*): Added many macros defining bits in
1169 TX39 control registers.
1170 (SignalInterrupt): Send actual PC instead of NULL.
1171 (SignalNMIReset): New exception type.
1172 * interp.c (board): New variable for future use to identify
1173 a particular board being simulated.
1174 (mips_option_handler,mips_options): Added "--board" option.
1175 (interrupt_event): Send actual PC.
1176 (sim_open): Make memory layout conditional on board setting.
1177 (signal_exception): Initial implementation of hardware interrupt
1178 handling. Accept another break instruction variant for simulator
1179 exit.
1180 (decode_coproc): Implement RFE instruction for TX39.
1181 (mips.igen): Decode RFE instruction as such.
1182 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1183 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1184 bbegin to implement memory map.
1185 * dv-tx3904cpu.c: New file.
1186 * dv-tx3904irc.c: New file.
1187
1188Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1189
1190 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1191
1192Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1193
1194 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1195 with calls to check_div_hilo.
1196
1197Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1198
1199 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1200 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1201 Add special r3900 version of do_mult_hilo.
1202 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1203 with calls to check_mult_hilo.
1204 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1205 with calls to check_div_hilo.
1206
1207Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1208
1209 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1210 Document a replacement.
1211
1212Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1213
1214 * interp.c (sim_monitor): Make mon_printf work.
1215
1216Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1217
1218 * sim-main.h (INSN_NAME): New arg `cpu'.
1219
1220Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1221
1222 * configure: Regenerated to track ../common/aclocal.m4 changes.
1223
1224Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1225
1226 * configure: Regenerated to track ../common/aclocal.m4 changes.
1227 * config.in: Ditto.
1228
1229Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1230
1231 * acconfig.h: New file.
1232 * configure.in: Reverted change of Apr 24; use sinclude again.
1233
1234Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1235
1236 * configure: Regenerated to track ../common/aclocal.m4 changes.
1237 * config.in: Ditto.
1238
1239Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1240
1241 * configure.in: Don't call sinclude.
1242
1243Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1244
1245 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1246
1247Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1248
1249 * mips.igen (ERET): Implement.
1250
1251 * interp.c (decode_coproc): Return sign-extended EPC.
1252
1253 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1254
1255 * interp.c (signal_exception): Do not ignore Trap.
1256 (signal_exception): On TRAP, restart at exception address.
1257 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1258 (signal_exception): Update.
1259 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1260 so that TRAP instructions are caught.
1261
1262Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1263
1264 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1265 contains HI/LO access history.
1266 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1267 (HIACCESS, LOACCESS): Delete, replace with
1268 (HIHISTORY, LOHISTORY): New macros.
1269 (CHECKHILO): Delete all, moved to mips.igen
1270
1271 * gencode.c (build_instruction): Do not generate checks for
1272 correct HI/LO register usage.
1273
1274 * interp.c (old_engine_run): Delete checks for correct HI/LO
1275 register usage.
1276
1277 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1278 check_mf_cycles): New functions.
1279 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1280 do_divu, domultx, do_mult, do_multu): Use.
1281
1282 * tx.igen ("madd", "maddu"): Use.
1283
1284Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1285
1286 * mips.igen (DSRAV): Use function do_dsrav.
1287 (SRAV): Use new function do_srav.
1288
1289 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1290 (B): Sign extend 11 bit immediate.
1291 (EXT-B*): Shift 16 bit immediate left by 1.
1292 (ADDIU*): Don't sign extend immediate value.
1293
1294Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1295
1296 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1297
1298 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1299 functions.
1300
1301 * mips.igen (delayslot32, nullify_next_insn): New functions.
1302 (m16.igen): Always include.
1303 (do_*): Add more tracing.
1304
1305 * m16.igen (delayslot16): Add NIA argument, could be called by a
1306 32 bit MIPS16 instruction.
1307
1308 * interp.c (ifetch16): Move function from here.
1309 * sim-main.c (ifetch16): To here.
1310
1311 * sim-main.c (ifetch16, ifetch32): Update to match current
1312 implementations of LH, LW.
1313 (signal_exception): Don't print out incorrect hex value of illegal
1314 instruction.
1315
1316Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1317
1318 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1319 instruction.
1320
1321 * m16.igen: Implement MIPS16 instructions.
1322
1323 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1324 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1325 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1326 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1327 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1328 bodies of corresponding code from 32 bit insn to these. Also used
1329 by MIPS16 versions of functions.
1330
1331 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1332 (IMEM16): Drop NR argument from macro.
1333
1334Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1335
1336 * Makefile.in (SIM_OBJS): Add sim-main.o.
1337
1338 * sim-main.h (address_translation, load_memory, store_memory,
1339 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1340 as INLINE_SIM_MAIN.
1341 (pr_addr, pr_uword64): Declare.
1342 (sim-main.c): Include when H_REVEALS_MODULE_P.
1343
1344 * interp.c (address_translation, load_memory, store_memory,
1345 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1346 from here.
1347 * sim-main.c: To here. Fix compilation problems.
1348
1349 * configure.in: Enable inlining.
1350 * configure: Re-config.
1351
1352Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1353
1354 * configure: Regenerated to track ../common/aclocal.m4 changes.
1355
1356Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1357
1358 * mips.igen: Include tx.igen.
1359 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1360 * tx.igen: New file, contains MADD and MADDU.
1361
1362 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1363 the hardwired constant `7'.
1364 (store_memory): Ditto.
1365 (LOADDRMASK): Move definition to sim-main.h.
1366
1367 mips.igen (MTC0): Enable for r3900.
1368 (ADDU): Add trace.
1369
1370 mips.igen (do_load_byte): Delete.
1371 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1372 do_store_right): New functions.
1373 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1374
1375 configure.in: Let the tx39 use igen again.
1376 configure: Update.
1377
1378Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1379
1380 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1381 not an address sized quantity. Return zero for cache sizes.
1382
1383Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1384
1385 * mips.igen (r3900): r3900 does not support 64 bit integer
1386 operations.
1387
1388Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1389
1390 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1391 than igen one.
1392 * configure : Rebuild.
1393
1394Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1395
1396 * configure: Regenerated to track ../common/aclocal.m4 changes.
1397
1398Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1399
1400 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1401
1402Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1403
1404 * configure: Regenerated to track ../common/aclocal.m4 changes.
1405 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1406
1407Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1408
1409 * configure: Regenerated to track ../common/aclocal.m4 changes.
1410
1411Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1412
1413 * interp.c (Max, Min): Comment out functions. Not yet used.
1414
1415Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1416
1417 * configure: Regenerated to track ../common/aclocal.m4 changes.
1418
1419Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1420
1421 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1422 configurable settings for stand-alone simulator.
1423
1424 * configure.in: Added X11 search, just in case.
1425
1426 * configure: Regenerated.
1427
1428Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1429
1430 * interp.c (sim_write, sim_read, load_memory, store_memory):
1431 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1432
1433Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1434
1435 * sim-main.h (GETFCC): Return an unsigned value.
1436
1437Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1438
1439 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1440 (DADD): Result destination is RD not RT.
1441
1442Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1443
1444 * sim-main.h (HIACCESS, LOACCESS): Always define.
1445
1446 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1447
1448 * interp.c (sim_info): Delete.
1449
1450Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1451
1452 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1453 (mips_option_handler): New argument `cpu'.
1454 (sim_open): Update call to sim_add_option_table.
1455
1456Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1457
1458 * mips.igen (CxC1): Add tracing.
1459
1460Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1461
1462 * sim-main.h (Max, Min): Declare.
1463
1464 * interp.c (Max, Min): New functions.
1465
1466 * mips.igen (BC1): Add tracing.
1467
1468Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1469
1470 * interp.c Added memory map for stack in vr4100
1471
1472Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1473
1474 * interp.c (load_memory): Add missing "break"'s.
1475
1476Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1477
1478 * interp.c (sim_store_register, sim_fetch_register): Pass in
1479 length parameter. Return -1.
1480
1481Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1482
1483 * interp.c: Added hardware init hook, fixed warnings.
1484
1485Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1486
1487 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1488
1489Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1490
1491 * interp.c (ifetch16): New function.
1492
1493 * sim-main.h (IMEM32): Rename IMEM.
1494 (IMEM16_IMMED): Define.
1495 (IMEM16): Define.
1496 (DELAY_SLOT): Update.
1497
1498 * m16run.c (sim_engine_run): New file.
1499
1500 * m16.igen: All instructions except LB.
1501 (LB): Call do_load_byte.
1502 * mips.igen (do_load_byte): New function.
1503 (LB): Call do_load_byte.
1504
1505 * mips.igen: Move spec for insn bit size and high bit from here.
1506 * Makefile.in (tmp-igen, tmp-m16): To here.
1507
1508 * m16.dc: New file, decode mips16 instructions.
1509
1510 * Makefile.in (SIM_NO_ALL): Define.
1511 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1512
1513Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1514
1515 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1516 point unit to 32 bit registers.
1517 * configure: Re-generate.
1518
1519Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1520
1521 * configure.in (sim_use_gen): Make IGEN the default simulator
1522 generator for generic 32 and 64 bit mips targets.
1523 * configure: Re-generate.
1524
1525Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1526
1527 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1528 bitsize.
1529
1530 * interp.c (sim_fetch_register, sim_store_register): Read/write
1531 FGR from correct location.
1532 (sim_open): Set size of FGR's according to
1533 WITH_TARGET_FLOATING_POINT_BITSIZE.
1534
1535 * sim-main.h (FGR): Store floating point registers in a separate
1536 array.
1537
1538Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1539
1540 * configure: Regenerated to track ../common/aclocal.m4 changes.
1541
1542Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1543
1544 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1545
1546 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1547
1548 * interp.c (pending_tick): New function. Deliver pending writes.
1549
1550 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1551 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1552 it can handle mixed sized quantites and single bits.
1553
1554Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1555
1556 * interp.c (oengine.h): Do not include when building with IGEN.
1557 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1558 (sim_info): Ditto for PROCESSOR_64BIT.
1559 (sim_monitor): Replace ut_reg with unsigned_word.
1560 (*): Ditto for t_reg.
1561 (LOADDRMASK): Define.
1562 (sim_open): Remove defunct check that host FP is IEEE compliant,
1563 using software to emulate floating point.
1564 (value_fpr, ...): Always compile, was conditional on HASFPU.
1565
1566Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1567
1568 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1569 size.
1570
1571 * interp.c (SD, CPU): Define.
1572 (mips_option_handler): Set flags in each CPU.
1573 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1574 (sim_close): Do not clear STATE, deleted anyway.
1575 (sim_write, sim_read): Assume CPU zero's vm should be used for
1576 data transfers.
1577 (sim_create_inferior): Set the PC for all processors.
1578 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1579 argument.
1580 (mips16_entry): Pass correct nr of args to store_word, load_word.
1581 (ColdReset): Cold reset all cpu's.
1582 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1583 (sim_monitor, load_memory, store_memory, signal_exception): Use
1584 `CPU' instead of STATE_CPU.
1585
1586
1587 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1588 SD or CPU_.
1589
1590 * sim-main.h (signal_exception): Add sim_cpu arg.
1591 (SignalException*): Pass both SD and CPU to signal_exception.
1592 * interp.c (signal_exception): Update.
1593
1594 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1595 Ditto
1596 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1597 address_translation): Ditto
1598 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1599
1600Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1601
1602 * configure: Regenerated to track ../common/aclocal.m4 changes.
1603
1604Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1605
1606 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1607
1608 * mips.igen (model): Map processor names onto BFD name.
1609
1610 * sim-main.h (CPU_CIA): Delete.
1611 (SET_CIA, GET_CIA): Define
1612
1613Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1614
1615 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1616 regiser.
1617
1618 * configure.in (default_endian): Configure a big-endian simulator
1619 by default.
1620 * configure: Re-generate.
1621
1622Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1623
1624 * configure: Regenerated to track ../common/aclocal.m4 changes.
1625
1626Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1627
1628 * interp.c (sim_monitor): Handle Densan monitor outbyte
1629 and inbyte functions.
1630
16311997-12-29 Felix Lee <flee@cygnus.com>
1632
1633 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1634
1635Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1636
1637 * Makefile.in (tmp-igen): Arrange for $zero to always be
1638 reset to zero after every instruction.
1639
1640Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1641
1642 * configure: Regenerated to track ../common/aclocal.m4 changes.
1643 * config.in: Ditto.
1644
1645Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1646
1647 * mips.igen (MSUB): Fix to work like MADD.
1648 * gencode.c (MSUB): Similarly.
1649
1650Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1651
1652 * configure: Regenerated to track ../common/aclocal.m4 changes.
1653
1654Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1655
1656 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1657
1658Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1659
1660 * sim-main.h (sim-fpu.h): Include.
1661
1662 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1663 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1664 using host independant sim_fpu module.
1665
1666Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1667
1668 * interp.c (signal_exception): Report internal errors with SIGABRT
1669 not SIGQUIT.
1670
1671 * sim-main.h (C0_CONFIG): New register.
1672 (signal.h): No longer include.
1673
1674 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1675
1676Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1677
1678 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1679
1680Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1681
1682 * mips.igen: Tag vr5000 instructions.
1683 (ANDI): Was missing mipsIV model, fix assembler syntax.
1684 (do_c_cond_fmt): New function.
1685 (C.cond.fmt): Handle mips I-III which do not support CC field
1686 separatly.
1687 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1688 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1689 in IV3.2 spec.
1690 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1691 vr5000 which saves LO in a GPR separatly.
1692
1693 * configure.in (enable-sim-igen): For vr5000, select vr5000
1694 specific instructions.
1695 * configure: Re-generate.
1696
1697Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1698
1699 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1700
1701 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1702 fmt_uninterpreted_64 bit cases to switch. Convert to
1703 fmt_formatted,
1704
1705 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1706
1707 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1708 as specified in IV3.2 spec.
1709 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1710
1711Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1712
1713 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1714 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1715 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1716 PENDING_FILL versions of instructions. Simplify.
1717 (X): New function.
1718 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1719 instructions.
1720 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1721 a signed value.
1722 (MTHI, MFHI): Disable code checking HI-LO.
1723
1724 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1725 global.
1726 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1727
1728Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1729
1730 * gencode.c (build_mips16_operands): Replace IPC with cia.
1731
1732 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1733 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1734 IPC to `cia'.
1735 (UndefinedResult): Replace function with macro/function
1736 combination.
1737 (sim_engine_run): Don't save PC in IPC.
1738
1739 * sim-main.h (IPC): Delete.
1740
1741
1742 * interp.c (signal_exception, store_word, load_word,
1743 address_translation, load_memory, store_memory, cache_op,
1744 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1745 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1746 current instruction address - cia - argument.
1747 (sim_read, sim_write): Call address_translation directly.
1748 (sim_engine_run): Rename variable vaddr to cia.
1749 (signal_exception): Pass cia to sim_monitor
1750
1751 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1752 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1753 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1754
1755 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1756 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1757 SIM_ASSERT.
1758
1759 * interp.c (signal_exception): Pass restart address to
1760 sim_engine_restart.
1761
1762 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1763 idecode.o): Add dependency.
1764
1765 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1766 Delete definitions
1767 (DELAY_SLOT): Update NIA not PC with branch address.
1768 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1769
1770 * mips.igen: Use CIA not PC in branch calculations.
1771 (illegal): Call SignalException.
1772 (BEQ, ADDIU): Fix assembler.
1773
1774Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1775
1776 * m16.igen (JALX): Was missing.
1777
1778 * configure.in (enable-sim-igen): New configuration option.
1779 * configure: Re-generate.
1780
1781 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1782
1783 * interp.c (load_memory, store_memory): Delete parameter RAW.
1784 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1785 bypassing {load,store}_memory.
1786
1787 * sim-main.h (ByteSwapMem): Delete definition.
1788
1789 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1790
1791 * interp.c (sim_do_command, sim_commands): Delete mips specific
1792 commands. Handled by module sim-options.
1793
1794 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1795 (WITH_MODULO_MEMORY): Define.
1796
1797 * interp.c (sim_info): Delete code printing memory size.
1798
1799 * interp.c (mips_size): Nee sim_size, delete function.
1800 (power2): Delete.
1801 (monitor, monitor_base, monitor_size): Delete global variables.
1802 (sim_open, sim_close): Delete code creating monitor and other
1803 memory regions. Use sim-memopts module, via sim_do_commandf, to
1804 manage memory regions.
1805 (load_memory, store_memory): Use sim-core for memory model.
1806
1807 * interp.c (address_translation): Delete all memory map code
1808 except line forcing 32 bit addresses.
1809
1810Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1811
1812 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1813 trace options.
1814
1815 * interp.c (logfh, logfile): Delete globals.
1816 (sim_open, sim_close): Delete code opening & closing log file.
1817 (mips_option_handler): Delete -l and -n options.
1818 (OPTION mips_options): Ditto.
1819
1820 * interp.c (OPTION mips_options): Rename option trace to dinero.
1821 (mips_option_handler): Update.
1822
1823Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1824
1825 * interp.c (fetch_str): New function.
1826 (sim_monitor): Rewrite using sim_read & sim_write.
1827 (sim_open): Check magic number.
1828 (sim_open): Write monitor vectors into memory using sim_write.
1829 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1830 (sim_read, sim_write): Simplify - transfer data one byte at a
1831 time.
1832 (load_memory, store_memory): Clarify meaning of parameter RAW.
1833
1834 * sim-main.h (isHOST): Defete definition.
1835 (isTARGET): Mark as depreciated.
1836 (address_translation): Delete parameter HOST.
1837
1838 * interp.c (address_translation): Delete parameter HOST.
1839
1840Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1841
1842 * mips.igen:
1843
1844 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1845 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1846
1847Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1848
1849 * mips.igen: Add model filter field to records.
1850
1851Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1852
1853 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1854
1855 interp.c (sim_engine_run): Do not compile function sim_engine_run
1856 when WITH_IGEN == 1.
1857
1858 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1859 target architecture.
1860
1861 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1862 igen. Replace with configuration variables sim_igen_flags /
1863 sim_m16_flags.
1864
1865 * m16.igen: New file. Copy mips16 insns here.
1866 * mips.igen: From here.
1867
1868Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1869
1870 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1871 to top.
1872 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1873
1874Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1875
1876 * gencode.c (build_instruction): Follow sim_write's lead in using
1877 BigEndianMem instead of !ByteSwapMem.
1878
1879Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1880
1881 * configure.in (sim_gen): Dependent on target, select type of
1882 generator. Always select old style generator.
1883
1884 configure: Re-generate.
1885
1886 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1887 targets.
1888 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1889 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1890 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1891 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1892 SIM_@sim_gen@_*, set by autoconf.
1893
1894Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1895
1896 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1897
1898 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1899 CURRENT_FLOATING_POINT instead.
1900
1901 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1902 (address_translation): Raise exception InstructionFetch when
1903 translation fails and isINSTRUCTION.
1904
1905 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1906 sim_engine_run): Change type of of vaddr and paddr to
1907 address_word.
1908 (address_translation, prefetch, load_memory, store_memory,
1909 cache_op): Change type of vAddr and pAddr to address_word.
1910
1911 * gencode.c (build_instruction): Change type of vaddr and paddr to
1912 address_word.
1913
1914Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1915
1916 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1917 macro to obtain result of ALU op.
1918
1919Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1920
1921 * interp.c (sim_info): Call profile_print.
1922
1923Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1924
1925 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1926
1927 * sim-main.h (WITH_PROFILE): Do not define, defined in
1928 common/sim-config.h. Use sim-profile module.
1929 (simPROFILE): Delete defintion.
1930
1931 * interp.c (PROFILE): Delete definition.
1932 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1933 (sim_close): Delete code writing profile histogram.
1934 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1935 Delete.
1936 (sim_engine_run): Delete code profiling the PC.
1937
1938Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1939
1940 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1941
1942 * interp.c (sim_monitor): Make register pointers of type
1943 unsigned_word*.
1944
1945 * sim-main.h: Make registers of type unsigned_word not
1946 signed_word.
1947
1948Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1949
1950 * interp.c (sync_operation): Rename from SyncOperation, make
1951 global, add SD argument.
1952 (prefetch): Rename from Prefetch, make global, add SD argument.
1953 (decode_coproc): Make global.
1954
1955 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1956
1957 * gencode.c (build_instruction): Generate DecodeCoproc not
1958 decode_coproc calls.
1959
1960 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1961 (SizeFGR): Move to sim-main.h
1962 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1963 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1964 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1965 sim-main.h.
1966 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1967 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1968 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1969 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1970 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1971 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1972
1973 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1974 exception.
1975 (sim-alu.h): Include.
1976 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1977 (sim_cia): Typedef to instruction_address.
1978
1979Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1980
1981 * Makefile.in (interp.o): Rename generated file engine.c to
1982 oengine.c.
1983
1984 * interp.c: Update.
1985
1986Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1987
1988 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1989
1990Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1991
1992 * gencode.c (build_instruction): For "FPSQRT", output correct
1993 number of arguments to Recip.
1994
1995Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1996
1997 * Makefile.in (interp.o): Depends on sim-main.h
1998
1999 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2000
2001 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2002 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2003 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2004 STATE, DSSTATE): Define
2005 (GPR, FGRIDX, ..): Define.
2006
2007 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2008 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2009 (GPR, FGRIDX, ...): Delete macros.
2010
2011 * interp.c: Update names to match defines from sim-main.h
2012
2013Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2014
2015 * interp.c (sim_monitor): Add SD argument.
2016 (sim_warning): Delete. Replace calls with calls to
2017 sim_io_eprintf.
2018 (sim_error): Delete. Replace calls with sim_io_error.
2019 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2020 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2021 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2022 argument.
2023 (mips_size): Rename from sim_size. Add SD argument.
2024
2025 * interp.c (simulator): Delete global variable.
2026 (callback): Delete global variable.
2027 (mips_option_handler, sim_open, sim_write, sim_read,
2028 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2029 sim_size,sim_monitor): Use sim_io_* not callback->*.
2030 (sim_open): ZALLOC simulator struct.
2031 (PROFILE): Do not define.
2032
2033Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2034
2035 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2036 support.h with corresponding code.
2037
2038 * sim-main.h (word64, uword64), support.h: Move definition to
2039 sim-main.h.
2040 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2041
2042 * support.h: Delete
2043 * Makefile.in: Update dependencies
2044 * interp.c: Do not include.
2045
2046Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2047
2048 * interp.c (address_translation, load_memory, store_memory,
2049 cache_op): Rename to from AddressTranslation et.al., make global,
2050 add SD argument
2051
2052 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2053 CacheOp): Define.
2054
2055 * interp.c (SignalException): Rename to signal_exception, make
2056 global.
2057
2058 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2059
2060 * sim-main.h (SignalException, SignalExceptionInterrupt,
2061 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2062 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2063 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2064 Define.
2065
2066 * interp.c, support.h: Use.
2067
2068Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2069
2070 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2071 to value_fpr / store_fpr. Add SD argument.
2072 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2073 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2074
2075 * sim-main.h (ValueFPR, StoreFPR): Define.
2076
2077Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2078
2079 * interp.c (sim_engine_run): Check consistency between configure
2080 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2081 and HASFPU.
2082
2083 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2084 (mips_fpu): Configure WITH_FLOATING_POINT.
2085 (mips_endian): Configure WITH_TARGET_ENDIAN.
2086 * configure: Update.
2087
2088Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2089
2090 * configure: Regenerated to track ../common/aclocal.m4 changes.
2091
2092Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2093
2094 * configure: Regenerated.
2095
2096Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2097
2098 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2099
2100Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2101
2102 * gencode.c (print_igen_insn_models): Assume certain architectures
2103 include all mips* instructions.
2104 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2105 instruction.
2106
2107 * Makefile.in (tmp.igen): Add target. Generate igen input from
2108 gencode file.
2109
2110 * gencode.c (FEATURE_IGEN): Define.
2111 (main): Add --igen option. Generate output in igen format.
2112 (process_instructions): Format output according to igen option.
2113 (print_igen_insn_format): New function.
2114 (print_igen_insn_models): New function.
2115 (process_instructions): Only issue warnings and ignore
2116 instructions when no FEATURE_IGEN.
2117
2118Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2119
2120 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2121 MIPS targets.
2122
2123Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2124
2125 * configure: Regenerated to track ../common/aclocal.m4 changes.
2126
2127Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2128
2129 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2130 SIM_RESERVED_BITS): Delete, moved to common.
2131 (SIM_EXTRA_CFLAGS): Update.
2132
2133Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2134
2135 * configure.in: Configure non-strict memory alignment.
2136 * configure: Regenerated to track ../common/aclocal.m4 changes.
2137
2138Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2139
2140 * configure: Regenerated to track ../common/aclocal.m4 changes.
2141
2142Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2143
2144 * gencode.c (SDBBP,DERET): Added (3900) insns.
2145 (RFE): Turn on for 3900.
2146 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2147 (dsstate): Made global.
2148 (SUBTARGET_R3900): Added.
2149 (CANCELDELAYSLOT): New.
2150 (SignalException): Ignore SystemCall rather than ignore and
2151 terminate. Add DebugBreakPoint handling.
2152 (decode_coproc): New insns RFE, DERET; and new registers Debug
2153 and DEPC protected by SUBTARGET_R3900.
2154 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2155 bits explicitly.
2156 * Makefile.in,configure.in: Add mips subtarget option.
2157 * configure: Update.
2158
2159Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2160
2161 * gencode.c: Add r3900 (tx39).
2162
2163
2164Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2165
2166 * gencode.c (build_instruction): Don't need to subtract 4 for
2167 JALR, just 2.
2168
2169Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2170
2171 * interp.c: Correct some HASFPU problems.
2172
2173Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2174
2175 * configure: Regenerated to track ../common/aclocal.m4 changes.
2176
2177Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2178
2179 * interp.c (mips_options): Fix samples option short form, should
2180 be `x'.
2181
2182Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2183
2184 * interp.c (sim_info): Enable info code. Was just returning.
2185
2186Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2187
2188 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2189 MFC0.
2190
2191Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2192
2193 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2194 constants.
2195 (build_instruction): Ditto for LL.
2196
2197Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2198
2199 * configure: Regenerated to track ../common/aclocal.m4 changes.
2200
2201Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2202
2203 * configure: Regenerated to track ../common/aclocal.m4 changes.
2204 * config.in: Ditto.
2205
2206Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2207
2208 * interp.c (sim_open): Add call to sim_analyze_program, update
2209 call to sim_config.
2210
2211Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2212
2213 * interp.c (sim_kill): Delete.
2214 (sim_create_inferior): Add ABFD argument. Set PC from same.
2215 (sim_load): Move code initializing trap handlers from here.
2216 (sim_open): To here.
2217 (sim_load): Delete, use sim-hload.c.
2218
2219 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2220
2221Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2222
2223 * configure: Regenerated to track ../common/aclocal.m4 changes.
2224 * config.in: Ditto.
2225
2226Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2227
2228 * interp.c (sim_open): Add ABFD argument.
2229 (sim_load): Move call to sim_config from here.
2230 (sim_open): To here. Check return status.
2231
2232Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2233
2234 * gencode.c (build_instruction): Two arg MADD should
2235 not assign result to $0.
2236
2237Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2238
2239 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2240 * sim/mips/configure.in: Regenerate.
2241
2242Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2243
2244 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2245 signed8, unsigned8 et.al. types.
2246
2247 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2248 hosts when selecting subreg.
2249
2250Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2251
2252 * interp.c (sim_engine_run): Reset the ZERO register to zero
2253 regardless of FEATURE_WARN_ZERO.
2254 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2255
2256Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2257
2258 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2259 (SignalException): For BreakPoints ignore any mode bits and just
2260 save the PC.
2261 (SignalException): Always set the CAUSE register.
2262
2263Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2264
2265 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2266 exception has been taken.
2267
2268 * interp.c: Implement the ERET and mt/f sr instructions.
2269
2270Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2271
2272 * interp.c (SignalException): Don't bother restarting an
2273 interrupt.
2274
2275Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2276
2277 * interp.c (SignalException): Really take an interrupt.
2278 (interrupt_event): Only deliver interrupts when enabled.
2279
2280Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2281
2282 * interp.c (sim_info): Only print info when verbose.
2283 (sim_info) Use sim_io_printf for output.
2284
2285Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2286
2287 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2288 mips architectures.
2289
2290Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2291
2292 * interp.c (sim_do_command): Check for common commands if a
2293 simulator specific command fails.
2294
2295Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2296
2297 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2298 and simBE when DEBUG is defined.
2299
2300Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2301
2302 * interp.c (interrupt_event): New function. Pass exception event
2303 onto exception handler.
2304
2305 * configure.in: Check for stdlib.h.
2306 * configure: Regenerate.
2307
2308 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2309 variable declaration.
2310 (build_instruction): Initialize memval1.
2311 (build_instruction): Add UNUSED attribute to byte, bigend,
2312 reverse.
2313 (build_operands): Ditto.
2314
2315 * interp.c: Fix GCC warnings.
2316 (sim_get_quit_code): Delete.
2317
2318 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2319 * Makefile.in: Ditto.
2320 * configure: Re-generate.
2321
2322 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2323
2324Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2325
2326 * interp.c (mips_option_handler): New function parse argumes using
2327 sim-options.
2328 (myname): Replace with STATE_MY_NAME.
2329 (sim_open): Delete check for host endianness - performed by
2330 sim_config.
2331 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2332 (sim_open): Move much of the initialization from here.
2333 (sim_load): To here. After the image has been loaded and
2334 endianness set.
2335 (sim_open): Move ColdReset from here.
2336 (sim_create_inferior): To here.
2337 (sim_open): Make FP check less dependant on host endianness.
2338
2339 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2340 run.
2341 * interp.c (sim_set_callbacks): Delete.
2342
2343 * interp.c (membank, membank_base, membank_size): Replace with
2344 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2345 (sim_open): Remove call to callback->init. gdb/run do this.
2346
2347 * interp.c: Update
2348
2349 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2350
2351 * interp.c (big_endian_p): Delete, replaced by
2352 current_target_byte_order.
2353
2354Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2355
2356 * interp.c (host_read_long, host_read_word, host_swap_word,
2357 host_swap_long): Delete. Using common sim-endian.
2358 (sim_fetch_register, sim_store_register): Use H2T.
2359 (pipeline_ticks): Delete. Handled by sim-events.
2360 (sim_info): Update.
2361 (sim_engine_run): Update.
2362
2363Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2364
2365 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2366 reason from here.
2367 (SignalException): To here. Signal using sim_engine_halt.
2368 (sim_stop_reason): Delete, moved to common.
2369
2370Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2371
2372 * interp.c (sim_open): Add callback argument.
2373 (sim_set_callbacks): Delete SIM_DESC argument.
2374 (sim_size): Ditto.
2375
2376Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2377
2378 * Makefile.in (SIM_OBJS): Add common modules.
2379
2380 * interp.c (sim_set_callbacks): Also set SD callback.
2381 (set_endianness, xfer_*, swap_*): Delete.
2382 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2383 Change to functions using sim-endian macros.
2384 (control_c, sim_stop): Delete, use common version.
2385 (simulate): Convert into.
2386 (sim_engine_run): This function.
2387 (sim_resume): Delete.
2388
2389 * interp.c (simulation): New variable - the simulator object.
2390 (sim_kind): Delete global - merged into simulation.
2391 (sim_load): Cleanup. Move PC assignment from here.
2392 (sim_create_inferior): To here.
2393
2394 * sim-main.h: New file.
2395 * interp.c (sim-main.h): Include.
2396
2397Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2398
2399 * configure: Regenerated to track ../common/aclocal.m4 changes.
2400
2401Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2402
2403 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2404
2405Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2406
2407 * gencode.c (build_instruction): DIV instructions: check
2408 for division by zero and integer overflow before using
2409 host's division operation.
2410
2411Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2412
2413 * Makefile.in (SIM_OBJS): Add sim-load.o.
2414 * interp.c: #include bfd.h.
2415 (target_byte_order): Delete.
2416 (sim_kind, myname, big_endian_p): New static locals.
2417 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2418 after argument parsing. Recognize -E arg, set endianness accordingly.
2419 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2420 load file into simulator. Set PC from bfd.
2421 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2422 (set_endianness): Use big_endian_p instead of target_byte_order.
2423
2424Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2425
2426 * interp.c (sim_size): Delete prototype - conflicts with
2427 definition in remote-sim.h. Correct definition.
2428
2429Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2430
2431 * configure: Regenerated to track ../common/aclocal.m4 changes.
2432 * config.in: Ditto.
2433
2434Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2435
2436 * interp.c (sim_open): New arg `kind'.
2437
2438 * configure: Regenerated to track ../common/aclocal.m4 changes.
2439
2440Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2441
2442 * configure: Regenerated to track ../common/aclocal.m4 changes.
2443
2444Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2445
2446 * interp.c (sim_open): Set optind to 0 before calling getopt.
2447
2448Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2449
2450 * configure: Regenerated to track ../common/aclocal.m4 changes.
2451
2452Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2453
2454 * interp.c : Replace uses of pr_addr with pr_uword64
2455 where the bit length is always 64 independent of SIM_ADDR.
2456 (pr_uword64) : added.
2457
2458Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2459
2460 * configure: Re-generate.
2461
2462Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2463
2464 * configure: Regenerate to track ../common/aclocal.m4 changes.
2465
2466Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2467
2468 * interp.c (sim_open): New SIM_DESC result. Argument is now
2469 in argv form.
2470 (other sim_*): New SIM_DESC argument.
2471
2472Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2473
2474 * interp.c: Fix printing of addresses for non-64-bit targets.
2475 (pr_addr): Add function to print address based on size.
2476
2477Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2478
2479 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2480
2481Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2482
2483 * gencode.c (build_mips16_operands): Correct computation of base
2484 address for extended PC relative instruction.
2485
2486Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2487
2488 * interp.c (mips16_entry): Add support for floating point cases.
2489 (SignalException): Pass floating point cases to mips16_entry.
2490 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2491 registers.
2492 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2493 or fmt_word.
2494 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2495 and then set the state to fmt_uninterpreted.
2496 (COP_SW): Temporarily set the state to fmt_word while calling
2497 ValueFPR.
2498
2499Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2500
2501 * gencode.c (build_instruction): The high order may be set in the
2502 comparison flags at any ISA level, not just ISA 4.
2503
2504Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2505
2506 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2507 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2508 * configure.in: sinclude ../common/aclocal.m4.
2509 * configure: Regenerated.
2510
2511Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2512
2513 * configure: Rebuild after change to aclocal.m4.
2514
2515Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2516
2517 * configure configure.in Makefile.in: Update to new configure
2518 scheme which is more compatible with WinGDB builds.
2519 * configure.in: Improve comment on how to run autoconf.
2520 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2521 * Makefile.in: Use autoconf substitution to install common
2522 makefile fragment.
2523
2524Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2525
2526 * gencode.c (build_instruction): Use BigEndianCPU instead of
2527 ByteSwapMem.
2528
2529Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2530
2531 * interp.c (sim_monitor): Make output to stdout visible in
2532 wingdb's I/O log window.
2533
2534Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2535
2536 * support.h: Undo previous change to SIGTRAP
2537 and SIGQUIT values.
2538
2539Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2540
2541 * interp.c (store_word, load_word): New static functions.
2542 (mips16_entry): New static function.
2543 (SignalException): Look for mips16 entry and exit instructions.
2544 (simulate): Use the correct index when setting fpr_state after
2545 doing a pending move.
2546
2547Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2548
2549 * interp.c: Fix byte-swapping code throughout to work on
2550 both little- and big-endian hosts.
2551
2552Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2553
2554 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2555 with gdb/config/i386/xm-windows.h.
2556
2557Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2558
2559 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2560 that messes up arithmetic shifts.
2561
2562Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2563
2564 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2565 SIGTRAP and SIGQUIT for _WIN32.
2566
2567Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2568
2569 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2570 force a 64 bit multiplication.
2571 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2572 destination register is 0, since that is the default mips16 nop
2573 instruction.
2574
2575Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2576
2577 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2578 (build_endian_shift): Don't check proc64.
2579 (build_instruction): Always set memval to uword64. Cast op2 to
2580 uword64 when shifting it left in memory instructions. Always use
2581 the same code for stores--don't special case proc64.
2582
2583 * gencode.c (build_mips16_operands): Fix base PC value for PC
2584 relative operands.
2585 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2586 jal instruction.
2587 * interp.c (simJALDELAYSLOT): Define.
2588 (JALDELAYSLOT): Define.
2589 (INDELAYSLOT, INJALDELAYSLOT): Define.
2590 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2591
2592Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2593
2594 * interp.c (sim_open): add flush_cache as a PMON routine
2595 (sim_monitor): handle flush_cache by ignoring it
2596
2597Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2598
2599 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2600 BigEndianMem.
2601 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2602 (BigEndianMem): Rename to ByteSwapMem and change sense.
2603 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2604 BigEndianMem references to !ByteSwapMem.
2605 (set_endianness): New function, with prototype.
2606 (sim_open): Call set_endianness.
2607 (sim_info): Use simBE instead of BigEndianMem.
2608 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2609 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2610 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2611 ifdefs, keeping the prototype declaration.
2612 (swap_word): Rewrite correctly.
2613 (ColdReset): Delete references to CONFIG. Delete endianness related
2614 code; moved to set_endianness.
2615
2616Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2617
2618 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2619 * interp.c (CHECKHILO): Define away.
2620 (simSIGINT): New macro.
2621 (membank_size): Increase from 1MB to 2MB.
2622 (control_c): New function.
2623 (sim_resume): Rename parameter signal to signal_number. Add local
2624 variable prev. Call signal before and after simulate.
2625 (sim_stop_reason): Add simSIGINT support.
2626 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2627 functions always.
2628 (sim_warning): Delete call to SignalException. Do call printf_filtered
2629 if logfh is NULL.
2630 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2631 a call to sim_warning.
2632
2633Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2634
2635 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2636 16 bit instructions.
2637
2638Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2639
2640 Add support for mips16 (16 bit MIPS implementation):
2641 * gencode.c (inst_type): Add mips16 instruction encoding types.
2642 (GETDATASIZEINSN): Define.
2643 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2644 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2645 mtlo.
2646 (MIPS16_DECODE): New table, for mips16 instructions.
2647 (bitmap_val): New static function.
2648 (struct mips16_op): Define.
2649 (mips16_op_table): New table, for mips16 operands.
2650 (build_mips16_operands): New static function.
2651 (process_instructions): If PC is odd, decode a mips16
2652 instruction. Break out instruction handling into new
2653 build_instruction function.
2654 (build_instruction): New static function, broken out of
2655 process_instructions. Check modifiers rather than flags for SHIFT
2656 bit count and m[ft]{hi,lo} direction.
2657 (usage): Pass program name to fprintf.
2658 (main): Remove unused variable this_option_optind. Change
2659 ``*loptarg++'' to ``loptarg++''.
2660 (my_strtoul): Parenthesize && within ||.
2661 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2662 (simulate): If PC is odd, fetch a 16 bit instruction, and
2663 increment PC by 2 rather than 4.
2664 * configure.in: Add case for mips16*-*-*.
2665 * configure: Rebuild.
2666
2667Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2668
2669 * interp.c: Allow -t to enable tracing in standalone simulator.
2670 Fix garbage output in trace file and error messages.
2671
2672Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2673
2674 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2675 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2676 * configure.in: Simplify using macros in ../common/aclocal.m4.
2677 * configure: Regenerated.
2678 * tconfig.in: New file.
2679
2680Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2681
2682 * interp.c: Fix bugs in 64-bit port.
2683 Use ansi function declarations for msvc compiler.
2684 Initialize and test file pointer in trace code.
2685 Prevent duplicate definition of LAST_EMED_REGNUM.
2686
2687Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2688
2689 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2690
2691Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2692
2693 * interp.c (SignalException): Check for explicit terminating
2694 breakpoint value.
2695 * gencode.c: Pass instruction value through SignalException()
2696 calls for Trap, Breakpoint and Syscall.
2697
2698Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2699
2700 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2701 only used on those hosts that provide it.
2702 * configure.in: Add sqrt() to list of functions to be checked for.
2703 * config.in: Re-generated.
2704 * configure: Re-generated.
2705
2706Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2707
2708 * gencode.c (process_instructions): Call build_endian_shift when
2709 expanding STORE RIGHT, to fix swr.
2710 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2711 clear the high bits.
2712 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2713 Fix float to int conversions to produce signed values.
2714
2715Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2716
2717 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2718 (process_instructions): Correct handling of nor instruction.
2719 Correct shift count for 32 bit shift instructions. Correct sign
2720 extension for arithmetic shifts to not shift the number of bits in
2721 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2722 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2723 Fix madd.
2724 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2725 It's OK to have a mult follow a mult. What's not OK is to have a
2726 mult follow an mfhi.
2727 (Convert): Comment out incorrect rounding code.
2728
2729Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2730
2731 * interp.c (sim_monitor): Improved monitor printf
2732 simulation. Tidied up simulator warnings, and added "--log" option
2733 for directing warning message output.
2734 * gencode.c: Use sim_warning() rather than WARNING macro.
2735
2736Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2737
2738 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2739 getopt1.o, rather than on gencode.c. Link objects together.
2740 Don't link against -liberty.
2741 (gencode.o, getopt.o, getopt1.o): New targets.
2742 * gencode.c: Include <ctype.h> and "ansidecl.h".
2743 (AND): Undefine after including "ansidecl.h".
2744 (ULONG_MAX): Define if not defined.
2745 (OP_*): Don't define macros; now defined in opcode/mips.h.
2746 (main): Call my_strtoul rather than strtoul.
2747 (my_strtoul): New static function.
2748
2749Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2750
2751 * gencode.c (process_instructions): Generate word64 and uword64
2752 instead of `long long' and `unsigned long long' data types.
2753 * interp.c: #include sysdep.h to get signals, and define default
2754 for SIGBUS.
2755 * (Convert): Work around for Visual-C++ compiler bug with type
2756 conversion.
2757 * support.h: Make things compile under Visual-C++ by using
2758 __int64 instead of `long long'. Change many refs to long long
2759 into word64/uword64 typedefs.
2760
2761Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2762
2763 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2764 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2765 (docdir): Removed.
2766 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2767 (AC_PROG_INSTALL): Added.
2768 (AC_PROG_CC): Moved to before configure.host call.
2769 * configure: Rebuilt.
2770
2771Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2772
2773 * configure.in: Define @SIMCONF@ depending on mips target.
2774 * configure: Rebuild.
2775 * Makefile.in (run): Add @SIMCONF@ to control simulator
2776 construction.
2777 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2778 * interp.c: Remove some debugging, provide more detailed error
2779 messages, update memory accesses to use LOADDRMASK.
2780
2781Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2782
2783 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2784 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2785 stamp-h.
2786 * configure: Rebuild.
2787 * config.in: New file, generated by autoheader.
2788 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2789 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2790 HAVE_ANINT and HAVE_AINT, as appropriate.
2791 * Makefile.in (run): Use @LIBS@ rather than -lm.
2792 (interp.o): Depend upon config.h.
2793 (Makefile): Just rebuild Makefile.
2794 (clean): Remove stamp-h.
2795 (mostlyclean): Make the same as clean, not as distclean.
2796 (config.h, stamp-h): New targets.
2797
2798Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2799
2800 * interp.c (ColdReset): Fix boolean test. Make all simulator
2801 globals static.
2802
2803Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2804
2805 * interp.c (xfer_direct_word, xfer_direct_long,
2806 swap_direct_word, swap_direct_long, xfer_big_word,
2807 xfer_big_long, xfer_little_word, xfer_little_long,
2808 swap_word,swap_long): Added.
2809 * interp.c (ColdReset): Provide function indirection to
2810 host<->simulated_target transfer routines.
2811 * interp.c (sim_store_register, sim_fetch_register): Updated to
2812 make use of indirected transfer routines.
2813
2814Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2815
2816 * gencode.c (process_instructions): Ensure FP ABS instruction
2817 recognised.
2818 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2819 system call support.
2820
2821Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2822
2823 * interp.c (sim_do_command): Complain if callback structure not
2824 initialised.
2825
2826Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2827
2828 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2829 support for Sun hosts.
2830 * Makefile.in (gencode): Ensure the host compiler and libraries
2831 used for cross-hosted build.
2832
2833Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2834
2835 * interp.c, gencode.c: Some more (TODO) tidying.
2836
2837Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2838
2839 * gencode.c, interp.c: Replaced explicit long long references with
2840 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2841 * support.h (SET64LO, SET64HI): Macros added.
2842
2843Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2844
2845 * configure: Regenerate with autoconf 2.7.
2846
2847Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2848
2849 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2850 * support.h: Remove superfluous "1" from #if.
2851 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2852
2853Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2854
2855 * interp.c (StoreFPR): Control UndefinedResult() call on
2856 WARN_RESULT manifest.
2857
2858Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2859
2860 * gencode.c: Tidied instruction decoding, and added FP instruction
2861 support.
2862
2863 * interp.c: Added dineroIII, and BSD profiling support. Also
2864 run-time FP handling.
2865
2866Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2867
2868 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2869 gencode.c, interp.c, support.h: created.
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