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* interp.c (sim_monitor): Handle Densan monitor outbyte
[deliverable/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
e0e0fc76
MA		 1Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2
3 * interp.c (sim_monitor): Handle Densan monitor outbyte
4 and inbyte functions.
5
76ef4165
FL		 61997-12-29 Felix Lee <flee@cygnus.com>
7
8 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
9
10Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
11
12 * Makefile.in (tmp-igen): Arrange for $zero to always be
13 reset to zero after every instruction.
14
9c8ec16d
AC		 15Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
16
17 * configure: Regenerated to track ../common/aclocal.m4 changes.
18 * config.in: Ditto.
19
255cbbf1 20start-sanitize-vr5400
b17d2d14
AC		 21Sat Dec 13 15:18:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
22
23 * vr5400.igen (Low32Bits, High32Bits): Sign extend extracted 32
24 bit values.
25
26end-sanitize-vr5400
27start-sanitize-vr5400
255cbbf1
JL		 28Fri Dec 12 12:26:07 1997 Jeffrey A Law (law@cygnus.com)
29
30 * configure.in (sim_igen_filter): Multi-sim vr5000 - vr5000 or
31 vr5400 with the vr5000 as the default.
32
33end-sanitize-vr5400
23850e92
JL		 34Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
35
36 * mips.igen (MSUB): Fix to work like MADD.
37 * gencode.c (MSUB): Similarly.
38
c02ed6a8
AC		 39start-sanitize-vr5400
40Tue Dec 9 12:02:12 1997 Andrew Cagney <cagney@b1.cygnus.com>
41
42 * configure.in (sim_igen_filter): Multi-sim vr5400 - vr5000 or
43 vr5400.
44
45end-sanitize-vr5400
6e51f990
DE		 46Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
47
48 * configure: Regenerated to track ../common/aclocal.m4 changes.
49
35c246c9
AC		 50Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
51
52 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
53
54start-sanitize-vr5400
0d5d0d10 55 * mdmx.igen (value_vr): Correct sim_io_eprintf format argument.
0931ce5a 56 (value_cc, store_cc): Implement.
0d5d0d10 57
35c246c9
AC		 58 * sim-main.h: Add 8*3*8 bit accumulator.
59
60 * vr5400.igen: Move mdmx instructins from here
61 * mdmx.igen: To here - new file. Add/fix missing instructions.
62 * mips.igen: Include mdmx.igen.
0931ce5a 63 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
35c246c9 64
c02ed6a8 65end-sanitize-vr5400
58fb5d0a
AC		 66Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
67
68 * sim-main.h (sim-fpu.h): Include.
69
70 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
71 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
72 using host independant sim_fpu module.
73
a09a30d2
AC		 74Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
75
232156de
AC		 76 * interp.c (signal_exception): Report internal errors with SIGABRT
77 not SIGQUIT.
a09a30d2 78
232156de
AC		 79 * sim-main.h (C0_CONFIG): New register.
80 (signal.h): No longer include.
81
82 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
a09a30d2 83
486740ce
DE		 84Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
85
86 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
87
f23e93da
AC		 88Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
89
90 * mips.igen: Tag vr5000 instructions.
91 (ANDI): Was missing mipsIV model, fix assembler syntax.
92 (do_c_cond_fmt): New function.
93 (C.cond.fmt): Handle mips I-III which do not support CC field
94 separatly.
95 (bc1): Handle mips IV which do not have a delaed FCC separatly.
96 (SDR): Mask paddr when BigEndianMem, not the converse as specified
97 in IV3.2 spec.
98 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
99 vr5000 which saves LO in a GPR separatly.
100
101 * configure.in (enable-sim-igen): For vr5000, select vr5000
102 specific instructions.
103 * configure: Re-generate.
104
105Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
106
107 * Makefile.in (SIM_OBJS): Add sim-fpu module.
108
109 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
110 fmt_uninterpreted_64 bit cases to switch. Convert to
111 fmt_formatted,
112
113 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
114
115 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
116 as specified in IV3.2 spec.
117 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
118
030843d7
AC		 119Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
120
121 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
122 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
123 (start-sanitize-r5900):
124 (LWXC1, SWXC1): Delete from r5900 instruction set.
125 (end-sanitize-r5900):
126 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
a94c5493 127 PENDING_FILL versions of instructions. Simplify.
030843d7
AC		 128 (X): New function.
129 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
130 instructions.
a94c5493
AC		 131 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
132 a signed value.
030843d7
AC		 133 (MTHI, MFHI): Disable code checking HI-LO.
134
135 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
136 global.
137 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
138
7ce8b917
AC		 139Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
140
95469ceb
AC		 141 * gencode.c (build_mips16_operands): Replace IPC with cia.
142
143 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
144 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
145 IPC to `cia'.
146 (UndefinedResult): Replace function with macro/function
147 combination.
148 (sim_engine_run): Don't save PC in IPC.
149
150 * sim-main.h (IPC): Delete.
151
152 start-sanitize-vr5400
153 * vr5400.igen (vr): Add missing cia argument to value_fpr.
154 (do_select): Rename function select.
155 end-sanitize-vr5400
156
7ce8b917
AC		 157 * interp.c (signal_exception, store_word, load_word,
158 address_translation, load_memory, store_memory, cache_op,
159 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
95469ceb
AC		 160 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
161 current instruction address - cia - argument.
7ce8b917
AC		 162 (sim_read, sim_write): Call address_translation directly.
163 (sim_engine_run): Rename variable vaddr to cia.
95469ceb
AC		 164 (signal_exception): Pass cia to sim_monitor
165
7ce8b917
AC		 166 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
167 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
168 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
169
170 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
171 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
172 SIM_ASSERT.
173
174 * interp.c (signal_exception): Pass restart address to
175 sim_engine_restart.
176
177 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
178 idecode.o): Add dependency.
179
180 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
181 Delete definitions
182 (DELAY_SLOT): Update NIA not PC with branch address.
183 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
184
185 * mips.igen: Use CIA not PC in branch calculations.
186 (illegal): Call SignalException.
187 (BEQ, ADDIU): Fix assembler.
188
63be8feb
AC		 189Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
190
44b8585a
AC		 191 * m16.igen (JALX): Was missing.
192
193 * configure.in (enable-sim-igen): New configuration option.
194 * configure: Re-generate.
195
63be8feb
AC		 196 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
197
198 * interp.c (load_memory, store_memory): Delete parameter RAW.
199 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
200 bypassing {load,store}_memory.
201
202 * sim-main.h (ByteSwapMem): Delete definition.
203
204 * Makefile.in (SIM_OBJS): Add sim-memopt module.
205
206 * interp.c (sim_do_command, sim_commands): Delete mips specific
207 commands. Handled by module sim-options.
208
209 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
210 (WITH_MODULO_MEMORY): Define.
211
212 * interp.c (sim_info): Delete code printing memory size.
213
214 * interp.c (mips_size): Nee sim_size, delete function.
215 (power2): Delete.
216 (monitor, monitor_base, monitor_size): Delete global variables.
217 (sim_open, sim_close): Delete code creating monitor and other
218 memory regions. Use sim-memopts module, via sim_do_commandf, to
219 manage memory regions.
220 (load_memory, store_memory): Use sim-core for memory model.
221
222 * interp.c (address_translation): Delete all memory map code
223 except line forcing 32 bit addresses.
224
22de994d
AC		 225Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
226
227 * sim-main.h (WITH_TRACE): Delete definition. Enables common
228 trace options.
229
230 * interp.c (logfh, logfile): Delete globals.
231 (sim_open, sim_close): Delete code opening & closing log file.
232 (mips_option_handler): Delete -l and -n options.
233 (OPTION mips_options): Ditto.
234
235 * interp.c (OPTION mips_options): Rename option trace to dinero.
236 (mips_option_handler): Update.
237
525d929e
AC		 238Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
239
240 * interp.c (fetch_str): New function.
241 (sim_monitor): Rewrite using sim_read & sim_write.
242 (sim_open): Check magic number.
243 (sim_open): Write monitor vectors into memory using sim_write.
244 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
245 (sim_read, sim_write): Simplify - transfer data one byte at a
246 time.
247 (load_memory, store_memory): Clarify meaning of parameter RAW.
248
249 * sim-main.h (isHOST): Defete definition.
250 (isTARGET): Mark as depreciated.
251 (address_translation): Delete parameter HOST.
252
253 * interp.c (address_translation): Delete parameter HOST.
254
6205f379
GRK		 255start-sanitize-tx49
256Wed Oct 29 14:21:32 1997 Gavin Koch <gavin@cygnus.com>
257
258 * gencode.c: Add tx49 configury and insns.
259 * configure.in: Add tx49 configury.
260 * configure: Update.
261
262end-sanitize-tx49
01b9cd49
AC		 263Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
264
265 * mips.igen:
266
267 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
268 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
269
89d09738
AC		 270Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
271
272 * mips.igen: Add model filter field to records.
273
16bd5d6e
AC		 274Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
275
276 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
277
278 interp.c (sim_engine_run): Do not compile function sim_engine_run
279 when WITH_IGEN == 1.
280
281 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
282 target architecture.
283
284 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
285 igen. Replace with configuration variables sim_igen_flags /
286 sim_m16_flags.
287
16bd5d6e 288 start-sanitize-r5900
8c31916d
AC		 289 * r5900.igen: New file. Copy r5900 insns here.
290 end-sanitize-r5900
16bd5d6e 291 start-sanitize-vr5400
58fb5d0a 292 * vr5400.igen: New file.
255cbbf1 293 end-sanitize-vr5400
16bd5d6e
AC		 294 * m16.igen: New file. Copy mips16 insns here.
295 * mips.igen: From here.
296
90ad43b2
AC		 297Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
298
299 start-sanitize-vr5400
300 * mips.igen: Tag all mipsIV instructions with vr5400 model.
301
302 * configure.in: Add mips64vr5400 target.
303 * configure: Re-generate.
304
305 end-sanitize-vr5400
306 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
307 to top.
308 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
309
635ae9cb
GRK		 310Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
311
312 * gencode.c (build_instruction): Follow sim_write's lead in using
313 BigEndianMem instead of !ByteSwapMem.
314
122edc03
AC		 315Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
316
317 * configure.in (sim_gen): Dependent on target, select type of
318 generator. Always select old style generator.
319
320 configure: Re-generate.
321
322 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
323 targets.
324 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
325 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
326 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
327 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
328 SIM_@sim_gen@_*, set by autoconf.
329
dad6f1f3
AC		 330Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
331
332 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
333
334 * interp.c (ColdReset): Remove #ifdef HASFPU, check
335 CURRENT_FLOATING_POINT instead.
336
337 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
338 (address_translation): Raise exception InstructionFetch when
339 translation fails and isINSTRUCTION.
340
341 * interp.c (sim_open, sim_write, sim_monitor, store_word,
342 sim_engine_run): Change type of of vaddr and paddr to
343 address_word.
344 (address_translation, prefetch, load_memory, store_memory,
345 cache_op): Change type of vAddr and pAddr to address_word.
346
347 * gencode.c (build_instruction): Change type of vaddr and paddr to
348 address_word.
349
92ad193b
AC		 350Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
351
352 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
353 macro to obtain result of ALU op.
354
aa324b9b
AC		 355Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
356
357 * interp.c (sim_info): Call profile_print.
358
e2f8ffb7
AC		 359Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
360
361 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
362
363 * sim-main.h (WITH_PROFILE): Do not define, defined in
364 common/sim-config.h. Use sim-profile module.
365 (simPROFILE): Delete defintion.
366
367 * interp.c (PROFILE): Delete definition.
368 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
369 (sim_close): Delete code writing profile histogram.
370 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
371 Delete.
372 (sim_engine_run): Delete code profiling the PC.
373
fb5a2a3e
AC		 374Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
375
376 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
377
378 * interp.c (sim_monitor): Make register pointers of type
379 unsigned_word*.
380
381 * sim-main.h: Make registers of type unsigned_word not
382 signed_word.
383
ea985d24
AC		 384Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
385
386start-sanitize-r5900
387 * sim-main.h (BYTES_IN_MMI_REGS, ..., SUB_REG_FETCH, ..., GPR_SB,
388 ...): Move to sim-main.h
389
390end-sanitize-r5900
391 * interp.c (sync_operation): Rename from SyncOperation, make
392 global, add SD argument.
393 (prefetch): Rename from Prefetch, make global, add SD argument.
394 (decode_coproc): Make global.
395
396 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
397
398 * gencode.c (build_instruction): Generate DecodeCoproc not
399 decode_coproc calls.
400
401 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
402 (SizeFGR): Move to sim-main.h
403 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
404 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
405 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
406 sim-main.h.
407 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
408 FP_RM_TOMINF, GETRM): Move to sim-main.h.
409 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
410 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
411 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
412 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
413
414 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
415 exception.
416 (sim-alu.h): Include.
417 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
418 (sim_cia): Typedef to instruction_address.
419
284e759d
AC		 420Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
421
422 * Makefile.in (interp.o): Rename generated file engine.c to
423 oengine.c.
424
425 * interp.c: Update.
426
339fb149
AC		 427Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
428
429 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
430
8b70f837
AC		 431Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
432
433 * gencode.c (build_instruction): For "FPSQRT", output correct
434 number of arguments to Recip.
435
0c2c5f61
AC		 436Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
437
438 * Makefile.in (interp.o): Depends on sim-main.h
439
440 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
441
442 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
443 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
444 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
445 STATE, DSSTATE): Define
446 (GPR, FGRIDX, ..): Define.
447
448 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
449 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
450 (GPR, FGRIDX, ...): Delete macros.
451
452 * interp.c: Update names to match defines from sim-main.h
453
18c64df6
AC		 454Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
455
456 * interp.c (sim_monitor): Add SD argument.
457 (sim_warning): Delete. Replace calls with calls to
458 sim_io_eprintf.
459 (sim_error): Delete. Replace calls with sim_io_error.
460 (open_trace, writeout32, writeout16, getnum): Add SD argument.
461 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
462 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
463 argument.
464 (mips_size): Rename from sim_size. Add SD argument.
465
466 * interp.c (simulator): Delete global variable.
467 (callback): Delete global variable.
468 (mips_option_handler, sim_open, sim_write, sim_read,
469 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
470 sim_size,sim_monitor): Use sim_io_* not callback->*.
471 (sim_open): ZALLOC simulator struct.
472 (PROFILE): Do not define.
473
474Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
475
476 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
477 support.h with corresponding code.
478
479 * sim-main.h (word64, uword64), support.h: Move definition to
480 sim-main.h.
481 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
482
483 * support.h: Delete
484 * Makefile.in: Update dependencies
485 * interp.c: Do not include.
486
487Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
488
489 * interp.c (address_translation, load_memory, store_memory,
490 cache_op): Rename to from AddressTranslation et.al., make global,
491 add SD argument
492
493 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
494 CacheOp): Define.
495
496 * interp.c (SignalException): Rename to signal_exception, make
497 global.
498
499 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
500
501 * sim-main.h (SignalException, SignalExceptionInterrupt,
502 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
503 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
504 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
505 Define.
506
507 * interp.c, support.h: Use.
508
509Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
510
511 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
512 to value_fpr / store_fpr. Add SD argument.
513 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
514 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
515
516 * sim-main.h (ValueFPR, StoreFPR): Define.
517
518Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
519
520 * interp.c (sim_engine_run): Check consistency between configure
521 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
522 and HASFPU.
523
524 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
525 (mips_fpu): Configure WITH_FLOATING_POINT.
526 (mips_endian): Configure WITH_TARGET_ENDIAN.
527 * configure: Update.
528
529Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
530
531 * configure: Regenerated to track ../common/aclocal.m4 changes.
532
adf4739e
AC		 533start-sanitize-r5900
534Mon Aug 25 19:11:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
535
536 * interp.c (MAX_REG): Allow up-to 128 registers.
537 (LO1, HI1): Define value that matches REGISTER_NAMES in gdb.
538 (REGISTER_SA): Ditto.
539 (sim_open): Initialize register_widths for r5900 specific
540 registers.
541 (sim_fetch_register, sim_store_register): Check for request of
542 r5900 specific SA register. Check for request for hi 64 bits of
543 r5900 specific registers.
544
545end-sanitize-r5900
26b20b0a
BM		 546Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
547
548 * configure: Regenerated.
549
6eedf3f4
MA		 550Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
551
552 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
553
e63bc706
AC		 554Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
555
6eedf3f4
MA		 556 * gencode.c (print_igen_insn_models): Assume certain architectures
557 include all mips* instructions.
558 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
559 instruction.
560
e63bc706
AC		 561 * Makefile.in (tmp.igen): Add target. Generate igen input from
562 gencode file.
563
564 * gencode.c (FEATURE_IGEN): Define.
565 (main): Add --igen option. Generate output in igen format.
566 (process_instructions): Format output according to igen option.
567 (print_igen_insn_format): New function.
568 (print_igen_insn_models): New function.
569 (process_instructions): Only issue warnings and ignore
570 instructions when no FEATURE_IGEN.
571
eb2e3c85
AC		 572Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
573
574 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
575 MIPS targets.
576
92f91d1f
AC		 577Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
578
579 * configure: Regenerated to track ../common/aclocal.m4 changes.
580
581Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
582
583 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
584 SIM_RESERVED_BITS): Delete, moved to common.
585 (SIM_EXTRA_CFLAGS): Update.
586
794e9ac9
AC		 587Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
588
76a6247f 589 * configure.in: Configure non-strict memory alignment.
794e9ac9
AC		 590 * configure: Regenerated to track ../common/aclocal.m4 changes.
591
b45caf05
AC		 592Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
593
594 * configure: Regenerated to track ../common/aclocal.m4 changes.
595
596Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
597
598 * gencode.c (SDBBP,DERET): Added (3900) insns.
599 (RFE): Turn on for 3900.
600 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
601 (dsstate): Made global.
602 (SUBTARGET_R3900): Added.
603 (CANCELDELAYSLOT): New.
604 (SignalException): Ignore SystemCall rather than ignore and
605 terminate. Add DebugBreakPoint handling.
606 (decode_coproc): New insns RFE, DERET; and new registers Debug
607 and DEPC protected by SUBTARGET_R3900.
608 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
609 bits explicitly.
610 * Makefile.in,configure.in: Add mips subtarget option.
611 * configure: Update.
612
7afa8d4e
GRK		 613Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
614
615 * gencode.c: Add r3900 (tx39).
616
617start-sanitize-tx19
618 * gencode.c: Fix some configuration problems by improving
619 the relationship between tx19 and tx39.
620end-sanitize-tx19
621
667065d0
GRK		 622Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
623
624 * gencode.c (build_instruction): Don't need to subtract 4 for
625 JALR, just 2.
626
9cb8397f
GRK		 627Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
628
629 * interp.c: Correct some HASFPU problems.
630
a2ab5e65
AC		 631Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
632
633 * configure: Regenerated to track ../common/aclocal.m4 changes.
634
11ac69e0
AC		 635Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
636
637 * interp.c (mips_options): Fix samples option short form, should
638 be `x'.
639
972f3a34
AC		 640Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
641
642 * interp.c (sim_info): Enable info code. Was just returning.
643
9eeaaefa
AC		 644Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
645
646 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
647 MFC0.
648
c31c13b4
AC		 649Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
650
651 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
652 constants.
653 (build_instruction): Ditto for LL.
654
b637f306
GRK		 655start-sanitize-tx19
656Sun Sep 7 16:05:46 1997 Gavin Koch <gavin@cygnus.com>
657
658 * mips/configure.in, mips/gencode: Add tx19/r1900.
659
660end-sanitize-tx19
6fea4763
DE		 661Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
662
663 * configure: Regenerated to track ../common/aclocal.m4 changes.
664
52352d38
AC		 665start-sanitize-r5900
666Mon Sep 1 18:43:30 1997 Andrew Cagney <cagney@b1.cygnus.com>
667
668 * gencode.c (build_instruction): For "pabsw" and "pabsh", check
669 for overflow due to ABS of MININT, set result to MAXINT.
670 (build_instruction): For "psrlvw", signextend bit 31.
671
672end-sanitize-r5900
88117054
AC		 673Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
674
675 * configure: Regenerated to track ../common/aclocal.m4 changes.
676 * config.in: Ditto.
677
fafce69a
AC		 678Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
679
680 * interp.c (sim_open): Add call to sim_analyze_program, update
681 call to sim_config.
682
7230ff0f
AC		 683Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
684
685 * interp.c (sim_kill): Delete.
fafce69a
AC		 686 (sim_create_inferior): Add ABFD argument. Set PC from same.
687 (sim_load): Move code initializing trap handlers from here.
688 (sim_open): To here.
689 (sim_load): Delete, use sim-hload.c.
690
691 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
7230ff0f 692
247fccde
AC		 693Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
694
695 * configure: Regenerated to track ../common/aclocal.m4 changes.
696 * config.in: Ditto.
697
698Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
699
700 * interp.c (sim_open): Add ABFD argument.
701 (sim_load): Move call to sim_config from here.
702 (sim_open): To here. Check return status.
703
704start-sanitize-r5900
705 * gencode.c (build_instruction): Do not define x8000000000000000,
706 x7FFFFFFFFFFFFFFF, or xFFFFFFFF80000000.
707
708end-sanitize-r5900
709start-sanitize-r5900
710Mon Jul 28 19:49:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
711
712 * gencode.c (build_instruction): For "pdivw", "pdivbw" and
713 "pdivuw" check for overflow due to signed divide by -1.
714
715end-sanitize-r5900
c12e2e4c
GRK		 716Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
717
718 * gencode.c (build_instruction): Two arg MADD should
719 not assign result to $0.
720
1e851d2c
AC		 721start-sanitize-r5900
722Thu Jul 10 11:58:48 1997 Andrew Cagney <cagney@critters.cygnus.com>
723
724 * gencode.c (build_instruction): For "ppac5" use unsigned
725 arrithmetic so that the sign bit doesn't smear when right shifted.
726 (build_instruction): For "pdiv" perform sign extension when
727 storing results in HI and LO.
728 (build_instructions): For "pdiv" and "pdivbw" check for
729 divide-by-zero.
730 (build_instruction): For "pmfhl.slw" update hi part of dest
731 register as well as low part.
732 (build_instruction): For "pmfhl" portably handle long long values.
733 (build_instruction): For "pmfhl.sh" correctly negative values.
734 Store half words 2 and three in the correct place.
735 (build_instruction): For "psllvw", sign extend value after shift.
736
737end-sanitize-r5900
738Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
739
740 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
741 * sim/mips/configure.in: Regenerate.
742
743Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
744
745 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
746 signed8, unsigned8 et.al. types.
747
748start-sanitize-r5900
749 * gencode.c (build_instruction): For PMULTU* do not sign extend
750 registers. Make generated code easier to debug.
751
752end-sanitize-r5900
753 * interp.c (SUB_REG_FETCH): Handle both little and big endian
754 hosts when selecting subreg.
755
756start-sanitize-r5900
757Tue Jul 8 18:07:20 1997 Andrew Cagney <cagney@andros.cygnus.com>
758
759 * gencode.c (type_for_data_len): For 32bit operations concerned
760 with overflow, perform op using 64bits.
761 (build_instruction): For PADD, always compute operation using type
762 returned by type_for_data_len.
763 (build_instruction): For PSUBU, when overflow, saturate to zero as
764 actually underflow.
765
766end-sanitize-r5900
ae19b07b
JL		 767Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
768
649625bb 769start-sanitize-r5900
64435234
JL		 770 * gencode.c (build_instruction): Handle "pext5" according to
771 version 1.95 of the r5900 ISA.
772
649625bb
JL		 773 * gencode.c (build_instruction): Handle "ppac5" according to
774 version 1.95 of the r5900 ISA.
649625bb 775
1e851d2c 776end-sanitize-r5900
05d1322f
JL		 777 * interp.c (sim_engine_run): Reset the ZERO register to zero
778 regardless of FEATURE_WARN_ZERO.
ae19b07b
JL		 779 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
780
781Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
782
783 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
784 (SignalException): For BreakPoints ignore any mode bits and just
785 save the PC.
786 (SignalException): Always set the CAUSE register.
787
56e7c849
AC		 788Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
789
790 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
791 exception has been taken.
792
793 * interp.c: Implement the ERET and mt/f sr instructions.
794
ae19b07b 795start-sanitize-r5900
56e7c849
AC		 796Mon Jun 2 23:28:19 1997 Andrew Cagney <cagney@b1.cygnus.com>
797
798 * gencode.c (build_instruction): For paddu, extract unsigned
799 sub-fields.
800
801 * gencode.c (build_instruction): Saturate padds instead of padd
802 instructions.
803
804end-sanitize-r5900
805Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
806
807 * interp.c (SignalException): Don't bother restarting an
808 interrupt.
809
810Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
811
812 * interp.c (SignalException): Really take an interrupt.
813 (interrupt_event): Only deliver interrupts when enabled.
814
815Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
816
817 * interp.c (sim_info): Only print info when verbose.
818 (sim_info) Use sim_io_printf for output.
819
2f2e6c5d
AC		 820Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
821
822 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
823 mips architectures.
824
825Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
826
827 * interp.c (sim_do_command): Check for common commands if a
828 simulator specific command fails.
829
d3d2a9f7
GRK		 830Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
831
832 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
833 and simBE when DEBUG is defined.
834
50a2a691
AC		 835Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
836
837 * interp.c (interrupt_event): New function. Pass exception event
838 onto exception handler.
839
840 * configure.in: Check for stdlib.h.
841 * configure: Regenerate.
842
843 * gencode.c (build_instruction): Add UNUSED attribute to tempS
844 variable declaration.
845 (build_instruction): Initialize memval1.
846 (build_instruction): Add UNUSED attribute to byte, bigend,
847 reverse.
848 (build_operands): Ditto.
849
850 * interp.c: Fix GCC warnings.
851 (sim_get_quit_code): Delete.
852
853 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
854 * Makefile.in: Ditto.
855 * configure: Re-generate.
856
857 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
858
859Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
860
861 * interp.c (mips_option_handler): New function parse argumes using
862 sim-options.
863 (myname): Replace with STATE_MY_NAME.
864 (sim_open): Delete check for host endianness - performed by
865 sim_config.
866 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
867 (sim_open): Move much of the initialization from here.
868 (sim_load): To here. After the image has been loaded and
869 endianness set.
870 (sim_open): Move ColdReset from here.
871 (sim_create_inferior): To here.
872 (sim_open): Make FP check less dependant on host endianness.
873
874 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
875 run.
876 * interp.c (sim_set_callbacks): Delete.
877
878 * interp.c (membank, membank_base, membank_size): Replace with
879 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
880 (sim_open): Remove call to callback->init. gdb/run do this.
881
882 * interp.c: Update
883
884 * sim-main.h (SIM_HAVE_FLATMEM): Define.
885
886 * interp.c (big_endian_p): Delete, replaced by
887 current_target_byte_order.
888
889Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
890
891 * interp.c (host_read_long, host_read_word, host_swap_word,
892 host_swap_long): Delete. Using common sim-endian.
893 (sim_fetch_register, sim_store_register): Use H2T.
894 (pipeline_ticks): Delete. Handled by sim-events.
895 (sim_info): Update.
896 (sim_engine_run): Update.
897
898Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
899
900 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
901 reason from here.
902 (SignalException): To here. Signal using sim_engine_halt.
903 (sim_stop_reason): Delete, moved to common.
904
905Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
906
907 * interp.c (sim_open): Add callback argument.
908 (sim_set_callbacks): Delete SIM_DESC argument.
909 (sim_size): Ditto.
910
2e61a3ad
AC		 911Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
912
913 * Makefile.in (SIM_OBJS): Add common modules.
914
915 * interp.c (sim_set_callbacks): Also set SD callback.
916 (set_endianness, xfer_*, swap_*): Delete.
917 (host_read_word, host_read_long, host_swap_word, host_swap_long):
918 Change to functions using sim-endian macros.
919 (control_c, sim_stop): Delete, use common version.
920 (simulate): Convert into.
921 (sim_engine_run): This function.
922 (sim_resume): Delete.
923
924 * interp.c (simulation): New variable - the simulator object.
925 (sim_kind): Delete global - merged into simulation.
926 (sim_load): Cleanup. Move PC assignment from here.
927 (sim_create_inferior): To here.
928
929 * sim-main.h: New file.
930 * interp.c (sim-main.h): Include.
931
932Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
933
934 * configure: Regenerated to track ../common/aclocal.m4 changes.
935
3be0e228
DE		 936Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
937
938 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
939
d654ba0a
GRK		 940Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
941
942 * gencode.c (build_instruction): DIV instructions: check
943 for division by zero and integer overflow before using
944 host's division operation.
945
9d52bcb7
DE		 946Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
947
948 * Makefile.in (SIM_OBJS): Add sim-load.o.
949 * interp.c: #include bfd.h.
950 (target_byte_order): Delete.
951 (sim_kind, myname, big_endian_p): New static locals.
952 (sim_open): Set sim_kind, myname. Move call to set_endianness to
953 after argument parsing. Recognize -E arg, set endianness accordingly.
954 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
955 load file into simulator. Set PC from bfd.
956 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
957 (set_endianness): Use big_endian_p instead of target_byte_order.
958
87e43259
AC		 959Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
960
961 * interp.c (sim_size): Delete prototype - conflicts with
962 definition in remote-sim.h. Correct definition.
963
964Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
965
966 * configure: Regenerated to track ../common/aclocal.m4 changes.
967 * config.in: Ditto.
968
fbda74b1
DE		 969Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
970
8a7c3105
DE		 971 * interp.c (sim_open): New arg `kind'.
972
fbda74b1
DE		 973 * configure: Regenerated to track ../common/aclocal.m4 changes.
974
a35e91c3
AC		 975Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
976
977 * configure: Regenerated to track ../common/aclocal.m4 changes.
978
979Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
980
981 * interp.c (sim_open): Set optind to 0 before calling getopt.
982
983Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
984
985 * configure: Regenerated to track ../common/aclocal.m4 changes.
986
6efa34d8
GRK		 987Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
988
989 * interp.c : Replace uses of pr_addr with pr_uword64
990 where the bit length is always 64 independent of SIM_ADDR.
991 (pr_uword64) : added.
992
a77aa7ec
AC		 993Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
994
995 * configure: Re-generate.
996
601fb8ae
MM		 997Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
998
999 * configure: Regenerate to track ../common/aclocal.m4 changes.
1000
53b9417e
DE		 1001Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
1002
1003 * interp.c (sim_open): New SIM_DESC result. Argument is now
1004 in argv form.
1005 (other sim_*): New SIM_DESC argument.
1006
1007start-sanitize-r5900
1008Wed Feb 26 18:32:21 1997 Gavin Koch <gavin@cygnus.com>
1009
1010 * gencode.c (POP_AND,POP_OR,POP_NOR,POP_XOR):
1011 Change values to avoid overloading DOUBLEWORD which is tested
1012 for all insns.
1013 * gencode.c: reinstate "offending code".
53b9417e 1014
56e7c849 1015end-sanitize-r5900
53b9417e
DE		 1016Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
1017
1018 * interp.c: Fix printing of addresses for non-64-bit targets.
1019 (pr_addr): Add function to print address based on size.
1020start-sanitize-r5900
1021 * gencode.c: #ifdef out offending code until a permanent fix
1022 can be added. Code is causing build errors for non-5900 mips targets.
1023end-sanitize-r5900
1024
1025start-sanitize-r5900
1026Thu Feb 20 10:40:24 1997 Gavin Koch <gavin@cetus.cygnus.com>
1027
1028 * gencode.c (process_instructions): Correct test for ISA dependent
1029 architecture bits in isa field of MIPS_DECODE.
1030
1031end-sanitize-r5900
7e05106d
MA		 1032Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
1033
1034 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
1035
2d18fbc6 1036start-sanitize-r5900
53b9417e 1037Tue Feb 18 17:03:47 1997 Gavin Koch <gavin@cygnus.com>
2d18fbc6
GRK		 1038
1039 * gencode.c (MIPS_DECODE): Correct instruction feature flags for
1040 PMADDUW.
1041
1042end-sanitize-r5900
1043Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
1044
1045 * gencode.c (build_mips16_operands): Correct computation of base
1046 address for extended PC relative instruction.
1047
276c2d7d
GRK		 1048start-sanitize-r5900
1049Fri Feb 7 11:12:44 1997 Gavin Koch <gavin@cygnus.com>
2d18fbc6
GRK		 1050
1051 * Makefile.in, configure, configure.in, gencode.c,
1052 interp.c, support.h: add r5900.
1053
276c2d7d 1054end-sanitize-r5900
da0bce9c
ILT		 1055Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
1056
1057 * interp.c (mips16_entry): Add support for floating point cases.
1058 (SignalException): Pass floating point cases to mips16_entry.
1059 (ValueFPR): Don't restrict fmt_single and fmt_word to even
1060 registers.
1061 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
1062 or fmt_word.
1063 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
1064 and then set the state to fmt_uninterpreted.
1065 (COP_SW): Temporarily set the state to fmt_word while calling
1066 ValueFPR.
1067
6389d856
ILT		 1068Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
1069
1070 * gencode.c (build_instruction): The high order may be set in the
1071 comparison flags at any ISA level, not just ISA 4.
1072
19c5af72
DE		 1073Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
1074
1075 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
1076 COMMON_{PRE,POST}_CONFIG_FRAG instead.
1077 * configure.in: sinclude ../common/aclocal.m4.
1078 * configure: Regenerated.
1079
736a306c
ILT		 1080Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
1081
1082 * configure: Rebuild after change to aclocal.m4.
1083
295dbbe4
SG		 1084Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
1085
1086 * configure configure.in Makefile.in: Update to new configure
1087 scheme which is more compatible with WinGDB builds.
1088 * configure.in: Improve comment on how to run autoconf.
1089 * configure: Re-run autoconf to get new ../common/aclocal.m4.
1090 * Makefile.in: Use autoconf substitution to install common
1091 makefile fragment.
1092
1093Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
1094
1095 * gencode.c (build_instruction): Use BigEndianCPU instead of
1096 ByteSwapMem.
1097
e1db0d47
MA		 1098Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
1099
1100 * interp.c (sim_monitor): Make output to stdout visible in
1101 wingdb's I/O log window.
1102
2902e8ab
MA		 1103Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
1104
1105 * support.h: Undo previous change to SIGTRAP
1106 and SIGQUIT values.
1107
7e6c297e
ILT		 1108Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
1109
1110 * interp.c (store_word, load_word): New static functions.
1111 (mips16_entry): New static function.
1112 (SignalException): Look for mips16 entry and exit instructions.
1113 (simulate): Use the correct index when setting fpr_state after
1114 doing a pending move.
1115
0049ba7a
MA		 1116Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
1117
1118 * interp.c: Fix byte-swapping code throughout to work on
1119 both little- and big-endian hosts.
1120
2510786b
MA		 1121Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
1122
1123 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
1124 with gdb/config/i386/xm-windows.h.
1125
39bf0ef4
MA		 1126Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
1127
1128 * gencode.c (build_instruction): Work around MSVC++ code gen bug
1129 that messes up arithmetic shifts.
1130
dbeec768
SG		 1131Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
1132
1133 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
1134 SIGTRAP and SIGQUIT for _WIN32.
1135
deffd638
ILT		 1136Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
1137
1138 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
1139 force a 64 bit multiplication.
1140 (build_instruction) [OR]: In mips16 mode, don't do anything if the
1141 destination register is 0, since that is the default mips16 nop
1142 instruction.
1143
aaff8437
ILT		 1144Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
1145
063443cf
ILT		 1146 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
1147 (build_endian_shift): Don't check proc64.
1148 (build_instruction): Always set memval to uword64. Cast op2 to
1149 uword64 when shifting it left in memory instructions. Always use
1150 the same code for stores--don't special case proc64.
1151
aaff8437
ILT		 1152 * gencode.c (build_mips16_operands): Fix base PC value for PC
1153 relative operands.
1154 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
1155 jal instruction.
1156 * interp.c (simJALDELAYSLOT): Define.
1157 (JALDELAYSLOT): Define.
1158 (INDELAYSLOT, INJALDELAYSLOT): Define.
1159 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
1160
280f90e1
AMT		 1161Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
1162
1163 * interp.c (sim_open): add flush_cache as a PMON routine
1164 (sim_monitor): handle flush_cache by ignoring it
1165
aaff8437
ILT		 1166Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
1167
1168 * gencode.c (build_instruction): Use !ByteSwapMem instead of
1169 BigEndianMem.
1170 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
1171 (BigEndianMem): Rename to ByteSwapMem and change sense.
1172 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
1173 BigEndianMem references to !ByteSwapMem.
1174 (set_endianness): New function, with prototype.
1175 (sim_open): Call set_endianness.
1176 (sim_info): Use simBE instead of BigEndianMem.
1177 (xfer_direct_word, xfer_direct_long, swap_direct_word,
1178 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
1179 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
1180 ifdefs, keeping the prototype declaration.
1181 (swap_word): Rewrite correctly.
1182 (ColdReset): Delete references to CONFIG. Delete endianness related
1183 code; moved to set_endianness.
1184
6429b296
JW		 1185Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
1186
1187 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
1188 * interp.c (CHECKHILO): Define away.
1189 (simSIGINT): New macro.
1190 (membank_size): Increase from 1MB to 2MB.
1191 (control_c): New function.
1192 (sim_resume): Rename parameter signal to signal_number. Add local
1193 variable prev. Call signal before and after simulate.
1194 (sim_stop_reason): Add simSIGINT support.
1195 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
1196 functions always.
1197 (sim_warning): Delete call to SignalException. Do call printf_filtered
1198 if logfh is NULL.
1199 (AddressTranslation): Add #ifdef DEBUG around debugging message and
1200 a call to sim_warning.
1201
1202Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
1203
1204 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
1205 16 bit instructions.
1206
831f59a2
ILT		 1207Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
1208
1209 Add support for mips16 (16 bit MIPS implementation):
1210 * gencode.c (inst_type): Add mips16 instruction encoding types.
1211 (GETDATASIZEINSN): Define.
1212 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
1213 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
1214 mtlo.
1215 (MIPS16_DECODE): New table, for mips16 instructions.
1216 (bitmap_val): New static function.
1217 (struct mips16_op): Define.
1218 (mips16_op_table): New table, for mips16 operands.
1219 (build_mips16_operands): New static function.
1220 (process_instructions): If PC is odd, decode a mips16
1221 instruction. Break out instruction handling into new
1222 build_instruction function.
1223 (build_instruction): New static function, broken out of
1224 process_instructions. Check modifiers rather than flags for SHIFT
1225 bit count and m[ft]{hi,lo} direction.
1226 (usage): Pass program name to fprintf.
1227 (main): Remove unused variable this_option_optind. Change
1228 ``*loptarg++'' to ``loptarg++''.
1229 (my_strtoul): Parenthesize && within ||.
350d33b8 1230 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
831f59a2
ILT		 1231 (simulate): If PC is odd, fetch a 16 bit instruction, and
1232 increment PC by 2 rather than 4.
1233 * configure.in: Add case for mips16*-*-*.
1234 * configure: Rebuild.
1235
1236Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
1237
1238 * interp.c: Allow -t to enable tracing in standalone simulator.
1239 Fix garbage output in trace file and error messages.
1240
e3d12c65
DE		 1241Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
1242
1243 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
1244 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
1245 * configure.in: Simplify using macros in ../common/aclocal.m4.
1246 * configure: Regenerated.
1247 * tconfig.in: New file.
1248
1249Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
1250
1251 * interp.c: Fix bugs in 64-bit port.
1252 Use ansi function declarations for msvc compiler.
1253 Initialize and test file pointer in trace code.
1254 Prevent duplicate definition of LAST_EMED_REGNUM.
1255
1256Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
1257
1258 * interp.c (xfer_big_long): Prevent unwanted sign extension.
1259
1260Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
1261
1262 * interp.c (SignalException): Check for explicit terminating
1263 breakpoint value.
1264 * gencode.c: Pass instruction value through SignalException()
1265 calls for Trap, Breakpoint and Syscall.
1266
1267Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
1268
1269 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
1270 only used on those hosts that provide it.
1271 * configure.in: Add sqrt() to list of functions to be checked for.
1272 * config.in: Re-generated.
1273 * configure: Re-generated.
1274
1275Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
1276
1277 * gencode.c (process_instructions): Call build_endian_shift when
1278 expanding STORE RIGHT, to fix swr.
1279 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
1280 clear the high bits.
1281 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
1282 Fix float to int conversions to produce signed values.
1283
cc5201d7
ILT		 1284Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
1285
458e1f58
ILT		 1286 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
1287 (process_instructions): Correct handling of nor instruction.
1288 Correct shift count for 32 bit shift instructions. Correct sign
1289 extension for arithmetic shifts to not shift the number of bits in
1290 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
1291 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
1292 Fix madd.
c05d1721
ILT		 1293 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
1294 It's OK to have a mult follow a mult. What's not OK is to have a
1295 mult follow an mfhi.
458e1f58 1296 (Convert): Comment out incorrect rounding code.
cc5201d7 1297
f24b7b69
JSC		 1298Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
1299
1300 * interp.c (sim_monitor): Improved monitor printf
1301 simulation. Tidied up simulator warnings, and added "--log" option
1302 for directing warning message output.
1303 * gencode.c: Use sim_warning() rather than WARNING macro.
1304
1305Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
1306
1307 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
1308 getopt1.o, rather than on gencode.c. Link objects together.
1309 Don't link against -liberty.
1310 (gencode.o, getopt.o, getopt1.o): New targets.
1311 * gencode.c: Include <ctype.h> and "ansidecl.h".
1312 (AND): Undefine after including "ansidecl.h".
1313 (ULONG_MAX): Define if not defined.
1314 (OP_*): Don't define macros; now defined in opcode/mips.h.
1315 (main): Call my_strtoul rather than strtoul.
1316 (my_strtoul): New static function.
1317
1318Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
1319
1320 * gencode.c (process_instructions): Generate word64 and uword64
1321 instead of `long long' and `unsigned long long' data types.
1322 * interp.c: #include sysdep.h to get signals, and define default
1323 for SIGBUS.
1324 * (Convert): Work around for Visual-C++ compiler bug with type
1325 conversion.
1326 * support.h: Make things compile under Visual-C++ by using
1327 __int64 instead of `long long'. Change many refs to long long
1328 into word64/uword64 typedefs.
1329
a271d1d9
JM		 1330Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
1331
1332 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
1333 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
1334 (docdir): Removed.
1335 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
1336 (AC_PROG_INSTALL): Added.
1337 (AC_PROG_CC): Moved to before configure.host call.
1338 * configure: Rebuilt.
1339
1340Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
1341
1342 * configure.in: Define @SIMCONF@ depending on mips target.
1343 * configure: Rebuild.
1344 * Makefile.in (run): Add @SIMCONF@ to control simulator
1345 construction.
1346 * gencode.c: Change LOADDRMASK to 64bit memory model only.
1347 * interp.c: Remove some debugging, provide more detailed error
1348 messages, update memory accesses to use LOADDRMASK.
1349
4fa134be
ILT		 1350Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
1351
1352 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
1353 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
1354 stamp-h.
1355 * configure: Rebuild.
1356 * config.in: New file, generated by autoheader.
1357 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
1358 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
1359 HAVE_ANINT and HAVE_AINT, as appropriate.
1360 * Makefile.in (run): Use @LIBS@ rather than -lm.
1361 (interp.o): Depend upon config.h.
1362 (Makefile): Just rebuild Makefile.
1363 (clean): Remove stamp-h.
1364 (mostlyclean): Make the same as clean, not as distclean.
1365 (config.h, stamp-h): New targets.
1366
1367Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
1368
1369 * interp.c (ColdReset): Fix boolean test. Make all simulator
1370 globals static.
1371
f7481d45
JSC		 1372Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
1373
1374 * interp.c (xfer_direct_word, xfer_direct_long,
1375 swap_direct_word, swap_direct_long, xfer_big_word,
1376 xfer_big_long, xfer_little_word, xfer_little_long,
1377 swap_word,swap_long): Added.
1378 * interp.c (ColdReset): Provide function indirection to
1379 host<->simulated_target transfer routines.
1380 * interp.c (sim_store_register, sim_fetch_register): Updated to
1381 make use of indirected transfer routines.
1382
1383Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
1384
1385 * gencode.c (process_instructions): Ensure FP ABS instruction
1386 recognised.
1387 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
1388 system call support.
1389
8b554809
JSC		 1390Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
1391
1392 * interp.c (sim_do_command): Complain if callback structure not
1393 initialised.
1394
d0757082
JSC		 1395Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
1396
1397 * interp.c (Convert): Provide round-to-nearest and round-to-zero
1398 support for Sun hosts.
1399 * Makefile.in (gencode): Ensure the host compiler and libraries
1400 used for cross-hosted build.
1401
e871dd18
JSC		 1402Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
1403
1404 * interp.c, gencode.c: Some more (TODO) tidying.
1405
1406Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
1407
1408 * gencode.c, interp.c: Replaced explicit long long references with
1409 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
1410 * support.h (SET64LO, SET64HI): Macros added.
1411
5c59ec43
ILT		 1412Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
1413
1414 * configure: Regenerate with autoconf 2.7.
1415
1416Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
1417
1418 * interp.c (LoadMemory): Enclose text following #endif in /* */.
1419 * support.h: Remove superfluous "1" from #if.
1420 * support.h (CHECKSIM): Remove stray 'a' at end of line.
1421
1422Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
1423
1424 * interp.c (StoreFPR): Control UndefinedResult() call on
1425 WARN_RESULT manifest.
1426
8bae0a0c
JSC		 1427Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
1428
1429 * gencode.c: Tidied instruction decoding, and added FP instruction
1430 support.
1431
1432 * interp.c: Added dineroIII, and BSD profiling support. Also
1433 run-time FP handling.
1434
1435Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
1436
1437 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
1438 gencode.c, interp.c, support.h: created.
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