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[deliverable/binutils-gdb.git] / sim / mips / Makefile.in
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c906108c
SS		 1# Makefile template for Configure for the MIPS simulator.
2# Written by Cygnus Support.
3
ae451ac6
ILT		 4SHELL = @SHELL@
5
c906108c
SS		 6## COMMON_PRE_CONFIG_FRAG
7
8srcdir=@srcdir@
9srcroot=$(srcdir)/../../
10
11# Object files created by various simulator generators.
12
13
14SIM_IGEN_OBJ = \
15 support.o \
16 itable.o \
17 semantics.o \
18 idecode.o \
19 icache.o \
20 @mips_igen_engine@ \
21 irun.o \
22
23
24SIM_M16_OBJ = \
25 m16_support.o \
26 m16_semantics.o \
27 m16_idecode.o \
28 m16_icache.o \
29 \
30 m32_support.o \
31 m32_semantics.o \
32 m32_idecode.o \
33 m32_icache.o \
34 \
35 itable.o \
36 m16run.o \
37
4c54fc26 38SIM_MULTI_OBJ = itable.o @sim_multi_obj@
c906108c
SS		 39
40MIPS_EXTRA_OBJS = @mips_extra_objs@
41MIPS_EXTRA_LIBS = @mips_extra_libs@
42
43SIM_OBJS = \
44 $(SIM_@sim_gen@_OBJ) \
45 $(SIM_NEW_COMMON_OBJS) \
46 $(MIPS_EXTRA_OBJS) \
487f79b7 47 cp1.o \
c906108c 48 interp.o \
f4f1b9f1 49 mdmx.o \
40a5538e 50 dsp.o \
c906108c
SS		 51 sim-main.o \
52 sim-hload.o \
53 sim-engine.o \
54 sim-stop.o \
55 sim-resume.o \
56 sim-reason.o \
57
58
59# List of flags to always pass to $(CC).
60SIM_SUBTARGET=@SIM_SUBTARGET@
61SIM_EXTRA_CFLAGS = $(SIM_SUBTARGET)
62
63SIM_EXTRA_CLEAN = clean-extra
4c54fc26 64SIM_EXTRA_DISTCLEAN = distclean-extra
c906108c
SS		 65
66SIM_EXTRA_ALL = $(SIM_@sim_gen@_ALL)
67
68SIM_EXTRA_LIBS = $(MIPS_EXTRA_LIBS)
69
70# List of main object files for `run'.
71SIM_RUN_OBJS = nrun.o
72
73
74
75## COMMON_POST_CONFIG_FRAG
76
77interp.o: $(srcdir)/interp.c config.h sim-main.h itable.h
487f79b7 78cp1.o: $(srcdir)/cp1.c config.h sim-main.h
c906108c 79
f4f1b9f1 80mdmx.o: $(srcdir)/mdmx.c $(srcdir)/sim-main.h
c906108c 81
40a5538e
CF		 82dsp.o: $(srcdir)/dsp.c $(srcdir)/sim-main.h
83
4c54fc26
CD		 84multi-run.o: multi-include.h tmp-mach-multi
85
c906108c
SS		 86../igen/igen:
87 cd ../igen && $(MAKE)
88
89IGEN_TRACE= # -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejection -G trace-entries # -G trace-all
90IGEN_INSN=$(srcdir)/mips.igen
91IGEN_DC=$(srcdir)/mips.dc
92M16_DC=$(srcdir)/m16.dc
93IGEN_INCLUDE=\
94 $(srcdir)/m16.igen \
d85c3a10 95 $(srcdir)/m16e.igen \
909daa82 96 $(srcdir)/mdmx.igen \
e7e81181 97 $(srcdir)/mips3d.igen \
7cbea089 98 $(srcdir)/sb1.igen \
c906108c
SS		 99 $(srcdir)/tx.igen \
100 $(srcdir)/vr.igen \
40a5538e 101 $(srcdir)/dsp.igen \
8b082fb1 102 $(srcdir)/dsp2.igen \
d85c3a10 103 $(srcdir)/mips3264r2.igen \
c906108c
SS		 104
105# NB: Since these can be built by a number of generators, care
106# must be taken to ensure that they are only dependant on
107# one of those generators.
108BUILT_SRC_FROM_GEN = \
109 itable.h \
110 itable.c \
111
112SIM_IGEN_ALL = tmp-igen
113SIM_M16_ALL = tmp-m16
4c54fc26 114SIM_MULTI_ALL = tmp-multi
c906108c
SS		 115
116$(BUILT_SRC_FROM_GEN): $(SIM_@sim_gen@_ALL)
117
118
119
120BUILT_SRC_FROM_IGEN = \
121 icache.h \
122 icache.c \
123 idecode.h \
124 idecode.c \
125 semantics.h \
126 semantics.c \
127 model.h \
128 model.c \
129 support.h \
130 support.c \
131 engine.h \
132 engine.c \
133 irun.c \
134
135$(BUILT_SRC_FROM_IGEN): tmp-igen
136
137tmp-igen: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
138 cd ../igen && $(MAKE)
139 ../igen/igen \
140 $(IGEN_TRACE) \
141 -I $(srcdir) \
142 -Werror \
143 -Wnodiscard \
144 @sim_igen_flags@ \
145 -G gen-direct-access \
146 -G gen-zero-r0 \
147 -B 32 \
148 -H 31 \
149 -i $(IGEN_INSN) \
150 -o $(IGEN_DC) \
151 -x \
152 -n icache.h -hc tmp-icache.h \
153 -n icache.c -c tmp-icache.c \
154 -n semantics.h -hs tmp-semantics.h \
155 -n semantics.c -s tmp-semantics.c \
156 -n idecode.h -hd tmp-idecode.h \
157 -n idecode.c -d tmp-idecode.c \
158 -n model.h -hm tmp-model.h \
159 -n model.c -m tmp-model.c \
160 -n support.h -hf tmp-support.h \
161 -n support.c -f tmp-support.c \
162 -n itable.h -ht tmp-itable.h \
163 -n itable.c -t tmp-itable.c \
164 -n engine.h -he tmp-engine.h \
165 -n engine.c -e tmp-engine.c \
166 -n irun.c -r tmp-irun.c
ae451ac6
ILT		 167 $(SHELL) $(srcdir)/../../move-if-change tmp-icache.h icache.h
168 $(SHELL) $(srcdir)/../../move-if-change tmp-icache.c icache.c
169 $(SHELL) $(srcdir)/../../move-if-change tmp-idecode.h idecode.h
170 $(SHELL) $(srcdir)/../../move-if-change tmp-idecode.c idecode.c
171 $(SHELL) $(srcdir)/../../move-if-change tmp-semantics.h semantics.h
172 $(SHELL) $(srcdir)/../../move-if-change tmp-semantics.c semantics.c
173 $(SHELL) $(srcdir)/../../move-if-change tmp-model.h model.h
174 $(SHELL) $(srcdir)/../../move-if-change tmp-model.c model.c
175 $(SHELL) $(srcdir)/../../move-if-change tmp-support.h support.h
176 $(SHELL) $(srcdir)/../../move-if-change tmp-support.c support.c
177 $(SHELL) $(srcdir)/../../move-if-change tmp-itable.h itable.h
178 $(SHELL) $(srcdir)/../../move-if-change tmp-itable.c itable.c
179 $(SHELL) $(srcdir)/../../move-if-change tmp-engine.h engine.h
180 $(SHELL) $(srcdir)/../../move-if-change tmp-engine.c engine.c
181 $(SHELL) $(srcdir)/../../move-if-change tmp-irun.c irun.c
c906108c
SS		 182 touch tmp-igen
183
184semantics.o: sim-main.h semantics.c $(SIM_EXTRA_DEPS)
185engine.o: sim-main.h engine.c $(SIM_EXTRA_DEPS)
186support.o: sim-main.h support.c $(SIM_EXTRA_DEPS)
187idecode.o: sim-main.h idecode.c $(SIM_EXTRA_DEPS)
188itable.o: sim-main.h itable.c $(SIM_EXTRA_DEPS)
efdcccc9 189m16run.o: sim-main.h m16_idecode.h m32_idecode.h $(SIM_EXTRA_DEPS)
c906108c 190
d85c3a10
TS		 191m16_semantics.o: sim-main.h m16_semantics.c $(SIM_EXTRA_DEPS)
192m16_support.o: sim-main.h m16_support.c $(SIM_EXTRA_DEPS)
193m16_idecode.o: sim-main.h m16_idecode.c $(SIM_EXTRA_DEPS)
194m16_icache.o: sim-main.h m16_icache.c $(SIM_EXTRA_DEPS)
c906108c 195
d85c3a10
TS		 196m32_semantics.o: sim-main.h m32_semantics.c $(SIM_EXTRA_DEPS)
197m32_support.o: sim-main.h m32_support.c $(SIM_EXTRA_DEPS)
198m32_idecode.o: sim-main.h m32_idecode.c $(SIM_EXTRA_DEPS)
199m32_icache.o: sim-main.h m32_icache.c $(SIM_EXTRA_DEPS)
c906108c
SS		 200
201BUILT_SRC_FROM_M16 = \
202 m16_icache.h \
203 m16_icache.c \
204 m16_idecode.h \
205 m16_idecode.c \
206 m16_semantics.h \
207 m16_semantics.c \
208 m16_model.h \
209 m16_model.c \
210 m16_support.h \
211 m16_support.c \
212 \
213 m32_icache.h \
214 m32_icache.c \
215 m32_idecode.h \
216 m32_idecode.c \
217 m32_semantics.h \
218 m32_semantics.c \
219 m32_model.h \
220 m32_model.c \
221 m32_support.h \
222 m32_support.c \
223
224$(BUILT_SRC_FROM_M16): tmp-m16
225
226tmp-m16: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
227 cd ../igen && $(MAKE)
228 ../igen/igen \
229 $(IGEN_TRACE) \
230 -I $(srcdir) \
231 -Werror \
232 -Wnodiscard \
233 @sim_m16_flags@ \
234 -G gen-direct-access \
235 -G gen-zero-r0 \
236 -B 16 \
237 -H 15 \
238 -i $(IGEN_INSN) \
239 -o $(M16_DC) \
240 -P m16_ \
241 -x \
242 -n m16_icache.h -hc tmp-icache.h \
243 -n m16_icache.c -c tmp-icache.c \
244 -n m16_semantics.h -hs tmp-semantics.h \
245 -n m16_semantics.c -s tmp-semantics.c \
246 -n m16_idecode.h -hd tmp-idecode.h \
247 -n m16_idecode.c -d tmp-idecode.c \
248 -n m16_model.h -hm tmp-model.h \
249 -n m16_model.c -m tmp-model.c \
250 -n m16_support.h -hf tmp-support.h \
251 -n m16_support.c -f tmp-support.c \
252 #
ae451ac6
ILT		 253 $(SHELL) $(srcdir)/../../move-if-change tmp-icache.h m16_icache.h
254 $(SHELL) $(srcdir)/../../move-if-change tmp-icache.c m16_icache.c
255 $(SHELL) $(srcdir)/../../move-if-change tmp-idecode.h m16_idecode.h
256 $(SHELL) $(srcdir)/../../move-if-change tmp-idecode.c m16_idecode.c
257 $(SHELL) $(srcdir)/../../move-if-change tmp-semantics.h m16_semantics.h
258 $(SHELL) $(srcdir)/../../move-if-change tmp-semantics.c m16_semantics.c
259 $(SHELL) $(srcdir)/../../move-if-change tmp-model.h m16_model.h
260 $(SHELL) $(srcdir)/../../move-if-change tmp-model.c m16_model.c
261 $(SHELL) $(srcdir)/../../move-if-change tmp-support.h m16_support.h
262 $(SHELL) $(srcdir)/../../move-if-change tmp-support.c m16_support.c
c906108c
SS		 263 ../igen/igen \
264 $(IGEN_TRACE) \
265 -I $(srcdir) \
266 -Werror \
267 -Wnodiscard \
268 @sim_igen_flags@ \
269 -G gen-direct-access \
270 -G gen-zero-r0 \
271 -B 32 \
272 -H 31 \
273 -i $(IGEN_INSN) \
274 -o $(IGEN_DC) \
275 -P m32_ \
276 -x \
277 -n m32_icache.h -hc tmp-icache.h \
278 -n m32_icache.c -c tmp-icache.c \
279 -n m32_semantics.h -hs tmp-semantics.h \
280 -n m32_semantics.c -s tmp-semantics.c \
281 -n m32_idecode.h -hd tmp-idecode.h \
282 -n m32_idecode.c -d tmp-idecode.c \
283 -n m32_model.h -hm tmp-model.h \
284 -n m32_model.c -m tmp-model.c \
285 -n m32_support.h -hf tmp-support.h \
286 -n m32_support.c -f tmp-support.c \
287 #
ae451ac6
ILT		 288 $(SHELL) $(srcdir)/../../move-if-change tmp-icache.h m32_icache.h
289 $(SHELL) $(srcdir)/../../move-if-change tmp-icache.c m32_icache.c
290 $(SHELL) $(srcdir)/../../move-if-change tmp-idecode.h m32_idecode.h
291 $(SHELL) $(srcdir)/../../move-if-change tmp-idecode.c m32_idecode.c
292 $(SHELL) $(srcdir)/../../move-if-change tmp-semantics.h m32_semantics.h
293 $(SHELL) $(srcdir)/../../move-if-change tmp-semantics.c m32_semantics.c
294 $(SHELL) $(srcdir)/../../move-if-change tmp-model.h m32_model.h
295 $(SHELL) $(srcdir)/../../move-if-change tmp-model.c m32_model.c
296 $(SHELL) $(srcdir)/../../move-if-change tmp-support.h m32_support.h
297 $(SHELL) $(srcdir)/../../move-if-change tmp-support.c m32_support.c
c906108c
SS		 298 ../igen/igen \
299 $(IGEN_TRACE) \
300 -I $(srcdir) \
301 -Werror \
302 -Wnodiscard \
303 -Wnowidth \
304 @sim_igen_flags@ @sim_m16_flags@ \
305 -G gen-direct-access \
306 -G gen-zero-r0 \
307 -i $(IGEN_INSN) \
308 -n itable.h -ht tmp-itable.h \
309 -n itable.c -t tmp-itable.c \
310 #
ae451ac6
ILT		 311 $(SHELL) $(srcdir)/../../move-if-change tmp-itable.h itable.h
312 $(SHELL) $(srcdir)/../../move-if-change tmp-itable.c itable.c
c906108c
SS		 313 touch tmp-m16
314
315
4c54fc26
CD		 316BUILT_SRC_FROM_MULTI = @sim_multi_src@
317SIM_MULTI_IGEN_CONFIGS = @sim_multi_igen_configs@
318
319$(BUILT_SRC_FROM_MULTI): tmp-multi
320tmp-multi: tmp-mach-multi tmp-itable-multi tmp-run-multi targ-vals.h
321tmp-mach-multi: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
322 for t in $(SIM_MULTI_IGEN_CONFIGS); do \
323 p=`echo $${t} | sed -e 's/:.*//'` ; \
324 m=`echo $${t} | sed -e 's/.*:\(.*\):.*/\1/'` ; \
325 f=`echo $${t} | sed -e 's/.*://'` ; \
326 case $${p} in \
327 m16*) e="-B 16 -H 15 -o $(M16_DC) -F 16" ;; \
328 *) e="-B 32 -H 31 -o $(IGEN_DC) -F $${f}" ;; \
329 esac; \
330 ../igen/igen \
331 $(IGEN_TRACE) \
332 $${e} \
333 -I $(srcdir) \
334 -Werror \
335 -Wnodiscard \
336 -N 0 \
337 -M $${m} \
338 -G gen-direct-access \
339 -G gen-zero-r0 \
340 -i $(IGEN_INSN) \
341 -P $${p}_ \
342 -x \
343 -n $${p}_icache.h -hc tmp-icache.h \
344 -n $${p}_icache.c -c tmp-icache.c \
345 -n $${p}_semantics.h -hs tmp-semantics.h \
346 -n $${p}_semantics.c -s tmp-semantics.c \
347 -n $${p}_idecode.h -hd tmp-idecode.h \
348 -n $${p}_idecode.c -d tmp-idecode.c \
349 -n $${p}_model.h -hm tmp-model.h \
350 -n $${p}_model.c -m tmp-model.c \
351 -n $${p}_support.h -hf tmp-support.h \
352 -n $${p}_support.c -f tmp-support.c \
353 -n $${p}_engine.h -he tmp-engine.h \
354 -n $${p}_engine.c -e tmp-engine.c \
355 ; \
ae451ac6
ILT		 356 $(SHELL) $(srcdir)/../../move-if-change tmp-icache.h $${p}_icache.h ; \
357 $(SHELL) $(srcdir)/../../move-if-change tmp-icache.c $${p}_icache.c ; \
358 $(SHELL) $(srcdir)/../../move-if-change tmp-idecode.h $${p}_idecode.h ; \
359 $(SHELL) $(srcdir)/../../move-if-change tmp-idecode.c $${p}_idecode.c ; \
360 $(SHELL) $(srcdir)/../../move-if-change tmp-semantics.h $${p}_semantics.h ; \
361 $(SHELL) $(srcdir)/../../move-if-change tmp-semantics.c $${p}_semantics.c ; \
362 $(SHELL) $(srcdir)/../../move-if-change tmp-model.h $${p}_model.h ; \
363 $(SHELL) $(srcdir)/../../move-if-change tmp-model.c $${p}_model.c ; \
364 $(SHELL) $(srcdir)/../../move-if-change tmp-support.h $${p}_support.h ; \
365 $(SHELL) $(srcdir)/../../move-if-change tmp-support.c $${p}_support.c ; \
366 $(SHELL) $(srcdir)/../../move-if-change tmp-engine.h $${p}_engine.h ; \
367 $(SHELL) $(srcdir)/../../move-if-change tmp-engine.c $${p}_engine.c ; \
4c54fc26
CD		 368 done
369 touch tmp-mach-multi
370tmp-itable-multi: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
371 ../igen/igen \
372 $(IGEN_TRACE) \
373 -I $(srcdir) \
374 -Werror \
375 -Wnodiscard \
376 -Wnowidth \
377 -N 0 \
378 @sim_multi_flags@ \
379 -G gen-direct-access \
380 -G gen-zero-r0 \
381 -i $(IGEN_INSN) \
382 -n itable.h -ht tmp-itable.h \
383 -n itable.c -t tmp-itable.c \
384 #
ae451ac6
ILT		 385 $(SHELL) $(srcdir)/../../move-if-change tmp-itable.h itable.h
386 $(SHELL) $(srcdir)/../../move-if-change tmp-itable.c itable.c
4c54fc26
CD		 387 touch tmp-itable-multi
388tmp-run-multi: $(srcdir)/m16run.c
389 for t in $(SIM_MULTI_IGEN_CONFIGS); do \
390 case $${t} in \
80551777 391 m16*) \
4c54fc26
CD		 392 m=`echo $${t} | sed -e 's/^m16//' -e 's/:.*//'`; \
393 sed < $(srcdir)/m16run.c > tmp-run \
394 -e "s/^sim_/m16$${m}_/" \
395 -e "s/m16_/m16$${m}_/" \
396 -e "s/m32_/m32$${m}_/" ; \
ae451ac6 397 $(SHELL) $(srcdir)/../../move-if-change tmp-run m16$${m}_run.c ; \
4c54fc26
CD		 398 esac \
399 done
400 touch tmp-run-multi
401
c906108c
SS		 402clean-extra:
403 rm -f $(BUILT_SRC_FROM_GEN)
404 rm -f $(BUILT_SRC_FROM_IGEN)
405 rm -f $(BUILT_SRC_FROM_M16)
4c54fc26 406 rm -f $(BUILT_SRC_FROM_MULTI)
c906108c 407 rm -f tmp-*
071da002 408 rm -f m16*.o m32*.o itable*.o
c906108c 409
4c54fc26
CD		 410distclean-extra:
411 rm -f multi-include.h multi-run.c
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