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1 | /*> cp1.h <*/ |
2 | /* MIPS Simulator FPU (CoProcessor 1) definitions. | |
e2882c85 | 3 | Copyright (C) 1997-2018 Free Software Foundation, Inc. |
cfe9ea23 | 4 | Derived from sim-main.h contributed by Cygnus Solutions, |
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5 | modified substantially by Ed Satterthwaite of Broadcom Corporation |
6 | (SiByte). | |
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7 | |
8 | This file is part of GDB, the GNU debugger. | |
9 | ||
10 | This program is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
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12 | the Free Software Foundation; either version 3 of the License, or |
13 | (at your option) any later version. | |
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14 | |
15 | This program is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
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20 | You should have received a copy of the GNU General Public License |
21 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
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22 | |
23 | #ifndef CP1_H | |
24 | #define CP1_H | |
25 | ||
26 | /* See sim-main.h for allocation of registers FCR0 and FCR31 (FCSR) | |
27 | in CPU state (struct sim_cpu), and for FPU functions. */ | |
28 | ||
29 | #define fcsr_FCC_mask (0xFE800000) | |
30 | #define fcsr_FCC_shift (23) | |
31 | #define fcsr_FCC_bit(cc) ((cc) == 0 ? 23 : (24 + (cc))) | |
32 | #define fcsr_FS (1 << 24) /* MIPS III onwards : Flush to Zero */ | |
33 | #define fcsr_ZERO_mask (0x007C0000) | |
34 | #define fcsr_CAUSE_mask (0x0003F000) | |
35 | #define fcsr_CAUSE_shift (12) | |
36 | #define fcsr_ENABLES_mask (0x00000F80) | |
37 | #define fcsr_ENABLES_shift (7) | |
38 | #define fcsr_FLAGS_mask (0x0000007C) | |
39 | #define fcsr_FLAGS_shift (2) | |
40 | #define fcsr_RM_mask (0x00000003) | |
41 | #define fcsr_RM_shift (0) | |
42 | ||
52714ff9 | 43 | #define fenr_FS (0x00000004) |
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44 | |
45 | /* Macros to update and retrieve the FCSR condition-code bits. This | |
46 | is complicated by the fact that there is a hole in the index range | |
47 | of the bits within the FCSR register. (Note that the number of bits | |
48 | visible depends on the ISA in use, but that is handled elsewhere.) */ | |
49 | #define SETFCC(cc,v) \ | |
50 | do { \ | |
51 | (FCSR = ((FCSR & ~(1 << fcsr_FCC_bit(cc))) | ((v) << fcsr_FCC_bit(cc)))); \ | |
52 | } while (0) | |
53 | #define GETFCC(cc) ((FCSR & (1 << fcsr_FCC_bit(cc))) != 0 ? 1 : 0) | |
54 | ||
55 | ||
56 | /* Read flush-to-zero bit (not right-justified). */ | |
57 | #define GETFS() ((int)(FCSR & fcsr_FS)) | |
58 | ||
59 | ||
60 | /* FCSR flag bits definitions and access macros. */ | |
61 | #define IR 0 /* I: Inexact Result */ | |
62 | #define UF 1 /* U: UnderFlow */ | |
63 | #define OF 2 /* O: OverFlow */ | |
64 | #define DZ 3 /* Z: Division by Zero */ | |
65 | #define IO 4 /* V: Invalid Operation */ | |
66 | #define UO 5 /* E: Unimplemented Operation (CAUSE field only) */ | |
67 | ||
68 | #define FP_FLAGS(b) (1 << ((b) + fcsr_FLAGS_shift)) | |
69 | #define FP_ENABLE(b) (1 << ((b) + fcsr_ENABLES_shift)) | |
70 | #define FP_CAUSE(b) (1 << ((b) + fcsr_CAUSE_shift)) | |
71 | ||
72 | ||
73 | /* Rounding mode bit definitions and access macros. */ | |
74 | #define FP_RM_NEAREST 0 /* Round to nearest (Round). */ | |
75 | #define FP_RM_TOZERO 1 /* Round to zero (Trunc). */ | |
76 | #define FP_RM_TOPINF 2 /* Round to Plus infinity (Ceil). */ | |
77 | #define FP_RM_TOMINF 3 /* Round to Minus infinity (Floor). */ | |
78 | ||
79 | #define GETRM() ((FCSR >> fcsr_RM_shift) & fcsr_RM_mask) | |
80 | ||
81 | ||
82 | #endif /* CP1_H */ |