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8b082fb1 TS |
1 | // -*- C -*- |
2 | ||
3 | // Simulator definition for the MIPS DSP REV 2 ASE. | |
8bf3ddc8 TS |
4 | // Copyright (C) 2007 Free Software Foundation, Inc. |
5 | // Contributed by MIPS Technologies, Inc. | |
6 | // Written by Chao-ying Fu (fu@mips.com). | |
8b082fb1 TS |
7 | // |
8 | // This file is part of GDB, the GNU debugger. | |
9 | // | |
10 | // This program is free software; you can redistribute it and/or modify | |
11 | // it under the terms of the GNU General Public License as published by | |
12 | // the Free Software Foundation; either version 2, or (at your option) | |
13 | // any later version. | |
14 | // | |
15 | // This program is distributed in the hope that it will be useful, | |
16 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | // GNU General Public License for more details. | |
19 | // | |
20 | // You should have received a copy of the GNU General Public License | |
21 | // along with GAS; see the file COPYING. If not, write to the Free | |
22 | // Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA | |
23 | // 02110-1301, USA. | |
24 | ||
25 | ||
26 | // op: 0 = ADD, 1 = SUB | |
27 | // sat: 0 = no saturation, 1 = saturation | |
28 | :function:::void:do_u_ph_op:int rd, int rs, int rt, int op, int sat | |
29 | { | |
30 | int i; | |
31 | unsigned32 h0; | |
32 | unsigned16 h1, h2; | |
33 | unsigned32 v1 = GPR[rs]; | |
34 | unsigned32 v2 = GPR[rt]; | |
35 | unsigned32 result = 0; | |
36 | for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16) | |
37 | { | |
38 | h1 = (unsigned16)(v1 & 0xffff); | |
39 | h2 = (unsigned16)(v2 & 0xffff); | |
40 | if (op == 0) // ADD | |
41 | h0 = (unsigned32)h1 + (unsigned32)h2; | |
42 | else // SUB | |
43 | h0 = (unsigned32)h1 - (unsigned32)h2; | |
44 | if (op == 0 && (h0 > (unsigned32)0x0000ffff)) // ADD SAT | |
45 | { | |
46 | DSPCR |= DSPCR_OUFLAG4; | |
47 | if (sat == 1) | |
48 | h0 = 0xffff; | |
49 | } | |
50 | else if (op == 1 && h1 < h2) // SUB SAT | |
51 | { | |
52 | DSPCR |= DSPCR_OUFLAG4; | |
53 | if (sat == 1) | |
54 | h0 = 0x0; | |
55 | } | |
56 | result |= ((unsigned32)((unsigned16)h0) << i); | |
57 | } | |
58 | GPR[rd] = EXTEND32 (result); | |
59 | } | |
60 | ||
61 | // op: 0 = ADD, 1 = SUB | |
62 | // round: 0 = no rounding, 1 = rounding | |
63 | :function:::void:do_uh_qb_op:int rd, int rs, int rt, int op, int round | |
64 | { | |
65 | int i; | |
66 | unsigned32 h0; | |
67 | unsigned8 h1, h2; | |
68 | unsigned32 v1 = GPR[rs]; | |
69 | unsigned32 v2 = GPR[rt]; | |
70 | unsigned32 result = 0; | |
71 | for (i = 0; i < 32; i += 8, v1 >>= 8, v2 >>= 8) | |
72 | { | |
73 | h1 = (unsigned8)(v1 & 0xff); | |
74 | h2 = (unsigned8)(v2 & 0xff); | |
75 | if (op == 0) // ADD | |
76 | h0 = (unsigned32)h1 + (unsigned32)h2; | |
77 | else // SUB | |
78 | h0 = (unsigned32)h1 - (unsigned32)h2; | |
79 | if (round == 1) | |
80 | h0 = (h0 + 1) >> 1; | |
81 | else | |
82 | h0 = h0 >> 1; | |
83 | result |= ((unsigned32)((unsigned8)h0) << i); | |
84 | } | |
85 | GPR[rd] = EXTEND32 (result); | |
86 | } | |
87 | ||
88 | // op: 0 = EQ, 1 = LT, 2 = LE | |
89 | :function:::void:do_qb_cmpgdu:int rd, int rs, int rt, int op | |
90 | { | |
91 | int i, j; | |
92 | unsigned32 v1 = GPR[rs]; | |
93 | unsigned32 v2 = GPR[rt]; | |
94 | unsigned8 h1, h2; | |
95 | unsigned32 result = 0; | |
96 | unsigned32 mask; | |
97 | for (i = 0, j = 0; i < 32; i += 8, j++, v1 >>= 8, v2 >>= 8) | |
98 | { | |
99 | h1 = (unsigned8)(v1 & 0xff); | |
100 | h2 = (unsigned8)(v2 & 0xff); | |
101 | mask = ~(1 << (DSPCR_CCOND_SHIFT + j)); | |
102 | DSPCR &= mask; | |
103 | if (op == 0) // EQ | |
104 | { | |
105 | result |= ((h1 == h2) << j); | |
106 | DSPCR |= ((h1 == h2) << (DSPCR_CCOND_SHIFT + j)); | |
107 | } | |
108 | else if (op == 1) // LT | |
109 | { | |
110 | result |= ((h1 < h2) << j); | |
111 | DSPCR |= ((h1 < h2) << (DSPCR_CCOND_SHIFT + j)); | |
112 | } | |
113 | else // LE | |
114 | { | |
115 | result |= ((h1 <= h2) << j); | |
116 | DSPCR |= ((h1 <= h2) << (DSPCR_CCOND_SHIFT + j)); | |
117 | } | |
118 | } | |
119 | GPR[rd] = EXTEND32 (result); | |
120 | } | |
121 | ||
122 | // op: 0 = DPA 1 = DPS | |
123 | :function:::void:do_w_ph_dot_product:int ac, int rs, int rt, int op | |
124 | { | |
125 | int i; | |
126 | unsigned32 v1 = GPR[rs]; | |
127 | unsigned32 v2 = GPR[rt]; | |
128 | signed16 h1, h2; | |
129 | signed32 result; | |
130 | unsigned32 lo = DSPLO(ac); | |
131 | unsigned32 hi = DSPHI(ac); | |
132 | signed64 prod = (signed64)((((unsigned64)hi) << 32) + (unsigned64)lo); | |
133 | for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16) | |
134 | { | |
135 | h1 = (signed16)(v1 & 0xffff); | |
136 | h2 = (signed16)(v2 & 0xffff); | |
137 | result = (signed32)h1 * (signed32)h2; | |
138 | if (op == 0) // DPA | |
139 | prod += (signed64)result; | |
140 | else // DPS | |
141 | prod -= (signed64)result; | |
142 | } | |
143 | DSPLO(ac) = EXTEND32 (prod); | |
144 | DSPHI(ac) = EXTEND32 (prod >> 32); | |
145 | } | |
146 | ||
147 | // round: 0 = no rounding, 1 = rounding | |
148 | :function:::void:do_w_mulq:int rd, int rs, int rt, int round | |
149 | { | |
150 | unsigned32 v1 = GPR[rs]; | |
151 | unsigned32 v2 = GPR[rt]; | |
152 | signed32 w1, w2; | |
153 | signed64 prod; | |
154 | unsigned32 result; | |
155 | w1 = (signed32) v1; | |
156 | w2 = (signed32 )v2; | |
157 | if (w1 == (signed32) 0x80000000 && w2 == (signed32) 0x80000000) | |
158 | { | |
159 | DSPCR |= DSPCR_OUFLAG5; | |
160 | prod = 0x7fffffff; | |
161 | } | |
162 | else | |
163 | { | |
164 | prod = ((signed64) w1 * (signed64) w2) << 1; | |
165 | if (round == 1) | |
166 | prod += 0x0000000080000000LL; | |
167 | prod = prod >> 32; | |
168 | } | |
169 | result = (unsigned32) prod; | |
170 | GPR[rd] = EXTEND32 (result); | |
171 | } | |
172 | ||
173 | // round: 0 = no rounding, 1 = rounding | |
174 | :function:::void:do_precr_sra:int rt, int rs, int sa, int round | |
175 | { | |
176 | unsigned32 v1 = GPR[rt]; | |
177 | unsigned32 v2 = GPR[rs]; | |
178 | signed32 w1 = (signed32) v1; | |
179 | signed32 w2 = (signed32) v2; | |
180 | signed32 result; | |
181 | if (sa != 0) | |
182 | { | |
183 | if (round == 1 && (w1 & (1 << (sa - 1)))) | |
184 | w1 = (w1 >> sa) + 1; | |
185 | else | |
186 | w1 = w1 >> sa; | |
187 | ||
188 | if (round == 1 && (w2 & (1 << (sa - 1)))) | |
189 | w2 = (w2 >> sa) + 1; | |
190 | else | |
191 | w2 = w2 >> sa; | |
192 | } | |
193 | result = (w1 << 16) | (w2 & 0xffff); | |
194 | GPR[rt] = EXTEND32 (result); | |
195 | } | |
196 | ||
197 | // round: 0 = no rounding, 1 = rounding | |
198 | :function:::void:do_qb_shra:int rd, int rt, int shift, int round | |
199 | { | |
200 | int i, j; | |
201 | signed8 q0; | |
202 | unsigned32 v1 = GPR[rt]; | |
203 | unsigned32 result = 0; | |
204 | for (i = 0; i < 32; i += 8, v1 >>= 8) | |
205 | { | |
206 | q0 = (signed8)(v1 & 0xff); | |
207 | if (shift != 0) | |
208 | { | |
209 | if (round == 1 && (q0 & (1 << (shift - 1)))) | |
210 | q0 = (q0 >> shift) + 1; | |
211 | else | |
212 | q0 = q0 >> shift; | |
213 | } | |
214 | result |= ((unsigned32)((unsigned8)q0) << i); | |
215 | } | |
216 | GPR[rd] = EXTEND32 (result); | |
217 | } | |
218 | ||
219 | :function:::void:do_ph_shrl:int rd, int rt, int shift | |
220 | { | |
221 | int i, j; | |
222 | unsigned16 h0; | |
223 | unsigned32 v1 = GPR[rt]; | |
224 | unsigned32 result = 0; | |
225 | for (i = 0; i < 32; i += 16, v1 >>= 16) | |
226 | { | |
227 | h0 = (unsigned16)(v1 & 0xffff); | |
228 | h0 = h0 >> shift; | |
229 | result |= ((unsigned32)h0 << i); | |
230 | } | |
231 | GPR[rd] = EXTEND32 (result); | |
232 | } | |
233 | ||
234 | // op: 0 = ADD, 1 = SUB | |
235 | // round: 0 = no rounding, 1 = rounding | |
236 | :function:::void:do_qh_ph_op:int rd, int rs, int rt, int op, int round | |
237 | { | |
238 | int i; | |
239 | signed32 h0; | |
240 | signed16 h1, h2; | |
241 | unsigned32 v1 = GPR[rs]; | |
242 | unsigned32 v2 = GPR[rt]; | |
243 | unsigned32 result = 0; | |
244 | for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16) | |
245 | { | |
246 | h1 = (signed16)(v1 & 0xffff); | |
247 | h2 = (signed16)(v2 & 0xffff); | |
248 | if (op == 0) // ADD | |
249 | h0 = (signed32)h1 + (signed32)h2; | |
250 | else // SUB | |
251 | h0 = (signed32)h1 - (signed32)h2; | |
252 | if (round == 1) | |
253 | h0 = (h0 + 1) >> 1; | |
254 | else | |
255 | h0 = h0 >> 1; | |
256 | result |= ((unsigned32)((unsigned16)h0) << i); | |
257 | } | |
258 | GPR[rd] = EXTEND32 (result); | |
259 | } | |
260 | ||
261 | // op: 0 = ADD, 1 = SUB | |
262 | // round: 0 = no rounding, 1 = rounding | |
263 | :function:::void:do_qh_w_op:int rd, int rs, int rt, int op, int round | |
264 | { | |
265 | int i; | |
266 | signed64 v0; | |
267 | signed32 v1 = (signed32)GPR[rs]; | |
268 | signed32 v2 = (signed32)GPR[rt]; | |
269 | if (op == 0) // ADD | |
270 | v0 = (signed64)v1 + (signed64)v2; | |
271 | else // SUB | |
272 | v0 = (signed64)v1 - (signed64)v2; | |
273 | if (round == 1) | |
274 | v0 = (v0 + 1) >> 1; | |
275 | else | |
276 | v0 = v0 >> 1; | |
277 | GPR[rd] = EXTEND32 (v0); | |
278 | } | |
279 | ||
280 | // op: 0 = DPAX, 1 = DPSX | |
281 | :function:::void:do_x_w_ph_dot_product:int ac, int rs, int rt, int op | |
282 | { | |
283 | int i; | |
284 | unsigned32 v1 = GPR[rs]; | |
285 | unsigned32 v2 = GPR[rt]; | |
286 | signed16 h1, h2; | |
287 | signed32 result; | |
288 | unsigned32 lo = DSPLO(ac); | |
289 | unsigned32 hi = DSPHI(ac); | |
290 | signed64 prod = (signed64)((((unsigned64)hi) << 32) + (unsigned64)lo); | |
291 | for (i = 0; i < 32; i += 16, v1 >>= 16, v2 <<= 16) | |
292 | { | |
293 | h1 = (signed16)(v1 & 0xffff); | |
294 | h2 = (signed16)((v2 & 0xffff0000) >> 16); | |
295 | result = (signed32)h1 * (signed32)h2; | |
296 | if (op == 0) // DPAX | |
297 | prod += (signed64)result; | |
298 | else // DPSX | |
299 | prod -= (signed64)result; | |
300 | } | |
301 | DSPLO(ac) = EXTEND32 (prod); | |
302 | DSPHI(ac) = EXTEND32 (prod >> 32); | |
303 | } | |
304 | ||
305 | // op: 0 = DPAQX, 1 = DPSQX | |
306 | // sat: 0 = no saturation, 1 = saturation of the accumulator | |
307 | :function:::void:do_qx_w_ph_dot_product:int ac, int rs, int rt, int op, int sat | |
308 | { | |
309 | int i; | |
310 | unsigned32 v1 = GPR[rs]; | |
311 | unsigned32 v2 = GPR[rt]; | |
312 | signed16 h1, h2; | |
313 | signed32 result; | |
314 | unsigned32 lo = DSPLO(ac); | |
315 | unsigned32 hi = DSPHI(ac); | |
316 | signed64 prod = (signed64)((((unsigned64)hi) << 32) + (unsigned64)lo); | |
317 | signed64 max, min; | |
318 | for (i = 0; i < 32; i += 16, v1 >>= 16, v2 <<= 16) | |
319 | { | |
320 | h1 = (signed16)(v1 & 0xffff); | |
321 | h2 = (signed16)((v2 & 0xffff0000) >> 16); | |
322 | if (h1 == (signed16)0x8000 && h2 == (signed16)0x8000) | |
323 | { | |
324 | DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac)); | |
325 | result = 0x7fffffff; | |
326 | } | |
327 | else | |
328 | result = ((signed32)h1 * (signed32)h2) << 1; | |
329 | if (op == 0) // DPAQX | |
330 | prod += (signed64)result; | |
331 | else // DPSQX | |
332 | prod -= (signed64)result; | |
333 | } | |
334 | // Saturation on the accumulator. | |
335 | if (sat == 1) | |
336 | { | |
337 | max = (signed64) 0x7fffffffLL; | |
338 | min = (signed64) 0xffffffff80000000LL; | |
339 | if (prod > max) | |
340 | { | |
341 | DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac)); | |
342 | prod = max; | |
343 | } | |
344 | else if (prod < min) | |
345 | { | |
346 | DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac)); | |
347 | prod = min; | |
348 | } | |
349 | } | |
350 | DSPLO(ac) = EXTEND32 (prod); | |
351 | DSPHI(ac) = EXTEND32 (prod >> 32); | |
352 | } | |
353 | ||
354 | 011111,00000,5.RT,5.RD,00001,010010:SPECIAL3:32::ABSQ_S.QB | |
355 | "absq_s.qb r<RD>, r<RT>" | |
356 | *dsp2: | |
357 | { | |
358 | int i; | |
359 | signed8 q0; | |
360 | unsigned32 v1 = GPR[RT]; | |
361 | unsigned32 result = 0; | |
362 | for (i = 0; i < 32; i += 8, v1 >>= 8) | |
363 | { | |
364 | q0 = (signed8)(v1 & 0xff); | |
365 | if (q0 == (signed8)0x80) | |
366 | { | |
367 | DSPCR |= DSPCR_OUFLAG4; | |
368 | q0 = 0x7f; | |
369 | } | |
370 | else if (q0 & 0x80) | |
371 | q0 = -q0; | |
372 | result |= ((unsigned32)((unsigned8)q0) << i); | |
373 | } | |
374 | GPR[RD] = EXTEND32 (result); | |
375 | } | |
376 | ||
377 | 011111,5.RS,5.RT,5.RD,01000,010000:SPECIAL3:32::ADDU.PH | |
378 | "addu.ph r<RD>, r<RS>, r<RT>" | |
379 | *dsp2: | |
380 | { | |
381 | do_u_ph_op (SD_, RD, RS, RT, 0, 0); | |
382 | } | |
383 | ||
384 | 011111,5.RS,5.RT,5.RD,01100,010000:SPECIAL3:32::ADDU_S.PH | |
385 | "addu_s.ph r<RD>, r<RS>, r<RT>" | |
386 | *dsp2: | |
387 | { | |
388 | do_u_ph_op (SD_, RD, RS, RT, 0, 1); | |
389 | } | |
390 | ||
391 | 011111,5.RS,5.RT,5.RD,00000,011000:SPECIAL3:32::ADDUH.QB | |
392 | "adduh.qb r<RD>, r<RS>, r<RT>" | |
393 | *dsp2: | |
394 | { | |
395 | do_uh_qb_op (SD_, RD, RS, RT, 0, 0); | |
396 | } | |
397 | ||
398 | 011111,5.RS,5.RT,5.RD,00010,011000:SPECIAL3:32::ADDUH_R.QB | |
399 | "adduh_r.qb r<RD>, r<RS>, r<RT>" | |
400 | *dsp2: | |
401 | { | |
402 | do_uh_qb_op (SD_, RD, RS, RT, 0, 1); | |
403 | } | |
404 | ||
405 | 011111,5.RS,5.RT,5.SA,00000,110001:SPECIAL3:32::APPEND | |
406 | "append r<RT>, r<RS>, <SA>" | |
407 | *dsp2: | |
408 | { | |
409 | unsigned32 v0 = GPR[RS]; | |
410 | unsigned32 v1 = GPR[RT]; | |
411 | unsigned32 result; | |
412 | unsigned32 mask = (1 << SA) - 1; | |
413 | result = (v1 << SA) | (v0 & mask); | |
414 | GPR[RT] = EXTEND32 (result); | |
415 | } | |
416 | ||
417 | 011111,5.RS,5.RT,000,2.BP,10000,110001:SPECIAL3:32::BALIGN | |
418 | "balign r<RT>, r<RS>, <BP>" | |
419 | *dsp2: | |
420 | { | |
421 | unsigned32 v0 = GPR[RS]; | |
422 | unsigned32 v1 = GPR[RT]; | |
423 | unsigned32 result; | |
424 | if (BP == 0) | |
425 | result = v1; | |
426 | else | |
427 | result = (v1 << 8 * BP) | (v0 >> 8 * (4 - BP)); | |
428 | GPR[RT] = EXTEND32 (result); | |
429 | } | |
430 | ||
431 | 011111,5.RS,5.RT,5.RD,11000,010001:SPECIAL3:32::CMPGDU.EQ.QB | |
432 | "cmpgdu.eq.qb r<RD>, r<RS>, r<RT>" | |
433 | *dsp2: | |
434 | { | |
435 | do_qb_cmpgdu (SD_, RD, RS, RT, 0); | |
436 | } | |
437 | ||
438 | 011111,5.RS,5.RT,5.RD,11001,010001:SPECIAL3:32::CMPGDU.LT.QB | |
439 | "cmpgdu.lt.qb r<RD>, r<RS>, r<RT>" | |
440 | *dsp2: | |
441 | { | |
442 | do_qb_cmpgdu (SD_, RD, RS, RT, 1); | |
443 | } | |
444 | ||
445 | 011111,5.RS,5.RT,5.RD,11010,010001:SPECIAL3:32::CMPGDU.LE.QB | |
446 | "cmpgdu.le.qb r<RD>, r<RS>, r<RT>" | |
447 | *dsp2: | |
448 | { | |
449 | do_qb_cmpgdu (SD_, RD, RS, RT, 2); | |
450 | } | |
451 | ||
452 | 011111,5.RS,5.RT,000,2.AC,00000,110000:SPECIAL3:32::DPA.W.PH | |
453 | "dpa.w.ph ac<AC>, r<RS>, r<RT>" | |
454 | *dsp2: | |
455 | { | |
456 | do_w_ph_dot_product (SD_, AC, RS, RT, 0); | |
457 | } | |
458 | ||
459 | 011111,5.RS,5.RT,000,2.AC,00001,110000:SPECIAL3:32::DPS.W.PH | |
460 | "dps.w.ph ac<AC>, r<RS>, r<RT>" | |
461 | *dsp2: | |
462 | { | |
463 | do_w_ph_dot_product (SD_, AC, RS, RT, 1); | |
464 | } | |
465 | ||
466 | 011111,5.RS,5.RT,5.RD,01100,011000:SPECIAL3:32::MUL.PH | |
467 | "mul.ph r<RD>, r<RS>, r<RT>" | |
468 | *dsp2: | |
469 | { | |
470 | do_ph_op (SD_, RD, RS, RT, 2, 0); | |
471 | } | |
472 | ||
473 | 011111,5.RS,5.RT,5.RD,01110,011000:SPECIAL3:32::MUL_S.PH | |
474 | "mul_s.ph r<RD>, r<RS>, r<RT>" | |
475 | *dsp2: | |
476 | { | |
477 | do_ph_op (SD_, RD, RS, RT, 2, 1); | |
478 | } | |
479 | ||
480 | 011111,5.RS,5.RT,5.RD,10111,011000:SPECIAL3:32::MULQ_RS.W | |
481 | "mulq_rs.w r<RD>, r<RS>, r<RT>" | |
482 | *dsp2: | |
483 | { | |
484 | do_w_mulq (SD_, RD, RS, RT, 1); | |
485 | } | |
486 | ||
487 | 011111,5.RS,5.RT,5.RD,11110,010000:SPECIAL3:32::MULQ_S.PH | |
488 | "mulq_s.ph r<RD>, r<RS>, r<RT>" | |
489 | *dsp2: | |
490 | { | |
491 | do_ph_mulq (SD_, RD, RS, RT, 0); | |
492 | } | |
493 | ||
494 | 011111,5.RS,5.RT,5.RD,10110,011000:SPECIAL3:32::MULQ_S.W | |
495 | "mulq_s.w r<RD>, r<RS>, r<RT>" | |
496 | *dsp2: | |
497 | { | |
498 | do_w_mulq (SD_, RD, RS, RT, 0); | |
499 | } | |
500 | ||
501 | 011111,5.RS,5.RT,000,2.AC,00010,110000:SPECIAL3:32::MULSA.W.PH | |
502 | "mulsa.w.ph ac<AC>, r<RS>, r<RT>" | |
503 | *dsp2: | |
504 | { | |
505 | int i; | |
506 | unsigned32 v1 = GPR[RS]; | |
507 | unsigned32 v2 = GPR[RT]; | |
508 | signed16 h1, h2; | |
509 | signed32 result; | |
510 | unsigned32 lo = DSPLO(AC); | |
511 | unsigned32 hi = DSPHI(AC); | |
512 | signed64 prod = (signed64)((((unsigned64)hi) << 32) + (unsigned64)lo); | |
513 | for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16) | |
514 | { | |
515 | h1 = (signed16)(v1 & 0xffff); | |
516 | h2 = (signed16)(v2 & 0xffff); | |
517 | result = (signed32)h1 * (signed32)h2; | |
518 | ||
519 | if (i == 0) | |
520 | prod -= (signed64) result; | |
521 | else | |
522 | prod += (signed64) result; | |
523 | } | |
524 | DSPLO(AC) = EXTEND32 (prod); | |
525 | DSPHI(AC) = EXTEND32 (prod >> 32); | |
526 | } | |
527 | ||
528 | 011111,5.RS,5.RT,5.RD,01101,010001:SPECIAL3:32::PRECR.QB.PH | |
529 | "precr.qb.ph r<RD>, r<RS>, r<RT>" | |
530 | *dsp2: | |
531 | { | |
532 | unsigned32 v1 = GPR[RS]; | |
533 | unsigned32 v2 = GPR[RT]; | |
534 | unsigned32 tempu = (v1 & 0xff0000) >> 16; | |
535 | unsigned32 tempv = (v1 & 0xff); | |
536 | unsigned32 tempw = (v2 & 0xff0000) >> 16; | |
537 | unsigned32 tempx = (v2 & 0xff); | |
538 | GPR[RD] = EXTEND32 ((tempu << 24) | (tempv << 16) | (tempw << 8) | tempx); | |
539 | } | |
540 | ||
541 | 011111,5.RS,5.RT,5.SA,11110,010001:SPECIAL3:32::PRECR_SRA.PH.W | |
542 | "precr_sra.ph.w r<RT>, r<RS>, <SA>" | |
543 | *dsp2: | |
544 | { | |
545 | do_precr_sra (SD_, RT, RS, SA, 0); | |
546 | } | |
547 | ||
548 | 011111,5.RS,5.RT,5.SA,11111,010001:SPECIAL3:32::PRECR_SRA_R.PH.W | |
549 | "precr_sra_r.ph.w r<RT>, r<RS>, <SA>" | |
550 | *dsp2: | |
551 | { | |
552 | do_precr_sra (SD_, RT, RS, SA, 1); | |
553 | } | |
554 | ||
555 | 011111,5.RS,5.RT,5.SA,00001,110001:SPECIAL3:32::PREPEND | |
556 | "prepend r<RT>, r<RS>, <SA>" | |
557 | *dsp2: | |
558 | { | |
559 | unsigned32 v0 = GPR[RS]; | |
560 | unsigned32 v1 = GPR[RT]; | |
561 | unsigned32 result; | |
562 | if (SA == 0) | |
563 | result = v1; | |
564 | else | |
565 | result = (v0 << (32 - SA)) | (v1 >> SA); | |
566 | GPR[RT] = EXTEND32 (result); | |
567 | } | |
568 | ||
569 | 011111,00,3.SHIFT3,5.RT,5.RD,00100,010011:SPECIAL3:32::SHRA.QB | |
570 | "shra.qb r<RD>, r<RT>, <SHIFT3>" | |
571 | *dsp2: | |
572 | { | |
573 | do_qb_shra (SD_, RD, RT, SHIFT3, 0); | |
574 | } | |
575 | ||
576 | 011111,00,3.SHIFT3,5.RT,5.RD,00101,010011:SPECIAL3:32::SHRA_R.QB | |
577 | "shra_r.qb r<RD>, r<RT>, <SHIFT3>" | |
578 | *dsp2: | |
579 | { | |
580 | do_qb_shra (SD_, RD, RT, SHIFT3, 1); | |
581 | } | |
582 | ||
583 | 011111,5.RS,5.RT,5.RD,00110,010011:SPECIAL3:32::SHRAV.QB | |
584 | "shrav.qb r<RD>, r<RT>, r<RS>" | |
585 | *dsp2: | |
586 | { | |
587 | unsigned32 shift = GPR[RS] & 0x7; | |
588 | do_qb_shra (SD_, RD, RT, shift, 0); | |
589 | } | |
590 | ||
591 | 011111,5.RS,5.RT,5.RD,00111,010011:SPECIAL3:32::SHRAV_R.QB | |
592 | "shrav_r.qb r<RD>, r<RT>, r<RS>" | |
593 | *dsp2: | |
594 | { | |
595 | unsigned32 shift = GPR[RS] & 0x7; | |
596 | do_qb_shra (SD_, RD, RT, shift, 1); | |
597 | } | |
598 | ||
599 | 011111,0,4.SHIFT4,5.RT,5.RD,11001,010011:SPECIAL3:32::SHRL.PH | |
600 | "shrl.ph r<RD>, r<RT>, <SHIFT4>" | |
601 | *dsp2: | |
602 | { | |
603 | do_ph_shrl (SD_, RD, RT, SHIFT4); | |
604 | } | |
605 | ||
606 | 011111,5.RS,5.RT,5.RD,11011,010011:SPECIAL3:32::SHRLV.PH | |
607 | "shrlv.ph r<RD>, r<RT>, r<RS>" | |
608 | *dsp2: | |
609 | { | |
610 | unsigned32 shift = GPR[RS] & 0xf; | |
611 | do_ph_shrl (SD_, RD, RT, shift); | |
612 | } | |
613 | ||
614 | 011111,5.RS,5.RT,5.RD,01001,010000:SPECIAL3:32::SUBU.PH | |
615 | "subu.ph r<RD>, r<RS>, r<RT>" | |
616 | *dsp2: | |
617 | { | |
618 | do_u_ph_op (SD_, RD, RS, RT, 1, 0); | |
619 | } | |
620 | ||
621 | 011111,5.RS,5.RT,5.RD,01101,010000:SPECIAL3:32::SUBU_S.PH | |
622 | "subu_s.ph r<RD>, r<RS>, r<RT>" | |
623 | *dsp2: | |
624 | { | |
625 | do_u_ph_op (SD_, RD, RS, RT, 1, 1); | |
626 | } | |
627 | ||
628 | 011111,5.RS,5.RT,5.RD,00001,011000:SPECIAL3:32::SUBUH.QB | |
629 | "subuh.qb r<RD>, r<RS>, r<RT>" | |
630 | *dsp2: | |
631 | { | |
632 | do_uh_qb_op (SD_, RD, RS, RT, 1, 0); | |
633 | } | |
634 | ||
635 | 011111,5.RS,5.RT,5.RD,00011,011000:SPECIAL3:32::SUBUH_R.QB | |
636 | "subuh_r.qb r<RD>, r<RS>, r<RT>" | |
637 | *dsp2: | |
638 | { | |
639 | do_uh_qb_op (SD_, RD, RS, RT, 1, 1); | |
640 | } | |
641 | ||
642 | 011111,5.RS,5.RT,5.RD,01000,011000:SPECIAL3:32::ADDQH.PH | |
643 | "addqh.ph r<RD>, r<RS>, r<RT>" | |
644 | *dsp2: | |
645 | { | |
646 | do_qh_ph_op (SD_, RD, RS, RT, 0, 0); | |
647 | } | |
648 | ||
649 | 011111,5.RS,5.RT,5.RD,01010,011000:SPECIAL3:32::ADDQH_R.PH | |
650 | "addqh_r.ph r<RD>, r<RS>, r<RT>" | |
651 | *dsp2: | |
652 | { | |
653 | do_qh_ph_op (SD_, RD, RS, RT, 0, 1); | |
654 | } | |
655 | ||
656 | 011111,5.RS,5.RT,5.RD,10000,011000:SPECIAL3:32::ADDQH.W | |
657 | "addqh.w r<RD>, r<RS>, r<RT>" | |
658 | *dsp2: | |
659 | { | |
660 | do_qh_w_op (SD_, RD, RS, RT, 0, 0); | |
661 | } | |
662 | ||
663 | 011111,5.RS,5.RT,5.RD,10010,011000:SPECIAL3:32::ADDQH_R.W | |
664 | "addqh_r.w r<RD>, r<RS>, r<RT>" | |
665 | *dsp2: | |
666 | { | |
667 | do_qh_w_op (SD_, RD, RS, RT, 0, 1); | |
668 | } | |
669 | ||
670 | 011111,5.RS,5.RT,5.RD,01001,011000:SPECIAL3:32::SUBQH.PH | |
671 | "subqh.ph r<RD>, r<RS>, r<RT>" | |
672 | *dsp2: | |
673 | { | |
674 | do_qh_ph_op (SD_, RD, RS, RT, 1, 0); | |
675 | } | |
676 | ||
677 | 011111,5.RS,5.RT,5.RD,01011,011000:SPECIAL3:32::SUBQH_R.PH | |
678 | "subqh_r.ph r<RD>, r<RS>, r<RT>" | |
679 | *dsp2: | |
680 | { | |
681 | do_qh_ph_op (SD_, RD, RS, RT, 1, 1); | |
682 | } | |
683 | ||
684 | 011111,5.RS,5.RT,5.RD,10001,011000:SPECIAL3:32::SUBQH.W | |
685 | "subqh.w r<RD>, r<RS>, r<RT>" | |
686 | *dsp2: | |
687 | { | |
688 | do_qh_w_op (SD_, RD, RS, RT, 1, 0); | |
689 | } | |
690 | ||
691 | 011111,5.RS,5.RT,5.RD,10011,011000:SPECIAL3:32::SUBQH_R.W | |
692 | "subqh_r.w r<RD>, r<RS>, r<RT>" | |
693 | *dsp2: | |
694 | { | |
695 | do_qh_w_op (SD_, RD, RS, RT, 1, 1); | |
696 | } | |
697 | ||
698 | 011111,5.RS,5.RT,000,2.AC,01000,110000:SPECIAL3:32::DPAX.W.PH | |
699 | "dpax.w.ph ac<AC>, r<RS>, r<RT>" | |
700 | *dsp2: | |
701 | { | |
702 | do_x_w_ph_dot_product (SD_, AC, RS, RT, 0); | |
703 | } | |
704 | ||
705 | 011111,5.RS,5.RT,000,2.AC,01001,110000:SPECIAL3:32::DPSX.W.PH | |
706 | "dpsx.w.ph ac<AC>, r<RS>, r<RT>" | |
707 | *dsp2: | |
708 | { | |
709 | do_x_w_ph_dot_product (SD_, AC, RS, RT, 1); | |
710 | } | |
711 | ||
712 | 011111,5.RS,5.RT,000,2.AC,11000,110000:SPECIAL3:32::DPAQX_S.W.PH | |
713 | "dpaqx_s.w.ph ac<AC>, r<RS>, r<RT>" | |
714 | *dsp2: | |
715 | { | |
716 | do_qx_w_ph_dot_product (SD_, AC, RS, RT, 0, 0); | |
717 | } | |
718 | ||
719 | 011111,5.RS,5.RT,000,2.AC,11010,110000:SPECIAL3:32::DPAQX_SA.W.PH | |
720 | "dpaqx_sa.w.ph ac<AC>, r<RS>, r<RT>" | |
721 | *dsp2: | |
722 | { | |
723 | do_qx_w_ph_dot_product (SD_, AC, RS, RT, 0, 1); | |
724 | } | |
725 | ||
726 | 011111,5.RS,5.RT,000,2.AC,11001,110000:SPECIAL3:32::DPSQX_S.W.PH | |
727 | "dpsqx_s.w.ph ac<AC>, r<RS>, r<RT>" | |
728 | *dsp2: | |
729 | { | |
730 | do_qx_w_ph_dot_product (SD_, AC, RS, RT, 1, 0); | |
731 | } | |
732 | ||
733 | 011111,5.RS,5.RT,000,2.AC,11011,110000:SPECIAL3:32::DPSQX_SA.W.PH | |
734 | "dpsqx_sa.w.ph ac<AC>, r<RS>, r<RT>" | |
735 | *dsp2: | |
736 | { | |
737 | do_qx_w_ph_dot_product (SD_, AC, RS, RT, 1, 1); | |
738 | } |