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cc9bc932 | 1 | /* This file is part of the program GDB, the GNU debugger. |
3fa454e9 FCE |
2 | |
3 | Copyright (C) 1998 Free Software Foundation, Inc. | |
4 | Contributed by Cygnus Solutions. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2 of the License, or | |
9 | (at your option) any later version. | |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program; if not, write to the Free Software | |
18 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
19 | ||
20 | */ | |
21 | ||
22 | ||
23 | #include "sim-main.h" | |
da040f2a | 24 | #include "hw-main.h" |
3fa454e9 FCE |
25 | |
26 | /* DEVICE | |
27 | ||
28 | ||
29 | tx3904cpu - tx3904 cpu virtual device | |
30 | ||
31 | ||
32 | DESCRIPTION | |
33 | ||
34 | ||
35 | Implements the external tx3904 functionality. This includes the | |
36 | delivery of of interrupts generated from other devices and the | |
37 | handling of device specific registers. | |
38 | ||
39 | ||
40 | PROPERTIES | |
41 | ||
42 | none | |
43 | ||
44 | ||
45 | PORTS | |
46 | ||
47 | ||
48 | reset (input) | |
49 | ||
50 | Currently ignored. | |
51 | ||
52 | ||
53 | nmi (input) | |
54 | ||
55 | Deliver a non-maskable interrupt to the processor. | |
56 | ||
57 | ||
58 | level (input) | |
59 | ||
60 | Deliver a maskable interrupt of given level, corresponding to | |
61 | IP[5:0], to processor. | |
62 | ||
63 | ||
64 | ||
65 | BUGS | |
66 | ||
67 | ||
68 | When delivering an interrupt, this code assumes that there is only | |
69 | one processor (number 0). | |
70 | ||
71 | This code does not attempt to be efficient at handling pending | |
72 | interrupts. It simply schedules the interrupt delivery handler | |
73 | every instruction cycle until all pending interrupts go away. An | |
74 | alternative implementation might modify instructions that change | |
75 | the PSW and have them check to see if the change makes an interrupt | |
76 | delivery possible. | |
77 | ||
78 | */ | |
79 | ||
80 | ||
81 | ||
82 | struct tx3904cpu { | |
83 | /* Pending interrupts for delivery by event handler */ | |
84 | int pending_reset, pending_nmi, pending_level; | |
85 | }; | |
86 | ||
87 | ||
88 | ||
89 | /* input port ID's */ | |
90 | ||
91 | enum { | |
92 | RESET_PORT, | |
93 | NMI_PORT, | |
94 | LEVEL_PORT, | |
95 | }; | |
96 | ||
97 | ||
98 | static const struct hw_port_descriptor tx3904cpu_ports[] = { | |
99 | ||
100 | /* interrupt inputs */ | |
101 | { "reset", RESET_PORT, 0, input_port, }, | |
102 | { "nmi", NMI_PORT, 0, input_port, }, | |
103 | { "level", LEVEL_PORT, 0, input_port, }, | |
104 | ||
105 | { NULL, }, | |
106 | }; | |
107 | ||
108 | ||
109 | /* Finish off the partially created hw device. Attach our local | |
110 | callbacks. Wire up our port names etc */ | |
111 | ||
da040f2a | 112 | static hw_port_event_method tx3904cpu_port_event; |
3fa454e9 FCE |
113 | |
114 | ||
115 | ||
116 | static void | |
117 | tx3904cpu_finish (struct hw *me) | |
118 | { | |
119 | struct tx3904cpu *controller; | |
120 | ||
121 | controller = HW_ZALLOC (me, struct tx3904cpu); | |
122 | set_hw_data (me, controller); | |
123 | set_hw_ports (me, tx3904cpu_ports); | |
124 | set_hw_port_event (me, tx3904cpu_port_event); | |
125 | ||
126 | /* Initialize the pending interrupt flags */ | |
127 | controller->pending_level = 0; | |
128 | controller->pending_reset = 0; | |
129 | controller->pending_nmi = 0; | |
130 | } | |
131 | ||
132 | ||
133 | ||
134 | /* An event arrives on an interrupt port */ | |
135 | ||
136 | static void | |
137 | deliver_tx3904cpu_interrupt (struct hw *me, | |
138 | void *data) | |
139 | { | |
140 | struct tx3904cpu *controller = hw_data (me); | |
da040f2a FCE |
141 | SIM_DESC sd = hw_system (me); |
142 | sim_cpu *cpu = STATE_CPU (sd, 0); /* NB: fix CPU 0. */ | |
3fa454e9 FCE |
143 | address_word cia = CIA_GET (cpu); |
144 | ||
145 | #define CPU cpu | |
146 | #define SD current_state | |
147 | ||
148 | if (controller->pending_reset) | |
149 | { | |
150 | controller->pending_reset = 0; | |
151 | HW_TRACE ((me, "reset pc=0x%08lx", (long) CIA_GET (cpu))); | |
152 | SignalExceptionNMIReset(); | |
153 | } | |
154 | else if (controller->pending_nmi) | |
155 | { | |
156 | controller->pending_nmi = 0; | |
157 | HW_TRACE ((me, "nmi pc=0x%08lx", (long) CIA_GET (cpu))); | |
158 | SignalExceptionNMIReset(); | |
159 | } | |
160 | else if (controller->pending_level) | |
161 | { | |
162 | HW_TRACE ((me, "interrupt level=%d pc=0x%08lx sr=0x%08lx", | |
163 | controller->pending_level, | |
164 | (long) CIA_GET (cpu), (long) SR)); | |
165 | ||
cc9bc932 FCE |
166 | /* Clear CAUSE register. It may stay this way if the interrupt |
167 | was cleared with a negative pending_level. */ | |
168 | CAUSE &= ~ (cause_IP_mask << cause_IP_shift); | |
3fa454e9 | 169 | |
cc9bc932 | 170 | if(controller->pending_level > 0) /* interrupt set */ |
3fa454e9 | 171 | { |
cc9bc932 FCE |
172 | /* set hardware-interrupt subfields of CAUSE register */ |
173 | CAUSE |= (controller->pending_level & cause_IP_mask) << cause_IP_shift; | |
174 | ||
175 | /* check for enabled / unmasked interrupts */ | |
176 | if((SR & status_IEc) && | |
177 | (controller->pending_level & ((SR >> status_IM_shift) & status_IM_mask))) | |
178 | { | |
179 | controller->pending_level = 0; | |
180 | SignalExceptionInterrupt(); | |
181 | } | |
182 | else | |
183 | { | |
184 | /* reschedule soon */ | |
185 | hw_event_queue_schedule (me, 1, deliver_tx3904cpu_interrupt, NULL); | |
186 | } | |
187 | } /* interrupt set */ | |
3fa454e9 FCE |
188 | } |
189 | #undef CPU cpu | |
190 | #undef SD current_state | |
191 | } | |
192 | ||
193 | ||
194 | static void | |
195 | tx3904cpu_port_event (struct hw *me, | |
196 | int my_port, | |
197 | struct hw *source, | |
198 | int source_port, | |
199 | int level) | |
200 | { | |
201 | struct tx3904cpu *controller = hw_data (me); | |
202 | ||
203 | switch (my_port) | |
204 | { | |
205 | case RESET_PORT: | |
206 | controller->pending_reset = 1; | |
207 | HW_TRACE ((me, "port-in reset")); | |
208 | break; | |
209 | ||
210 | case NMI_PORT: | |
211 | controller->pending_nmi = 1; | |
212 | HW_TRACE ((me, "port-in nmi")); | |
213 | break; | |
214 | ||
215 | case LEVEL_PORT: | |
cc9bc932 FCE |
216 | /* level == 0 means that the interrupt was cleared */ |
217 | if(level == 0) | |
218 | controller->pending_level = -1; /* signal end of interrupt */ | |
219 | else | |
220 | controller->pending_level = level; | |
3fa454e9 FCE |
221 | HW_TRACE ((me, "port-in level=%d", level)); |
222 | break; | |
223 | ||
224 | default: | |
225 | hw_abort (me, "bad switch"); | |
226 | break; | |
227 | } | |
228 | ||
229 | /* Schedule an event to be delivered immediately after current | |
230 | instruction. */ | |
231 | hw_event_queue_schedule (me, 0, deliver_tx3904cpu_interrupt, NULL); | |
232 | } | |
233 | ||
234 | ||
da040f2a | 235 | const struct hw_descriptor dv_tx3904cpu_descriptor[] = { |
3fa454e9 FCE |
236 | { "tx3904cpu", tx3904cpu_finish, }, |
237 | { NULL }, | |
238 | }; |