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Rewrite the mipsI/II/III pending-slot code.
[deliverable/binutils-gdb.git] / sim / mips / interp.c
CommitLineData
8bae0a0c
JSC		 1/*> interp.c <*/
2/* Simulator for the MIPS architecture.
3
4 This file is part of the MIPS sim
5
6 THIS SOFTWARE IS NOT COPYRIGHTED
7
8 Cygnus offers the following for use in the public domain. Cygnus
9 makes no warranty with regard to the software or it's performance
10 and the user accepts the software "AS IS" with all faults.
11
12 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
13 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
14 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
15
16 $Revision$
17 $Author$
e3d12c65 18 $Date$
8bae0a0c
JSC		 19
20NOTEs:
21
8bae0a0c
JSC		 22The IDT monitor (found on the VR4300 board), seems to lie about
23register contents. It seems to treat the registers as sign-extended
2432-bit values. This cause *REAL* problems when single-stepping 64-bit
25code on the hardware.
26
27*/
28
e2f8ffb7
AC		 29/* The TRACE manifests enable the provision of extra features. If they
30 are not defined then a simpler (quicker) simulator is constructed
31 without the required run-time checks, etc. */
8bae0a0c
JSC		 32#if 1 /* 0 to allow user build selection, 1 to force inclusion */
33#define TRACE (1)
8bae0a0c
JSC		 34#endif
35
2e61a3ad
AC		 36#include "bfd.h"
37#include "sim-main.h"
38#include "sim-utils.h"
39#include "sim-options.h"
50a2a691 40#include "sim-assert.h"
2e61a3ad 41
4fa134be
ILT		 42#include "config.h"
43
8bae0a0c
JSC		 44#include <stdio.h>
45#include <stdarg.h>
46#include <ansidecl.h>
8bae0a0c
JSC		 47#include <ctype.h>
48#include <limits.h>
49#include <math.h>
4fa134be
ILT		 50#ifdef HAVE_STDLIB_H
51#include <stdlib.h>
52#endif
53#ifdef HAVE_STRING_H
54#include <string.h>
55#else
56#ifdef HAVE_STRINGS_H
57#include <strings.h>
58#endif
59#endif
8bae0a0c
JSC		 60
61#include "getopt.h"
62#include "libiberty.h"
9d52bcb7 63#include "bfd.h"
8bae0a0c 64#include "callback.h" /* GDB simulator callback interface */
e3d12c65 65#include "remote-sim.h" /* GDB simulator interface */
8bae0a0c 66
f24b7b69
JSC		 67#include "sysdep.h"
68
53b9417e
DE		 69#ifndef PARAMS
70#define PARAMS(x)
71#endif
72
73char* pr_addr PARAMS ((SIM_ADDR addr));
87e43259 74char* pr_uword64 PARAMS ((uword64 addr));
53b9417e 75
f24b7b69 76
8bae0a0c 77/* Get the simulator engine description, without including the code: */
192ae475
AC		 78#if (WITH_IGEN)
79#define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3)
80#else
8bae0a0c 81#define SIM_MANIFESTS
284e759d 82#include "oengine.c"
8bae0a0c 83#undef SIM_MANIFESTS
192ae475 84#endif
8bae0a0c 85
01737f42
AC		 86/* Within interp.c we refer to the sim_state and sim_cpu directly. */
87#define SD sd
88#define CPU cpu
89
f7481d45 90
8bae0a0c
JSC		 91/* The following reserved instruction value is used when a simulator
92 trap is required. NOTE: Care must be taken, since this value may be
93 used in later revisions of the MIPS ISA. */
53b9417e
DE		 94#define RSVD_INSTRUCTION (0x00000005)
95#define RSVD_INSTRUCTION_MASK (0xFC00003F)
96
97#define RSVD_INSTRUCTION_ARG_SHIFT 6
98#define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF
99
8bae0a0c 100
6eedf3f4
MA		 101/* Bits in the Debug register */
102#define Debug_DBD 0x80000000 /* Debug Branch Delay */
103#define Debug_DM 0x40000000 /* Debug Mode */
104#define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */
105
106
107
8bae0a0c 108
8bae0a0c 109
e3d12c65
DE		 110/*---------------------------------------------------------------------------*/
111/*-- GDB simulator interface ------------------------------------------------*/
112/*---------------------------------------------------------------------------*/
113
0c2c5f61 114static void ColdReset PARAMS((SIM_DESC sd));
e3d12c65
DE		 115
116/*---------------------------------------------------------------------------*/
117
8bae0a0c 118
8bae0a0c 119
8bae0a0c 120#define DELAYSLOT() {\
0c2c5f61 121 if (STATE & simDELAYSLOT)\
18c64df6 122 sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\
0c2c5f61 123 STATE |= simDELAYSLOT;\
8bae0a0c
JSC		 124 }
125
aaff8437
ILT		 126#define JALDELAYSLOT() {\
127 DELAYSLOT ();\
0c2c5f61 128 STATE |= simJALDELAYSLOT;\
aaff8437
ILT		 129 }
130
8bae0a0c 131#define NULLIFY() {\
0c2c5f61
AC		 132 STATE &= ~simDELAYSLOT;\
133 STATE |= simSKIPNEXT;\
8bae0a0c
JSC		 134 }
135
6eedf3f4 136#define CANCELDELAYSLOT() {\
0c2c5f61
AC		 137 DSSTATE = 0;\
138 STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\
6eedf3f4
MA		 139 }
140
0c2c5f61
AC		 141#define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0)
142#define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0)
aaff8437 143
a9f7253f
JSC		 144#define K0BASE (0x80000000)
145#define K0SIZE (0x20000000)
146#define K1BASE (0xA0000000)
147#define K1SIZE (0x20000000)
525d929e
AC		 148#define MONITOR_BASE (0xBFC00000)
149#define MONITOR_SIZE (1 << 11)
150#define MEM_SIZE (2 << 20)
a9f7253f 151
8bae0a0c 152#if defined(TRACE)
4fa134be 153static char *tracefile = "trace.din"; /* default filename for trace log */
030843d7 154FILE *tracefh = NULL;
18c64df6 155static void open_trace PARAMS((SIM_DESC sd));
8bae0a0c
JSC		 156#endif /* TRACE */
157
22de994d
AC		 158#define OPTION_DINERO_TRACE 200
159#define OPTION_DINERO_FILE 201
160
50a2a691
AC		 161static SIM_RC
162mips_option_handler (sd, opt, arg)
163 SIM_DESC sd;
164 int opt;
165 char *arg;
2e61a3ad 166{
01737f42 167 int cpu_nr;
50a2a691
AC		 168 switch (opt)
169 {
22de994d 170 case OPTION_DINERO_TRACE: /* ??? */
50a2a691
AC		 171#if defined(TRACE)
172 /* Eventually the simTRACE flag could be treated as a toggle, to
173 allow external control of the program points being traced
174 (i.e. only from main onwards, excluding the run-time setup,
175 etc.). */
01737f42 176 for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++)
50a2a691 177 {
01737f42
AC		 178 sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
179 if (arg == NULL)
180 STATE |= simTRACE;
181 else if (strcmp (arg, "yes") == 0)
182 STATE |= simTRACE;
183 else if (strcmp (arg, "no") == 0)
184 STATE &= ~simTRACE;
185 else if (strcmp (arg, "on") == 0)
186 STATE |= simTRACE;
187 else if (strcmp (arg, "off") == 0)
188 STATE &= ~simTRACE;
189 else
190 {
191 fprintf (stderr, "Unreconized dinero-trace option `%s'\n", arg);
192 return SIM_RC_FAIL;
193 }
50a2a691
AC		 194 }
195 return SIM_RC_OK;
196#else /* !TRACE */
197 fprintf(stderr,"\
22de994d 198Simulator constructed without dinero tracing support (for performance).\n\
50a2a691
AC		 199Re-compile simulator with \"-DTRACE\" to enable this option.\n");
200 return SIM_RC_FAIL;
201#endif /* !TRACE */
202
22de994d 203 case OPTION_DINERO_FILE:
50a2a691
AC		 204#if defined(TRACE)
205 if (optarg != NULL) {
206 char *tmp;
207 tmp = (char *)malloc(strlen(optarg) + 1);
208 if (tmp == NULL)
209 {
18c64df6 210 sim_io_printf(sd,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg);
50a2a691
AC		 211 return SIM_RC_FAIL;
212 }
213 else {
214 strcpy(tmp,optarg);
215 tracefile = tmp;
18c64df6 216 sim_io_printf(sd,"Placing trace information into file \"%s\"\n",tracefile);
50a2a691
AC		 217 }
218 }
219#endif /* TRACE */
220 return SIM_RC_OK;
221
50a2a691
AC		 222 }
223
224 return SIM_RC_OK;
2e61a3ad 225}
50a2a691
AC		 226
227static const OPTION mips_options[] =
2e61a3ad 228{
22de994d
AC		 229 { {"dinero-trace", optional_argument, NULL, OPTION_DINERO_TRACE},
230 '\0', "on|off", "Enable dinero tracing",
50a2a691 231 mips_option_handler },
22de994d
AC		 232 { {"dinero-file", required_argument, NULL, OPTION_DINERO_FILE},
233 '\0', "FILE", "Write dinero trace to FILE",
50a2a691 234 mips_option_handler },
50a2a691
AC		 235 { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL }
236};
237
238
56e7c849
AC		 239int interrupt_pending;
240
50a2a691
AC		 241static void
242interrupt_event (SIM_DESC sd, void *data)
2e61a3ad 243{
01737f42 244 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
56e7c849
AC		 245 if (SR & status_IE)
246 {
247 interrupt_pending = 0;
18c64df6 248 SignalExceptionInterrupt ();
56e7c849
AC		 249 }
250 else if (!interrupt_pending)
251 sim_events_schedule (sd, 1, interrupt_event, data);
2e61a3ad 252}
f7481d45 253
f7481d45 254
50a2a691 255
8bae0a0c
JSC		 256/*---------------------------------------------------------------------------*/
257/*-- GDB simulator interface ------------------------------------------------*/
258/*---------------------------------------------------------------------------*/
259
53b9417e 260SIM_DESC
247fccde 261sim_open (kind, cb, abfd, argv)
87e43259 262 SIM_OPEN_KIND kind;
50a2a691 263 host_callback *cb;
247fccde 264 struct _bfd *abfd;
53b9417e 265 char **argv;
8bae0a0c 266{
18c64df6 267 SIM_DESC sd = sim_state_alloc (kind, cb);
01737f42 268 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
2e61a3ad 269
525d929e
AC		 270 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
271
50a2a691
AC		 272 /* FIXME: watchpoints code shouldn't need this */
273 STATE_WATCHPOINTS (sd)->pc = &(PC);
274 STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC);
275 STATE_WATCHPOINTS (sd)->interrupt_handler = interrupt_event;
276
0c2c5f61 277 STATE = 0;
50a2a691 278
2e61a3ad
AC		 279 if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
280 return 0;
50a2a691 281 sim_add_option_table (sd, mips_options);
2e61a3ad 282
63be8feb
AC		 283 /* Allocate core managed memory */
284
285 /* the monitor */
286 sim_do_commandf (sd, "memory region 0x%lx,0x%lx", MONITOR_BASE, MONITOR_SIZE);
287 /* For compatibility with the old code - under this (at level one)
288 are the kernel spaces K0 & K1. Both of these map to a single
289 smaller sub region */
290 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x",
291 K1BASE, K0SIZE,
292 MEM_SIZE, /* actual size */
293 K0BASE);
294
2e61a3ad
AC		 295 /* getopt will print the error message so we just have to exit if this fails.
296 FIXME: Hmmm... in the case of gdb we need getopt to call
297 print_filtered. */
298 if (sim_parse_args (sd, argv) != SIM_RC_OK)
299 {
300 /* Uninstall the modules to avoid memory leaks,
301 file descriptor leaks, etc. */
302 sim_module_uninstall (sd);
303 return 0;
304 }
2e61a3ad 305
fafce69a
AC		 306 /* check for/establish the a reference program image */
307 if (sim_analyze_program (sd,
308 (STATE_PROG_ARGV (sd) != NULL
309 ? *STATE_PROG_ARGV (sd)
310 : NULL),
311 abfd) != SIM_RC_OK)
312 {
313 sim_module_uninstall (sd);
314 return 0;
315 }
316
247fccde
AC		 317 /* Configure/verify the target byte order and other runtime
318 configuration options */
fafce69a 319 if (sim_config (sd) != SIM_RC_OK)
247fccde
AC		 320 {
321 sim_module_uninstall (sd);
322 return 0;
323 }
324
2e61a3ad
AC		 325 if (sim_post_argv_init (sd) != SIM_RC_OK)
326 {
327 /* Uninstall the modules to avoid memory leaks,
328 file descriptor leaks, etc. */
329 sim_module_uninstall (sd);
330 return 0;
331 }
332
50a2a691
AC		 333 /* verify assumptions the simulator made about the host type system.
334 This macro does not return if there is a problem */
7ce8b917
AC		 335 SIM_ASSERT (sizeof(int) == (4 * sizeof(char)));
336 SIM_ASSERT (sizeof(word64) == (8 * sizeof(char)));
8bae0a0c 337
8bae0a0c
JSC		 338 /* This is NASTY, in that we are assuming the size of specific
339 registers: */
340 {
341 int rn;
342 for (rn = 0; (rn < (LAST_EMBED_REGNUM + 1)); rn++) {
343 if (rn < 32)
192ae475 344 cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
8bae0a0c 345 else if ((rn >= FGRIDX) && (rn < (FGRIDX + 32)))
192ae475 346 cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
8bae0a0c 347 else if ((rn >= 33) && (rn <= 37))
192ae475 348 cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
8bae0a0c 349 else if ((rn == SRIDX) || (rn == FCR0IDX) || (rn == FCR31IDX) || ((rn >= 72) && (rn <= 89)))
0c2c5f61 350 cpu->register_widths[rn] = 32;
8bae0a0c 351 else
0c2c5f61 352 cpu->register_widths[rn] = 0;
8bae0a0c 353 }
18c64df6
AC		 354 /* start-sanitize-r5900 */
355
356 /* set the 5900 "upper" registers to 64 bits */
357 for( rn = LAST_EMBED_REGNUM+1; rn < NUM_REGS; rn++)
0c2c5f61 358 cpu->register_widths[rn] = 64;
18c64df6 359 /* end-sanitize-r5900 */
8bae0a0c
JSC		 360 }
361
8bae0a0c 362#if defined(TRACE)
0c2c5f61 363 if (STATE & simTRACE)
18c64df6 364 open_trace(sd);
8bae0a0c
JSC		 365#endif /* TRACE */
366
fafce69a
AC		 367 /* Write the monitor trap address handlers into the monitor (eeprom)
368 address space. This can only be done once the target endianness
369 has been determined. */
370 {
371 unsigned loop;
372 /* Entry into the IDT monitor is via fixed address vectors, and
373 not using machine instructions. To avoid clashing with use of
374 the MIPS TRAP system, we place our own (simulator specific)
375 "undefined" instructions into the relevant vector slots. */
525d929e
AC		 376 for (loop = 0; (loop < MONITOR_SIZE); loop += 4)
377 {
378 address_word vaddr = (MONITOR_BASE + loop);
379 unsigned32 insn = (RSVD_INSTRUCTION | (((loop >> 2) & RSVD_INSTRUCTION_ARG_MASK) << RSVD_INSTRUCTION_ARG_SHIFT));
380 H2T (insn);
381 sim_write (sd, vaddr, (char *)&insn, sizeof (insn));
382 }
fafce69a
AC		 383 /* The PMON monitor uses the same address space, but rather than
384 branching into it the address of a routine is loaded. We can
385 cheat for the moment, and direct the PMON routine to IDT style
386 instructions within the monitor space. This relies on the IDT
387 monitor not using the locations from 0xBFC00500 onwards as its
388 entry points.*/
389 for (loop = 0; (loop < 24); loop++)
390 {
525d929e
AC		 391 address_word vaddr = (MONITOR_BASE + 0x500 + (loop * 4));
392 unsigned32 value = ((0x500 - 8) / 8); /* default UNDEFINED reason code */
fafce69a
AC		 393 switch (loop)
394 {
395 case 0: /* read */
396 value = 7;
397 break;
fafce69a
AC		 398 case 1: /* write */
399 value = 8;
400 break;
fafce69a
AC		 401 case 2: /* open */
402 value = 6;
403 break;
fafce69a
AC		 404 case 3: /* close */
405 value = 10;
406 break;
fafce69a
AC		 407 case 5: /* printf */
408 value = ((0x500 - 16) / 8); /* not an IDT reason code */
409 break;
fafce69a
AC		 410 case 8: /* cliexit */
411 value = 17;
412 break;
fafce69a
AC		 413 case 11: /* flush_cache */
414 value = 28;
415 break;
416 }
525d929e
AC		 417 /* FIXME - should monitor_base be SIM_ADDR?? */
418 value = ((unsigned int)MONITOR_BASE + (value * 8));
419 H2T (value);
420 sim_write (sd, vaddr, (char *)&value, sizeof (value));
fafce69a
AC		 421
422 /* The LSI MiniRISC PMON has its vectors at 0x200, not 0x500. */
423 vaddr -= 0x300;
525d929e 424 sim_write (sd, vaddr, (char *)&value, sizeof (value));
fafce69a
AC		 425 }
426 }
427
2e61a3ad 428 return sd;
8bae0a0c
JSC		 429}
430
6429b296
JW		 431#if defined(TRACE)
432static void
18c64df6
AC		 433open_trace(sd)
434 SIM_DESC sd;
6429b296
JW		 435{
436 tracefh = fopen(tracefile,"wb+");
437 if (tracefh == NULL)
438 {
18c64df6 439 sim_io_eprintf(sd,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile);
6429b296
JW		 440 tracefh = stderr;
441 }
442}
443#endif /* TRACE */
444
8bae0a0c 445void
53b9417e
DE		 446sim_close (sd, quitting)
447 SIM_DESC sd;
8bae0a0c
JSC		 448 int quitting;
449{
450#ifdef DEBUG
451 printf("DBG: sim_close: entered (quitting = %d)\n",quitting);
452#endif
453
8bae0a0c
JSC		 454 /* "quitting" is non-zero if we cannot hang on errors */
455
456 /* Ensure that any resources allocated through the callback
457 mechanism are released: */
18c64df6 458 sim_io_shutdown (sd);
8bae0a0c 459
8bae0a0c 460#if defined(TRACE)
e3d12c65 461 if (tracefh != NULL && tracefh != stderr)
8bae0a0c 462 fclose(tracefh);
e3d12c65 463 tracefh = NULL;
8bae0a0c
JSC		 464#endif /* TRACE */
465
01737f42
AC		 466 /* FIXME - free SD */
467
8bae0a0c
JSC		 468 return;
469}
470
8bae0a0c
JSC		 471
472int
53b9417e
DE		 473sim_write (sd,addr,buffer,size)
474 SIM_DESC sd;
8bae0a0c
JSC		 475 SIM_ADDR addr;
476 unsigned char *buffer;
477 int size;
478{
525d929e 479 int index;
01737f42 480 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
8bae0a0c
JSC		 481
482 /* Return the number of bytes written, or zero if error. */
483#ifdef DEBUG
18c64df6 484 sim_io_printf(sd,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr),size);
8bae0a0c
JSC		 485#endif
486
525d929e
AC		 487 /* We use raw read and write routines, since we do not want to count
488 the GDB memory accesses in our statistics gathering. */
489
490 for (index = 0; index < size; index++)
491 {
492 address_word vaddr = (address_word)addr + index;
493 address_word paddr;
494 int cca;
01737f42 495 if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isSTORE, &paddr, &cca, isRAW))
525d929e 496 break;
01737f42 497 if (sim_core_write_buffer (SD, CPU, sim_core_read_map, buffer + index, paddr, 1) != 1)
63be8feb 498 break;
8bae0a0c 499 }
8bae0a0c 500
525d929e 501 return(index);
8bae0a0c
JSC		 502}
503
504int
53b9417e
DE		 505sim_read (sd,addr,buffer,size)
506 SIM_DESC sd;
8bae0a0c
JSC		 507 SIM_ADDR addr;
508 unsigned char *buffer;
509 int size;
510{
511 int index;
01737f42 512 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
8bae0a0c
JSC		 513
514 /* Return the number of bytes read, or zero if error. */
515#ifdef DEBUG
18c64df6 516 sim_io_printf(sd,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr),size);
8bae0a0c
JSC		 517#endif /* DEBUG */
518
525d929e
AC		 519 for (index = 0; (index < size); index++)
520 {
521 address_word vaddr = (address_word)addr + index;
522 address_word paddr;
525d929e 523 int cca;
01737f42 524 if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isLOAD, &paddr, &cca, isRAW))
525d929e 525 break;
01737f42 526 if (sim_core_read_buffer (SD, CPU, sim_core_read_map, buffer + index, paddr, 1) != 1)
63be8feb 527 break;
525d929e 528 }
8bae0a0c
JSC		 529
530 return(index);
531}
532
533void
53b9417e
DE		 534sim_store_register (sd,rn,memory)
535 SIM_DESC sd;
8bae0a0c
JSC		 536 int rn;
537 unsigned char *memory;
538{
01737f42 539 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
50a2a691
AC		 540 /* NOTE: gdb (the client) stores registers in target byte order
541 while the simulator uses host byte order */
8bae0a0c 542#ifdef DEBUG
18c64df6 543 sim_io_printf(sd,"sim_store_register(%d,*memory=0x%s);\n",rn,pr_addr(*((SIM_ADDR *)memory)));
8bae0a0c
JSC		 544#endif /* DEBUG */
545
546 /* Unfortunately this suffers from the same problem as the register
547 numbering one. We need to know what the width of each logical
548 register number is for the architecture being simulated. */
50a2a691 549
0c2c5f61 550 if (cpu->register_widths[rn] == 0)
18c64df6
AC		 551 sim_io_eprintf(sd,"Invalid register width for %d (register store ignored)\n",rn);
552 /* start-sanitize-r5900 */
553 else if (rn == REGISTER_SA)
554 SA = T2H_8(*(uword64*)memory);
555 else if (rn > LAST_EMBED_REGNUM)
0c2c5f61 556 cpu->registers1[rn - LAST_EMBED_REGNUM - 1] = T2H_8(*(uword64*)memory);
18c64df6 557 /* end-sanitize-r5900 */
0c2c5f61
AC		 558 else if (cpu->register_widths[rn] == 32)
559 cpu->registers[rn] = T2H_4 (*(unsigned int*)memory);
50a2a691 560 else
0c2c5f61 561 cpu->registers[rn] = T2H_8 (*(uword64*)memory);
8bae0a0c
JSC		 562
563 return;
564}
565
566void
53b9417e
DE		 567sim_fetch_register (sd,rn,memory)
568 SIM_DESC sd;
8bae0a0c
JSC		 569 int rn;
570 unsigned char *memory;
571{
01737f42 572 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
50a2a691
AC		 573 /* NOTE: gdb (the client) stores registers in target byte order
574 while the simulator uses host byte order */
8bae0a0c 575#ifdef DEBUG
18c64df6 576 sim_io_printf(sd,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn,pr_addr(registers[rn]));
8bae0a0c
JSC		 577#endif /* DEBUG */
578
0c2c5f61 579 if (cpu->register_widths[rn] == 0)
18c64df6
AC		 580 sim_io_eprintf(sd,"Invalid register width for %d (register fetch ignored)\n",rn);
581 /* start-sanitize-r5900 */
582 else if (rn == REGISTER_SA)
583 *((uword64 *)memory) = H2T_8(SA);
584 else if (rn > LAST_EMBED_REGNUM)
0c2c5f61 585 *((uword64 *)memory) = H2T_8(cpu->registers1[rn - LAST_EMBED_REGNUM - 1]);
18c64df6 586 /* end-sanitize-r5900 */
0c2c5f61
AC		 587 else if (cpu->register_widths[rn] == 32)
588 *((unsigned int *)memory) = H2T_4 ((unsigned int)(cpu->registers[rn] & 0xFFFFFFFF));
18c64df6 589 else /* 64bit register */
0c2c5f61 590 *((uword64 *)memory) = H2T_8 (cpu->registers[rn]);
50a2a691 591
8bae0a0c
JSC		 592 return;
593}
50a2a691 594
8bae0a0c
JSC		 595
596void
53b9417e
DE		 597sim_info (sd,verbose)
598 SIM_DESC sd;
8bae0a0c
JSC		 599 int verbose;
600{
601 /* Accessed from the GDB "info files" command: */
56e7c849
AC		 602 if (STATE_VERBOSE_P (sd) || verbose)
603 {
604
605 sim_io_printf (sd, "MIPS %d-bit %s endian simulator\n",
192ae475 606 WITH_TARGET_WORD_BITSIZE,
56e7c849
AC		 607 (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN ? "Big" : "Little"));
608
8bae0a0c 609#if !defined(FASTSIM)
56e7c849
AC		 610 /* It would be a useful feature, if when performing multi-cycle
611 simulations (rather than single-stepping) we keep the start and
612 end times of the execution, so that we can give a performance
613 figure for the simulator. */
8bae0a0c 614#endif /* !FASTSIM */
56e7c849
AC		 615 sim_io_printf (sd, "Number of execution cycles = %ld\n",
616 (long) sim_events_time (sd));
617
618 /* print information pertaining to MIPS ISA and architecture being simulated */
619 /* things that may be interesting */
620 /* instructions executed - if available */
621 /* cycles executed - if available */
622 /* pipeline stalls - if available */
623 /* virtual time taken */
624 /* profiling size */
625 /* profiling frequency */
626 /* profile minpc */
627 /* profile maxpc */
628 }
aa324b9b 629 profile_print (sd, STATE_VERBOSE_P (sd), NULL, NULL);
8bae0a0c
JSC		 630}
631
8bae0a0c 632
9d52bcb7 633SIM_RC
fafce69a 634sim_create_inferior (sd, abfd, argv,env)
53b9417e 635 SIM_DESC sd;
fafce69a 636 struct _bfd *abfd;
8bae0a0c
JSC		 637 char **argv;
638 char **env;
639{
50a2a691 640
8bae0a0c 641#ifdef DEBUG
9d52bcb7
DE		 642 printf("DBG: sim_create_inferior entered: start_address = 0x%s\n",
643 pr_addr(PC));
8bae0a0c
JSC		 644#endif /* DEBUG */
645
0c2c5f61 646 ColdReset(sd);
50a2a691 647
fafce69a 648 if (abfd != NULL)
01737f42
AC		 649 {
650 /* override PC value set by ColdReset () */
651 int cpu_nr;
652 for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++)
653 {
654 sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
655 CIA_SET (cpu, (unsigned64) bfd_get_start_address (abfd));
656 }
657 }
2e61a3ad 658
f24b7b69 659#if 0 /* def DEBUG */
dad6f1f3 660 if (argv || env)
8bae0a0c 661 {
dad6f1f3
AC		 662 /* We should really place the argv slot values into the argument
663 registers, and onto the stack as required. However, this
664 assumes that we have a stack defined, which is not
665 necessarily true at the moment. */
666 char **cptr;
667 sim_io_printf(sd,"sim_create_inferior() : passed arguments ignored\n");
668 for (cptr = argv; (cptr && *cptr); cptr++)
669 printf("DBG: arg \"%s\"\n",*cptr);
8bae0a0c
JSC		 670 }
671#endif /* DEBUG */
8bae0a0c 672
9d52bcb7 673 return SIM_RC_OK;
8bae0a0c
JSC		 674}
675
8bae0a0c 676void
53b9417e
DE		 677sim_do_command (sd,cmd)
678 SIM_DESC sd;
8bae0a0c
JSC		 679 char *cmd;
680{
63be8feb
AC		 681 if (sim_args_command (sd, cmd) != SIM_RC_OK)
682 sim_io_printf (sd, "Error: \"%s\" is not a valid MIPS simulator command.\n",
683 cmd);
8bae0a0c
JSC		 684}
685
8bae0a0c
JSC		 686/*---------------------------------------------------------------------------*/
687/*-- Private simulator support interface ------------------------------------*/
688/*---------------------------------------------------------------------------*/
689
525d929e
AC		 690/* Read a null terminated string from memory, return in a buffer */
691static char *
692fetch_str (sd, addr)
693 SIM_DESC sd;
694 address_word addr;
695{
696 char *buf;
697 int nr = 0;
698 char null;
699 while (sim_read (sd, addr + nr, &null, 1) == 1 && null != 0)
700 nr++;
701 buf = NZALLOC (char, nr + 1);
702 sim_read (sd, addr, buf, nr);
703 return buf;
704}
705
a9f7253f 706/* Simple monitor interface (currently setup for the IDT and PMON monitors) */
8bae0a0c 707static void
01737f42
AC		 708sim_monitor (SIM_DESC sd,
709 sim_cpu *cpu,
710 address_word cia,
711 unsigned int reason)
8bae0a0c 712{
53b9417e
DE		 713#ifdef DEBUG
714 printf("DBG: sim_monitor: entered (reason = %d)\n",reason);
715#endif /* DEBUG */
716
8bae0a0c
JSC		 717 /* The IDT monitor actually allows two instructions per vector
718 slot. However, the simulator currently causes a trap on each
719 individual instruction. We cheat, and lose the bottom bit. */
720 reason >>= 1;
721
722 /* The following callback functions are available, however the
723 monitor we are simulating does not make use of them: get_errno,
724 isatty, lseek, rename, system, time and unlink */
525d929e
AC		 725 switch (reason)
726 {
727
8bae0a0c
JSC		 728 case 6: /* int open(char *path,int flags) */
729 {
525d929e
AC		 730 char *path = fetch_str (sd, A0);
731 V0 = sim_io_open (sd, path, (int)A1);
732 zfree (path);
733 break;
8bae0a0c 734 }
8bae0a0c
JSC		 735
736 case 7: /* int read(int file,char *ptr,int len) */
737 {
525d929e
AC		 738 int fd = A0;
739 int nr = A2;
740 char *buf = zalloc (nr);
741 V0 = sim_io_read (sd, fd, buf, nr);
742 sim_write (sd, A1, buf, nr);
743 zfree (buf);
8bae0a0c
JSC		 744 }
745 break;
746
747 case 8: /* int write(int file,char *ptr,int len) */
748 {
525d929e
AC		 749 int fd = A0;
750 int nr = A2;
751 char *buf = zalloc (nr);
752 sim_read (sd, A1, buf, nr);
753 V0 = sim_io_write (sd, fd, buf, nr);
754 zfree (buf);
755 break;
8bae0a0c 756 }
8bae0a0c
JSC		 757
758 case 10: /* int close(int file) */
525d929e
AC		 759 {
760 V0 = sim_io_close (sd, (int)A0);
761 break;
762 }
8bae0a0c 763
e0e0fc76
MA		 764 case 2: /* Densan monitor: char inbyte(int waitflag) */
765 {
766 if (A0 == 0) /* waitflag == NOWAIT */
192ae475 767 V0 = (unsigned_word)-1;
e0e0fc76
MA		 768 }
769 /* Drop through to case 11 */
770
8bae0a0c
JSC		 771 case 11: /* char inbyte(void) */
772 {
773 char tmp;
525d929e
AC		 774 if (sim_io_read_stdin (sd, &tmp, sizeof(char)) != sizeof(char))
775 {
776 sim_io_error(sd,"Invalid return from character read");
192ae475 777 V0 = (unsigned_word)-1;
525d929e 778 }
8bae0a0c 779 else
192ae475 780 V0 = (unsigned_word)tmp;
525d929e 781 break;
8bae0a0c 782 }
8bae0a0c 783
e0e0fc76 784 case 3: /* Densan monitor: void co(char chr) */
8bae0a0c
JSC		 785 case 12: /* void outbyte(char chr) : write a byte to "stdout" */
786 {
787 char tmp = (char)(A0 & 0xFF);
525d929e
AC		 788 sim_io_write_stdout (sd, &tmp, sizeof(char));
789 break;
8bae0a0c 790 }
8bae0a0c
JSC		 791
792 case 17: /* void _exit() */
525d929e
AC		 793 {
794 sim_io_eprintf (sd, "sim_monitor(17): _exit(int reason) to be coded\n");
01737f42 795 sim_engine_halt (SD, CPU, NULL, NULL_CIA, sim_exited,
525d929e
AC		 796 (unsigned int)(A0 & 0xFFFFFFFF));
797 break;
798 }
8bae0a0c 799
280f90e1
AMT		 800 case 28 : /* PMON flush_cache */
801 break;
802
8bae0a0c
JSC		 803 case 55: /* void get_mem_info(unsigned int *ptr) */
804 /* in: A0 = pointer to three word memory location */
805 /* out: [A0 + 0] = size */
806 /* [A0 + 4] = instruction cache size */
807 /* [A0 + 8] = data cache size */
808 {
525d929e
AC		 809 address_word value = MEM_SIZE /* FIXME STATE_MEM_SIZE (sd) */;
810 H2T (value);
811 sim_write (sd, A0, (char *)&value, sizeof (value));
030843d7 812 /* sim_io_eprintf (sd, "sim: get_mem_info() depreciated\n"); */
525d929e 813 break;
8bae0a0c 814 }
525d929e 815
a9f7253f
JSC		 816 case 158 : /* PMON printf */
817 /* in: A0 = pointer to format string */
818 /* A1 = optional argument 1 */
819 /* A2 = optional argument 2 */
820 /* A3 = optional argument 3 */
821 /* out: void */
f24b7b69 822 /* The following is based on the PMON printf source */
a9f7253f 823 {
525d929e
AC		 824 address_word s = A0;
825 char c;
826 signed_word *ap = &A1; /* 1st argument */
f24b7b69
JSC		 827 /* This isn't the quickest way, since we call the host print
828 routine for every character almost. But it does avoid
829 having to allocate and manage a temporary string buffer. */
525d929e
AC		 830 /* TODO: Include check that we only use three arguments (A1,
831 A2 and A3) */
832 while (sim_read (sd, s++, &c, 1) && c != '\0')
833 {
834 if (c == '%')
835 {
836 char tmp[40];
837 enum {FMT_RJUST, FMT_LJUST, FMT_RJUST0, FMT_CENTER} fmt = FMT_RJUST;
838 int width = 0, trunc = 0, haddot = 0, longlong = 0;
839 while (sim_read (sd, s++, &c, 1) && c != '\0')
840 {
841 if (strchr ("dobxXulscefg%", s))
842 break;
843 else if (c == '-')
844 fmt = FMT_LJUST;
845 else if (c == '0')
846 fmt = FMT_RJUST0;
847 else if (c == '~')
848 fmt = FMT_CENTER;
849 else if (c == '*')
850 {
851 if (haddot)
852 trunc = (int)*ap++;
853 else
854 width = (int)*ap++;
855 }
856 else if (c >= '1' && c <= '9')
857 {
858 address_word t = s;
859 unsigned int n;
860 while (sim_read (sd, s++, &c, 1) == 1 && isdigit (c))
861 tmp[s - t] = c;
862 tmp[s - t] = '\0';
863 n = (unsigned int)strtol(tmp,NULL,10);
864 if (haddot)
865 trunc = n;
866 else
867 width = n;
868 s--;
869 }
870 else if (c == '.')
871 haddot = 1;
872 }
873 switch (c)
874 {
875 case '%':
876 sim_io_printf (sd, "%%");
877 break;
878 case 's':
879 if ((int)*ap != 0)
880 {
881 address_word p = *ap++;
882 char ch;
883 while (sim_read (sd, p++, &ch, 1) == 1 && ch != '\0')
884 sim_io_printf(sd, "%c", ch);
885 }
886 else
887 sim_io_printf(sd,"(null)");
888 break;
889 case 'c':
890 sim_io_printf (sd, "%c", (int)*ap++);
891 break;
892 default:
893 if (c == 'l')
894 {
895 sim_read (sd, s++, &c, 1);
896 if (c == 'l')
897 {
898 longlong = 1;
899 sim_read (sd, s++, &c, 1);
900 }
901 }
902 if (strchr ("dobxXu", c))
903 {
904 word64 lv = (word64) *ap++;
905 if (c == 'b')
906 sim_io_printf(sd,"<binary not supported>");
907 else
908 {
909 sprintf (tmp, "%%%s%c", longlong ? "ll" : "", c);
910 if (longlong)
911 sim_io_printf(sd, tmp, lv);
912 else
913 sim_io_printf(sd, tmp, (int)lv);
914 }
915 }
916 else if (strchr ("eEfgG", c))
917 {
918 double dbl = *(double*)(ap++);
919 sprintf (tmp, "%%%d.%d%c", width, trunc, c);
920 sim_io_printf (sd, tmp, dbl);
921 trunc = 0;
922 }
923 }
924 }
925 else
926 sim_io_printf(sd, "%c", c);
927 }
928 break;
a9f7253f 929 }
a9f7253f 930
8bae0a0c 931 default:
525d929e 932 sim_io_error (sd, "TODO: sim_monitor(%d) : PC = 0x%s\n",
95469ceb 933 reason, pr_addr(cia));
8bae0a0c
JSC		 934 break;
935 }
936 return;
937}
938
7e6c297e
ILT		 939/* Store a word into memory. */
940
941static void
01737f42
AC		 942store_word (SIM_DESC sd,
943 sim_cpu *cpu,
944 address_word cia,
945 uword64 vaddr,
192ae475 946 signed_word val)
7e6c297e 947{
dad6f1f3 948 address_word paddr;
7e6c297e
ILT		 949 int uncached;
950
951 if ((vaddr & 3) != 0)
18c64df6 952 SignalExceptionAddressStore ();
7e6c297e
ILT		 953 else
954 {
955 if (AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached,
956 isTARGET, isREAL))
957 {
958 const uword64 mask = 7;
959 uword64 memval;
960 unsigned int byte;
961
962 paddr = (paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2));
963 byte = (vaddr & mask) ^ (BigEndianCPU << 2);
964 memval = ((uword64) val) << (8 * byte);
53b9417e 965 StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr,
7e6c297e
ILT		 966 isREAL);
967 }
968 }
969}
970
971/* Load a word from memory. */
972
192ae475 973static signed_word
01737f42
AC		 974load_word (SIM_DESC sd,
975 sim_cpu *cpu,
976 address_word cia,
977 uword64 vaddr)
7e6c297e
ILT		 978{
979 if ((vaddr & 3) != 0)
18c64df6 980 SignalExceptionAddressLoad ();
7e6c297e
ILT		 981 else
982 {
dad6f1f3 983 address_word paddr;
7e6c297e
ILT		 984 int uncached;
985
986 if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached,
987 isTARGET, isREAL))
988 {
989 const uword64 mask = 0x7;
990 const unsigned int reverse = ReverseEndian ? 1 : 0;
991 const unsigned int bigend = BigEndianCPU ? 1 : 0;
992 uword64 memval;
993 unsigned int byte;
994
995 paddr = (paddr & ~mask) | ((paddr & mask) ^ (reverse << 2));
53b9417e 996 LoadMemory (&memval,NULL,uncached, AccessLength_WORD, paddr, vaddr,
7e6c297e
ILT		 997 isDATA, isREAL);
998 byte = (vaddr & mask) ^ (bigend << 2);
999 return SIGNEXTEND (((memval >> (8 * byte)) & 0xffffffff), 32);
1000 }
1001 }
1002
1003 return 0;
1004}
1005
1006/* Simulate the mips16 entry and exit pseudo-instructions. These
1007 would normally be handled by the reserved instruction exception
1008 code, but for ease of simulation we just handle them directly. */
1009
1010static void
01737f42
AC		 1011mips16_entry (SIM_DESC sd,
1012 sim_cpu *cpu,
1013 address_word cia,
1014 unsigned int insn)
7e6c297e
ILT		 1015{
1016 int aregs, sregs, rreg;
1017
53b9417e
DE		 1018#ifdef DEBUG
1019 printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn);
1020#endif /* DEBUG */
1021
7e6c297e
ILT		 1022 aregs = (insn & 0x700) >> 8;
1023 sregs = (insn & 0x0c0) >> 6;
1024 rreg = (insn & 0x020) >> 5;
1025
da0bce9c
ILT		 1026 /* This should be checked by the caller. */
1027 if (sregs == 3)
7e6c297e
ILT		 1028 abort ();
1029
da0bce9c 1030 if (aregs < 5)
7e6c297e
ILT		 1031 {
1032 int i;
192ae475 1033 signed_word tsp;
7e6c297e
ILT		 1034
1035 /* This is the entry pseudo-instruction. */
1036
1037 for (i = 0; i < aregs; i++)
01737f42 1038 store_word (SD, CPU, cia, (uword64) (SP + 4 * i), GPR[i + 4]);
7e6c297e
ILT		 1039
1040 tsp = SP;
1041 SP -= 32;
1042
1043 if (rreg)
1044 {
1045 tsp -= 4;
01737f42 1046 store_word (SD, CPU, cia, (uword64) tsp, RA);
7e6c297e
ILT		 1047 }
1048
1049 for (i = 0; i < sregs; i++)
1050 {
1051 tsp -= 4;
01737f42 1052 store_word (SD, CPU, cia, (uword64) tsp, GPR[16 + i]);
7e6c297e
ILT		 1053 }
1054 }
1055 else
1056 {
1057 int i;
192ae475 1058 signed_word tsp;
7e6c297e
ILT		 1059
1060 /* This is the exit pseudo-instruction. */
1061
1062 tsp = SP + 32;
1063
1064 if (rreg)
1065 {
1066 tsp -= 4;
01737f42 1067 RA = load_word (SD, CPU, cia, (uword64) tsp);
7e6c297e
ILT		 1068 }
1069
1070 for (i = 0; i < sregs; i++)
1071 {
1072 tsp -= 4;
01737f42 1073 GPR[i + 16] = load_word (SD, CPU, cia, (uword64) tsp);
7e6c297e
ILT		 1074 }
1075
1076 SP += 32;
1077
192ae475 1078 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
da0bce9c 1079 {
192ae475
AC		 1080 if (aregs == 5)
1081 {
1082 FGR[0] = WORD64LO (GPR[4]);
1083 FPR_STATE[0] = fmt_uninterpreted;
1084 }
1085 else if (aregs == 6)
1086 {
1087 FGR[0] = WORD64LO (GPR[5]);
1088 FGR[1] = WORD64LO (GPR[4]);
1089 FPR_STATE[0] = fmt_uninterpreted;
1090 FPR_STATE[1] = fmt_uninterpreted;
1091 }
1092 }
da0bce9c 1093
7e6c297e
ILT		 1094 PC = RA;
1095 }
192ae475 1096
7e6c297e
ILT		 1097}
1098
8bae0a0c
JSC		 1099/*-- trace support ----------------------------------------------------------*/
1100
1101/* The TRACE support is provided (if required) in the memory accessing
1102 routines. Since we are also providing the architecture specific
1103 features, the architecture simulation code can also deal with
1104 notifying the TRACE world of cache flushes, etc. Similarly we do
1105 not need to provide profiling support in the simulator engine,
1106 since we can sample in the instruction fetch control loop. By
1107 defining the TRACE manifest, we add tracing as a run-time
1108 option. */
1109
1110#if defined(TRACE)
1111/* Tracing by default produces "din" format (as required by
1112 dineroIII). Each line of such a trace file *MUST* have a din label
1113 and address field. The rest of the line is ignored, so comments can
1114 be included if desired. The first field is the label which must be
1115 one of the following values:
1116
1117 0 read data
1118 1 write data
1119 2 instruction fetch
1120 3 escape record (treated as unknown access type)
1121 4 escape record (causes cache flush)
1122
1123 The address field is a 32bit (lower-case) hexadecimal address
1124 value. The address should *NOT* be preceded by "0x".
1125
1126 The size of the memory transfer is not important when dealing with
1127 cache lines (as long as no more than a cache line can be
1128 transferred in a single operation :-), however more information
1129 could be given following the dineroIII requirement to allow more
1130 complete memory and cache simulators to provide better
1131 results. i.e. the University of Pisa has a cache simulator that can
1132 also take bus size and speed as (variable) inputs to calculate
1133 complete system performance (a much more useful ability when trying
1134 to construct an end product, rather than a processor). They
1135 currently have an ARM version of their tool called ChARM. */
1136
e3d12c65 1137
030843d7 1138void
01737f42
AC		 1139dotrace (SIM_DESC sd,
1140 sim_cpu *cpu,
1141 FILE *tracefh,
1142 int type,
1143 SIM_ADDR address,
1144 int width,
1145 char *comment,...)
8bae0a0c 1146{
0c2c5f61 1147 if (STATE & simTRACE) {
8bae0a0c 1148 va_list ap;
53b9417e 1149 fprintf(tracefh,"%d %s ; width %d ; ",
6429b296 1150 type,
53b9417e
DE		 1151 pr_addr(address),
1152 width);
8bae0a0c 1153 va_start(ap,comment);
6429b296 1154 vfprintf(tracefh,comment,ap);
8bae0a0c
JSC		 1155 va_end(ap);
1156 fprintf(tracefh,"\n");
1157 }
1158 /* NOTE: Since the "din" format will only accept 32bit addresses, and
1159 we may be generating 64bit ones, we should put the hi-32bits of the
1160 address into the comment field. */
1161
1162 /* TODO: Provide a buffer for the trace lines. We can then avoid
1163 performing writes until the buffer is filled, or the file is
1164 being closed. */
1165
1166 /* NOTE: We could consider adding a comment field to the "din" file
1167 produced using type 3 markers (unknown access). This would then
1168 allow information about the program that the "din" is for, and
1169 the MIPs world that was being simulated, to be placed into the
1170 trace file. */
1171
1172 return;
1173}
1174#endif /* TRACE */
1175
1176/*---------------------------------------------------------------------------*/
1177/*-- simulator engine -------------------------------------------------------*/
1178/*---------------------------------------------------------------------------*/
1179
1180static void
01737f42 1181ColdReset (SIM_DESC sd)
8bae0a0c 1182{
01737f42
AC		 1183 int cpu_nr;
1184 for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++)
dad6f1f3 1185 {
01737f42
AC		 1186 sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
1187 /* RESET: Fixed PC address: */
1188 PC = UNSIGNED64 (0xFFFFFFFFBFC00000);
1189 /* The reset vector address is in the unmapped, uncached memory space. */
1190
1191 SR &= ~(status_SR | status_TS | status_RP);
1192 SR |= (status_ERL | status_BEV);
1193
1194 /* Cheat and allow access to the complete register set immediately */
1195 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT
1196 && WITH_TARGET_WORD_BITSIZE == 64)
1197 SR |= status_FR; /* 64bit registers */
1198
1199 /* Ensure that any instructions with pending register updates are
1200 cleared: */
2acd126a 1201 PENDING_INVALIDATE();
01737f42
AC		 1202
1203 /* Initialise the FPU registers to the unknown state */
1204 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
1205 {
1206 int rn;
1207 for (rn = 0; (rn < 32); rn++)
1208 FPR_STATE[rn] = fmt_uninterpreted;
1209 }
1210
dad6f1f3 1211 }
8bae0a0c
JSC		 1212}
1213
dad6f1f3
AC		 1214/* Description from page A-22 of the "MIPS IV Instruction Set" manual
1215 (revision 3.1) */
8bae0a0c
JSC		 1216/* Translate a virtual address to a physical address and cache
1217 coherence algorithm describing the mechanism used to resolve the
1218 memory reference. Given the virtual address vAddr, and whether the
1219 reference is to Instructions ot Data (IorD), find the corresponding
1220 physical address (pAddr) and the cache coherence algorithm (CCA)
1221 used to resolve the reference. If the virtual address is in one of
1222 the unmapped address spaces the physical address and the CCA are
1223 determined directly by the virtual address. If the virtual address
1224 is in one of the mapped address spaces then the TLB is used to
1225 determine the physical address and access type; if the required
1226 translation is not present in the TLB or the desired access is not
1227 permitted the function fails and an exception is taken.
1228
dad6f1f3
AC		 1229 NOTE: Normally (RAW == 0), when address translation fails, this
1230 function raises an exception and does not return. */
8bae0a0c 1231
18c64df6 1232int
01737f42
AC		 1233address_translation (SIM_DESC sd,
1234 sim_cpu *cpu,
1235 address_word cia,
1236 address_word vAddr,
1237 int IorD,
1238 int LorS,
1239 address_word *pAddr,
1240 int *CCA,
1241 int raw)
8bae0a0c
JSC		 1242{
1243 int res = -1; /* TRUE : Assume good return */
1244
1245#ifdef DEBUG
18c64df6 1246 sim_io_printf(sd,"AddressTranslation(0x%s,%s,%s,...);\n",pr_addr(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"),(LorS ? "iSTORE" : "isLOAD"));
8bae0a0c
JSC		 1247#endif
1248
1249 /* Check that the address is valid for this memory model */
1250
1251 /* For a simple (flat) memory model, we simply pass virtual
1252 addressess through (mostly) unchanged. */
1253 vAddr &= 0xFFFFFFFF;
a9f7253f 1254
8bae0a0c
JSC		 1255 *pAddr = vAddr; /* default for isTARGET */
1256 *CCA = Uncached; /* not used for isHOST */
1257
8bae0a0c
JSC		 1258 return(res);
1259}
1260
63be8feb
AC		 1261/* Description from page A-23 of the "MIPS IV Instruction Set" manual
1262 (revision 3.1) */
8bae0a0c
JSC		 1263/* Prefetch data from memory. Prefetch is an advisory instruction for
1264 which an implementation specific action is taken. The action taken
1265 may increase performance, but must not change the meaning of the
1266 program, or alter architecturally-visible state. */
50a2a691 1267
ea985d24 1268void
01737f42
AC		 1269prefetch (SIM_DESC sd,
1270 sim_cpu *cpu,
1271 address_word cia,
1272 int CCA,
1273 address_word pAddr,
1274 address_word vAddr,
1275 int DATA,
1276 int hint)
8bae0a0c
JSC		 1277{
1278#ifdef DEBUG
18c64df6 1279 sim_io_printf(sd,"Prefetch(%d,0x%s,0x%s,%d,%d);\n",CCA,pr_addr(pAddr),pr_addr(vAddr),DATA,hint);
8bae0a0c
JSC		 1280#endif /* DEBUG */
1281
1282 /* For our simple memory model we do nothing */
1283 return;
1284}
1285
63be8feb
AC		 1286/* Description from page A-22 of the "MIPS IV Instruction Set" manual
1287 (revision 3.1) */
8bae0a0c
JSC		 1288/* Load a value from memory. Use the cache and main memory as
1289 specified in the Cache Coherence Algorithm (CCA) and the sort of
1290 access (IorD) to find the contents of AccessLength memory bytes
1291 starting at physical location pAddr. The data is returned in the
1292 fixed width naturally-aligned memory element (MemElem). The
1293 low-order two (or three) bits of the address and the AccessLength
1294 indicate which of the bytes within MemElem needs to be given to the
1295 processor. If the memory access type of the reference is uncached
1296 then only the referenced bytes are read from memory and valid
1297 within the memory element. If the access type is cached, and the
1298 data is not present in cache, an implementation specific size and
1299 alignment block of memory is read and loaded into the cache to
1300 satisfy a load reference. At a minimum, the block is the entire
1301 memory element. */
18c64df6 1302void
01737f42
AC		 1303load_memory (SIM_DESC sd,
1304 sim_cpu *cpu,
1305 address_word cia,
1306 uword64* memvalp,
1307 uword64* memval1p,
1308 int CCA,
1309 int AccessLength,
1310 address_word pAddr,
1311 address_word vAddr,
1312 int IorD)
8bae0a0c 1313{
50a2a691
AC		 1314 uword64 value = 0;
1315 uword64 value1 = 0;
8bae0a0c
JSC		 1316
1317#ifdef DEBUG
63be8feb 1318 sim_io_printf(sd,"DBG: LoadMemory(%p,%p,%d,%d,0x%s,0x%s,%s)\n",memvalp,memval1p,CCA,AccessLength,pr_addr(pAddr),pr_addr(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"));
8bae0a0c
JSC		 1319#endif /* DEBUG */
1320
1321#if defined(WARN_MEM)
1322 if (CCA != uncached)
63be8feb 1323 sim_io_eprintf(sd,"LoadMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA);
8bae0a0c
JSC		 1324#endif /* WARN_MEM */
1325
8bae0a0c
JSC		 1326 /* If instruction fetch then we need to check that the two lo-order
1327 bits are zero, otherwise raise a InstructionFetch exception: */
6429b296
JW		 1328 if ((IorD == isINSTRUCTION)
1329 && ((pAddr & 0x3) != 0)
1330 && (((pAddr & 0x1) != 0) || ((vAddr & 0x1) == 0)))
63be8feb
AC		 1331 SignalExceptionInstructionFetch ();
1332
1333 if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK)
1334 {
1335 /* In reality this should be a Bus Error */
1336 sim_io_error (sd, "AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",
1337 AccessLength,
1338 (LOADDRMASK + 1) << 2,
1339 pr_addr (pAddr));
1340 }
8bae0a0c 1341
8bae0a0c 1342#if defined(TRACE)
01737f42 1343 dotrace (SD, CPU, tracefh,((IorD == isDATA) ? 0 : 2),(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"load%s",((IorD == isDATA) ? "" : " instruction"));
8bae0a0c 1344#endif /* TRACE */
63be8feb
AC		 1345
1346 /* Read the specified number of bytes from memory. Adjust for
1347 host/target byte ordering/ Align the least significant byte
1348 read. */
8bae0a0c 1349
63be8feb
AC		 1350 switch (AccessLength)
1351 {
1352 case AccessLength_QUADWORD :
1353 {
01737f42 1354 unsigned_16 val = sim_core_read_aligned_16 (cpu, NULL_CIA,
63be8feb
AC		 1355 sim_core_read_map, pAddr);
1356 value1 = VH8_16 (val);
1357 value = VL8_16 (val);
1358 break;
8bae0a0c 1359 }
63be8feb 1360 case AccessLength_DOUBLEWORD :
01737f42 1361 value = sim_core_read_aligned_8 (cpu, NULL_CIA,
63be8feb
AC		 1362 sim_core_read_map, pAddr);
1363 break;
1364 case AccessLength_SEPTIBYTE :
01737f42 1365 value = sim_core_read_misaligned_7 (cpu, NULL_CIA,
63be8feb
AC		 1366 sim_core_read_map, pAddr);
1367 case AccessLength_SEXTIBYTE :
01737f42 1368 value = sim_core_read_misaligned_6 (cpu, NULL_CIA,
63be8feb
AC		 1369 sim_core_read_map, pAddr);
1370 case AccessLength_QUINTIBYTE :
01737f42 1371 value = sim_core_read_misaligned_5 (cpu, NULL_CIA,
63be8feb
AC		 1372 sim_core_read_map, pAddr);
1373 case AccessLength_WORD :
01737f42 1374 value = sim_core_read_aligned_4 (cpu, NULL_CIA,
63be8feb
AC		 1375 sim_core_read_map, pAddr);
1376 break;
1377 case AccessLength_TRIPLEBYTE :
01737f42 1378 value = sim_core_read_misaligned_3 (cpu, NULL_CIA,
63be8feb
AC		 1379 sim_core_read_map, pAddr);
1380 case AccessLength_HALFWORD :
01737f42 1381 value = sim_core_read_aligned_2 (cpu, NULL_CIA,
63be8feb
AC		 1382 sim_core_read_map, pAddr);
1383 break;
1384 case AccessLength_BYTE :
01737f42 1385 value = sim_core_read_aligned_1 (cpu, NULL_CIA,
63be8feb
AC		 1386 sim_core_read_map, pAddr);
1387 break;
1388 default:
1389 abort ();
1390 }
1391
8bae0a0c 1392#ifdef DEBUG
63be8feb
AC		 1393 printf("DBG: LoadMemory() : (offset %d) : value = 0x%s%s\n",
1394 (int)(pAddr & LOADDRMASK),pr_uword64(value1),pr_uword64(value));
8bae0a0c 1395#endif /* DEBUG */
63be8feb
AC		 1396
1397 /* See also store_memory. */
1398 if (AccessLength <= AccessLength_DOUBLEWORD)
1399 {
1400 if (BigEndianMem)
1401 /* for big endian target, byte (pAddr&LOADDRMASK == 0) is
1402 shifted to the most significant byte position. */
1403 value <<= (((7 - (pAddr & LOADDRMASK)) - AccessLength) * 8);
1404 else
1405 /* For little endian target, byte (pAddr&LOADDRMASK == 0)
1406 is already in the correct postition. */
1407 value <<= ((pAddr & LOADDRMASK) * 8);
1408 }
1409
8bae0a0c 1410#ifdef DEBUG
63be8feb
AC		 1411 printf("DBG: LoadMemory() : shifted value = 0x%s%s\n",
1412 pr_uword64(value1),pr_uword64(value));
e871dd18 1413#endif /* DEBUG */
63be8feb 1414
525d929e
AC		 1415 *memvalp = value;
1416 if (memval1p) *memval1p = value1;
8bae0a0c
JSC		 1417}
1418
53b9417e 1419
50a2a691
AC		 1420/* Description from page A-23 of the "MIPS IV Instruction Set" manual
1421 (revision 3.1) */
8bae0a0c
JSC		 1422/* Store a value to memory. The specified data is stored into the
1423 physical location pAddr using the memory hierarchy (data caches and
1424 main memory) as specified by the Cache Coherence Algorithm
1425 (CCA). The MemElem contains the data for an aligned, fixed-width
1426 memory element (word for 32-bit processors, doubleword for 64-bit
1427 processors), though only the bytes that will actually be stored to
1428 memory need to be valid. The low-order two (or three) bits of pAddr
1429 and the AccessLength field indicates which of the bytes within the
1430 MemElem data should actually be stored; only these bytes in memory
1431 will be changed. */
53b9417e 1432
18c64df6 1433void
01737f42
AC		 1434store_memory (SIM_DESC sd,
1435 sim_cpu *cpu,
1436 address_word cia,
1437 int CCA,
1438 int AccessLength,
1439 uword64 MemElem,
1440 uword64 MemElem1, /* High order 64 bits */
1441 address_word pAddr,
1442 address_word vAddr)
8bae0a0c
JSC		 1443{
1444#ifdef DEBUG
63be8feb 1445 sim_io_printf(sd,"DBG: StoreMemory(%d,%d,0x%s,0x%s,0x%s,0x%s)\n",CCA,AccessLength,pr_uword64(MemElem),pr_uword64(MemElem1),pr_addr(pAddr),pr_addr(vAddr));
8bae0a0c 1446#endif /* DEBUG */
63be8feb 1447
8bae0a0c
JSC		 1448#if defined(WARN_MEM)
1449 if (CCA != uncached)
63be8feb 1450 sim_io_eprintf(sd,"StoreMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA);
8bae0a0c 1451#endif /* WARN_MEM */
63be8feb
AC		 1452
1453 if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK)
1454 sim_io_error(sd,"AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",AccessLength,(LOADDRMASK + 1)<<2,pr_addr(pAddr));
1455
8bae0a0c 1456#if defined(TRACE)
01737f42 1457 dotrace (SD, CPU, tracefh,1,(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"store");
8bae0a0c 1458#endif /* TRACE */
63be8feb 1459
8bae0a0c 1460#ifdef DEBUG
63be8feb 1461 printf("DBG: StoreMemory: offset = %d MemElem = 0x%s%s\n",(unsigned int)(pAddr & LOADDRMASK),pr_uword64(MemElem1),pr_uword64(MemElem));
8bae0a0c 1462#endif /* DEBUG */
63be8feb
AC		 1463
1464 /* See also load_memory */
1465 if (AccessLength <= AccessLength_DOUBLEWORD)
1466 {
1467 if (BigEndianMem)
1468 /* for big endian target, byte (pAddr&LOADDRMASK == 0) is
1469 shifted to the most significant byte position. */
1470 MemElem >>= (((7 - (pAddr & LOADDRMASK)) - AccessLength) * 8);
1471 else
1472 /* For little endian target, byte (pAddr&LOADDRMASK == 0)
1473 is already in the correct postition. */
1474 MemElem >>= ((pAddr & LOADDRMASK) * 8);
1475 }
1476
8bae0a0c 1477#ifdef DEBUG
63be8feb 1478 printf("DBG: StoreMemory: shift = %d MemElem = 0x%s%s\n",shift,pr_uword64(MemElem1),pr_uword64(MemElem));
8bae0a0c 1479#endif /* DEBUG */
63be8feb
AC		 1480
1481 switch (AccessLength)
1482 {
1483 case AccessLength_QUADWORD :
1484 {
1485 unsigned_16 val = U16_8 (MemElem1, MemElem);
01737f42 1486 sim_core_write_aligned_16 (cpu, NULL_CIA,
63be8feb
AC		 1487 sim_core_write_map, pAddr, val);
1488 break;
8bae0a0c 1489 }
63be8feb 1490 case AccessLength_DOUBLEWORD :
01737f42 1491 sim_core_write_aligned_8 (cpu, NULL_CIA,
63be8feb
AC		 1492 sim_core_write_map, pAddr, MemElem);
1493 break;
1494 case AccessLength_SEPTIBYTE :
01737f42 1495 sim_core_write_misaligned_7 (cpu, NULL_CIA,
63be8feb
AC		 1496 sim_core_write_map, pAddr, MemElem);
1497 break;
1498 case AccessLength_SEXTIBYTE :
01737f42 1499 sim_core_write_misaligned_6 (cpu, NULL_CIA,
63be8feb
AC		 1500 sim_core_write_map, pAddr, MemElem);
1501 break;
1502 case AccessLength_QUINTIBYTE :
01737f42 1503 sim_core_write_misaligned_5 (cpu, NULL_CIA,
63be8feb
AC		 1504 sim_core_write_map, pAddr, MemElem);
1505 break;
1506 case AccessLength_WORD :
01737f42 1507 sim_core_write_aligned_4 (cpu, NULL_CIA,
63be8feb
AC		 1508 sim_core_write_map, pAddr, MemElem);
1509 break;
1510 case AccessLength_TRIPLEBYTE :
01737f42 1511 sim_core_write_misaligned_3 (cpu, NULL_CIA,
63be8feb
AC		 1512 sim_core_write_map, pAddr, MemElem);
1513 break;
1514 case AccessLength_HALFWORD :
01737f42 1515 sim_core_write_aligned_2 (cpu, NULL_CIA,
63be8feb
AC		 1516 sim_core_write_map, pAddr, MemElem);
1517 break;
1518 case AccessLength_BYTE :
01737f42 1519 sim_core_write_aligned_1 (cpu, NULL_CIA,
63be8feb
AC		 1520 sim_core_write_map, pAddr, MemElem);
1521 break;
1522 default:
1523 abort ();
1524 }
1525
8bae0a0c
JSC		 1526 return;
1527}
1528
53b9417e 1529
dad6f1f3 1530unsigned32
7ce8b917 1531ifetch32 (SIM_DESC sd,
01737f42 1532 sim_cpu *cpu,
7ce8b917
AC		 1533 address_word cia,
1534 address_word vaddr)
dad6f1f3
AC		 1535{
1536 /* Copy the action of the LW instruction */
1537 address_word reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0);
1538 address_word bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0);
1539 unsigned64 value;
1540 address_word paddr;
1541 unsigned32 instruction;
1542 unsigned byte;
1543 int cca;
1544 AddressTranslation (vaddr, isINSTRUCTION, isLOAD, &paddr, &cca, isTARGET, isREAL);
1545 paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2)));
1546 LoadMemory (&value, NULL, cca, AccessLength_WORD, paddr, vaddr, isINSTRUCTION, isREAL);
1547 byte = ((vaddr & LOADDRMASK) ^ (bigend << 2));
1548 instruction = ((value >> (8 * byte)) & 0xFFFFFFFF);
1549 return instruction;
1550}
1551
1552
8bae0a0c
JSC		 1553/* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1554/* Order loads and stores to synchronise shared memory. Perform the
1555 action necessary to make the effects of groups of synchronizable
1556 loads and stores indicated by stype occur in the same order for all
1557 processors. */
ea985d24 1558void
01737f42
AC		 1559sync_operation (SIM_DESC sd,
1560 sim_cpu *cpu,
1561 address_word cia,
1562 int stype)
8bae0a0c
JSC		 1563{
1564#ifdef DEBUG
18c64df6 1565 sim_io_printf(sd,"SyncOperation(%d) : TODO\n",stype);
8bae0a0c
JSC		 1566#endif /* DEBUG */
1567 return;
1568}
1569
1570/* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1571/* Signal an exception condition. This will result in an exception
1572 that aborts the instruction. The instruction operation pseudocode
50a2a691 1573 will never see a return from this function call. */
2e61a3ad 1574
18c64df6 1575void
7ce8b917 1576signal_exception (SIM_DESC sd,
01737f42 1577 sim_cpu *cpu,
7ce8b917
AC		 1578 address_word cia,
1579 int exception,...)
8bae0a0c 1580{
56e7c849 1581 int vector;
6eedf3f4
MA		 1582
1583#ifdef DEBUG
95469ceb 1584 sim_io_printf(sd,"DBG: SignalException(%d) PC = 0x%s\n",exception,pr_addr(cia));
6eedf3f4
MA		 1585#endif /* DEBUG */
1586
8bae0a0c
JSC		 1587 /* Ensure that any active atomic read/modify/write operation will fail: */
1588 LLBIT = 0;
1589
1590 switch (exception) {
1591 /* TODO: For testing purposes I have been ignoring TRAPs. In
1592 reality we should either simulate them, or allow the user to
6eedf3f4
MA		 1593 ignore them at run-time.
1594 Same for SYSCALL */
8bae0a0c 1595 case Trap :
95469ceb 1596 sim_io_eprintf(sd,"Ignoring instruction TRAP (PC 0x%s)\n",pr_addr(cia));
8bae0a0c
JSC		 1597 break;
1598
6eedf3f4
MA		 1599 case SystemCall :
1600 {
1601 va_list ap;
1602 unsigned int instruction;
1603 unsigned int code;
1604
1605 va_start(ap,exception);
1606 instruction = va_arg(ap,unsigned int);
1607 va_end(ap);
1608
1609 code = (instruction >> 6) & 0xFFFFF;
1610
18c64df6 1611 sim_io_eprintf(sd,"Ignoring instruction `syscall %d' (PC 0x%s)\n",
95469ceb 1612 code, pr_addr(cia));
6eedf3f4
MA		 1613 }
1614 break;
1615
1616 case DebugBreakPoint :
1617 if (! (Debug & Debug_DM))
1618 {
1619 if (INDELAYSLOT())
1620 {
1621 CANCELDELAYSLOT();
1622
1623 Debug |= Debug_DBD; /* signaled from within in delay slot */
95469ceb 1624 DEPC = cia - 4; /* reference the branch instruction */
6eedf3f4
MA		 1625 }
1626 else
1627 {
1628 Debug &= ~Debug_DBD; /* not signaled from within a delay slot */
95469ceb 1629 DEPC = cia;
6eedf3f4
MA		 1630 }
1631
1632 Debug |= Debug_DM; /* in debugging mode */
1633 Debug |= Debug_DBp; /* raising a DBp exception */
1634 PC = 0xBFC00200;
01737f42 1635 sim_engine_restart (SD, CPU, NULL, NULL_CIA);
6eedf3f4
MA		 1636 }
1637 break;
1638
8bae0a0c
JSC		 1639 case ReservedInstruction :
1640 {
1641 va_list ap;
1642 unsigned int instruction;
1643 va_start(ap,exception);
1644 instruction = va_arg(ap,unsigned int);
1645 va_end(ap);
1646 /* Provide simple monitor support using ReservedInstruction
1647 exceptions. The following code simulates the fixed vector
1648 entry points into the IDT monitor by causing a simulator
1649 trap, performing the monitor operation, and returning to
1650 the address held in the $ra register (standard PCS return
1651 address). This means we only need to pre-load the vector
1652 space with suitable instruction values. For systems were
1653 actual trap instructions are used, we would not need to
1654 perform this magic. */
7ce8b917
AC		 1655 if ((instruction & RSVD_INSTRUCTION_MASK) == RSVD_INSTRUCTION)
1656 {
01737f42 1657 sim_monitor (SD, CPU, cia, ((instruction >> RSVD_INSTRUCTION_ARG_SHIFT) & RSVD_INSTRUCTION_ARG_MASK) );
7ce8b917
AC		 1658 /* NOTE: This assumes that a branch-and-link style
1659 instruction was used to enter the vector (which is the
1660 case with the current IDT monitor). */
01737f42 1661 sim_engine_restart (SD, CPU, NULL, RA);
7ce8b917 1662 }
7e6c297e
ILT		 1663 /* Look for the mips16 entry and exit instructions, and
1664 simulate a handler for them. */
95469ceb 1665 else if ((cia & 1) != 0
7e6c297e 1666 && (instruction & 0xf81f) == 0xe809
7ce8b917
AC		 1667 && (instruction & 0x0c0) != 0x0c0)
1668 {
01737f42 1669 mips16_entry (SD, CPU, cia, instruction);
7ce8b917
AC		 1670 sim_engine_restart (sd, NULL, NULL, NULL_CIA);
1671 }
1672 /* else fall through to normal exception processing */
95469ceb 1673 sim_io_eprintf(sd,"ReservedInstruction 0x%08X at PC = 0x%s\n",instruction,pr_addr(cia));
8bae0a0c
JSC		 1674 }
1675
05d1322f 1676 case BreakPoint:
e3d12c65 1677#ifdef DEBUG
95469ceb 1678 sim_io_printf(sd,"DBG: SignalException(%d) PC = 0x%s\n",exception,pr_addr(cia));
8bae0a0c 1679#endif /* DEBUG */
05d1322f
JL		 1680 /* Keep a copy of the current A0 in-case this is the program exit
1681 breakpoint: */
1682 {
1683 va_list ap;
1684 unsigned int instruction;
1685 va_start(ap,exception);
1686 instruction = va_arg(ap,unsigned int);
1687 va_end(ap);
1688 /* Check for our special terminating BREAK: */
1689 if ((instruction & 0x03FFFFC0) == 0x03ff0000) {
01737f42 1690 sim_engine_halt (SD, CPU, NULL, cia,
05d1322f
JL		 1691 sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
1692 }
1693 }
0c2c5f61 1694 if (STATE & simDELAYSLOT)
95469ceb 1695 PC = cia - 4; /* reference the branch instruction */
05d1322f 1696 else
95469ceb 1697 PC = cia;
01737f42 1698 sim_engine_halt (SD, CPU, NULL, cia,
232156de 1699 sim_stopped, SIM_SIGTRAP);
05d1322f
JL		 1700
1701 default:
8bae0a0c
JSC		 1702 /* Store exception code into current exception id variable (used
1703 by exit code): */
1704
1705 /* TODO: If not simulating exceptions then stop the simulator
1706 execution. At the moment we always stop the simulation. */
e3d12c65 1707
56e7c849
AC		 1708 /* See figure 5-17 for an outline of the code below */
1709 if (! (SR & status_EXL))
1710 {
1711 CAUSE = (exception << 2);
0c2c5f61 1712 if (STATE & simDELAYSLOT)
56e7c849 1713 {
0c2c5f61 1714 STATE &= ~simDELAYSLOT;
56e7c849 1715 CAUSE |= cause_BD;
95469ceb 1716 EPC = (cia - 4); /* reference the branch instruction */
56e7c849
AC		 1717 }
1718 else
95469ceb 1719 EPC = cia;
56e7c849
AC		 1720 /* FIXME: TLB et.al. */
1721 vector = 0x180;
1722 }
1723 else
1724 {
05d1322f 1725 CAUSE = (exception << 2);
56e7c849
AC		 1726 vector = 0x180;
1727 }
1728 SR |= status_EXL;
e3d12c65
DE		 1729 /* Store exception code into current exception id variable (used
1730 by exit code): */
56e7c849
AC		 1731 if (SR & status_BEV)
1732 PC = (signed)0xBFC00200 + 0x180;
1733 else
1734 PC = (signed)0x80000000 + 0x180;
1735
50a2a691
AC		 1736 switch ((CAUSE >> 2) & 0x1F)
1737 {
1738 case Interrupt:
56e7c849
AC		 1739 /* Interrupts arrive during event processing, no need to
1740 restart */
1741 return;
50a2a691
AC		 1742
1743 case TLBModification:
1744 case TLBLoad:
1745 case TLBStore:
1746 case AddressLoad:
1747 case AddressStore:
1748 case InstructionFetch:
1749 case DataReference:
56e7c849
AC		 1750 /* The following is so that the simulator will continue from the
1751 exception address on breakpoint operations. */
1752 PC = EPC;
01737f42 1753 sim_engine_halt (SD, CPU, NULL, NULL_CIA,
232156de 1754 sim_stopped, SIM_SIGBUS);
50a2a691
AC		 1755
1756 case ReservedInstruction:
1757 case CoProcessorUnusable:
56e7c849 1758 PC = EPC;
01737f42 1759 sim_engine_halt (SD, CPU, NULL, NULL_CIA,
232156de 1760 sim_stopped, SIM_SIGILL);
50a2a691
AC		 1761
1762 case IntegerOverflow:
1763 case FPE:
01737f42 1764 sim_engine_halt (SD, CPU, NULL, NULL_CIA,
232156de 1765 sim_stopped, SIM_SIGFPE);
50a2a691
AC		 1766
1767 case Trap:
1768 case Watch:
1769 case SystemCall:
56e7c849 1770 PC = EPC;
01737f42 1771 sim_engine_halt (SD, CPU, NULL, NULL_CIA,
232156de 1772 sim_stopped, SIM_SIGTRAP);
50a2a691 1773
05d1322f
JL		 1774 case BreakPoint:
1775 PC = EPC;
01737f42 1776 sim_engine_abort (SD, CPU, NULL_CIA,
05d1322f
JL		 1777 "FATAL: Should not encounter a breakpoint\n");
1778
50a2a691 1779 default : /* Unknown internal exception */
56e7c849 1780 PC = EPC;
01737f42 1781 sim_engine_halt (SD, CPU, NULL, NULL_CIA,
232156de 1782 sim_stopped, SIM_SIGABRT);
50a2a691
AC		 1783
1784 }
8bae0a0c
JSC		 1785
1786 case SimulatorFault:
1787 {
1788 va_list ap;
1789 char *msg;
1790 va_start(ap,exception);
1791 msg = va_arg(ap,char *);
50a2a691 1792 va_end(ap);
01737f42 1793 sim_engine_abort (SD, CPU, NULL_CIA,
2e61a3ad 1794 "FATAL: Simulator error \"%s\"\n",msg);
8bae0a0c 1795 }
8bae0a0c
JSC		 1796 }
1797
1798 return;
1799}
1800
1801#if defined(WARN_RESULT)
1802/* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1803/* This function indicates that the result of the operation is
1804 undefined. However, this should not affect the instruction
1805 stream. All that is meant to happen is that the destination
1806 register is set to an undefined result. To keep the simulator
1807 simple, we just don't bother updating the destination register, so
1808 the overall result will be undefined. If desired we can stop the
1809 simulator by raising a pseudo-exception. */
95469ceb 1810#define UndefinedResult() undefined_result (sd,cia)
8bae0a0c 1811static void
95469ceb
AC		 1812undefined_result(sd,cia)
1813 SIM_DESC sd;
1814 address_word cia;
8bae0a0c 1815{
95469ceb 1816 sim_io_eprintf(sd,"UndefinedResult: PC = 0x%s\n",pr_addr(cia));
8bae0a0c
JSC		 1817#if 0 /* Disabled for the moment, since it actually happens a lot at the moment. */
1818 state |= simSTOP;
1819#endif
1820 return;
1821}
1822#endif /* WARN_RESULT */
1823
18c64df6 1824void
01737f42
AC		 1825cache_op (SIM_DESC sd,
1826 sim_cpu *cpu,
1827 address_word cia,
1828 int op,
1829 address_word pAddr,
1830 address_word vAddr,
1831 unsigned int instruction)
8bae0a0c 1832{
f24b7b69
JSC		 1833#if 1 /* stop warning message being displayed (we should really just remove the code) */
1834 static int icache_warning = 1;
1835 static int dcache_warning = 1;
1836#else
a9f7253f
JSC		 1837 static int icache_warning = 0;
1838 static int dcache_warning = 0;
f24b7b69 1839#endif
a9f7253f 1840
8bae0a0c
JSC		 1841 /* If CP0 is not useable (User or Supervisor mode) and the CP0
1842 enable bit in the Status Register is clear - a coprocessor
1843 unusable exception is taken. */
a9f7253f 1844#if 0
95469ceb 1845 sim_io_printf(sd,"TODO: Cache availability checking (PC = 0x%s)\n",pr_addr(cia));
a9f7253f 1846#endif
8bae0a0c
JSC		 1847
1848 switch (op & 0x3) {
1849 case 0: /* instruction cache */
1850 switch (op >> 2) {
1851 case 0: /* Index Invalidate */
1852 case 1: /* Index Load Tag */
1853 case 2: /* Index Store Tag */
1854 case 4: /* Hit Invalidate */
1855 case 5: /* Fill */
1856 case 6: /* Hit Writeback */
a9f7253f
JSC		 1857 if (!icache_warning)
1858 {
18c64df6 1859 sim_io_eprintf(sd,"Instruction CACHE operation %d to be coded\n",(op >> 2));
a9f7253f
JSC		 1860 icache_warning = 1;
1861 }
8bae0a0c
JSC		 1862 break;
1863
1864 default:
1865 SignalException(ReservedInstruction,instruction);
1866 break;
1867 }
1868 break;
1869
1870 case 1: /* data cache */
1871 switch (op >> 2) {
1872 case 0: /* Index Writeback Invalidate */
1873 case 1: /* Index Load Tag */
1874 case 2: /* Index Store Tag */
1875 case 3: /* Create Dirty */
1876 case 4: /* Hit Invalidate */
1877 case 5: /* Hit Writeback Invalidate */
1878 case 6: /* Hit Writeback */
a9f7253f
JSC		 1879 if (!dcache_warning)
1880 {
18c64df6 1881 sim_io_eprintf(sd,"Data CACHE operation %d to be coded\n",(op >> 2));
a9f7253f
JSC		 1882 dcache_warning = 1;
1883 }
8bae0a0c
JSC		 1884 break;
1885
1886 default:
1887 SignalException(ReservedInstruction,instruction);
1888 break;
1889 }
1890 break;
1891
1892 default: /* unrecognised cache ID */
1893 SignalException(ReservedInstruction,instruction);
1894 break;
1895 }
1896
1897 return;
1898}
1899
1900/*-- FPU support routines ---------------------------------------------------*/
1901
8bae0a0c
JSC		 1902/* Numbers are held in normalized form. The SINGLE and DOUBLE binary
1903 formats conform to ANSI/IEEE Std 754-1985. */
1904/* SINGLE precision floating:
1905 * seeeeeeeefffffffffffffffffffffff
1906 * s = 1bit = sign
1907 * e = 8bits = exponent
1908 * f = 23bits = fraction
1909 */
1910/* SINGLE precision fixed:
1911 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
1912 * s = 1bit = sign
1913 * i = 31bits = integer
1914 */
1915/* DOUBLE precision floating:
1916 * seeeeeeeeeeeffffffffffffffffffffffffffffffffffffffffffffffffffff
1917 * s = 1bit = sign
1918 * e = 11bits = exponent
1919 * f = 52bits = fraction
1920 */
1921/* DOUBLE precision fixed:
1922 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
1923 * s = 1bit = sign
1924 * i = 63bits = integer
1925 */
1926
1927/* Extract sign-bit: */
1928#define FP_S_s(v) (((v) & ((unsigned)1 << 31)) ? 1 : 0)
e871dd18 1929#define FP_D_s(v) (((v) & ((uword64)1 << 63)) ? 1 : 0)
8bae0a0c
JSC		 1930/* Extract biased exponent: */
1931#define FP_S_be(v) (((v) >> 23) & 0xFF)
1932#define FP_D_be(v) (((v) >> 52) & 0x7FF)
1933/* Extract unbiased Exponent: */
1934#define FP_S_e(v) (FP_S_be(v) - 0x7F)
1935#define FP_D_e(v) (FP_D_be(v) - 0x3FF)
1936/* Extract complete fraction field: */
1937#define FP_S_f(v) ((v) & ~((unsigned)0x1FF << 23))
e871dd18 1938#define FP_D_f(v) ((v) & ~((uword64)0xFFF << 52))
8bae0a0c
JSC		 1939/* Extract numbered fraction bit: */
1940#define FP_S_fb(b,v) (((v) & (1 << (23 - (b)))) ? 1 : 0)
1941#define FP_D_fb(b,v) (((v) & (1 << (52 - (b)))) ? 1 : 0)
1942
1943/* Explicit QNaN values used when value required: */
1944#define FPQNaN_SINGLE (0x7FBFFFFF)
1945#define FPQNaN_WORD (0x7FFFFFFF)
e871dd18
JSC		 1946#define FPQNaN_DOUBLE (((uword64)0x7FF7FFFF << 32) | 0xFFFFFFFF)
1947#define FPQNaN_LONG (((uword64)0x7FFFFFFF << 32) | 0xFFFFFFFF)
8bae0a0c
JSC		 1948
1949/* Explicit Infinity values used when required: */
1950#define FPINF_SINGLE (0x7F800000)
e871dd18 1951#define FPINF_DOUBLE (((uword64)0x7FF00000 << 32) | 0x00000000)
8bae0a0c
JSC		 1952
1953#if 1 /* def DEBUG */
1954#define RMMODE(v) (((v) == FP_RM_NEAREST) ? "Round" : (((v) == FP_RM_TOZERO) ? "Trunc" : (((v) == FP_RM_TOPINF) ? "Ceil" : "Floor")))
1955#define DOFMT(v) (((v) == fmt_single) ? "single" : (((v) == fmt_double) ? "double" : (((v) == fmt_word) ? "word" : (((v) == fmt_long) ? "long" : (((v) == fmt_unknown) ? "<unknown>" : (((v) == fmt_uninterpreted) ? "<uninterpreted>" : "<format error>"))))))
1956#endif /* DEBUG */
1957
18c64df6 1958uword64
01737f42
AC		 1959value_fpr (SIM_DESC sd,
1960 sim_cpu *cpu,
1961 address_word cia,
1962 int fpr,
1963 FP_formats fmt)
8bae0a0c 1964{
50a2a691 1965 uword64 value = 0;
8bae0a0c
JSC		 1966 int err = 0;
1967
1968 /* Treat unused register values, as fixed-point 64bit values: */
1969 if ((fmt == fmt_uninterpreted) || (fmt == fmt_unknown))
1970#if 1
1971 /* If request to read data as "uninterpreted", then use the current
1972 encoding: */
0c2c5f61 1973 fmt = FPR_STATE[fpr];
8bae0a0c
JSC		 1974#else
1975 fmt = fmt_long;
1976#endif
1977
1978 /* For values not yet accessed, set to the desired format: */
0c2c5f61
AC		 1979 if (FPR_STATE[fpr] == fmt_uninterpreted) {
1980 FPR_STATE[fpr] = fmt;
8bae0a0c
JSC		 1981#ifdef DEBUG
1982 printf("DBG: Register %d was fmt_uninterpreted. Now %s\n",fpr,DOFMT(fmt));
1983#endif /* DEBUG */
1984 }
0c2c5f61 1985 if (fmt != FPR_STATE[fpr]) {
95469ceb 1986 sim_io_eprintf(sd,"FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",fpr,DOFMT(FPR_STATE[fpr]),DOFMT(fmt),pr_addr(cia));
0c2c5f61 1987 FPR_STATE[fpr] = fmt_unknown;
8bae0a0c
JSC		 1988 }
1989
0c2c5f61 1990 if (FPR_STATE[fpr] == fmt_unknown) {
8bae0a0c
JSC		 1991 /* Set QNaN value: */
1992 switch (fmt) {
1993 case fmt_single:
1994 value = FPQNaN_SINGLE;
1995 break;
1996
1997 case fmt_double:
1998 value = FPQNaN_DOUBLE;
1999 break;
2000
2001 case fmt_word:
2002 value = FPQNaN_WORD;
2003 break;
2004
2005 case fmt_long:
2006 value = FPQNaN_LONG;
2007 break;
2008
2009 default:
2010 err = -1;
2011 break;
2012 }
2013 } else if (SizeFGR() == 64) {
2014 switch (fmt) {
2015 case fmt_single:
2016 case fmt_word:
2017 value = (FGR[fpr] & 0xFFFFFFFF);
2018 break;
2019
2020 case fmt_uninterpreted:
2021 case fmt_double:
2022 case fmt_long:
2023 value = FGR[fpr];
2024 break;
2025
2026 default :
2027 err = -1;
2028 break;
2029 }
da0bce9c 2030 } else {
8bae0a0c
JSC		 2031 switch (fmt) {
2032 case fmt_single:
2033 case fmt_word:
2034 value = (FGR[fpr] & 0xFFFFFFFF);
2035 break;
2036
2037 case fmt_uninterpreted:
2038 case fmt_double:
2039 case fmt_long:
da0bce9c
ILT		 2040 if ((fpr & 1) == 0) { /* even registers only */
2041 value = ((((uword64)FGR[fpr+1]) << 32) | (FGR[fpr] & 0xFFFFFFFF));
2042 } else {
18c64df6 2043 SignalException(ReservedInstruction,0);
da0bce9c 2044 }
8bae0a0c
JSC		 2045 break;
2046
2047 default :
2048 err = -1;
2049 break;
2050 }
2051 }
2052
2053 if (err)
18c64df6 2054 SignalExceptionSimulatorFault ("Unrecognised FP format in ValueFPR()");
8bae0a0c
JSC		 2055
2056#ifdef DEBUG
95469ceb 2057 printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(cia),SizeFGR());
8bae0a0c
JSC		 2058#endif /* DEBUG */
2059
2060 return(value);
2061}
2062
18c64df6 2063void
01737f42
AC		 2064store_fpr (SIM_DESC sd,
2065 sim_cpu *cpu,
2066 address_word cia,
2067 int fpr,
2068 FP_formats fmt,
2069 uword64 value)
8bae0a0c
JSC		 2070{
2071 int err = 0;
2072
2073#ifdef DEBUG
95469ceb 2074 printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(cia),SizeFGR());
8bae0a0c
JSC		 2075#endif /* DEBUG */
2076
2077 if (SizeFGR() == 64) {
2078 switch (fmt) {
a09a30d2
AC		 2079 case fmt_uninterpreted_32:
2080 fmt = fmt_uninterpreted;
8bae0a0c
JSC		 2081 case fmt_single :
2082 case fmt_word :
e871dd18 2083 FGR[fpr] = (((uword64)0xDEADC0DE << 32) | (value & 0xFFFFFFFF));
0c2c5f61 2084 FPR_STATE[fpr] = fmt;
8bae0a0c
JSC		 2085 break;
2086
a09a30d2
AC		 2087 case fmt_uninterpreted_64:
2088 fmt = fmt_uninterpreted;
8bae0a0c
JSC		 2089 case fmt_uninterpreted:
2090 case fmt_double :
2091 case fmt_long :
2092 FGR[fpr] = value;
0c2c5f61 2093 FPR_STATE[fpr] = fmt;
8bae0a0c
JSC		 2094 break;
2095
2096 default :
0c2c5f61 2097 FPR_STATE[fpr] = fmt_unknown;
8bae0a0c
JSC		 2098 err = -1;
2099 break;
2100 }
da0bce9c 2101 } else {
8bae0a0c 2102 switch (fmt) {
a09a30d2
AC		 2103 case fmt_uninterpreted_32:
2104 fmt = fmt_uninterpreted;
8bae0a0c
JSC		 2105 case fmt_single :
2106 case fmt_word :
8bae0a0c 2107 FGR[fpr] = (value & 0xFFFFFFFF);
0c2c5f61 2108 FPR_STATE[fpr] = fmt;
8bae0a0c
JSC		 2109 break;
2110
a09a30d2
AC		 2111 case fmt_uninterpreted_64:
2112 fmt = fmt_uninterpreted;
8bae0a0c
JSC		 2113 case fmt_uninterpreted:
2114 case fmt_double :
2115 case fmt_long :
da0bce9c
ILT		 2116 if ((fpr & 1) == 0) { /* even register number only */
2117 FGR[fpr+1] = (value >> 32);
2118 FGR[fpr] = (value & 0xFFFFFFFF);
0c2c5f61
AC		 2119 FPR_STATE[fpr + 1] = fmt;
2120 FPR_STATE[fpr] = fmt;
da0bce9c 2121 } else {
0c2c5f61
AC		 2122 FPR_STATE[fpr] = fmt_unknown;
2123 FPR_STATE[fpr + 1] = fmt_unknown;
18c64df6 2124 SignalException(ReservedInstruction,0);
da0bce9c 2125 }
8bae0a0c
JSC		 2126 break;
2127
2128 default :
0c2c5f61 2129 FPR_STATE[fpr] = fmt_unknown;
8bae0a0c
JSC		 2130 err = -1;
2131 break;
2132 }
e871dd18
JSC		 2133 }
2134#if defined(WARN_RESULT)
2135 else
2136 UndefinedResult();
2137#endif /* WARN_RESULT */
8bae0a0c
JSC		 2138
2139 if (err)
18c64df6 2140 SignalExceptionSimulatorFault ("Unrecognised FP format in StoreFPR()");
8bae0a0c
JSC		 2141
2142#ifdef DEBUG
53b9417e 2143 printf("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",fpr,pr_addr(FGR[fpr]),DOFMT(fmt));
8bae0a0c
JSC		 2144#endif /* DEBUG */
2145
2146 return;
2147}
2148
18c64df6 2149int
8bae0a0c 2150NaN(op,fmt)
e871dd18 2151 uword64 op;
8bae0a0c
JSC		 2152 FP_formats fmt;
2153{
2154 int boolean = 0;
8bae0a0c
JSC		 2155 switch (fmt) {
2156 case fmt_single:
8bae0a0c 2157 case fmt_word:
76ef4165
FL		 2158 {
2159 sim_fpu wop;
2160 sim_fpu_32to (&wop, op);
2161 boolean = sim_fpu_is_nan (&wop);
2162 break;
2163 }
2164 case fmt_double:
8bae0a0c 2165 case fmt_long:
76ef4165
FL		 2166 {
2167 sim_fpu wop;
2168 sim_fpu_64to (&wop, op);
2169 boolean = sim_fpu_is_nan (&wop);
2170 break;
2171 }
50a2a691
AC		 2172 default:
2173 fprintf (stderr, "Bad switch\n");
2174 abort ();
8bae0a0c
JSC		 2175 }
2176
2177#ifdef DEBUG
53b9417e 2178printf("DBG: NaN: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op),DOFMT(fmt));
8bae0a0c
JSC		 2179#endif /* DEBUG */
2180
2181 return(boolean);
2182}
2183
18c64df6 2184int
8bae0a0c 2185Infinity(op,fmt)
e871dd18 2186 uword64 op;
8bae0a0c
JSC		 2187 FP_formats fmt;
2188{
2189 int boolean = 0;
2190
2191#ifdef DEBUG
95469ceb 2192 printf("DBG: Infinity: format %s 0x%s\n",DOFMT(fmt),pr_addr(op));
8bae0a0c
JSC		 2193#endif /* DEBUG */
2194
8bae0a0c
JSC		 2195 switch (fmt) {
2196 case fmt_single:
76ef4165
FL		 2197 {
2198 sim_fpu wop;
2199 sim_fpu_32to (&wop, op);
2200 boolean = sim_fpu_is_infinity (&wop);
2201 break;
2202 }
8bae0a0c 2203 case fmt_double:
76ef4165
FL		 2204 {
2205 sim_fpu wop;
2206 sim_fpu_64to (&wop, op);
2207 boolean = sim_fpu_is_infinity (&wop);
2208 break;
2209 }
8bae0a0c
JSC		 2210 default:
2211 printf("DBG: TODO: unrecognised format (%s) for Infinity check\n",DOFMT(fmt));
2212 break;
2213 }
2214
2215#ifdef DEBUG
53b9417e 2216 printf("DBG: Infinity: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op),DOFMT(fmt));
8bae0a0c
JSC		 2217#endif /* DEBUG */
2218
2219 return(boolean);
2220}
2221
18c64df6 2222int
8bae0a0c 2223Less(op1,op2,fmt)
e871dd18
JSC		 2224 uword64 op1;
2225 uword64 op2;
8bae0a0c
JSC		 2226 FP_formats fmt;
2227{
2228 int boolean = 0;
2229
e871dd18
JSC		 2230 /* Argument checking already performed by the FPCOMPARE code */
2231
8bae0a0c 2232#ifdef DEBUG
53b9417e 2233 printf("DBG: Less: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
8bae0a0c
JSC		 2234#endif /* DEBUG */
2235
8bae0a0c
JSC		 2236 /* The format type should already have been checked: */
2237 switch (fmt) {
2238 case fmt_single:
2239 {
76ef4165
FL		 2240 sim_fpu wop1;
2241 sim_fpu wop2;
2242 sim_fpu_32to (&wop1, op1);
2243 sim_fpu_32to (&wop2, op2);
2244 boolean = sim_fpu_is_lt (&wop1, &wop2);
2245 break;
8bae0a0c 2246 }
8bae0a0c 2247 case fmt_double:
76ef4165
FL		 2248 {
2249 sim_fpu wop1;
2250 sim_fpu wop2;
2251 sim_fpu_64to (&wop1, op1);
2252 sim_fpu_64to (&wop2, op2);
2253 boolean = sim_fpu_is_lt (&wop1, &wop2);
2254 break;
2255 }
50a2a691
AC		 2256 default:
2257 fprintf (stderr, "Bad switch\n");
2258 abort ();
8bae0a0c
JSC		 2259 }
2260
2261#ifdef DEBUG
2262 printf("DBG: Less: returning %d (format = %s)\n",boolean,DOFMT(fmt));
2263#endif /* DEBUG */
2264
2265 return(boolean);
2266}
2267
18c64df6 2268int
8bae0a0c 2269Equal(op1,op2,fmt)
e871dd18
JSC		 2270 uword64 op1;
2271 uword64 op2;
8bae0a0c
JSC		 2272 FP_formats fmt;
2273{
2274 int boolean = 0;
2275
e871dd18
JSC		 2276 /* Argument checking already performed by the FPCOMPARE code */
2277
8bae0a0c 2278#ifdef DEBUG
53b9417e 2279 printf("DBG: Equal: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
8bae0a0c
JSC		 2280#endif /* DEBUG */
2281
8bae0a0c
JSC		 2282 /* The format type should already have been checked: */
2283 switch (fmt) {
2284 case fmt_single:
76ef4165
FL		 2285 {
2286 sim_fpu wop1;
2287 sim_fpu wop2;
2288 sim_fpu_32to (&wop1, op1);
2289 sim_fpu_32to (&wop2, op2);
2290 boolean = sim_fpu_is_eq (&wop1, &wop2);
2291 break;
2292 }
8bae0a0c 2293 case fmt_double:
76ef4165
FL		 2294 {
2295 sim_fpu wop1;
2296 sim_fpu wop2;
2297 sim_fpu_64to (&wop1, op1);
2298 sim_fpu_64to (&wop2, op2);
2299 boolean = sim_fpu_is_eq (&wop1, &wop2);
2300 break;
2301 }
50a2a691
AC		 2302 default:
2303 fprintf (stderr, "Bad switch\n");
2304 abort ();
8bae0a0c
JSC		 2305 }
2306
2307#ifdef DEBUG
2308 printf("DBG: Equal: returning %d (format = %s)\n",boolean,DOFMT(fmt));
2309#endif /* DEBUG */
2310
2311 return(boolean);
2312}
2313
18c64df6 2314uword64
a9f7253f
JSC		 2315AbsoluteValue(op,fmt)
2316 uword64 op;
2317 FP_formats fmt;
2318{
50a2a691 2319 uword64 result = 0;
a9f7253f
JSC		 2320
2321#ifdef DEBUG
53b9417e 2322 printf("DBG: AbsoluteValue: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
a9f7253f
JSC		 2323#endif /* DEBUG */
2324
2325 /* The format type should already have been checked: */
2326 switch (fmt) {
2327 case fmt_single:
2328 {
76ef4165
FL		 2329 sim_fpu wop;
2330 unsigned32 ans;
2331 sim_fpu_32to (&wop, op);
2332 sim_fpu_abs (&wop, &wop);
2333 sim_fpu_to32 (&ans, &wop);
2334 result = ans;
2335 break;
a9f7253f 2336 }
a9f7253f
JSC		 2337 case fmt_double:
2338 {
76ef4165
FL		 2339 sim_fpu wop;
2340 unsigned64 ans;
2341 sim_fpu_64to (&wop, op);
2342 sim_fpu_abs (&wop, &wop);
2343 sim_fpu_to64 (&ans, &wop);
2344 result = ans;
2345 break;
a9f7253f 2346 }
50a2a691
AC		 2347 default:
2348 fprintf (stderr, "Bad switch\n");
2349 abort ();
a9f7253f
JSC		 2350 }
2351
2352 return(result);
2353}
2354
18c64df6 2355uword64
8bae0a0c 2356Negate(op,fmt)
e871dd18 2357 uword64 op;
8bae0a0c
JSC		 2358 FP_formats fmt;
2359{
50a2a691 2360 uword64 result = 0;
8bae0a0c
JSC		 2361
2362#ifdef DEBUG
53b9417e 2363 printf("DBG: Negate: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
8bae0a0c
JSC		 2364#endif /* DEBUG */
2365
2366 /* The format type should already have been checked: */
2367 switch (fmt) {
2368 case fmt_single:
2369 {
76ef4165
FL		 2370 sim_fpu wop;
2371 unsigned32 ans;
2372 sim_fpu_32to (&wop, op);
2373 sim_fpu_neg (&wop, &wop);
2374 sim_fpu_to32 (&ans, &wop);
2375 result = ans;
2376 break;
8bae0a0c 2377 }
8bae0a0c
JSC		 2378 case fmt_double:
2379 {
76ef4165
FL		 2380 sim_fpu wop;
2381 unsigned64 ans;
2382 sim_fpu_64to (&wop, op);
2383 sim_fpu_neg (&wop, &wop);
2384 sim_fpu_to64 (&ans, &wop);
2385 result = ans;
2386 break;
8bae0a0c 2387 }
50a2a691
AC		 2388 default:
2389 fprintf (stderr, "Bad switch\n");
2390 abort ();
8bae0a0c
JSC		 2391 }
2392
2393 return(result);
2394}
2395
18c64df6 2396uword64
8bae0a0c 2397Add(op1,op2,fmt)
e871dd18
JSC		 2398 uword64 op1;
2399 uword64 op2;
8bae0a0c
JSC		 2400 FP_formats fmt;
2401{
50a2a691 2402 uword64 result = 0;
8bae0a0c
JSC		 2403
2404#ifdef DEBUG
53b9417e 2405 printf("DBG: Add: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
8bae0a0c
JSC		 2406#endif /* DEBUG */
2407
e871dd18
JSC		 2408 /* The registers must specify FPRs valid for operands of type
2409 "fmt". If they are not valid, the result is undefined. */
8bae0a0c
JSC		 2410
2411 /* The format type should already have been checked: */
2412 switch (fmt) {
2413 case fmt_single:
2414 {
76ef4165
FL		 2415 sim_fpu wop1;
2416 sim_fpu wop2;
2417 sim_fpu ans;
2418 unsigned32 res;
2419 sim_fpu_32to (&wop1, op1);
2420 sim_fpu_32to (&wop2, op2);
2421 sim_fpu_add (&ans, &wop1, &wop2);
2422 sim_fpu_to32 (&res, &ans);
2423 result = res;
2424 break;
8bae0a0c 2425 }
8bae0a0c
JSC		 2426 case fmt_double:
2427 {
76ef4165
FL		 2428 sim_fpu wop1;
2429 sim_fpu wop2;
2430 sim_fpu ans;
2431 unsigned64 res;
2432 sim_fpu_64to (&wop1, op1);
2433 sim_fpu_64to (&wop2, op2);
2434 sim_fpu_add (&ans, &wop1, &wop2);
2435 sim_fpu_to64 (&res, &ans);
2436 result = res;
2437 break;
8bae0a0c 2438 }
50a2a691
AC		 2439 default:
2440 fprintf (stderr, "Bad switch\n");
2441 abort ();
8bae0a0c
JSC		 2442 }
2443
2444#ifdef DEBUG
53b9417e 2445 printf("DBG: Add: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
8bae0a0c
JSC		 2446#endif /* DEBUG */
2447
2448 return(result);
2449}
2450
18c64df6 2451uword64
8bae0a0c 2452Sub(op1,op2,fmt)
e871dd18
JSC		 2453 uword64 op1;
2454 uword64 op2;
8bae0a0c
JSC		 2455 FP_formats fmt;
2456{
50a2a691 2457 uword64 result = 0;
8bae0a0c
JSC		 2458
2459#ifdef DEBUG
53b9417e 2460 printf("DBG: Sub: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
8bae0a0c
JSC		 2461#endif /* DEBUG */
2462
e871dd18
JSC		 2463 /* The registers must specify FPRs valid for operands of type
2464 "fmt". If they are not valid, the result is undefined. */
8bae0a0c
JSC		 2465
2466 /* The format type should already have been checked: */
2467 switch (fmt) {
2468 case fmt_single:
2469 {
76ef4165
FL		 2470 sim_fpu wop1;
2471 sim_fpu wop2;
2472 sim_fpu ans;
2473 unsigned32 res;
2474 sim_fpu_32to (&wop1, op1);
2475 sim_fpu_32to (&wop2, op2);
2476 sim_fpu_sub (&ans, &wop1, &wop2);
2477 sim_fpu_to32 (&res, &ans);
2478 result = res;
8bae0a0c
JSC		 2479 }
2480 break;
2481 case fmt_double:
2482 {
76ef4165
FL		 2483 sim_fpu wop1;
2484 sim_fpu wop2;
2485 sim_fpu ans;
2486 unsigned64 res;
2487 sim_fpu_64to (&wop1, op1);
2488 sim_fpu_64to (&wop2, op2);
2489 sim_fpu_sub (&ans, &wop1, &wop2);
2490 sim_fpu_to64 (&res, &ans);
2491 result = res;
8bae0a0c
JSC		 2492 }
2493 break;
50a2a691
AC		 2494 default:
2495 fprintf (stderr, "Bad switch\n");
2496 abort ();
8bae0a0c
JSC		 2497 }
2498
2499#ifdef DEBUG
53b9417e 2500 printf("DBG: Sub: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
8bae0a0c
JSC		 2501#endif /* DEBUG */
2502
2503 return(result);
2504}
2505
18c64df6 2506uword64
8bae0a0c 2507Multiply(op1,op2,fmt)
e871dd18
JSC		 2508 uword64 op1;
2509 uword64 op2;
8bae0a0c
JSC		 2510 FP_formats fmt;
2511{
50a2a691 2512 uword64 result = 0;
8bae0a0c
JSC		 2513
2514#ifdef DEBUG
53b9417e 2515 printf("DBG: Multiply: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
8bae0a0c
JSC		 2516#endif /* DEBUG */
2517
e871dd18
JSC		 2518 /* The registers must specify FPRs valid for operands of type
2519 "fmt". If they are not valid, the result is undefined. */
8bae0a0c
JSC		 2520
2521 /* The format type should already have been checked: */
2522 switch (fmt) {
2523 case fmt_single:
2524 {
76ef4165
FL		 2525 sim_fpu wop1;
2526 sim_fpu wop2;
2527 sim_fpu ans;
2528 unsigned32 res;
2529 sim_fpu_32to (&wop1, op1);
2530 sim_fpu_32to (&wop2, op2);
2531 sim_fpu_mul (&ans, &wop1, &wop2);
2532 sim_fpu_to32 (&res, &ans);
2533 result = res;
2534 break;
8bae0a0c 2535 }
8bae0a0c
JSC		 2536 case fmt_double:
2537 {
76ef4165
FL		 2538 sim_fpu wop1;
2539 sim_fpu wop2;
2540 sim_fpu ans;
2541 unsigned64 res;
2542 sim_fpu_64to (&wop1, op1);
2543 sim_fpu_64to (&wop2, op2);
2544 sim_fpu_mul (&ans, &wop1, &wop2);
2545 sim_fpu_to64 (&res, &ans);
2546 result = res;
2547 break;
8bae0a0c 2548 }
50a2a691
AC		 2549 default:
2550 fprintf (stderr, "Bad switch\n");
2551 abort ();
8bae0a0c
JSC		 2552 }
2553
2554#ifdef DEBUG
53b9417e 2555 printf("DBG: Multiply: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
8bae0a0c
JSC		 2556#endif /* DEBUG */
2557
2558 return(result);
2559}
2560
18c64df6 2561uword64
8bae0a0c 2562Divide(op1,op2,fmt)
e871dd18
JSC		 2563 uword64 op1;
2564 uword64 op2;
8bae0a0c
JSC		 2565 FP_formats fmt;
2566{
50a2a691 2567 uword64 result = 0;
8bae0a0c
JSC		 2568
2569#ifdef DEBUG
53b9417e 2570 printf("DBG: Divide: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
8bae0a0c
JSC		 2571#endif /* DEBUG */
2572
e871dd18
JSC		 2573 /* The registers must specify FPRs valid for operands of type
2574 "fmt". If they are not valid, the result is undefined. */
8bae0a0c
JSC		 2575
2576 /* The format type should already have been checked: */
2577 switch (fmt) {
2578 case fmt_single:
2579 {
76ef4165
FL		 2580 sim_fpu wop1;
2581 sim_fpu wop2;
2582 sim_fpu ans;
2583 unsigned32 res;
2584 sim_fpu_32to (&wop1, op1);
2585 sim_fpu_32to (&wop2, op2);
2586 sim_fpu_div (&ans, &wop1, &wop2);
2587 sim_fpu_to32 (&res, &ans);
2588 result = res;
2589 break;
8bae0a0c 2590 }
8bae0a0c
JSC		 2591 case fmt_double:
2592 {
76ef4165
FL		 2593 sim_fpu wop1;
2594 sim_fpu wop2;
2595 sim_fpu ans;
2596 unsigned64 res;
2597 sim_fpu_64to (&wop1, op1);
2598 sim_fpu_64to (&wop2, op2);
2599 sim_fpu_div (&ans, &wop1, &wop2);
2600 sim_fpu_to64 (&res, &ans);
2601 result = res;
2602 break;
8bae0a0c 2603 }
50a2a691
AC		 2604 default:
2605 fprintf (stderr, "Bad switch\n");
2606 abort ();
8bae0a0c
JSC		 2607 }
2608
2609#ifdef DEBUG
53b9417e 2610 printf("DBG: Divide: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
8bae0a0c
JSC		 2611#endif /* DEBUG */
2612
2613 return(result);
2614}
2615
18c64df6 2616uword64 UNUSED
8bae0a0c 2617Recip(op,fmt)
e871dd18 2618 uword64 op;
8bae0a0c
JSC		 2619 FP_formats fmt;
2620{
50a2a691 2621 uword64 result = 0;
8bae0a0c
JSC		 2622
2623#ifdef DEBUG
53b9417e 2624 printf("DBG: Recip: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
8bae0a0c
JSC		 2625#endif /* DEBUG */
2626
e871dd18
JSC		 2627 /* The registers must specify FPRs valid for operands of type
2628 "fmt". If they are not valid, the result is undefined. */
8bae0a0c
JSC		 2629
2630 /* The format type should already have been checked: */
2631 switch (fmt) {
2632 case fmt_single:
2633 {
76ef4165
FL		 2634 sim_fpu wop;
2635 sim_fpu ans;
2636 unsigned32 res;
2637 sim_fpu_32to (&wop, op);
2638 sim_fpu_inv (&ans, &wop);
2639 sim_fpu_to32 (&res, &ans);
2640 result = res;
2641 break;
8bae0a0c 2642 }
8bae0a0c
JSC		 2643 case fmt_double:
2644 {
76ef4165
FL		 2645 sim_fpu wop;
2646 sim_fpu ans;
2647 unsigned64 res;
2648 sim_fpu_64to (&wop, op);
2649 sim_fpu_inv (&ans, &wop);
2650 sim_fpu_to64 (&res, &ans);
2651 result = res;
2652 break;
8bae0a0c 2653 }
50a2a691
AC		 2654 default:
2655 fprintf (stderr, "Bad switch\n");
2656 abort ();
8bae0a0c
JSC		 2657 }
2658
2659#ifdef DEBUG
53b9417e 2660 printf("DBG: Recip: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
8bae0a0c
JSC		 2661#endif /* DEBUG */
2662
2663 return(result);
2664}
2665
18c64df6 2666uword64
8bae0a0c 2667SquareRoot(op,fmt)
e871dd18 2668 uword64 op;
8bae0a0c
JSC		 2669 FP_formats fmt;
2670{
50a2a691 2671 uword64 result = 0;
8bae0a0c
JSC		 2672
2673#ifdef DEBUG
53b9417e 2674 printf("DBG: SquareRoot: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
8bae0a0c
JSC		 2675#endif /* DEBUG */
2676
e871dd18
JSC		 2677 /* The registers must specify FPRs valid for operands of type
2678 "fmt". If they are not valid, the result is undefined. */
8bae0a0c
JSC		 2679
2680 /* The format type should already have been checked: */
2681 switch (fmt) {
2682 case fmt_single:
2683 {
76ef4165
FL		 2684 sim_fpu wop;
2685 sim_fpu ans;
2686 unsigned32 res;
2687 sim_fpu_32to (&wop, op);
2688 sim_fpu_sqrt (&ans, &wop);
2689 sim_fpu_to32 (&res, &ans);
2690 result = res;
2691 break;
8bae0a0c 2692 }
8bae0a0c
JSC		 2693 case fmt_double:
2694 {
76ef4165
FL		 2695 sim_fpu wop;
2696 sim_fpu ans;
2697 unsigned64 res;
2698 sim_fpu_64to (&wop, op);
2699 sim_fpu_sqrt (&ans, &wop);
2700 sim_fpu_to64 (&res, &ans);
2701 result = res;
2702 break;
8bae0a0c 2703 }
50a2a691
AC		 2704 default:
2705 fprintf (stderr, "Bad switch\n");
2706 abort ();
8bae0a0c
JSC		 2707 }
2708
2709#ifdef DEBUG
53b9417e 2710 printf("DBG: SquareRoot: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
8bae0a0c
JSC		 2711#endif /* DEBUG */
2712
2713 return(result);
2714}
2715
18c64df6 2716uword64
01737f42
AC		 2717convert (SIM_DESC sd,
2718 sim_cpu *cpu,
2719 address_word cia,
2720 int rm,
2721 uword64 op,
2722 FP_formats from,
2723 FP_formats to)
8bae0a0c 2724{
76ef4165
FL		 2725 sim_fpu wop;
2726 sim_fpu_round round;
2727 unsigned32 result32;
2728 unsigned64 result64;
8bae0a0c
JSC		 2729
2730#ifdef DEBUG
53b9417e 2731 printf("DBG: Convert: mode %s : op 0x%s : from %s : to %s : (PC = 0x%s)\n",RMMODE(rm),pr_addr(op),DOFMT(from),DOFMT(to),pr_addr(IPC));
8bae0a0c
JSC		 2732#endif /* DEBUG */
2733
76ef4165 2734 switch (rm)
8bae0a0c 2735 {
76ef4165
FL		 2736 case FP_RM_NEAREST:
2737 /* Round result to nearest representable value. When two
2738 representable values are equally near, round to the value
2739 that has a least significant bit of zero (i.e. is even). */
2740 round = sim_fpu_round_near;
2741 break;
2742 case FP_RM_TOZERO:
2743 /* Round result to the value closest to, and not greater in
2744 magnitude than, the result. */
2745 round = sim_fpu_round_zero;
2746 break;
2747 case FP_RM_TOPINF:
2748 /* Round result to the value closest to, and not less than,
2749 the result. */
2750 round = sim_fpu_round_up;
2751 break;
2752
2753 case FP_RM_TOMINF:
2754 /* Round result to the value closest to, and not greater than,
2755 the result. */
2756 round = sim_fpu_round_down;
2757 break;
2758 default:
2759 round = 0;
2760 fprintf (stderr, "Bad switch\n");
2761 abort ();
8bae0a0c 2762 }
76ef4165
FL		 2763
2764 /* Convert the input to sim_fpu internal format */
2765 switch (from)
8bae0a0c 2766 {
76ef4165
FL		 2767 case fmt_double:
2768 sim_fpu_64to (&wop, op);
2769 break;
2770 case fmt_single:
2771 sim_fpu_32to (&wop, op);
2772 break;
2773 case fmt_word:
2774 sim_fpu_i32to (&wop, op, round);
2775 break;
2776 case fmt_long:
2777 sim_fpu_i64to (&wop, op, round);
2778 break;
2779 default:
2780 fprintf (stderr, "Bad switch\n");
2781 abort ();
8bae0a0c 2782 }
8bae0a0c 2783
76ef4165
FL		 2784 /* Convert sim_fpu format into the output */
2785 /* The value WOP is converted to the destination format, rounding
2786 using mode RM. When the destination is a fixed-point format, then
2787 a source value of Infinity, NaN or one which would round to an
2788 integer outside the fixed point range then an IEEE Invalid
2789 Operation condition is raised. */
2790 switch (to)
2791 {
2792 case fmt_single:
2793 sim_fpu_round_32 (&wop, round, 0);
2794 sim_fpu_to32 (&result32, &wop);
2795 result64 = result32;
2796 break;
2797 case fmt_double:
2798 sim_fpu_round_64 (&wop, round, 0);
2799 sim_fpu_to64 (&result64, &wop);
2800 break;
2801 case fmt_word:
2802 sim_fpu_to32i (&result32, &wop, round);
2803 result64 = result32;
2804 break;
2805 case fmt_long:
2806 sim_fpu_to64i (&result64, &wop, round);
2807 break;
2808 default:
2809 result64 = 0;
2810 fprintf (stderr, "Bad switch\n");
2811 abort ();
8bae0a0c 2812 }
76ef4165 2813
8bae0a0c 2814#ifdef DEBUG
76ef4165 2815 printf("DBG: Convert: returning 0x%s (to format = %s)\n",pr_addr(result64),DOFMT(to));
8bae0a0c
JSC		 2816#endif /* DEBUG */
2817
76ef4165 2818 return(result64);
8bae0a0c 2819}
8bae0a0c 2820
76ef4165 2821
8bae0a0c
JSC		 2822/*-- co-processor support routines ------------------------------------------*/
2823
2f2e6c5d 2824static int UNUSED
8bae0a0c
JSC		 2825CoProcPresent(coproc_number)
2826 unsigned int coproc_number;
2827{
2828 /* Return TRUE if simulator provides a model for the given co-processor number */
2829 return(0);
2830}
2831
18c64df6 2832void
01737f42
AC		 2833cop_lw (SIM_DESC sd,
2834 sim_cpu *cpu,
2835 address_word cia,
2836 int coproc_num,
2837 int coproc_reg,
2838 unsigned int memword)
8bae0a0c 2839{
192ae475
AC		 2840 switch (coproc_num)
2841 {
8bae0a0c 2842 case 1:
192ae475
AC		 2843 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
2844 {
8bae0a0c 2845#ifdef DEBUG
192ae475 2846 printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword,pr_addr(memword));
8bae0a0c 2847#endif
192ae475
AC		 2848 StoreFPR(coproc_reg,fmt_word,(uword64)memword);
2849 FPR_STATE[coproc_reg] = fmt_uninterpreted;
2850 break;
2851 }
8bae0a0c
JSC		 2852
2853 default:
f24b7b69 2854#if 0 /* this should be controlled by a configuration option */
192ae475 2855 sim_io_printf(sd,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,memword,pr_addr(cia));
f24b7b69 2856#endif
192ae475
AC		 2857 break;
2858 }
8bae0a0c
JSC		 2859
2860 return;
2861}
2862
18c64df6 2863void
01737f42
AC		 2864cop_ld (SIM_DESC sd,
2865 sim_cpu *cpu,
2866 address_word cia,
2867 int coproc_num,
2868 int coproc_reg,
2869 uword64 memword)
8bae0a0c
JSC		 2870{
2871 switch (coproc_num) {
8bae0a0c 2872 case 1:
192ae475
AC		 2873 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
2874 {
2875 StoreFPR(coproc_reg,fmt_uninterpreted,memword);
2876 break;
2877 }
8bae0a0c
JSC		 2878
2879 default:
f24b7b69 2880#if 0 /* this message should be controlled by a configuration option */
95469ceb 2881 sim_io_printf(sd,"COP_LD(%d,%d,0x%s) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(memword),pr_addr(cia));
f24b7b69 2882#endif
8bae0a0c
JSC		 2883 break;
2884 }
2885
2886 return;
2887}
2888
18c64df6 2889unsigned int
01737f42
AC		 2890cop_sw (SIM_DESC sd,
2891 sim_cpu *cpu,
2892 address_word cia,
2893 int coproc_num,
2894 int coproc_reg)
8bae0a0c
JSC		 2895{
2896 unsigned int value = 0;
da0bce9c 2897
192ae475
AC		 2898 switch (coproc_num)
2899 {
8bae0a0c 2900 case 1:
192ae475
AC		 2901 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
2902 {
2903 FP_formats hold;
2904 hold = FPR_STATE[coproc_reg];
2905 FPR_STATE[coproc_reg] = fmt_word;
2906 value = (unsigned int)ValueFPR(coproc_reg,fmt_uninterpreted);
2907 FPR_STATE[coproc_reg] = hold;
2908 break;
2909 }
8bae0a0c
JSC		 2910
2911 default:
f24b7b69 2912#if 0 /* should be controlled by configuration option */
192ae475 2913 sim_io_printf(sd,"COP_SW(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
f24b7b69 2914#endif
192ae475
AC		 2915 break;
2916 }
8bae0a0c
JSC		 2917
2918 return(value);
2919}
2920
18c64df6 2921uword64
01737f42
AC		 2922cop_sd (SIM_DESC sd,
2923 sim_cpu *cpu,
2924 address_word cia,
2925 int coproc_num,
2926 int coproc_reg)
8bae0a0c 2927{
e871dd18 2928 uword64 value = 0;
192ae475
AC		 2929 switch (coproc_num)
2930 {
8bae0a0c 2931 case 1:
192ae475
AC		 2932 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
2933 {
2934 value = ValueFPR(coproc_reg,fmt_uninterpreted);
2935 break;
2936 }
8bae0a0c
JSC		 2937
2938 default:
f24b7b69 2939#if 0 /* should be controlled by configuration option */
192ae475 2940 sim_io_printf(sd,"COP_SD(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
f24b7b69 2941#endif
192ae475
AC		 2942 break;
2943 }
8bae0a0c
JSC		 2944
2945 return(value);
2946}
2947
ea985d24 2948void
01737f42
AC		 2949decode_coproc (SIM_DESC sd,
2950 sim_cpu *cpu,
2951 address_word cia,
2952 unsigned int instruction)
8bae0a0c
JSC		 2953{
2954 int coprocnum = ((instruction >> 26) & 3);
2955
56e7c849
AC		 2956 switch (coprocnum)
2957 {
8bae0a0c
JSC		 2958 case 0: /* standard CPU control and cache registers */
2959 {
8bae0a0c
JSC		 2960 int code = ((instruction >> 21) & 0x1F);
2961 /* R4000 Users Manual (second edition) lists the following CP0
2962 instructions:
56e7c849
AC		 2963 DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000)
2964 DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000)
2965 MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000)
2966 MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000)
2967 TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001)
2968 TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010)
2969 TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110)
2970 TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000)
2971 CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
2972 ERET Exception return (VR4100 = 01000010000000000000000000011000)
2973 */
2974 if (((code == 0x00) || (code == 0x04)) && ((instruction & 0x7FF) == 0))
2975 {
2976 int rt = ((instruction >> 16) & 0x1F);
2977 int rd = ((instruction >> 11) & 0x1F);
2978
2979 switch (rd) /* NOTEs: Standard CP0 registers */
2980 {
2981 /* 0 = Index R4000 VR4100 VR4300 */
2982 /* 1 = Random R4000 VR4100 VR4300 */
2983 /* 2 = EntryLo0 R4000 VR4100 VR4300 */
2984 /* 3 = EntryLo1 R4000 VR4100 VR4300 */
2985 /* 4 = Context R4000 VR4100 VR4300 */
2986 /* 5 = PageMask R4000 VR4100 VR4300 */
2987 /* 6 = Wired R4000 VR4100 VR4300 */
2988 /* 8 = BadVAddr R4000 VR4100 VR4300 */
2989 /* 9 = Count R4000 VR4100 VR4300 */
2990 /* 10 = EntryHi R4000 VR4100 VR4300 */
2991 /* 11 = Compare R4000 VR4100 VR4300 */
2992 /* 12 = SR R4000 VR4100 VR4300 */
2993 case 12:
2994 if (code == 0x00)
2995 GPR[rt] = SR;
2996 else
2997 SR = GPR[rt];
2998 break;
2999 /* 13 = Cause R4000 VR4100 VR4300 */
05d1322f
JL		 3000 case 13:
3001 if (code == 0x00)
3002 GPR[rt] = CAUSE;
3003 else
3004 CAUSE = GPR[rt];
3005 break;
56e7c849
AC		 3006 /* 14 = EPC R4000 VR4100 VR4300 */
3007 /* 15 = PRId R4000 VR4100 VR4300 */
6eedf3f4
MA		 3008#ifdef SUBTARGET_R3900
3009 /* 16 = Debug */
3010 case 16:
3011 if (code == 0x00)
3012 GPR[rt] = Debug;
3013 else
3014 Debug = GPR[rt];
3015 break;
3016#else
56e7c849 3017 /* 16 = Config R4000 VR4100 VR4300 */
a09a30d2
AC		 3018 case 16:
3019 if (code == 0x00)
3020 GPR[rt] = C0_CONFIG;
3021 else
3022 C0_CONFIG = GPR[rt];
3023 break;
6eedf3f4
MA		 3024#endif
3025#ifdef SUBTARGET_R3900
3026 /* 17 = Debug */
3027 case 17:
3028 if (code == 0x00)
3029 GPR[rt] = DEPC;
3030 else
3031 DEPC = GPR[rt];
3032 break;
3033#else
56e7c849 3034 /* 17 = LLAddr R4000 VR4100 VR4300 */
6eedf3f4 3035#endif
56e7c849
AC		 3036 /* 18 = WatchLo R4000 VR4100 VR4300 */
3037 /* 19 = WatchHi R4000 VR4100 VR4300 */
3038 /* 20 = XContext R4000 VR4100 VR4300 */
3039 /* 26 = PErr or ECC R4000 VR4100 VR4300 */
3040 /* 27 = CacheErr R4000 VR4100 */
3041 /* 28 = TagLo R4000 VR4100 VR4300 */
3042 /* 29 = TagHi R4000 VR4100 VR4300 */
3043 /* 30 = ErrorEPC R4000 VR4100 VR4300 */
3044 GPR[rt] = 0xDEADC0DE; /* CPR[0,rd] */
3045 /* CPR[0,rd] = GPR[rt]; */
3046 default:
3047 if (code == 0x00)
18c64df6 3048 sim_io_printf(sd,"Warning: MFC0 %d,%d ignored (architecture specific)\n",rt,rd);
56e7c849 3049 else
18c64df6 3050 sim_io_printf(sd,"Warning: MTC0 %d,%d ignored (architecture specific)\n",rt,rd);
56e7c849
AC		 3051 }
3052 }
3053 else if (code == 0x10 && (instruction & 0x3f) == 0x18)
3054 {
3055 /* ERET */
3056 if (SR & status_ERL)
3057 {
3058 /* Oops, not yet available */
18c64df6 3059 sim_io_printf(sd,"Warning: ERET when SR[ERL] set not handled yet");
56e7c849
AC		 3060 PC = EPC;
3061 SR &= ~status_ERL;
3062 }
3063 else
3064 {
3065 PC = EPC;
3066 SR &= ~status_EXL;
3067 }
3068 }
6eedf3f4
MA		 3069 else if (code == 0x10 && (instruction & 0x3f) == 0x10)
3070 {
3071 /* RFE */
3072 }
3073 else if (code == 0x10 && (instruction & 0x3f) == 0x1F)
3074 {
3075 /* DERET */
3076 Debug &= ~Debug_DM;
3077 DELAYSLOT();
3078 DSPC = DEPC;
3079 }
56e7c849 3080 else
95469ceb 3081 sim_io_eprintf(sd,"Unrecognised COP0 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction,pr_addr(cia));
e871dd18 3082 /* TODO: When executing an ERET or RFE instruction we should
8bae0a0c
JSC		 3083 clear LLBIT, to ensure that any out-standing atomic
3084 read/modify/write sequence fails. */
3085 }
56e7c849
AC		 3086 break;
3087
8bae0a0c 3088 case 2: /* undefined co-processor */
95469ceb 3089 sim_io_eprintf(sd,"COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction,pr_addr(cia));
8bae0a0c 3090 break;
56e7c849 3091
8bae0a0c
JSC		 3092 case 1: /* should not occur (FPU co-processor) */
3093 case 3: /* should not occur (FPU co-processor) */
3094 SignalException(ReservedInstruction,instruction);
3095 break;
56e7c849
AC		 3096 }
3097
8bae0a0c
JSC		 3098 return;
3099}
3100
3101/*-- instruction simulation -------------------------------------------------*/
3102
16bd5d6e
AC		 3103/* When the IGEN simulator is being built, the function below is be
3104 replaced by a generated version. However, WITH_IGEN == 2 indicates
3105 that the fubction below should be compiled but under a different
3106 name (to allow backward compatibility) */
3107
3108#if (WITH_IGEN != 1)
3109#if (WITH_IGEN > 1)
dad6f1f3
AC		 3110void old_engine_run PARAMS ((SIM_DESC sd, int next_cpu_nr, int siggnal));
3111void
9ec6741b 3112old_engine_run (sd, next_cpu_nr, nr_cpus, siggnal)
dad6f1f3 3113#else
2e61a3ad 3114void
9ec6741b 3115sim_engine_run (sd, next_cpu_nr, nr_cpus, siggnal)
dad6f1f3 3116#endif
2e61a3ad
AC		 3117 SIM_DESC sd;
3118 int next_cpu_nr; /* ignore */
9ec6741b 3119 int nr_cpus; /* ignore */
2e61a3ad 3120 int siggnal; /* ignore */
8bae0a0c 3121{
01737f42 3122 sim_cpu *cpu = STATE_CPU (sd, 0); /* hardwire to cpu 0 */
50a2a691 3123#if !defined(FASTSIM)
8bae0a0c 3124 unsigned int pipeline_count = 1;
50a2a691 3125#endif
8bae0a0c
JSC		 3126
3127#ifdef DEBUG
50a2a691 3128 if (STATE_MEMORY (sd) == NULL) {
8bae0a0c
JSC		 3129 printf("DBG: simulate() entered with no memory\n");
3130 exit(1);
3131 }
3132#endif /* DEBUG */
3133
3134#if 0 /* Disabled to check that everything works OK */
3135 /* The VR4300 seems to sign-extend the PC on its first
3136 access. However, this may just be because it is currently
3137 configured in 32bit mode. However... */
3138 PC = SIGNEXTEND(PC,32);
3139#endif
3140
3141 /* main controlling loop */
2e61a3ad 3142 while (1) {
7ce8b917
AC		 3143 /* vaddr is slowly being replaced with cia - current instruction
3144 address */
3145 address_word cia = (uword64)PC;
3146 address_word vaddr = cia;
dad6f1f3 3147 address_word paddr;
8bae0a0c 3148 int cca;
53b9417e 3149 unsigned int instruction; /* uword64? what's this used for? FIXME! */
8bae0a0c
JSC		 3150
3151#ifdef DEBUG
3152 {
3153 printf("DBG: state = 0x%08X :",state);
8bae0a0c
JSC		 3154 if (state & simHALTEX) printf(" simHALTEX");
3155 if (state & simHALTIN) printf(" simHALTIN");
53b9417e 3156 printf("\n");
8bae0a0c
JSC		 3157 }
3158#endif /* DEBUG */
3159
0c2c5f61 3160 DSSTATE = (STATE & simDELAYSLOT);
8bae0a0c
JSC		 3161#ifdef DEBUG
3162 if (dsstate)
18c64df6 3163 sim_io_printf(sd,"DBG: DSPC = 0x%s\n",pr_addr(DSPC));
8bae0a0c
JSC		 3164#endif /* DEBUG */
3165
7ce8b917
AC		 3166 /* Fetch the next instruction from the simulator memory: */
3167 if (AddressTranslation(cia,isINSTRUCTION,isLOAD,&paddr,&cca,isTARGET,isREAL)) {
6429b296
JW		 3168 if ((vaddr & 1) == 0) {
3169 /* Copy the action of the LW instruction */
3170 unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0);
3171 unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0);
3172 uword64 value;
3173 unsigned int byte;
3174 paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2)));
53b9417e 3175 LoadMemory(&value,NULL,cca,AccessLength_WORD,paddr,vaddr,isINSTRUCTION,isREAL);
6429b296
JW		 3176 byte = ((vaddr & LOADDRMASK) ^ (bigend << 2));
3177 instruction = ((value >> (8 * byte)) & 0xFFFFFFFF);
3178 } else {
3179 /* Copy the action of the LH instruction */
3180 unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 1) : 0);
3181 unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 1) : 0);
3182 uword64 value;
3183 unsigned int byte;
3184 paddr = (((paddr & ~ (uword64) 1) & ~LOADDRMASK)
3185 | (((paddr & ~ (uword64) 1) & LOADDRMASK) ^ (reverse << 1)));
53b9417e 3186 LoadMemory(&value,NULL,cca, AccessLength_HALFWORD,
6429b296
JW		 3187 paddr & ~ (uword64) 1,
3188 vaddr, isINSTRUCTION, isREAL);
3189 byte = (((vaddr &~ (uword64) 1) & LOADDRMASK) ^ (bigend << 1));
3190 instruction = ((value >> (8 * byte)) & 0xFFFF);
3191 }
8bae0a0c 3192 } else {
53b9417e 3193 fprintf(stderr,"Cannot translate address for PC = 0x%s failed\n",pr_addr(PC));
8bae0a0c
JSC		 3194 exit(1);
3195 }
3196
3197#ifdef DEBUG
18c64df6 3198 sim_io_printf(sd,"DBG: fetched 0x%08X from PC = 0x%s\n",instruction,pr_addr(PC));
8bae0a0c
JSC		 3199#endif /* DEBUG */
3200
8bae0a0c
JSC		 3201 /* This is required by exception processing, to ensure that we can
3202 cope with exceptions in the delay slots of branches that may
3203 already have changed the PC. */
6429b296
JW		 3204 if ((vaddr & 1) == 0)
3205 PC += 4; /* increment ready for the next fetch */
3206 else
3207 PC += 2;
8bae0a0c
JSC		 3208 /* NOTE: If we perform a delay slot change to the PC, this
3209 increment is not requuired. However, it would make the
3210 simulator more complicated to try and avoid this small hit. */
3211
3212 /* Currently this code provides a simple model. For more
3213 complicated models we could perform exception status checks at
3214 this point, and set the simSTOP state as required. This could
3215 also include processing any hardware interrupts raised by any
3216 I/O model attached to the simulator context.
3217
3218 Support for "asynchronous" I/O events within the simulated world
3219 could be providing by managing a counter, and calling a I/O
3220 specific handler when a particular threshold is reached. On most
3221 architectures a decrement and check for zero operation is
3222 usually quicker than an increment and compare. However, the
3223 process of managing a known value decrement to zero, is higher
3224 than the cost of using an explicit value UINT_MAX into the
3225 future. Which system is used will depend on how complicated the
3226 I/O model is, and how much it is likely to affect the simulator
3227 bandwidth.
3228
3229 If events need to be scheduled further in the future than
3230 UINT_MAX event ticks, then the I/O model should just provide its
3231 own counter, triggered from the event system. */
3232
3233 /* MIPS pipeline ticks. To allow for future support where the
3234 pipeline hit of individual instructions is known, this control
3235 loop manages a "pipeline_count" variable. It is initialised to
3236 1 (one), and will only be changed by the simulator engine when
3237 executing an instruction. If the engine does not have access to
3238 pipeline cycle count information then all instructions will be
3239 treated as using a single cycle. NOTE: A standard system is not
3240 provided by the default simulator because different MIPS
3241 architectures have different cycle counts for the same
50a2a691
AC		 3242 instructions.
3243
3244 [NOTE: pipeline_count has been replaced the event queue] */
8bae0a0c 3245
a09a30d2
AC		 3246 /* shuffle the floating point status pipeline state */
3247 ENGINE_ISSUE_PREFIX_HOOK();
8bae0a0c
JSC		 3248
3249/* NOTE: For multi-context simulation environments the "instruction"
3250 variable should be local to this routine. */
3251
3252/* Shorthand accesses for engine. Note: If we wanted to use global
3253 variables (and a single-threaded simulator engine), then we can
3254 create the actual variables with these names. */
3255
0c2c5f61 3256 if (!(STATE & simSKIPNEXT)) {
8bae0a0c 3257 /* Include the simulator engine */
284e759d 3258#include "oengine.c"
f24b7b69 3259#if ((GPRLEN == 64) && !PROCESSOR_64BIT) || ((GPRLEN == 32) && PROCESSOR_64BIT)
8bae0a0c
JSC		 3260#error "Mismatch between run-time simulator code and simulation engine"
3261#endif
18c64df6
AC		 3262#if (WITH_TARGET_WORD_BITSIZE != GPRLEN)
3263#error "Mismatch between configure WITH_TARGET_WORD_BITSIZE and gencode GPRLEN"
3264#endif
76ef4165 3265#if ((WITH_FLOATING_POINT == HARD_FLOATING_POINT) != defined (HASFPU))
18c64df6
AC		 3266#error "Mismatch between configure WITH_FLOATING_POINT and gencode HASFPU"
3267#endif
8bae0a0c
JSC		 3268
3269#if defined(WARN_LOHI)
3270 /* Decrement the HI/LO validity ticks */
3271 if (HIACCESS > 0)
3272 HIACCESS--;
3273 if (LOACCESS > 0)
3274 LOACCESS--;
0425cfb3 3275 /* start-sanitize-r5900 */
53b9417e
DE		 3276 if (HI1ACCESS > 0)
3277 HI1ACCESS--;
3278 if (LO1ACCESS > 0)
3279 LO1ACCESS--;
0425cfb3 3280 /* end-sanitize-r5900 */
8bae0a0c
JSC		 3281#endif /* WARN_LOHI */
3282
8bae0a0c
JSC		 3283 /* For certain MIPS architectures, GPR[0] is hardwired to zero. We
3284 should check for it being changed. It is better doing it here,
3285 than within the simulator, since it will help keep the simulator
3286 small. */
3287 if (ZERO != 0) {
05d1322f 3288#if defined(WARN_ZERO)
95469ceb 3289 sim_io_eprintf(sd,"The ZERO register has been updated with 0x%s (PC = 0x%s) (reset back to zero)\n",pr_addr(ZERO),pr_addr(cia));
05d1322f 3290#endif /* WARN_ZERO */
8bae0a0c
JSC		 3291 ZERO = 0; /* reset back to zero before next instruction */
3292 }
8bae0a0c 3293 } else /* simSKIPNEXT check */
0c2c5f61 3294 STATE &= ~simSKIPNEXT;
8bae0a0c
JSC		 3295
3296 /* If the delay slot was active before the instruction is
3297 executed, then update the PC to its new value: */
0c2c5f61 3298 if (DSSTATE) {
8bae0a0c 3299#ifdef DEBUG
53b9417e 3300 printf("DBG: dsstate set before instruction execution - updating PC to 0x%s\n",pr_addr(DSPC));
8bae0a0c
JSC		 3301#endif /* DEBUG */
3302 PC = DSPC;
6eedf3f4 3303 CANCELDELAYSLOT();
8bae0a0c
JSC		 3304 }
3305
2acd126a
AC		 3306 if (MIPSISA < 4)
3307 PENDING_TICK();
8bae0a0c
JSC		 3308
3309#if !defined(FASTSIM)
50a2a691
AC		 3310 if (sim_events_tickn (sd, pipeline_count))
3311 {
3312 /* cpu->cia = cia; */
3313 sim_events_process (sd);
3314 }
3315#else
2e61a3ad
AC		 3316 if (sim_events_tick (sd))
3317 {
3318 /* cpu->cia = cia; */
3319 sim_events_process (sd);
3320 }
50a2a691 3321#endif /* FASTSIM */
8bae0a0c 3322 }
8bae0a0c 3323}
16bd5d6e
AC		 3324#endif
3325
8bae0a0c 3326
53b9417e
DE		 3327/* This code copied from gdb's utils.c. Would like to share this code,
3328 but don't know of a common place where both could get to it. */
3329
3330/* Temporary storage using circular buffer */
3331#define NUMCELLS 16
3332#define CELLSIZE 32
3333static char*
3334get_cell()
3335{
3336 static char buf[NUMCELLS][CELLSIZE];
3337 static int cell=0;
3338 if (++cell>=NUMCELLS) cell=0;
3339 return buf[cell];
3340}
3341
3342/* Print routines to handle variable size regs, etc */
3343
3344/* Eliminate warning from compiler on 32-bit systems */
3345static int thirty_two = 32;
3346
3347char*
3348pr_addr(addr)
3349 SIM_ADDR addr;
3350{
3351 char *paddr_str=get_cell();
3352 switch (sizeof(addr))
3353 {
3354 case 8:
50a2a691 3355 sprintf(paddr_str,"%08lx%08lx",
53b9417e
DE		 3356 (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff));
3357 break;
3358 case 4:
50a2a691 3359 sprintf(paddr_str,"%08lx",(unsigned long)addr);
53b9417e
DE		 3360 break;
3361 case 2:
3362 sprintf(paddr_str,"%04x",(unsigned short)(addr&0xffff));
3363 break;
3364 default:
3365 sprintf(paddr_str,"%x",addr);
3366 }
3367 return paddr_str;
3368}
3369
87e43259
AC		 3370char*
3371pr_uword64(addr)
3372 uword64 addr;
3373{
3374 char *paddr_str=get_cell();
50a2a691 3375 sprintf(paddr_str,"%08lx%08lx",
87e43259
AC		 3376 (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff));
3377 return paddr_str;
3378}
3379
3380
2acd126a
AC		 3381void
3382pending_tick (SIM_DESC sd,
3383 sim_cpu *cpu,
3384 address_word cia)
3385{
3386 if (PENDING_TRACE)
3387 sim_io_printf (sd, "PENDING_DRAIN - pending_in = %d, pending_out = %d, pending_total = %d\n", PENDING_IN, PENDING_OUT, PENDING_TOTAL);
3388 if (PENDING_OUT != PENDING_IN)
3389 {
3390 int loop;
3391 int index = PENDING_OUT;
3392 int total = PENDING_TOTAL;
3393 if (PENDING_TOTAL == 0)
3394 sim_engine_abort (SD, CPU, cia, "PENDING_DRAIN - Mis-match on pending update pointers\n");
3395 for (loop = 0; (loop < total); loop++)
3396 {
3397 if (PENDING_SLOT_DEST[index] != NULL)
3398 {
3399 PENDING_SLOT_DELAY[index] -= 1;
3400 if (PENDING_SLOT_DELAY[index] == 0)
3401 {
3402 if (PENDING_SLOT_BIT[index] >= 0)
3403 switch (PENDING_SLOT_SIZE[index])
3404 {
3405 case 32:
3406 if (PENDING_SLOT_VALUE[index])
3407 *(unsigned32*)PENDING_SLOT_DEST[index] |=
3408 BIT32 (PENDING_SLOT_BIT[index]);
3409 else
3410 *(unsigned32*)PENDING_SLOT_DEST[index] &=
3411 BIT32 (PENDING_SLOT_BIT[index]);
3412 break;
3413 case 64:
3414 if (PENDING_SLOT_VALUE[index])
3415 *(unsigned64*)PENDING_SLOT_DEST[index] |=
3416 BIT64 (PENDING_SLOT_BIT[index]);
3417 else
3418 *(unsigned64*)PENDING_SLOT_DEST[index] &=
3419 BIT64 (PENDING_SLOT_BIT[index]);
3420 break;
3421 break;
3422 }
3423 else
3424 switch (PENDING_SLOT_SIZE[index])
3425 {
3426 case 32:
3427 *(unsigned32*)PENDING_SLOT_DEST[index] =
3428 PENDING_SLOT_VALUE[index];
3429 break;
3430 case 64:
3431 *(unsigned64*)PENDING_SLOT_DEST[index] =
3432 PENDING_SLOT_VALUE[index];
3433 break;
3434 }
3435 }
3436 if (PENDING_OUT == index)
3437 {
3438 PENDING_SLOT_DEST[index] = NULL;
3439 PENDING_OUT = (PENDING_OUT + 1) % PSLOTS;
3440 PENDING_TOTAL--;
3441 }
3442 }
3443 }
3444 index = (index + 1) % PSLOTS;
3445 }
3446}
3447
8bae0a0c
JSC		 3448/*---------------------------------------------------------------------------*/
3449/*> EOF interp.c <*/
GDB Binutils - Deliverables
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