Commit | Line | Data |
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8bae0a0c JSC |
1 | /*> interp.c <*/ |
2 | /* Simulator for the MIPS architecture. | |
3 | ||
4 | This file is part of the MIPS sim | |
5 | ||
6 | THIS SOFTWARE IS NOT COPYRIGHTED | |
7 | ||
8 | Cygnus offers the following for use in the public domain. Cygnus | |
9 | makes no warranty with regard to the software or it's performance | |
10 | and the user accepts the software "AS IS" with all faults. | |
11 | ||
12 | CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO | |
13 | THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
14 | MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. | |
15 | ||
16 | $Revision$ | |
17 | $Author$ | |
e3d12c65 | 18 | $Date$ |
8bae0a0c JSC |
19 | |
20 | NOTEs: | |
21 | ||
8bae0a0c JSC |
22 | The IDT monitor (found on the VR4300 board), seems to lie about |
23 | register contents. It seems to treat the registers as sign-extended | |
24 | 32-bit values. This cause *REAL* problems when single-stepping 64-bit | |
25 | code on the hardware. | |
26 | ||
27 | */ | |
28 | ||
e2f8ffb7 AC |
29 | /* The TRACE manifests enable the provision of extra features. If they |
30 | are not defined then a simpler (quicker) simulator is constructed | |
31 | without the required run-time checks, etc. */ | |
8bae0a0c JSC |
32 | #if 1 /* 0 to allow user build selection, 1 to force inclusion */ |
33 | #define TRACE (1) | |
8bae0a0c JSC |
34 | #endif |
35 | ||
2e61a3ad AC |
36 | #include "bfd.h" |
37 | #include "sim-main.h" | |
38 | #include "sim-utils.h" | |
39 | #include "sim-options.h" | |
50a2a691 | 40 | #include "sim-assert.h" |
2e61a3ad | 41 | |
4fa134be ILT |
42 | #include "config.h" |
43 | ||
8bae0a0c JSC |
44 | #include <stdio.h> |
45 | #include <stdarg.h> | |
46 | #include <ansidecl.h> | |
8bae0a0c JSC |
47 | #include <ctype.h> |
48 | #include <limits.h> | |
49 | #include <math.h> | |
4fa134be ILT |
50 | #ifdef HAVE_STDLIB_H |
51 | #include <stdlib.h> | |
52 | #endif | |
53 | #ifdef HAVE_STRING_H | |
54 | #include <string.h> | |
55 | #else | |
56 | #ifdef HAVE_STRINGS_H | |
57 | #include <strings.h> | |
58 | #endif | |
59 | #endif | |
8bae0a0c JSC |
60 | |
61 | #include "getopt.h" | |
62 | #include "libiberty.h" | |
9d52bcb7 | 63 | #include "bfd.h" |
8bae0a0c | 64 | #include "callback.h" /* GDB simulator callback interface */ |
e3d12c65 | 65 | #include "remote-sim.h" /* GDB simulator interface */ |
8bae0a0c | 66 | |
f24b7b69 JSC |
67 | #include "sysdep.h" |
68 | ||
d44859a2 RU |
69 | /* start-sanitize-sky */ |
70 | #ifdef TARGET_SKY | |
71 | #include "sky-vu.h" | |
72 | #endif | |
73 | /* end-sanitize-sky */ | |
74 | ||
53b9417e DE |
75 | #ifndef PARAMS |
76 | #define PARAMS(x) | |
77 | #endif | |
78 | ||
79 | char* pr_addr PARAMS ((SIM_ADDR addr)); | |
87e43259 | 80 | char* pr_uword64 PARAMS ((uword64 addr)); |
53b9417e | 81 | |
f24b7b69 | 82 | |
8bae0a0c | 83 | /* Get the simulator engine description, without including the code: */ |
192ae475 AC |
84 | #if (WITH_IGEN) |
85 | #define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3) | |
86 | #else | |
8bae0a0c | 87 | #define SIM_MANIFESTS |
284e759d | 88 | #include "oengine.c" |
8bae0a0c | 89 | #undef SIM_MANIFESTS |
192ae475 | 90 | #endif |
8bae0a0c | 91 | |
01737f42 AC |
92 | /* Within interp.c we refer to the sim_state and sim_cpu directly. */ |
93 | #define SD sd | |
94 | #define CPU cpu | |
95 | ||
f7481d45 | 96 | |
8bae0a0c JSC |
97 | /* The following reserved instruction value is used when a simulator |
98 | trap is required. NOTE: Care must be taken, since this value may be | |
99 | used in later revisions of the MIPS ISA. */ | |
53b9417e DE |
100 | #define RSVD_INSTRUCTION (0x00000005) |
101 | #define RSVD_INSTRUCTION_MASK (0xFC00003F) | |
102 | ||
103 | #define RSVD_INSTRUCTION_ARG_SHIFT 6 | |
104 | #define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF | |
105 | ||
8bae0a0c | 106 | |
6eedf3f4 MA |
107 | /* Bits in the Debug register */ |
108 | #define Debug_DBD 0x80000000 /* Debug Branch Delay */ | |
109 | #define Debug_DM 0x40000000 /* Debug Mode */ | |
110 | #define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */ | |
111 | ||
112 | ||
113 | ||
8bae0a0c | 114 | |
8bae0a0c | 115 | |
e3d12c65 DE |
116 | /*---------------------------------------------------------------------------*/ |
117 | /*-- GDB simulator interface ------------------------------------------------*/ | |
118 | /*---------------------------------------------------------------------------*/ | |
119 | ||
0c2c5f61 | 120 | static void ColdReset PARAMS((SIM_DESC sd)); |
e3d12c65 DE |
121 | |
122 | /*---------------------------------------------------------------------------*/ | |
123 | ||
8bae0a0c | 124 | |
8bae0a0c | 125 | |
8bae0a0c | 126 | #define DELAYSLOT() {\ |
0c2c5f61 | 127 | if (STATE & simDELAYSLOT)\ |
18c64df6 | 128 | sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\ |
0c2c5f61 | 129 | STATE |= simDELAYSLOT;\ |
8bae0a0c JSC |
130 | } |
131 | ||
aaff8437 ILT |
132 | #define JALDELAYSLOT() {\ |
133 | DELAYSLOT ();\ | |
0c2c5f61 | 134 | STATE |= simJALDELAYSLOT;\ |
aaff8437 ILT |
135 | } |
136 | ||
8bae0a0c | 137 | #define NULLIFY() {\ |
0c2c5f61 AC |
138 | STATE &= ~simDELAYSLOT;\ |
139 | STATE |= simSKIPNEXT;\ | |
8bae0a0c JSC |
140 | } |
141 | ||
6eedf3f4 | 142 | #define CANCELDELAYSLOT() {\ |
0c2c5f61 AC |
143 | DSSTATE = 0;\ |
144 | STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\ | |
6eedf3f4 MA |
145 | } |
146 | ||
0c2c5f61 AC |
147 | #define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0) |
148 | #define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0) | |
aaff8437 | 149 | |
a9f7253f JSC |
150 | #define K0BASE (0x80000000) |
151 | #define K0SIZE (0x20000000) | |
152 | #define K1BASE (0xA0000000) | |
153 | #define K1SIZE (0x20000000) | |
525d929e AC |
154 | #define MONITOR_BASE (0xBFC00000) |
155 | #define MONITOR_SIZE (1 << 11) | |
156 | #define MEM_SIZE (2 << 20) | |
82ea14fd AC |
157 | /* start-sanitize-sky */ |
158 | #ifdef TARGET_SKY | |
159 | #undef MEM_SIZE | |
160 | #define MEM_SIZE (16 << 20) /* 16 MB */ | |
161 | #endif | |
162 | /* end-sanitize-sky */ | |
a9f7253f | 163 | |
8bae0a0c | 164 | #if defined(TRACE) |
4fa134be | 165 | static char *tracefile = "trace.din"; /* default filename for trace log */ |
030843d7 | 166 | FILE *tracefh = NULL; |
18c64df6 | 167 | static void open_trace PARAMS((SIM_DESC sd)); |
8bae0a0c JSC |
168 | #endif /* TRACE */ |
169 | ||
7c5d88c1 DE |
170 | static DECLARE_OPTION_HANDLER (mips_option_handler); |
171 | ||
22de994d AC |
172 | #define OPTION_DINERO_TRACE 200 |
173 | #define OPTION_DINERO_FILE 201 | |
174 | ||
50a2a691 | 175 | static SIM_RC |
7c5d88c1 | 176 | mips_option_handler (sd, cpu, opt, arg, is_command) |
50a2a691 | 177 | SIM_DESC sd; |
7c5d88c1 | 178 | sim_cpu *cpu; |
50a2a691 AC |
179 | int opt; |
180 | char *arg; | |
7c5d88c1 | 181 | int is_command; |
2e61a3ad | 182 | { |
01737f42 | 183 | int cpu_nr; |
50a2a691 AC |
184 | switch (opt) |
185 | { | |
22de994d | 186 | case OPTION_DINERO_TRACE: /* ??? */ |
50a2a691 AC |
187 | #if defined(TRACE) |
188 | /* Eventually the simTRACE flag could be treated as a toggle, to | |
189 | allow external control of the program points being traced | |
190 | (i.e. only from main onwards, excluding the run-time setup, | |
191 | etc.). */ | |
82ea14fd | 192 | for (cpu_nr = 0; cpu_nr < MAX_NR_PROCESSORS; cpu_nr++) |
50a2a691 | 193 | { |
01737f42 AC |
194 | sim_cpu *cpu = STATE_CPU (sd, cpu_nr); |
195 | if (arg == NULL) | |
196 | STATE |= simTRACE; | |
197 | else if (strcmp (arg, "yes") == 0) | |
198 | STATE |= simTRACE; | |
199 | else if (strcmp (arg, "no") == 0) | |
200 | STATE &= ~simTRACE; | |
201 | else if (strcmp (arg, "on") == 0) | |
202 | STATE |= simTRACE; | |
203 | else if (strcmp (arg, "off") == 0) | |
204 | STATE &= ~simTRACE; | |
205 | else | |
206 | { | |
207 | fprintf (stderr, "Unreconized dinero-trace option `%s'\n", arg); | |
208 | return SIM_RC_FAIL; | |
209 | } | |
50a2a691 AC |
210 | } |
211 | return SIM_RC_OK; | |
212 | #else /* !TRACE */ | |
213 | fprintf(stderr,"\ | |
22de994d | 214 | Simulator constructed without dinero tracing support (for performance).\n\ |
50a2a691 AC |
215 | Re-compile simulator with \"-DTRACE\" to enable this option.\n"); |
216 | return SIM_RC_FAIL; | |
217 | #endif /* !TRACE */ | |
218 | ||
22de994d | 219 | case OPTION_DINERO_FILE: |
50a2a691 AC |
220 | #if defined(TRACE) |
221 | if (optarg != NULL) { | |
222 | char *tmp; | |
223 | tmp = (char *)malloc(strlen(optarg) + 1); | |
224 | if (tmp == NULL) | |
225 | { | |
18c64df6 | 226 | sim_io_printf(sd,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg); |
50a2a691 AC |
227 | return SIM_RC_FAIL; |
228 | } | |
229 | else { | |
230 | strcpy(tmp,optarg); | |
231 | tracefile = tmp; | |
18c64df6 | 232 | sim_io_printf(sd,"Placing trace information into file \"%s\"\n",tracefile); |
50a2a691 AC |
233 | } |
234 | } | |
235 | #endif /* TRACE */ | |
236 | return SIM_RC_OK; | |
237 | ||
50a2a691 AC |
238 | } |
239 | ||
240 | return SIM_RC_OK; | |
2e61a3ad | 241 | } |
50a2a691 AC |
242 | |
243 | static const OPTION mips_options[] = | |
2e61a3ad | 244 | { |
22de994d AC |
245 | { {"dinero-trace", optional_argument, NULL, OPTION_DINERO_TRACE}, |
246 | '\0', "on|off", "Enable dinero tracing", | |
50a2a691 | 247 | mips_option_handler }, |
22de994d AC |
248 | { {"dinero-file", required_argument, NULL, OPTION_DINERO_FILE}, |
249 | '\0', "FILE", "Write dinero trace to FILE", | |
50a2a691 | 250 | mips_option_handler }, |
50a2a691 AC |
251 | { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL } |
252 | }; | |
253 | ||
254 | ||
56e7c849 AC |
255 | int interrupt_pending; |
256 | ||
50a2a691 AC |
257 | static void |
258 | interrupt_event (SIM_DESC sd, void *data) | |
2e61a3ad | 259 | { |
01737f42 | 260 | sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */ |
56e7c849 AC |
261 | if (SR & status_IE) |
262 | { | |
263 | interrupt_pending = 0; | |
18c64df6 | 264 | SignalExceptionInterrupt (); |
56e7c849 AC |
265 | } |
266 | else if (!interrupt_pending) | |
267 | sim_events_schedule (sd, 1, interrupt_event, data); | |
2e61a3ad | 268 | } |
f7481d45 | 269 | |
f7481d45 | 270 | |
2c88fae9 IC |
271 | /*---------------------------------------------------------------------------*/ |
272 | /*-- Device registration hook -----------------------------------------------*/ | |
273 | /*---------------------------------------------------------------------------*/ | |
97908603 | 274 | static void device_init(SIM_DESC sd) { |
2c88fae9 IC |
275 | #ifdef DEVICE_INIT |
276 | extern void register_devices(SIM_DESC); | |
277 | register_devices(sd); | |
278 | #endif | |
279 | } | |
50a2a691 | 280 | |
97908603 | 281 | /* start-sanitize-sky */ |
7aa6042f | 282 | #ifdef TARGET_SKY |
97908603 | 283 | static struct { |
a859684b RU |
284 | short i[NUM_VU_INTEGER_REGS]; |
285 | int f[NUM_VU_REGS - NUM_VU_INTEGER_REGS]; | |
97908603 | 286 | } vu_regs[2]; |
7aa6042f | 287 | #endif |
97908603 RU |
288 | /* end-sanitize-sky */ |
289 | ||
8bae0a0c JSC |
290 | /*---------------------------------------------------------------------------*/ |
291 | /*-- GDB simulator interface ------------------------------------------------*/ | |
292 | /*---------------------------------------------------------------------------*/ | |
293 | ||
53b9417e | 294 | SIM_DESC |
247fccde | 295 | sim_open (kind, cb, abfd, argv) |
87e43259 | 296 | SIM_OPEN_KIND kind; |
50a2a691 | 297 | host_callback *cb; |
247fccde | 298 | struct _bfd *abfd; |
53b9417e | 299 | char **argv; |
8bae0a0c | 300 | { |
18c64df6 | 301 | SIM_DESC sd = sim_state_alloc (kind, cb); |
01737f42 | 302 | sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */ |
2e61a3ad | 303 | |
525d929e AC |
304 | SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); |
305 | ||
50a2a691 AC |
306 | /* FIXME: watchpoints code shouldn't need this */ |
307 | STATE_WATCHPOINTS (sd)->pc = &(PC); | |
308 | STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC); | |
309 | STATE_WATCHPOINTS (sd)->interrupt_handler = interrupt_event; | |
310 | ||
0c2c5f61 | 311 | STATE = 0; |
50a2a691 | 312 | |
2e61a3ad AC |
313 | if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK) |
314 | return 0; | |
7c5d88c1 | 315 | sim_add_option_table (sd, NULL, mips_options); |
2e61a3ad | 316 | |
63be8feb AC |
317 | /* Allocate core managed memory */ |
318 | ||
319 | /* the monitor */ | |
320 | sim_do_commandf (sd, "memory region 0x%lx,0x%lx", MONITOR_BASE, MONITOR_SIZE); | |
321 | /* For compatibility with the old code - under this (at level one) | |
322 | are the kernel spaces K0 & K1. Both of these map to a single | |
323 | smaller sub region */ | |
a48e8c8d | 324 | sim_do_command(sd," memory region 0x7fff8000,0x8000") ; /* MTZ- 32 k stack */ |
fd909089 FCE |
325 | /* start-sanitize-sky */ |
326 | #ifndef TARGET_SKY | |
327 | /* end-sanitize-sky */ | |
63be8feb AC |
328 | sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x", |
329 | K1BASE, K0SIZE, | |
330 | MEM_SIZE, /* actual size */ | |
331 | K0BASE); | |
fd909089 FCE |
332 | /* start-sanitize-sky */ |
333 | #else | |
334 | sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x,0x%0x", | |
335 | K1BASE, K0SIZE, | |
336 | MEM_SIZE, /* actual size */ | |
337 | K0BASE, | |
338 | 0); /* add alias at 0x0000 */ | |
9ce23bf9 | 339 | #endif |
fd909089 | 340 | /* end-sanitize-sky */ |
63be8feb | 341 | |
2c88fae9 IC |
342 | device_init(sd); |
343 | ||
2e61a3ad AC |
344 | /* getopt will print the error message so we just have to exit if this fails. |
345 | FIXME: Hmmm... in the case of gdb we need getopt to call | |
346 | print_filtered. */ | |
347 | if (sim_parse_args (sd, argv) != SIM_RC_OK) | |
348 | { | |
349 | /* Uninstall the modules to avoid memory leaks, | |
350 | file descriptor leaks, etc. */ | |
351 | sim_module_uninstall (sd); | |
352 | return 0; | |
353 | } | |
2e61a3ad | 354 | |
fafce69a AC |
355 | /* check for/establish the a reference program image */ |
356 | if (sim_analyze_program (sd, | |
357 | (STATE_PROG_ARGV (sd) != NULL | |
358 | ? *STATE_PROG_ARGV (sd) | |
359 | : NULL), | |
360 | abfd) != SIM_RC_OK) | |
361 | { | |
362 | sim_module_uninstall (sd); | |
363 | return 0; | |
364 | } | |
365 | ||
247fccde AC |
366 | /* Configure/verify the target byte order and other runtime |
367 | configuration options */ | |
fafce69a | 368 | if (sim_config (sd) != SIM_RC_OK) |
247fccde AC |
369 | { |
370 | sim_module_uninstall (sd); | |
371 | return 0; | |
372 | } | |
373 | ||
2e61a3ad AC |
374 | if (sim_post_argv_init (sd) != SIM_RC_OK) |
375 | { | |
376 | /* Uninstall the modules to avoid memory leaks, | |
377 | file descriptor leaks, etc. */ | |
378 | sim_module_uninstall (sd); | |
379 | return 0; | |
380 | } | |
381 | ||
50a2a691 AC |
382 | /* verify assumptions the simulator made about the host type system. |
383 | This macro does not return if there is a problem */ | |
7ce8b917 AC |
384 | SIM_ASSERT (sizeof(int) == (4 * sizeof(char))); |
385 | SIM_ASSERT (sizeof(word64) == (8 * sizeof(char))); | |
8bae0a0c | 386 | |
8bae0a0c JSC |
387 | /* This is NASTY, in that we are assuming the size of specific |
388 | registers: */ | |
389 | { | |
390 | int rn; | |
a97f304b AC |
391 | for (rn = 0; (rn < (LAST_EMBED_REGNUM + 1)); rn++) |
392 | { | |
393 | if (rn < 32) | |
394 | cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE; | |
395 | else if ((rn >= FGRIDX) && (rn < (FGRIDX + NR_FGR))) | |
396 | cpu->register_widths[rn] = WITH_TARGET_FLOATING_POINT_BITSIZE; | |
397 | else if ((rn >= 33) && (rn <= 37)) | |
398 | cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE; | |
a48e8c8d AC |
399 | else if ((rn == SRIDX) |
400 | || (rn == FCR0IDX) | |
401 | || (rn == FCR31IDX) | |
402 | || ((rn >= 72) && (rn <= 89))) | |
a97f304b AC |
403 | cpu->register_widths[rn] = 32; |
404 | else | |
405 | cpu->register_widths[rn] = 0; | |
406 | } | |
18c64df6 AC |
407 | /* start-sanitize-r5900 */ |
408 | ||
409 | /* set the 5900 "upper" registers to 64 bits */ | |
410 | for( rn = LAST_EMBED_REGNUM+1; rn < NUM_REGS; rn++) | |
0c2c5f61 | 411 | cpu->register_widths[rn] = 64; |
18c64df6 | 412 | /* end-sanitize-r5900 */ |
97908603 RU |
413 | |
414 | /* start-sanitize-sky */ | |
415 | #ifdef TARGET_SKY | |
416 | /* Now the VU registers */ | |
a859684b | 417 | for( rn = 0; rn < NUM_VU_INTEGER_REGS; rn++ ) { |
97908603 RU |
418 | cpu->register_widths[rn + NUM_R5900_REGS] = 16; |
419 | cpu->register_widths[rn + NUM_R5900_REGS + NUM_VU_REGS] = 16; | |
420 | ||
421 | /* Hack for now - to test gdb interface */ | |
422 | vu_regs[0].i[rn] = rn + 0x100; | |
423 | vu_regs[1].i[rn] = rn + 0x200; | |
424 | } | |
425 | ||
a859684b | 426 | for( rn = NUM_VU_INTEGER_REGS; rn < NUM_VU_REGS; rn++ ) { |
97908603 | 427 | float f; |
a859684b | 428 | int first_vec_reg = NUM_VU_INTEGER_REGS + 8; |
97908603 RU |
429 | |
430 | cpu->register_widths[rn + NUM_R5900_REGS] = 32; | |
431 | cpu->register_widths[rn + NUM_R5900_REGS + NUM_VU_REGS] = 32; | |
432 | ||
433 | /* Hack for now - to test gdb interface */ | |
a859684b RU |
434 | if( rn < first_vec_reg ) { |
435 | f = rn - NUM_VU_INTEGER_REGS + 100.0; | |
436 | vu_regs[0].f[rn-NUM_VU_INTEGER_REGS] = *((unsigned *) &f); | |
437 | f = rn - NUM_VU_INTEGER_REGS + 200.0; | |
438 | vu_regs[1].f[rn-NUM_VU_INTEGER_REGS] = *((unsigned *) &f); | |
97908603 RU |
439 | } |
440 | else { | |
a859684b RU |
441 | f = (rn - first_vec_reg)/4 + (rn - first_vec_reg)%4 + 1000.0; |
442 | vu_regs[0].f[rn-NUM_VU_INTEGER_REGS] = *((unsigned *) &f); | |
443 | f = (rn - first_vec_reg)/4 + (rn - first_vec_reg)%4 + 2000.0; | |
444 | vu_regs[1].f[rn-NUM_VU_INTEGER_REGS] = *((unsigned *) &f); | |
97908603 RU |
445 | } |
446 | } | |
447 | #endif | |
448 | /* end-sanitize-sky */ | |
8bae0a0c JSC |
449 | } |
450 | ||
8bae0a0c | 451 | #if defined(TRACE) |
0c2c5f61 | 452 | if (STATE & simTRACE) |
18c64df6 | 453 | open_trace(sd); |
8bae0a0c JSC |
454 | #endif /* TRACE */ |
455 | ||
fafce69a AC |
456 | /* Write the monitor trap address handlers into the monitor (eeprom) |
457 | address space. This can only be done once the target endianness | |
458 | has been determined. */ | |
459 | { | |
460 | unsigned loop; | |
461 | /* Entry into the IDT monitor is via fixed address vectors, and | |
462 | not using machine instructions. To avoid clashing with use of | |
463 | the MIPS TRAP system, we place our own (simulator specific) | |
464 | "undefined" instructions into the relevant vector slots. */ | |
525d929e AC |
465 | for (loop = 0; (loop < MONITOR_SIZE); loop += 4) |
466 | { | |
467 | address_word vaddr = (MONITOR_BASE + loop); | |
468 | unsigned32 insn = (RSVD_INSTRUCTION | (((loop >> 2) & RSVD_INSTRUCTION_ARG_MASK) << RSVD_INSTRUCTION_ARG_SHIFT)); | |
469 | H2T (insn); | |
470 | sim_write (sd, vaddr, (char *)&insn, sizeof (insn)); | |
471 | } | |
fafce69a AC |
472 | /* The PMON monitor uses the same address space, but rather than |
473 | branching into it the address of a routine is loaded. We can | |
474 | cheat for the moment, and direct the PMON routine to IDT style | |
475 | instructions within the monitor space. This relies on the IDT | |
476 | monitor not using the locations from 0xBFC00500 onwards as its | |
477 | entry points.*/ | |
478 | for (loop = 0; (loop < 24); loop++) | |
479 | { | |
525d929e AC |
480 | address_word vaddr = (MONITOR_BASE + 0x500 + (loop * 4)); |
481 | unsigned32 value = ((0x500 - 8) / 8); /* default UNDEFINED reason code */ | |
fafce69a AC |
482 | switch (loop) |
483 | { | |
484 | case 0: /* read */ | |
485 | value = 7; | |
486 | break; | |
fafce69a AC |
487 | case 1: /* write */ |
488 | value = 8; | |
489 | break; | |
fafce69a AC |
490 | case 2: /* open */ |
491 | value = 6; | |
492 | break; | |
fafce69a AC |
493 | case 3: /* close */ |
494 | value = 10; | |
495 | break; | |
fafce69a AC |
496 | case 5: /* printf */ |
497 | value = ((0x500 - 16) / 8); /* not an IDT reason code */ | |
498 | break; | |
fafce69a AC |
499 | case 8: /* cliexit */ |
500 | value = 17; | |
501 | break; | |
fafce69a AC |
502 | case 11: /* flush_cache */ |
503 | value = 28; | |
504 | break; | |
505 | } | |
525d929e AC |
506 | /* FIXME - should monitor_base be SIM_ADDR?? */ |
507 | value = ((unsigned int)MONITOR_BASE + (value * 8)); | |
508 | H2T (value); | |
509 | sim_write (sd, vaddr, (char *)&value, sizeof (value)); | |
fafce69a AC |
510 | |
511 | /* The LSI MiniRISC PMON has its vectors at 0x200, not 0x500. */ | |
512 | vaddr -= 0x300; | |
525d929e | 513 | sim_write (sd, vaddr, (char *)&value, sizeof (value)); |
fafce69a AC |
514 | } |
515 | } | |
516 | ||
2e61a3ad | 517 | return sd; |
8bae0a0c JSC |
518 | } |
519 | ||
6429b296 JW |
520 | #if defined(TRACE) |
521 | static void | |
18c64df6 AC |
522 | open_trace(sd) |
523 | SIM_DESC sd; | |
6429b296 JW |
524 | { |
525 | tracefh = fopen(tracefile,"wb+"); | |
526 | if (tracefh == NULL) | |
527 | { | |
18c64df6 | 528 | sim_io_eprintf(sd,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile); |
6429b296 JW |
529 | tracefh = stderr; |
530 | } | |
531 | } | |
532 | #endif /* TRACE */ | |
533 | ||
8bae0a0c | 534 | void |
53b9417e DE |
535 | sim_close (sd, quitting) |
536 | SIM_DESC sd; | |
8bae0a0c JSC |
537 | int quitting; |
538 | { | |
539 | #ifdef DEBUG | |
540 | printf("DBG: sim_close: entered (quitting = %d)\n",quitting); | |
541 | #endif | |
542 | ||
8bae0a0c JSC |
543 | /* "quitting" is non-zero if we cannot hang on errors */ |
544 | ||
545 | /* Ensure that any resources allocated through the callback | |
546 | mechanism are released: */ | |
18c64df6 | 547 | sim_io_shutdown (sd); |
8bae0a0c | 548 | |
8bae0a0c | 549 | #if defined(TRACE) |
e3d12c65 | 550 | if (tracefh != NULL && tracefh != stderr) |
8bae0a0c | 551 | fclose(tracefh); |
e3d12c65 | 552 | tracefh = NULL; |
8bae0a0c JSC |
553 | #endif /* TRACE */ |
554 | ||
01737f42 AC |
555 | /* FIXME - free SD */ |
556 | ||
8bae0a0c JSC |
557 | return; |
558 | } | |
559 | ||
8bae0a0c JSC |
560 | |
561 | int | |
53b9417e DE |
562 | sim_write (sd,addr,buffer,size) |
563 | SIM_DESC sd; | |
8bae0a0c JSC |
564 | SIM_ADDR addr; |
565 | unsigned char *buffer; | |
566 | int size; | |
567 | { | |
525d929e | 568 | int index; |
01737f42 | 569 | sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */ |
8bae0a0c JSC |
570 | |
571 | /* Return the number of bytes written, or zero if error. */ | |
572 | #ifdef DEBUG | |
18c64df6 | 573 | sim_io_printf(sd,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr),size); |
8bae0a0c JSC |
574 | #endif |
575 | ||
525d929e AC |
576 | /* We use raw read and write routines, since we do not want to count |
577 | the GDB memory accesses in our statistics gathering. */ | |
578 | ||
579 | for (index = 0; index < size; index++) | |
580 | { | |
581 | address_word vaddr = (address_word)addr + index; | |
582 | address_word paddr; | |
583 | int cca; | |
01737f42 | 584 | if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isSTORE, &paddr, &cca, isRAW)) |
525d929e | 585 | break; |
82ea14fd | 586 | if (sim_core_write_buffer (SD, CPU, read_map, buffer + index, paddr, 1) != 1) |
63be8feb | 587 | break; |
8bae0a0c | 588 | } |
8bae0a0c | 589 | |
525d929e | 590 | return(index); |
8bae0a0c JSC |
591 | } |
592 | ||
593 | int | |
53b9417e DE |
594 | sim_read (sd,addr,buffer,size) |
595 | SIM_DESC sd; | |
8bae0a0c JSC |
596 | SIM_ADDR addr; |
597 | unsigned char *buffer; | |
598 | int size; | |
599 | { | |
600 | int index; | |
01737f42 | 601 | sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */ |
8bae0a0c JSC |
602 | |
603 | /* Return the number of bytes read, or zero if error. */ | |
604 | #ifdef DEBUG | |
18c64df6 | 605 | sim_io_printf(sd,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr),size); |
8bae0a0c JSC |
606 | #endif /* DEBUG */ |
607 | ||
525d929e AC |
608 | for (index = 0; (index < size); index++) |
609 | { | |
610 | address_word vaddr = (address_word)addr + index; | |
611 | address_word paddr; | |
525d929e | 612 | int cca; |
01737f42 | 613 | if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isLOAD, &paddr, &cca, isRAW)) |
525d929e | 614 | break; |
82ea14fd | 615 | if (sim_core_read_buffer (SD, CPU, read_map, buffer + index, paddr, 1) != 1) |
63be8feb | 616 | break; |
525d929e | 617 | } |
8bae0a0c JSC |
618 | |
619 | return(index); | |
620 | } | |
621 | ||
f319bab2 GRK |
622 | int |
623 | sim_store_register (sd,rn,memory,length) | |
53b9417e | 624 | SIM_DESC sd; |
8bae0a0c JSC |
625 | int rn; |
626 | unsigned char *memory; | |
f319bab2 | 627 | int length; |
8bae0a0c | 628 | { |
01737f42 | 629 | sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */ |
50a2a691 AC |
630 | /* NOTE: gdb (the client) stores registers in target byte order |
631 | while the simulator uses host byte order */ | |
8bae0a0c | 632 | #ifdef DEBUG |
18c64df6 | 633 | sim_io_printf(sd,"sim_store_register(%d,*memory=0x%s);\n",rn,pr_addr(*((SIM_ADDR *)memory))); |
8bae0a0c JSC |
634 | #endif /* DEBUG */ |
635 | ||
636 | /* Unfortunately this suffers from the same problem as the register | |
637 | numbering one. We need to know what the width of each logical | |
638 | register number is for the architecture being simulated. */ | |
50a2a691 | 639 | |
0c2c5f61 | 640 | if (cpu->register_widths[rn] == 0) |
a48e8c8d AC |
641 | { |
642 | sim_io_eprintf(sd,"Invalid register width for %d (register store ignored)\n",rn); | |
643 | return 0; | |
644 | } | |
645 | ||
646 | /* start-sanitize-r5900 */ | |
647 | if (rn >= 90 && rn < 90 + 32) | |
648 | { | |
649 | GPR1[rn - 90] = T2H_8 (*(unsigned64*)memory); | |
650 | return 8; | |
651 | } | |
652 | switch (rn) | |
653 | { | |
654 | case REGISTER_SA: | |
655 | SA = T2H_8(*(unsigned64*)memory); | |
656 | return 8; | |
657 | case 122: /* FIXME */ | |
658 | LO1 = T2H_8(*(unsigned64*)memory); | |
659 | return 8; | |
660 | case 123: /* FIXME */ | |
661 | HI1 = T2H_8(*(unsigned64*)memory); | |
662 | return 8; | |
663 | } | |
a48e8c8d | 664 | /* end-sanitize-r5900 */ |
ce4713dc | 665 | |
97908603 RU |
666 | /* start-sanitize-sky */ |
667 | #ifdef TARGET_SKY | |
a859684b | 668 | if (rn >= NUM_R5900_REGS) |
ce4713dc | 669 | { |
a859684b RU |
670 | int size = 4; /* Default register size */ |
671 | ||
ce4713dc | 672 | rn = rn - NUM_R5900_REGS; |
97908603 | 673 | |
a859684b | 674 | if (rn < NUM_VU_INTEGER_REGS) |
d44859a2 | 675 | size = write_vu_int_reg (&(vu0_state.regs), rn, memory); |
97908603 | 676 | else if( rn < NUM_VU_REGS ) |
a859684b RU |
677 | vu_regs[0].f[rn - NUM_VU_INTEGER_REGS] |
678 | = T2H_4( *(unsigned int *) memory ); | |
ce4713dc RU |
679 | else { |
680 | rn = rn - NUM_VU_REGS; | |
681 | ||
a859684b | 682 | if( rn < NUM_VU_INTEGER_REGS ) |
d44859a2 | 683 | size = write_vu_int_reg (&(vu1_state.regs), rn, memory); |
ce4713dc | 684 | else if( rn < NUM_VU_REGS ) |
a859684b RU |
685 | vu_regs[1].f[rn - NUM_VU_INTEGER_REGS] |
686 | = T2H_4( *(unsigned int *) memory ); | |
ce4713dc RU |
687 | else |
688 | sim_io_eprintf( sd, "Invalid VU register (register store ignored)\n" ); | |
689 | } | |
a859684b RU |
690 | |
691 | return size; | |
97908603 | 692 | } |
97908603 RU |
693 | #endif |
694 | /* end-sanitize-sky */ | |
a48e8c8d AC |
695 | |
696 | if (rn >= FGRIDX && rn < FGRIDX + NR_FGR) | |
a97f304b AC |
697 | { |
698 | if (cpu->register_widths[rn] == 32) | |
a48e8c8d AC |
699 | { |
700 | cpu->fgr[rn - FGRIDX] = T2H_4 (*(unsigned32*)memory); | |
701 | return 4; | |
702 | } | |
a97f304b | 703 | else |
a48e8c8d AC |
704 | { |
705 | cpu->fgr[rn - FGRIDX] = T2H_8 (*(unsigned64*)memory); | |
706 | return 8; | |
707 | } | |
a97f304b | 708 | } |
8bae0a0c | 709 | |
a48e8c8d AC |
710 | if (cpu->register_widths[rn] == 32) |
711 | { | |
712 | cpu->registers[rn] = T2H_4 (*(unsigned32*)memory); | |
713 | return 4; | |
714 | } | |
715 | else | |
716 | { | |
717 | cpu->registers[rn] = T2H_8 (*(unsigned64*)memory); | |
718 | return 8; | |
719 | } | |
8bae0a0c JSC |
720 | } |
721 | ||
f319bab2 GRK |
722 | int |
723 | sim_fetch_register (sd,rn,memory,length) | |
53b9417e | 724 | SIM_DESC sd; |
8bae0a0c JSC |
725 | int rn; |
726 | unsigned char *memory; | |
f319bab2 | 727 | int length; |
8bae0a0c | 728 | { |
01737f42 | 729 | sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */ |
50a2a691 AC |
730 | /* NOTE: gdb (the client) stores registers in target byte order |
731 | while the simulator uses host byte order */ | |
8bae0a0c | 732 | #ifdef DEBUG |
18c64df6 | 733 | sim_io_printf(sd,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn,pr_addr(registers[rn])); |
8bae0a0c JSC |
734 | #endif /* DEBUG */ |
735 | ||
0c2c5f61 | 736 | if (cpu->register_widths[rn] == 0) |
a48e8c8d AC |
737 | { |
738 | sim_io_eprintf (sd, "Invalid register width for %d (register fetch ignored)\n",rn); | |
739 | return 0; | |
740 | } | |
741 | ||
742 | /* start-sanitize-r5900 */ | |
743 | if (rn >= 90 && rn < 90 + 32) | |
744 | { | |
745 | *(unsigned64*)memory = GPR1[rn - 90]; | |
746 | return 8; | |
747 | } | |
748 | switch (rn) | |
749 | { | |
750 | case REGISTER_SA: | |
751 | *((unsigned64*)memory) = H2T_8(SA); | |
752 | return 8; | |
753 | case 122: /* FIXME */ | |
754 | *((unsigned64*)memory) = H2T_8(LO1); | |
755 | return 8; | |
756 | case 123: /* FIXME */ | |
757 | *((unsigned64*)memory) = H2T_8(HI1); | |
758 | return 8; | |
759 | } | |
a48e8c8d | 760 | /* end-sanitize-r5900 */ |
ce4713dc | 761 | |
97908603 RU |
762 | /* start-sanitize-sky */ |
763 | #ifdef TARGET_SKY | |
a859684b | 764 | if (rn >= NUM_R5900_REGS) |
ce4713dc | 765 | { |
a859684b RU |
766 | int size = 4; /* default register width */ |
767 | ||
ce4713dc | 768 | rn = rn - NUM_R5900_REGS; |
97908603 | 769 | |
a859684b | 770 | if (rn < NUM_VU_INTEGER_REGS) |
d44859a2 | 771 | size = read_vu_int_reg (&(vu0_state.regs), rn, memory); |
a859684b RU |
772 | else if (rn < NUM_VU_REGS) |
773 | *((unsigned int *) memory) | |
774 | = H2T_4( vu_regs[0].f[rn - NUM_VU_INTEGER_REGS] ); | |
775 | else | |
776 | { | |
777 | rn = rn - NUM_VU_REGS; | |
ce4713dc | 778 | |
a859684b | 779 | if (rn < NUM_VU_INTEGER_REGS) |
d44859a2 | 780 | size = read_vu_int_reg (&(vu1_state.regs), rn, memory); |
a859684b RU |
781 | else if (rn < NUM_VU_REGS) |
782 | (*(unsigned int *) memory) | |
783 | = H2T_4( vu_regs[1].f[rn - NUM_VU_INTEGER_REGS] ); | |
784 | else | |
785 | sim_io_eprintf( sd, "Invalid VU register (register fetch ignored)\n" ); | |
786 | } | |
787 | ||
788 | return size; | |
97908603 | 789 | } |
97908603 RU |
790 | #endif |
791 | /* end-sanitize-sky */ | |
a48e8c8d AC |
792 | |
793 | /* Any floating point register */ | |
794 | if (rn >= FGRIDX && rn < FGRIDX + NR_FGR) | |
a97f304b AC |
795 | { |
796 | if (cpu->register_widths[rn] == 32) | |
a48e8c8d AC |
797 | { |
798 | *(unsigned32*)memory = H2T_4 (cpu->fgr[rn - FGRIDX]); | |
799 | return 4; | |
800 | } | |
a97f304b | 801 | else |
a48e8c8d AC |
802 | { |
803 | *(unsigned64*)memory = H2T_8 (cpu->fgr[rn - FGRIDX]); | |
804 | return 8; | |
805 | } | |
a97f304b | 806 | } |
50a2a691 | 807 | |
a48e8c8d AC |
808 | if (cpu->register_widths[rn] == 32) |
809 | { | |
810 | *(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->registers[rn])); | |
811 | return 4; | |
812 | } | |
813 | else | |
814 | { | |
815 | *(unsigned64*)memory = H2T_8 ((unsigned64)(cpu->registers[rn])); | |
816 | return 8; | |
817 | } | |
8bae0a0c | 818 | } |
50a2a691 | 819 | |
8bae0a0c | 820 | |
9d52bcb7 | 821 | SIM_RC |
fafce69a | 822 | sim_create_inferior (sd, abfd, argv,env) |
53b9417e | 823 | SIM_DESC sd; |
fafce69a | 824 | struct _bfd *abfd; |
8bae0a0c JSC |
825 | char **argv; |
826 | char **env; | |
827 | { | |
50a2a691 | 828 | |
8bae0a0c | 829 | #ifdef DEBUG |
9d52bcb7 DE |
830 | printf("DBG: sim_create_inferior entered: start_address = 0x%s\n", |
831 | pr_addr(PC)); | |
8bae0a0c JSC |
832 | #endif /* DEBUG */ |
833 | ||
0c2c5f61 | 834 | ColdReset(sd); |
50a2a691 | 835 | |
fafce69a | 836 | if (abfd != NULL) |
01737f42 AC |
837 | { |
838 | /* override PC value set by ColdReset () */ | |
839 | int cpu_nr; | |
840 | for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++) | |
841 | { | |
842 | sim_cpu *cpu = STATE_CPU (sd, cpu_nr); | |
843 | CIA_SET (cpu, (unsigned64) bfd_get_start_address (abfd)); | |
844 | } | |
845 | } | |
2e61a3ad | 846 | |
f24b7b69 | 847 | #if 0 /* def DEBUG */ |
dad6f1f3 | 848 | if (argv || env) |
8bae0a0c | 849 | { |
dad6f1f3 AC |
850 | /* We should really place the argv slot values into the argument |
851 | registers, and onto the stack as required. However, this | |
852 | assumes that we have a stack defined, which is not | |
853 | necessarily true at the moment. */ | |
854 | char **cptr; | |
855 | sim_io_printf(sd,"sim_create_inferior() : passed arguments ignored\n"); | |
856 | for (cptr = argv; (cptr && *cptr); cptr++) | |
857 | printf("DBG: arg \"%s\"\n",*cptr); | |
8bae0a0c JSC |
858 | } |
859 | #endif /* DEBUG */ | |
8bae0a0c | 860 | |
9d52bcb7 | 861 | return SIM_RC_OK; |
8bae0a0c JSC |
862 | } |
863 | ||
8bae0a0c | 864 | void |
53b9417e DE |
865 | sim_do_command (sd,cmd) |
866 | SIM_DESC sd; | |
8bae0a0c JSC |
867 | char *cmd; |
868 | { | |
63be8feb AC |
869 | if (sim_args_command (sd, cmd) != SIM_RC_OK) |
870 | sim_io_printf (sd, "Error: \"%s\" is not a valid MIPS simulator command.\n", | |
871 | cmd); | |
8bae0a0c JSC |
872 | } |
873 | ||
8bae0a0c JSC |
874 | /*---------------------------------------------------------------------------*/ |
875 | /*-- Private simulator support interface ------------------------------------*/ | |
876 | /*---------------------------------------------------------------------------*/ | |
877 | ||
525d929e AC |
878 | /* Read a null terminated string from memory, return in a buffer */ |
879 | static char * | |
880 | fetch_str (sd, addr) | |
881 | SIM_DESC sd; | |
882 | address_word addr; | |
883 | { | |
884 | char *buf; | |
885 | int nr = 0; | |
886 | char null; | |
887 | while (sim_read (sd, addr + nr, &null, 1) == 1 && null != 0) | |
888 | nr++; | |
889 | buf = NZALLOC (char, nr + 1); | |
890 | sim_read (sd, addr, buf, nr); | |
891 | return buf; | |
892 | } | |
893 | ||
a9f7253f | 894 | /* Simple monitor interface (currently setup for the IDT and PMON monitors) */ |
8bae0a0c | 895 | static void |
01737f42 AC |
896 | sim_monitor (SIM_DESC sd, |
897 | sim_cpu *cpu, | |
898 | address_word cia, | |
899 | unsigned int reason) | |
8bae0a0c | 900 | { |
53b9417e DE |
901 | #ifdef DEBUG |
902 | printf("DBG: sim_monitor: entered (reason = %d)\n",reason); | |
903 | #endif /* DEBUG */ | |
904 | ||
8bae0a0c JSC |
905 | /* The IDT monitor actually allows two instructions per vector |
906 | slot. However, the simulator currently causes a trap on each | |
907 | individual instruction. We cheat, and lose the bottom bit. */ | |
908 | reason >>= 1; | |
909 | ||
910 | /* The following callback functions are available, however the | |
911 | monitor we are simulating does not make use of them: get_errno, | |
912 | isatty, lseek, rename, system, time and unlink */ | |
525d929e AC |
913 | switch (reason) |
914 | { | |
915 | ||
8bae0a0c JSC |
916 | case 6: /* int open(char *path,int flags) */ |
917 | { | |
525d929e AC |
918 | char *path = fetch_str (sd, A0); |
919 | V0 = sim_io_open (sd, path, (int)A1); | |
920 | zfree (path); | |
921 | break; | |
8bae0a0c | 922 | } |
8bae0a0c JSC |
923 | |
924 | case 7: /* int read(int file,char *ptr,int len) */ | |
925 | { | |
525d929e AC |
926 | int fd = A0; |
927 | int nr = A2; | |
928 | char *buf = zalloc (nr); | |
929 | V0 = sim_io_read (sd, fd, buf, nr); | |
930 | sim_write (sd, A1, buf, nr); | |
931 | zfree (buf); | |
8bae0a0c JSC |
932 | } |
933 | break; | |
934 | ||
935 | case 8: /* int write(int file,char *ptr,int len) */ | |
936 | { | |
525d929e AC |
937 | int fd = A0; |
938 | int nr = A2; | |
939 | char *buf = zalloc (nr); | |
940 | sim_read (sd, A1, buf, nr); | |
941 | V0 = sim_io_write (sd, fd, buf, nr); | |
942 | zfree (buf); | |
943 | break; | |
8bae0a0c | 944 | } |
8bae0a0c JSC |
945 | |
946 | case 10: /* int close(int file) */ | |
525d929e AC |
947 | { |
948 | V0 = sim_io_close (sd, (int)A0); | |
949 | break; | |
950 | } | |
8bae0a0c | 951 | |
e0e0fc76 MA |
952 | case 2: /* Densan monitor: char inbyte(int waitflag) */ |
953 | { | |
954 | if (A0 == 0) /* waitflag == NOWAIT */ | |
192ae475 | 955 | V0 = (unsigned_word)-1; |
e0e0fc76 MA |
956 | } |
957 | /* Drop through to case 11 */ | |
958 | ||
8bae0a0c JSC |
959 | case 11: /* char inbyte(void) */ |
960 | { | |
961 | char tmp; | |
525d929e AC |
962 | if (sim_io_read_stdin (sd, &tmp, sizeof(char)) != sizeof(char)) |
963 | { | |
964 | sim_io_error(sd,"Invalid return from character read"); | |
192ae475 | 965 | V0 = (unsigned_word)-1; |
525d929e | 966 | } |
8bae0a0c | 967 | else |
192ae475 | 968 | V0 = (unsigned_word)tmp; |
525d929e | 969 | break; |
8bae0a0c | 970 | } |
8bae0a0c | 971 | |
e0e0fc76 | 972 | case 3: /* Densan monitor: void co(char chr) */ |
8bae0a0c JSC |
973 | case 12: /* void outbyte(char chr) : write a byte to "stdout" */ |
974 | { | |
975 | char tmp = (char)(A0 & 0xFF); | |
525d929e AC |
976 | sim_io_write_stdout (sd, &tmp, sizeof(char)); |
977 | break; | |
8bae0a0c | 978 | } |
8bae0a0c JSC |
979 | |
980 | case 17: /* void _exit() */ | |
525d929e AC |
981 | { |
982 | sim_io_eprintf (sd, "sim_monitor(17): _exit(int reason) to be coded\n"); | |
01737f42 | 983 | sim_engine_halt (SD, CPU, NULL, NULL_CIA, sim_exited, |
525d929e AC |
984 | (unsigned int)(A0 & 0xFFFFFFFF)); |
985 | break; | |
986 | } | |
8bae0a0c | 987 | |
280f90e1 AMT |
988 | case 28 : /* PMON flush_cache */ |
989 | break; | |
990 | ||
8bae0a0c JSC |
991 | case 55: /* void get_mem_info(unsigned int *ptr) */ |
992 | /* in: A0 = pointer to three word memory location */ | |
993 | /* out: [A0 + 0] = size */ | |
994 | /* [A0 + 4] = instruction cache size */ | |
995 | /* [A0 + 8] = data cache size */ | |
996 | { | |
525d929e AC |
997 | address_word value = MEM_SIZE /* FIXME STATE_MEM_SIZE (sd) */; |
998 | H2T (value); | |
999 | sim_write (sd, A0, (char *)&value, sizeof (value)); | |
030843d7 | 1000 | /* sim_io_eprintf (sd, "sim: get_mem_info() depreciated\n"); */ |
525d929e | 1001 | break; |
8bae0a0c | 1002 | } |
525d929e | 1003 | |
a9f7253f JSC |
1004 | case 158 : /* PMON printf */ |
1005 | /* in: A0 = pointer to format string */ | |
1006 | /* A1 = optional argument 1 */ | |
1007 | /* A2 = optional argument 2 */ | |
1008 | /* A3 = optional argument 3 */ | |
1009 | /* out: void */ | |
f24b7b69 | 1010 | /* The following is based on the PMON printf source */ |
a9f7253f | 1011 | { |
525d929e AC |
1012 | address_word s = A0; |
1013 | char c; | |
1014 | signed_word *ap = &A1; /* 1st argument */ | |
f24b7b69 JSC |
1015 | /* This isn't the quickest way, since we call the host print |
1016 | routine for every character almost. But it does avoid | |
1017 | having to allocate and manage a temporary string buffer. */ | |
525d929e AC |
1018 | /* TODO: Include check that we only use three arguments (A1, |
1019 | A2 and A3) */ | |
1020 | while (sim_read (sd, s++, &c, 1) && c != '\0') | |
1021 | { | |
1022 | if (c == '%') | |
1023 | { | |
1024 | char tmp[40]; | |
1025 | enum {FMT_RJUST, FMT_LJUST, FMT_RJUST0, FMT_CENTER} fmt = FMT_RJUST; | |
1026 | int width = 0, trunc = 0, haddot = 0, longlong = 0; | |
1027 | while (sim_read (sd, s++, &c, 1) && c != '\0') | |
1028 | { | |
1029 | if (strchr ("dobxXulscefg%", s)) | |
1030 | break; | |
1031 | else if (c == '-') | |
1032 | fmt = FMT_LJUST; | |
1033 | else if (c == '0') | |
1034 | fmt = FMT_RJUST0; | |
1035 | else if (c == '~') | |
1036 | fmt = FMT_CENTER; | |
1037 | else if (c == '*') | |
1038 | { | |
1039 | if (haddot) | |
1040 | trunc = (int)*ap++; | |
1041 | else | |
1042 | width = (int)*ap++; | |
1043 | } | |
1044 | else if (c >= '1' && c <= '9') | |
1045 | { | |
1046 | address_word t = s; | |
1047 | unsigned int n; | |
1048 | while (sim_read (sd, s++, &c, 1) == 1 && isdigit (c)) | |
1049 | tmp[s - t] = c; | |
1050 | tmp[s - t] = '\0'; | |
1051 | n = (unsigned int)strtol(tmp,NULL,10); | |
1052 | if (haddot) | |
1053 | trunc = n; | |
1054 | else | |
1055 | width = n; | |
1056 | s--; | |
1057 | } | |
1058 | else if (c == '.') | |
1059 | haddot = 1; | |
1060 | } | |
1061 | switch (c) | |
1062 | { | |
1063 | case '%': | |
1064 | sim_io_printf (sd, "%%"); | |
1065 | break; | |
1066 | case 's': | |
1067 | if ((int)*ap != 0) | |
1068 | { | |
1069 | address_word p = *ap++; | |
1070 | char ch; | |
1071 | while (sim_read (sd, p++, &ch, 1) == 1 && ch != '\0') | |
1072 | sim_io_printf(sd, "%c", ch); | |
1073 | } | |
1074 | else | |
1075 | sim_io_printf(sd,"(null)"); | |
1076 | break; | |
1077 | case 'c': | |
1078 | sim_io_printf (sd, "%c", (int)*ap++); | |
1079 | break; | |
1080 | default: | |
1081 | if (c == 'l') | |
1082 | { | |
1083 | sim_read (sd, s++, &c, 1); | |
1084 | if (c == 'l') | |
1085 | { | |
1086 | longlong = 1; | |
1087 | sim_read (sd, s++, &c, 1); | |
1088 | } | |
1089 | } | |
1090 | if (strchr ("dobxXu", c)) | |
1091 | { | |
1092 | word64 lv = (word64) *ap++; | |
1093 | if (c == 'b') | |
1094 | sim_io_printf(sd,"<binary not supported>"); | |
1095 | else | |
1096 | { | |
1097 | sprintf (tmp, "%%%s%c", longlong ? "ll" : "", c); | |
1098 | if (longlong) | |
1099 | sim_io_printf(sd, tmp, lv); | |
1100 | else | |
1101 | sim_io_printf(sd, tmp, (int)lv); | |
1102 | } | |
1103 | } | |
1104 | else if (strchr ("eEfgG", c)) | |
1105 | { | |
1106 | double dbl = *(double*)(ap++); | |
1107 | sprintf (tmp, "%%%d.%d%c", width, trunc, c); | |
1108 | sim_io_printf (sd, tmp, dbl); | |
1109 | trunc = 0; | |
1110 | } | |
1111 | } | |
1112 | } | |
1113 | else | |
1114 | sim_io_printf(sd, "%c", c); | |
1115 | } | |
1116 | break; | |
a9f7253f | 1117 | } |
a9f7253f | 1118 | |
8bae0a0c | 1119 | default: |
525d929e | 1120 | sim_io_error (sd, "TODO: sim_monitor(%d) : PC = 0x%s\n", |
95469ceb | 1121 | reason, pr_addr(cia)); |
8bae0a0c JSC |
1122 | break; |
1123 | } | |
1124 | return; | |
1125 | } | |
1126 | ||
7e6c297e ILT |
1127 | /* Store a word into memory. */ |
1128 | ||
1129 | static void | |
01737f42 AC |
1130 | store_word (SIM_DESC sd, |
1131 | sim_cpu *cpu, | |
1132 | address_word cia, | |
1133 | uword64 vaddr, | |
192ae475 | 1134 | signed_word val) |
7e6c297e | 1135 | { |
dad6f1f3 | 1136 | address_word paddr; |
7e6c297e ILT |
1137 | int uncached; |
1138 | ||
1139 | if ((vaddr & 3) != 0) | |
18c64df6 | 1140 | SignalExceptionAddressStore (); |
7e6c297e ILT |
1141 | else |
1142 | { | |
1143 | if (AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, | |
1144 | isTARGET, isREAL)) | |
1145 | { | |
1146 | const uword64 mask = 7; | |
1147 | uword64 memval; | |
1148 | unsigned int byte; | |
1149 | ||
1150 | paddr = (paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)); | |
1151 | byte = (vaddr & mask) ^ (BigEndianCPU << 2); | |
1152 | memval = ((uword64) val) << (8 * byte); | |
53b9417e | 1153 | StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr, |
7e6c297e ILT |
1154 | isREAL); |
1155 | } | |
1156 | } | |
1157 | } | |
1158 | ||
1159 | /* Load a word from memory. */ | |
1160 | ||
192ae475 | 1161 | static signed_word |
01737f42 AC |
1162 | load_word (SIM_DESC sd, |
1163 | sim_cpu *cpu, | |
1164 | address_word cia, | |
1165 | uword64 vaddr) | |
7e6c297e ILT |
1166 | { |
1167 | if ((vaddr & 3) != 0) | |
18c64df6 | 1168 | SignalExceptionAddressLoad (); |
7e6c297e ILT |
1169 | else |
1170 | { | |
dad6f1f3 | 1171 | address_word paddr; |
7e6c297e ILT |
1172 | int uncached; |
1173 | ||
1174 | if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, | |
1175 | isTARGET, isREAL)) | |
1176 | { | |
1177 | const uword64 mask = 0x7; | |
1178 | const unsigned int reverse = ReverseEndian ? 1 : 0; | |
1179 | const unsigned int bigend = BigEndianCPU ? 1 : 0; | |
1180 | uword64 memval; | |
1181 | unsigned int byte; | |
1182 | ||
1183 | paddr = (paddr & ~mask) | ((paddr & mask) ^ (reverse << 2)); | |
53b9417e | 1184 | LoadMemory (&memval,NULL,uncached, AccessLength_WORD, paddr, vaddr, |
7e6c297e ILT |
1185 | isDATA, isREAL); |
1186 | byte = (vaddr & mask) ^ (bigend << 2); | |
1187 | return SIGNEXTEND (((memval >> (8 * byte)) & 0xffffffff), 32); | |
1188 | } | |
1189 | } | |
1190 | ||
1191 | return 0; | |
1192 | } | |
1193 | ||
1194 | /* Simulate the mips16 entry and exit pseudo-instructions. These | |
1195 | would normally be handled by the reserved instruction exception | |
1196 | code, but for ease of simulation we just handle them directly. */ | |
1197 | ||
1198 | static void | |
01737f42 AC |
1199 | mips16_entry (SIM_DESC sd, |
1200 | sim_cpu *cpu, | |
1201 | address_word cia, | |
1202 | unsigned int insn) | |
7e6c297e ILT |
1203 | { |
1204 | int aregs, sregs, rreg; | |
1205 | ||
53b9417e DE |
1206 | #ifdef DEBUG |
1207 | printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn); | |
1208 | #endif /* DEBUG */ | |
1209 | ||
7e6c297e ILT |
1210 | aregs = (insn & 0x700) >> 8; |
1211 | sregs = (insn & 0x0c0) >> 6; | |
1212 | rreg = (insn & 0x020) >> 5; | |
1213 | ||
da0bce9c ILT |
1214 | /* This should be checked by the caller. */ |
1215 | if (sregs == 3) | |
7e6c297e ILT |
1216 | abort (); |
1217 | ||
da0bce9c | 1218 | if (aregs < 5) |
7e6c297e ILT |
1219 | { |
1220 | int i; | |
192ae475 | 1221 | signed_word tsp; |
7e6c297e ILT |
1222 | |
1223 | /* This is the entry pseudo-instruction. */ | |
1224 | ||
1225 | for (i = 0; i < aregs; i++) | |
01737f42 | 1226 | store_word (SD, CPU, cia, (uword64) (SP + 4 * i), GPR[i + 4]); |
7e6c297e ILT |
1227 | |
1228 | tsp = SP; | |
1229 | SP -= 32; | |
1230 | ||
1231 | if (rreg) | |
1232 | { | |
1233 | tsp -= 4; | |
01737f42 | 1234 | store_word (SD, CPU, cia, (uword64) tsp, RA); |
7e6c297e ILT |
1235 | } |
1236 | ||
1237 | for (i = 0; i < sregs; i++) | |
1238 | { | |
1239 | tsp -= 4; | |
01737f42 | 1240 | store_word (SD, CPU, cia, (uword64) tsp, GPR[16 + i]); |
7e6c297e ILT |
1241 | } |
1242 | } | |
1243 | else | |
1244 | { | |
1245 | int i; | |
192ae475 | 1246 | signed_word tsp; |
7e6c297e ILT |
1247 | |
1248 | /* This is the exit pseudo-instruction. */ | |
1249 | ||
1250 | tsp = SP + 32; | |
1251 | ||
1252 | if (rreg) | |
1253 | { | |
1254 | tsp -= 4; | |
01737f42 | 1255 | RA = load_word (SD, CPU, cia, (uword64) tsp); |
7e6c297e ILT |
1256 | } |
1257 | ||
1258 | for (i = 0; i < sregs; i++) | |
1259 | { | |
1260 | tsp -= 4; | |
01737f42 | 1261 | GPR[i + 16] = load_word (SD, CPU, cia, (uword64) tsp); |
7e6c297e ILT |
1262 | } |
1263 | ||
1264 | SP += 32; | |
1265 | ||
192ae475 | 1266 | if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT) |
da0bce9c | 1267 | { |
192ae475 AC |
1268 | if (aregs == 5) |
1269 | { | |
1270 | FGR[0] = WORD64LO (GPR[4]); | |
1271 | FPR_STATE[0] = fmt_uninterpreted; | |
1272 | } | |
1273 | else if (aregs == 6) | |
1274 | { | |
1275 | FGR[0] = WORD64LO (GPR[5]); | |
1276 | FGR[1] = WORD64LO (GPR[4]); | |
1277 | FPR_STATE[0] = fmt_uninterpreted; | |
1278 | FPR_STATE[1] = fmt_uninterpreted; | |
1279 | } | |
1280 | } | |
da0bce9c | 1281 | |
7e6c297e ILT |
1282 | PC = RA; |
1283 | } | |
192ae475 | 1284 | |
7e6c297e ILT |
1285 | } |
1286 | ||
8bae0a0c JSC |
1287 | /*-- trace support ----------------------------------------------------------*/ |
1288 | ||
1289 | /* The TRACE support is provided (if required) in the memory accessing | |
1290 | routines. Since we are also providing the architecture specific | |
1291 | features, the architecture simulation code can also deal with | |
1292 | notifying the TRACE world of cache flushes, etc. Similarly we do | |
1293 | not need to provide profiling support in the simulator engine, | |
1294 | since we can sample in the instruction fetch control loop. By | |
1295 | defining the TRACE manifest, we add tracing as a run-time | |
1296 | option. */ | |
1297 | ||
1298 | #if defined(TRACE) | |
1299 | /* Tracing by default produces "din" format (as required by | |
1300 | dineroIII). Each line of such a trace file *MUST* have a din label | |
1301 | and address field. The rest of the line is ignored, so comments can | |
1302 | be included if desired. The first field is the label which must be | |
1303 | one of the following values: | |
1304 | ||
1305 | 0 read data | |
1306 | 1 write data | |
1307 | 2 instruction fetch | |
1308 | 3 escape record (treated as unknown access type) | |
1309 | 4 escape record (causes cache flush) | |
1310 | ||
1311 | The address field is a 32bit (lower-case) hexadecimal address | |
1312 | value. The address should *NOT* be preceded by "0x". | |
1313 | ||
1314 | The size of the memory transfer is not important when dealing with | |
1315 | cache lines (as long as no more than a cache line can be | |
1316 | transferred in a single operation :-), however more information | |
1317 | could be given following the dineroIII requirement to allow more | |
1318 | complete memory and cache simulators to provide better | |
1319 | results. i.e. the University of Pisa has a cache simulator that can | |
1320 | also take bus size and speed as (variable) inputs to calculate | |
1321 | complete system performance (a much more useful ability when trying | |
1322 | to construct an end product, rather than a processor). They | |
1323 | currently have an ARM version of their tool called ChARM. */ | |
1324 | ||
e3d12c65 | 1325 | |
030843d7 | 1326 | void |
01737f42 AC |
1327 | dotrace (SIM_DESC sd, |
1328 | sim_cpu *cpu, | |
1329 | FILE *tracefh, | |
1330 | int type, | |
1331 | SIM_ADDR address, | |
1332 | int width, | |
1333 | char *comment,...) | |
8bae0a0c | 1334 | { |
0c2c5f61 | 1335 | if (STATE & simTRACE) { |
8bae0a0c | 1336 | va_list ap; |
53b9417e | 1337 | fprintf(tracefh,"%d %s ; width %d ; ", |
6429b296 | 1338 | type, |
53b9417e DE |
1339 | pr_addr(address), |
1340 | width); | |
8bae0a0c | 1341 | va_start(ap,comment); |
6429b296 | 1342 | vfprintf(tracefh,comment,ap); |
8bae0a0c JSC |
1343 | va_end(ap); |
1344 | fprintf(tracefh,"\n"); | |
1345 | } | |
1346 | /* NOTE: Since the "din" format will only accept 32bit addresses, and | |
1347 | we may be generating 64bit ones, we should put the hi-32bits of the | |
1348 | address into the comment field. */ | |
1349 | ||
1350 | /* TODO: Provide a buffer for the trace lines. We can then avoid | |
1351 | performing writes until the buffer is filled, or the file is | |
1352 | being closed. */ | |
1353 | ||
1354 | /* NOTE: We could consider adding a comment field to the "din" file | |
1355 | produced using type 3 markers (unknown access). This would then | |
1356 | allow information about the program that the "din" is for, and | |
1357 | the MIPs world that was being simulated, to be placed into the | |
1358 | trace file. */ | |
1359 | ||
1360 | return; | |
1361 | } | |
1362 | #endif /* TRACE */ | |
1363 | ||
1364 | /*---------------------------------------------------------------------------*/ | |
1365 | /*-- simulator engine -------------------------------------------------------*/ | |
1366 | /*---------------------------------------------------------------------------*/ | |
1367 | ||
1368 | static void | |
01737f42 | 1369 | ColdReset (SIM_DESC sd) |
8bae0a0c | 1370 | { |
01737f42 AC |
1371 | int cpu_nr; |
1372 | for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++) | |
dad6f1f3 | 1373 | { |
01737f42 AC |
1374 | sim_cpu *cpu = STATE_CPU (sd, cpu_nr); |
1375 | /* RESET: Fixed PC address: */ | |
1376 | PC = UNSIGNED64 (0xFFFFFFFFBFC00000); | |
1377 | /* The reset vector address is in the unmapped, uncached memory space. */ | |
1378 | ||
1379 | SR &= ~(status_SR | status_TS | status_RP); | |
1380 | SR |= (status_ERL | status_BEV); | |
1381 | ||
1382 | /* Cheat and allow access to the complete register set immediately */ | |
1383 | if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT | |
1384 | && WITH_TARGET_WORD_BITSIZE == 64) | |
1385 | SR |= status_FR; /* 64bit registers */ | |
1386 | ||
1387 | /* Ensure that any instructions with pending register updates are | |
1388 | cleared: */ | |
2acd126a | 1389 | PENDING_INVALIDATE(); |
01737f42 AC |
1390 | |
1391 | /* Initialise the FPU registers to the unknown state */ | |
1392 | if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT) | |
1393 | { | |
1394 | int rn; | |
1395 | for (rn = 0; (rn < 32); rn++) | |
1396 | FPR_STATE[rn] = fmt_uninterpreted; | |
1397 | } | |
1398 | ||
dad6f1f3 | 1399 | } |
8bae0a0c JSC |
1400 | } |
1401 | ||
dad6f1f3 AC |
1402 | /* Description from page A-22 of the "MIPS IV Instruction Set" manual |
1403 | (revision 3.1) */ | |
8bae0a0c JSC |
1404 | /* Translate a virtual address to a physical address and cache |
1405 | coherence algorithm describing the mechanism used to resolve the | |
1406 | memory reference. Given the virtual address vAddr, and whether the | |
1407 | reference is to Instructions ot Data (IorD), find the corresponding | |
1408 | physical address (pAddr) and the cache coherence algorithm (CCA) | |
1409 | used to resolve the reference. If the virtual address is in one of | |
1410 | the unmapped address spaces the physical address and the CCA are | |
1411 | determined directly by the virtual address. If the virtual address | |
1412 | is in one of the mapped address spaces then the TLB is used to | |
1413 | determine the physical address and access type; if the required | |
1414 | translation is not present in the TLB or the desired access is not | |
1415 | permitted the function fails and an exception is taken. | |
1416 | ||
dad6f1f3 AC |
1417 | NOTE: Normally (RAW == 0), when address translation fails, this |
1418 | function raises an exception and does not return. */ | |
8bae0a0c | 1419 | |
18c64df6 | 1420 | int |
01737f42 AC |
1421 | address_translation (SIM_DESC sd, |
1422 | sim_cpu *cpu, | |
1423 | address_word cia, | |
1424 | address_word vAddr, | |
1425 | int IorD, | |
1426 | int LorS, | |
1427 | address_word *pAddr, | |
1428 | int *CCA, | |
1429 | int raw) | |
8bae0a0c JSC |
1430 | { |
1431 | int res = -1; /* TRUE : Assume good return */ | |
1432 | ||
1433 | #ifdef DEBUG | |
18c64df6 | 1434 | sim_io_printf(sd,"AddressTranslation(0x%s,%s,%s,...);\n",pr_addr(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"),(LorS ? "iSTORE" : "isLOAD")); |
8bae0a0c JSC |
1435 | #endif |
1436 | ||
1437 | /* Check that the address is valid for this memory model */ | |
1438 | ||
1439 | /* For a simple (flat) memory model, we simply pass virtual | |
1440 | addressess through (mostly) unchanged. */ | |
1441 | vAddr &= 0xFFFFFFFF; | |
a9f7253f | 1442 | |
8bae0a0c JSC |
1443 | *pAddr = vAddr; /* default for isTARGET */ |
1444 | *CCA = Uncached; /* not used for isHOST */ | |
1445 | ||
8bae0a0c JSC |
1446 | return(res); |
1447 | } | |
1448 | ||
63be8feb AC |
1449 | /* Description from page A-23 of the "MIPS IV Instruction Set" manual |
1450 | (revision 3.1) */ | |
8bae0a0c JSC |
1451 | /* Prefetch data from memory. Prefetch is an advisory instruction for |
1452 | which an implementation specific action is taken. The action taken | |
1453 | may increase performance, but must not change the meaning of the | |
1454 | program, or alter architecturally-visible state. */ | |
50a2a691 | 1455 | |
ea985d24 | 1456 | void |
01737f42 AC |
1457 | prefetch (SIM_DESC sd, |
1458 | sim_cpu *cpu, | |
1459 | address_word cia, | |
1460 | int CCA, | |
1461 | address_word pAddr, | |
1462 | address_word vAddr, | |
1463 | int DATA, | |
1464 | int hint) | |
8bae0a0c JSC |
1465 | { |
1466 | #ifdef DEBUG | |
18c64df6 | 1467 | sim_io_printf(sd,"Prefetch(%d,0x%s,0x%s,%d,%d);\n",CCA,pr_addr(pAddr),pr_addr(vAddr),DATA,hint); |
8bae0a0c JSC |
1468 | #endif /* DEBUG */ |
1469 | ||
1470 | /* For our simple memory model we do nothing */ | |
1471 | return; | |
1472 | } | |
1473 | ||
63be8feb AC |
1474 | /* Description from page A-22 of the "MIPS IV Instruction Set" manual |
1475 | (revision 3.1) */ | |
8bae0a0c JSC |
1476 | /* Load a value from memory. Use the cache and main memory as |
1477 | specified in the Cache Coherence Algorithm (CCA) and the sort of | |
1478 | access (IorD) to find the contents of AccessLength memory bytes | |
1479 | starting at physical location pAddr. The data is returned in the | |
1480 | fixed width naturally-aligned memory element (MemElem). The | |
1481 | low-order two (or three) bits of the address and the AccessLength | |
1482 | indicate which of the bytes within MemElem needs to be given to the | |
1483 | processor. If the memory access type of the reference is uncached | |
1484 | then only the referenced bytes are read from memory and valid | |
1485 | within the memory element. If the access type is cached, and the | |
1486 | data is not present in cache, an implementation specific size and | |
1487 | alignment block of memory is read and loaded into the cache to | |
1488 | satisfy a load reference. At a minimum, the block is the entire | |
1489 | memory element. */ | |
18c64df6 | 1490 | void |
01737f42 AC |
1491 | load_memory (SIM_DESC sd, |
1492 | sim_cpu *cpu, | |
1493 | address_word cia, | |
1494 | uword64* memvalp, | |
1495 | uword64* memval1p, | |
1496 | int CCA, | |
1497 | int AccessLength, | |
1498 | address_word pAddr, | |
1499 | address_word vAddr, | |
1500 | int IorD) | |
8bae0a0c | 1501 | { |
50a2a691 AC |
1502 | uword64 value = 0; |
1503 | uword64 value1 = 0; | |
8bae0a0c JSC |
1504 | |
1505 | #ifdef DEBUG | |
63be8feb | 1506 | sim_io_printf(sd,"DBG: LoadMemory(%p,%p,%d,%d,0x%s,0x%s,%s)\n",memvalp,memval1p,CCA,AccessLength,pr_addr(pAddr),pr_addr(vAddr),(IorD ? "isDATA" : "isINSTRUCTION")); |
8bae0a0c JSC |
1507 | #endif /* DEBUG */ |
1508 | ||
1509 | #if defined(WARN_MEM) | |
1510 | if (CCA != uncached) | |
63be8feb | 1511 | sim_io_eprintf(sd,"LoadMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA); |
8bae0a0c JSC |
1512 | #endif /* WARN_MEM */ |
1513 | ||
8bae0a0c JSC |
1514 | /* If instruction fetch then we need to check that the two lo-order |
1515 | bits are zero, otherwise raise a InstructionFetch exception: */ | |
6429b296 JW |
1516 | if ((IorD == isINSTRUCTION) |
1517 | && ((pAddr & 0x3) != 0) | |
1518 | && (((pAddr & 0x1) != 0) || ((vAddr & 0x1) == 0))) | |
63be8feb AC |
1519 | SignalExceptionInstructionFetch (); |
1520 | ||
1521 | if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK) | |
1522 | { | |
1523 | /* In reality this should be a Bus Error */ | |
1524 | sim_io_error (sd, "AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n", | |
1525 | AccessLength, | |
1526 | (LOADDRMASK + 1) << 2, | |
1527 | pr_addr (pAddr)); | |
1528 | } | |
8bae0a0c | 1529 | |
8bae0a0c | 1530 | #if defined(TRACE) |
01737f42 | 1531 | dotrace (SD, CPU, tracefh,((IorD == isDATA) ? 0 : 2),(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"load%s",((IorD == isDATA) ? "" : " instruction")); |
8bae0a0c | 1532 | #endif /* TRACE */ |
63be8feb AC |
1533 | |
1534 | /* Read the specified number of bytes from memory. Adjust for | |
1535 | host/target byte ordering/ Align the least significant byte | |
1536 | read. */ | |
8bae0a0c | 1537 | |
63be8feb AC |
1538 | switch (AccessLength) |
1539 | { | |
1540 | case AccessLength_QUADWORD : | |
1541 | { | |
82ea14fd | 1542 | unsigned_16 val = sim_core_read_aligned_16 (cpu, NULL_CIA, read_map, pAddr); |
63be8feb AC |
1543 | value1 = VH8_16 (val); |
1544 | value = VL8_16 (val); | |
1545 | break; | |
8bae0a0c | 1546 | } |
63be8feb | 1547 | case AccessLength_DOUBLEWORD : |
01737f42 | 1548 | value = sim_core_read_aligned_8 (cpu, NULL_CIA, |
82ea14fd | 1549 | read_map, pAddr); |
63be8feb AC |
1550 | break; |
1551 | case AccessLength_SEPTIBYTE : | |
01737f42 | 1552 | value = sim_core_read_misaligned_7 (cpu, NULL_CIA, |
82ea14fd | 1553 | read_map, pAddr); |
f319bab2 | 1554 | break; |
63be8feb | 1555 | case AccessLength_SEXTIBYTE : |
01737f42 | 1556 | value = sim_core_read_misaligned_6 (cpu, NULL_CIA, |
82ea14fd | 1557 | read_map, pAddr); |
f319bab2 | 1558 | break; |
63be8feb | 1559 | case AccessLength_QUINTIBYTE : |
01737f42 | 1560 | value = sim_core_read_misaligned_5 (cpu, NULL_CIA, |
82ea14fd | 1561 | read_map, pAddr); |
f319bab2 | 1562 | break; |
63be8feb | 1563 | case AccessLength_WORD : |
01737f42 | 1564 | value = sim_core_read_aligned_4 (cpu, NULL_CIA, |
82ea14fd | 1565 | read_map, pAddr); |
63be8feb AC |
1566 | break; |
1567 | case AccessLength_TRIPLEBYTE : | |
01737f42 | 1568 | value = sim_core_read_misaligned_3 (cpu, NULL_CIA, |
82ea14fd | 1569 | read_map, pAddr); |
f319bab2 | 1570 | break; |
63be8feb | 1571 | case AccessLength_HALFWORD : |
01737f42 | 1572 | value = sim_core_read_aligned_2 (cpu, NULL_CIA, |
82ea14fd | 1573 | read_map, pAddr); |
63be8feb AC |
1574 | break; |
1575 | case AccessLength_BYTE : | |
01737f42 | 1576 | value = sim_core_read_aligned_1 (cpu, NULL_CIA, |
82ea14fd | 1577 | read_map, pAddr); |
63be8feb AC |
1578 | break; |
1579 | default: | |
1580 | abort (); | |
1581 | } | |
1582 | ||
8bae0a0c | 1583 | #ifdef DEBUG |
63be8feb AC |
1584 | printf("DBG: LoadMemory() : (offset %d) : value = 0x%s%s\n", |
1585 | (int)(pAddr & LOADDRMASK),pr_uword64(value1),pr_uword64(value)); | |
8bae0a0c | 1586 | #endif /* DEBUG */ |
63be8feb AC |
1587 | |
1588 | /* See also store_memory. */ | |
1589 | if (AccessLength <= AccessLength_DOUBLEWORD) | |
1590 | { | |
1591 | if (BigEndianMem) | |
1592 | /* for big endian target, byte (pAddr&LOADDRMASK == 0) is | |
1593 | shifted to the most significant byte position. */ | |
1594 | value <<= (((7 - (pAddr & LOADDRMASK)) - AccessLength) * 8); | |
1595 | else | |
1596 | /* For little endian target, byte (pAddr&LOADDRMASK == 0) | |
1597 | is already in the correct postition. */ | |
1598 | value <<= ((pAddr & LOADDRMASK) * 8); | |
1599 | } | |
1600 | ||
8bae0a0c | 1601 | #ifdef DEBUG |
63be8feb AC |
1602 | printf("DBG: LoadMemory() : shifted value = 0x%s%s\n", |
1603 | pr_uword64(value1),pr_uword64(value)); | |
e871dd18 | 1604 | #endif /* DEBUG */ |
63be8feb | 1605 | |
525d929e AC |
1606 | *memvalp = value; |
1607 | if (memval1p) *memval1p = value1; | |
8bae0a0c JSC |
1608 | } |
1609 | ||
53b9417e | 1610 | |
50a2a691 AC |
1611 | /* Description from page A-23 of the "MIPS IV Instruction Set" manual |
1612 | (revision 3.1) */ | |
8bae0a0c JSC |
1613 | /* Store a value to memory. The specified data is stored into the |
1614 | physical location pAddr using the memory hierarchy (data caches and | |
1615 | main memory) as specified by the Cache Coherence Algorithm | |
1616 | (CCA). The MemElem contains the data for an aligned, fixed-width | |
1617 | memory element (word for 32-bit processors, doubleword for 64-bit | |
1618 | processors), though only the bytes that will actually be stored to | |
1619 | memory need to be valid. The low-order two (or three) bits of pAddr | |
1620 | and the AccessLength field indicates which of the bytes within the | |
1621 | MemElem data should actually be stored; only these bytes in memory | |
1622 | will be changed. */ | |
53b9417e | 1623 | |
18c64df6 | 1624 | void |
01737f42 AC |
1625 | store_memory (SIM_DESC sd, |
1626 | sim_cpu *cpu, | |
1627 | address_word cia, | |
1628 | int CCA, | |
1629 | int AccessLength, | |
1630 | uword64 MemElem, | |
1631 | uword64 MemElem1, /* High order 64 bits */ | |
1632 | address_word pAddr, | |
1633 | address_word vAddr) | |
8bae0a0c JSC |
1634 | { |
1635 | #ifdef DEBUG | |
63be8feb | 1636 | sim_io_printf(sd,"DBG: StoreMemory(%d,%d,0x%s,0x%s,0x%s,0x%s)\n",CCA,AccessLength,pr_uword64(MemElem),pr_uword64(MemElem1),pr_addr(pAddr),pr_addr(vAddr)); |
8bae0a0c | 1637 | #endif /* DEBUG */ |
63be8feb | 1638 | |
8bae0a0c JSC |
1639 | #if defined(WARN_MEM) |
1640 | if (CCA != uncached) | |
63be8feb | 1641 | sim_io_eprintf(sd,"StoreMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA); |
8bae0a0c | 1642 | #endif /* WARN_MEM */ |
63be8feb AC |
1643 | |
1644 | if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK) | |
1645 | sim_io_error(sd,"AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",AccessLength,(LOADDRMASK + 1)<<2,pr_addr(pAddr)); | |
1646 | ||
8bae0a0c | 1647 | #if defined(TRACE) |
01737f42 | 1648 | dotrace (SD, CPU, tracefh,1,(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"store"); |
8bae0a0c | 1649 | #endif /* TRACE */ |
63be8feb | 1650 | |
8bae0a0c | 1651 | #ifdef DEBUG |
63be8feb | 1652 | printf("DBG: StoreMemory: offset = %d MemElem = 0x%s%s\n",(unsigned int)(pAddr & LOADDRMASK),pr_uword64(MemElem1),pr_uword64(MemElem)); |
8bae0a0c | 1653 | #endif /* DEBUG */ |
63be8feb AC |
1654 | |
1655 | /* See also load_memory */ | |
1656 | if (AccessLength <= AccessLength_DOUBLEWORD) | |
1657 | { | |
1658 | if (BigEndianMem) | |
1659 | /* for big endian target, byte (pAddr&LOADDRMASK == 0) is | |
1660 | shifted to the most significant byte position. */ | |
1661 | MemElem >>= (((7 - (pAddr & LOADDRMASK)) - AccessLength) * 8); | |
1662 | else | |
1663 | /* For little endian target, byte (pAddr&LOADDRMASK == 0) | |
1664 | is already in the correct postition. */ | |
1665 | MemElem >>= ((pAddr & LOADDRMASK) * 8); | |
1666 | } | |
1667 | ||
8bae0a0c | 1668 | #ifdef DEBUG |
63be8feb | 1669 | printf("DBG: StoreMemory: shift = %d MemElem = 0x%s%s\n",shift,pr_uword64(MemElem1),pr_uword64(MemElem)); |
8bae0a0c | 1670 | #endif /* DEBUG */ |
63be8feb AC |
1671 | |
1672 | switch (AccessLength) | |
1673 | { | |
1674 | case AccessLength_QUADWORD : | |
1675 | { | |
1676 | unsigned_16 val = U16_8 (MemElem1, MemElem); | |
82ea14fd | 1677 | sim_core_write_aligned_16 (cpu, NULL_CIA, write_map, pAddr, val); |
63be8feb | 1678 | break; |
8bae0a0c | 1679 | } |
63be8feb | 1680 | case AccessLength_DOUBLEWORD : |
01737f42 | 1681 | sim_core_write_aligned_8 (cpu, NULL_CIA, |
82ea14fd | 1682 | write_map, pAddr, MemElem); |
63be8feb AC |
1683 | break; |
1684 | case AccessLength_SEPTIBYTE : | |
01737f42 | 1685 | sim_core_write_misaligned_7 (cpu, NULL_CIA, |
82ea14fd | 1686 | write_map, pAddr, MemElem); |
63be8feb AC |
1687 | break; |
1688 | case AccessLength_SEXTIBYTE : | |
01737f42 | 1689 | sim_core_write_misaligned_6 (cpu, NULL_CIA, |
82ea14fd | 1690 | write_map, pAddr, MemElem); |
63be8feb AC |
1691 | break; |
1692 | case AccessLength_QUINTIBYTE : | |
01737f42 | 1693 | sim_core_write_misaligned_5 (cpu, NULL_CIA, |
82ea14fd | 1694 | write_map, pAddr, MemElem); |
63be8feb AC |
1695 | break; |
1696 | case AccessLength_WORD : | |
01737f42 | 1697 | sim_core_write_aligned_4 (cpu, NULL_CIA, |
82ea14fd | 1698 | write_map, pAddr, MemElem); |
63be8feb AC |
1699 | break; |
1700 | case AccessLength_TRIPLEBYTE : | |
01737f42 | 1701 | sim_core_write_misaligned_3 (cpu, NULL_CIA, |
82ea14fd | 1702 | write_map, pAddr, MemElem); |
63be8feb AC |
1703 | break; |
1704 | case AccessLength_HALFWORD : | |
01737f42 | 1705 | sim_core_write_aligned_2 (cpu, NULL_CIA, |
82ea14fd | 1706 | write_map, pAddr, MemElem); |
63be8feb AC |
1707 | break; |
1708 | case AccessLength_BYTE : | |
01737f42 | 1709 | sim_core_write_aligned_1 (cpu, NULL_CIA, |
82ea14fd | 1710 | write_map, pAddr, MemElem); |
63be8feb AC |
1711 | break; |
1712 | default: | |
1713 | abort (); | |
1714 | } | |
1715 | ||
8bae0a0c JSC |
1716 | return; |
1717 | } | |
1718 | ||
53b9417e | 1719 | |
dad6f1f3 | 1720 | unsigned32 |
7ce8b917 | 1721 | ifetch32 (SIM_DESC sd, |
01737f42 | 1722 | sim_cpu *cpu, |
7ce8b917 AC |
1723 | address_word cia, |
1724 | address_word vaddr) | |
dad6f1f3 AC |
1725 | { |
1726 | /* Copy the action of the LW instruction */ | |
1727 | address_word reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0); | |
1728 | address_word bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0); | |
1729 | unsigned64 value; | |
1730 | address_word paddr; | |
1731 | unsigned32 instruction; | |
1732 | unsigned byte; | |
1733 | int cca; | |
1734 | AddressTranslation (vaddr, isINSTRUCTION, isLOAD, &paddr, &cca, isTARGET, isREAL); | |
1735 | paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2))); | |
37379a25 AC |
1736 | LoadMemory (&value, NULL, cca, AccessLength_WORD, paddr, vaddr, isINSTRUCTION, isREAL); |
1737 | byte = ((vaddr & LOADDRMASK) ^ (bigend << 2)); | |
1738 | instruction = ((value >> (8 * byte)) & 0xFFFFFFFF); | |
1739 | return instruction; | |
1740 | } | |
1741 | ||
1742 | ||
1743 | unsigned16 | |
1744 | ifetch16 (SIM_DESC sd, | |
1745 | sim_cpu *cpu, | |
1746 | address_word cia, | |
1747 | address_word vaddr) | |
1748 | { | |
1749 | /* Copy the action of the LW instruction */ | |
1750 | address_word reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0); | |
1751 | address_word bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0); | |
1752 | unsigned64 value; | |
1753 | address_word paddr; | |
1754 | unsigned16 instruction; | |
1755 | unsigned byte; | |
1756 | int cca; | |
1757 | AddressTranslation (vaddr, isINSTRUCTION, isLOAD, &paddr, &cca, isTARGET, isREAL); | |
1758 | paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2))); | |
dad6f1f3 AC |
1759 | LoadMemory (&value, NULL, cca, AccessLength_WORD, paddr, vaddr, isINSTRUCTION, isREAL); |
1760 | byte = ((vaddr & LOADDRMASK) ^ (bigend << 2)); | |
1761 | instruction = ((value >> (8 * byte)) & 0xFFFFFFFF); | |
1762 | return instruction; | |
1763 | } | |
1764 | ||
1765 | ||
8bae0a0c JSC |
1766 | /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */ |
1767 | /* Order loads and stores to synchronise shared memory. Perform the | |
1768 | action necessary to make the effects of groups of synchronizable | |
1769 | loads and stores indicated by stype occur in the same order for all | |
1770 | processors. */ | |
ea985d24 | 1771 | void |
01737f42 AC |
1772 | sync_operation (SIM_DESC sd, |
1773 | sim_cpu *cpu, | |
1774 | address_word cia, | |
1775 | int stype) | |
8bae0a0c JSC |
1776 | { |
1777 | #ifdef DEBUG | |
18c64df6 | 1778 | sim_io_printf(sd,"SyncOperation(%d) : TODO\n",stype); |
8bae0a0c JSC |
1779 | #endif /* DEBUG */ |
1780 | return; | |
1781 | } | |
1782 | ||
1783 | /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */ | |
1784 | /* Signal an exception condition. This will result in an exception | |
1785 | that aborts the instruction. The instruction operation pseudocode | |
50a2a691 | 1786 | will never see a return from this function call. */ |
2e61a3ad | 1787 | |
18c64df6 | 1788 | void |
7ce8b917 | 1789 | signal_exception (SIM_DESC sd, |
01737f42 | 1790 | sim_cpu *cpu, |
7ce8b917 AC |
1791 | address_word cia, |
1792 | int exception,...) | |
8bae0a0c | 1793 | { |
56e7c849 | 1794 | int vector; |
6eedf3f4 MA |
1795 | |
1796 | #ifdef DEBUG | |
95469ceb | 1797 | sim_io_printf(sd,"DBG: SignalException(%d) PC = 0x%s\n",exception,pr_addr(cia)); |
6eedf3f4 MA |
1798 | #endif /* DEBUG */ |
1799 | ||
8bae0a0c JSC |
1800 | /* Ensure that any active atomic read/modify/write operation will fail: */ |
1801 | LLBIT = 0; | |
1802 | ||
1803 | switch (exception) { | |
1804 | /* TODO: For testing purposes I have been ignoring TRAPs. In | |
1805 | reality we should either simulate them, or allow the user to | |
6eedf3f4 MA |
1806 | ignore them at run-time. |
1807 | Same for SYSCALL */ | |
8bae0a0c | 1808 | case Trap : |
95469ceb | 1809 | sim_io_eprintf(sd,"Ignoring instruction TRAP (PC 0x%s)\n",pr_addr(cia)); |
8bae0a0c JSC |
1810 | break; |
1811 | ||
6eedf3f4 MA |
1812 | case SystemCall : |
1813 | { | |
1814 | va_list ap; | |
1815 | unsigned int instruction; | |
1816 | unsigned int code; | |
1817 | ||
1818 | va_start(ap,exception); | |
1819 | instruction = va_arg(ap,unsigned int); | |
1820 | va_end(ap); | |
1821 | ||
1822 | code = (instruction >> 6) & 0xFFFFF; | |
1823 | ||
18c64df6 | 1824 | sim_io_eprintf(sd,"Ignoring instruction `syscall %d' (PC 0x%s)\n", |
95469ceb | 1825 | code, pr_addr(cia)); |
6eedf3f4 MA |
1826 | } |
1827 | break; | |
1828 | ||
1829 | case DebugBreakPoint : | |
1830 | if (! (Debug & Debug_DM)) | |
1831 | { | |
1832 | if (INDELAYSLOT()) | |
1833 | { | |
1834 | CANCELDELAYSLOT(); | |
1835 | ||
1836 | Debug |= Debug_DBD; /* signaled from within in delay slot */ | |
95469ceb | 1837 | DEPC = cia - 4; /* reference the branch instruction */ |
6eedf3f4 MA |
1838 | } |
1839 | else | |
1840 | { | |
1841 | Debug &= ~Debug_DBD; /* not signaled from within a delay slot */ | |
95469ceb | 1842 | DEPC = cia; |
6eedf3f4 MA |
1843 | } |
1844 | ||
1845 | Debug |= Debug_DM; /* in debugging mode */ | |
1846 | Debug |= Debug_DBp; /* raising a DBp exception */ | |
1847 | PC = 0xBFC00200; | |
01737f42 | 1848 | sim_engine_restart (SD, CPU, NULL, NULL_CIA); |
6eedf3f4 MA |
1849 | } |
1850 | break; | |
1851 | ||
8bae0a0c JSC |
1852 | case ReservedInstruction : |
1853 | { | |
1854 | va_list ap; | |
1855 | unsigned int instruction; | |
1856 | va_start(ap,exception); | |
1857 | instruction = va_arg(ap,unsigned int); | |
1858 | va_end(ap); | |
1859 | /* Provide simple monitor support using ReservedInstruction | |
1860 | exceptions. The following code simulates the fixed vector | |
1861 | entry points into the IDT monitor by causing a simulator | |
1862 | trap, performing the monitor operation, and returning to | |
1863 | the address held in the $ra register (standard PCS return | |
1864 | address). This means we only need to pre-load the vector | |
1865 | space with suitable instruction values. For systems were | |
1866 | actual trap instructions are used, we would not need to | |
1867 | perform this magic. */ | |
7ce8b917 AC |
1868 | if ((instruction & RSVD_INSTRUCTION_MASK) == RSVD_INSTRUCTION) |
1869 | { | |
01737f42 | 1870 | sim_monitor (SD, CPU, cia, ((instruction >> RSVD_INSTRUCTION_ARG_SHIFT) & RSVD_INSTRUCTION_ARG_MASK) ); |
7ce8b917 AC |
1871 | /* NOTE: This assumes that a branch-and-link style |
1872 | instruction was used to enter the vector (which is the | |
1873 | case with the current IDT monitor). */ | |
01737f42 | 1874 | sim_engine_restart (SD, CPU, NULL, RA); |
7ce8b917 | 1875 | } |
7e6c297e ILT |
1876 | /* Look for the mips16 entry and exit instructions, and |
1877 | simulate a handler for them. */ | |
95469ceb | 1878 | else if ((cia & 1) != 0 |
7e6c297e | 1879 | && (instruction & 0xf81f) == 0xe809 |
7ce8b917 AC |
1880 | && (instruction & 0x0c0) != 0x0c0) |
1881 | { | |
01737f42 | 1882 | mips16_entry (SD, CPU, cia, instruction); |
7ce8b917 AC |
1883 | sim_engine_restart (sd, NULL, NULL, NULL_CIA); |
1884 | } | |
1885 | /* else fall through to normal exception processing */ | |
95469ceb | 1886 | sim_io_eprintf(sd,"ReservedInstruction 0x%08X at PC = 0x%s\n",instruction,pr_addr(cia)); |
8bae0a0c JSC |
1887 | } |
1888 | ||
05d1322f | 1889 | case BreakPoint: |
e3d12c65 | 1890 | #ifdef DEBUG |
95469ceb | 1891 | sim_io_printf(sd,"DBG: SignalException(%d) PC = 0x%s\n",exception,pr_addr(cia)); |
8bae0a0c | 1892 | #endif /* DEBUG */ |
05d1322f JL |
1893 | /* Keep a copy of the current A0 in-case this is the program exit |
1894 | breakpoint: */ | |
1895 | { | |
1896 | va_list ap; | |
1897 | unsigned int instruction; | |
1898 | va_start(ap,exception); | |
1899 | instruction = va_arg(ap,unsigned int); | |
1900 | va_end(ap); | |
1901 | /* Check for our special terminating BREAK: */ | |
1902 | if ((instruction & 0x03FFFFC0) == 0x03ff0000) { | |
01737f42 | 1903 | sim_engine_halt (SD, CPU, NULL, cia, |
05d1322f JL |
1904 | sim_exited, (unsigned int)(A0 & 0xFFFFFFFF)); |
1905 | } | |
1906 | } | |
0c2c5f61 | 1907 | if (STATE & simDELAYSLOT) |
95469ceb | 1908 | PC = cia - 4; /* reference the branch instruction */ |
05d1322f | 1909 | else |
95469ceb | 1910 | PC = cia; |
01737f42 | 1911 | sim_engine_halt (SD, CPU, NULL, cia, |
232156de | 1912 | sim_stopped, SIM_SIGTRAP); |
05d1322f JL |
1913 | |
1914 | default: | |
8bae0a0c JSC |
1915 | /* Store exception code into current exception id variable (used |
1916 | by exit code): */ | |
1917 | ||
1918 | /* TODO: If not simulating exceptions then stop the simulator | |
1919 | execution. At the moment we always stop the simulation. */ | |
e3d12c65 | 1920 | |
56e7c849 AC |
1921 | /* See figure 5-17 for an outline of the code below */ |
1922 | if (! (SR & status_EXL)) | |
1923 | { | |
1924 | CAUSE = (exception << 2); | |
0c2c5f61 | 1925 | if (STATE & simDELAYSLOT) |
56e7c849 | 1926 | { |
0c2c5f61 | 1927 | STATE &= ~simDELAYSLOT; |
56e7c849 | 1928 | CAUSE |= cause_BD; |
95469ceb | 1929 | EPC = (cia - 4); /* reference the branch instruction */ |
56e7c849 AC |
1930 | } |
1931 | else | |
95469ceb | 1932 | EPC = cia; |
56e7c849 AC |
1933 | /* FIXME: TLB et.al. */ |
1934 | vector = 0x180; | |
1935 | } | |
1936 | else | |
1937 | { | |
05d1322f | 1938 | CAUSE = (exception << 2); |
56e7c849 AC |
1939 | vector = 0x180; |
1940 | } | |
1941 | SR |= status_EXL; | |
e3d12c65 DE |
1942 | /* Store exception code into current exception id variable (used |
1943 | by exit code): */ | |
56e7c849 AC |
1944 | if (SR & status_BEV) |
1945 | PC = (signed)0xBFC00200 + 0x180; | |
1946 | else | |
1947 | PC = (signed)0x80000000 + 0x180; | |
1948 | ||
50a2a691 AC |
1949 | switch ((CAUSE >> 2) & 0x1F) |
1950 | { | |
1951 | case Interrupt: | |
56e7c849 AC |
1952 | /* Interrupts arrive during event processing, no need to |
1953 | restart */ | |
1954 | return; | |
50a2a691 AC |
1955 | |
1956 | case TLBModification: | |
1957 | case TLBLoad: | |
1958 | case TLBStore: | |
1959 | case AddressLoad: | |
1960 | case AddressStore: | |
1961 | case InstructionFetch: | |
1962 | case DataReference: | |
56e7c849 AC |
1963 | /* The following is so that the simulator will continue from the |
1964 | exception address on breakpoint operations. */ | |
1965 | PC = EPC; | |
01737f42 | 1966 | sim_engine_halt (SD, CPU, NULL, NULL_CIA, |
232156de | 1967 | sim_stopped, SIM_SIGBUS); |
50a2a691 AC |
1968 | |
1969 | case ReservedInstruction: | |
1970 | case CoProcessorUnusable: | |
56e7c849 | 1971 | PC = EPC; |
01737f42 | 1972 | sim_engine_halt (SD, CPU, NULL, NULL_CIA, |
232156de | 1973 | sim_stopped, SIM_SIGILL); |
50a2a691 AC |
1974 | |
1975 | case IntegerOverflow: | |
1976 | case FPE: | |
01737f42 | 1977 | sim_engine_halt (SD, CPU, NULL, NULL_CIA, |
232156de | 1978 | sim_stopped, SIM_SIGFPE); |
50a2a691 AC |
1979 | |
1980 | case Trap: | |
1981 | case Watch: | |
1982 | case SystemCall: | |
56e7c849 | 1983 | PC = EPC; |
01737f42 | 1984 | sim_engine_halt (SD, CPU, NULL, NULL_CIA, |
232156de | 1985 | sim_stopped, SIM_SIGTRAP); |
50a2a691 | 1986 | |
05d1322f JL |
1987 | case BreakPoint: |
1988 | PC = EPC; | |
01737f42 | 1989 | sim_engine_abort (SD, CPU, NULL_CIA, |
05d1322f JL |
1990 | "FATAL: Should not encounter a breakpoint\n"); |
1991 | ||
50a2a691 | 1992 | default : /* Unknown internal exception */ |
56e7c849 | 1993 | PC = EPC; |
01737f42 | 1994 | sim_engine_halt (SD, CPU, NULL, NULL_CIA, |
232156de | 1995 | sim_stopped, SIM_SIGABRT); |
50a2a691 AC |
1996 | |
1997 | } | |
8bae0a0c JSC |
1998 | |
1999 | case SimulatorFault: | |
2000 | { | |
2001 | va_list ap; | |
2002 | char *msg; | |
2003 | va_start(ap,exception); | |
2004 | msg = va_arg(ap,char *); | |
50a2a691 | 2005 | va_end(ap); |
01737f42 | 2006 | sim_engine_abort (SD, CPU, NULL_CIA, |
2e61a3ad | 2007 | "FATAL: Simulator error \"%s\"\n",msg); |
8bae0a0c | 2008 | } |
8bae0a0c JSC |
2009 | } |
2010 | ||
2011 | return; | |
2012 | } | |
2013 | ||
2014 | #if defined(WARN_RESULT) | |
2015 | /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */ | |
2016 | /* This function indicates that the result of the operation is | |
2017 | undefined. However, this should not affect the instruction | |
2018 | stream. All that is meant to happen is that the destination | |
2019 | register is set to an undefined result. To keep the simulator | |
2020 | simple, we just don't bother updating the destination register, so | |
2021 | the overall result will be undefined. If desired we can stop the | |
2022 | simulator by raising a pseudo-exception. */ | |
95469ceb | 2023 | #define UndefinedResult() undefined_result (sd,cia) |
8bae0a0c | 2024 | static void |
95469ceb AC |
2025 | undefined_result(sd,cia) |
2026 | SIM_DESC sd; | |
2027 | address_word cia; | |
8bae0a0c | 2028 | { |
95469ceb | 2029 | sim_io_eprintf(sd,"UndefinedResult: PC = 0x%s\n",pr_addr(cia)); |
8bae0a0c JSC |
2030 | #if 0 /* Disabled for the moment, since it actually happens a lot at the moment. */ |
2031 | state |= simSTOP; | |
2032 | #endif | |
2033 | return; | |
2034 | } | |
2035 | #endif /* WARN_RESULT */ | |
2036 | ||
18c64df6 | 2037 | void |
01737f42 AC |
2038 | cache_op (SIM_DESC sd, |
2039 | sim_cpu *cpu, | |
2040 | address_word cia, | |
2041 | int op, | |
2042 | address_word pAddr, | |
2043 | address_word vAddr, | |
2044 | unsigned int instruction) | |
8bae0a0c | 2045 | { |
f24b7b69 JSC |
2046 | #if 1 /* stop warning message being displayed (we should really just remove the code) */ |
2047 | static int icache_warning = 1; | |
2048 | static int dcache_warning = 1; | |
2049 | #else | |
a9f7253f JSC |
2050 | static int icache_warning = 0; |
2051 | static int dcache_warning = 0; | |
f24b7b69 | 2052 | #endif |
a9f7253f | 2053 | |
8bae0a0c JSC |
2054 | /* If CP0 is not useable (User or Supervisor mode) and the CP0 |
2055 | enable bit in the Status Register is clear - a coprocessor | |
2056 | unusable exception is taken. */ | |
a9f7253f | 2057 | #if 0 |
95469ceb | 2058 | sim_io_printf(sd,"TODO: Cache availability checking (PC = 0x%s)\n",pr_addr(cia)); |
a9f7253f | 2059 | #endif |
8bae0a0c JSC |
2060 | |
2061 | switch (op & 0x3) { | |
2062 | case 0: /* instruction cache */ | |
2063 | switch (op >> 2) { | |
2064 | case 0: /* Index Invalidate */ | |
2065 | case 1: /* Index Load Tag */ | |
2066 | case 2: /* Index Store Tag */ | |
2067 | case 4: /* Hit Invalidate */ | |
2068 | case 5: /* Fill */ | |
2069 | case 6: /* Hit Writeback */ | |
a9f7253f JSC |
2070 | if (!icache_warning) |
2071 | { | |
18c64df6 | 2072 | sim_io_eprintf(sd,"Instruction CACHE operation %d to be coded\n",(op >> 2)); |
a9f7253f JSC |
2073 | icache_warning = 1; |
2074 | } | |
8bae0a0c JSC |
2075 | break; |
2076 | ||
2077 | default: | |
2078 | SignalException(ReservedInstruction,instruction); | |
2079 | break; | |
2080 | } | |
2081 | break; | |
2082 | ||
2083 | case 1: /* data cache */ | |
2084 | switch (op >> 2) { | |
2085 | case 0: /* Index Writeback Invalidate */ | |
2086 | case 1: /* Index Load Tag */ | |
2087 | case 2: /* Index Store Tag */ | |
2088 | case 3: /* Create Dirty */ | |
2089 | case 4: /* Hit Invalidate */ | |
2090 | case 5: /* Hit Writeback Invalidate */ | |
2091 | case 6: /* Hit Writeback */ | |
a9f7253f JSC |
2092 | if (!dcache_warning) |
2093 | { | |
18c64df6 | 2094 | sim_io_eprintf(sd,"Data CACHE operation %d to be coded\n",(op >> 2)); |
a9f7253f JSC |
2095 | dcache_warning = 1; |
2096 | } | |
8bae0a0c JSC |
2097 | break; |
2098 | ||
2099 | default: | |
2100 | SignalException(ReservedInstruction,instruction); | |
2101 | break; | |
2102 | } | |
2103 | break; | |
2104 | ||
2105 | default: /* unrecognised cache ID */ | |
2106 | SignalException(ReservedInstruction,instruction); | |
2107 | break; | |
2108 | } | |
2109 | ||
2110 | return; | |
2111 | } | |
2112 | ||
2113 | /*-- FPU support routines ---------------------------------------------------*/ | |
2114 | ||
8bae0a0c JSC |
2115 | /* Numbers are held in normalized form. The SINGLE and DOUBLE binary |
2116 | formats conform to ANSI/IEEE Std 754-1985. */ | |
2117 | /* SINGLE precision floating: | |
2118 | * seeeeeeeefffffffffffffffffffffff | |
2119 | * s = 1bit = sign | |
2120 | * e = 8bits = exponent | |
2121 | * f = 23bits = fraction | |
2122 | */ | |
2123 | /* SINGLE precision fixed: | |
2124 | * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiii | |
2125 | * s = 1bit = sign | |
2126 | * i = 31bits = integer | |
2127 | */ | |
2128 | /* DOUBLE precision floating: | |
2129 | * seeeeeeeeeeeffffffffffffffffffffffffffffffffffffffffffffffffffff | |
2130 | * s = 1bit = sign | |
2131 | * e = 11bits = exponent | |
2132 | * f = 52bits = fraction | |
2133 | */ | |
2134 | /* DOUBLE precision fixed: | |
2135 | * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii | |
2136 | * s = 1bit = sign | |
2137 | * i = 63bits = integer | |
2138 | */ | |
2139 | ||
2140 | /* Extract sign-bit: */ | |
2141 | #define FP_S_s(v) (((v) & ((unsigned)1 << 31)) ? 1 : 0) | |
e871dd18 | 2142 | #define FP_D_s(v) (((v) & ((uword64)1 << 63)) ? 1 : 0) |
8bae0a0c JSC |
2143 | /* Extract biased exponent: */ |
2144 | #define FP_S_be(v) (((v) >> 23) & 0xFF) | |
2145 | #define FP_D_be(v) (((v) >> 52) & 0x7FF) | |
2146 | /* Extract unbiased Exponent: */ | |
2147 | #define FP_S_e(v) (FP_S_be(v) - 0x7F) | |
2148 | #define FP_D_e(v) (FP_D_be(v) - 0x3FF) | |
2149 | /* Extract complete fraction field: */ | |
2150 | #define FP_S_f(v) ((v) & ~((unsigned)0x1FF << 23)) | |
e871dd18 | 2151 | #define FP_D_f(v) ((v) & ~((uword64)0xFFF << 52)) |
8bae0a0c JSC |
2152 | /* Extract numbered fraction bit: */ |
2153 | #define FP_S_fb(b,v) (((v) & (1 << (23 - (b)))) ? 1 : 0) | |
2154 | #define FP_D_fb(b,v) (((v) & (1 << (52 - (b)))) ? 1 : 0) | |
2155 | ||
2156 | /* Explicit QNaN values used when value required: */ | |
2157 | #define FPQNaN_SINGLE (0x7FBFFFFF) | |
2158 | #define FPQNaN_WORD (0x7FFFFFFF) | |
e871dd18 JSC |
2159 | #define FPQNaN_DOUBLE (((uword64)0x7FF7FFFF << 32) | 0xFFFFFFFF) |
2160 | #define FPQNaN_LONG (((uword64)0x7FFFFFFF << 32) | 0xFFFFFFFF) | |
8bae0a0c JSC |
2161 | |
2162 | /* Explicit Infinity values used when required: */ | |
2163 | #define FPINF_SINGLE (0x7F800000) | |
e871dd18 | 2164 | #define FPINF_DOUBLE (((uword64)0x7FF00000 << 32) | 0x00000000) |
8bae0a0c JSC |
2165 | |
2166 | #if 1 /* def DEBUG */ | |
2167 | #define RMMODE(v) (((v) == FP_RM_NEAREST) ? "Round" : (((v) == FP_RM_TOZERO) ? "Trunc" : (((v) == FP_RM_TOPINF) ? "Ceil" : "Floor"))) | |
2168 | #define DOFMT(v) (((v) == fmt_single) ? "single" : (((v) == fmt_double) ? "double" : (((v) == fmt_word) ? "word" : (((v) == fmt_long) ? "long" : (((v) == fmt_unknown) ? "<unknown>" : (((v) == fmt_uninterpreted) ? "<uninterpreted>" : "<format error>")))))) | |
2169 | #endif /* DEBUG */ | |
2170 | ||
18c64df6 | 2171 | uword64 |
01737f42 AC |
2172 | value_fpr (SIM_DESC sd, |
2173 | sim_cpu *cpu, | |
2174 | address_word cia, | |
2175 | int fpr, | |
2176 | FP_formats fmt) | |
8bae0a0c | 2177 | { |
50a2a691 | 2178 | uword64 value = 0; |
8bae0a0c JSC |
2179 | int err = 0; |
2180 | ||
2181 | /* Treat unused register values, as fixed-point 64bit values: */ | |
2182 | if ((fmt == fmt_uninterpreted) || (fmt == fmt_unknown)) | |
2183 | #if 1 | |
2184 | /* If request to read data as "uninterpreted", then use the current | |
2185 | encoding: */ | |
0c2c5f61 | 2186 | fmt = FPR_STATE[fpr]; |
8bae0a0c JSC |
2187 | #else |
2188 | fmt = fmt_long; | |
2189 | #endif | |
2190 | ||
2191 | /* For values not yet accessed, set to the desired format: */ | |
0c2c5f61 AC |
2192 | if (FPR_STATE[fpr] == fmt_uninterpreted) { |
2193 | FPR_STATE[fpr] = fmt; | |
8bae0a0c JSC |
2194 | #ifdef DEBUG |
2195 | printf("DBG: Register %d was fmt_uninterpreted. Now %s\n",fpr,DOFMT(fmt)); | |
2196 | #endif /* DEBUG */ | |
2197 | } | |
0c2c5f61 | 2198 | if (fmt != FPR_STATE[fpr]) { |
95469ceb | 2199 | sim_io_eprintf(sd,"FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",fpr,DOFMT(FPR_STATE[fpr]),DOFMT(fmt),pr_addr(cia)); |
0c2c5f61 | 2200 | FPR_STATE[fpr] = fmt_unknown; |
8bae0a0c JSC |
2201 | } |
2202 | ||
0c2c5f61 | 2203 | if (FPR_STATE[fpr] == fmt_unknown) { |
8bae0a0c JSC |
2204 | /* Set QNaN value: */ |
2205 | switch (fmt) { | |
2206 | case fmt_single: | |
2207 | value = FPQNaN_SINGLE; | |
2208 | break; | |
2209 | ||
2210 | case fmt_double: | |
2211 | value = FPQNaN_DOUBLE; | |
2212 | break; | |
2213 | ||
2214 | case fmt_word: | |
2215 | value = FPQNaN_WORD; | |
2216 | break; | |
2217 | ||
2218 | case fmt_long: | |
2219 | value = FPQNaN_LONG; | |
2220 | break; | |
2221 | ||
2222 | default: | |
2223 | err = -1; | |
2224 | break; | |
2225 | } | |
2226 | } else if (SizeFGR() == 64) { | |
2227 | switch (fmt) { | |
2228 | case fmt_single: | |
2229 | case fmt_word: | |
2230 | value = (FGR[fpr] & 0xFFFFFFFF); | |
2231 | break; | |
2232 | ||
2233 | case fmt_uninterpreted: | |
2234 | case fmt_double: | |
2235 | case fmt_long: | |
2236 | value = FGR[fpr]; | |
2237 | break; | |
2238 | ||
2239 | default : | |
2240 | err = -1; | |
2241 | break; | |
2242 | } | |
da0bce9c | 2243 | } else { |
8bae0a0c JSC |
2244 | switch (fmt) { |
2245 | case fmt_single: | |
2246 | case fmt_word: | |
2247 | value = (FGR[fpr] & 0xFFFFFFFF); | |
2248 | break; | |
2249 | ||
2250 | case fmt_uninterpreted: | |
2251 | case fmt_double: | |
2252 | case fmt_long: | |
da0bce9c ILT |
2253 | if ((fpr & 1) == 0) { /* even registers only */ |
2254 | value = ((((uword64)FGR[fpr+1]) << 32) | (FGR[fpr] & 0xFFFFFFFF)); | |
2255 | } else { | |
18c64df6 | 2256 | SignalException(ReservedInstruction,0); |
da0bce9c | 2257 | } |
8bae0a0c JSC |
2258 | break; |
2259 | ||
2260 | default : | |
2261 | err = -1; | |
2262 | break; | |
2263 | } | |
2264 | } | |
2265 | ||
2266 | if (err) | |
18c64df6 | 2267 | SignalExceptionSimulatorFault ("Unrecognised FP format in ValueFPR()"); |
8bae0a0c JSC |
2268 | |
2269 | #ifdef DEBUG | |
95469ceb | 2270 | printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(cia),SizeFGR()); |
8bae0a0c JSC |
2271 | #endif /* DEBUG */ |
2272 | ||
2273 | return(value); | |
2274 | } | |
2275 | ||
18c64df6 | 2276 | void |
01737f42 AC |
2277 | store_fpr (SIM_DESC sd, |
2278 | sim_cpu *cpu, | |
2279 | address_word cia, | |
2280 | int fpr, | |
2281 | FP_formats fmt, | |
2282 | uword64 value) | |
8bae0a0c JSC |
2283 | { |
2284 | int err = 0; | |
2285 | ||
2286 | #ifdef DEBUG | |
95469ceb | 2287 | printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(cia),SizeFGR()); |
8bae0a0c JSC |
2288 | #endif /* DEBUG */ |
2289 | ||
2290 | if (SizeFGR() == 64) { | |
2291 | switch (fmt) { | |
a09a30d2 AC |
2292 | case fmt_uninterpreted_32: |
2293 | fmt = fmt_uninterpreted; | |
8bae0a0c JSC |
2294 | case fmt_single : |
2295 | case fmt_word : | |
e871dd18 | 2296 | FGR[fpr] = (((uword64)0xDEADC0DE << 32) | (value & 0xFFFFFFFF)); |
0c2c5f61 | 2297 | FPR_STATE[fpr] = fmt; |
8bae0a0c JSC |
2298 | break; |
2299 | ||
a09a30d2 AC |
2300 | case fmt_uninterpreted_64: |
2301 | fmt = fmt_uninterpreted; | |
8bae0a0c JSC |
2302 | case fmt_uninterpreted: |
2303 | case fmt_double : | |
2304 | case fmt_long : | |
2305 | FGR[fpr] = value; | |
0c2c5f61 | 2306 | FPR_STATE[fpr] = fmt; |
8bae0a0c JSC |
2307 | break; |
2308 | ||
2309 | default : | |
0c2c5f61 | 2310 | FPR_STATE[fpr] = fmt_unknown; |
8bae0a0c JSC |
2311 | err = -1; |
2312 | break; | |
2313 | } | |
da0bce9c | 2314 | } else { |
8bae0a0c | 2315 | switch (fmt) { |
a09a30d2 AC |
2316 | case fmt_uninterpreted_32: |
2317 | fmt = fmt_uninterpreted; | |
8bae0a0c JSC |
2318 | case fmt_single : |
2319 | case fmt_word : | |
8bae0a0c | 2320 | FGR[fpr] = (value & 0xFFFFFFFF); |
0c2c5f61 | 2321 | FPR_STATE[fpr] = fmt; |
8bae0a0c JSC |
2322 | break; |
2323 | ||
a09a30d2 AC |
2324 | case fmt_uninterpreted_64: |
2325 | fmt = fmt_uninterpreted; | |
8bae0a0c JSC |
2326 | case fmt_uninterpreted: |
2327 | case fmt_double : | |
2328 | case fmt_long : | |
da0bce9c ILT |
2329 | if ((fpr & 1) == 0) { /* even register number only */ |
2330 | FGR[fpr+1] = (value >> 32); | |
2331 | FGR[fpr] = (value & 0xFFFFFFFF); | |
0c2c5f61 AC |
2332 | FPR_STATE[fpr + 1] = fmt; |
2333 | FPR_STATE[fpr] = fmt; | |
da0bce9c | 2334 | } else { |
0c2c5f61 AC |
2335 | FPR_STATE[fpr] = fmt_unknown; |
2336 | FPR_STATE[fpr + 1] = fmt_unknown; | |
18c64df6 | 2337 | SignalException(ReservedInstruction,0); |
da0bce9c | 2338 | } |
8bae0a0c JSC |
2339 | break; |
2340 | ||
2341 | default : | |
0c2c5f61 | 2342 | FPR_STATE[fpr] = fmt_unknown; |
8bae0a0c JSC |
2343 | err = -1; |
2344 | break; | |
2345 | } | |
e871dd18 JSC |
2346 | } |
2347 | #if defined(WARN_RESULT) | |
2348 | else | |
2349 | UndefinedResult(); | |
2350 | #endif /* WARN_RESULT */ | |
8bae0a0c JSC |
2351 | |
2352 | if (err) | |
18c64df6 | 2353 | SignalExceptionSimulatorFault ("Unrecognised FP format in StoreFPR()"); |
8bae0a0c JSC |
2354 | |
2355 | #ifdef DEBUG | |
53b9417e | 2356 | printf("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",fpr,pr_addr(FGR[fpr]),DOFMT(fmt)); |
8bae0a0c JSC |
2357 | #endif /* DEBUG */ |
2358 | ||
2359 | return; | |
2360 | } | |
2361 | ||
18c64df6 | 2362 | int |
8bae0a0c | 2363 | NaN(op,fmt) |
e871dd18 | 2364 | uword64 op; |
8bae0a0c JSC |
2365 | FP_formats fmt; |
2366 | { | |
2367 | int boolean = 0; | |
8bae0a0c JSC |
2368 | switch (fmt) { |
2369 | case fmt_single: | |
8bae0a0c | 2370 | case fmt_word: |
76ef4165 FL |
2371 | { |
2372 | sim_fpu wop; | |
2373 | sim_fpu_32to (&wop, op); | |
2374 | boolean = sim_fpu_is_nan (&wop); | |
2375 | break; | |
2376 | } | |
2377 | case fmt_double: | |
8bae0a0c | 2378 | case fmt_long: |
76ef4165 FL |
2379 | { |
2380 | sim_fpu wop; | |
2381 | sim_fpu_64to (&wop, op); | |
2382 | boolean = sim_fpu_is_nan (&wop); | |
2383 | break; | |
2384 | } | |
50a2a691 AC |
2385 | default: |
2386 | fprintf (stderr, "Bad switch\n"); | |
2387 | abort (); | |
8bae0a0c JSC |
2388 | } |
2389 | ||
2390 | #ifdef DEBUG | |
53b9417e | 2391 | printf("DBG: NaN: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op),DOFMT(fmt)); |
8bae0a0c JSC |
2392 | #endif /* DEBUG */ |
2393 | ||
2394 | return(boolean); | |
2395 | } | |
2396 | ||
18c64df6 | 2397 | int |
8bae0a0c | 2398 | Infinity(op,fmt) |
e871dd18 | 2399 | uword64 op; |
8bae0a0c JSC |
2400 | FP_formats fmt; |
2401 | { | |
2402 | int boolean = 0; | |
2403 | ||
2404 | #ifdef DEBUG | |
95469ceb | 2405 | printf("DBG: Infinity: format %s 0x%s\n",DOFMT(fmt),pr_addr(op)); |
8bae0a0c JSC |
2406 | #endif /* DEBUG */ |
2407 | ||
8bae0a0c JSC |
2408 | switch (fmt) { |
2409 | case fmt_single: | |
76ef4165 FL |
2410 | { |
2411 | sim_fpu wop; | |
2412 | sim_fpu_32to (&wop, op); | |
2413 | boolean = sim_fpu_is_infinity (&wop); | |
2414 | break; | |
2415 | } | |
8bae0a0c | 2416 | case fmt_double: |
76ef4165 FL |
2417 | { |
2418 | sim_fpu wop; | |
2419 | sim_fpu_64to (&wop, op); | |
2420 | boolean = sim_fpu_is_infinity (&wop); | |
2421 | break; | |
2422 | } | |
8bae0a0c JSC |
2423 | default: |
2424 | printf("DBG: TODO: unrecognised format (%s) for Infinity check\n",DOFMT(fmt)); | |
2425 | break; | |
2426 | } | |
2427 | ||
2428 | #ifdef DEBUG | |
53b9417e | 2429 | printf("DBG: Infinity: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op),DOFMT(fmt)); |
8bae0a0c JSC |
2430 | #endif /* DEBUG */ |
2431 | ||
2432 | return(boolean); | |
2433 | } | |
2434 | ||
18c64df6 | 2435 | int |
8bae0a0c | 2436 | Less(op1,op2,fmt) |
e871dd18 JSC |
2437 | uword64 op1; |
2438 | uword64 op2; | |
8bae0a0c JSC |
2439 | FP_formats fmt; |
2440 | { | |
2441 | int boolean = 0; | |
2442 | ||
e871dd18 JSC |
2443 | /* Argument checking already performed by the FPCOMPARE code */ |
2444 | ||
8bae0a0c | 2445 | #ifdef DEBUG |
53b9417e | 2446 | printf("DBG: Less: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); |
8bae0a0c JSC |
2447 | #endif /* DEBUG */ |
2448 | ||
8bae0a0c JSC |
2449 | /* The format type should already have been checked: */ |
2450 | switch (fmt) { | |
2451 | case fmt_single: | |
2452 | { | |
76ef4165 FL |
2453 | sim_fpu wop1; |
2454 | sim_fpu wop2; | |
2455 | sim_fpu_32to (&wop1, op1); | |
2456 | sim_fpu_32to (&wop2, op2); | |
2457 | boolean = sim_fpu_is_lt (&wop1, &wop2); | |
2458 | break; | |
8bae0a0c | 2459 | } |
8bae0a0c | 2460 | case fmt_double: |
76ef4165 FL |
2461 | { |
2462 | sim_fpu wop1; | |
2463 | sim_fpu wop2; | |
2464 | sim_fpu_64to (&wop1, op1); | |
2465 | sim_fpu_64to (&wop2, op2); | |
2466 | boolean = sim_fpu_is_lt (&wop1, &wop2); | |
2467 | break; | |
2468 | } | |
50a2a691 AC |
2469 | default: |
2470 | fprintf (stderr, "Bad switch\n"); | |
2471 | abort (); | |
8bae0a0c JSC |
2472 | } |
2473 | ||
2474 | #ifdef DEBUG | |
2475 | printf("DBG: Less: returning %d (format = %s)\n",boolean,DOFMT(fmt)); | |
2476 | #endif /* DEBUG */ | |
2477 | ||
2478 | return(boolean); | |
2479 | } | |
2480 | ||
18c64df6 | 2481 | int |
8bae0a0c | 2482 | Equal(op1,op2,fmt) |
e871dd18 JSC |
2483 | uword64 op1; |
2484 | uword64 op2; | |
8bae0a0c JSC |
2485 | FP_formats fmt; |
2486 | { | |
2487 | int boolean = 0; | |
2488 | ||
e871dd18 JSC |
2489 | /* Argument checking already performed by the FPCOMPARE code */ |
2490 | ||
8bae0a0c | 2491 | #ifdef DEBUG |
53b9417e | 2492 | printf("DBG: Equal: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); |
8bae0a0c JSC |
2493 | #endif /* DEBUG */ |
2494 | ||
8bae0a0c JSC |
2495 | /* The format type should already have been checked: */ |
2496 | switch (fmt) { | |
2497 | case fmt_single: | |
76ef4165 FL |
2498 | { |
2499 | sim_fpu wop1; | |
2500 | sim_fpu wop2; | |
2501 | sim_fpu_32to (&wop1, op1); | |
2502 | sim_fpu_32to (&wop2, op2); | |
2503 | boolean = sim_fpu_is_eq (&wop1, &wop2); | |
2504 | break; | |
2505 | } | |
8bae0a0c | 2506 | case fmt_double: |
76ef4165 FL |
2507 | { |
2508 | sim_fpu wop1; | |
2509 | sim_fpu wop2; | |
2510 | sim_fpu_64to (&wop1, op1); | |
2511 | sim_fpu_64to (&wop2, op2); | |
2512 | boolean = sim_fpu_is_eq (&wop1, &wop2); | |
2513 | break; | |
2514 | } | |
50a2a691 AC |
2515 | default: |
2516 | fprintf (stderr, "Bad switch\n"); | |
2517 | abort (); | |
8bae0a0c JSC |
2518 | } |
2519 | ||
2520 | #ifdef DEBUG | |
2521 | printf("DBG: Equal: returning %d (format = %s)\n",boolean,DOFMT(fmt)); | |
2522 | #endif /* DEBUG */ | |
2523 | ||
2524 | return(boolean); | |
2525 | } | |
2526 | ||
18c64df6 | 2527 | uword64 |
a9f7253f JSC |
2528 | AbsoluteValue(op,fmt) |
2529 | uword64 op; | |
2530 | FP_formats fmt; | |
2531 | { | |
50a2a691 | 2532 | uword64 result = 0; |
a9f7253f JSC |
2533 | |
2534 | #ifdef DEBUG | |
53b9417e | 2535 | printf("DBG: AbsoluteValue: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op)); |
a9f7253f JSC |
2536 | #endif /* DEBUG */ |
2537 | ||
2538 | /* The format type should already have been checked: */ | |
2539 | switch (fmt) { | |
2540 | case fmt_single: | |
2541 | { | |
76ef4165 FL |
2542 | sim_fpu wop; |
2543 | unsigned32 ans; | |
2544 | sim_fpu_32to (&wop, op); | |
2545 | sim_fpu_abs (&wop, &wop); | |
2546 | sim_fpu_to32 (&ans, &wop); | |
2547 | result = ans; | |
2548 | break; | |
a9f7253f | 2549 | } |
a9f7253f JSC |
2550 | case fmt_double: |
2551 | { | |
76ef4165 FL |
2552 | sim_fpu wop; |
2553 | unsigned64 ans; | |
2554 | sim_fpu_64to (&wop, op); | |
2555 | sim_fpu_abs (&wop, &wop); | |
2556 | sim_fpu_to64 (&ans, &wop); | |
2557 | result = ans; | |
2558 | break; | |
a9f7253f | 2559 | } |
50a2a691 AC |
2560 | default: |
2561 | fprintf (stderr, "Bad switch\n"); | |
2562 | abort (); | |
a9f7253f JSC |
2563 | } |
2564 | ||
2565 | return(result); | |
2566 | } | |
2567 | ||
18c64df6 | 2568 | uword64 |
8bae0a0c | 2569 | Negate(op,fmt) |
e871dd18 | 2570 | uword64 op; |
8bae0a0c JSC |
2571 | FP_formats fmt; |
2572 | { | |
50a2a691 | 2573 | uword64 result = 0; |
8bae0a0c JSC |
2574 | |
2575 | #ifdef DEBUG | |
53b9417e | 2576 | printf("DBG: Negate: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op)); |
8bae0a0c JSC |
2577 | #endif /* DEBUG */ |
2578 | ||
2579 | /* The format type should already have been checked: */ | |
2580 | switch (fmt) { | |
2581 | case fmt_single: | |
2582 | { | |
76ef4165 FL |
2583 | sim_fpu wop; |
2584 | unsigned32 ans; | |
2585 | sim_fpu_32to (&wop, op); | |
2586 | sim_fpu_neg (&wop, &wop); | |
2587 | sim_fpu_to32 (&ans, &wop); | |
2588 | result = ans; | |
2589 | break; | |
8bae0a0c | 2590 | } |
8bae0a0c JSC |
2591 | case fmt_double: |
2592 | { | |
76ef4165 FL |
2593 | sim_fpu wop; |
2594 | unsigned64 ans; | |
2595 | sim_fpu_64to (&wop, op); | |
2596 | sim_fpu_neg (&wop, &wop); | |
2597 | sim_fpu_to64 (&ans, &wop); | |
2598 | result = ans; | |
2599 | break; | |
8bae0a0c | 2600 | } |
50a2a691 AC |
2601 | default: |
2602 | fprintf (stderr, "Bad switch\n"); | |
2603 | abort (); | |
8bae0a0c JSC |
2604 | } |
2605 | ||
2606 | return(result); | |
2607 | } | |
2608 | ||
18c64df6 | 2609 | uword64 |
8bae0a0c | 2610 | Add(op1,op2,fmt) |
e871dd18 JSC |
2611 | uword64 op1; |
2612 | uword64 op2; | |
8bae0a0c JSC |
2613 | FP_formats fmt; |
2614 | { | |
50a2a691 | 2615 | uword64 result = 0; |
8bae0a0c JSC |
2616 | |
2617 | #ifdef DEBUG | |
53b9417e | 2618 | printf("DBG: Add: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); |
8bae0a0c JSC |
2619 | #endif /* DEBUG */ |
2620 | ||
e871dd18 JSC |
2621 | /* The registers must specify FPRs valid for operands of type |
2622 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
2623 | |
2624 | /* The format type should already have been checked: */ | |
2625 | switch (fmt) { | |
2626 | case fmt_single: | |
2627 | { | |
76ef4165 FL |
2628 | sim_fpu wop1; |
2629 | sim_fpu wop2; | |
2630 | sim_fpu ans; | |
2631 | unsigned32 res; | |
2632 | sim_fpu_32to (&wop1, op1); | |
2633 | sim_fpu_32to (&wop2, op2); | |
2634 | sim_fpu_add (&ans, &wop1, &wop2); | |
2635 | sim_fpu_to32 (&res, &ans); | |
2636 | result = res; | |
2637 | break; | |
8bae0a0c | 2638 | } |
8bae0a0c JSC |
2639 | case fmt_double: |
2640 | { | |
76ef4165 FL |
2641 | sim_fpu wop1; |
2642 | sim_fpu wop2; | |
2643 | sim_fpu ans; | |
2644 | unsigned64 res; | |
2645 | sim_fpu_64to (&wop1, op1); | |
2646 | sim_fpu_64to (&wop2, op2); | |
2647 | sim_fpu_add (&ans, &wop1, &wop2); | |
2648 | sim_fpu_to64 (&res, &ans); | |
2649 | result = res; | |
2650 | break; | |
8bae0a0c | 2651 | } |
50a2a691 AC |
2652 | default: |
2653 | fprintf (stderr, "Bad switch\n"); | |
2654 | abort (); | |
8bae0a0c JSC |
2655 | } |
2656 | ||
2657 | #ifdef DEBUG | |
53b9417e | 2658 | printf("DBG: Add: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); |
8bae0a0c JSC |
2659 | #endif /* DEBUG */ |
2660 | ||
2661 | return(result); | |
2662 | } | |
2663 | ||
18c64df6 | 2664 | uword64 |
8bae0a0c | 2665 | Sub(op1,op2,fmt) |
e871dd18 JSC |
2666 | uword64 op1; |
2667 | uword64 op2; | |
8bae0a0c JSC |
2668 | FP_formats fmt; |
2669 | { | |
50a2a691 | 2670 | uword64 result = 0; |
8bae0a0c JSC |
2671 | |
2672 | #ifdef DEBUG | |
53b9417e | 2673 | printf("DBG: Sub: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); |
8bae0a0c JSC |
2674 | #endif /* DEBUG */ |
2675 | ||
e871dd18 JSC |
2676 | /* The registers must specify FPRs valid for operands of type |
2677 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
2678 | |
2679 | /* The format type should already have been checked: */ | |
2680 | switch (fmt) { | |
2681 | case fmt_single: | |
2682 | { | |
76ef4165 FL |
2683 | sim_fpu wop1; |
2684 | sim_fpu wop2; | |
2685 | sim_fpu ans; | |
2686 | unsigned32 res; | |
2687 | sim_fpu_32to (&wop1, op1); | |
2688 | sim_fpu_32to (&wop2, op2); | |
2689 | sim_fpu_sub (&ans, &wop1, &wop2); | |
2690 | sim_fpu_to32 (&res, &ans); | |
2691 | result = res; | |
8bae0a0c JSC |
2692 | } |
2693 | break; | |
2694 | case fmt_double: | |
2695 | { | |
76ef4165 FL |
2696 | sim_fpu wop1; |
2697 | sim_fpu wop2; | |
2698 | sim_fpu ans; | |
2699 | unsigned64 res; | |
2700 | sim_fpu_64to (&wop1, op1); | |
2701 | sim_fpu_64to (&wop2, op2); | |
2702 | sim_fpu_sub (&ans, &wop1, &wop2); | |
2703 | sim_fpu_to64 (&res, &ans); | |
2704 | result = res; | |
8bae0a0c JSC |
2705 | } |
2706 | break; | |
50a2a691 AC |
2707 | default: |
2708 | fprintf (stderr, "Bad switch\n"); | |
2709 | abort (); | |
8bae0a0c JSC |
2710 | } |
2711 | ||
2712 | #ifdef DEBUG | |
53b9417e | 2713 | printf("DBG: Sub: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); |
8bae0a0c JSC |
2714 | #endif /* DEBUG */ |
2715 | ||
2716 | return(result); | |
2717 | } | |
2718 | ||
18c64df6 | 2719 | uword64 |
8bae0a0c | 2720 | Multiply(op1,op2,fmt) |
e871dd18 JSC |
2721 | uword64 op1; |
2722 | uword64 op2; | |
8bae0a0c JSC |
2723 | FP_formats fmt; |
2724 | { | |
50a2a691 | 2725 | uword64 result = 0; |
8bae0a0c JSC |
2726 | |
2727 | #ifdef DEBUG | |
53b9417e | 2728 | printf("DBG: Multiply: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); |
8bae0a0c JSC |
2729 | #endif /* DEBUG */ |
2730 | ||
e871dd18 JSC |
2731 | /* The registers must specify FPRs valid for operands of type |
2732 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
2733 | |
2734 | /* The format type should already have been checked: */ | |
2735 | switch (fmt) { | |
2736 | case fmt_single: | |
2737 | { | |
76ef4165 FL |
2738 | sim_fpu wop1; |
2739 | sim_fpu wop2; | |
2740 | sim_fpu ans; | |
2741 | unsigned32 res; | |
2742 | sim_fpu_32to (&wop1, op1); | |
2743 | sim_fpu_32to (&wop2, op2); | |
2744 | sim_fpu_mul (&ans, &wop1, &wop2); | |
2745 | sim_fpu_to32 (&res, &ans); | |
2746 | result = res; | |
2747 | break; | |
8bae0a0c | 2748 | } |
8bae0a0c JSC |
2749 | case fmt_double: |
2750 | { | |
76ef4165 FL |
2751 | sim_fpu wop1; |
2752 | sim_fpu wop2; | |
2753 | sim_fpu ans; | |
2754 | unsigned64 res; | |
2755 | sim_fpu_64to (&wop1, op1); | |
2756 | sim_fpu_64to (&wop2, op2); | |
2757 | sim_fpu_mul (&ans, &wop1, &wop2); | |
2758 | sim_fpu_to64 (&res, &ans); | |
2759 | result = res; | |
2760 | break; | |
8bae0a0c | 2761 | } |
50a2a691 AC |
2762 | default: |
2763 | fprintf (stderr, "Bad switch\n"); | |
2764 | abort (); | |
8bae0a0c JSC |
2765 | } |
2766 | ||
2767 | #ifdef DEBUG | |
53b9417e | 2768 | printf("DBG: Multiply: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); |
8bae0a0c JSC |
2769 | #endif /* DEBUG */ |
2770 | ||
2771 | return(result); | |
2772 | } | |
2773 | ||
18c64df6 | 2774 | uword64 |
8bae0a0c | 2775 | Divide(op1,op2,fmt) |
e871dd18 JSC |
2776 | uword64 op1; |
2777 | uword64 op2; | |
8bae0a0c JSC |
2778 | FP_formats fmt; |
2779 | { | |
50a2a691 | 2780 | uword64 result = 0; |
8bae0a0c JSC |
2781 | |
2782 | #ifdef DEBUG | |
53b9417e | 2783 | printf("DBG: Divide: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); |
8bae0a0c JSC |
2784 | #endif /* DEBUG */ |
2785 | ||
e871dd18 JSC |
2786 | /* The registers must specify FPRs valid for operands of type |
2787 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
2788 | |
2789 | /* The format type should already have been checked: */ | |
2790 | switch (fmt) { | |
2791 | case fmt_single: | |
2792 | { | |
76ef4165 FL |
2793 | sim_fpu wop1; |
2794 | sim_fpu wop2; | |
2795 | sim_fpu ans; | |
2796 | unsigned32 res; | |
2797 | sim_fpu_32to (&wop1, op1); | |
2798 | sim_fpu_32to (&wop2, op2); | |
2799 | sim_fpu_div (&ans, &wop1, &wop2); | |
2800 | sim_fpu_to32 (&res, &ans); | |
2801 | result = res; | |
2802 | break; | |
8bae0a0c | 2803 | } |
8bae0a0c JSC |
2804 | case fmt_double: |
2805 | { | |
76ef4165 FL |
2806 | sim_fpu wop1; |
2807 | sim_fpu wop2; | |
2808 | sim_fpu ans; | |
2809 | unsigned64 res; | |
2810 | sim_fpu_64to (&wop1, op1); | |
2811 | sim_fpu_64to (&wop2, op2); | |
2812 | sim_fpu_div (&ans, &wop1, &wop2); | |
2813 | sim_fpu_to64 (&res, &ans); | |
2814 | result = res; | |
2815 | break; | |
8bae0a0c | 2816 | } |
50a2a691 AC |
2817 | default: |
2818 | fprintf (stderr, "Bad switch\n"); | |
2819 | abort (); | |
8bae0a0c JSC |
2820 | } |
2821 | ||
2822 | #ifdef DEBUG | |
53b9417e | 2823 | printf("DBG: Divide: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); |
8bae0a0c JSC |
2824 | #endif /* DEBUG */ |
2825 | ||
2826 | return(result); | |
2827 | } | |
2828 | ||
18c64df6 | 2829 | uword64 UNUSED |
8bae0a0c | 2830 | Recip(op,fmt) |
e871dd18 | 2831 | uword64 op; |
8bae0a0c JSC |
2832 | FP_formats fmt; |
2833 | { | |
50a2a691 | 2834 | uword64 result = 0; |
8bae0a0c JSC |
2835 | |
2836 | #ifdef DEBUG | |
53b9417e | 2837 | printf("DBG: Recip: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op)); |
8bae0a0c JSC |
2838 | #endif /* DEBUG */ |
2839 | ||
e871dd18 JSC |
2840 | /* The registers must specify FPRs valid for operands of type |
2841 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
2842 | |
2843 | /* The format type should already have been checked: */ | |
2844 | switch (fmt) { | |
2845 | case fmt_single: | |
2846 | { | |
76ef4165 FL |
2847 | sim_fpu wop; |
2848 | sim_fpu ans; | |
2849 | unsigned32 res; | |
2850 | sim_fpu_32to (&wop, op); | |
2851 | sim_fpu_inv (&ans, &wop); | |
2852 | sim_fpu_to32 (&res, &ans); | |
2853 | result = res; | |
2854 | break; | |
8bae0a0c | 2855 | } |
8bae0a0c JSC |
2856 | case fmt_double: |
2857 | { | |
76ef4165 FL |
2858 | sim_fpu wop; |
2859 | sim_fpu ans; | |
2860 | unsigned64 res; | |
2861 | sim_fpu_64to (&wop, op); | |
2862 | sim_fpu_inv (&ans, &wop); | |
2863 | sim_fpu_to64 (&res, &ans); | |
2864 | result = res; | |
2865 | break; | |
8bae0a0c | 2866 | } |
50a2a691 AC |
2867 | default: |
2868 | fprintf (stderr, "Bad switch\n"); | |
2869 | abort (); | |
8bae0a0c JSC |
2870 | } |
2871 | ||
2872 | #ifdef DEBUG | |
53b9417e | 2873 | printf("DBG: Recip: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); |
8bae0a0c JSC |
2874 | #endif /* DEBUG */ |
2875 | ||
2876 | return(result); | |
2877 | } | |
2878 | ||
18c64df6 | 2879 | uword64 |
8bae0a0c | 2880 | SquareRoot(op,fmt) |
e871dd18 | 2881 | uword64 op; |
8bae0a0c JSC |
2882 | FP_formats fmt; |
2883 | { | |
50a2a691 | 2884 | uword64 result = 0; |
8bae0a0c JSC |
2885 | |
2886 | #ifdef DEBUG | |
53b9417e | 2887 | printf("DBG: SquareRoot: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op)); |
8bae0a0c JSC |
2888 | #endif /* DEBUG */ |
2889 | ||
e871dd18 JSC |
2890 | /* The registers must specify FPRs valid for operands of type |
2891 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
2892 | |
2893 | /* The format type should already have been checked: */ | |
2894 | switch (fmt) { | |
2895 | case fmt_single: | |
2896 | { | |
76ef4165 FL |
2897 | sim_fpu wop; |
2898 | sim_fpu ans; | |
2899 | unsigned32 res; | |
2900 | sim_fpu_32to (&wop, op); | |
2901 | sim_fpu_sqrt (&ans, &wop); | |
2902 | sim_fpu_to32 (&res, &ans); | |
2903 | result = res; | |
2904 | break; | |
8bae0a0c | 2905 | } |
8bae0a0c JSC |
2906 | case fmt_double: |
2907 | { | |
76ef4165 FL |
2908 | sim_fpu wop; |
2909 | sim_fpu ans; | |
2910 | unsigned64 res; | |
2911 | sim_fpu_64to (&wop, op); | |
2912 | sim_fpu_sqrt (&ans, &wop); | |
2913 | sim_fpu_to64 (&res, &ans); | |
2914 | result = res; | |
2915 | break; | |
8bae0a0c | 2916 | } |
50a2a691 AC |
2917 | default: |
2918 | fprintf (stderr, "Bad switch\n"); | |
2919 | abort (); | |
8bae0a0c JSC |
2920 | } |
2921 | ||
2922 | #ifdef DEBUG | |
53b9417e | 2923 | printf("DBG: SquareRoot: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); |
8bae0a0c JSC |
2924 | #endif /* DEBUG */ |
2925 | ||
2926 | return(result); | |
2927 | } | |
2928 | ||
82ea14fd | 2929 | #if 0 |
a48e8c8d AC |
2930 | uword64 |
2931 | Max (uword64 op1, | |
2932 | uword64 op2, | |
2933 | FP_formats fmt) | |
2934 | { | |
2935 | int cmp; | |
2936 | unsigned64 result; | |
2937 | ||
2938 | #ifdef DEBUG | |
2939 | printf("DBG: Max: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); | |
2940 | #endif /* DEBUG */ | |
2941 | ||
2942 | /* The registers must specify FPRs valid for operands of type | |
2943 | "fmt". If they are not valid, the result is undefined. */ | |
2944 | ||
2945 | /* The format type should already have been checked: */ | |
2946 | switch (fmt) | |
2947 | { | |
2948 | case fmt_single: | |
2949 | { | |
2950 | sim_fpu wop1; | |
2951 | sim_fpu wop2; | |
2952 | sim_fpu_32to (&wop1, op1); | |
2953 | sim_fpu_32to (&wop2, op2); | |
2954 | cmp = sim_fpu_cmp (&wop1, &wop2); | |
2955 | break; | |
2956 | } | |
2957 | case fmt_double: | |
2958 | { | |
2959 | sim_fpu wop1; | |
2960 | sim_fpu wop2; | |
2961 | sim_fpu_64to (&wop1, op1); | |
2962 | sim_fpu_64to (&wop2, op2); | |
2963 | cmp = sim_fpu_cmp (&wop1, &wop2); | |
2964 | break; | |
2965 | } | |
2966 | default: | |
2967 | fprintf (stderr, "Bad switch\n"); | |
2968 | abort (); | |
2969 | } | |
2970 | ||
2971 | switch (cmp) | |
2972 | { | |
2973 | case SIM_FPU_IS_SNAN: | |
2974 | case SIM_FPU_IS_QNAN: | |
2975 | result = op1; | |
2976 | case SIM_FPU_IS_NINF: | |
2977 | case SIM_FPU_IS_NNUMBER: | |
2978 | case SIM_FPU_IS_NDENORM: | |
2979 | case SIM_FPU_IS_NZERO: | |
2980 | result = op2; /* op1 - op2 < 0 */ | |
2981 | case SIM_FPU_IS_PINF: | |
2982 | case SIM_FPU_IS_PNUMBER: | |
2983 | case SIM_FPU_IS_PDENORM: | |
2984 | case SIM_FPU_IS_PZERO: | |
2985 | result = op1; /* op1 - op2 > 0 */ | |
2986 | default: | |
2987 | fprintf (stderr, "Bad switch\n"); | |
2988 | abort (); | |
2989 | } | |
2990 | ||
2991 | #ifdef DEBUG | |
2992 | printf("DBG: Max: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); | |
2993 | #endif /* DEBUG */ | |
2994 | ||
2995 | return(result); | |
2996 | } | |
82ea14fd | 2997 | #endif |
a48e8c8d | 2998 | |
82ea14fd | 2999 | #if 0 |
a48e8c8d AC |
3000 | uword64 |
3001 | Min (uword64 op1, | |
3002 | uword64 op2, | |
3003 | FP_formats fmt) | |
3004 | { | |
3005 | int cmp; | |
3006 | unsigned64 result; | |
3007 | ||
3008 | #ifdef DEBUG | |
3009 | printf("DBG: Min: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); | |
3010 | #endif /* DEBUG */ | |
3011 | ||
3012 | /* The registers must specify FPRs valid for operands of type | |
3013 | "fmt". If they are not valid, the result is undefined. */ | |
3014 | ||
3015 | /* The format type should already have been checked: */ | |
3016 | switch (fmt) | |
3017 | { | |
3018 | case fmt_single: | |
3019 | { | |
3020 | sim_fpu wop1; | |
3021 | sim_fpu wop2; | |
3022 | sim_fpu_32to (&wop1, op1); | |
3023 | sim_fpu_32to (&wop2, op2); | |
3024 | cmp = sim_fpu_cmp (&wop1, &wop2); | |
3025 | break; | |
3026 | } | |
3027 | case fmt_double: | |
3028 | { | |
3029 | sim_fpu wop1; | |
3030 | sim_fpu wop2; | |
3031 | sim_fpu_64to (&wop1, op1); | |
3032 | sim_fpu_64to (&wop2, op2); | |
3033 | cmp = sim_fpu_cmp (&wop1, &wop2); | |
3034 | break; | |
3035 | } | |
3036 | default: | |
3037 | fprintf (stderr, "Bad switch\n"); | |
3038 | abort (); | |
3039 | } | |
3040 | ||
3041 | switch (cmp) | |
3042 | { | |
3043 | case SIM_FPU_IS_SNAN: | |
3044 | case SIM_FPU_IS_QNAN: | |
3045 | result = op1; | |
3046 | case SIM_FPU_IS_NINF: | |
3047 | case SIM_FPU_IS_NNUMBER: | |
3048 | case SIM_FPU_IS_NDENORM: | |
3049 | case SIM_FPU_IS_NZERO: | |
3050 | result = op1; /* op1 - op2 < 0 */ | |
3051 | case SIM_FPU_IS_PINF: | |
3052 | case SIM_FPU_IS_PNUMBER: | |
3053 | case SIM_FPU_IS_PDENORM: | |
3054 | case SIM_FPU_IS_PZERO: | |
3055 | result = op2; /* op1 - op2 > 0 */ | |
3056 | default: | |
3057 | fprintf (stderr, "Bad switch\n"); | |
3058 | abort (); | |
3059 | } | |
3060 | ||
3061 | #ifdef DEBUG | |
3062 | printf("DBG: Min: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); | |
3063 | #endif /* DEBUG */ | |
3064 | ||
3065 | return(result); | |
3066 | } | |
82ea14fd | 3067 | #endif |
a48e8c8d | 3068 | |
18c64df6 | 3069 | uword64 |
01737f42 AC |
3070 | convert (SIM_DESC sd, |
3071 | sim_cpu *cpu, | |
3072 | address_word cia, | |
3073 | int rm, | |
3074 | uword64 op, | |
3075 | FP_formats from, | |
3076 | FP_formats to) | |
8bae0a0c | 3077 | { |
76ef4165 FL |
3078 | sim_fpu wop; |
3079 | sim_fpu_round round; | |
3080 | unsigned32 result32; | |
3081 | unsigned64 result64; | |
8bae0a0c JSC |
3082 | |
3083 | #ifdef DEBUG | |
53b9417e | 3084 | printf("DBG: Convert: mode %s : op 0x%s : from %s : to %s : (PC = 0x%s)\n",RMMODE(rm),pr_addr(op),DOFMT(from),DOFMT(to),pr_addr(IPC)); |
8bae0a0c JSC |
3085 | #endif /* DEBUG */ |
3086 | ||
76ef4165 | 3087 | switch (rm) |
8bae0a0c | 3088 | { |
76ef4165 FL |
3089 | case FP_RM_NEAREST: |
3090 | /* Round result to nearest representable value. When two | |
3091 | representable values are equally near, round to the value | |
3092 | that has a least significant bit of zero (i.e. is even). */ | |
3093 | round = sim_fpu_round_near; | |
3094 | break; | |
3095 | case FP_RM_TOZERO: | |
3096 | /* Round result to the value closest to, and not greater in | |
3097 | magnitude than, the result. */ | |
3098 | round = sim_fpu_round_zero; | |
3099 | break; | |
3100 | case FP_RM_TOPINF: | |
3101 | /* Round result to the value closest to, and not less than, | |
3102 | the result. */ | |
3103 | round = sim_fpu_round_up; | |
3104 | break; | |
3105 | ||
3106 | case FP_RM_TOMINF: | |
3107 | /* Round result to the value closest to, and not greater than, | |
3108 | the result. */ | |
3109 | round = sim_fpu_round_down; | |
3110 | break; | |
3111 | default: | |
3112 | round = 0; | |
3113 | fprintf (stderr, "Bad switch\n"); | |
3114 | abort (); | |
8bae0a0c | 3115 | } |
76ef4165 FL |
3116 | |
3117 | /* Convert the input to sim_fpu internal format */ | |
3118 | switch (from) | |
8bae0a0c | 3119 | { |
76ef4165 FL |
3120 | case fmt_double: |
3121 | sim_fpu_64to (&wop, op); | |
3122 | break; | |
3123 | case fmt_single: | |
3124 | sim_fpu_32to (&wop, op); | |
3125 | break; | |
3126 | case fmt_word: | |
3127 | sim_fpu_i32to (&wop, op, round); | |
3128 | break; | |
3129 | case fmt_long: | |
3130 | sim_fpu_i64to (&wop, op, round); | |
3131 | break; | |
3132 | default: | |
3133 | fprintf (stderr, "Bad switch\n"); | |
3134 | abort (); | |
8bae0a0c | 3135 | } |
8bae0a0c | 3136 | |
76ef4165 FL |
3137 | /* Convert sim_fpu format into the output */ |
3138 | /* The value WOP is converted to the destination format, rounding | |
3139 | using mode RM. When the destination is a fixed-point format, then | |
3140 | a source value of Infinity, NaN or one which would round to an | |
3141 | integer outside the fixed point range then an IEEE Invalid | |
3142 | Operation condition is raised. */ | |
3143 | switch (to) | |
3144 | { | |
3145 | case fmt_single: | |
3146 | sim_fpu_round_32 (&wop, round, 0); | |
3147 | sim_fpu_to32 (&result32, &wop); | |
3148 | result64 = result32; | |
3149 | break; | |
3150 | case fmt_double: | |
3151 | sim_fpu_round_64 (&wop, round, 0); | |
3152 | sim_fpu_to64 (&result64, &wop); | |
3153 | break; | |
3154 | case fmt_word: | |
3155 | sim_fpu_to32i (&result32, &wop, round); | |
3156 | result64 = result32; | |
3157 | break; | |
3158 | case fmt_long: | |
3159 | sim_fpu_to64i (&result64, &wop, round); | |
3160 | break; | |
3161 | default: | |
3162 | result64 = 0; | |
3163 | fprintf (stderr, "Bad switch\n"); | |
3164 | abort (); | |
8bae0a0c | 3165 | } |
76ef4165 | 3166 | |
8bae0a0c | 3167 | #ifdef DEBUG |
76ef4165 | 3168 | printf("DBG: Convert: returning 0x%s (to format = %s)\n",pr_addr(result64),DOFMT(to)); |
8bae0a0c JSC |
3169 | #endif /* DEBUG */ |
3170 | ||
76ef4165 | 3171 | return(result64); |
8bae0a0c | 3172 | } |
8bae0a0c | 3173 | |
76ef4165 | 3174 | |
8bae0a0c JSC |
3175 | /*-- co-processor support routines ------------------------------------------*/ |
3176 | ||
2f2e6c5d | 3177 | static int UNUSED |
8bae0a0c JSC |
3178 | CoProcPresent(coproc_number) |
3179 | unsigned int coproc_number; | |
3180 | { | |
3181 | /* Return TRUE if simulator provides a model for the given co-processor number */ | |
3182 | return(0); | |
3183 | } | |
3184 | ||
18c64df6 | 3185 | void |
01737f42 AC |
3186 | cop_lw (SIM_DESC sd, |
3187 | sim_cpu *cpu, | |
3188 | address_word cia, | |
3189 | int coproc_num, | |
3190 | int coproc_reg, | |
3191 | unsigned int memword) | |
8bae0a0c | 3192 | { |
192ae475 AC |
3193 | switch (coproc_num) |
3194 | { | |
8bae0a0c | 3195 | case 1: |
192ae475 AC |
3196 | if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT) |
3197 | { | |
8bae0a0c | 3198 | #ifdef DEBUG |
192ae475 | 3199 | printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword,pr_addr(memword)); |
8bae0a0c | 3200 | #endif |
192ae475 AC |
3201 | StoreFPR(coproc_reg,fmt_word,(uword64)memword); |
3202 | FPR_STATE[coproc_reg] = fmt_uninterpreted; | |
3203 | break; | |
3204 | } | |
8bae0a0c JSC |
3205 | |
3206 | default: | |
f24b7b69 | 3207 | #if 0 /* this should be controlled by a configuration option */ |
192ae475 | 3208 | sim_io_printf(sd,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,memword,pr_addr(cia)); |
f24b7b69 | 3209 | #endif |
192ae475 AC |
3210 | break; |
3211 | } | |
8bae0a0c JSC |
3212 | |
3213 | return; | |
3214 | } | |
3215 | ||
18c64df6 | 3216 | void |
01737f42 AC |
3217 | cop_ld (SIM_DESC sd, |
3218 | sim_cpu *cpu, | |
3219 | address_word cia, | |
3220 | int coproc_num, | |
3221 | int coproc_reg, | |
3222 | uword64 memword) | |
8bae0a0c JSC |
3223 | { |
3224 | switch (coproc_num) { | |
8bae0a0c | 3225 | case 1: |
192ae475 AC |
3226 | if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT) |
3227 | { | |
3228 | StoreFPR(coproc_reg,fmt_uninterpreted,memword); | |
3229 | break; | |
3230 | } | |
8bae0a0c JSC |
3231 | |
3232 | default: | |
f24b7b69 | 3233 | #if 0 /* this message should be controlled by a configuration option */ |
95469ceb | 3234 | sim_io_printf(sd,"COP_LD(%d,%d,0x%s) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(memword),pr_addr(cia)); |
f24b7b69 | 3235 | #endif |
8bae0a0c JSC |
3236 | break; |
3237 | } | |
3238 | ||
3239 | return; | |
3240 | } | |
3241 | ||
18c64df6 | 3242 | unsigned int |
01737f42 AC |
3243 | cop_sw (SIM_DESC sd, |
3244 | sim_cpu *cpu, | |
3245 | address_word cia, | |
3246 | int coproc_num, | |
3247 | int coproc_reg) | |
8bae0a0c JSC |
3248 | { |
3249 | unsigned int value = 0; | |
da0bce9c | 3250 | |
192ae475 AC |
3251 | switch (coproc_num) |
3252 | { | |
8bae0a0c | 3253 | case 1: |
192ae475 AC |
3254 | if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT) |
3255 | { | |
3256 | FP_formats hold; | |
3257 | hold = FPR_STATE[coproc_reg]; | |
3258 | FPR_STATE[coproc_reg] = fmt_word; | |
3259 | value = (unsigned int)ValueFPR(coproc_reg,fmt_uninterpreted); | |
3260 | FPR_STATE[coproc_reg] = hold; | |
3261 | break; | |
3262 | } | |
8bae0a0c JSC |
3263 | |
3264 | default: | |
f24b7b69 | 3265 | #if 0 /* should be controlled by configuration option */ |
192ae475 | 3266 | sim_io_printf(sd,"COP_SW(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia)); |
f24b7b69 | 3267 | #endif |
192ae475 AC |
3268 | break; |
3269 | } | |
8bae0a0c JSC |
3270 | |
3271 | return(value); | |
3272 | } | |
3273 | ||
18c64df6 | 3274 | uword64 |
01737f42 AC |
3275 | cop_sd (SIM_DESC sd, |
3276 | sim_cpu *cpu, | |
3277 | address_word cia, | |
3278 | int coproc_num, | |
3279 | int coproc_reg) | |
8bae0a0c | 3280 | { |
e871dd18 | 3281 | uword64 value = 0; |
192ae475 AC |
3282 | switch (coproc_num) |
3283 | { | |
8bae0a0c | 3284 | case 1: |
192ae475 AC |
3285 | if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT) |
3286 | { | |
3287 | value = ValueFPR(coproc_reg,fmt_uninterpreted); | |
3288 | break; | |
3289 | } | |
8bae0a0c JSC |
3290 | |
3291 | default: | |
f24b7b69 | 3292 | #if 0 /* should be controlled by configuration option */ |
192ae475 | 3293 | sim_io_printf(sd,"COP_SD(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia)); |
f24b7b69 | 3294 | #endif |
192ae475 AC |
3295 | break; |
3296 | } | |
8bae0a0c JSC |
3297 | |
3298 | return(value); | |
3299 | } | |
3300 | ||
ea985d24 | 3301 | void |
01737f42 AC |
3302 | decode_coproc (SIM_DESC sd, |
3303 | sim_cpu *cpu, | |
3304 | address_word cia, | |
3305 | unsigned int instruction) | |
8bae0a0c JSC |
3306 | { |
3307 | int coprocnum = ((instruction >> 26) & 3); | |
3308 | ||
56e7c849 AC |
3309 | switch (coprocnum) |
3310 | { | |
8bae0a0c JSC |
3311 | case 0: /* standard CPU control and cache registers */ |
3312 | { | |
8bae0a0c JSC |
3313 | int code = ((instruction >> 21) & 0x1F); |
3314 | /* R4000 Users Manual (second edition) lists the following CP0 | |
3315 | instructions: | |
56e7c849 AC |
3316 | DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000) |
3317 | DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000) | |
3318 | MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000) | |
3319 | MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000) | |
3320 | TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001) | |
3321 | TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010) | |
3322 | TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110) | |
3323 | TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000) | |
3324 | CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii) | |
3325 | ERET Exception return (VR4100 = 01000010000000000000000000011000) | |
3326 | */ | |
3327 | if (((code == 0x00) || (code == 0x04)) && ((instruction & 0x7FF) == 0)) | |
3328 | { | |
3329 | int rt = ((instruction >> 16) & 0x1F); | |
3330 | int rd = ((instruction >> 11) & 0x1F); | |
3331 | ||
3332 | switch (rd) /* NOTEs: Standard CP0 registers */ | |
3333 | { | |
3334 | /* 0 = Index R4000 VR4100 VR4300 */ | |
3335 | /* 1 = Random R4000 VR4100 VR4300 */ | |
3336 | /* 2 = EntryLo0 R4000 VR4100 VR4300 */ | |
3337 | /* 3 = EntryLo1 R4000 VR4100 VR4300 */ | |
3338 | /* 4 = Context R4000 VR4100 VR4300 */ | |
3339 | /* 5 = PageMask R4000 VR4100 VR4300 */ | |
3340 | /* 6 = Wired R4000 VR4100 VR4300 */ | |
3341 | /* 8 = BadVAddr R4000 VR4100 VR4300 */ | |
3342 | /* 9 = Count R4000 VR4100 VR4300 */ | |
3343 | /* 10 = EntryHi R4000 VR4100 VR4300 */ | |
3344 | /* 11 = Compare R4000 VR4100 VR4300 */ | |
3345 | /* 12 = SR R4000 VR4100 VR4300 */ | |
3346 | case 12: | |
3347 | if (code == 0x00) | |
3348 | GPR[rt] = SR; | |
3349 | else | |
3350 | SR = GPR[rt]; | |
3351 | break; | |
3352 | /* 13 = Cause R4000 VR4100 VR4300 */ | |
05d1322f JL |
3353 | case 13: |
3354 | if (code == 0x00) | |
3355 | GPR[rt] = CAUSE; | |
3356 | else | |
3357 | CAUSE = GPR[rt]; | |
3358 | break; | |
56e7c849 AC |
3359 | /* 14 = EPC R4000 VR4100 VR4300 */ |
3360 | /* 15 = PRId R4000 VR4100 VR4300 */ | |
6eedf3f4 MA |
3361 | #ifdef SUBTARGET_R3900 |
3362 | /* 16 = Debug */ | |
3363 | case 16: | |
3364 | if (code == 0x00) | |
3365 | GPR[rt] = Debug; | |
3366 | else | |
3367 | Debug = GPR[rt]; | |
3368 | break; | |
3369 | #else | |
56e7c849 | 3370 | /* 16 = Config R4000 VR4100 VR4300 */ |
a09a30d2 AC |
3371 | case 16: |
3372 | if (code == 0x00) | |
3373 | GPR[rt] = C0_CONFIG; | |
3374 | else | |
3375 | C0_CONFIG = GPR[rt]; | |
3376 | break; | |
6eedf3f4 MA |
3377 | #endif |
3378 | #ifdef SUBTARGET_R3900 | |
3379 | /* 17 = Debug */ | |
3380 | case 17: | |
3381 | if (code == 0x00) | |
3382 | GPR[rt] = DEPC; | |
3383 | else | |
3384 | DEPC = GPR[rt]; | |
3385 | break; | |
3386 | #else | |
56e7c849 | 3387 | /* 17 = LLAddr R4000 VR4100 VR4300 */ |
6eedf3f4 | 3388 | #endif |
56e7c849 AC |
3389 | /* 18 = WatchLo R4000 VR4100 VR4300 */ |
3390 | /* 19 = WatchHi R4000 VR4100 VR4300 */ | |
3391 | /* 20 = XContext R4000 VR4100 VR4300 */ | |
3392 | /* 26 = PErr or ECC R4000 VR4100 VR4300 */ | |
3393 | /* 27 = CacheErr R4000 VR4100 */ | |
3394 | /* 28 = TagLo R4000 VR4100 VR4300 */ | |
3395 | /* 29 = TagHi R4000 VR4100 VR4300 */ | |
3396 | /* 30 = ErrorEPC R4000 VR4100 VR4300 */ | |
3397 | GPR[rt] = 0xDEADC0DE; /* CPR[0,rd] */ | |
3398 | /* CPR[0,rd] = GPR[rt]; */ | |
3399 | default: | |
3400 | if (code == 0x00) | |
18c64df6 | 3401 | sim_io_printf(sd,"Warning: MFC0 %d,%d ignored (architecture specific)\n",rt,rd); |
56e7c849 | 3402 | else |
18c64df6 | 3403 | sim_io_printf(sd,"Warning: MTC0 %d,%d ignored (architecture specific)\n",rt,rd); |
56e7c849 AC |
3404 | } |
3405 | } | |
3406 | else if (code == 0x10 && (instruction & 0x3f) == 0x18) | |
3407 | { | |
3408 | /* ERET */ | |
3409 | if (SR & status_ERL) | |
3410 | { | |
3411 | /* Oops, not yet available */ | |
18c64df6 | 3412 | sim_io_printf(sd,"Warning: ERET when SR[ERL] set not handled yet"); |
56e7c849 AC |
3413 | PC = EPC; |
3414 | SR &= ~status_ERL; | |
3415 | } | |
3416 | else | |
3417 | { | |
3418 | PC = EPC; | |
3419 | SR &= ~status_EXL; | |
3420 | } | |
3421 | } | |
6eedf3f4 MA |
3422 | else if (code == 0x10 && (instruction & 0x3f) == 0x10) |
3423 | { | |
3424 | /* RFE */ | |
3425 | } | |
3426 | else if (code == 0x10 && (instruction & 0x3f) == 0x1F) | |
3427 | { | |
3428 | /* DERET */ | |
3429 | Debug &= ~Debug_DM; | |
3430 | DELAYSLOT(); | |
3431 | DSPC = DEPC; | |
3432 | } | |
56e7c849 | 3433 | else |
95469ceb | 3434 | sim_io_eprintf(sd,"Unrecognised COP0 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction,pr_addr(cia)); |
e871dd18 | 3435 | /* TODO: When executing an ERET or RFE instruction we should |
8bae0a0c JSC |
3436 | clear LLBIT, to ensure that any out-standing atomic |
3437 | read/modify/write sequence fails. */ | |
3438 | } | |
56e7c849 AC |
3439 | break; |
3440 | ||
8bae0a0c | 3441 | case 2: /* undefined co-processor */ |
95469ceb | 3442 | sim_io_eprintf(sd,"COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction,pr_addr(cia)); |
8bae0a0c | 3443 | break; |
56e7c849 | 3444 | |
8bae0a0c JSC |
3445 | case 1: /* should not occur (FPU co-processor) */ |
3446 | case 3: /* should not occur (FPU co-processor) */ | |
3447 | SignalException(ReservedInstruction,instruction); | |
3448 | break; | |
56e7c849 AC |
3449 | } |
3450 | ||
8bae0a0c JSC |
3451 | return; |
3452 | } | |
3453 | ||
3454 | /*-- instruction simulation -------------------------------------------------*/ | |
3455 | ||
16bd5d6e AC |
3456 | /* When the IGEN simulator is being built, the function below is be |
3457 | replaced by a generated version. However, WITH_IGEN == 2 indicates | |
3458 | that the fubction below should be compiled but under a different | |
3459 | name (to allow backward compatibility) */ | |
3460 | ||
3461 | #if (WITH_IGEN != 1) | |
3462 | #if (WITH_IGEN > 1) | |
dad6f1f3 AC |
3463 | void old_engine_run PARAMS ((SIM_DESC sd, int next_cpu_nr, int siggnal)); |
3464 | void | |
9ec6741b | 3465 | old_engine_run (sd, next_cpu_nr, nr_cpus, siggnal) |
dad6f1f3 | 3466 | #else |
2e61a3ad | 3467 | void |
9ec6741b | 3468 | sim_engine_run (sd, next_cpu_nr, nr_cpus, siggnal) |
dad6f1f3 | 3469 | #endif |
2e61a3ad AC |
3470 | SIM_DESC sd; |
3471 | int next_cpu_nr; /* ignore */ | |
9ec6741b | 3472 | int nr_cpus; /* ignore */ |
2e61a3ad | 3473 | int siggnal; /* ignore */ |
8bae0a0c | 3474 | { |
01737f42 | 3475 | sim_cpu *cpu = STATE_CPU (sd, 0); /* hardwire to cpu 0 */ |
50a2a691 | 3476 | #if !defined(FASTSIM) |
8bae0a0c | 3477 | unsigned int pipeline_count = 1; |
50a2a691 | 3478 | #endif |
8bae0a0c JSC |
3479 | |
3480 | #ifdef DEBUG | |
50a2a691 | 3481 | if (STATE_MEMORY (sd) == NULL) { |
8bae0a0c JSC |
3482 | printf("DBG: simulate() entered with no memory\n"); |
3483 | exit(1); | |
3484 | } | |
3485 | #endif /* DEBUG */ | |
3486 | ||
3487 | #if 0 /* Disabled to check that everything works OK */ | |
3488 | /* The VR4300 seems to sign-extend the PC on its first | |
3489 | access. However, this may just be because it is currently | |
3490 | configured in 32bit mode. However... */ | |
3491 | PC = SIGNEXTEND(PC,32); | |
3492 | #endif | |
3493 | ||
3494 | /* main controlling loop */ | |
2e61a3ad | 3495 | while (1) { |
7ce8b917 AC |
3496 | /* vaddr is slowly being replaced with cia - current instruction |
3497 | address */ | |
3498 | address_word cia = (uword64)PC; | |
3499 | address_word vaddr = cia; | |
dad6f1f3 | 3500 | address_word paddr; |
8bae0a0c | 3501 | int cca; |
53b9417e | 3502 | unsigned int instruction; /* uword64? what's this used for? FIXME! */ |
8bae0a0c JSC |
3503 | |
3504 | #ifdef DEBUG | |
3505 | { | |
3506 | printf("DBG: state = 0x%08X :",state); | |
8bae0a0c JSC |
3507 | if (state & simHALTEX) printf(" simHALTEX"); |
3508 | if (state & simHALTIN) printf(" simHALTIN"); | |
53b9417e | 3509 | printf("\n"); |
8bae0a0c JSC |
3510 | } |
3511 | #endif /* DEBUG */ | |
3512 | ||
0c2c5f61 | 3513 | DSSTATE = (STATE & simDELAYSLOT); |
8bae0a0c JSC |
3514 | #ifdef DEBUG |
3515 | if (dsstate) | |
18c64df6 | 3516 | sim_io_printf(sd,"DBG: DSPC = 0x%s\n",pr_addr(DSPC)); |
8bae0a0c JSC |
3517 | #endif /* DEBUG */ |
3518 | ||
7ce8b917 AC |
3519 | /* Fetch the next instruction from the simulator memory: */ |
3520 | if (AddressTranslation(cia,isINSTRUCTION,isLOAD,&paddr,&cca,isTARGET,isREAL)) { | |
6429b296 JW |
3521 | if ((vaddr & 1) == 0) { |
3522 | /* Copy the action of the LW instruction */ | |
3523 | unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0); | |
3524 | unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0); | |
3525 | uword64 value; | |
3526 | unsigned int byte; | |
3527 | paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2))); | |
53b9417e | 3528 | LoadMemory(&value,NULL,cca,AccessLength_WORD,paddr,vaddr,isINSTRUCTION,isREAL); |
6429b296 JW |
3529 | byte = ((vaddr & LOADDRMASK) ^ (bigend << 2)); |
3530 | instruction = ((value >> (8 * byte)) & 0xFFFFFFFF); | |
3531 | } else { | |
3532 | /* Copy the action of the LH instruction */ | |
3533 | unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 1) : 0); | |
3534 | unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 1) : 0); | |
3535 | uword64 value; | |
3536 | unsigned int byte; | |
3537 | paddr = (((paddr & ~ (uword64) 1) & ~LOADDRMASK) | |
3538 | | (((paddr & ~ (uword64) 1) & LOADDRMASK) ^ (reverse << 1))); | |
53b9417e | 3539 | LoadMemory(&value,NULL,cca, AccessLength_HALFWORD, |
6429b296 JW |
3540 | paddr & ~ (uword64) 1, |
3541 | vaddr, isINSTRUCTION, isREAL); | |
3542 | byte = (((vaddr &~ (uword64) 1) & LOADDRMASK) ^ (bigend << 1)); | |
3543 | instruction = ((value >> (8 * byte)) & 0xFFFF); | |
3544 | } | |
8bae0a0c | 3545 | } else { |
53b9417e | 3546 | fprintf(stderr,"Cannot translate address for PC = 0x%s failed\n",pr_addr(PC)); |
8bae0a0c JSC |
3547 | exit(1); |
3548 | } | |
3549 | ||
3550 | #ifdef DEBUG | |
18c64df6 | 3551 | sim_io_printf(sd,"DBG: fetched 0x%08X from PC = 0x%s\n",instruction,pr_addr(PC)); |
8bae0a0c JSC |
3552 | #endif /* DEBUG */ |
3553 | ||
8bae0a0c JSC |
3554 | /* This is required by exception processing, to ensure that we can |
3555 | cope with exceptions in the delay slots of branches that may | |
3556 | already have changed the PC. */ | |
6429b296 JW |
3557 | if ((vaddr & 1) == 0) |
3558 | PC += 4; /* increment ready for the next fetch */ | |
3559 | else | |
3560 | PC += 2; | |
8bae0a0c JSC |
3561 | /* NOTE: If we perform a delay slot change to the PC, this |
3562 | increment is not requuired. However, it would make the | |
3563 | simulator more complicated to try and avoid this small hit. */ | |
3564 | ||
3565 | /* Currently this code provides a simple model. For more | |
3566 | complicated models we could perform exception status checks at | |
3567 | this point, and set the simSTOP state as required. This could | |
3568 | also include processing any hardware interrupts raised by any | |
3569 | I/O model attached to the simulator context. | |
3570 | ||
3571 | Support for "asynchronous" I/O events within the simulated world | |
3572 | could be providing by managing a counter, and calling a I/O | |
3573 | specific handler when a particular threshold is reached. On most | |
3574 | architectures a decrement and check for zero operation is | |
3575 | usually quicker than an increment and compare. However, the | |
3576 | process of managing a known value decrement to zero, is higher | |
3577 | than the cost of using an explicit value UINT_MAX into the | |
3578 | future. Which system is used will depend on how complicated the | |
3579 | I/O model is, and how much it is likely to affect the simulator | |
3580 | bandwidth. | |
3581 | ||
3582 | If events need to be scheduled further in the future than | |
3583 | UINT_MAX event ticks, then the I/O model should just provide its | |
3584 | own counter, triggered from the event system. */ | |
3585 | ||
3586 | /* MIPS pipeline ticks. To allow for future support where the | |
3587 | pipeline hit of individual instructions is known, this control | |
3588 | loop manages a "pipeline_count" variable. It is initialised to | |
3589 | 1 (one), and will only be changed by the simulator engine when | |
3590 | executing an instruction. If the engine does not have access to | |
3591 | pipeline cycle count information then all instructions will be | |
3592 | treated as using a single cycle. NOTE: A standard system is not | |
3593 | provided by the default simulator because different MIPS | |
3594 | architectures have different cycle counts for the same | |
50a2a691 AC |
3595 | instructions. |
3596 | ||
3597 | [NOTE: pipeline_count has been replaced the event queue] */ | |
8bae0a0c | 3598 | |
a09a30d2 AC |
3599 | /* shuffle the floating point status pipeline state */ |
3600 | ENGINE_ISSUE_PREFIX_HOOK(); | |
8bae0a0c JSC |
3601 | |
3602 | /* NOTE: For multi-context simulation environments the "instruction" | |
3603 | variable should be local to this routine. */ | |
3604 | ||
3605 | /* Shorthand accesses for engine. Note: If we wanted to use global | |
3606 | variables (and a single-threaded simulator engine), then we can | |
3607 | create the actual variables with these names. */ | |
3608 | ||
0c2c5f61 | 3609 | if (!(STATE & simSKIPNEXT)) { |
8bae0a0c | 3610 | /* Include the simulator engine */ |
284e759d | 3611 | #include "oengine.c" |
f24b7b69 | 3612 | #if ((GPRLEN == 64) && !PROCESSOR_64BIT) || ((GPRLEN == 32) && PROCESSOR_64BIT) |
8bae0a0c JSC |
3613 | #error "Mismatch between run-time simulator code and simulation engine" |
3614 | #endif | |
18c64df6 AC |
3615 | #if (WITH_TARGET_WORD_BITSIZE != GPRLEN) |
3616 | #error "Mismatch between configure WITH_TARGET_WORD_BITSIZE and gencode GPRLEN" | |
3617 | #endif | |
76ef4165 | 3618 | #if ((WITH_FLOATING_POINT == HARD_FLOATING_POINT) != defined (HASFPU)) |
18c64df6 AC |
3619 | #error "Mismatch between configure WITH_FLOATING_POINT and gencode HASFPU" |
3620 | #endif | |
8bae0a0c JSC |
3621 | |
3622 | #if defined(WARN_LOHI) | |
3623 | /* Decrement the HI/LO validity ticks */ | |
3624 | if (HIACCESS > 0) | |
3625 | HIACCESS--; | |
3626 | if (LOACCESS > 0) | |
3627 | LOACCESS--; | |
0425cfb3 | 3628 | /* start-sanitize-r5900 */ |
53b9417e DE |
3629 | if (HI1ACCESS > 0) |
3630 | HI1ACCESS--; | |
3631 | if (LO1ACCESS > 0) | |
3632 | LO1ACCESS--; | |
0425cfb3 | 3633 | /* end-sanitize-r5900 */ |
8bae0a0c JSC |
3634 | #endif /* WARN_LOHI */ |
3635 | ||
8bae0a0c JSC |
3636 | /* For certain MIPS architectures, GPR[0] is hardwired to zero. We |
3637 | should check for it being changed. It is better doing it here, | |
3638 | than within the simulator, since it will help keep the simulator | |
3639 | small. */ | |
3640 | if (ZERO != 0) { | |
05d1322f | 3641 | #if defined(WARN_ZERO) |
95469ceb | 3642 | sim_io_eprintf(sd,"The ZERO register has been updated with 0x%s (PC = 0x%s) (reset back to zero)\n",pr_addr(ZERO),pr_addr(cia)); |
05d1322f | 3643 | #endif /* WARN_ZERO */ |
8bae0a0c JSC |
3644 | ZERO = 0; /* reset back to zero before next instruction */ |
3645 | } | |
8bae0a0c | 3646 | } else /* simSKIPNEXT check */ |
0c2c5f61 | 3647 | STATE &= ~simSKIPNEXT; |
8bae0a0c JSC |
3648 | |
3649 | /* If the delay slot was active before the instruction is | |
3650 | executed, then update the PC to its new value: */ | |
0c2c5f61 | 3651 | if (DSSTATE) { |
8bae0a0c | 3652 | #ifdef DEBUG |
53b9417e | 3653 | printf("DBG: dsstate set before instruction execution - updating PC to 0x%s\n",pr_addr(DSPC)); |
8bae0a0c JSC |
3654 | #endif /* DEBUG */ |
3655 | PC = DSPC; | |
6eedf3f4 | 3656 | CANCELDELAYSLOT(); |
8bae0a0c JSC |
3657 | } |
3658 | ||
2acd126a AC |
3659 | if (MIPSISA < 4) |
3660 | PENDING_TICK(); | |
8bae0a0c JSC |
3661 | |
3662 | #if !defined(FASTSIM) | |
50a2a691 AC |
3663 | if (sim_events_tickn (sd, pipeline_count)) |
3664 | { | |
3665 | /* cpu->cia = cia; */ | |
3666 | sim_events_process (sd); | |
3667 | } | |
3668 | #else | |
2e61a3ad AC |
3669 | if (sim_events_tick (sd)) |
3670 | { | |
3671 | /* cpu->cia = cia; */ | |
3672 | sim_events_process (sd); | |
3673 | } | |
50a2a691 | 3674 | #endif /* FASTSIM */ |
8bae0a0c | 3675 | } |
8bae0a0c | 3676 | } |
16bd5d6e AC |
3677 | #endif |
3678 | ||
8bae0a0c | 3679 | |
53b9417e DE |
3680 | /* This code copied from gdb's utils.c. Would like to share this code, |
3681 | but don't know of a common place where both could get to it. */ | |
3682 | ||
3683 | /* Temporary storage using circular buffer */ | |
3684 | #define NUMCELLS 16 | |
3685 | #define CELLSIZE 32 | |
3686 | static char* | |
3687 | get_cell() | |
3688 | { | |
3689 | static char buf[NUMCELLS][CELLSIZE]; | |
3690 | static int cell=0; | |
3691 | if (++cell>=NUMCELLS) cell=0; | |
3692 | return buf[cell]; | |
3693 | } | |
3694 | ||
3695 | /* Print routines to handle variable size regs, etc */ | |
3696 | ||
3697 | /* Eliminate warning from compiler on 32-bit systems */ | |
3698 | static int thirty_two = 32; | |
3699 | ||
3700 | char* | |
3701 | pr_addr(addr) | |
3702 | SIM_ADDR addr; | |
3703 | { | |
3704 | char *paddr_str=get_cell(); | |
3705 | switch (sizeof(addr)) | |
3706 | { | |
3707 | case 8: | |
50a2a691 | 3708 | sprintf(paddr_str,"%08lx%08lx", |
53b9417e DE |
3709 | (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff)); |
3710 | break; | |
3711 | case 4: | |
50a2a691 | 3712 | sprintf(paddr_str,"%08lx",(unsigned long)addr); |
53b9417e DE |
3713 | break; |
3714 | case 2: | |
3715 | sprintf(paddr_str,"%04x",(unsigned short)(addr&0xffff)); | |
3716 | break; | |
3717 | default: | |
3718 | sprintf(paddr_str,"%x",addr); | |
3719 | } | |
3720 | return paddr_str; | |
3721 | } | |
3722 | ||
87e43259 AC |
3723 | char* |
3724 | pr_uword64(addr) | |
3725 | uword64 addr; | |
3726 | { | |
3727 | char *paddr_str=get_cell(); | |
50a2a691 | 3728 | sprintf(paddr_str,"%08lx%08lx", |
87e43259 AC |
3729 | (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff)); |
3730 | return paddr_str; | |
3731 | } | |
3732 | ||
3733 | ||
2acd126a AC |
3734 | void |
3735 | pending_tick (SIM_DESC sd, | |
3736 | sim_cpu *cpu, | |
3737 | address_word cia) | |
3738 | { | |
3739 | if (PENDING_TRACE) | |
3740 | sim_io_printf (sd, "PENDING_DRAIN - pending_in = %d, pending_out = %d, pending_total = %d\n", PENDING_IN, PENDING_OUT, PENDING_TOTAL); | |
3741 | if (PENDING_OUT != PENDING_IN) | |
3742 | { | |
3743 | int loop; | |
3744 | int index = PENDING_OUT; | |
3745 | int total = PENDING_TOTAL; | |
3746 | if (PENDING_TOTAL == 0) | |
3747 | sim_engine_abort (SD, CPU, cia, "PENDING_DRAIN - Mis-match on pending update pointers\n"); | |
3748 | for (loop = 0; (loop < total); loop++) | |
3749 | { | |
3750 | if (PENDING_SLOT_DEST[index] != NULL) | |
3751 | { | |
3752 | PENDING_SLOT_DELAY[index] -= 1; | |
3753 | if (PENDING_SLOT_DELAY[index] == 0) | |
3754 | { | |
3755 | if (PENDING_SLOT_BIT[index] >= 0) | |
3756 | switch (PENDING_SLOT_SIZE[index]) | |
3757 | { | |
3758 | case 32: | |
3759 | if (PENDING_SLOT_VALUE[index]) | |
3760 | *(unsigned32*)PENDING_SLOT_DEST[index] |= | |
3761 | BIT32 (PENDING_SLOT_BIT[index]); | |
3762 | else | |
3763 | *(unsigned32*)PENDING_SLOT_DEST[index] &= | |
3764 | BIT32 (PENDING_SLOT_BIT[index]); | |
3765 | break; | |
3766 | case 64: | |
3767 | if (PENDING_SLOT_VALUE[index]) | |
3768 | *(unsigned64*)PENDING_SLOT_DEST[index] |= | |
3769 | BIT64 (PENDING_SLOT_BIT[index]); | |
3770 | else | |
3771 | *(unsigned64*)PENDING_SLOT_DEST[index] &= | |
3772 | BIT64 (PENDING_SLOT_BIT[index]); | |
3773 | break; | |
3774 | break; | |
3775 | } | |
3776 | else | |
3777 | switch (PENDING_SLOT_SIZE[index]) | |
3778 | { | |
3779 | case 32: | |
3780 | *(unsigned32*)PENDING_SLOT_DEST[index] = | |
3781 | PENDING_SLOT_VALUE[index]; | |
3782 | break; | |
3783 | case 64: | |
3784 | *(unsigned64*)PENDING_SLOT_DEST[index] = | |
3785 | PENDING_SLOT_VALUE[index]; | |
3786 | break; | |
3787 | } | |
3788 | } | |
3789 | if (PENDING_OUT == index) | |
3790 | { | |
3791 | PENDING_SLOT_DEST[index] = NULL; | |
3792 | PENDING_OUT = (PENDING_OUT + 1) % PSLOTS; | |
3793 | PENDING_TOTAL--; | |
3794 | } | |
3795 | } | |
3796 | } | |
3797 | index = (index + 1) % PSLOTS; | |
3798 | } | |
3799 | } | |
3800 | ||
8bae0a0c JSC |
3801 | /*---------------------------------------------------------------------------*/ |
3802 | /*> EOF interp.c <*/ |