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8bae0a0c JSC |
1 | /*> interp.c <*/ |
2 | /* Simulator for the MIPS architecture. | |
3 | ||
4 | This file is part of the MIPS sim | |
5 | ||
6 | THIS SOFTWARE IS NOT COPYRIGHTED | |
7 | ||
8 | Cygnus offers the following for use in the public domain. Cygnus | |
9 | makes no warranty with regard to the software or it's performance | |
10 | and the user accepts the software "AS IS" with all faults. | |
11 | ||
12 | CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO | |
13 | THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
14 | MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. | |
15 | ||
16 | $Revision$ | |
17 | $Author$ | |
e3d12c65 | 18 | $Date$ |
8bae0a0c JSC |
19 | |
20 | NOTEs: | |
21 | ||
22 | We only need to take account of the target endianness when moving data | |
23 | between the simulator and the host. We do not need to worry about the | |
24 | endianness of the host, since this sim code and GDB are executing in | |
25 | the same process. | |
26 | ||
27 | The IDT monitor (found on the VR4300 board), seems to lie about | |
28 | register contents. It seems to treat the registers as sign-extended | |
29 | 32-bit values. This cause *REAL* problems when single-stepping 64-bit | |
30 | code on the hardware. | |
31 | ||
32 | */ | |
33 | ||
e2f8ffb7 AC |
34 | /* The TRACE manifests enable the provision of extra features. If they |
35 | are not defined then a simpler (quicker) simulator is constructed | |
36 | without the required run-time checks, etc. */ | |
8bae0a0c JSC |
37 | #if 1 /* 0 to allow user build selection, 1 to force inclusion */ |
38 | #define TRACE (1) | |
8bae0a0c JSC |
39 | #endif |
40 | ||
2e61a3ad AC |
41 | #include "bfd.h" |
42 | #include "sim-main.h" | |
43 | #include "sim-utils.h" | |
44 | #include "sim-options.h" | |
50a2a691 | 45 | #include "sim-assert.h" |
2e61a3ad | 46 | |
4fa134be ILT |
47 | #include "config.h" |
48 | ||
8bae0a0c JSC |
49 | #include <stdio.h> |
50 | #include <stdarg.h> | |
51 | #include <ansidecl.h> | |
8bae0a0c JSC |
52 | #include <ctype.h> |
53 | #include <limits.h> | |
54 | #include <math.h> | |
4fa134be ILT |
55 | #ifdef HAVE_STDLIB_H |
56 | #include <stdlib.h> | |
57 | #endif | |
58 | #ifdef HAVE_STRING_H | |
59 | #include <string.h> | |
60 | #else | |
61 | #ifdef HAVE_STRINGS_H | |
62 | #include <strings.h> | |
63 | #endif | |
64 | #endif | |
8bae0a0c JSC |
65 | |
66 | #include "getopt.h" | |
67 | #include "libiberty.h" | |
9d52bcb7 | 68 | #include "bfd.h" |
8bae0a0c | 69 | #include "callback.h" /* GDB simulator callback interface */ |
e3d12c65 | 70 | #include "remote-sim.h" /* GDB simulator interface */ |
8bae0a0c | 71 | |
f24b7b69 JSC |
72 | #include "sysdep.h" |
73 | ||
53b9417e DE |
74 | #ifndef PARAMS |
75 | #define PARAMS(x) | |
76 | #endif | |
77 | ||
78 | char* pr_addr PARAMS ((SIM_ADDR addr)); | |
87e43259 | 79 | char* pr_uword64 PARAMS ((uword64 addr)); |
53b9417e | 80 | |
f24b7b69 | 81 | |
8bae0a0c JSC |
82 | /* Get the simulator engine description, without including the code: */ |
83 | #define SIM_MANIFESTS | |
284e759d | 84 | #include "oengine.c" |
8bae0a0c JSC |
85 | #undef SIM_MANIFESTS |
86 | ||
f7481d45 | 87 | |
8bae0a0c JSC |
88 | /* The following reserved instruction value is used when a simulator |
89 | trap is required. NOTE: Care must be taken, since this value may be | |
90 | used in later revisions of the MIPS ISA. */ | |
53b9417e DE |
91 | #define RSVD_INSTRUCTION (0x00000005) |
92 | #define RSVD_INSTRUCTION_MASK (0xFC00003F) | |
93 | ||
94 | #define RSVD_INSTRUCTION_ARG_SHIFT 6 | |
95 | #define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF | |
96 | ||
8bae0a0c | 97 | |
6eedf3f4 MA |
98 | /* Bits in the Debug register */ |
99 | #define Debug_DBD 0x80000000 /* Debug Branch Delay */ | |
100 | #define Debug_DM 0x40000000 /* Debug Mode */ | |
101 | #define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */ | |
102 | ||
103 | ||
104 | ||
8bae0a0c | 105 | |
8bae0a0c | 106 | |
e3d12c65 DE |
107 | /*---------------------------------------------------------------------------*/ |
108 | /*-- GDB simulator interface ------------------------------------------------*/ | |
109 | /*---------------------------------------------------------------------------*/ | |
110 | ||
0c2c5f61 AC |
111 | static void dotrace PARAMS((SIM_DESC sd,FILE *tracefh,int type,SIM_ADDR address,int width,char *comment,...)); |
112 | static void ColdReset PARAMS((SIM_DESC sd)); | |
18c64df6 | 113 | static long getnum PARAMS((SIM_DESC sd, char *value)); |
e3d12c65 | 114 | static unsigned int power2 PARAMS((unsigned int value)); |
18c64df6 | 115 | static void mips_size PARAMS((SIM_DESC sd, int n)); |
e3d12c65 DE |
116 | |
117 | /*---------------------------------------------------------------------------*/ | |
118 | ||
8bae0a0c | 119 | |
8bae0a0c | 120 | |
8bae0a0c | 121 | #define DELAYSLOT() {\ |
0c2c5f61 | 122 | if (STATE & simDELAYSLOT)\ |
18c64df6 | 123 | sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\ |
0c2c5f61 | 124 | STATE |= simDELAYSLOT;\ |
8bae0a0c JSC |
125 | } |
126 | ||
aaff8437 ILT |
127 | #define JALDELAYSLOT() {\ |
128 | DELAYSLOT ();\ | |
0c2c5f61 | 129 | STATE |= simJALDELAYSLOT;\ |
aaff8437 ILT |
130 | } |
131 | ||
8bae0a0c | 132 | #define NULLIFY() {\ |
0c2c5f61 AC |
133 | STATE &= ~simDELAYSLOT;\ |
134 | STATE |= simSKIPNEXT;\ | |
8bae0a0c JSC |
135 | } |
136 | ||
6eedf3f4 | 137 | #define CANCELDELAYSLOT() {\ |
0c2c5f61 AC |
138 | DSSTATE = 0;\ |
139 | STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\ | |
6eedf3f4 MA |
140 | } |
141 | ||
0c2c5f61 AC |
142 | #define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0) |
143 | #define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0) | |
aaff8437 | 144 | |
a9f7253f JSC |
145 | #define K0BASE (0x80000000) |
146 | #define K0SIZE (0x20000000) | |
147 | #define K1BASE (0xA0000000) | |
148 | #define K1SIZE (0x20000000) | |
525d929e AC |
149 | #define MONITOR_BASE (0xBFC00000) |
150 | #define MONITOR_SIZE (1 << 11) | |
151 | #define MEM_SIZE (2 << 20) | |
a9f7253f | 152 | |
8bae0a0c | 153 | /* Simple run-time monitor support */ |
4fa134be | 154 | static unsigned char *monitor = NULL; |
525d929e AC |
155 | static ut_reg monitor_base = MONITOR_BASE; |
156 | static unsigned monitor_size = MONITOR_SIZE; /* power-of-2 */ | |
8bae0a0c JSC |
157 | |
158 | #if defined(TRACE) | |
4fa134be ILT |
159 | static char *tracefile = "trace.din"; /* default filename for trace log */ |
160 | static FILE *tracefh = NULL; | |
18c64df6 | 161 | static void open_trace PARAMS((SIM_DESC sd)); |
8bae0a0c JSC |
162 | #endif /* TRACE */ |
163 | ||
22de994d AC |
164 | #define OPTION_DINERO_TRACE 200 |
165 | #define OPTION_DINERO_FILE 201 | |
166 | ||
50a2a691 AC |
167 | static SIM_RC |
168 | mips_option_handler (sd, opt, arg) | |
169 | SIM_DESC sd; | |
170 | int opt; | |
171 | char *arg; | |
2e61a3ad | 172 | { |
50a2a691 AC |
173 | switch (opt) |
174 | { | |
22de994d | 175 | case OPTION_DINERO_TRACE: /* ??? */ |
50a2a691 AC |
176 | #if defined(TRACE) |
177 | /* Eventually the simTRACE flag could be treated as a toggle, to | |
178 | allow external control of the program points being traced | |
179 | (i.e. only from main onwards, excluding the run-time setup, | |
180 | etc.). */ | |
181 | if (arg == NULL) | |
0c2c5f61 | 182 | STATE |= simTRACE; |
50a2a691 | 183 | else if (strcmp (arg, "yes") == 0) |
0c2c5f61 | 184 | STATE |= simTRACE; |
50a2a691 | 185 | else if (strcmp (arg, "no") == 0) |
0c2c5f61 | 186 | STATE &= ~simTRACE; |
22de994d AC |
187 | else if (strcmp (arg, "on") == 0) |
188 | STATE |= simTRACE; | |
189 | else if (strcmp (arg, "off") == 0) | |
190 | STATE &= ~simTRACE; | |
50a2a691 AC |
191 | else |
192 | { | |
22de994d | 193 | fprintf (stderr, "Unreconized dinero-trace option `%s'\n", arg); |
50a2a691 AC |
194 | return SIM_RC_FAIL; |
195 | } | |
196 | return SIM_RC_OK; | |
197 | #else /* !TRACE */ | |
198 | fprintf(stderr,"\ | |
22de994d | 199 | Simulator constructed without dinero tracing support (for performance).\n\ |
50a2a691 AC |
200 | Re-compile simulator with \"-DTRACE\" to enable this option.\n"); |
201 | return SIM_RC_FAIL; | |
202 | #endif /* !TRACE */ | |
203 | ||
22de994d | 204 | case OPTION_DINERO_FILE: |
50a2a691 AC |
205 | #if defined(TRACE) |
206 | if (optarg != NULL) { | |
207 | char *tmp; | |
208 | tmp = (char *)malloc(strlen(optarg) + 1); | |
209 | if (tmp == NULL) | |
210 | { | |
18c64df6 | 211 | sim_io_printf(sd,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg); |
50a2a691 AC |
212 | return SIM_RC_FAIL; |
213 | } | |
214 | else { | |
215 | strcpy(tmp,optarg); | |
216 | tracefile = tmp; | |
18c64df6 | 217 | sim_io_printf(sd,"Placing trace information into file \"%s\"\n",tracefile); |
50a2a691 AC |
218 | } |
219 | } | |
220 | #endif /* TRACE */ | |
221 | return SIM_RC_OK; | |
222 | ||
50a2a691 AC |
223 | } |
224 | ||
225 | return SIM_RC_OK; | |
2e61a3ad | 226 | } |
50a2a691 AC |
227 | |
228 | static const OPTION mips_options[] = | |
2e61a3ad | 229 | { |
22de994d AC |
230 | { {"dinero-trace", optional_argument, NULL, OPTION_DINERO_TRACE}, |
231 | '\0', "on|off", "Enable dinero tracing", | |
50a2a691 | 232 | mips_option_handler }, |
22de994d AC |
233 | { {"dinero-file", required_argument, NULL, OPTION_DINERO_FILE}, |
234 | '\0', "FILE", "Write dinero trace to FILE", | |
50a2a691 | 235 | mips_option_handler }, |
50a2a691 AC |
236 | { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL } |
237 | }; | |
238 | ||
239 | ||
56e7c849 AC |
240 | int interrupt_pending; |
241 | ||
50a2a691 AC |
242 | static void |
243 | interrupt_event (SIM_DESC sd, void *data) | |
2e61a3ad | 244 | { |
56e7c849 AC |
245 | if (SR & status_IE) |
246 | { | |
247 | interrupt_pending = 0; | |
18c64df6 | 248 | SignalExceptionInterrupt (); |
56e7c849 AC |
249 | } |
250 | else if (!interrupt_pending) | |
251 | sim_events_schedule (sd, 1, interrupt_event, data); | |
2e61a3ad | 252 | } |
f7481d45 | 253 | |
f7481d45 | 254 | |
50a2a691 | 255 | |
8bae0a0c JSC |
256 | /*---------------------------------------------------------------------------*/ |
257 | /*-- GDB simulator interface ------------------------------------------------*/ | |
258 | /*---------------------------------------------------------------------------*/ | |
259 | ||
53b9417e | 260 | SIM_DESC |
247fccde | 261 | sim_open (kind, cb, abfd, argv) |
87e43259 | 262 | SIM_OPEN_KIND kind; |
50a2a691 | 263 | host_callback *cb; |
247fccde | 264 | struct _bfd *abfd; |
53b9417e | 265 | char **argv; |
8bae0a0c | 266 | { |
18c64df6 | 267 | SIM_DESC sd = sim_state_alloc (kind, cb); |
0c2c5f61 | 268 | sim_cpu *cpu = STATE_CPU (sd, 0); |
2e61a3ad | 269 | |
525d929e AC |
270 | SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); |
271 | ||
50a2a691 AC |
272 | /* FIXME: watchpoints code shouldn't need this */ |
273 | STATE_WATCHPOINTS (sd)->pc = &(PC); | |
274 | STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC); | |
275 | STATE_WATCHPOINTS (sd)->interrupt_handler = interrupt_event; | |
276 | ||
277 | /* memory defaults (unless sim_size was here first) */ | |
278 | if (STATE_MEM_SIZE (sd) == 0) | |
525d929e | 279 | STATE_MEM_SIZE (sd) = MEM_SIZE; |
50a2a691 AC |
280 | STATE_MEM_BASE (sd) = K1BASE; |
281 | ||
0c2c5f61 | 282 | STATE = 0; |
50a2a691 | 283 | |
2e61a3ad AC |
284 | if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK) |
285 | return 0; | |
50a2a691 | 286 | sim_add_option_table (sd, mips_options); |
2e61a3ad | 287 | |
2e61a3ad AC |
288 | /* getopt will print the error message so we just have to exit if this fails. |
289 | FIXME: Hmmm... in the case of gdb we need getopt to call | |
290 | print_filtered. */ | |
291 | if (sim_parse_args (sd, argv) != SIM_RC_OK) | |
292 | { | |
293 | /* Uninstall the modules to avoid memory leaks, | |
294 | file descriptor leaks, etc. */ | |
295 | sim_module_uninstall (sd); | |
296 | return 0; | |
297 | } | |
2e61a3ad | 298 | |
fafce69a AC |
299 | /* check for/establish the a reference program image */ |
300 | if (sim_analyze_program (sd, | |
301 | (STATE_PROG_ARGV (sd) != NULL | |
302 | ? *STATE_PROG_ARGV (sd) | |
303 | : NULL), | |
304 | abfd) != SIM_RC_OK) | |
305 | { | |
306 | sim_module_uninstall (sd); | |
307 | return 0; | |
308 | } | |
309 | ||
247fccde AC |
310 | /* Configure/verify the target byte order and other runtime |
311 | configuration options */ | |
fafce69a | 312 | if (sim_config (sd) != SIM_RC_OK) |
247fccde AC |
313 | { |
314 | sim_module_uninstall (sd); | |
315 | return 0; | |
316 | } | |
317 | ||
2e61a3ad AC |
318 | if (sim_post_argv_init (sd) != SIM_RC_OK) |
319 | { | |
320 | /* Uninstall the modules to avoid memory leaks, | |
321 | file descriptor leaks, etc. */ | |
322 | sim_module_uninstall (sd); | |
323 | return 0; | |
324 | } | |
325 | ||
50a2a691 AC |
326 | /* verify assumptions the simulator made about the host type system. |
327 | This macro does not return if there is a problem */ | |
18c64df6 AC |
328 | if (sizeof(int) != (4 * sizeof(char))) |
329 | SignalExceptionSimulatorFault ("sizeof(int) != 4"); | |
330 | if (sizeof(word64) != (8 * sizeof(char))) | |
331 | SignalExceptionSimulatorFault ("sizeof(word64) != 8"); | |
8bae0a0c | 332 | |
8bae0a0c JSC |
333 | #if defined(HASFPU) |
334 | /* Check that the host FPU conforms to IEEE 754-1985 for the SINGLE | |
335 | and DOUBLE binary formats. This is a bit nasty, requiring that we | |
336 | trust the explicit manifests held in the source: */ | |
50a2a691 AC |
337 | /* TODO: We need to cope with the simulated target and the host not |
338 | having the same endianness. This will require the high and low | |
339 | words of a (double) to be swapped when converting between the | |
340 | host and the simulated target. */ | |
8bae0a0c | 341 | { |
50a2a691 AC |
342 | union { |
343 | unsigned int i[2]; | |
344 | double d; | |
345 | float f[2]; | |
346 | } s; | |
347 | ||
348 | s.d = (double)523.2939453125; | |
349 | ||
350 | if ((s.i[0] == 0 && (s.f[1] != (float)4.01102924346923828125 | |
351 | || s.i[1] != 0x40805A5A)) | |
352 | || (s.i[1] == 0 && (s.f[0] != (float)4.01102924346923828125 | |
353 | || s.i[0] != 0x40805A5A))) | |
354 | { | |
355 | fprintf(stderr,"The host executing the simulator does not seem to have IEEE 754-1985 std FP\n"); | |
356 | return 0; | |
357 | } | |
8bae0a0c JSC |
358 | } |
359 | #endif /* HASFPU */ | |
360 | ||
361 | /* This is NASTY, in that we are assuming the size of specific | |
362 | registers: */ | |
363 | { | |
364 | int rn; | |
365 | for (rn = 0; (rn < (LAST_EMBED_REGNUM + 1)); rn++) { | |
366 | if (rn < 32) | |
0c2c5f61 | 367 | cpu->register_widths[rn] = GPRLEN; |
8bae0a0c | 368 | else if ((rn >= FGRIDX) && (rn < (FGRIDX + 32))) |
0c2c5f61 | 369 | cpu->register_widths[rn] = GPRLEN; |
8bae0a0c | 370 | else if ((rn >= 33) && (rn <= 37)) |
0c2c5f61 | 371 | cpu->register_widths[rn] = GPRLEN; |
8bae0a0c | 372 | else if ((rn == SRIDX) || (rn == FCR0IDX) || (rn == FCR31IDX) || ((rn >= 72) && (rn <= 89))) |
0c2c5f61 | 373 | cpu->register_widths[rn] = 32; |
8bae0a0c | 374 | else |
0c2c5f61 | 375 | cpu->register_widths[rn] = 0; |
8bae0a0c | 376 | } |
18c64df6 AC |
377 | /* start-sanitize-r5900 */ |
378 | ||
379 | /* set the 5900 "upper" registers to 64 bits */ | |
380 | for( rn = LAST_EMBED_REGNUM+1; rn < NUM_REGS; rn++) | |
0c2c5f61 | 381 | cpu->register_widths[rn] = 64; |
18c64df6 | 382 | /* end-sanitize-r5900 */ |
8bae0a0c JSC |
383 | } |
384 | ||
8bae0a0c | 385 | |
50a2a691 AC |
386 | /* FIXME: In the future both of these malloc's can be replaced by |
387 | calls to sim-core. */ | |
9d52bcb7 | 388 | |
8bae0a0c JSC |
389 | /* If the host has "mmap" available we could use it to provide a |
390 | very large virtual address space for the simulator, since memory | |
391 | would only be allocated within the "mmap" space as it is | |
392 | accessed. This can also be linked to the architecture specific | |
393 | support, required to simulate the MMU. */ | |
18c64df6 | 394 | mips_size(sd, STATE_MEM_SIZE (sd)); |
50a2a691 | 395 | /* NOTE: The above will also have enabled any profiling state! */ |
18c64df6 | 396 | |
50a2a691 | 397 | /* Create the monitor address space as well */ |
8bae0a0c | 398 | monitor = (unsigned char *)calloc(1,monitor_size); |
50a2a691 AC |
399 | if (!monitor) |
400 | fprintf(stderr,"Not enough VM for monitor simulation (%d bytes)\n", | |
401 | monitor_size); | |
8bae0a0c JSC |
402 | |
403 | #if defined(TRACE) | |
0c2c5f61 | 404 | if (STATE & simTRACE) |
18c64df6 | 405 | open_trace(sd); |
8bae0a0c JSC |
406 | #endif /* TRACE */ |
407 | ||
fafce69a AC |
408 | /* Write the monitor trap address handlers into the monitor (eeprom) |
409 | address space. This can only be done once the target endianness | |
410 | has been determined. */ | |
411 | { | |
412 | unsigned loop; | |
413 | /* Entry into the IDT monitor is via fixed address vectors, and | |
414 | not using machine instructions. To avoid clashing with use of | |
415 | the MIPS TRAP system, we place our own (simulator specific) | |
416 | "undefined" instructions into the relevant vector slots. */ | |
525d929e AC |
417 | for (loop = 0; (loop < MONITOR_SIZE); loop += 4) |
418 | { | |
419 | address_word vaddr = (MONITOR_BASE + loop); | |
420 | unsigned32 insn = (RSVD_INSTRUCTION | (((loop >> 2) & RSVD_INSTRUCTION_ARG_MASK) << RSVD_INSTRUCTION_ARG_SHIFT)); | |
421 | H2T (insn); | |
422 | sim_write (sd, vaddr, (char *)&insn, sizeof (insn)); | |
423 | } | |
fafce69a AC |
424 | /* The PMON monitor uses the same address space, but rather than |
425 | branching into it the address of a routine is loaded. We can | |
426 | cheat for the moment, and direct the PMON routine to IDT style | |
427 | instructions within the monitor space. This relies on the IDT | |
428 | monitor not using the locations from 0xBFC00500 onwards as its | |
429 | entry points.*/ | |
430 | for (loop = 0; (loop < 24); loop++) | |
431 | { | |
525d929e AC |
432 | address_word vaddr = (MONITOR_BASE + 0x500 + (loop * 4)); |
433 | unsigned32 value = ((0x500 - 8) / 8); /* default UNDEFINED reason code */ | |
fafce69a AC |
434 | switch (loop) |
435 | { | |
436 | case 0: /* read */ | |
437 | value = 7; | |
438 | break; | |
fafce69a AC |
439 | case 1: /* write */ |
440 | value = 8; | |
441 | break; | |
fafce69a AC |
442 | case 2: /* open */ |
443 | value = 6; | |
444 | break; | |
fafce69a AC |
445 | case 3: /* close */ |
446 | value = 10; | |
447 | break; | |
fafce69a AC |
448 | case 5: /* printf */ |
449 | value = ((0x500 - 16) / 8); /* not an IDT reason code */ | |
450 | break; | |
fafce69a AC |
451 | case 8: /* cliexit */ |
452 | value = 17; | |
453 | break; | |
fafce69a AC |
454 | case 11: /* flush_cache */ |
455 | value = 28; | |
456 | break; | |
457 | } | |
525d929e AC |
458 | /* FIXME - should monitor_base be SIM_ADDR?? */ |
459 | value = ((unsigned int)MONITOR_BASE + (value * 8)); | |
460 | H2T (value); | |
461 | sim_write (sd, vaddr, (char *)&value, sizeof (value)); | |
fafce69a AC |
462 | |
463 | /* The LSI MiniRISC PMON has its vectors at 0x200, not 0x500. */ | |
464 | vaddr -= 0x300; | |
525d929e | 465 | sim_write (sd, vaddr, (char *)&value, sizeof (value)); |
fafce69a AC |
466 | } |
467 | } | |
468 | ||
2e61a3ad | 469 | return sd; |
8bae0a0c JSC |
470 | } |
471 | ||
6429b296 JW |
472 | #if defined(TRACE) |
473 | static void | |
18c64df6 AC |
474 | open_trace(sd) |
475 | SIM_DESC sd; | |
6429b296 JW |
476 | { |
477 | tracefh = fopen(tracefile,"wb+"); | |
478 | if (tracefh == NULL) | |
479 | { | |
18c64df6 | 480 | sim_io_eprintf(sd,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile); |
6429b296 JW |
481 | tracefh = stderr; |
482 | } | |
483 | } | |
484 | #endif /* TRACE */ | |
485 | ||
8bae0a0c | 486 | void |
53b9417e DE |
487 | sim_close (sd, quitting) |
488 | SIM_DESC sd; | |
8bae0a0c JSC |
489 | int quitting; |
490 | { | |
491 | #ifdef DEBUG | |
492 | printf("DBG: sim_close: entered (quitting = %d)\n",quitting); | |
493 | #endif | |
494 | ||
8bae0a0c JSC |
495 | /* "quitting" is non-zero if we cannot hang on errors */ |
496 | ||
497 | /* Ensure that any resources allocated through the callback | |
498 | mechanism are released: */ | |
18c64df6 | 499 | sim_io_shutdown (sd); |
8bae0a0c | 500 | |
8bae0a0c | 501 | #if defined(TRACE) |
e3d12c65 | 502 | if (tracefh != NULL && tracefh != stderr) |
8bae0a0c | 503 | fclose(tracefh); |
e3d12c65 | 504 | tracefh = NULL; |
0c2c5f61 | 505 | STATE &= ~simTRACE; |
8bae0a0c JSC |
506 | #endif /* TRACE */ |
507 | ||
50a2a691 AC |
508 | if (STATE_MEMORY (sd) != NULL) |
509 | free(STATE_MEMORY (sd)); /* cfree not available on all hosts */ | |
510 | STATE_MEMORY (sd) = NULL; | |
8bae0a0c JSC |
511 | |
512 | return; | |
513 | } | |
514 | ||
8bae0a0c JSC |
515 | |
516 | int | |
53b9417e DE |
517 | sim_write (sd,addr,buffer,size) |
518 | SIM_DESC sd; | |
8bae0a0c JSC |
519 | SIM_ADDR addr; |
520 | unsigned char *buffer; | |
521 | int size; | |
522 | { | |
525d929e | 523 | int index; |
8bae0a0c JSC |
524 | |
525 | /* Return the number of bytes written, or zero if error. */ | |
526 | #ifdef DEBUG | |
18c64df6 | 527 | sim_io_printf(sd,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr),size); |
8bae0a0c JSC |
528 | #endif |
529 | ||
525d929e AC |
530 | /* We use raw read and write routines, since we do not want to count |
531 | the GDB memory accesses in our statistics gathering. */ | |
532 | ||
533 | for (index = 0; index < size; index++) | |
534 | { | |
535 | address_word vaddr = (address_word)addr + index; | |
536 | address_word paddr; | |
537 | int cca; | |
538 | if (!AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &cca, isTARGET, isRAW)) | |
539 | break; | |
540 | StoreMemory (cca, AccessLength_BYTE, buffer[index], 0, paddr, vaddr, isRAW); | |
8bae0a0c | 541 | } |
8bae0a0c | 542 | |
525d929e | 543 | return(index); |
8bae0a0c JSC |
544 | } |
545 | ||
546 | int | |
53b9417e DE |
547 | sim_read (sd,addr,buffer,size) |
548 | SIM_DESC sd; | |
8bae0a0c JSC |
549 | SIM_ADDR addr; |
550 | unsigned char *buffer; | |
551 | int size; | |
552 | { | |
553 | int index; | |
554 | ||
555 | /* Return the number of bytes read, or zero if error. */ | |
556 | #ifdef DEBUG | |
18c64df6 | 557 | sim_io_printf(sd,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr),size); |
8bae0a0c JSC |
558 | #endif /* DEBUG */ |
559 | ||
525d929e AC |
560 | for (index = 0; (index < size); index++) |
561 | { | |
562 | address_word vaddr = (address_word)addr + index; | |
563 | address_word paddr; | |
564 | unsigned64 value; | |
565 | int cca; | |
566 | if (!AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &cca, isTARGET, isRAW)) | |
567 | break; | |
568 | LoadMemory (&value, NULL, cca, AccessLength_BYTE, paddr, vaddr, isDATA, isRAW); | |
8bae0a0c | 569 | buffer[index] = (unsigned char)(value&0xFF); |
525d929e | 570 | } |
8bae0a0c JSC |
571 | |
572 | return(index); | |
573 | } | |
574 | ||
575 | void | |
53b9417e DE |
576 | sim_store_register (sd,rn,memory) |
577 | SIM_DESC sd; | |
8bae0a0c JSC |
578 | int rn; |
579 | unsigned char *memory; | |
580 | { | |
0c2c5f61 | 581 | sim_cpu *cpu = STATE_CPU (sd, 0); |
50a2a691 AC |
582 | /* NOTE: gdb (the client) stores registers in target byte order |
583 | while the simulator uses host byte order */ | |
8bae0a0c | 584 | #ifdef DEBUG |
18c64df6 | 585 | sim_io_printf(sd,"sim_store_register(%d,*memory=0x%s);\n",rn,pr_addr(*((SIM_ADDR *)memory))); |
8bae0a0c JSC |
586 | #endif /* DEBUG */ |
587 | ||
588 | /* Unfortunately this suffers from the same problem as the register | |
589 | numbering one. We need to know what the width of each logical | |
590 | register number is for the architecture being simulated. */ | |
50a2a691 | 591 | |
0c2c5f61 | 592 | if (cpu->register_widths[rn] == 0) |
18c64df6 AC |
593 | sim_io_eprintf(sd,"Invalid register width for %d (register store ignored)\n",rn); |
594 | /* start-sanitize-r5900 */ | |
595 | else if (rn == REGISTER_SA) | |
596 | SA = T2H_8(*(uword64*)memory); | |
597 | else if (rn > LAST_EMBED_REGNUM) | |
0c2c5f61 | 598 | cpu->registers1[rn - LAST_EMBED_REGNUM - 1] = T2H_8(*(uword64*)memory); |
18c64df6 | 599 | /* end-sanitize-r5900 */ |
0c2c5f61 AC |
600 | else if (cpu->register_widths[rn] == 32) |
601 | cpu->registers[rn] = T2H_4 (*(unsigned int*)memory); | |
50a2a691 | 602 | else |
0c2c5f61 | 603 | cpu->registers[rn] = T2H_8 (*(uword64*)memory); |
8bae0a0c JSC |
604 | |
605 | return; | |
606 | } | |
607 | ||
608 | void | |
53b9417e DE |
609 | sim_fetch_register (sd,rn,memory) |
610 | SIM_DESC sd; | |
8bae0a0c JSC |
611 | int rn; |
612 | unsigned char *memory; | |
613 | { | |
0c2c5f61 | 614 | sim_cpu *cpu = STATE_CPU (sd, 0); |
50a2a691 AC |
615 | /* NOTE: gdb (the client) stores registers in target byte order |
616 | while the simulator uses host byte order */ | |
8bae0a0c | 617 | #ifdef DEBUG |
18c64df6 | 618 | sim_io_printf(sd,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn,pr_addr(registers[rn])); |
8bae0a0c JSC |
619 | #endif /* DEBUG */ |
620 | ||
0c2c5f61 | 621 | if (cpu->register_widths[rn] == 0) |
18c64df6 AC |
622 | sim_io_eprintf(sd,"Invalid register width for %d (register fetch ignored)\n",rn); |
623 | /* start-sanitize-r5900 */ | |
624 | else if (rn == REGISTER_SA) | |
625 | *((uword64 *)memory) = H2T_8(SA); | |
626 | else if (rn > LAST_EMBED_REGNUM) | |
0c2c5f61 | 627 | *((uword64 *)memory) = H2T_8(cpu->registers1[rn - LAST_EMBED_REGNUM - 1]); |
18c64df6 | 628 | /* end-sanitize-r5900 */ |
0c2c5f61 AC |
629 | else if (cpu->register_widths[rn] == 32) |
630 | *((unsigned int *)memory) = H2T_4 ((unsigned int)(cpu->registers[rn] & 0xFFFFFFFF)); | |
18c64df6 | 631 | else /* 64bit register */ |
0c2c5f61 | 632 | *((uword64 *)memory) = H2T_8 (cpu->registers[rn]); |
50a2a691 | 633 | |
8bae0a0c JSC |
634 | return; |
635 | } | |
50a2a691 | 636 | |
8bae0a0c JSC |
637 | |
638 | void | |
53b9417e DE |
639 | sim_info (sd,verbose) |
640 | SIM_DESC sd; | |
8bae0a0c JSC |
641 | int verbose; |
642 | { | |
643 | /* Accessed from the GDB "info files" command: */ | |
56e7c849 AC |
644 | if (STATE_VERBOSE_P (sd) || verbose) |
645 | { | |
646 | ||
647 | sim_io_printf (sd, "MIPS %d-bit %s endian simulator\n", | |
648 | (PROCESSOR_64BIT ? 64 : 32), | |
649 | (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN ? "Big" : "Little")); | |
650 | ||
651 | sim_io_printf (sd, "0x%08X bytes of memory at 0x%s\n", | |
652 | STATE_MEM_SIZE (sd), | |
653 | pr_addr (STATE_MEM_BASE (sd))); | |
654 | ||
8bae0a0c | 655 | #if !defined(FASTSIM) |
56e7c849 AC |
656 | /* It would be a useful feature, if when performing multi-cycle |
657 | simulations (rather than single-stepping) we keep the start and | |
658 | end times of the execution, so that we can give a performance | |
659 | figure for the simulator. */ | |
8bae0a0c | 660 | #endif /* !FASTSIM */ |
56e7c849 AC |
661 | sim_io_printf (sd, "Number of execution cycles = %ld\n", |
662 | (long) sim_events_time (sd)); | |
663 | ||
664 | /* print information pertaining to MIPS ISA and architecture being simulated */ | |
665 | /* things that may be interesting */ | |
666 | /* instructions executed - if available */ | |
667 | /* cycles executed - if available */ | |
668 | /* pipeline stalls - if available */ | |
669 | /* virtual time taken */ | |
670 | /* profiling size */ | |
671 | /* profiling frequency */ | |
672 | /* profile minpc */ | |
673 | /* profile maxpc */ | |
674 | } | |
aa324b9b | 675 | profile_print (sd, STATE_VERBOSE_P (sd), NULL, NULL); |
8bae0a0c JSC |
676 | } |
677 | ||
8bae0a0c | 678 | |
9d52bcb7 | 679 | SIM_RC |
fafce69a | 680 | sim_create_inferior (sd, abfd, argv,env) |
53b9417e | 681 | SIM_DESC sd; |
fafce69a | 682 | struct _bfd *abfd; |
8bae0a0c JSC |
683 | char **argv; |
684 | char **env; | |
685 | { | |
50a2a691 | 686 | |
8bae0a0c | 687 | #ifdef DEBUG |
9d52bcb7 DE |
688 | printf("DBG: sim_create_inferior entered: start_address = 0x%s\n", |
689 | pr_addr(PC)); | |
8bae0a0c JSC |
690 | #endif /* DEBUG */ |
691 | ||
0c2c5f61 | 692 | ColdReset(sd); |
50a2a691 | 693 | |
fafce69a | 694 | if (abfd != NULL) |
dad6f1f3 AC |
695 | /* override PC value set by ColdReset () */ |
696 | PC = (unsigned64) bfd_get_start_address (abfd); | |
2e61a3ad | 697 | |
f24b7b69 | 698 | #if 0 /* def DEBUG */ |
dad6f1f3 | 699 | if (argv || env) |
8bae0a0c | 700 | { |
dad6f1f3 AC |
701 | /* We should really place the argv slot values into the argument |
702 | registers, and onto the stack as required. However, this | |
703 | assumes that we have a stack defined, which is not | |
704 | necessarily true at the moment. */ | |
705 | char **cptr; | |
706 | sim_io_printf(sd,"sim_create_inferior() : passed arguments ignored\n"); | |
707 | for (cptr = argv; (cptr && *cptr); cptr++) | |
708 | printf("DBG: arg \"%s\"\n",*cptr); | |
8bae0a0c JSC |
709 | } |
710 | #endif /* DEBUG */ | |
8bae0a0c | 711 | |
9d52bcb7 | 712 | return SIM_RC_OK; |
8bae0a0c JSC |
713 | } |
714 | ||
8bae0a0c JSC |
715 | typedef enum {e_terminate,e_help,e_setmemsize,e_reset} e_cmds; |
716 | ||
717 | static struct t_sim_command { | |
718 | e_cmds id; | |
719 | const char *name; | |
720 | const char *help; | |
721 | } sim_commands[] = { | |
722 | {e_help, "help", ": Show MIPS simulator private commands"}, | |
723 | {e_setmemsize,"set-memory-size","<n> : Specify amount of memory simulated"}, | |
724 | {e_reset, "reset-system", ": Reset the simulated processor"}, | |
725 | {e_terminate, NULL} | |
726 | }; | |
727 | ||
728 | void | |
53b9417e DE |
729 | sim_do_command (sd,cmd) |
730 | SIM_DESC sd; | |
8bae0a0c JSC |
731 | char *cmd; |
732 | { | |
733 | struct t_sim_command *cptr; | |
734 | ||
735 | if (!(cmd && *cmd != '\0')) | |
736 | cmd = "help"; | |
737 | ||
738 | /* NOTE: Accessed from the GDB "sim" commmand: */ | |
739 | for (cptr = sim_commands; cptr && cptr->name; cptr++) | |
2f2e6c5d AC |
740 | if (strncmp (cmd, cptr->name, strlen(cptr->name)) == 0) |
741 | { | |
742 | cmd += strlen(cptr->name); | |
743 | switch (cptr->id) { | |
744 | case e_help: /* no arguments */ | |
745 | { /* no arguments */ | |
746 | struct t_sim_command *lptr; | |
18c64df6 | 747 | sim_io_printf(sd,"List of MIPS simulator commands:\n"); |
2f2e6c5d | 748 | for (lptr = sim_commands; lptr->name; lptr++) |
18c64df6 | 749 | sim_io_printf(sd,"%s %s\n",lptr->name,lptr->help); |
2f2e6c5d AC |
750 | sim_args_command (sd, "help"); |
751 | } | |
8bae0a0c JSC |
752 | break; |
753 | ||
2f2e6c5d AC |
754 | case e_setmemsize: /* memory size argument */ |
755 | { | |
18c64df6 AC |
756 | unsigned int newsize = (unsigned int)getnum(sd, cmd); |
757 | mips_size(sd, newsize); | |
2f2e6c5d | 758 | } |
8bae0a0c JSC |
759 | break; |
760 | ||
2f2e6c5d | 761 | case e_reset: /* no arguments */ |
0c2c5f61 | 762 | ColdReset(sd); |
2f2e6c5d AC |
763 | /* NOTE: See the comments in sim_open() relating to device |
764 | initialisation. */ | |
765 | break; | |
8bae0a0c | 766 | |
2f2e6c5d | 767 | default: |
18c64df6 | 768 | sim_io_printf(sd,"FATAL: Matched \"%s\", but failed to match command id %d.\n",cmd,cptr->id); |
2f2e6c5d AC |
769 | break; |
770 | } | |
771 | break; | |
772 | } | |
8bae0a0c JSC |
773 | |
774 | if (!(cptr->name)) | |
2f2e6c5d AC |
775 | { |
776 | /* try for a common command when the sim specific lookup fails */ | |
777 | if (sim_args_command (sd, cmd) != SIM_RC_OK) | |
18c64df6 | 778 | sim_io_printf(sd,"Error: \"%s\" is not a valid MIPS simulator command.\n",cmd); |
2f2e6c5d | 779 | } |
8bae0a0c JSC |
780 | |
781 | return; | |
782 | } | |
783 | ||
784 | /*---------------------------------------------------------------------------*/ | |
785 | /* NOTE: The following routines do not seem to be used by GDB at the | |
786 | moment. However, they may be useful to the standalone simulator | |
787 | world. */ | |
788 | ||
789 | ||
18c64df6 AC |
790 | static void |
791 | mips_size(sd, newsize) | |
792 | SIM_DESC sd; | |
87e43259 | 793 | int newsize; |
8bae0a0c JSC |
794 | { |
795 | char *new; | |
796 | /* Used by "run", and internally, to set the simulated memory size */ | |
f24b7b69 | 797 | if (newsize == 0) { |
18c64df6 | 798 | sim_io_printf(sd,"Zero not valid: Memory size still 0x%08X bytes\n",STATE_MEM_SIZE (sd)); |
f24b7b69 JSC |
799 | return; |
800 | } | |
8bae0a0c | 801 | newsize = power2(newsize); |
50a2a691 AC |
802 | if (STATE_MEMORY (sd) == NULL) |
803 | new = (char *)calloc(64,(STATE_MEM_SIZE (sd) / 64)); | |
8bae0a0c | 804 | else |
50a2a691 | 805 | new = (char *)realloc(STATE_MEMORY (sd),newsize); |
8bae0a0c | 806 | if (new == NULL) { |
50a2a691 | 807 | if (STATE_MEMORY (sd) == NULL) |
18c64df6 | 808 | sim_io_error(sd,"Not enough VM for simulation memory of 0x%08X bytes",STATE_MEM_SIZE (sd)); |
8bae0a0c | 809 | else |
18c64df6 | 810 | sim_io_eprintf(sd,"Failed to resize memory (still 0x%08X bytes)\n",STATE_MEM_SIZE (sd)); |
8bae0a0c | 811 | } else { |
50a2a691 AC |
812 | STATE_MEM_SIZE (sd) = (unsigned)newsize; |
813 | STATE_MEMORY (sd) = new; | |
8bae0a0c | 814 | } |
8bae0a0c JSC |
815 | return; |
816 | } | |
817 | ||
8bae0a0c JSC |
818 | |
819 | /*---------------------------------------------------------------------------*/ | |
820 | /*-- Private simulator support interface ------------------------------------*/ | |
821 | /*---------------------------------------------------------------------------*/ | |
822 | ||
525d929e AC |
823 | /* Read a null terminated string from memory, return in a buffer */ |
824 | static char * | |
825 | fetch_str (sd, addr) | |
826 | SIM_DESC sd; | |
827 | address_word addr; | |
828 | { | |
829 | char *buf; | |
830 | int nr = 0; | |
831 | char null; | |
832 | while (sim_read (sd, addr + nr, &null, 1) == 1 && null != 0) | |
833 | nr++; | |
834 | buf = NZALLOC (char, nr + 1); | |
835 | sim_read (sd, addr, buf, nr); | |
836 | return buf; | |
837 | } | |
838 | ||
a9f7253f | 839 | /* Simple monitor interface (currently setup for the IDT and PMON monitors) */ |
8bae0a0c | 840 | static void |
18c64df6 AC |
841 | sim_monitor(sd,reason) |
842 | SIM_DESC sd; | |
8bae0a0c JSC |
843 | unsigned int reason; |
844 | { | |
53b9417e DE |
845 | #ifdef DEBUG |
846 | printf("DBG: sim_monitor: entered (reason = %d)\n",reason); | |
847 | #endif /* DEBUG */ | |
848 | ||
8bae0a0c JSC |
849 | /* The IDT monitor actually allows two instructions per vector |
850 | slot. However, the simulator currently causes a trap on each | |
851 | individual instruction. We cheat, and lose the bottom bit. */ | |
852 | reason >>= 1; | |
853 | ||
854 | /* The following callback functions are available, however the | |
855 | monitor we are simulating does not make use of them: get_errno, | |
856 | isatty, lseek, rename, system, time and unlink */ | |
525d929e AC |
857 | switch (reason) |
858 | { | |
859 | ||
8bae0a0c JSC |
860 | case 6: /* int open(char *path,int flags) */ |
861 | { | |
525d929e AC |
862 | char *path = fetch_str (sd, A0); |
863 | V0 = sim_io_open (sd, path, (int)A1); | |
864 | zfree (path); | |
865 | break; | |
8bae0a0c | 866 | } |
8bae0a0c JSC |
867 | |
868 | case 7: /* int read(int file,char *ptr,int len) */ | |
869 | { | |
525d929e AC |
870 | int fd = A0; |
871 | int nr = A2; | |
872 | char *buf = zalloc (nr); | |
873 | V0 = sim_io_read (sd, fd, buf, nr); | |
874 | sim_write (sd, A1, buf, nr); | |
875 | zfree (buf); | |
8bae0a0c JSC |
876 | } |
877 | break; | |
878 | ||
879 | case 8: /* int write(int file,char *ptr,int len) */ | |
880 | { | |
525d929e AC |
881 | int fd = A0; |
882 | int nr = A2; | |
883 | char *buf = zalloc (nr); | |
884 | sim_read (sd, A1, buf, nr); | |
885 | V0 = sim_io_write (sd, fd, buf, nr); | |
886 | zfree (buf); | |
887 | break; | |
8bae0a0c | 888 | } |
8bae0a0c JSC |
889 | |
890 | case 10: /* int close(int file) */ | |
525d929e AC |
891 | { |
892 | V0 = sim_io_close (sd, (int)A0); | |
893 | break; | |
894 | } | |
8bae0a0c JSC |
895 | |
896 | case 11: /* char inbyte(void) */ | |
897 | { | |
898 | char tmp; | |
525d929e AC |
899 | if (sim_io_read_stdin (sd, &tmp, sizeof(char)) != sizeof(char)) |
900 | { | |
901 | sim_io_error(sd,"Invalid return from character read"); | |
902 | V0 = (ut_reg)-1; | |
903 | } | |
8bae0a0c | 904 | else |
525d929e AC |
905 | V0 = (ut_reg)tmp; |
906 | break; | |
8bae0a0c | 907 | } |
8bae0a0c JSC |
908 | |
909 | case 12: /* void outbyte(char chr) : write a byte to "stdout" */ | |
910 | { | |
911 | char tmp = (char)(A0 & 0xFF); | |
525d929e AC |
912 | sim_io_write_stdout (sd, &tmp, sizeof(char)); |
913 | break; | |
8bae0a0c | 914 | } |
8bae0a0c JSC |
915 | |
916 | case 17: /* void _exit() */ | |
525d929e AC |
917 | { |
918 | sim_io_eprintf (sd, "sim_monitor(17): _exit(int reason) to be coded\n"); | |
919 | sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA, sim_exited, | |
920 | (unsigned int)(A0 & 0xFFFFFFFF)); | |
921 | break; | |
922 | } | |
8bae0a0c | 923 | |
280f90e1 AMT |
924 | case 28 : /* PMON flush_cache */ |
925 | break; | |
926 | ||
8bae0a0c JSC |
927 | case 55: /* void get_mem_info(unsigned int *ptr) */ |
928 | /* in: A0 = pointer to three word memory location */ | |
929 | /* out: [A0 + 0] = size */ | |
930 | /* [A0 + 4] = instruction cache size */ | |
931 | /* [A0 + 8] = data cache size */ | |
932 | { | |
525d929e AC |
933 | address_word value = MEM_SIZE /* FIXME STATE_MEM_SIZE (sd) */; |
934 | H2T (value); | |
935 | sim_write (sd, A0, (char *)&value, sizeof (value)); | |
936 | sim_io_eprintf (sd, "sim: get_mem_info() depreciated\n"); | |
937 | break; | |
8bae0a0c | 938 | } |
525d929e | 939 | |
a9f7253f JSC |
940 | case 158 : /* PMON printf */ |
941 | /* in: A0 = pointer to format string */ | |
942 | /* A1 = optional argument 1 */ | |
943 | /* A2 = optional argument 2 */ | |
944 | /* A3 = optional argument 3 */ | |
945 | /* out: void */ | |
f24b7b69 | 946 | /* The following is based on the PMON printf source */ |
a9f7253f | 947 | { |
525d929e AC |
948 | address_word s = A0; |
949 | char c; | |
950 | signed_word *ap = &A1; /* 1st argument */ | |
f24b7b69 JSC |
951 | /* This isn't the quickest way, since we call the host print |
952 | routine for every character almost. But it does avoid | |
953 | having to allocate and manage a temporary string buffer. */ | |
525d929e AC |
954 | /* TODO: Include check that we only use three arguments (A1, |
955 | A2 and A3) */ | |
956 | while (sim_read (sd, s++, &c, 1) && c != '\0') | |
957 | { | |
958 | if (c == '%') | |
959 | { | |
960 | char tmp[40]; | |
961 | enum {FMT_RJUST, FMT_LJUST, FMT_RJUST0, FMT_CENTER} fmt = FMT_RJUST; | |
962 | int width = 0, trunc = 0, haddot = 0, longlong = 0; | |
963 | while (sim_read (sd, s++, &c, 1) && c != '\0') | |
964 | { | |
965 | if (strchr ("dobxXulscefg%", s)) | |
966 | break; | |
967 | else if (c == '-') | |
968 | fmt = FMT_LJUST; | |
969 | else if (c == '0') | |
970 | fmt = FMT_RJUST0; | |
971 | else if (c == '~') | |
972 | fmt = FMT_CENTER; | |
973 | else if (c == '*') | |
974 | { | |
975 | if (haddot) | |
976 | trunc = (int)*ap++; | |
977 | else | |
978 | width = (int)*ap++; | |
979 | } | |
980 | else if (c >= '1' && c <= '9') | |
981 | { | |
982 | address_word t = s; | |
983 | unsigned int n; | |
984 | while (sim_read (sd, s++, &c, 1) == 1 && isdigit (c)) | |
985 | tmp[s - t] = c; | |
986 | tmp[s - t] = '\0'; | |
987 | n = (unsigned int)strtol(tmp,NULL,10); | |
988 | if (haddot) | |
989 | trunc = n; | |
990 | else | |
991 | width = n; | |
992 | s--; | |
993 | } | |
994 | else if (c == '.') | |
995 | haddot = 1; | |
996 | } | |
997 | switch (c) | |
998 | { | |
999 | case '%': | |
1000 | sim_io_printf (sd, "%%"); | |
1001 | break; | |
1002 | case 's': | |
1003 | if ((int)*ap != 0) | |
1004 | { | |
1005 | address_word p = *ap++; | |
1006 | char ch; | |
1007 | while (sim_read (sd, p++, &ch, 1) == 1 && ch != '\0') | |
1008 | sim_io_printf(sd, "%c", ch); | |
1009 | } | |
1010 | else | |
1011 | sim_io_printf(sd,"(null)"); | |
1012 | break; | |
1013 | case 'c': | |
1014 | sim_io_printf (sd, "%c", (int)*ap++); | |
1015 | break; | |
1016 | default: | |
1017 | if (c == 'l') | |
1018 | { | |
1019 | sim_read (sd, s++, &c, 1); | |
1020 | if (c == 'l') | |
1021 | { | |
1022 | longlong = 1; | |
1023 | sim_read (sd, s++, &c, 1); | |
1024 | } | |
1025 | } | |
1026 | if (strchr ("dobxXu", c)) | |
1027 | { | |
1028 | word64 lv = (word64) *ap++; | |
1029 | if (c == 'b') | |
1030 | sim_io_printf(sd,"<binary not supported>"); | |
1031 | else | |
1032 | { | |
1033 | sprintf (tmp, "%%%s%c", longlong ? "ll" : "", c); | |
1034 | if (longlong) | |
1035 | sim_io_printf(sd, tmp, lv); | |
1036 | else | |
1037 | sim_io_printf(sd, tmp, (int)lv); | |
1038 | } | |
1039 | } | |
1040 | else if (strchr ("eEfgG", c)) | |
1041 | { | |
1042 | double dbl = *(double*)(ap++); | |
1043 | sprintf (tmp, "%%%d.%d%c", width, trunc, c); | |
1044 | sim_io_printf (sd, tmp, dbl); | |
1045 | trunc = 0; | |
1046 | } | |
1047 | } | |
1048 | } | |
1049 | else | |
1050 | sim_io_printf(sd, "%c", c); | |
1051 | } | |
1052 | break; | |
a9f7253f | 1053 | } |
a9f7253f | 1054 | |
8bae0a0c | 1055 | default: |
525d929e AC |
1056 | sim_io_error (sd, "TODO: sim_monitor(%d) : PC = 0x%s\n", |
1057 | reason, pr_addr(IPC)); | |
8bae0a0c JSC |
1058 | break; |
1059 | } | |
1060 | return; | |
1061 | } | |
1062 | ||
7e6c297e ILT |
1063 | /* Store a word into memory. */ |
1064 | ||
1065 | static void | |
18c64df6 AC |
1066 | store_word (sd, vaddr, val) |
1067 | SIM_DESC sd; | |
7e6c297e ILT |
1068 | uword64 vaddr; |
1069 | t_reg val; | |
1070 | { | |
dad6f1f3 | 1071 | address_word paddr; |
7e6c297e ILT |
1072 | int uncached; |
1073 | ||
1074 | if ((vaddr & 3) != 0) | |
18c64df6 | 1075 | SignalExceptionAddressStore (); |
7e6c297e ILT |
1076 | else |
1077 | { | |
1078 | if (AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, | |
1079 | isTARGET, isREAL)) | |
1080 | { | |
1081 | const uword64 mask = 7; | |
1082 | uword64 memval; | |
1083 | unsigned int byte; | |
1084 | ||
1085 | paddr = (paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)); | |
1086 | byte = (vaddr & mask) ^ (BigEndianCPU << 2); | |
1087 | memval = ((uword64) val) << (8 * byte); | |
53b9417e | 1088 | StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr, |
7e6c297e ILT |
1089 | isREAL); |
1090 | } | |
1091 | } | |
1092 | } | |
1093 | ||
1094 | /* Load a word from memory. */ | |
1095 | ||
1096 | static t_reg | |
18c64df6 AC |
1097 | load_word (sd, vaddr) |
1098 | SIM_DESC sd; | |
7e6c297e ILT |
1099 | uword64 vaddr; |
1100 | { | |
1101 | if ((vaddr & 3) != 0) | |
18c64df6 | 1102 | SignalExceptionAddressLoad (); |
7e6c297e ILT |
1103 | else |
1104 | { | |
dad6f1f3 | 1105 | address_word paddr; |
7e6c297e ILT |
1106 | int uncached; |
1107 | ||
1108 | if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, | |
1109 | isTARGET, isREAL)) | |
1110 | { | |
1111 | const uword64 mask = 0x7; | |
1112 | const unsigned int reverse = ReverseEndian ? 1 : 0; | |
1113 | const unsigned int bigend = BigEndianCPU ? 1 : 0; | |
1114 | uword64 memval; | |
1115 | unsigned int byte; | |
1116 | ||
1117 | paddr = (paddr & ~mask) | ((paddr & mask) ^ (reverse << 2)); | |
53b9417e | 1118 | LoadMemory (&memval,NULL,uncached, AccessLength_WORD, paddr, vaddr, |
7e6c297e ILT |
1119 | isDATA, isREAL); |
1120 | byte = (vaddr & mask) ^ (bigend << 2); | |
1121 | return SIGNEXTEND (((memval >> (8 * byte)) & 0xffffffff), 32); | |
1122 | } | |
1123 | } | |
1124 | ||
1125 | return 0; | |
1126 | } | |
1127 | ||
1128 | /* Simulate the mips16 entry and exit pseudo-instructions. These | |
1129 | would normally be handled by the reserved instruction exception | |
1130 | code, but for ease of simulation we just handle them directly. */ | |
1131 | ||
1132 | static void | |
0c2c5f61 AC |
1133 | mips16_entry (sd,insn) |
1134 | SIM_DESC sd; | |
7e6c297e ILT |
1135 | unsigned int insn; |
1136 | { | |
1137 | int aregs, sregs, rreg; | |
1138 | ||
53b9417e DE |
1139 | #ifdef DEBUG |
1140 | printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn); | |
1141 | #endif /* DEBUG */ | |
1142 | ||
7e6c297e ILT |
1143 | aregs = (insn & 0x700) >> 8; |
1144 | sregs = (insn & 0x0c0) >> 6; | |
1145 | rreg = (insn & 0x020) >> 5; | |
1146 | ||
da0bce9c ILT |
1147 | /* This should be checked by the caller. */ |
1148 | if (sregs == 3) | |
7e6c297e ILT |
1149 | abort (); |
1150 | ||
da0bce9c | 1151 | if (aregs < 5) |
7e6c297e ILT |
1152 | { |
1153 | int i; | |
1154 | t_reg tsp; | |
1155 | ||
1156 | /* This is the entry pseudo-instruction. */ | |
1157 | ||
1158 | for (i = 0; i < aregs; i++) | |
0c2c5f61 | 1159 | store_word ((uword64) (SP + 4 * i), GPR[i + 4]); |
7e6c297e ILT |
1160 | |
1161 | tsp = SP; | |
1162 | SP -= 32; | |
1163 | ||
1164 | if (rreg) | |
1165 | { | |
1166 | tsp -= 4; | |
1167 | store_word ((uword64) tsp, RA); | |
1168 | } | |
1169 | ||
1170 | for (i = 0; i < sregs; i++) | |
1171 | { | |
1172 | tsp -= 4; | |
0c2c5f61 | 1173 | store_word ((uword64) tsp, GPR[16 + i]); |
7e6c297e ILT |
1174 | } |
1175 | } | |
1176 | else | |
1177 | { | |
1178 | int i; | |
1179 | t_reg tsp; | |
1180 | ||
1181 | /* This is the exit pseudo-instruction. */ | |
1182 | ||
1183 | tsp = SP + 32; | |
1184 | ||
1185 | if (rreg) | |
1186 | { | |
1187 | tsp -= 4; | |
1188 | RA = load_word ((uword64) tsp); | |
1189 | } | |
1190 | ||
1191 | for (i = 0; i < sregs; i++) | |
1192 | { | |
1193 | tsp -= 4; | |
0c2c5f61 | 1194 | GPR[i + 16] = load_word ((uword64) tsp); |
7e6c297e ILT |
1195 | } |
1196 | ||
1197 | SP += 32; | |
1198 | ||
9cb8397f | 1199 | #if defined(HASFPU) |
da0bce9c ILT |
1200 | if (aregs == 5) |
1201 | { | |
1202 | FGR[0] = WORD64LO (GPR[4]); | |
0c2c5f61 | 1203 | FPR_STATE[0] = fmt_uninterpreted; |
da0bce9c ILT |
1204 | } |
1205 | else if (aregs == 6) | |
1206 | { | |
1207 | FGR[0] = WORD64LO (GPR[5]); | |
1208 | FGR[1] = WORD64LO (GPR[4]); | |
0c2c5f61 AC |
1209 | FPR_STATE[0] = fmt_uninterpreted; |
1210 | FPR_STATE[1] = fmt_uninterpreted; | |
da0bce9c | 1211 | } |
9cb8397f | 1212 | #endif /* defined(HASFPU) */ |
da0bce9c | 1213 | |
7e6c297e ILT |
1214 | PC = RA; |
1215 | } | |
1216 | } | |
1217 | ||
8bae0a0c JSC |
1218 | static unsigned int |
1219 | power2(value) | |
1220 | unsigned int value; | |
1221 | { | |
1222 | int loop,tmp; | |
1223 | ||
1224 | /* Round *UP* to the nearest power-of-2 if not already one */ | |
1225 | if (value != (value & ~(value - 1))) { | |
1226 | for (tmp = value, loop = 0; (tmp != 0); loop++) | |
1227 | tmp >>= 1; | |
1228 | value = (1 << loop); | |
1229 | } | |
1230 | ||
1231 | return(value); | |
1232 | } | |
1233 | ||
1234 | static long | |
18c64df6 AC |
1235 | getnum(sd,value) |
1236 | SIM_DESC sd; | |
8bae0a0c JSC |
1237 | char *value; |
1238 | { | |
1239 | long num; | |
1240 | char *end; | |
1241 | ||
1242 | num = strtol(value,&end,10); | |
1243 | if (end == value) | |
18c64df6 | 1244 | sim_io_printf(sd,"Warning: Invalid number \"%s\" ignored, using zero\n",value); |
8bae0a0c JSC |
1245 | else { |
1246 | if (*end && ((tolower(*end) == 'k') || (tolower(*end) == 'm'))) { | |
1247 | if (tolower(*end) == 'k') | |
1248 | num *= (1 << 10); | |
1249 | else | |
1250 | num *= (1 << 20); | |
1251 | end++; | |
1252 | } | |
1253 | if (*end) | |
18c64df6 | 1254 | sim_io_printf(sd,"Warning: Spurious characters \"%s\" at end of number ignored\n",end); |
8bae0a0c JSC |
1255 | } |
1256 | ||
1257 | return(num); | |
1258 | } | |
1259 | ||
1260 | /*-- trace support ----------------------------------------------------------*/ | |
1261 | ||
1262 | /* The TRACE support is provided (if required) in the memory accessing | |
1263 | routines. Since we are also providing the architecture specific | |
1264 | features, the architecture simulation code can also deal with | |
1265 | notifying the TRACE world of cache flushes, etc. Similarly we do | |
1266 | not need to provide profiling support in the simulator engine, | |
1267 | since we can sample in the instruction fetch control loop. By | |
1268 | defining the TRACE manifest, we add tracing as a run-time | |
1269 | option. */ | |
1270 | ||
1271 | #if defined(TRACE) | |
1272 | /* Tracing by default produces "din" format (as required by | |
1273 | dineroIII). Each line of such a trace file *MUST* have a din label | |
1274 | and address field. The rest of the line is ignored, so comments can | |
1275 | be included if desired. The first field is the label which must be | |
1276 | one of the following values: | |
1277 | ||
1278 | 0 read data | |
1279 | 1 write data | |
1280 | 2 instruction fetch | |
1281 | 3 escape record (treated as unknown access type) | |
1282 | 4 escape record (causes cache flush) | |
1283 | ||
1284 | The address field is a 32bit (lower-case) hexadecimal address | |
1285 | value. The address should *NOT* be preceded by "0x". | |
1286 | ||
1287 | The size of the memory transfer is not important when dealing with | |
1288 | cache lines (as long as no more than a cache line can be | |
1289 | transferred in a single operation :-), however more information | |
1290 | could be given following the dineroIII requirement to allow more | |
1291 | complete memory and cache simulators to provide better | |
1292 | results. i.e. the University of Pisa has a cache simulator that can | |
1293 | also take bus size and speed as (variable) inputs to calculate | |
1294 | complete system performance (a much more useful ability when trying | |
1295 | to construct an end product, rather than a processor). They | |
1296 | currently have an ARM version of their tool called ChARM. */ | |
1297 | ||
e3d12c65 | 1298 | |
8bae0a0c | 1299 | static |
0c2c5f61 | 1300 | void dotrace(SIM_DESC sd,FILE *tracefh,int type,SIM_ADDR address,int width,char *comment,...) |
8bae0a0c | 1301 | { |
0c2c5f61 | 1302 | if (STATE & simTRACE) { |
8bae0a0c | 1303 | va_list ap; |
53b9417e | 1304 | fprintf(tracefh,"%d %s ; width %d ; ", |
6429b296 | 1305 | type, |
53b9417e DE |
1306 | pr_addr(address), |
1307 | width); | |
8bae0a0c | 1308 | va_start(ap,comment); |
6429b296 | 1309 | vfprintf(tracefh,comment,ap); |
8bae0a0c JSC |
1310 | va_end(ap); |
1311 | fprintf(tracefh,"\n"); | |
1312 | } | |
1313 | /* NOTE: Since the "din" format will only accept 32bit addresses, and | |
1314 | we may be generating 64bit ones, we should put the hi-32bits of the | |
1315 | address into the comment field. */ | |
1316 | ||
1317 | /* TODO: Provide a buffer for the trace lines. We can then avoid | |
1318 | performing writes until the buffer is filled, or the file is | |
1319 | being closed. */ | |
1320 | ||
1321 | /* NOTE: We could consider adding a comment field to the "din" file | |
1322 | produced using type 3 markers (unknown access). This would then | |
1323 | allow information about the program that the "din" is for, and | |
1324 | the MIPs world that was being simulated, to be placed into the | |
1325 | trace file. */ | |
1326 | ||
1327 | return; | |
1328 | } | |
1329 | #endif /* TRACE */ | |
1330 | ||
1331 | /*---------------------------------------------------------------------------*/ | |
1332 | /*-- simulator engine -------------------------------------------------------*/ | |
1333 | /*---------------------------------------------------------------------------*/ | |
1334 | ||
1335 | static void | |
dad6f1f3 | 1336 | ColdReset (sd) |
0c2c5f61 | 1337 | SIM_DESC sd; |
8bae0a0c JSC |
1338 | { |
1339 | /* RESET: Fixed PC address: */ | |
dad6f1f3 | 1340 | PC = UNSIGNED64 (0xFFFFFFFFBFC00000); |
8bae0a0c JSC |
1341 | /* The reset vector address is in the unmapped, uncached memory space. */ |
1342 | ||
1343 | SR &= ~(status_SR | status_TS | status_RP); | |
1344 | SR |= (status_ERL | status_BEV); | |
8bae0a0c | 1345 | |
dad6f1f3 AC |
1346 | /* Cheat and allow access to the complete register set immediately */ |
1347 | if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT | |
1348 | && WITH_TARGET_WORD_BITSIZE == 64) | |
1349 | SR |= status_FR; /* 64bit registers */ | |
8bae0a0c JSC |
1350 | |
1351 | /* Ensure that any instructions with pending register updates are | |
1352 | cleared: */ | |
1353 | { | |
1354 | int loop; | |
1355 | for (loop = 0; (loop < PSLOTS); loop++) | |
0c2c5f61 AC |
1356 | PENDING_SLOT_REG[loop] = (LAST_EMBED_REGNUM + 1); |
1357 | PENDING_IN = PENDING_OUT = PENDING_TOTAL = 0; | |
8bae0a0c JSC |
1358 | } |
1359 | ||
8bae0a0c | 1360 | /* Initialise the FPU registers to the unknown state */ |
dad6f1f3 AC |
1361 | if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT) |
1362 | { | |
1363 | int rn; | |
1364 | for (rn = 0; (rn < 32); rn++) | |
1365 | FPR_STATE[rn] = fmt_uninterpreted; | |
1366 | } | |
8bae0a0c JSC |
1367 | |
1368 | return; | |
1369 | } | |
1370 | ||
dad6f1f3 AC |
1371 | /* Description from page A-22 of the "MIPS IV Instruction Set" manual |
1372 | (revision 3.1) */ | |
8bae0a0c JSC |
1373 | /* Translate a virtual address to a physical address and cache |
1374 | coherence algorithm describing the mechanism used to resolve the | |
1375 | memory reference. Given the virtual address vAddr, and whether the | |
1376 | reference is to Instructions ot Data (IorD), find the corresponding | |
1377 | physical address (pAddr) and the cache coherence algorithm (CCA) | |
1378 | used to resolve the reference. If the virtual address is in one of | |
1379 | the unmapped address spaces the physical address and the CCA are | |
1380 | determined directly by the virtual address. If the virtual address | |
1381 | is in one of the mapped address spaces then the TLB is used to | |
1382 | determine the physical address and access type; if the required | |
1383 | translation is not present in the TLB or the desired access is not | |
1384 | permitted the function fails and an exception is taken. | |
1385 | ||
dad6f1f3 AC |
1386 | NOTE: Normally (RAW == 0), when address translation fails, this |
1387 | function raises an exception and does not return. */ | |
8bae0a0c | 1388 | |
18c64df6 | 1389 | int |
525d929e | 1390 | address_translation(sd,vAddr,IorD,LorS,pAddr,CCA,raw) |
18c64df6 | 1391 | SIM_DESC sd; |
dad6f1f3 | 1392 | address_word vAddr; |
8bae0a0c JSC |
1393 | int IorD; |
1394 | int LorS; | |
dad6f1f3 | 1395 | address_word *pAddr; |
8bae0a0c | 1396 | int *CCA; |
8bae0a0c JSC |
1397 | int raw; |
1398 | { | |
1399 | int res = -1; /* TRUE : Assume good return */ | |
1400 | ||
1401 | #ifdef DEBUG | |
18c64df6 | 1402 | sim_io_printf(sd,"AddressTranslation(0x%s,%s,%s,...);\n",pr_addr(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"),(LorS ? "iSTORE" : "isLOAD")); |
8bae0a0c JSC |
1403 | #endif |
1404 | ||
1405 | /* Check that the address is valid for this memory model */ | |
1406 | ||
1407 | /* For a simple (flat) memory model, we simply pass virtual | |
1408 | addressess through (mostly) unchanged. */ | |
1409 | vAddr &= 0xFFFFFFFF; | |
a9f7253f JSC |
1410 | |
1411 | /* Treat the kernel memory spaces identically for the moment: */ | |
50a2a691 | 1412 | if ((STATE_MEM_BASE (sd) == K1BASE) && (vAddr >= K0BASE) && (vAddr < (K0BASE + K0SIZE))) |
a9f7253f JSC |
1413 | vAddr += (K1BASE - K0BASE); |
1414 | ||
1415 | /* Also assume that the K1BASE memory wraps. This is required to | |
1416 | allow the PMON run-time __sizemem() routine to function (without | |
1417 | having to provide exception simulation). NOTE: A kludge to work | |
1418 | around the fact that the monitor memory is currently held in the | |
1419 | K1BASE space. */ | |
1420 | if (((vAddr < monitor_base) || (vAddr >= (monitor_base + monitor_size))) && (vAddr >= K1BASE && vAddr < (K1BASE + K1SIZE))) | |
50a2a691 | 1421 | vAddr = (K1BASE | (vAddr & (STATE_MEM_SIZE (sd) - 1))); |
a9f7253f | 1422 | |
8bae0a0c JSC |
1423 | *pAddr = vAddr; /* default for isTARGET */ |
1424 | *CCA = Uncached; /* not used for isHOST */ | |
1425 | ||
1426 | /* NOTE: This is a duplicate of the code that appears in the | |
1427 | LoadMemory and StoreMemory functions. They should be merged into | |
1428 | a single function (that can be in-lined if required). */ | |
50a2a691 | 1429 | if ((vAddr >= STATE_MEM_BASE (sd)) && (vAddr < (STATE_MEM_BASE (sd) + STATE_MEM_SIZE (sd)))) { |
525d929e | 1430 | /* do nothing */ |
8bae0a0c | 1431 | } else if ((vAddr >= monitor_base) && (vAddr < (monitor_base + monitor_size))) { |
525d929e | 1432 | /* do nothing */ |
8bae0a0c | 1433 | } else { |
6429b296 | 1434 | #ifdef DEBUG |
18c64df6 | 1435 | sim_io_eprintf(sd,"Failed: AddressTranslation(0x%s,%s,%s,...) IPC = 0x%s\n",pr_addr(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"),(LorS ? "isSTORE" : "isLOAD"),pr_addr(IPC)); |
8bae0a0c JSC |
1436 | #endif /* DEBUG */ |
1437 | res = 0; /* AddressTranslation has failed */ | |
e3d12c65 | 1438 | *pAddr = (SIM_ADDR)-1; |
8bae0a0c | 1439 | if (!raw) /* only generate exceptions on real memory transfers */ |
dad6f1f3 AC |
1440 | { |
1441 | if (IorD == isINSTRUCTION) | |
1442 | SignalExceptionInstructionFetch (); | |
1443 | else if (LorS == isSTORE) | |
1444 | SignalExceptionAddressStore (); | |
1445 | else | |
1446 | SignalExceptionAddressLoad (); | |
1447 | } | |
6429b296 | 1448 | #ifdef DEBUG |
8bae0a0c | 1449 | else |
dad6f1f3 AC |
1450 | /* This is a normal occurance during gdb operation, for instance |
1451 | trying to print parameters at function start before they have | |
1452 | been setup, and hence we should not print a warning except | |
1453 | when debugging the simulator. */ | |
1454 | sim_io_eprintf(sd,"AddressTranslation for %s %s from 0x%s failed\n",(IorD ? "data" : "instruction"),(LorS ? "store" : "load"),pr_addr(vAddr)); | |
6429b296 | 1455 | #endif |
8bae0a0c JSC |
1456 | } |
1457 | ||
1458 | return(res); | |
1459 | } | |
1460 | ||
1461 | /* Description from page A-23 of the "MIPS IV Instruction Set" manual (revision 3.1) */ | |
1462 | /* Prefetch data from memory. Prefetch is an advisory instruction for | |
1463 | which an implementation specific action is taken. The action taken | |
1464 | may increase performance, but must not change the meaning of the | |
1465 | program, or alter architecturally-visible state. */ | |
50a2a691 | 1466 | |
ea985d24 AC |
1467 | void |
1468 | prefetch(sd,CCA,pAddr,vAddr,DATA,hint) | |
1469 | SIM_DESC sd; | |
8bae0a0c | 1470 | int CCA; |
dad6f1f3 AC |
1471 | address_word pAddr; |
1472 | address_word vAddr; | |
8bae0a0c JSC |
1473 | int DATA; |
1474 | int hint; | |
1475 | { | |
1476 | #ifdef DEBUG | |
18c64df6 | 1477 | sim_io_printf(sd,"Prefetch(%d,0x%s,0x%s,%d,%d);\n",CCA,pr_addr(pAddr),pr_addr(vAddr),DATA,hint); |
8bae0a0c JSC |
1478 | #endif /* DEBUG */ |
1479 | ||
1480 | /* For our simple memory model we do nothing */ | |
1481 | return; | |
1482 | } | |
1483 | ||
1484 | /* Description from page A-22 of the "MIPS IV Instruction Set" manual (revision 3.1) */ | |
1485 | /* Load a value from memory. Use the cache and main memory as | |
1486 | specified in the Cache Coherence Algorithm (CCA) and the sort of | |
1487 | access (IorD) to find the contents of AccessLength memory bytes | |
1488 | starting at physical location pAddr. The data is returned in the | |
1489 | fixed width naturally-aligned memory element (MemElem). The | |
1490 | low-order two (or three) bits of the address and the AccessLength | |
1491 | indicate which of the bytes within MemElem needs to be given to the | |
1492 | processor. If the memory access type of the reference is uncached | |
1493 | then only the referenced bytes are read from memory and valid | |
1494 | within the memory element. If the access type is cached, and the | |
1495 | data is not present in cache, an implementation specific size and | |
1496 | alignment block of memory is read and loaded into the cache to | |
1497 | satisfy a load reference. At a minimum, the block is the entire | |
1498 | memory element. */ | |
18c64df6 AC |
1499 | void |
1500 | load_memory(sd,memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) | |
1501 | SIM_DESC sd; | |
53b9417e DE |
1502 | uword64* memvalp; |
1503 | uword64* memval1p; | |
8bae0a0c JSC |
1504 | int CCA; |
1505 | int AccessLength; | |
dad6f1f3 AC |
1506 | address_word pAddr; |
1507 | address_word vAddr; | |
8bae0a0c JSC |
1508 | int IorD; |
1509 | int raw; | |
1510 | { | |
50a2a691 AC |
1511 | uword64 value = 0; |
1512 | uword64 value1 = 0; | |
8bae0a0c JSC |
1513 | |
1514 | #ifdef DEBUG | |
50a2a691 | 1515 | if (STATE_MEMORY (sd) == NULL) |
18c64df6 | 1516 | sim_io_printf(sd,"DBG: LoadMemory(%p,%p,%d,%d,0x%s,0x%s,%s,%s)\n",memvalp,memval1p,CCA,AccessLength,pr_addr(pAddr),pr_addr(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"),(raw ? "isRAW" : "isREAL")); |
8bae0a0c JSC |
1517 | #endif /* DEBUG */ |
1518 | ||
1519 | #if defined(WARN_MEM) | |
1520 | if (CCA != uncached) | |
18c64df6 | 1521 | sim_io_eprintf(sd,"LoadMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA); |
8bae0a0c JSC |
1522 | |
1523 | if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK) { | |
1524 | /* In reality this should be a Bus Error */ | |
18c64df6 | 1525 | sim_io_error(sd,"AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",AccessLength,(LOADDRMASK + 1)<<2,pr_addr(pAddr)); |
8bae0a0c JSC |
1526 | } |
1527 | #endif /* WARN_MEM */ | |
1528 | ||
1529 | /* Decide which physical memory locations are being dealt with. At | |
1530 | this point we should be able to split the pAddr bits into the | |
525d929e AC |
1531 | relevant address map being simulated. */ |
1532 | /* If the "raw" variable is set, the memory read being performed | |
1533 | should *NOT* update any I/O state or affect the CPU state | |
1534 | (including statistics gathering). The parameter MEMVALP is least | |
1535 | significant byte justified. */ | |
8bae0a0c JSC |
1536 | |
1537 | /* If instruction fetch then we need to check that the two lo-order | |
1538 | bits are zero, otherwise raise a InstructionFetch exception: */ | |
6429b296 JW |
1539 | if ((IorD == isINSTRUCTION) |
1540 | && ((pAddr & 0x3) != 0) | |
1541 | && (((pAddr & 0x1) != 0) || ((vAddr & 0x1) == 0))) | |
18c64df6 | 1542 | SignalExceptionInstructionFetch (); |
8bae0a0c | 1543 | else { |
50a2a691 | 1544 | unsigned int index = 0; |
8bae0a0c JSC |
1545 | unsigned char *mem = NULL; |
1546 | ||
8bae0a0c JSC |
1547 | #if defined(TRACE) |
1548 | if (!raw) | |
0c2c5f61 | 1549 | dotrace(sd,tracefh,((IorD == isDATA) ? 0 : 2),(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"load%s",((IorD == isDATA) ? "" : " instruction")); |
8bae0a0c JSC |
1550 | #endif /* TRACE */ |
1551 | ||
1552 | /* NOTE: Quicker methods of decoding the address space can be used | |
1553 | when a real memory map is being simulated (i.e. using hi-order | |
1554 | address bits to select device). */ | |
50a2a691 AC |
1555 | if ((pAddr >= STATE_MEM_BASE (sd)) && (pAddr < (STATE_MEM_BASE (sd) + STATE_MEM_SIZE (sd)))) { |
1556 | index = ((unsigned int)(pAddr - STATE_MEM_BASE (sd)) & (STATE_MEM_SIZE (sd) - 1)); | |
1557 | mem = STATE_MEMORY (sd); | |
8bae0a0c JSC |
1558 | } else if ((pAddr >= monitor_base) && (pAddr < (monitor_base + monitor_size))) { |
1559 | index = ((unsigned int)(pAddr - monitor_base) & (monitor_size - 1)); | |
1560 | mem = monitor; | |
1561 | } | |
1562 | if (mem == NULL) | |
18c64df6 | 1563 | sim_io_error(sd,"Simulator memory not found for physical address 0x%s\n",pr_addr(pAddr)); |
8bae0a0c JSC |
1564 | else { |
1565 | /* If we obtained the endianness of the host, and it is the same | |
1566 | as the target memory system we can optimise the memory | |
1567 | accesses. However, without that information we must perform | |
1568 | slow transfer, and hope that the compiler optimisation will | |
1569 | merge successive loads. */ | |
8bae0a0c JSC |
1570 | |
1571 | /* In reality we should always be loading a doubleword value (or | |
1572 | word value in 32bit memory worlds). The external code then | |
1573 | extracts the required bytes. However, to keep performance | |
1574 | high we only load the required bytes into the relevant | |
1575 | slots. */ | |
0049ba7a | 1576 | if (BigEndianMem) |
8bae0a0c | 1577 | switch (AccessLength) { /* big-endian memory */ |
53b9417e DE |
1578 | case AccessLength_QUADWORD : |
1579 | value1 |= ((uword64)mem[index++] << 56); | |
1580 | case 14: /* AccessLength is one less than datalen */ | |
1581 | value1 |= ((uword64)mem[index++] << 48); | |
1582 | case 13: | |
1583 | value1 |= ((uword64)mem[index++] << 40); | |
1584 | case 12: | |
1585 | value1 |= ((uword64)mem[index++] << 32); | |
1586 | case 11: | |
1587 | value1 |= ((unsigned int)mem[index++] << 24); | |
1588 | case 10: | |
1589 | value1 |= ((unsigned int)mem[index++] << 16); | |
1590 | case 9: | |
1591 | value1 |= ((unsigned int)mem[index++] << 8); | |
1592 | case 8: | |
1593 | value1 |= mem[index]; | |
1594 | ||
8bae0a0c | 1595 | case AccessLength_DOUBLEWORD : |
e871dd18 | 1596 | value |= ((uword64)mem[index++] << 56); |
8bae0a0c | 1597 | case AccessLength_SEPTIBYTE : |
e871dd18 | 1598 | value |= ((uword64)mem[index++] << 48); |
8bae0a0c | 1599 | case AccessLength_SEXTIBYTE : |
e871dd18 | 1600 | value |= ((uword64)mem[index++] << 40); |
8bae0a0c | 1601 | case AccessLength_QUINTIBYTE : |
e871dd18 | 1602 | value |= ((uword64)mem[index++] << 32); |
8bae0a0c JSC |
1603 | case AccessLength_WORD : |
1604 | value |= ((unsigned int)mem[index++] << 24); | |
1605 | case AccessLength_TRIPLEBYTE : | |
1606 | value |= ((unsigned int)mem[index++] << 16); | |
1607 | case AccessLength_HALFWORD : | |
1608 | value |= ((unsigned int)mem[index++] << 8); | |
1609 | case AccessLength_BYTE : | |
1610 | value |= mem[index]; | |
1611 | break; | |
1612 | } | |
1613 | else { | |
1614 | index += (AccessLength + 1); | |
1615 | switch (AccessLength) { /* little-endian memory */ | |
53b9417e DE |
1616 | case AccessLength_QUADWORD : |
1617 | value1 |= ((uword64)mem[--index] << 56); | |
1618 | case 14: /* AccessLength is one less than datalen */ | |
1619 | value1 |= ((uword64)mem[--index] << 48); | |
1620 | case 13: | |
1621 | value1 |= ((uword64)mem[--index] << 40); | |
1622 | case 12: | |
1623 | value1 |= ((uword64)mem[--index] << 32); | |
1624 | case 11: | |
1625 | value1 |= ((uword64)mem[--index] << 24); | |
1626 | case 10: | |
1627 | value1 |= ((uword64)mem[--index] << 16); | |
1628 | case 9: | |
1629 | value1 |= ((uword64)mem[--index] << 8); | |
1630 | case 8: | |
1631 | value1 |= ((uword64)mem[--index] << 0); | |
1632 | ||
8bae0a0c | 1633 | case AccessLength_DOUBLEWORD : |
e871dd18 | 1634 | value |= ((uword64)mem[--index] << 56); |
8bae0a0c | 1635 | case AccessLength_SEPTIBYTE : |
e871dd18 | 1636 | value |= ((uword64)mem[--index] << 48); |
8bae0a0c | 1637 | case AccessLength_SEXTIBYTE : |
e871dd18 | 1638 | value |= ((uword64)mem[--index] << 40); |
8bae0a0c | 1639 | case AccessLength_QUINTIBYTE : |
e871dd18 | 1640 | value |= ((uword64)mem[--index] << 32); |
8bae0a0c | 1641 | case AccessLength_WORD : |
e871dd18 | 1642 | value |= ((uword64)mem[--index] << 24); |
8bae0a0c | 1643 | case AccessLength_TRIPLEBYTE : |
e871dd18 | 1644 | value |= ((uword64)mem[--index] << 16); |
8bae0a0c | 1645 | case AccessLength_HALFWORD : |
e871dd18 | 1646 | value |= ((uword64)mem[--index] << 8); |
8bae0a0c | 1647 | case AccessLength_BYTE : |
e871dd18 | 1648 | value |= ((uword64)mem[--index] << 0); |
8bae0a0c JSC |
1649 | break; |
1650 | } | |
1651 | } | |
1652 | ||
1653 | #ifdef DEBUG | |
53b9417e | 1654 | printf("DBG: LoadMemory() : (offset %d) : value = 0x%s%s\n", |
87e43259 | 1655 | (int)(pAddr & LOADDRMASK),pr_uword64(value1),pr_uword64(value)); |
8bae0a0c JSC |
1656 | #endif /* DEBUG */ |
1657 | ||
525d929e AC |
1658 | /* When dealing with raw memory accesses there is no need to |
1659 | deal with shifts. */ | |
53b9417e DE |
1660 | if (AccessLength <= AccessLength_DOUBLEWORD) { |
1661 | if (!raw) { /* do nothing for raw accessess */ | |
1662 | if (BigEndianMem) | |
1663 | value <<= (((7 - (pAddr & LOADDRMASK)) - AccessLength) * 8); | |
1664 | else /* little-endian only needs to be shifted up to the correct byte offset */ | |
1665 | value <<= ((pAddr & LOADDRMASK) * 8); | |
1666 | } | |
8bae0a0c JSC |
1667 | } |
1668 | ||
1669 | #ifdef DEBUG | |
53b9417e | 1670 | printf("DBG: LoadMemory() : shifted value = 0x%s%s\n", |
87e43259 | 1671 | pr_uword64(value1),pr_uword64(value)); |
e871dd18 | 1672 | #endif /* DEBUG */ |
8bae0a0c JSC |
1673 | } |
1674 | } | |
1675 | ||
525d929e AC |
1676 | *memvalp = value; |
1677 | if (memval1p) *memval1p = value1; | |
8bae0a0c JSC |
1678 | } |
1679 | ||
53b9417e | 1680 | |
50a2a691 AC |
1681 | /* Description from page A-23 of the "MIPS IV Instruction Set" manual |
1682 | (revision 3.1) */ | |
8bae0a0c JSC |
1683 | /* Store a value to memory. The specified data is stored into the |
1684 | physical location pAddr using the memory hierarchy (data caches and | |
1685 | main memory) as specified by the Cache Coherence Algorithm | |
1686 | (CCA). The MemElem contains the data for an aligned, fixed-width | |
1687 | memory element (word for 32-bit processors, doubleword for 64-bit | |
1688 | processors), though only the bytes that will actually be stored to | |
1689 | memory need to be valid. The low-order two (or three) bits of pAddr | |
1690 | and the AccessLength field indicates which of the bytes within the | |
1691 | MemElem data should actually be stored; only these bytes in memory | |
1692 | will be changed. */ | |
53b9417e | 1693 | |
18c64df6 AC |
1694 | void |
1695 | store_memory(sd,CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) | |
1696 | SIM_DESC sd; | |
8bae0a0c JSC |
1697 | int CCA; |
1698 | int AccessLength; | |
e871dd18 | 1699 | uword64 MemElem; |
53b9417e | 1700 | uword64 MemElem1; /* High order 64 bits */ |
dad6f1f3 AC |
1701 | address_word pAddr; |
1702 | address_word vAddr; | |
8bae0a0c JSC |
1703 | int raw; |
1704 | { | |
1705 | #ifdef DEBUG | |
18c64df6 | 1706 | sim_io_printf(sd,"DBG: StoreMemory(%d,%d,0x%s,0x%s,0x%s,0x%s,%s)\n",CCA,AccessLength,pr_uword64(MemElem),pr_uword64(MemElem1),pr_addr(pAddr),pr_addr(vAddr),(raw ? "isRAW" : "isREAL")); |
8bae0a0c JSC |
1707 | #endif /* DEBUG */ |
1708 | ||
1709 | #if defined(WARN_MEM) | |
1710 | if (CCA != uncached) | |
18c64df6 | 1711 | sim_io_eprintf(sd,"StoreMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA); |
8bae0a0c JSC |
1712 | |
1713 | if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK) | |
18c64df6 | 1714 | sim_io_error(sd,"AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",AccessLength,(LOADDRMASK + 1)<<2,pr_addr(pAddr)); |
8bae0a0c JSC |
1715 | #endif /* WARN_MEM */ |
1716 | ||
1717 | #if defined(TRACE) | |
1718 | if (!raw) | |
0c2c5f61 | 1719 | dotrace(sd,tracefh,1,(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"store"); |
8bae0a0c JSC |
1720 | #endif /* TRACE */ |
1721 | ||
1722 | /* See the comments in the LoadMemory routine about optimising | |
1723 | memory accesses. Also if we wanted to make the simulator smaller, | |
1724 | we could merge a lot of this code with the LoadMemory | |
1725 | routine. However, this would slow the simulator down with | |
1726 | run-time conditionals. */ | |
525d929e AC |
1727 | |
1728 | /* If the "raw" variable is set, the memory read being performed | |
1729 | should *NOT* update any I/O state or affect the CPU state | |
1730 | (including statistics gathering). The parameter MEMELEM is least | |
1731 | significant byte justified. */ | |
8bae0a0c | 1732 | { |
50a2a691 | 1733 | unsigned int index = 0; |
8bae0a0c JSC |
1734 | unsigned char *mem = NULL; |
1735 | ||
50a2a691 AC |
1736 | if ((pAddr >= STATE_MEM_BASE (sd)) && (pAddr < (STATE_MEM_BASE (sd) + STATE_MEM_SIZE (sd)))) { |
1737 | index = ((unsigned int)(pAddr - STATE_MEM_BASE (sd)) & (STATE_MEM_SIZE (sd) - 1)); | |
1738 | mem = STATE_MEMORY (sd); | |
8bae0a0c JSC |
1739 | } else if ((pAddr >= monitor_base) && (pAddr < (monitor_base + monitor_size))) { |
1740 | index = ((unsigned int)(pAddr - monitor_base) & (monitor_size - 1)); | |
1741 | mem = monitor; | |
1742 | } | |
1743 | ||
1744 | if (mem == NULL) | |
18c64df6 | 1745 | sim_io_error(sd,"Simulator memory not found for physical address 0x%s\n",pr_addr(pAddr)); |
8bae0a0c JSC |
1746 | else { |
1747 | int shift = 0; | |
1748 | ||
1749 | #ifdef DEBUG | |
87e43259 | 1750 | printf("DBG: StoreMemory: offset = %d MemElem = 0x%s%s\n",(unsigned int)(pAddr & LOADDRMASK),pr_uword64(MemElem1),pr_uword64(MemElem)); |
8bae0a0c JSC |
1751 | #endif /* DEBUG */ |
1752 | ||
53b9417e DE |
1753 | if (AccessLength <= AccessLength_DOUBLEWORD) { |
1754 | if (BigEndianMem) { | |
1755 | if (raw) | |
525d929e AC |
1756 | /* need to shift raw (least significant byte aligned) data |
1757 | into correct byte slots */ | |
53b9417e DE |
1758 | shift = ((7 - AccessLength) * 8); |
1759 | else /* real memory access */ | |
1760 | shift = ((pAddr & LOADDRMASK) * 8); | |
1761 | MemElem <<= shift; | |
1762 | } else { | |
1763 | /* no need to shift raw little-endian data */ | |
1764 | if (!raw) | |
1765 | MemElem >>= ((pAddr & LOADDRMASK) * 8); | |
1766 | } | |
8bae0a0c JSC |
1767 | } |
1768 | ||
1769 | #ifdef DEBUG | |
87e43259 | 1770 | printf("DBG: StoreMemory: shift = %d MemElem = 0x%s%s\n",shift,pr_uword64(MemElem1),pr_uword64(MemElem)); |
8bae0a0c JSC |
1771 | #endif /* DEBUG */ |
1772 | ||
0049ba7a | 1773 | if (BigEndianMem) { |
8bae0a0c | 1774 | switch (AccessLength) { /* big-endian memory */ |
53b9417e DE |
1775 | case AccessLength_QUADWORD : |
1776 | mem[index++] = (unsigned char)(MemElem1 >> 56); | |
1777 | MemElem1 <<= 8; | |
1778 | case 14 : | |
1779 | mem[index++] = (unsigned char)(MemElem1 >> 56); | |
1780 | MemElem1 <<= 8; | |
1781 | case 13 : | |
1782 | mem[index++] = (unsigned char)(MemElem1 >> 56); | |
1783 | MemElem1 <<= 8; | |
1784 | case 12 : | |
1785 | mem[index++] = (unsigned char)(MemElem1 >> 56); | |
1786 | MemElem1 <<= 8; | |
1787 | case 11 : | |
1788 | mem[index++] = (unsigned char)(MemElem1 >> 56); | |
1789 | MemElem1 <<= 8; | |
1790 | case 10 : | |
1791 | mem[index++] = (unsigned char)(MemElem1 >> 56); | |
1792 | MemElem1 <<= 8; | |
1793 | case 9 : | |
1794 | mem[index++] = (unsigned char)(MemElem1 >> 56); | |
1795 | MemElem1 <<= 8; | |
1796 | case 8 : | |
1797 | mem[index++] = (unsigned char)(MemElem1 >> 56); | |
1798 | ||
8bae0a0c JSC |
1799 | case AccessLength_DOUBLEWORD : |
1800 | mem[index++] = (unsigned char)(MemElem >> 56); | |
1801 | MemElem <<= 8; | |
1802 | case AccessLength_SEPTIBYTE : | |
1803 | mem[index++] = (unsigned char)(MemElem >> 56); | |
1804 | MemElem <<= 8; | |
1805 | case AccessLength_SEXTIBYTE : | |
1806 | mem[index++] = (unsigned char)(MemElem >> 56); | |
1807 | MemElem <<= 8; | |
1808 | case AccessLength_QUINTIBYTE : | |
1809 | mem[index++] = (unsigned char)(MemElem >> 56); | |
1810 | MemElem <<= 8; | |
1811 | case AccessLength_WORD : | |
1812 | mem[index++] = (unsigned char)(MemElem >> 56); | |
1813 | MemElem <<= 8; | |
1814 | case AccessLength_TRIPLEBYTE : | |
1815 | mem[index++] = (unsigned char)(MemElem >> 56); | |
1816 | MemElem <<= 8; | |
1817 | case AccessLength_HALFWORD : | |
1818 | mem[index++] = (unsigned char)(MemElem >> 56); | |
1819 | MemElem <<= 8; | |
1820 | case AccessLength_BYTE : | |
1821 | mem[index++] = (unsigned char)(MemElem >> 56); | |
1822 | break; | |
1823 | } | |
1824 | } else { | |
1825 | index += (AccessLength + 1); | |
1826 | switch (AccessLength) { /* little-endian memory */ | |
53b9417e DE |
1827 | case AccessLength_QUADWORD : |
1828 | mem[--index] = (unsigned char)(MemElem1 >> 56); | |
1829 | case 14 : | |
1830 | mem[--index] = (unsigned char)(MemElem1 >> 48); | |
1831 | case 13 : | |
1832 | mem[--index] = (unsigned char)(MemElem1 >> 40); | |
1833 | case 12 : | |
1834 | mem[--index] = (unsigned char)(MemElem1 >> 32); | |
1835 | case 11 : | |
1836 | mem[--index] = (unsigned char)(MemElem1 >> 24); | |
1837 | case 10 : | |
1838 | mem[--index] = (unsigned char)(MemElem1 >> 16); | |
1839 | case 9 : | |
1840 | mem[--index] = (unsigned char)(MemElem1 >> 8); | |
1841 | case 8 : | |
1842 | mem[--index] = (unsigned char)(MemElem1 >> 0); | |
1843 | ||
8bae0a0c JSC |
1844 | case AccessLength_DOUBLEWORD : |
1845 | mem[--index] = (unsigned char)(MemElem >> 56); | |
1846 | case AccessLength_SEPTIBYTE : | |
1847 | mem[--index] = (unsigned char)(MemElem >> 48); | |
1848 | case AccessLength_SEXTIBYTE : | |
1849 | mem[--index] = (unsigned char)(MemElem >> 40); | |
1850 | case AccessLength_QUINTIBYTE : | |
1851 | mem[--index] = (unsigned char)(MemElem >> 32); | |
1852 | case AccessLength_WORD : | |
1853 | mem[--index] = (unsigned char)(MemElem >> 24); | |
1854 | case AccessLength_TRIPLEBYTE : | |
1855 | mem[--index] = (unsigned char)(MemElem >> 16); | |
1856 | case AccessLength_HALFWORD : | |
1857 | mem[--index] = (unsigned char)(MemElem >> 8); | |
1858 | case AccessLength_BYTE : | |
1859 | mem[--index] = (unsigned char)(MemElem >> 0); | |
1860 | break; | |
1861 | } | |
1862 | } | |
1863 | } | |
1864 | } | |
1865 | ||
1866 | return; | |
1867 | } | |
1868 | ||
53b9417e | 1869 | |
dad6f1f3 AC |
1870 | unsigned32 |
1871 | ifetch32 (SIM_DESC sd, address_word vaddr) | |
1872 | { | |
1873 | /* Copy the action of the LW instruction */ | |
1874 | address_word reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0); | |
1875 | address_word bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0); | |
1876 | unsigned64 value; | |
1877 | address_word paddr; | |
1878 | unsigned32 instruction; | |
1879 | unsigned byte; | |
1880 | int cca; | |
1881 | AddressTranslation (vaddr, isINSTRUCTION, isLOAD, &paddr, &cca, isTARGET, isREAL); | |
1882 | paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2))); | |
1883 | LoadMemory (&value, NULL, cca, AccessLength_WORD, paddr, vaddr, isINSTRUCTION, isREAL); | |
1884 | byte = ((vaddr & LOADDRMASK) ^ (bigend << 2)); | |
1885 | instruction = ((value >> (8 * byte)) & 0xFFFFFFFF); | |
1886 | return instruction; | |
1887 | } | |
1888 | ||
1889 | ||
8bae0a0c JSC |
1890 | /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */ |
1891 | /* Order loads and stores to synchronise shared memory. Perform the | |
1892 | action necessary to make the effects of groups of synchronizable | |
1893 | loads and stores indicated by stype occur in the same order for all | |
1894 | processors. */ | |
ea985d24 AC |
1895 | void |
1896 | sync_operation(sd,stype) | |
1897 | SIM_DESC sd; | |
8bae0a0c JSC |
1898 | int stype; |
1899 | { | |
1900 | #ifdef DEBUG | |
18c64df6 | 1901 | sim_io_printf(sd,"SyncOperation(%d) : TODO\n",stype); |
8bae0a0c JSC |
1902 | #endif /* DEBUG */ |
1903 | return; | |
1904 | } | |
1905 | ||
1906 | /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */ | |
1907 | /* Signal an exception condition. This will result in an exception | |
1908 | that aborts the instruction. The instruction operation pseudocode | |
50a2a691 | 1909 | will never see a return from this function call. */ |
2e61a3ad | 1910 | |
18c64df6 AC |
1911 | void |
1912 | signal_exception (SIM_DESC sd, int exception,...) | |
8bae0a0c | 1913 | { |
56e7c849 | 1914 | int vector; |
6eedf3f4 MA |
1915 | |
1916 | #ifdef DEBUG | |
18c64df6 | 1917 | sim_io_printf(sd,"DBG: SignalException(%d) IPC = 0x%s\n",exception,pr_addr(IPC)); |
6eedf3f4 MA |
1918 | #endif /* DEBUG */ |
1919 | ||
8bae0a0c JSC |
1920 | /* Ensure that any active atomic read/modify/write operation will fail: */ |
1921 | LLBIT = 0; | |
1922 | ||
1923 | switch (exception) { | |
1924 | /* TODO: For testing purposes I have been ignoring TRAPs. In | |
1925 | reality we should either simulate them, or allow the user to | |
6eedf3f4 MA |
1926 | ignore them at run-time. |
1927 | Same for SYSCALL */ | |
8bae0a0c | 1928 | case Trap : |
18c64df6 | 1929 | sim_io_eprintf(sd,"Ignoring instruction TRAP (PC 0x%s)\n",pr_addr(IPC)); |
8bae0a0c JSC |
1930 | break; |
1931 | ||
6eedf3f4 MA |
1932 | case SystemCall : |
1933 | { | |
1934 | va_list ap; | |
1935 | unsigned int instruction; | |
1936 | unsigned int code; | |
1937 | ||
1938 | va_start(ap,exception); | |
1939 | instruction = va_arg(ap,unsigned int); | |
1940 | va_end(ap); | |
1941 | ||
1942 | code = (instruction >> 6) & 0xFFFFF; | |
1943 | ||
18c64df6 | 1944 | sim_io_eprintf(sd,"Ignoring instruction `syscall %d' (PC 0x%s)\n", |
6eedf3f4 MA |
1945 | code, pr_addr(IPC)); |
1946 | } | |
1947 | break; | |
1948 | ||
1949 | case DebugBreakPoint : | |
1950 | if (! (Debug & Debug_DM)) | |
1951 | { | |
1952 | if (INDELAYSLOT()) | |
1953 | { | |
1954 | CANCELDELAYSLOT(); | |
1955 | ||
1956 | Debug |= Debug_DBD; /* signaled from within in delay slot */ | |
1957 | DEPC = IPC - 4; /* reference the branch instruction */ | |
1958 | } | |
1959 | else | |
1960 | { | |
1961 | Debug &= ~Debug_DBD; /* not signaled from within a delay slot */ | |
1962 | DEPC = IPC; | |
1963 | } | |
1964 | ||
1965 | Debug |= Debug_DM; /* in debugging mode */ | |
1966 | Debug |= Debug_DBp; /* raising a DBp exception */ | |
1967 | PC = 0xBFC00200; | |
1968 | sim_engine_restart (sd, STATE_CPU (sd, 0), NULL, NULL_CIA); | |
1969 | } | |
1970 | break; | |
1971 | ||
8bae0a0c JSC |
1972 | case ReservedInstruction : |
1973 | { | |
1974 | va_list ap; | |
1975 | unsigned int instruction; | |
1976 | va_start(ap,exception); | |
1977 | instruction = va_arg(ap,unsigned int); | |
1978 | va_end(ap); | |
1979 | /* Provide simple monitor support using ReservedInstruction | |
1980 | exceptions. The following code simulates the fixed vector | |
1981 | entry points into the IDT monitor by causing a simulator | |
1982 | trap, performing the monitor operation, and returning to | |
1983 | the address held in the $ra register (standard PCS return | |
1984 | address). This means we only need to pre-load the vector | |
1985 | space with suitable instruction values. For systems were | |
1986 | actual trap instructions are used, we would not need to | |
1987 | perform this magic. */ | |
53b9417e | 1988 | if ((instruction & RSVD_INSTRUCTION_MASK) == RSVD_INSTRUCTION) { |
18c64df6 | 1989 | sim_monitor(sd, ((instruction >> RSVD_INSTRUCTION_ARG_SHIFT) & RSVD_INSTRUCTION_ARG_MASK) ); |
8bae0a0c JSC |
1990 | PC = RA; /* simulate the return from the vector entry */ |
1991 | /* NOTE: This assumes that a branch-and-link style | |
1992 | instruction was used to enter the vector (which is the | |
1993 | case with the current IDT monitor). */ | |
2e61a3ad | 1994 | sim_engine_restart (sd, STATE_CPU (sd, 0), NULL, NULL_CIA); |
7e6c297e ILT |
1995 | } |
1996 | /* Look for the mips16 entry and exit instructions, and | |
1997 | simulate a handler for them. */ | |
1998 | else if ((IPC & 1) != 0 | |
1999 | && (instruction & 0xf81f) == 0xe809 | |
7e6c297e ILT |
2000 | && (instruction & 0x0c0) != 0x0c0) { |
2001 | mips16_entry (instruction); | |
2e61a3ad | 2002 | sim_engine_restart (sd, STATE_CPU (sd, 0), NULL, NULL_CIA); |
8bae0a0c | 2003 | } /* else fall through to normal exception processing */ |
18c64df6 | 2004 | sim_io_eprintf(sd,"ReservedInstruction 0x%08X at IPC = 0x%s\n",instruction,pr_addr(IPC)); |
8bae0a0c JSC |
2005 | } |
2006 | ||
05d1322f | 2007 | case BreakPoint: |
e3d12c65 | 2008 | #ifdef DEBUG |
18c64df6 | 2009 | sim_io_printf(sd,"DBG: SignalException(%d) IPC = 0x%s\n",exception,pr_addr(IPC)); |
8bae0a0c | 2010 | #endif /* DEBUG */ |
05d1322f JL |
2011 | /* Keep a copy of the current A0 in-case this is the program exit |
2012 | breakpoint: */ | |
2013 | { | |
2014 | va_list ap; | |
2015 | unsigned int instruction; | |
2016 | va_start(ap,exception); | |
2017 | instruction = va_arg(ap,unsigned int); | |
2018 | va_end(ap); | |
2019 | /* Check for our special terminating BREAK: */ | |
2020 | if ((instruction & 0x03FFFFC0) == 0x03ff0000) { | |
2021 | sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA, | |
2022 | sim_exited, (unsigned int)(A0 & 0xFFFFFFFF)); | |
2023 | } | |
2024 | } | |
0c2c5f61 | 2025 | if (STATE & simDELAYSLOT) |
05d1322f JL |
2026 | PC = IPC - 4; /* reference the branch instruction */ |
2027 | else | |
2028 | PC = IPC; | |
2029 | sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA, | |
2030 | sim_stopped, SIGTRAP); | |
2031 | ||
2032 | default: | |
8bae0a0c JSC |
2033 | /* Store exception code into current exception id variable (used |
2034 | by exit code): */ | |
2035 | ||
2036 | /* TODO: If not simulating exceptions then stop the simulator | |
2037 | execution. At the moment we always stop the simulation. */ | |
e3d12c65 | 2038 | |
56e7c849 AC |
2039 | /* See figure 5-17 for an outline of the code below */ |
2040 | if (! (SR & status_EXL)) | |
2041 | { | |
2042 | CAUSE = (exception << 2); | |
0c2c5f61 | 2043 | if (STATE & simDELAYSLOT) |
56e7c849 | 2044 | { |
0c2c5f61 | 2045 | STATE &= ~simDELAYSLOT; |
56e7c849 AC |
2046 | CAUSE |= cause_BD; |
2047 | EPC = (IPC - 4); /* reference the branch instruction */ | |
2048 | } | |
2049 | else | |
2050 | EPC = IPC; | |
2051 | /* FIXME: TLB et.al. */ | |
2052 | vector = 0x180; | |
2053 | } | |
2054 | else | |
2055 | { | |
05d1322f | 2056 | CAUSE = (exception << 2); |
56e7c849 AC |
2057 | vector = 0x180; |
2058 | } | |
2059 | SR |= status_EXL; | |
e3d12c65 DE |
2060 | /* Store exception code into current exception id variable (used |
2061 | by exit code): */ | |
56e7c849 AC |
2062 | if (SR & status_BEV) |
2063 | PC = (signed)0xBFC00200 + 0x180; | |
2064 | else | |
2065 | PC = (signed)0x80000000 + 0x180; | |
2066 | ||
50a2a691 AC |
2067 | switch ((CAUSE >> 2) & 0x1F) |
2068 | { | |
2069 | case Interrupt: | |
56e7c849 AC |
2070 | /* Interrupts arrive during event processing, no need to |
2071 | restart */ | |
2072 | return; | |
50a2a691 AC |
2073 | |
2074 | case TLBModification: | |
2075 | case TLBLoad: | |
2076 | case TLBStore: | |
2077 | case AddressLoad: | |
2078 | case AddressStore: | |
2079 | case InstructionFetch: | |
2080 | case DataReference: | |
56e7c849 AC |
2081 | /* The following is so that the simulator will continue from the |
2082 | exception address on breakpoint operations. */ | |
2083 | PC = EPC; | |
50a2a691 AC |
2084 | sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA, |
2085 | sim_stopped, SIGBUS); | |
2086 | ||
2087 | case ReservedInstruction: | |
2088 | case CoProcessorUnusable: | |
56e7c849 | 2089 | PC = EPC; |
50a2a691 AC |
2090 | sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA, |
2091 | sim_stopped, SIGILL); | |
2092 | ||
2093 | case IntegerOverflow: | |
2094 | case FPE: | |
2095 | sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA, | |
2096 | sim_stopped, SIGFPE); | |
2097 | ||
2098 | case Trap: | |
2099 | case Watch: | |
2100 | case SystemCall: | |
56e7c849 | 2101 | PC = EPC; |
50a2a691 AC |
2102 | sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA, |
2103 | sim_stopped, SIGTRAP); | |
2104 | ||
05d1322f JL |
2105 | case BreakPoint: |
2106 | PC = EPC; | |
2107 | sim_engine_abort (sd, STATE_CPU (sd, 0), NULL_CIA, | |
2108 | "FATAL: Should not encounter a breakpoint\n"); | |
2109 | ||
50a2a691 | 2110 | default : /* Unknown internal exception */ |
56e7c849 | 2111 | PC = EPC; |
50a2a691 AC |
2112 | sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA, |
2113 | sim_stopped, SIGQUIT); | |
2114 | ||
2115 | } | |
8bae0a0c JSC |
2116 | |
2117 | case SimulatorFault: | |
2118 | { | |
2119 | va_list ap; | |
2120 | char *msg; | |
2121 | va_start(ap,exception); | |
2122 | msg = va_arg(ap,char *); | |
50a2a691 | 2123 | va_end(ap); |
2e61a3ad AC |
2124 | sim_engine_abort (sd, STATE_CPU (sd, 0), NULL_CIA, |
2125 | "FATAL: Simulator error \"%s\"\n",msg); | |
8bae0a0c | 2126 | } |
8bae0a0c JSC |
2127 | } |
2128 | ||
2129 | return; | |
2130 | } | |
2131 | ||
2132 | #if defined(WARN_RESULT) | |
2133 | /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */ | |
2134 | /* This function indicates that the result of the operation is | |
2135 | undefined. However, this should not affect the instruction | |
2136 | stream. All that is meant to happen is that the destination | |
2137 | register is set to an undefined result. To keep the simulator | |
2138 | simple, we just don't bother updating the destination register, so | |
2139 | the overall result will be undefined. If desired we can stop the | |
2140 | simulator by raising a pseudo-exception. */ | |
2141 | static void | |
2142 | UndefinedResult() | |
2143 | { | |
18c64df6 | 2144 | sim_io_eprintf(sd,"UndefinedResult: IPC = 0x%s\n",pr_addr(IPC)); |
8bae0a0c JSC |
2145 | #if 0 /* Disabled for the moment, since it actually happens a lot at the moment. */ |
2146 | state |= simSTOP; | |
2147 | #endif | |
2148 | return; | |
2149 | } | |
2150 | #endif /* WARN_RESULT */ | |
2151 | ||
18c64df6 AC |
2152 | void |
2153 | cache_op(sd,op,pAddr,vAddr,instruction) | |
2154 | SIM_DESC sd; | |
8bae0a0c | 2155 | int op; |
dad6f1f3 AC |
2156 | address_word pAddr; |
2157 | address_word vAddr; | |
8bae0a0c JSC |
2158 | unsigned int instruction; |
2159 | { | |
f24b7b69 JSC |
2160 | #if 1 /* stop warning message being displayed (we should really just remove the code) */ |
2161 | static int icache_warning = 1; | |
2162 | static int dcache_warning = 1; | |
2163 | #else | |
a9f7253f JSC |
2164 | static int icache_warning = 0; |
2165 | static int dcache_warning = 0; | |
f24b7b69 | 2166 | #endif |
a9f7253f | 2167 | |
8bae0a0c JSC |
2168 | /* If CP0 is not useable (User or Supervisor mode) and the CP0 |
2169 | enable bit in the Status Register is clear - a coprocessor | |
2170 | unusable exception is taken. */ | |
a9f7253f | 2171 | #if 0 |
18c64df6 | 2172 | sim_io_printf(sd,"TODO: Cache availability checking (PC = 0x%s)\n",pr_addr(IPC)); |
a9f7253f | 2173 | #endif |
8bae0a0c JSC |
2174 | |
2175 | switch (op & 0x3) { | |
2176 | case 0: /* instruction cache */ | |
2177 | switch (op >> 2) { | |
2178 | case 0: /* Index Invalidate */ | |
2179 | case 1: /* Index Load Tag */ | |
2180 | case 2: /* Index Store Tag */ | |
2181 | case 4: /* Hit Invalidate */ | |
2182 | case 5: /* Fill */ | |
2183 | case 6: /* Hit Writeback */ | |
a9f7253f JSC |
2184 | if (!icache_warning) |
2185 | { | |
18c64df6 | 2186 | sim_io_eprintf(sd,"Instruction CACHE operation %d to be coded\n",(op >> 2)); |
a9f7253f JSC |
2187 | icache_warning = 1; |
2188 | } | |
8bae0a0c JSC |
2189 | break; |
2190 | ||
2191 | default: | |
2192 | SignalException(ReservedInstruction,instruction); | |
2193 | break; | |
2194 | } | |
2195 | break; | |
2196 | ||
2197 | case 1: /* data cache */ | |
2198 | switch (op >> 2) { | |
2199 | case 0: /* Index Writeback Invalidate */ | |
2200 | case 1: /* Index Load Tag */ | |
2201 | case 2: /* Index Store Tag */ | |
2202 | case 3: /* Create Dirty */ | |
2203 | case 4: /* Hit Invalidate */ | |
2204 | case 5: /* Hit Writeback Invalidate */ | |
2205 | case 6: /* Hit Writeback */ | |
a9f7253f JSC |
2206 | if (!dcache_warning) |
2207 | { | |
18c64df6 | 2208 | sim_io_eprintf(sd,"Data CACHE operation %d to be coded\n",(op >> 2)); |
a9f7253f JSC |
2209 | dcache_warning = 1; |
2210 | } | |
8bae0a0c JSC |
2211 | break; |
2212 | ||
2213 | default: | |
2214 | SignalException(ReservedInstruction,instruction); | |
2215 | break; | |
2216 | } | |
2217 | break; | |
2218 | ||
2219 | default: /* unrecognised cache ID */ | |
2220 | SignalException(ReservedInstruction,instruction); | |
2221 | break; | |
2222 | } | |
2223 | ||
2224 | return; | |
2225 | } | |
2226 | ||
2227 | /*-- FPU support routines ---------------------------------------------------*/ | |
2228 | ||
2229 | #if defined(HASFPU) /* Only needed when building FPU aware simulators */ | |
2230 | ||
8bae0a0c JSC |
2231 | /* Numbers are held in normalized form. The SINGLE and DOUBLE binary |
2232 | formats conform to ANSI/IEEE Std 754-1985. */ | |
2233 | /* SINGLE precision floating: | |
2234 | * seeeeeeeefffffffffffffffffffffff | |
2235 | * s = 1bit = sign | |
2236 | * e = 8bits = exponent | |
2237 | * f = 23bits = fraction | |
2238 | */ | |
2239 | /* SINGLE precision fixed: | |
2240 | * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiii | |
2241 | * s = 1bit = sign | |
2242 | * i = 31bits = integer | |
2243 | */ | |
2244 | /* DOUBLE precision floating: | |
2245 | * seeeeeeeeeeeffffffffffffffffffffffffffffffffffffffffffffffffffff | |
2246 | * s = 1bit = sign | |
2247 | * e = 11bits = exponent | |
2248 | * f = 52bits = fraction | |
2249 | */ | |
2250 | /* DOUBLE precision fixed: | |
2251 | * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii | |
2252 | * s = 1bit = sign | |
2253 | * i = 63bits = integer | |
2254 | */ | |
2255 | ||
2256 | /* Extract sign-bit: */ | |
2257 | #define FP_S_s(v) (((v) & ((unsigned)1 << 31)) ? 1 : 0) | |
e871dd18 | 2258 | #define FP_D_s(v) (((v) & ((uword64)1 << 63)) ? 1 : 0) |
8bae0a0c JSC |
2259 | /* Extract biased exponent: */ |
2260 | #define FP_S_be(v) (((v) >> 23) & 0xFF) | |
2261 | #define FP_D_be(v) (((v) >> 52) & 0x7FF) | |
2262 | /* Extract unbiased Exponent: */ | |
2263 | #define FP_S_e(v) (FP_S_be(v) - 0x7F) | |
2264 | #define FP_D_e(v) (FP_D_be(v) - 0x3FF) | |
2265 | /* Extract complete fraction field: */ | |
2266 | #define FP_S_f(v) ((v) & ~((unsigned)0x1FF << 23)) | |
e871dd18 | 2267 | #define FP_D_f(v) ((v) & ~((uword64)0xFFF << 52)) |
8bae0a0c JSC |
2268 | /* Extract numbered fraction bit: */ |
2269 | #define FP_S_fb(b,v) (((v) & (1 << (23 - (b)))) ? 1 : 0) | |
2270 | #define FP_D_fb(b,v) (((v) & (1 << (52 - (b)))) ? 1 : 0) | |
2271 | ||
2272 | /* Explicit QNaN values used when value required: */ | |
2273 | #define FPQNaN_SINGLE (0x7FBFFFFF) | |
2274 | #define FPQNaN_WORD (0x7FFFFFFF) | |
e871dd18 JSC |
2275 | #define FPQNaN_DOUBLE (((uword64)0x7FF7FFFF << 32) | 0xFFFFFFFF) |
2276 | #define FPQNaN_LONG (((uword64)0x7FFFFFFF << 32) | 0xFFFFFFFF) | |
8bae0a0c JSC |
2277 | |
2278 | /* Explicit Infinity values used when required: */ | |
2279 | #define FPINF_SINGLE (0x7F800000) | |
e871dd18 | 2280 | #define FPINF_DOUBLE (((uword64)0x7FF00000 << 32) | 0x00000000) |
8bae0a0c JSC |
2281 | |
2282 | #if 1 /* def DEBUG */ | |
2283 | #define RMMODE(v) (((v) == FP_RM_NEAREST) ? "Round" : (((v) == FP_RM_TOZERO) ? "Trunc" : (((v) == FP_RM_TOPINF) ? "Ceil" : "Floor"))) | |
2284 | #define DOFMT(v) (((v) == fmt_single) ? "single" : (((v) == fmt_double) ? "double" : (((v) == fmt_word) ? "word" : (((v) == fmt_long) ? "long" : (((v) == fmt_unknown) ? "<unknown>" : (((v) == fmt_uninterpreted) ? "<uninterpreted>" : "<format error>")))))) | |
2285 | #endif /* DEBUG */ | |
2286 | ||
18c64df6 AC |
2287 | uword64 |
2288 | value_fpr(sd,fpr,fmt) | |
2289 | SIM_DESC sd; | |
2290 | int fpr; | |
2291 | FP_formats fmt; | |
8bae0a0c | 2292 | { |
50a2a691 | 2293 | uword64 value = 0; |
8bae0a0c JSC |
2294 | int err = 0; |
2295 | ||
2296 | /* Treat unused register values, as fixed-point 64bit values: */ | |
2297 | if ((fmt == fmt_uninterpreted) || (fmt == fmt_unknown)) | |
2298 | #if 1 | |
2299 | /* If request to read data as "uninterpreted", then use the current | |
2300 | encoding: */ | |
0c2c5f61 | 2301 | fmt = FPR_STATE[fpr]; |
8bae0a0c JSC |
2302 | #else |
2303 | fmt = fmt_long; | |
2304 | #endif | |
2305 | ||
2306 | /* For values not yet accessed, set to the desired format: */ | |
0c2c5f61 AC |
2307 | if (FPR_STATE[fpr] == fmt_uninterpreted) { |
2308 | FPR_STATE[fpr] = fmt; | |
8bae0a0c JSC |
2309 | #ifdef DEBUG |
2310 | printf("DBG: Register %d was fmt_uninterpreted. Now %s\n",fpr,DOFMT(fmt)); | |
2311 | #endif /* DEBUG */ | |
2312 | } | |
0c2c5f61 AC |
2313 | if (fmt != FPR_STATE[fpr]) { |
2314 | sim_io_eprintf(sd,"FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",fpr,DOFMT(FPR_STATE[fpr]),DOFMT(fmt),pr_addr(IPC)); | |
2315 | FPR_STATE[fpr] = fmt_unknown; | |
8bae0a0c JSC |
2316 | } |
2317 | ||
0c2c5f61 | 2318 | if (FPR_STATE[fpr] == fmt_unknown) { |
8bae0a0c JSC |
2319 | /* Set QNaN value: */ |
2320 | switch (fmt) { | |
2321 | case fmt_single: | |
2322 | value = FPQNaN_SINGLE; | |
2323 | break; | |
2324 | ||
2325 | case fmt_double: | |
2326 | value = FPQNaN_DOUBLE; | |
2327 | break; | |
2328 | ||
2329 | case fmt_word: | |
2330 | value = FPQNaN_WORD; | |
2331 | break; | |
2332 | ||
2333 | case fmt_long: | |
2334 | value = FPQNaN_LONG; | |
2335 | break; | |
2336 | ||
2337 | default: | |
2338 | err = -1; | |
2339 | break; | |
2340 | } | |
2341 | } else if (SizeFGR() == 64) { | |
2342 | switch (fmt) { | |
2343 | case fmt_single: | |
2344 | case fmt_word: | |
2345 | value = (FGR[fpr] & 0xFFFFFFFF); | |
2346 | break; | |
2347 | ||
2348 | case fmt_uninterpreted: | |
2349 | case fmt_double: | |
2350 | case fmt_long: | |
2351 | value = FGR[fpr]; | |
2352 | break; | |
2353 | ||
2354 | default : | |
2355 | err = -1; | |
2356 | break; | |
2357 | } | |
da0bce9c | 2358 | } else { |
8bae0a0c JSC |
2359 | switch (fmt) { |
2360 | case fmt_single: | |
2361 | case fmt_word: | |
2362 | value = (FGR[fpr] & 0xFFFFFFFF); | |
2363 | break; | |
2364 | ||
2365 | case fmt_uninterpreted: | |
2366 | case fmt_double: | |
2367 | case fmt_long: | |
da0bce9c ILT |
2368 | if ((fpr & 1) == 0) { /* even registers only */ |
2369 | value = ((((uword64)FGR[fpr+1]) << 32) | (FGR[fpr] & 0xFFFFFFFF)); | |
2370 | } else { | |
18c64df6 | 2371 | SignalException(ReservedInstruction,0); |
da0bce9c | 2372 | } |
8bae0a0c JSC |
2373 | break; |
2374 | ||
2375 | default : | |
2376 | err = -1; | |
2377 | break; | |
2378 | } | |
2379 | } | |
2380 | ||
2381 | if (err) | |
18c64df6 | 2382 | SignalExceptionSimulatorFault ("Unrecognised FP format in ValueFPR()"); |
8bae0a0c JSC |
2383 | |
2384 | #ifdef DEBUG | |
53b9417e | 2385 | printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(IPC),SizeFGR()); |
8bae0a0c JSC |
2386 | #endif /* DEBUG */ |
2387 | ||
2388 | return(value); | |
2389 | } | |
2390 | ||
18c64df6 AC |
2391 | void |
2392 | store_fpr(sd,fpr,fmt,value) | |
2393 | SIM_DESC sd; | |
8bae0a0c JSC |
2394 | int fpr; |
2395 | FP_formats fmt; | |
e871dd18 | 2396 | uword64 value; |
8bae0a0c JSC |
2397 | { |
2398 | int err = 0; | |
2399 | ||
2400 | #ifdef DEBUG | |
53b9417e | 2401 | printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(IPC),SizeFGR()); |
8bae0a0c JSC |
2402 | #endif /* DEBUG */ |
2403 | ||
2404 | if (SizeFGR() == 64) { | |
2405 | switch (fmt) { | |
2406 | case fmt_single : | |
2407 | case fmt_word : | |
e871dd18 | 2408 | FGR[fpr] = (((uword64)0xDEADC0DE << 32) | (value & 0xFFFFFFFF)); |
0c2c5f61 | 2409 | FPR_STATE[fpr] = fmt; |
8bae0a0c JSC |
2410 | break; |
2411 | ||
2412 | case fmt_uninterpreted: | |
2413 | case fmt_double : | |
2414 | case fmt_long : | |
2415 | FGR[fpr] = value; | |
0c2c5f61 | 2416 | FPR_STATE[fpr] = fmt; |
8bae0a0c JSC |
2417 | break; |
2418 | ||
2419 | default : | |
0c2c5f61 | 2420 | FPR_STATE[fpr] = fmt_unknown; |
8bae0a0c JSC |
2421 | err = -1; |
2422 | break; | |
2423 | } | |
da0bce9c | 2424 | } else { |
8bae0a0c JSC |
2425 | switch (fmt) { |
2426 | case fmt_single : | |
2427 | case fmt_word : | |
8bae0a0c | 2428 | FGR[fpr] = (value & 0xFFFFFFFF); |
0c2c5f61 | 2429 | FPR_STATE[fpr] = fmt; |
8bae0a0c JSC |
2430 | break; |
2431 | ||
2432 | case fmt_uninterpreted: | |
2433 | case fmt_double : | |
2434 | case fmt_long : | |
da0bce9c ILT |
2435 | if ((fpr & 1) == 0) { /* even register number only */ |
2436 | FGR[fpr+1] = (value >> 32); | |
2437 | FGR[fpr] = (value & 0xFFFFFFFF); | |
0c2c5f61 AC |
2438 | FPR_STATE[fpr + 1] = fmt; |
2439 | FPR_STATE[fpr] = fmt; | |
da0bce9c | 2440 | } else { |
0c2c5f61 AC |
2441 | FPR_STATE[fpr] = fmt_unknown; |
2442 | FPR_STATE[fpr + 1] = fmt_unknown; | |
18c64df6 | 2443 | SignalException(ReservedInstruction,0); |
da0bce9c | 2444 | } |
8bae0a0c JSC |
2445 | break; |
2446 | ||
2447 | default : | |
0c2c5f61 | 2448 | FPR_STATE[fpr] = fmt_unknown; |
8bae0a0c JSC |
2449 | err = -1; |
2450 | break; | |
2451 | } | |
e871dd18 JSC |
2452 | } |
2453 | #if defined(WARN_RESULT) | |
2454 | else | |
2455 | UndefinedResult(); | |
2456 | #endif /* WARN_RESULT */ | |
8bae0a0c JSC |
2457 | |
2458 | if (err) | |
18c64df6 | 2459 | SignalExceptionSimulatorFault ("Unrecognised FP format in StoreFPR()"); |
8bae0a0c JSC |
2460 | |
2461 | #ifdef DEBUG | |
53b9417e | 2462 | printf("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",fpr,pr_addr(FGR[fpr]),DOFMT(fmt)); |
8bae0a0c JSC |
2463 | #endif /* DEBUG */ |
2464 | ||
2465 | return; | |
2466 | } | |
2467 | ||
18c64df6 | 2468 | int |
8bae0a0c | 2469 | NaN(op,fmt) |
e871dd18 | 2470 | uword64 op; |
8bae0a0c JSC |
2471 | FP_formats fmt; |
2472 | { | |
2473 | int boolean = 0; | |
2474 | ||
2475 | /* Check if (((E - bias) == (E_max + 1)) && (fraction != 0)). We | |
2476 | know that the exponent field is biased... we we cheat and avoid | |
2477 | removing the bias value. */ | |
2478 | switch (fmt) { | |
2479 | case fmt_single: | |
2480 | boolean = ((FP_S_be(op) == 0xFF) && (FP_S_f(op) != 0)); | |
2481 | /* We could use "FP_S_fb(1,op)" to ascertain whether we are | |
2482 | dealing with a SNaN or QNaN */ | |
2483 | break; | |
2484 | case fmt_double: | |
2485 | boolean = ((FP_D_be(op) == 0x7FF) && (FP_D_f(op) != 0)); | |
2486 | /* We could use "FP_S_fb(1,op)" to ascertain whether we are | |
2487 | dealing with a SNaN or QNaN */ | |
2488 | break; | |
2489 | case fmt_word: | |
2490 | boolean = (op == FPQNaN_WORD); | |
2491 | break; | |
2492 | case fmt_long: | |
2493 | boolean = (op == FPQNaN_LONG); | |
2494 | break; | |
50a2a691 AC |
2495 | default: |
2496 | fprintf (stderr, "Bad switch\n"); | |
2497 | abort (); | |
8bae0a0c JSC |
2498 | } |
2499 | ||
2500 | #ifdef DEBUG | |
53b9417e | 2501 | printf("DBG: NaN: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op),DOFMT(fmt)); |
8bae0a0c JSC |
2502 | #endif /* DEBUG */ |
2503 | ||
2504 | return(boolean); | |
2505 | } | |
2506 | ||
18c64df6 | 2507 | int |
8bae0a0c | 2508 | Infinity(op,fmt) |
e871dd18 | 2509 | uword64 op; |
8bae0a0c JSC |
2510 | FP_formats fmt; |
2511 | { | |
2512 | int boolean = 0; | |
2513 | ||
2514 | #ifdef DEBUG | |
53b9417e | 2515 | printf("DBG: Infinity: format %s 0x%s (PC = 0x%s)\n",DOFMT(fmt),pr_addr(op),pr_addr(IPC)); |
8bae0a0c JSC |
2516 | #endif /* DEBUG */ |
2517 | ||
2518 | /* Check if (((E - bias) == (E_max + 1)) && (fraction == 0)). We | |
2519 | know that the exponent field is biased... we we cheat and avoid | |
2520 | removing the bias value. */ | |
2521 | switch (fmt) { | |
2522 | case fmt_single: | |
2523 | boolean = ((FP_S_be(op) == 0xFF) && (FP_S_f(op) == 0)); | |
2524 | break; | |
2525 | case fmt_double: | |
2526 | boolean = ((FP_D_be(op) == 0x7FF) && (FP_D_f(op) == 0)); | |
2527 | break; | |
2528 | default: | |
2529 | printf("DBG: TODO: unrecognised format (%s) for Infinity check\n",DOFMT(fmt)); | |
2530 | break; | |
2531 | } | |
2532 | ||
2533 | #ifdef DEBUG | |
53b9417e | 2534 | printf("DBG: Infinity: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op),DOFMT(fmt)); |
8bae0a0c JSC |
2535 | #endif /* DEBUG */ |
2536 | ||
2537 | return(boolean); | |
2538 | } | |
2539 | ||
18c64df6 | 2540 | int |
8bae0a0c | 2541 | Less(op1,op2,fmt) |
e871dd18 JSC |
2542 | uword64 op1; |
2543 | uword64 op2; | |
8bae0a0c JSC |
2544 | FP_formats fmt; |
2545 | { | |
2546 | int boolean = 0; | |
2547 | ||
e871dd18 JSC |
2548 | /* Argument checking already performed by the FPCOMPARE code */ |
2549 | ||
8bae0a0c | 2550 | #ifdef DEBUG |
53b9417e | 2551 | printf("DBG: Less: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); |
8bae0a0c JSC |
2552 | #endif /* DEBUG */ |
2553 | ||
8bae0a0c JSC |
2554 | /* The format type should already have been checked: */ |
2555 | switch (fmt) { | |
2556 | case fmt_single: | |
2557 | { | |
2558 | unsigned int wop1 = (unsigned int)op1; | |
2559 | unsigned int wop2 = (unsigned int)op2; | |
2560 | boolean = (*(float *)&wop1 < *(float *)&wop2); | |
2561 | } | |
2562 | break; | |
2563 | case fmt_double: | |
2564 | boolean = (*(double *)&op1 < *(double *)&op2); | |
2565 | break; | |
50a2a691 AC |
2566 | default: |
2567 | fprintf (stderr, "Bad switch\n"); | |
2568 | abort (); | |
8bae0a0c JSC |
2569 | } |
2570 | ||
2571 | #ifdef DEBUG | |
2572 | printf("DBG: Less: returning %d (format = %s)\n",boolean,DOFMT(fmt)); | |
2573 | #endif /* DEBUG */ | |
2574 | ||
2575 | return(boolean); | |
2576 | } | |
2577 | ||
18c64df6 | 2578 | int |
8bae0a0c | 2579 | Equal(op1,op2,fmt) |
e871dd18 JSC |
2580 | uword64 op1; |
2581 | uword64 op2; | |
8bae0a0c JSC |
2582 | FP_formats fmt; |
2583 | { | |
2584 | int boolean = 0; | |
2585 | ||
e871dd18 JSC |
2586 | /* Argument checking already performed by the FPCOMPARE code */ |
2587 | ||
8bae0a0c | 2588 | #ifdef DEBUG |
53b9417e | 2589 | printf("DBG: Equal: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); |
8bae0a0c JSC |
2590 | #endif /* DEBUG */ |
2591 | ||
8bae0a0c JSC |
2592 | /* The format type should already have been checked: */ |
2593 | switch (fmt) { | |
2594 | case fmt_single: | |
2595 | boolean = ((op1 & 0xFFFFFFFF) == (op2 & 0xFFFFFFFF)); | |
2596 | break; | |
2597 | case fmt_double: | |
2598 | boolean = (op1 == op2); | |
2599 | break; | |
50a2a691 AC |
2600 | default: |
2601 | fprintf (stderr, "Bad switch\n"); | |
2602 | abort (); | |
8bae0a0c JSC |
2603 | } |
2604 | ||
2605 | #ifdef DEBUG | |
2606 | printf("DBG: Equal: returning %d (format = %s)\n",boolean,DOFMT(fmt)); | |
2607 | #endif /* DEBUG */ | |
2608 | ||
2609 | return(boolean); | |
2610 | } | |
2611 | ||
18c64df6 | 2612 | uword64 |
a9f7253f JSC |
2613 | AbsoluteValue(op,fmt) |
2614 | uword64 op; | |
2615 | FP_formats fmt; | |
2616 | { | |
50a2a691 | 2617 | uword64 result = 0; |
a9f7253f JSC |
2618 | |
2619 | #ifdef DEBUG | |
53b9417e | 2620 | printf("DBG: AbsoluteValue: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op)); |
a9f7253f JSC |
2621 | #endif /* DEBUG */ |
2622 | ||
2623 | /* The format type should already have been checked: */ | |
2624 | switch (fmt) { | |
2625 | case fmt_single: | |
2626 | { | |
2627 | unsigned int wop = (unsigned int)op; | |
2628 | float tmp = ((float)fabs((double)*(float *)&wop)); | |
2629 | result = (uword64)*(unsigned int *)&tmp; | |
2630 | } | |
2631 | break; | |
2632 | case fmt_double: | |
2633 | { | |
2634 | double tmp = (fabs(*(double *)&op)); | |
2635 | result = *(uword64 *)&tmp; | |
2636 | } | |
50a2a691 AC |
2637 | default: |
2638 | fprintf (stderr, "Bad switch\n"); | |
2639 | abort (); | |
a9f7253f JSC |
2640 | } |
2641 | ||
2642 | return(result); | |
2643 | } | |
2644 | ||
18c64df6 | 2645 | uword64 |
8bae0a0c | 2646 | Negate(op,fmt) |
e871dd18 | 2647 | uword64 op; |
8bae0a0c JSC |
2648 | FP_formats fmt; |
2649 | { | |
50a2a691 | 2650 | uword64 result = 0; |
8bae0a0c JSC |
2651 | |
2652 | #ifdef DEBUG | |
53b9417e | 2653 | printf("DBG: Negate: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op)); |
8bae0a0c JSC |
2654 | #endif /* DEBUG */ |
2655 | ||
2656 | /* The format type should already have been checked: */ | |
2657 | switch (fmt) { | |
2658 | case fmt_single: | |
2659 | { | |
2660 | unsigned int wop = (unsigned int)op; | |
2661 | float tmp = ((float)0.0 - *(float *)&wop); | |
e871dd18 | 2662 | result = (uword64)*(unsigned int *)&tmp; |
8bae0a0c JSC |
2663 | } |
2664 | break; | |
2665 | case fmt_double: | |
2666 | { | |
2667 | double tmp = ((double)0.0 - *(double *)&op); | |
e871dd18 | 2668 | result = *(uword64 *)&tmp; |
8bae0a0c JSC |
2669 | } |
2670 | break; | |
50a2a691 AC |
2671 | default: |
2672 | fprintf (stderr, "Bad switch\n"); | |
2673 | abort (); | |
8bae0a0c JSC |
2674 | } |
2675 | ||
2676 | return(result); | |
2677 | } | |
2678 | ||
18c64df6 | 2679 | uword64 |
8bae0a0c | 2680 | Add(op1,op2,fmt) |
e871dd18 JSC |
2681 | uword64 op1; |
2682 | uword64 op2; | |
8bae0a0c JSC |
2683 | FP_formats fmt; |
2684 | { | |
50a2a691 | 2685 | uword64 result = 0; |
8bae0a0c JSC |
2686 | |
2687 | #ifdef DEBUG | |
53b9417e | 2688 | printf("DBG: Add: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); |
8bae0a0c JSC |
2689 | #endif /* DEBUG */ |
2690 | ||
e871dd18 JSC |
2691 | /* The registers must specify FPRs valid for operands of type |
2692 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
2693 | |
2694 | /* The format type should already have been checked: */ | |
2695 | switch (fmt) { | |
2696 | case fmt_single: | |
2697 | { | |
2698 | unsigned int wop1 = (unsigned int)op1; | |
2699 | unsigned int wop2 = (unsigned int)op2; | |
2700 | float tmp = (*(float *)&wop1 + *(float *)&wop2); | |
e871dd18 | 2701 | result = (uword64)*(unsigned int *)&tmp; |
8bae0a0c JSC |
2702 | } |
2703 | break; | |
2704 | case fmt_double: | |
2705 | { | |
2706 | double tmp = (*(double *)&op1 + *(double *)&op2); | |
e871dd18 | 2707 | result = *(uword64 *)&tmp; |
8bae0a0c JSC |
2708 | } |
2709 | break; | |
50a2a691 AC |
2710 | default: |
2711 | fprintf (stderr, "Bad switch\n"); | |
2712 | abort (); | |
8bae0a0c JSC |
2713 | } |
2714 | ||
2715 | #ifdef DEBUG | |
53b9417e | 2716 | printf("DBG: Add: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); |
8bae0a0c JSC |
2717 | #endif /* DEBUG */ |
2718 | ||
2719 | return(result); | |
2720 | } | |
2721 | ||
18c64df6 | 2722 | uword64 |
8bae0a0c | 2723 | Sub(op1,op2,fmt) |
e871dd18 JSC |
2724 | uword64 op1; |
2725 | uword64 op2; | |
8bae0a0c JSC |
2726 | FP_formats fmt; |
2727 | { | |
50a2a691 | 2728 | uword64 result = 0; |
8bae0a0c JSC |
2729 | |
2730 | #ifdef DEBUG | |
53b9417e | 2731 | printf("DBG: Sub: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); |
8bae0a0c JSC |
2732 | #endif /* DEBUG */ |
2733 | ||
e871dd18 JSC |
2734 | /* The registers must specify FPRs valid for operands of type |
2735 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
2736 | |
2737 | /* The format type should already have been checked: */ | |
2738 | switch (fmt) { | |
2739 | case fmt_single: | |
2740 | { | |
2741 | unsigned int wop1 = (unsigned int)op1; | |
2742 | unsigned int wop2 = (unsigned int)op2; | |
2743 | float tmp = (*(float *)&wop1 - *(float *)&wop2); | |
e871dd18 | 2744 | result = (uword64)*(unsigned int *)&tmp; |
8bae0a0c JSC |
2745 | } |
2746 | break; | |
2747 | case fmt_double: | |
2748 | { | |
2749 | double tmp = (*(double *)&op1 - *(double *)&op2); | |
e871dd18 | 2750 | result = *(uword64 *)&tmp; |
8bae0a0c JSC |
2751 | } |
2752 | break; | |
50a2a691 AC |
2753 | default: |
2754 | fprintf (stderr, "Bad switch\n"); | |
2755 | abort (); | |
8bae0a0c JSC |
2756 | } |
2757 | ||
2758 | #ifdef DEBUG | |
53b9417e | 2759 | printf("DBG: Sub: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); |
8bae0a0c JSC |
2760 | #endif /* DEBUG */ |
2761 | ||
2762 | return(result); | |
2763 | } | |
2764 | ||
18c64df6 | 2765 | uword64 |
8bae0a0c | 2766 | Multiply(op1,op2,fmt) |
e871dd18 JSC |
2767 | uword64 op1; |
2768 | uword64 op2; | |
8bae0a0c JSC |
2769 | FP_formats fmt; |
2770 | { | |
50a2a691 | 2771 | uword64 result = 0; |
8bae0a0c JSC |
2772 | |
2773 | #ifdef DEBUG | |
53b9417e | 2774 | printf("DBG: Multiply: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); |
8bae0a0c JSC |
2775 | #endif /* DEBUG */ |
2776 | ||
e871dd18 JSC |
2777 | /* The registers must specify FPRs valid for operands of type |
2778 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
2779 | |
2780 | /* The format type should already have been checked: */ | |
2781 | switch (fmt) { | |
2782 | case fmt_single: | |
2783 | { | |
2784 | unsigned int wop1 = (unsigned int)op1; | |
2785 | unsigned int wop2 = (unsigned int)op2; | |
2786 | float tmp = (*(float *)&wop1 * *(float *)&wop2); | |
e871dd18 | 2787 | result = (uword64)*(unsigned int *)&tmp; |
8bae0a0c JSC |
2788 | } |
2789 | break; | |
2790 | case fmt_double: | |
2791 | { | |
2792 | double tmp = (*(double *)&op1 * *(double *)&op2); | |
e871dd18 | 2793 | result = *(uword64 *)&tmp; |
8bae0a0c JSC |
2794 | } |
2795 | break; | |
50a2a691 AC |
2796 | default: |
2797 | fprintf (stderr, "Bad switch\n"); | |
2798 | abort (); | |
8bae0a0c JSC |
2799 | } |
2800 | ||
2801 | #ifdef DEBUG | |
53b9417e | 2802 | printf("DBG: Multiply: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); |
8bae0a0c JSC |
2803 | #endif /* DEBUG */ |
2804 | ||
2805 | return(result); | |
2806 | } | |
2807 | ||
18c64df6 | 2808 | uword64 |
8bae0a0c | 2809 | Divide(op1,op2,fmt) |
e871dd18 JSC |
2810 | uword64 op1; |
2811 | uword64 op2; | |
8bae0a0c JSC |
2812 | FP_formats fmt; |
2813 | { | |
50a2a691 | 2814 | uword64 result = 0; |
8bae0a0c JSC |
2815 | |
2816 | #ifdef DEBUG | |
53b9417e | 2817 | printf("DBG: Divide: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); |
8bae0a0c JSC |
2818 | #endif /* DEBUG */ |
2819 | ||
e871dd18 JSC |
2820 | /* The registers must specify FPRs valid for operands of type |
2821 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
2822 | |
2823 | /* The format type should already have been checked: */ | |
2824 | switch (fmt) { | |
2825 | case fmt_single: | |
2826 | { | |
2827 | unsigned int wop1 = (unsigned int)op1; | |
2828 | unsigned int wop2 = (unsigned int)op2; | |
2829 | float tmp = (*(float *)&wop1 / *(float *)&wop2); | |
e871dd18 | 2830 | result = (uword64)*(unsigned int *)&tmp; |
8bae0a0c JSC |
2831 | } |
2832 | break; | |
2833 | case fmt_double: | |
2834 | { | |
2835 | double tmp = (*(double *)&op1 / *(double *)&op2); | |
e871dd18 | 2836 | result = *(uword64 *)&tmp; |
8bae0a0c JSC |
2837 | } |
2838 | break; | |
50a2a691 AC |
2839 | default: |
2840 | fprintf (stderr, "Bad switch\n"); | |
2841 | abort (); | |
8bae0a0c JSC |
2842 | } |
2843 | ||
2844 | #ifdef DEBUG | |
53b9417e | 2845 | printf("DBG: Divide: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); |
8bae0a0c JSC |
2846 | #endif /* DEBUG */ |
2847 | ||
2848 | return(result); | |
2849 | } | |
2850 | ||
18c64df6 | 2851 | uword64 UNUSED |
8bae0a0c | 2852 | Recip(op,fmt) |
e871dd18 | 2853 | uword64 op; |
8bae0a0c JSC |
2854 | FP_formats fmt; |
2855 | { | |
50a2a691 | 2856 | uword64 result = 0; |
8bae0a0c JSC |
2857 | |
2858 | #ifdef DEBUG | |
53b9417e | 2859 | printf("DBG: Recip: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op)); |
8bae0a0c JSC |
2860 | #endif /* DEBUG */ |
2861 | ||
e871dd18 JSC |
2862 | /* The registers must specify FPRs valid for operands of type |
2863 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
2864 | |
2865 | /* The format type should already have been checked: */ | |
2866 | switch (fmt) { | |
2867 | case fmt_single: | |
2868 | { | |
2869 | unsigned int wop = (unsigned int)op; | |
2870 | float tmp = ((float)1.0 / *(float *)&wop); | |
e871dd18 | 2871 | result = (uword64)*(unsigned int *)&tmp; |
8bae0a0c JSC |
2872 | } |
2873 | break; | |
2874 | case fmt_double: | |
2875 | { | |
2876 | double tmp = ((double)1.0 / *(double *)&op); | |
e871dd18 | 2877 | result = *(uword64 *)&tmp; |
8bae0a0c JSC |
2878 | } |
2879 | break; | |
50a2a691 AC |
2880 | default: |
2881 | fprintf (stderr, "Bad switch\n"); | |
2882 | abort (); | |
8bae0a0c JSC |
2883 | } |
2884 | ||
2885 | #ifdef DEBUG | |
53b9417e | 2886 | printf("DBG: Recip: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); |
8bae0a0c JSC |
2887 | #endif /* DEBUG */ |
2888 | ||
2889 | return(result); | |
2890 | } | |
2891 | ||
18c64df6 | 2892 | uword64 |
8bae0a0c | 2893 | SquareRoot(op,fmt) |
e871dd18 | 2894 | uword64 op; |
8bae0a0c JSC |
2895 | FP_formats fmt; |
2896 | { | |
50a2a691 | 2897 | uword64 result = 0; |
8bae0a0c JSC |
2898 | |
2899 | #ifdef DEBUG | |
53b9417e | 2900 | printf("DBG: SquareRoot: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op)); |
8bae0a0c JSC |
2901 | #endif /* DEBUG */ |
2902 | ||
e871dd18 JSC |
2903 | /* The registers must specify FPRs valid for operands of type |
2904 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
2905 | |
2906 | /* The format type should already have been checked: */ | |
2907 | switch (fmt) { | |
2908 | case fmt_single: | |
2909 | { | |
2910 | unsigned int wop = (unsigned int)op; | |
e3d12c65 | 2911 | #ifdef HAVE_SQRT |
8bae0a0c | 2912 | float tmp = ((float)sqrt((double)*(float *)&wop)); |
e871dd18 | 2913 | result = (uword64)*(unsigned int *)&tmp; |
e3d12c65 DE |
2914 | #else |
2915 | /* TODO: Provide square-root */ | |
2916 | result = (uword64)0; | |
2917 | #endif | |
8bae0a0c JSC |
2918 | } |
2919 | break; | |
2920 | case fmt_double: | |
2921 | { | |
e3d12c65 | 2922 | #ifdef HAVE_SQRT |
8bae0a0c | 2923 | double tmp = (sqrt(*(double *)&op)); |
e871dd18 | 2924 | result = *(uword64 *)&tmp; |
e3d12c65 DE |
2925 | #else |
2926 | /* TODO: Provide square-root */ | |
2927 | result = (uword64)0; | |
2928 | #endif | |
8bae0a0c JSC |
2929 | } |
2930 | break; | |
50a2a691 AC |
2931 | default: |
2932 | fprintf (stderr, "Bad switch\n"); | |
2933 | abort (); | |
8bae0a0c JSC |
2934 | } |
2935 | ||
2936 | #ifdef DEBUG | |
53b9417e | 2937 | printf("DBG: SquareRoot: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); |
8bae0a0c JSC |
2938 | #endif /* DEBUG */ |
2939 | ||
2940 | return(result); | |
2941 | } | |
2942 | ||
18c64df6 AC |
2943 | uword64 |
2944 | convert(sd,rm,op,from,to) | |
2945 | SIM_DESC sd; | |
8bae0a0c | 2946 | int rm; |
e871dd18 | 2947 | uword64 op; |
8bae0a0c JSC |
2948 | FP_formats from; |
2949 | FP_formats to; | |
2950 | { | |
50a2a691 | 2951 | uword64 result = 0; |
8bae0a0c JSC |
2952 | |
2953 | #ifdef DEBUG | |
53b9417e | 2954 | printf("DBG: Convert: mode %s : op 0x%s : from %s : to %s : (PC = 0x%s)\n",RMMODE(rm),pr_addr(op),DOFMT(from),DOFMT(to),pr_addr(IPC)); |
8bae0a0c JSC |
2955 | #endif /* DEBUG */ |
2956 | ||
2957 | /* The value "op" is converted to the destination format, rounding | |
2958 | using mode "rm". When the destination is a fixed-point format, | |
2959 | then a source value of Infinity, NaN or one which would round to | |
2960 | an integer outside the fixed point range then an IEEE Invalid | |
2961 | Operation condition is raised. */ | |
2962 | switch (to) { | |
2963 | case fmt_single: | |
2964 | { | |
2965 | float tmp; | |
2966 | switch (from) { | |
2967 | case fmt_double: | |
2968 | tmp = (float)(*(double *)&op); | |
2969 | break; | |
2970 | ||
2971 | case fmt_word: | |
2972 | tmp = (float)((int)(op & 0xFFFFFFFF)); | |
2973 | break; | |
2974 | ||
2975 | case fmt_long: | |
e3d12c65 | 2976 | tmp = (float)((word64)op); |
8bae0a0c | 2977 | break; |
50a2a691 AC |
2978 | default: |
2979 | fprintf (stderr, "Bad switch\n"); | |
2980 | abort (); | |
8bae0a0c JSC |
2981 | } |
2982 | ||
458e1f58 ILT |
2983 | #if 0 |
2984 | /* FIXME: This code is incorrect. The rounding mode does not | |
2985 | round to integral values; it rounds to the nearest | |
2986 | representable value in the format. */ | |
2987 | ||
8bae0a0c JSC |
2988 | switch (rm) { |
2989 | case FP_RM_NEAREST: | |
e871dd18 JSC |
2990 | /* Round result to nearest representable value. When two |
2991 | representable values are equally near, round to the value | |
2992 | that has a least significant bit of zero (i.e. is even). */ | |
4fa134be | 2993 | #ifdef HAVE_ANINT |
e871dd18 | 2994 | tmp = (float)anint((double)tmp); |
d0757082 JSC |
2995 | #else |
2996 | /* TODO: Provide round-to-nearest */ | |
2997 | #endif | |
8bae0a0c JSC |
2998 | break; |
2999 | ||
3000 | case FP_RM_TOZERO: | |
e871dd18 JSC |
3001 | /* Round result to the value closest to, and not greater in |
3002 | magnitude than, the result. */ | |
4fa134be | 3003 | #ifdef HAVE_AINT |
e871dd18 | 3004 | tmp = (float)aint((double)tmp); |
d0757082 JSC |
3005 | #else |
3006 | /* TODO: Provide round-to-zero */ | |
3007 | #endif | |
8bae0a0c JSC |
3008 | break; |
3009 | ||
3010 | case FP_RM_TOPINF: | |
e871dd18 JSC |
3011 | /* Round result to the value closest to, and not less than, |
3012 | the result. */ | |
3013 | tmp = (float)ceil((double)tmp); | |
8bae0a0c JSC |
3014 | break; |
3015 | ||
3016 | case FP_RM_TOMINF: | |
e871dd18 JSC |
3017 | /* Round result to the value closest to, and not greater than, |
3018 | the result. */ | |
3019 | tmp = (float)floor((double)tmp); | |
8bae0a0c JSC |
3020 | break; |
3021 | } | |
458e1f58 ILT |
3022 | #endif /* 0 */ |
3023 | ||
e871dd18 | 3024 | result = (uword64)*(unsigned int *)&tmp; |
8bae0a0c JSC |
3025 | } |
3026 | break; | |
3027 | ||
3028 | case fmt_double: | |
3029 | { | |
3030 | double tmp; | |
f24b7b69 | 3031 | word64 xxx; |
8bae0a0c JSC |
3032 | |
3033 | switch (from) { | |
3034 | case fmt_single: | |
3035 | { | |
3036 | unsigned int wop = (unsigned int)op; | |
3037 | tmp = (double)(*(float *)&wop); | |
3038 | } | |
3039 | break; | |
3040 | ||
3041 | case fmt_word: | |
f24b7b69 | 3042 | xxx = SIGNEXTEND((op & 0xFFFFFFFF),32); |
e3d12c65 | 3043 | tmp = (double)xxx; |
8bae0a0c JSC |
3044 | break; |
3045 | ||
3046 | case fmt_long: | |
e871dd18 | 3047 | tmp = (double)((word64)op); |
8bae0a0c | 3048 | break; |
50a2a691 AC |
3049 | |
3050 | default: | |
3051 | fprintf (stderr, "Bad switch\n"); | |
3052 | abort (); | |
8bae0a0c | 3053 | } |
e871dd18 | 3054 | |
458e1f58 ILT |
3055 | #if 0 |
3056 | /* FIXME: This code is incorrect. The rounding mode does not | |
3057 | round to integral values; it rounds to the nearest | |
3058 | representable value in the format. */ | |
3059 | ||
8bae0a0c JSC |
3060 | switch (rm) { |
3061 | case FP_RM_NEAREST: | |
4fa134be | 3062 | #ifdef HAVE_ANINT |
e871dd18 | 3063 | tmp = anint(*(double *)&tmp); |
d0757082 JSC |
3064 | #else |
3065 | /* TODO: Provide round-to-nearest */ | |
3066 | #endif | |
8bae0a0c JSC |
3067 | break; |
3068 | ||
3069 | case FP_RM_TOZERO: | |
4fa134be | 3070 | #ifdef HAVE_AINT |
e871dd18 | 3071 | tmp = aint(*(double *)&tmp); |
d0757082 JSC |
3072 | #else |
3073 | /* TODO: Provide round-to-zero */ | |
3074 | #endif | |
8bae0a0c JSC |
3075 | break; |
3076 | ||
3077 | case FP_RM_TOPINF: | |
3078 | tmp = ceil(*(double *)&tmp); | |
3079 | break; | |
3080 | ||
3081 | case FP_RM_TOMINF: | |
3082 | tmp = floor(*(double *)&tmp); | |
3083 | break; | |
3084 | } | |
458e1f58 ILT |
3085 | #endif /* 0 */ |
3086 | ||
e871dd18 | 3087 | result = *(uword64 *)&tmp; |
8bae0a0c JSC |
3088 | } |
3089 | break; | |
3090 | ||
3091 | case fmt_word: | |
3092 | case fmt_long: | |
3093 | if (Infinity(op,from) || NaN(op,from) || (1 == 0/*TODO: check range */)) { | |
3094 | printf("DBG: TODO: update FCSR\n"); | |
18c64df6 | 3095 | SignalExceptionFPE (); |
8bae0a0c JSC |
3096 | } else { |
3097 | if (to == fmt_word) { | |
50a2a691 | 3098 | int tmp = 0; |
8bae0a0c JSC |
3099 | switch (from) { |
3100 | case fmt_single: | |
3101 | { | |
3102 | unsigned int wop = (unsigned int)op; | |
e3d12c65 | 3103 | tmp = (int)*((float *)&wop); |
8bae0a0c JSC |
3104 | } |
3105 | break; | |
3106 | case fmt_double: | |
e3d12c65 | 3107 | tmp = (int)*((double *)&op); |
8bae0a0c | 3108 | #ifdef DEBUG |
53b9417e | 3109 | printf("DBG: from double %.30f (0x%s) to word: 0x%08X\n",*((double *)&op),pr_addr(op),tmp); |
8bae0a0c JSC |
3110 | #endif /* DEBUG */ |
3111 | break; | |
50a2a691 AC |
3112 | default: |
3113 | fprintf (stderr, "Bad switch\n"); | |
3114 | abort (); | |
8bae0a0c | 3115 | } |
e871dd18 | 3116 | result = (uword64)tmp; |
8bae0a0c | 3117 | } else { /* fmt_long */ |
50a2a691 | 3118 | word64 tmp = 0; |
8bae0a0c JSC |
3119 | switch (from) { |
3120 | case fmt_single: | |
3121 | { | |
3122 | unsigned int wop = (unsigned int)op; | |
e3d12c65 | 3123 | tmp = (word64)*((float *)&wop); |
8bae0a0c JSC |
3124 | } |
3125 | break; | |
3126 | case fmt_double: | |
e3d12c65 | 3127 | tmp = (word64)*((double *)&op); |
8bae0a0c | 3128 | break; |
50a2a691 AC |
3129 | default: |
3130 | fprintf (stderr, "Bad switch\n"); | |
3131 | abort (); | |
8bae0a0c | 3132 | } |
e3d12c65 | 3133 | result = (uword64)tmp; |
8bae0a0c JSC |
3134 | } |
3135 | } | |
3136 | break; | |
50a2a691 AC |
3137 | default: |
3138 | fprintf (stderr, "Bad switch\n"); | |
3139 | abort (); | |
8bae0a0c JSC |
3140 | } |
3141 | ||
3142 | #ifdef DEBUG | |
53b9417e | 3143 | printf("DBG: Convert: returning 0x%s (to format = %s)\n",pr_addr(result),DOFMT(to)); |
8bae0a0c JSC |
3144 | #endif /* DEBUG */ |
3145 | ||
3146 | return(result); | |
3147 | } | |
3148 | #endif /* HASFPU */ | |
3149 | ||
3150 | /*-- co-processor support routines ------------------------------------------*/ | |
3151 | ||
2f2e6c5d | 3152 | static int UNUSED |
8bae0a0c JSC |
3153 | CoProcPresent(coproc_number) |
3154 | unsigned int coproc_number; | |
3155 | { | |
3156 | /* Return TRUE if simulator provides a model for the given co-processor number */ | |
3157 | return(0); | |
3158 | } | |
3159 | ||
18c64df6 AC |
3160 | void |
3161 | cop_lw(sd,coproc_num,coproc_reg,memword) | |
3162 | SIM_DESC sd; | |
8bae0a0c JSC |
3163 | int coproc_num, coproc_reg; |
3164 | unsigned int memword; | |
3165 | { | |
3166 | switch (coproc_num) { | |
3167 | #if defined(HASFPU) | |
3168 | case 1: | |
3169 | #ifdef DEBUG | |
53b9417e | 3170 | printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword,pr_addr(memword)); |
8bae0a0c | 3171 | #endif |
da0bce9c | 3172 | StoreFPR(coproc_reg,fmt_word,(uword64)memword); |
0c2c5f61 | 3173 | FPR_STATE[coproc_reg] = fmt_uninterpreted; |
8bae0a0c JSC |
3174 | break; |
3175 | #endif /* HASFPU */ | |
3176 | ||
3177 | default: | |
f24b7b69 | 3178 | #if 0 /* this should be controlled by a configuration option */ |
18c64df6 | 3179 | sim_io_printf(sd,"COP_LW(%d,%d,0x%08X) at IPC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,memword,pr_addr(IPC)); |
f24b7b69 | 3180 | #endif |
8bae0a0c JSC |
3181 | break; |
3182 | } | |
3183 | ||
3184 | return; | |
3185 | } | |
3186 | ||
18c64df6 AC |
3187 | void |
3188 | cop_ld(sd,coproc_num,coproc_reg,memword) | |
3189 | SIM_DESC sd; | |
8bae0a0c | 3190 | int coproc_num, coproc_reg; |
e871dd18 | 3191 | uword64 memword; |
8bae0a0c JSC |
3192 | { |
3193 | switch (coproc_num) { | |
3194 | #if defined(HASFPU) | |
3195 | case 1: | |
3196 | StoreFPR(coproc_reg,fmt_uninterpreted,memword); | |
3197 | break; | |
3198 | #endif /* HASFPU */ | |
3199 | ||
3200 | default: | |
f24b7b69 | 3201 | #if 0 /* this message should be controlled by a configuration option */ |
18c64df6 | 3202 | sim_io_printf(sd,"COP_LD(%d,%d,0x%s) at IPC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(memword),pr_addr(IPC)); |
f24b7b69 | 3203 | #endif |
8bae0a0c JSC |
3204 | break; |
3205 | } | |
3206 | ||
3207 | return; | |
3208 | } | |
3209 | ||
18c64df6 AC |
3210 | unsigned int |
3211 | cop_sw(sd,coproc_num,coproc_reg) | |
3212 | SIM_DESC sd; | |
8bae0a0c JSC |
3213 | int coproc_num, coproc_reg; |
3214 | { | |
3215 | unsigned int value = 0; | |
da0bce9c | 3216 | |
8bae0a0c JSC |
3217 | switch (coproc_num) { |
3218 | #if defined(HASFPU) | |
3219 | case 1: | |
3220 | #if 1 | |
9cb8397f GRK |
3221 | { |
3222 | FP_formats hold; | |
0c2c5f61 AC |
3223 | hold = FPR_STATE[coproc_reg]; |
3224 | FPR_STATE[coproc_reg] = fmt_word; | |
9cb8397f | 3225 | value = (unsigned int)ValueFPR(coproc_reg,fmt_uninterpreted); |
0c2c5f61 | 3226 | FPR_STATE[coproc_reg] = hold; |
9cb8397f | 3227 | } |
8bae0a0c JSC |
3228 | #else |
3229 | #if 1 | |
0c2c5f61 | 3230 | value = (unsigned int)ValueFPR(coproc_reg,FPR_STATE[coproc_reg]); |
8bae0a0c JSC |
3231 | #else |
3232 | #ifdef DEBUG | |
0c2c5f61 | 3233 | printf("DBG: COP_SW: reg in format %s (will be accessing as single)\n",DOFMT(FPR_STATE[coproc_reg])); |
8bae0a0c JSC |
3234 | #endif /* DEBUG */ |
3235 | value = (unsigned int)ValueFPR(coproc_reg,fmt_single); | |
3236 | #endif | |
3237 | #endif | |
3238 | break; | |
3239 | #endif /* HASFPU */ | |
3240 | ||
3241 | default: | |
f24b7b69 | 3242 | #if 0 /* should be controlled by configuration option */ |
18c64df6 | 3243 | sim_io_printf(sd,"COP_SW(%d,%d) at IPC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(IPC)); |
f24b7b69 | 3244 | #endif |
8bae0a0c JSC |
3245 | break; |
3246 | } | |
3247 | ||
3248 | return(value); | |
3249 | } | |
3250 | ||
18c64df6 AC |
3251 | uword64 |
3252 | cop_sd(sd,coproc_num,coproc_reg) | |
3253 | SIM_DESC sd; | |
8bae0a0c JSC |
3254 | int coproc_num, coproc_reg; |
3255 | { | |
e871dd18 | 3256 | uword64 value = 0; |
8bae0a0c JSC |
3257 | switch (coproc_num) { |
3258 | #if defined(HASFPU) | |
3259 | case 1: | |
3260 | #if 1 | |
3261 | value = ValueFPR(coproc_reg,fmt_uninterpreted); | |
3262 | #else | |
3263 | #if 1 | |
0c2c5f61 | 3264 | value = ValueFPR(coproc_reg,FPR_STATE[coproc_reg]); |
8bae0a0c JSC |
3265 | #else |
3266 | #ifdef DEBUG | |
0c2c5f61 | 3267 | printf("DBG: COP_SD: reg in format %s (will be accessing as double)\n",DOFMT(FPR_STATE[coproc_reg])); |
8bae0a0c JSC |
3268 | #endif /* DEBUG */ |
3269 | value = ValueFPR(coproc_reg,fmt_double); | |
3270 | #endif | |
3271 | #endif | |
3272 | break; | |
3273 | #endif /* HASFPU */ | |
3274 | ||
3275 | default: | |
f24b7b69 | 3276 | #if 0 /* should be controlled by configuration option */ |
18c64df6 | 3277 | sim_io_printf(sd,"COP_SD(%d,%d) at IPC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(IPC)); |
f24b7b69 | 3278 | #endif |
8bae0a0c JSC |
3279 | break; |
3280 | } | |
3281 | ||
3282 | return(value); | |
3283 | } | |
3284 | ||
ea985d24 | 3285 | void |
18c64df6 AC |
3286 | decode_coproc(sd,instruction) |
3287 | SIM_DESC sd; | |
8bae0a0c JSC |
3288 | unsigned int instruction; |
3289 | { | |
3290 | int coprocnum = ((instruction >> 26) & 3); | |
3291 | ||
56e7c849 AC |
3292 | switch (coprocnum) |
3293 | { | |
8bae0a0c JSC |
3294 | case 0: /* standard CPU control and cache registers */ |
3295 | { | |
8bae0a0c JSC |
3296 | int code = ((instruction >> 21) & 0x1F); |
3297 | /* R4000 Users Manual (second edition) lists the following CP0 | |
3298 | instructions: | |
56e7c849 AC |
3299 | DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000) |
3300 | DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000) | |
3301 | MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000) | |
3302 | MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000) | |
3303 | TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001) | |
3304 | TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010) | |
3305 | TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110) | |
3306 | TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000) | |
3307 | CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii) | |
3308 | ERET Exception return (VR4100 = 01000010000000000000000000011000) | |
3309 | */ | |
3310 | if (((code == 0x00) || (code == 0x04)) && ((instruction & 0x7FF) == 0)) | |
3311 | { | |
3312 | int rt = ((instruction >> 16) & 0x1F); | |
3313 | int rd = ((instruction >> 11) & 0x1F); | |
3314 | ||
3315 | switch (rd) /* NOTEs: Standard CP0 registers */ | |
3316 | { | |
3317 | /* 0 = Index R4000 VR4100 VR4300 */ | |
3318 | /* 1 = Random R4000 VR4100 VR4300 */ | |
3319 | /* 2 = EntryLo0 R4000 VR4100 VR4300 */ | |
3320 | /* 3 = EntryLo1 R4000 VR4100 VR4300 */ | |
3321 | /* 4 = Context R4000 VR4100 VR4300 */ | |
3322 | /* 5 = PageMask R4000 VR4100 VR4300 */ | |
3323 | /* 6 = Wired R4000 VR4100 VR4300 */ | |
3324 | /* 8 = BadVAddr R4000 VR4100 VR4300 */ | |
3325 | /* 9 = Count R4000 VR4100 VR4300 */ | |
3326 | /* 10 = EntryHi R4000 VR4100 VR4300 */ | |
3327 | /* 11 = Compare R4000 VR4100 VR4300 */ | |
3328 | /* 12 = SR R4000 VR4100 VR4300 */ | |
3329 | case 12: | |
3330 | if (code == 0x00) | |
3331 | GPR[rt] = SR; | |
3332 | else | |
3333 | SR = GPR[rt]; | |
3334 | break; | |
3335 | /* 13 = Cause R4000 VR4100 VR4300 */ | |
05d1322f JL |
3336 | case 13: |
3337 | if (code == 0x00) | |
3338 | GPR[rt] = CAUSE; | |
3339 | else | |
3340 | CAUSE = GPR[rt]; | |
3341 | break; | |
56e7c849 AC |
3342 | /* 14 = EPC R4000 VR4100 VR4300 */ |
3343 | /* 15 = PRId R4000 VR4100 VR4300 */ | |
6eedf3f4 MA |
3344 | #ifdef SUBTARGET_R3900 |
3345 | /* 16 = Debug */ | |
3346 | case 16: | |
3347 | if (code == 0x00) | |
3348 | GPR[rt] = Debug; | |
3349 | else | |
3350 | Debug = GPR[rt]; | |
3351 | break; | |
3352 | #else | |
56e7c849 | 3353 | /* 16 = Config R4000 VR4100 VR4300 */ |
6eedf3f4 MA |
3354 | #endif |
3355 | #ifdef SUBTARGET_R3900 | |
3356 | /* 17 = Debug */ | |
3357 | case 17: | |
3358 | if (code == 0x00) | |
3359 | GPR[rt] = DEPC; | |
3360 | else | |
3361 | DEPC = GPR[rt]; | |
3362 | break; | |
3363 | #else | |
56e7c849 | 3364 | /* 17 = LLAddr R4000 VR4100 VR4300 */ |
6eedf3f4 | 3365 | #endif |
56e7c849 AC |
3366 | /* 18 = WatchLo R4000 VR4100 VR4300 */ |
3367 | /* 19 = WatchHi R4000 VR4100 VR4300 */ | |
3368 | /* 20 = XContext R4000 VR4100 VR4300 */ | |
3369 | /* 26 = PErr or ECC R4000 VR4100 VR4300 */ | |
3370 | /* 27 = CacheErr R4000 VR4100 */ | |
3371 | /* 28 = TagLo R4000 VR4100 VR4300 */ | |
3372 | /* 29 = TagHi R4000 VR4100 VR4300 */ | |
3373 | /* 30 = ErrorEPC R4000 VR4100 VR4300 */ | |
3374 | GPR[rt] = 0xDEADC0DE; /* CPR[0,rd] */ | |
3375 | /* CPR[0,rd] = GPR[rt]; */ | |
3376 | default: | |
3377 | if (code == 0x00) | |
18c64df6 | 3378 | sim_io_printf(sd,"Warning: MFC0 %d,%d ignored (architecture specific)\n",rt,rd); |
56e7c849 | 3379 | else |
18c64df6 | 3380 | sim_io_printf(sd,"Warning: MTC0 %d,%d ignored (architecture specific)\n",rt,rd); |
56e7c849 AC |
3381 | } |
3382 | } | |
3383 | else if (code == 0x10 && (instruction & 0x3f) == 0x18) | |
3384 | { | |
3385 | /* ERET */ | |
3386 | if (SR & status_ERL) | |
3387 | { | |
3388 | /* Oops, not yet available */ | |
18c64df6 | 3389 | sim_io_printf(sd,"Warning: ERET when SR[ERL] set not handled yet"); |
56e7c849 AC |
3390 | PC = EPC; |
3391 | SR &= ~status_ERL; | |
3392 | } | |
3393 | else | |
3394 | { | |
3395 | PC = EPC; | |
3396 | SR &= ~status_EXL; | |
3397 | } | |
3398 | } | |
6eedf3f4 MA |
3399 | else if (code == 0x10 && (instruction & 0x3f) == 0x10) |
3400 | { | |
3401 | /* RFE */ | |
3402 | } | |
3403 | else if (code == 0x10 && (instruction & 0x3f) == 0x1F) | |
3404 | { | |
3405 | /* DERET */ | |
3406 | Debug &= ~Debug_DM; | |
3407 | DELAYSLOT(); | |
3408 | DSPC = DEPC; | |
3409 | } | |
56e7c849 | 3410 | else |
18c64df6 | 3411 | sim_io_eprintf(sd,"Unrecognised COP0 instruction 0x%08X at IPC = 0x%s : No handler present\n",instruction,pr_addr(IPC)); |
e871dd18 | 3412 | /* TODO: When executing an ERET or RFE instruction we should |
8bae0a0c JSC |
3413 | clear LLBIT, to ensure that any out-standing atomic |
3414 | read/modify/write sequence fails. */ | |
3415 | } | |
56e7c849 AC |
3416 | break; |
3417 | ||
8bae0a0c | 3418 | case 2: /* undefined co-processor */ |
18c64df6 | 3419 | sim_io_eprintf(sd,"COP2 instruction 0x%08X at IPC = 0x%s : No handler present\n",instruction,pr_addr(IPC)); |
8bae0a0c | 3420 | break; |
56e7c849 | 3421 | |
8bae0a0c JSC |
3422 | case 1: /* should not occur (FPU co-processor) */ |
3423 | case 3: /* should not occur (FPU co-processor) */ | |
3424 | SignalException(ReservedInstruction,instruction); | |
3425 | break; | |
56e7c849 AC |
3426 | } |
3427 | ||
8bae0a0c JSC |
3428 | return; |
3429 | } | |
3430 | ||
3431 | /*-- instruction simulation -------------------------------------------------*/ | |
3432 | ||
16bd5d6e AC |
3433 | /* When the IGEN simulator is being built, the function below is be |
3434 | replaced by a generated version. However, WITH_IGEN == 2 indicates | |
3435 | that the fubction below should be compiled but under a different | |
3436 | name (to allow backward compatibility) */ | |
3437 | ||
3438 | #if (WITH_IGEN != 1) | |
3439 | #if (WITH_IGEN > 1) | |
dad6f1f3 AC |
3440 | void old_engine_run PARAMS ((SIM_DESC sd, int next_cpu_nr, int siggnal)); |
3441 | void | |
3442 | old_engine_run (sd, next_cpu_nr, siggnal) | |
3443 | #else | |
2e61a3ad AC |
3444 | void |
3445 | sim_engine_run (sd, next_cpu_nr, siggnal) | |
dad6f1f3 | 3446 | #endif |
2e61a3ad AC |
3447 | SIM_DESC sd; |
3448 | int next_cpu_nr; /* ignore */ | |
3449 | int siggnal; /* ignore */ | |
8bae0a0c | 3450 | { |
50a2a691 | 3451 | #if !defined(FASTSIM) |
8bae0a0c | 3452 | unsigned int pipeline_count = 1; |
50a2a691 | 3453 | #endif |
8bae0a0c JSC |
3454 | |
3455 | #ifdef DEBUG | |
50a2a691 | 3456 | if (STATE_MEMORY (sd) == NULL) { |
8bae0a0c JSC |
3457 | printf("DBG: simulate() entered with no memory\n"); |
3458 | exit(1); | |
3459 | } | |
3460 | #endif /* DEBUG */ | |
3461 | ||
3462 | #if 0 /* Disabled to check that everything works OK */ | |
3463 | /* The VR4300 seems to sign-extend the PC on its first | |
3464 | access. However, this may just be because it is currently | |
3465 | configured in 32bit mode. However... */ | |
3466 | PC = SIGNEXTEND(PC,32); | |
3467 | #endif | |
3468 | ||
3469 | /* main controlling loop */ | |
2e61a3ad | 3470 | while (1) { |
8bae0a0c | 3471 | /* Fetch the next instruction from the simulator memory: */ |
dad6f1f3 AC |
3472 | address_word vaddr = (uword64)PC; |
3473 | address_word paddr; | |
8bae0a0c | 3474 | int cca; |
53b9417e | 3475 | unsigned int instruction; /* uword64? what's this used for? FIXME! */ |
8bae0a0c JSC |
3476 | |
3477 | #ifdef DEBUG | |
3478 | { | |
3479 | printf("DBG: state = 0x%08X :",state); | |
8bae0a0c JSC |
3480 | if (state & simHALTEX) printf(" simHALTEX"); |
3481 | if (state & simHALTIN) printf(" simHALTIN"); | |
53b9417e | 3482 | printf("\n"); |
8bae0a0c JSC |
3483 | } |
3484 | #endif /* DEBUG */ | |
3485 | ||
0c2c5f61 | 3486 | DSSTATE = (STATE & simDELAYSLOT); |
8bae0a0c JSC |
3487 | #ifdef DEBUG |
3488 | if (dsstate) | |
18c64df6 | 3489 | sim_io_printf(sd,"DBG: DSPC = 0x%s\n",pr_addr(DSPC)); |
8bae0a0c JSC |
3490 | #endif /* DEBUG */ |
3491 | ||
6429b296 JW |
3492 | if (AddressTranslation(PC,isINSTRUCTION,isLOAD,&paddr,&cca,isTARGET,isREAL)) { |
3493 | if ((vaddr & 1) == 0) { | |
3494 | /* Copy the action of the LW instruction */ | |
3495 | unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0); | |
3496 | unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0); | |
3497 | uword64 value; | |
3498 | unsigned int byte; | |
3499 | paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2))); | |
53b9417e | 3500 | LoadMemory(&value,NULL,cca,AccessLength_WORD,paddr,vaddr,isINSTRUCTION,isREAL); |
6429b296 JW |
3501 | byte = ((vaddr & LOADDRMASK) ^ (bigend << 2)); |
3502 | instruction = ((value >> (8 * byte)) & 0xFFFFFFFF); | |
3503 | } else { | |
3504 | /* Copy the action of the LH instruction */ | |
3505 | unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 1) : 0); | |
3506 | unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 1) : 0); | |
3507 | uword64 value; | |
3508 | unsigned int byte; | |
3509 | paddr = (((paddr & ~ (uword64) 1) & ~LOADDRMASK) | |
3510 | | (((paddr & ~ (uword64) 1) & LOADDRMASK) ^ (reverse << 1))); | |
53b9417e | 3511 | LoadMemory(&value,NULL,cca, AccessLength_HALFWORD, |
6429b296 JW |
3512 | paddr & ~ (uword64) 1, |
3513 | vaddr, isINSTRUCTION, isREAL); | |
3514 | byte = (((vaddr &~ (uword64) 1) & LOADDRMASK) ^ (bigend << 1)); | |
3515 | instruction = ((value >> (8 * byte)) & 0xFFFF); | |
3516 | } | |
8bae0a0c | 3517 | } else { |
53b9417e | 3518 | fprintf(stderr,"Cannot translate address for PC = 0x%s failed\n",pr_addr(PC)); |
8bae0a0c JSC |
3519 | exit(1); |
3520 | } | |
3521 | ||
3522 | #ifdef DEBUG | |
18c64df6 | 3523 | sim_io_printf(sd,"DBG: fetched 0x%08X from PC = 0x%s\n",instruction,pr_addr(PC)); |
8bae0a0c JSC |
3524 | #endif /* DEBUG */ |
3525 | ||
8bae0a0c JSC |
3526 | IPC = PC; /* copy PC for this instruction */ |
3527 | /* This is required by exception processing, to ensure that we can | |
3528 | cope with exceptions in the delay slots of branches that may | |
3529 | already have changed the PC. */ | |
6429b296 JW |
3530 | if ((vaddr & 1) == 0) |
3531 | PC += 4; /* increment ready for the next fetch */ | |
3532 | else | |
3533 | PC += 2; | |
8bae0a0c JSC |
3534 | /* NOTE: If we perform a delay slot change to the PC, this |
3535 | increment is not requuired. However, it would make the | |
3536 | simulator more complicated to try and avoid this small hit. */ | |
3537 | ||
3538 | /* Currently this code provides a simple model. For more | |
3539 | complicated models we could perform exception status checks at | |
3540 | this point, and set the simSTOP state as required. This could | |
3541 | also include processing any hardware interrupts raised by any | |
3542 | I/O model attached to the simulator context. | |
3543 | ||
3544 | Support for "asynchronous" I/O events within the simulated world | |
3545 | could be providing by managing a counter, and calling a I/O | |
3546 | specific handler when a particular threshold is reached. On most | |
3547 | architectures a decrement and check for zero operation is | |
3548 | usually quicker than an increment and compare. However, the | |
3549 | process of managing a known value decrement to zero, is higher | |
3550 | than the cost of using an explicit value UINT_MAX into the | |
3551 | future. Which system is used will depend on how complicated the | |
3552 | I/O model is, and how much it is likely to affect the simulator | |
3553 | bandwidth. | |
3554 | ||
3555 | If events need to be scheduled further in the future than | |
3556 | UINT_MAX event ticks, then the I/O model should just provide its | |
3557 | own counter, triggered from the event system. */ | |
3558 | ||
3559 | /* MIPS pipeline ticks. To allow for future support where the | |
3560 | pipeline hit of individual instructions is known, this control | |
3561 | loop manages a "pipeline_count" variable. It is initialised to | |
3562 | 1 (one), and will only be changed by the simulator engine when | |
3563 | executing an instruction. If the engine does not have access to | |
3564 | pipeline cycle count information then all instructions will be | |
3565 | treated as using a single cycle. NOTE: A standard system is not | |
3566 | provided by the default simulator because different MIPS | |
3567 | architectures have different cycle counts for the same | |
50a2a691 AC |
3568 | instructions. |
3569 | ||
3570 | [NOTE: pipeline_count has been replaced the event queue] */ | |
8bae0a0c JSC |
3571 | |
3572 | #if defined(HASFPU) | |
3573 | /* Set previous flag, depending on current: */ | |
0c2c5f61 AC |
3574 | if (STATE & simPCOC0) |
3575 | STATE |= simPCOC1; | |
8bae0a0c | 3576 | else |
0c2c5f61 | 3577 | STATE &= ~simPCOC1; |
8bae0a0c JSC |
3578 | /* and update the current value: */ |
3579 | if (GETFCC(0)) | |
0c2c5f61 | 3580 | STATE |= simPCOC0; |
8bae0a0c | 3581 | else |
0c2c5f61 | 3582 | STATE &= ~simPCOC0; |
8bae0a0c JSC |
3583 | #endif /* HASFPU */ |
3584 | ||
3585 | /* NOTE: For multi-context simulation environments the "instruction" | |
3586 | variable should be local to this routine. */ | |
3587 | ||
3588 | /* Shorthand accesses for engine. Note: If we wanted to use global | |
3589 | variables (and a single-threaded simulator engine), then we can | |
3590 | create the actual variables with these names. */ | |
3591 | ||
0c2c5f61 | 3592 | if (!(STATE & simSKIPNEXT)) { |
8bae0a0c | 3593 | /* Include the simulator engine */ |
284e759d | 3594 | #include "oengine.c" |
f24b7b69 | 3595 | #if ((GPRLEN == 64) && !PROCESSOR_64BIT) || ((GPRLEN == 32) && PROCESSOR_64BIT) |
8bae0a0c JSC |
3596 | #error "Mismatch between run-time simulator code and simulation engine" |
3597 | #endif | |
18c64df6 AC |
3598 | #if (WITH_TARGET_WORD_BITSIZE != GPRLEN) |
3599 | #error "Mismatch between configure WITH_TARGET_WORD_BITSIZE and gencode GPRLEN" | |
3600 | #endif | |
3601 | #if (WITH_FLOATING_POINT == HARD_FLOATING_POINT != defined (HASFPU)) | |
3602 | #error "Mismatch between configure WITH_FLOATING_POINT and gencode HASFPU" | |
3603 | #endif | |
8bae0a0c JSC |
3604 | |
3605 | #if defined(WARN_LOHI) | |
3606 | /* Decrement the HI/LO validity ticks */ | |
3607 | if (HIACCESS > 0) | |
3608 | HIACCESS--; | |
3609 | if (LOACCESS > 0) | |
3610 | LOACCESS--; | |
0425cfb3 | 3611 | /* start-sanitize-r5900 */ |
53b9417e DE |
3612 | if (HI1ACCESS > 0) |
3613 | HI1ACCESS--; | |
3614 | if (LO1ACCESS > 0) | |
3615 | LO1ACCESS--; | |
0425cfb3 | 3616 | /* end-sanitize-r5900 */ |
8bae0a0c JSC |
3617 | #endif /* WARN_LOHI */ |
3618 | ||
8bae0a0c JSC |
3619 | /* For certain MIPS architectures, GPR[0] is hardwired to zero. We |
3620 | should check for it being changed. It is better doing it here, | |
3621 | than within the simulator, since it will help keep the simulator | |
3622 | small. */ | |
3623 | if (ZERO != 0) { | |
05d1322f | 3624 | #if defined(WARN_ZERO) |
18c64df6 | 3625 | sim_io_eprintf(sd,"The ZERO register has been updated with 0x%s (PC = 0x%s) (reset back to zero)\n",pr_addr(ZERO),pr_addr(IPC)); |
05d1322f | 3626 | #endif /* WARN_ZERO */ |
8bae0a0c JSC |
3627 | ZERO = 0; /* reset back to zero before next instruction */ |
3628 | } | |
8bae0a0c | 3629 | } else /* simSKIPNEXT check */ |
0c2c5f61 | 3630 | STATE &= ~simSKIPNEXT; |
8bae0a0c JSC |
3631 | |
3632 | /* If the delay slot was active before the instruction is | |
3633 | executed, then update the PC to its new value: */ | |
0c2c5f61 | 3634 | if (DSSTATE) { |
8bae0a0c | 3635 | #ifdef DEBUG |
53b9417e | 3636 | printf("DBG: dsstate set before instruction execution - updating PC to 0x%s\n",pr_addr(DSPC)); |
8bae0a0c JSC |
3637 | #endif /* DEBUG */ |
3638 | PC = DSPC; | |
6eedf3f4 | 3639 | CANCELDELAYSLOT(); |
8bae0a0c JSC |
3640 | } |
3641 | ||
3642 | if (MIPSISA < 4) { /* The following is only required on pre MIPS IV processors: */ | |
3643 | /* Deal with pending register updates: */ | |
3644 | #ifdef DEBUG | |
3645 | printf("DBG: EMPTY BEFORE pending_in = %d, pending_out = %d, pending_total = %d\n",pending_in,pending_out,pending_total); | |
3646 | #endif /* DEBUG */ | |
0c2c5f61 | 3647 | if (PENDING_OUT != PENDING_IN) { |
8bae0a0c | 3648 | int loop; |
0c2c5f61 AC |
3649 | int index = PENDING_OUT; |
3650 | int total = PENDING_TOTAL; | |
3651 | if (PENDING_TOTAL == 0) { | |
8bae0a0c JSC |
3652 | fprintf(stderr,"FATAL: Mis-match on pending update pointers\n"); |
3653 | exit(1); | |
3654 | } | |
3655 | for (loop = 0; (loop < total); loop++) { | |
3656 | #ifdef DEBUG | |
3657 | printf("DBG: BEFORE index = %d, loop = %d\n",index,loop); | |
3658 | #endif /* DEBUG */ | |
0c2c5f61 | 3659 | if (PENDING_SLOT_REG[index] != (LAST_EMBED_REGNUM + 1)) { |
8bae0a0c | 3660 | #ifdef DEBUG |
0c2c5f61 | 3661 | printf("pending_slot_count[%d] = %d\n",index,PENDING_SLOT_COUNT[index]); |
8bae0a0c | 3662 | #endif /* DEBUG */ |
0c2c5f61 | 3663 | if (--(PENDING_SLOT_COUNT[index]) == 0) { |
8bae0a0c | 3664 | #ifdef DEBUG |
0c2c5f61 AC |
3665 | printf("pending_slot_reg[%d] = %d\n",index,PENDING_SLOT_REG[index]); |
3666 | printf("pending_slot_value[%d] = 0x%s\n",index,pr_addr(PENDING_SLOT_VALUE[index])); | |
8bae0a0c | 3667 | #endif /* DEBUG */ |
0c2c5f61 | 3668 | if (PENDING_SLOT_REG[index] == COCIDX) { |
9cb8397f | 3669 | #if defined(HASFPU) |
8bae0a0c | 3670 | SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0)); |
9cb8397f GRK |
3671 | #else |
3672 | ; | |
3673 | #endif | |
8bae0a0c | 3674 | } else { |
0c2c5f61 | 3675 | REGISTERS[PENDING_SLOT_REG[index]] = PENDING_SLOT_VALUE[index]; |
8bae0a0c JSC |
3676 | #if defined(HASFPU) |
3677 | /* The only time we have PENDING updates to FPU | |
3678 | registers, is when performing binary transfers. This | |
3679 | means we should update the register type field. */ | |
0c2c5f61 AC |
3680 | if ((PENDING_SLOT_REG[index] >= FGRIDX) && (PENDING_SLOT_REG[index] < (FGRIDX + 32))) |
3681 | FPR_STATE[PENDING_SLOT_REG[index] - FGRIDX] = fmt_uninterpreted; | |
8bae0a0c JSC |
3682 | #endif /* HASFPU */ |
3683 | } | |
3684 | #ifdef DEBUG | |
0c2c5f61 | 3685 | printf("registers[%d] = 0x%s\n",PENDING_SLOT_REG[index],pr_addr(REGISTERS[PENDING_SLOT_REG[index]])); |
8bae0a0c | 3686 | #endif /* DEBUG */ |
0c2c5f61 AC |
3687 | PENDING_SLOT_REG[index] = (LAST_EMBED_REGNUM + 1); |
3688 | PENDING_OUT++; | |
3689 | if (PENDING_OUT == PSLOTS) | |
3690 | PENDING_OUT = 0; | |
3691 | PENDING_TOTAL--; | |
8bae0a0c JSC |
3692 | } |
3693 | } | |
3694 | #ifdef DEBUG | |
3695 | printf("DBG: AFTER index = %d, loop = %d\n",index,loop); | |
3696 | #endif /* DEBUG */ | |
3697 | index++; | |
3698 | if (index == PSLOTS) | |
3699 | index = 0; | |
3700 | } | |
3701 | } | |
3702 | #ifdef DEBUG | |
0c2c5f61 | 3703 | printf("DBG: EMPTY AFTER pending_in = %d, pending_out = %d, pending_total = %d\n",PENDING_IN,PENDING_OUT,PENDING_TOTAL); |
8bae0a0c JSC |
3704 | #endif /* DEBUG */ |
3705 | } | |
3706 | ||
3707 | #if !defined(FASTSIM) | |
50a2a691 AC |
3708 | if (sim_events_tickn (sd, pipeline_count)) |
3709 | { | |
3710 | /* cpu->cia = cia; */ | |
3711 | sim_events_process (sd); | |
3712 | } | |
3713 | #else | |
2e61a3ad AC |
3714 | if (sim_events_tick (sd)) |
3715 | { | |
3716 | /* cpu->cia = cia; */ | |
3717 | sim_events_process (sd); | |
3718 | } | |
50a2a691 | 3719 | #endif /* FASTSIM */ |
8bae0a0c | 3720 | } |
8bae0a0c | 3721 | } |
16bd5d6e AC |
3722 | #endif |
3723 | ||
8bae0a0c | 3724 | |
53b9417e DE |
3725 | /* This code copied from gdb's utils.c. Would like to share this code, |
3726 | but don't know of a common place where both could get to it. */ | |
3727 | ||
3728 | /* Temporary storage using circular buffer */ | |
3729 | #define NUMCELLS 16 | |
3730 | #define CELLSIZE 32 | |
3731 | static char* | |
3732 | get_cell() | |
3733 | { | |
3734 | static char buf[NUMCELLS][CELLSIZE]; | |
3735 | static int cell=0; | |
3736 | if (++cell>=NUMCELLS) cell=0; | |
3737 | return buf[cell]; | |
3738 | } | |
3739 | ||
3740 | /* Print routines to handle variable size regs, etc */ | |
3741 | ||
3742 | /* Eliminate warning from compiler on 32-bit systems */ | |
3743 | static int thirty_two = 32; | |
3744 | ||
3745 | char* | |
3746 | pr_addr(addr) | |
3747 | SIM_ADDR addr; | |
3748 | { | |
3749 | char *paddr_str=get_cell(); | |
3750 | switch (sizeof(addr)) | |
3751 | { | |
3752 | case 8: | |
50a2a691 | 3753 | sprintf(paddr_str,"%08lx%08lx", |
53b9417e DE |
3754 | (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff)); |
3755 | break; | |
3756 | case 4: | |
50a2a691 | 3757 | sprintf(paddr_str,"%08lx",(unsigned long)addr); |
53b9417e DE |
3758 | break; |
3759 | case 2: | |
3760 | sprintf(paddr_str,"%04x",(unsigned short)(addr&0xffff)); | |
3761 | break; | |
3762 | default: | |
3763 | sprintf(paddr_str,"%x",addr); | |
3764 | } | |
3765 | return paddr_str; | |
3766 | } | |
3767 | ||
87e43259 AC |
3768 | char* |
3769 | pr_uword64(addr) | |
3770 | uword64 addr; | |
3771 | { | |
3772 | char *paddr_str=get_cell(); | |
50a2a691 | 3773 | sprintf(paddr_str,"%08lx%08lx", |
87e43259 AC |
3774 | (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff)); |
3775 | return paddr_str; | |
3776 | } | |
3777 | ||
3778 | ||
8bae0a0c JSC |
3779 | /*---------------------------------------------------------------------------*/ |
3780 | /*> EOF interp.c <*/ |